1 /* Copyright 2008-2012 Broadcom Corporation 2 * 3 * Unless you and Broadcom execute a separate written software license 4 * agreement governing use of this software, this software is licensed to you 5 * under the terms of the GNU General Public License version 2, available 6 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL"). 7 * 8 * Notwithstanding the above, under no circumstances may you combine this 9 * software in any way with any other Broadcom software provided under a 10 * license other than the GPL, without Broadcom's express prior written 11 * consent. 12 * 13 * Written by Yaniv Rosner 14 * 15 */ 16 17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 18 19 #include <linux/kernel.h> 20 #include <linux/errno.h> 21 #include <linux/pci.h> 22 #include <linux/netdevice.h> 23 #include <linux/delay.h> 24 #include <linux/ethtool.h> 25 #include <linux/mutex.h> 26 27 #include "bnx2x.h" 28 #include "bnx2x_cmn.h" 29 30 /********************************************************/ 31 #define ETH_HLEN 14 32 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ 33 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8) 34 #define ETH_MIN_PACKET_SIZE 60 35 #define ETH_MAX_PACKET_SIZE 1500 36 #define ETH_MAX_JUMBO_PACKET_SIZE 9600 37 #define MDIO_ACCESS_TIMEOUT 1000 38 #define WC_LANE_MAX 4 39 #define I2C_SWITCH_WIDTH 2 40 #define I2C_BSC0 0 41 #define I2C_BSC1 1 42 #define I2C_WA_RETRY_CNT 3 43 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1) 44 #define MCPR_IMC_COMMAND_READ_OP 1 45 #define MCPR_IMC_COMMAND_WRITE_OP 2 46 47 /* LED Blink rate that will achieve ~15.9Hz */ 48 #define LED_BLINK_RATE_VAL_E3 354 49 #define LED_BLINK_RATE_VAL_E1X_E2 480 50 /***********************************************************/ 51 /* Shortcut definitions */ 52 /***********************************************************/ 53 54 #define NIG_LATCH_BC_ENABLE_MI_INT 0 55 56 #define NIG_STATUS_EMAC0_MI_INT \ 57 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT 58 #define NIG_STATUS_XGXS0_LINK10G \ 59 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G 60 #define NIG_STATUS_XGXS0_LINK_STATUS \ 61 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS 62 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \ 63 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE 64 #define NIG_STATUS_SERDES0_LINK_STATUS \ 65 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS 66 #define NIG_MASK_MI_INT \ 67 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT 68 #define NIG_MASK_XGXS0_LINK10G \ 69 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G 70 #define NIG_MASK_XGXS0_LINK_STATUS \ 71 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS 72 #define NIG_MASK_SERDES0_LINK_STATUS \ 73 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS 74 75 #define MDIO_AN_CL73_OR_37_COMPLETE \ 76 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \ 77 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE) 78 79 #define XGXS_RESET_BITS \ 80 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \ 81 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \ 82 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \ 83 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \ 84 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB) 85 86 #define SERDES_RESET_BITS \ 87 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \ 88 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \ 89 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \ 90 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD) 91 92 #define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37 93 #define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73 94 #define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM 95 #define AUTONEG_PARALLEL \ 96 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 97 #define AUTONEG_SGMII_FIBER_AUTODET \ 98 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 99 #define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 100 101 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \ 102 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 103 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \ 104 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 105 #define GP_STATUS_SPEED_MASK \ 106 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 107 #define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 108 #define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 109 #define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 110 #define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 111 #define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 112 #define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 113 #define GP_STATUS_10G_HIG \ 114 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 115 #define GP_STATUS_10G_CX4 \ 116 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 117 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 118 #define GP_STATUS_10G_KX4 \ 119 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 120 #define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR 121 #define GP_STATUS_10G_XFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI 122 #define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS 123 #define GP_STATUS_10G_SFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI 124 #define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD 125 #define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD 126 #define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD 127 #define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4 128 #define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD 129 #define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD 130 #define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD 131 #define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD 132 #define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD 133 #define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD 134 #define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD 135 #define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD 136 #define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD 137 #define LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD 138 #define LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD 139 140 141 142 #define SFP_EEPROM_CON_TYPE_ADDR 0x2 143 #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7 144 #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21 145 146 147 #define SFP_EEPROM_COMP_CODE_ADDR 0x3 148 #define SFP_EEPROM_COMP_CODE_SR_MASK (1<<4) 149 #define SFP_EEPROM_COMP_CODE_LR_MASK (1<<5) 150 #define SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6) 151 152 #define SFP_EEPROM_FC_TX_TECH_ADDR 0x8 153 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4 154 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8 155 156 #define SFP_EEPROM_OPTIONS_ADDR 0x40 157 #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1 158 #define SFP_EEPROM_OPTIONS_SIZE 2 159 160 #define EDC_MODE_LINEAR 0x0022 161 #define EDC_MODE_LIMITING 0x0044 162 #define EDC_MODE_PASSIVE_DAC 0x0055 163 164 /* ETS defines*/ 165 #define DCBX_INVALID_COS (0xFF) 166 167 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000) 168 #define ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000) 169 #define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS (1360) 170 #define ETS_E3B0_NIG_MIN_W_VAL_20GBPS (2720) 171 #define ETS_E3B0_PBF_MIN_W_VAL (10000) 172 173 #define MAX_PACKET_SIZE (9700) 174 #define MAX_KR_LINK_RETRY 4 175 176 /**********************************************************/ 177 /* INTERFACE */ 178 /**********************************************************/ 179 180 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \ 181 bnx2x_cl45_write(_bp, _phy, \ 182 (_phy)->def_md_devad, \ 183 (_bank + (_addr & 0xf)), \ 184 _val) 185 186 #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \ 187 bnx2x_cl45_read(_bp, _phy, \ 188 (_phy)->def_md_devad, \ 189 (_bank + (_addr & 0xf)), \ 190 _val) 191 192 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits) 193 { 194 u32 val = REG_RD(bp, reg); 195 196 val |= bits; 197 REG_WR(bp, reg, val); 198 return val; 199 } 200 201 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits) 202 { 203 u32 val = REG_RD(bp, reg); 204 205 val &= ~bits; 206 REG_WR(bp, reg, val); 207 return val; 208 } 209 210 /* 211 * bnx2x_check_lfa - This function checks if link reinitialization is required, 212 * or link flap can be avoided. 213 * 214 * @params: link parameters 215 * Returns 0 if Link Flap Avoidance conditions are met otherwise, the failed 216 * condition code. 217 */ 218 static int bnx2x_check_lfa(struct link_params *params) 219 { 220 u32 link_status, cfg_idx, lfa_mask, cfg_size; 221 u32 cur_speed_cap_mask, cur_req_fc_auto_adv, additional_config; 222 u32 saved_val, req_val, eee_status; 223 struct bnx2x *bp = params->bp; 224 225 additional_config = 226 REG_RD(bp, params->lfa_base + 227 offsetof(struct shmem_lfa, additional_config)); 228 229 /* NOTE: must be first condition checked - 230 * to verify DCC bit is cleared in any case! 231 */ 232 if (additional_config & NO_LFA_DUE_TO_DCC_MASK) { 233 DP(NETIF_MSG_LINK, "No LFA due to DCC flap after clp exit\n"); 234 REG_WR(bp, params->lfa_base + 235 offsetof(struct shmem_lfa, additional_config), 236 additional_config & ~NO_LFA_DUE_TO_DCC_MASK); 237 return LFA_DCC_LFA_DISABLED; 238 } 239 240 /* Verify that link is up */ 241 link_status = REG_RD(bp, params->shmem_base + 242 offsetof(struct shmem_region, 243 port_mb[params->port].link_status)); 244 if (!(link_status & LINK_STATUS_LINK_UP)) 245 return LFA_LINK_DOWN; 246 247 /* Verify that loopback mode is not set */ 248 if (params->loopback_mode) 249 return LFA_LOOPBACK_ENABLED; 250 251 /* Verify that MFW supports LFA */ 252 if (!params->lfa_base) 253 return LFA_MFW_IS_TOO_OLD; 254 255 if (params->num_phys == 3) { 256 cfg_size = 2; 257 lfa_mask = 0xffffffff; 258 } else { 259 cfg_size = 1; 260 lfa_mask = 0xffff; 261 } 262 263 /* Compare Duplex */ 264 saved_val = REG_RD(bp, params->lfa_base + 265 offsetof(struct shmem_lfa, req_duplex)); 266 req_val = params->req_duplex[0] | (params->req_duplex[1] << 16); 267 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) { 268 DP(NETIF_MSG_LINK, "Duplex mismatch %x vs. %x\n", 269 (saved_val & lfa_mask), (req_val & lfa_mask)); 270 return LFA_DUPLEX_MISMATCH; 271 } 272 /* Compare Flow Control */ 273 saved_val = REG_RD(bp, params->lfa_base + 274 offsetof(struct shmem_lfa, req_flow_ctrl)); 275 req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16); 276 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) { 277 DP(NETIF_MSG_LINK, "Flow control mismatch %x vs. %x\n", 278 (saved_val & lfa_mask), (req_val & lfa_mask)); 279 return LFA_FLOW_CTRL_MISMATCH; 280 } 281 /* Compare Link Speed */ 282 saved_val = REG_RD(bp, params->lfa_base + 283 offsetof(struct shmem_lfa, req_line_speed)); 284 req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16); 285 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) { 286 DP(NETIF_MSG_LINK, "Link speed mismatch %x vs. %x\n", 287 (saved_val & lfa_mask), (req_val & lfa_mask)); 288 return LFA_LINK_SPEED_MISMATCH; 289 } 290 291 for (cfg_idx = 0; cfg_idx < cfg_size; cfg_idx++) { 292 cur_speed_cap_mask = REG_RD(bp, params->lfa_base + 293 offsetof(struct shmem_lfa, 294 speed_cap_mask[cfg_idx])); 295 296 if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) { 297 DP(NETIF_MSG_LINK, "Speed Cap mismatch %x vs. %x\n", 298 cur_speed_cap_mask, 299 params->speed_cap_mask[cfg_idx]); 300 return LFA_SPEED_CAP_MISMATCH; 301 } 302 } 303 304 cur_req_fc_auto_adv = 305 REG_RD(bp, params->lfa_base + 306 offsetof(struct shmem_lfa, additional_config)) & 307 REQ_FC_AUTO_ADV_MASK; 308 309 if ((u16)cur_req_fc_auto_adv != params->req_fc_auto_adv) { 310 DP(NETIF_MSG_LINK, "Flow Ctrl AN mismatch %x vs. %x\n", 311 cur_req_fc_auto_adv, params->req_fc_auto_adv); 312 return LFA_FLOW_CTRL_MISMATCH; 313 } 314 315 eee_status = REG_RD(bp, params->shmem2_base + 316 offsetof(struct shmem2_region, 317 eee_status[params->port])); 318 319 if (((eee_status & SHMEM_EEE_LPI_REQUESTED_BIT) ^ 320 (params->eee_mode & EEE_MODE_ENABLE_LPI)) || 321 ((eee_status & SHMEM_EEE_REQUESTED_BIT) ^ 322 (params->eee_mode & EEE_MODE_ADV_LPI))) { 323 DP(NETIF_MSG_LINK, "EEE mismatch %x vs. %x\n", params->eee_mode, 324 eee_status); 325 return LFA_EEE_MISMATCH; 326 } 327 328 /* LFA conditions are met */ 329 return 0; 330 } 331 /******************************************************************/ 332 /* EPIO/GPIO section */ 333 /******************************************************************/ 334 static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en) 335 { 336 u32 epio_mask, gp_oenable; 337 *en = 0; 338 /* Sanity check */ 339 if (epio_pin > 31) { 340 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin); 341 return; 342 } 343 344 epio_mask = 1 << epio_pin; 345 /* Set this EPIO to output */ 346 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE); 347 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask); 348 349 *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin; 350 } 351 static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en) 352 { 353 u32 epio_mask, gp_output, gp_oenable; 354 355 /* Sanity check */ 356 if (epio_pin > 31) { 357 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin); 358 return; 359 } 360 DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en); 361 epio_mask = 1 << epio_pin; 362 /* Set this EPIO to output */ 363 gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS); 364 if (en) 365 gp_output |= epio_mask; 366 else 367 gp_output &= ~epio_mask; 368 369 REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output); 370 371 /* Set the value for this EPIO */ 372 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE); 373 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask); 374 } 375 376 static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val) 377 { 378 if (pin_cfg == PIN_CFG_NA) 379 return; 380 if (pin_cfg >= PIN_CFG_EPIO0) { 381 bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val); 382 } else { 383 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3; 384 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2; 385 bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port); 386 } 387 } 388 389 static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val) 390 { 391 if (pin_cfg == PIN_CFG_NA) 392 return -EINVAL; 393 if (pin_cfg >= PIN_CFG_EPIO0) { 394 bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val); 395 } else { 396 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3; 397 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2; 398 *val = bnx2x_get_gpio(bp, gpio_num, gpio_port); 399 } 400 return 0; 401 402 } 403 /******************************************************************/ 404 /* ETS section */ 405 /******************************************************************/ 406 static void bnx2x_ets_e2e3a0_disabled(struct link_params *params) 407 { 408 /* ETS disabled configuration*/ 409 struct bnx2x *bp = params->bp; 410 411 DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n"); 412 413 /* mapping between entry priority to client number (0,1,2 -debug and 414 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST) 415 * 3bits client num. 416 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 417 * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000 418 */ 419 420 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688); 421 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves 422 * as strict. Bits 0,1,2 - debug and management entries, 3 - 423 * COS0 entry, 4 - COS1 entry. 424 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT 425 * bit4 bit3 bit2 bit1 bit0 426 * MCP and debug are strict 427 */ 428 429 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); 430 /* defines which entries (clients) are subjected to WFQ arbitration */ 431 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0); 432 /* For strict priority entries defines the number of consecutive 433 * slots for the highest priority. 434 */ 435 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); 436 /* mapping between the CREDIT_WEIGHT registers and actual client 437 * numbers 438 */ 439 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0); 440 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0); 441 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0); 442 443 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0); 444 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0); 445 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0); 446 /* ETS mode disable */ 447 REG_WR(bp, PBF_REG_ETS_ENABLED, 0); 448 /* If ETS mode is enabled (there is no strict priority) defines a WFQ 449 * weight for COS0/COS1. 450 */ 451 REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710); 452 REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710); 453 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */ 454 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680); 455 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680); 456 /* Defines the number of consecutive slots for the strict priority */ 457 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); 458 } 459 /****************************************************************************** 460 * Description: 461 * Getting min_w_val will be set according to line speed . 462 *. 463 ******************************************************************************/ 464 static u32 bnx2x_ets_get_min_w_val_nig(const struct link_vars *vars) 465 { 466 u32 min_w_val = 0; 467 /* Calculate min_w_val.*/ 468 if (vars->link_up) { 469 if (vars->line_speed == SPEED_20000) 470 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS; 471 else 472 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS; 473 } else 474 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS; 475 /* If the link isn't up (static configuration for example ) The 476 * link will be according to 20GBPS. 477 */ 478 return min_w_val; 479 } 480 /****************************************************************************** 481 * Description: 482 * Getting credit upper bound form min_w_val. 483 *. 484 ******************************************************************************/ 485 static u32 bnx2x_ets_get_credit_upper_bound(const u32 min_w_val) 486 { 487 const u32 credit_upper_bound = (u32)MAXVAL((150 * min_w_val), 488 MAX_PACKET_SIZE); 489 return credit_upper_bound; 490 } 491 /****************************************************************************** 492 * Description: 493 * Set credit upper bound for NIG. 494 *. 495 ******************************************************************************/ 496 static void bnx2x_ets_e3b0_set_credit_upper_bound_nig( 497 const struct link_params *params, 498 const u32 min_w_val) 499 { 500 struct bnx2x *bp = params->bp; 501 const u8 port = params->port; 502 const u32 credit_upper_bound = 503 bnx2x_ets_get_credit_upper_bound(min_w_val); 504 505 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 : 506 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound); 507 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 : 508 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound); 509 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 : 510 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound); 511 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 : 512 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound); 513 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 : 514 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound); 515 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 : 516 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound); 517 518 if (!port) { 519 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6, 520 credit_upper_bound); 521 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7, 522 credit_upper_bound); 523 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8, 524 credit_upper_bound); 525 } 526 } 527 /****************************************************************************** 528 * Description: 529 * Will return the NIG ETS registers to init values.Except 530 * credit_upper_bound. 531 * That isn't used in this configuration (No WFQ is enabled) and will be 532 * configured acording to spec 533 *. 534 ******************************************************************************/ 535 static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params, 536 const struct link_vars *vars) 537 { 538 struct bnx2x *bp = params->bp; 539 const u8 port = params->port; 540 const u32 min_w_val = bnx2x_ets_get_min_w_val_nig(vars); 541 /* Mapping between entry priority to client number (0,1,2 -debug and 542 * management clients, 3 - COS0 client, 4 - COS1, ... 8 - 543 * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by 544 * reset value or init tool 545 */ 546 if (port) { 547 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210); 548 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0); 549 } else { 550 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210); 551 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8); 552 } 553 /* For strict priority entries defines the number of consecutive 554 * slots for the highest priority. 555 */ 556 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS : 557 NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); 558 /* Mapping between the CREDIT_WEIGHT registers and actual client 559 * numbers 560 */ 561 if (port) { 562 /*Port 1 has 6 COS*/ 563 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543); 564 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0); 565 } else { 566 /*Port 0 has 9 COS*/ 567 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 568 0x43210876); 569 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5); 570 } 571 572 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves 573 * as strict. Bits 0,1,2 - debug and management entries, 3 - 574 * COS0 entry, 4 - COS1 entry. 575 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT 576 * bit4 bit3 bit2 bit1 bit0 577 * MCP and debug are strict 578 */ 579 if (port) 580 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f); 581 else 582 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff); 583 /* defines which entries (clients) are subjected to WFQ arbitration */ 584 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ : 585 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0); 586 587 /* Please notice the register address are note continuous and a 588 * for here is note appropriate.In 2 port mode port0 only COS0-5 589 * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4 590 * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT 591 * are never used for WFQ 592 */ 593 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 : 594 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0); 595 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 : 596 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0); 597 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 : 598 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0); 599 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 : 600 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0); 601 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 : 602 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0); 603 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 : 604 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0); 605 if (!port) { 606 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0); 607 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0); 608 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0); 609 } 610 611 bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val); 612 } 613 /****************************************************************************** 614 * Description: 615 * Set credit upper bound for PBF. 616 *. 617 ******************************************************************************/ 618 static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf( 619 const struct link_params *params, 620 const u32 min_w_val) 621 { 622 struct bnx2x *bp = params->bp; 623 const u32 credit_upper_bound = 624 bnx2x_ets_get_credit_upper_bound(min_w_val); 625 const u8 port = params->port; 626 u32 base_upper_bound = 0; 627 u8 max_cos = 0; 628 u8 i = 0; 629 /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4 630 * port mode port1 has COS0-2 that can be used for WFQ. 631 */ 632 if (!port) { 633 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0; 634 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0; 635 } else { 636 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1; 637 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1; 638 } 639 640 for (i = 0; i < max_cos; i++) 641 REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound); 642 } 643 644 /****************************************************************************** 645 * Description: 646 * Will return the PBF ETS registers to init values.Except 647 * credit_upper_bound. 648 * That isn't used in this configuration (No WFQ is enabled) and will be 649 * configured acording to spec 650 *. 651 ******************************************************************************/ 652 static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params) 653 { 654 struct bnx2x *bp = params->bp; 655 const u8 port = params->port; 656 const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL; 657 u8 i = 0; 658 u32 base_weight = 0; 659 u8 max_cos = 0; 660 661 /* Mapping between entry priority to client number 0 - COS0 662 * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num. 663 * TODO_ETS - Should be done by reset value or init tool 664 */ 665 if (port) 666 /* 0x688 (|011|0 10|00 1|000) */ 667 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688); 668 else 669 /* (10 1|100 |011|0 10|00 1|000) */ 670 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688); 671 672 /* TODO_ETS - Should be done by reset value or init tool */ 673 if (port) 674 /* 0x688 (|011|0 10|00 1|000)*/ 675 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688); 676 else 677 /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */ 678 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688); 679 680 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 : 681 PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100); 682 683 684 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 : 685 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0); 686 687 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 : 688 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0); 689 /* In 2 port mode port0 has COS0-5 that can be used for WFQ. 690 * In 4 port mode port1 has COS0-2 that can be used for WFQ. 691 */ 692 if (!port) { 693 base_weight = PBF_REG_COS0_WEIGHT_P0; 694 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0; 695 } else { 696 base_weight = PBF_REG_COS0_WEIGHT_P1; 697 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1; 698 } 699 700 for (i = 0; i < max_cos; i++) 701 REG_WR(bp, base_weight + (0x4 * i), 0); 702 703 bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf); 704 } 705 /****************************************************************************** 706 * Description: 707 * E3B0 disable will return basicly the values to init values. 708 *. 709 ******************************************************************************/ 710 static int bnx2x_ets_e3b0_disabled(const struct link_params *params, 711 const struct link_vars *vars) 712 { 713 struct bnx2x *bp = params->bp; 714 715 if (!CHIP_IS_E3B0(bp)) { 716 DP(NETIF_MSG_LINK, 717 "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n"); 718 return -EINVAL; 719 } 720 721 bnx2x_ets_e3b0_nig_disabled(params, vars); 722 723 bnx2x_ets_e3b0_pbf_disabled(params); 724 725 return 0; 726 } 727 728 /****************************************************************************** 729 * Description: 730 * Disable will return basicly the values to init values. 731 * 732 ******************************************************************************/ 733 int bnx2x_ets_disabled(struct link_params *params, 734 struct link_vars *vars) 735 { 736 struct bnx2x *bp = params->bp; 737 int bnx2x_status = 0; 738 739 if ((CHIP_IS_E2(bp)) || (CHIP_IS_E3A0(bp))) 740 bnx2x_ets_e2e3a0_disabled(params); 741 else if (CHIP_IS_E3B0(bp)) 742 bnx2x_status = bnx2x_ets_e3b0_disabled(params, vars); 743 else { 744 DP(NETIF_MSG_LINK, "bnx2x_ets_disabled - chip not supported\n"); 745 return -EINVAL; 746 } 747 748 return bnx2x_status; 749 } 750 751 /****************************************************************************** 752 * Description 753 * Set the COS mappimg to SP and BW until this point all the COS are not 754 * set as SP or BW. 755 ******************************************************************************/ 756 static int bnx2x_ets_e3b0_cli_map(const struct link_params *params, 757 const struct bnx2x_ets_params *ets_params, 758 const u8 cos_sp_bitmap, 759 const u8 cos_bw_bitmap) 760 { 761 struct bnx2x *bp = params->bp; 762 const u8 port = params->port; 763 const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3); 764 const u8 pbf_cli_sp_bitmap = cos_sp_bitmap; 765 const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3; 766 const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap; 767 768 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT : 769 NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap); 770 771 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 : 772 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap); 773 774 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ : 775 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 776 nig_cli_subject2wfq_bitmap); 777 778 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 : 779 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0, 780 pbf_cli_subject2wfq_bitmap); 781 782 return 0; 783 } 784 785 /****************************************************************************** 786 * Description: 787 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are 788 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable. 789 ******************************************************************************/ 790 static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp, 791 const u8 cos_entry, 792 const u32 min_w_val_nig, 793 const u32 min_w_val_pbf, 794 const u16 total_bw, 795 const u8 bw, 796 const u8 port) 797 { 798 u32 nig_reg_adress_crd_weight = 0; 799 u32 pbf_reg_adress_crd_weight = 0; 800 /* Calculate and set BW for this COS - use 1 instead of 0 for BW */ 801 const u32 cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw; 802 const u32 cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw; 803 804 switch (cos_entry) { 805 case 0: 806 nig_reg_adress_crd_weight = 807 (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 : 808 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0; 809 pbf_reg_adress_crd_weight = (port) ? 810 PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0; 811 break; 812 case 1: 813 nig_reg_adress_crd_weight = (port) ? 814 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 : 815 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1; 816 pbf_reg_adress_crd_weight = (port) ? 817 PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0; 818 break; 819 case 2: 820 nig_reg_adress_crd_weight = (port) ? 821 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 : 822 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2; 823 824 pbf_reg_adress_crd_weight = (port) ? 825 PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0; 826 break; 827 case 3: 828 if (port) 829 return -EINVAL; 830 nig_reg_adress_crd_weight = 831 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3; 832 pbf_reg_adress_crd_weight = 833 PBF_REG_COS3_WEIGHT_P0; 834 break; 835 case 4: 836 if (port) 837 return -EINVAL; 838 nig_reg_adress_crd_weight = 839 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4; 840 pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0; 841 break; 842 case 5: 843 if (port) 844 return -EINVAL; 845 nig_reg_adress_crd_weight = 846 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5; 847 pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0; 848 break; 849 } 850 851 REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig); 852 853 REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf); 854 855 return 0; 856 } 857 /****************************************************************************** 858 * Description: 859 * Calculate the total BW.A value of 0 isn't legal. 860 * 861 ******************************************************************************/ 862 static int bnx2x_ets_e3b0_get_total_bw( 863 const struct link_params *params, 864 struct bnx2x_ets_params *ets_params, 865 u16 *total_bw) 866 { 867 struct bnx2x *bp = params->bp; 868 u8 cos_idx = 0; 869 u8 is_bw_cos_exist = 0; 870 871 *total_bw = 0 ; 872 /* Calculate total BW requested */ 873 for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) { 874 if (ets_params->cos[cos_idx].state == bnx2x_cos_state_bw) { 875 is_bw_cos_exist = 1; 876 if (!ets_params->cos[cos_idx].params.bw_params.bw) { 877 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config BW" 878 "was set to 0\n"); 879 /* This is to prevent a state when ramrods 880 * can't be sent 881 */ 882 ets_params->cos[cos_idx].params.bw_params.bw 883 = 1; 884 } 885 *total_bw += 886 ets_params->cos[cos_idx].params.bw_params.bw; 887 } 888 } 889 890 /* Check total BW is valid */ 891 if ((is_bw_cos_exist == 1) && (*total_bw != 100)) { 892 if (*total_bw == 0) { 893 DP(NETIF_MSG_LINK, 894 "bnx2x_ets_E3B0_config total BW shouldn't be 0\n"); 895 return -EINVAL; 896 } 897 DP(NETIF_MSG_LINK, 898 "bnx2x_ets_E3B0_config total BW should be 100\n"); 899 /* We can handle a case whre the BW isn't 100 this can happen 900 * if the TC are joined. 901 */ 902 } 903 return 0; 904 } 905 906 /****************************************************************************** 907 * Description: 908 * Invalidate all the sp_pri_to_cos. 909 * 910 ******************************************************************************/ 911 static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos) 912 { 913 u8 pri = 0; 914 for (pri = 0; pri < DCBX_MAX_NUM_COS; pri++) 915 sp_pri_to_cos[pri] = DCBX_INVALID_COS; 916 } 917 /****************************************************************************** 918 * Description: 919 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers 920 * according to sp_pri_to_cos. 921 * 922 ******************************************************************************/ 923 static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params, 924 u8 *sp_pri_to_cos, const u8 pri, 925 const u8 cos_entry) 926 { 927 struct bnx2x *bp = params->bp; 928 const u8 port = params->port; 929 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 : 930 DCBX_E3B0_MAX_NUM_COS_PORT0; 931 932 if (pri >= max_num_of_cos) { 933 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid " 934 "parameter Illegal strict priority\n"); 935 return -EINVAL; 936 } 937 938 if (sp_pri_to_cos[pri] != DCBX_INVALID_COS) { 939 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid " 940 "parameter There can't be two COS's with " 941 "the same strict pri\n"); 942 return -EINVAL; 943 } 944 945 sp_pri_to_cos[pri] = cos_entry; 946 return 0; 947 948 } 949 950 /****************************************************************************** 951 * Description: 952 * Returns the correct value according to COS and priority in 953 * the sp_pri_cli register. 954 * 955 ******************************************************************************/ 956 static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset, 957 const u8 pri_set, 958 const u8 pri_offset, 959 const u8 entry_size) 960 { 961 u64 pri_cli_nig = 0; 962 pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size * 963 (pri_set + pri_offset)); 964 965 return pri_cli_nig; 966 } 967 /****************************************************************************** 968 * Description: 969 * Returns the correct value according to COS and priority in the 970 * sp_pri_cli register for NIG. 971 * 972 ******************************************************************************/ 973 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set) 974 { 975 /* MCP Dbg0 and dbg1 are always with higher strict pri*/ 976 const u8 nig_cos_offset = 3; 977 const u8 nig_pri_offset = 3; 978 979 return bnx2x_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set, 980 nig_pri_offset, 4); 981 982 } 983 /****************************************************************************** 984 * Description: 985 * Returns the correct value according to COS and priority in the 986 * sp_pri_cli register for PBF. 987 * 988 ******************************************************************************/ 989 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set) 990 { 991 const u8 pbf_cos_offset = 0; 992 const u8 pbf_pri_offset = 0; 993 994 return bnx2x_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set, 995 pbf_pri_offset, 3); 996 997 } 998 999 /****************************************************************************** 1000 * Description: 1001 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers 1002 * according to sp_pri_to_cos.(which COS has higher priority) 1003 * 1004 ******************************************************************************/ 1005 static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params, 1006 u8 *sp_pri_to_cos) 1007 { 1008 struct bnx2x *bp = params->bp; 1009 u8 i = 0; 1010 const u8 port = params->port; 1011 /* MCP Dbg0 and dbg1 are always with higher strict pri*/ 1012 u64 pri_cli_nig = 0x210; 1013 u32 pri_cli_pbf = 0x0; 1014 u8 pri_set = 0; 1015 u8 pri_bitmask = 0; 1016 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 : 1017 DCBX_E3B0_MAX_NUM_COS_PORT0; 1018 1019 u8 cos_bit_to_set = (1 << max_num_of_cos) - 1; 1020 1021 /* Set all the strict priority first */ 1022 for (i = 0; i < max_num_of_cos; i++) { 1023 if (sp_pri_to_cos[i] != DCBX_INVALID_COS) { 1024 if (sp_pri_to_cos[i] >= DCBX_MAX_NUM_COS) { 1025 DP(NETIF_MSG_LINK, 1026 "bnx2x_ets_e3b0_sp_set_pri_cli_reg " 1027 "invalid cos entry\n"); 1028 return -EINVAL; 1029 } 1030 1031 pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig( 1032 sp_pri_to_cos[i], pri_set); 1033 1034 pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf( 1035 sp_pri_to_cos[i], pri_set); 1036 pri_bitmask = 1 << sp_pri_to_cos[i]; 1037 /* COS is used remove it from bitmap.*/ 1038 if (!(pri_bitmask & cos_bit_to_set)) { 1039 DP(NETIF_MSG_LINK, 1040 "bnx2x_ets_e3b0_sp_set_pri_cli_reg " 1041 "invalid There can't be two COS's with" 1042 " the same strict pri\n"); 1043 return -EINVAL; 1044 } 1045 cos_bit_to_set &= ~pri_bitmask; 1046 pri_set++; 1047 } 1048 } 1049 1050 /* Set all the Non strict priority i= COS*/ 1051 for (i = 0; i < max_num_of_cos; i++) { 1052 pri_bitmask = 1 << i; 1053 /* Check if COS was already used for SP */ 1054 if (pri_bitmask & cos_bit_to_set) { 1055 /* COS wasn't used for SP */ 1056 pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig( 1057 i, pri_set); 1058 1059 pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf( 1060 i, pri_set); 1061 /* COS is used remove it from bitmap.*/ 1062 cos_bit_to_set &= ~pri_bitmask; 1063 pri_set++; 1064 } 1065 } 1066 1067 if (pri_set != max_num_of_cos) { 1068 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_set_pri_cli_reg not all " 1069 "entries were set\n"); 1070 return -EINVAL; 1071 } 1072 1073 if (port) { 1074 /* Only 6 usable clients*/ 1075 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 1076 (u32)pri_cli_nig); 1077 1078 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf); 1079 } else { 1080 /* Only 9 usable clients*/ 1081 const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig); 1082 const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF); 1083 1084 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 1085 pri_cli_nig_lsb); 1086 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 1087 pri_cli_nig_msb); 1088 1089 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf); 1090 } 1091 return 0; 1092 } 1093 1094 /****************************************************************************** 1095 * Description: 1096 * Configure the COS to ETS according to BW and SP settings. 1097 ******************************************************************************/ 1098 int bnx2x_ets_e3b0_config(const struct link_params *params, 1099 const struct link_vars *vars, 1100 struct bnx2x_ets_params *ets_params) 1101 { 1102 struct bnx2x *bp = params->bp; 1103 int bnx2x_status = 0; 1104 const u8 port = params->port; 1105 u16 total_bw = 0; 1106 const u32 min_w_val_nig = bnx2x_ets_get_min_w_val_nig(vars); 1107 const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL; 1108 u8 cos_bw_bitmap = 0; 1109 u8 cos_sp_bitmap = 0; 1110 u8 sp_pri_to_cos[DCBX_MAX_NUM_COS] = {0}; 1111 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 : 1112 DCBX_E3B0_MAX_NUM_COS_PORT0; 1113 u8 cos_entry = 0; 1114 1115 if (!CHIP_IS_E3B0(bp)) { 1116 DP(NETIF_MSG_LINK, 1117 "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n"); 1118 return -EINVAL; 1119 } 1120 1121 if ((ets_params->num_of_cos > max_num_of_cos)) { 1122 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config the number of COS " 1123 "isn't supported\n"); 1124 return -EINVAL; 1125 } 1126 1127 /* Prepare sp strict priority parameters*/ 1128 bnx2x_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos); 1129 1130 /* Prepare BW parameters*/ 1131 bnx2x_status = bnx2x_ets_e3b0_get_total_bw(params, ets_params, 1132 &total_bw); 1133 if (bnx2x_status) { 1134 DP(NETIF_MSG_LINK, 1135 "bnx2x_ets_E3B0_config get_total_bw failed\n"); 1136 return -EINVAL; 1137 } 1138 1139 /* Upper bound is set according to current link speed (min_w_val 1140 * should be the same for upper bound and COS credit val). 1141 */ 1142 bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig); 1143 bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf); 1144 1145 1146 for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) { 1147 if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) { 1148 cos_bw_bitmap |= (1 << cos_entry); 1149 /* The function also sets the BW in HW(not the mappin 1150 * yet) 1151 */ 1152 bnx2x_status = bnx2x_ets_e3b0_set_cos_bw( 1153 bp, cos_entry, min_w_val_nig, min_w_val_pbf, 1154 total_bw, 1155 ets_params->cos[cos_entry].params.bw_params.bw, 1156 port); 1157 } else if (bnx2x_cos_state_strict == 1158 ets_params->cos[cos_entry].state){ 1159 cos_sp_bitmap |= (1 << cos_entry); 1160 1161 bnx2x_status = bnx2x_ets_e3b0_sp_pri_to_cos_set( 1162 params, 1163 sp_pri_to_cos, 1164 ets_params->cos[cos_entry].params.sp_params.pri, 1165 cos_entry); 1166 1167 } else { 1168 DP(NETIF_MSG_LINK, 1169 "bnx2x_ets_e3b0_config cos state not valid\n"); 1170 return -EINVAL; 1171 } 1172 if (bnx2x_status) { 1173 DP(NETIF_MSG_LINK, 1174 "bnx2x_ets_e3b0_config set cos bw failed\n"); 1175 return bnx2x_status; 1176 } 1177 } 1178 1179 /* Set SP register (which COS has higher priority) */ 1180 bnx2x_status = bnx2x_ets_e3b0_sp_set_pri_cli_reg(params, 1181 sp_pri_to_cos); 1182 1183 if (bnx2x_status) { 1184 DP(NETIF_MSG_LINK, 1185 "bnx2x_ets_E3B0_config set_pri_cli_reg failed\n"); 1186 return bnx2x_status; 1187 } 1188 1189 /* Set client mapping of BW and strict */ 1190 bnx2x_status = bnx2x_ets_e3b0_cli_map(params, ets_params, 1191 cos_sp_bitmap, 1192 cos_bw_bitmap); 1193 1194 if (bnx2x_status) { 1195 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config SP failed\n"); 1196 return bnx2x_status; 1197 } 1198 return 0; 1199 } 1200 static void bnx2x_ets_bw_limit_common(const struct link_params *params) 1201 { 1202 /* ETS disabled configuration */ 1203 struct bnx2x *bp = params->bp; 1204 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n"); 1205 /* Defines which entries (clients) are subjected to WFQ arbitration 1206 * COS0 0x8 1207 * COS1 0x10 1208 */ 1209 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18); 1210 /* Mapping between the ARB_CREDIT_WEIGHT registers and actual 1211 * client numbers (WEIGHT_0 does not actually have to represent 1212 * client 0) 1213 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 1214 * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010 1215 */ 1216 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A); 1217 1218 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 1219 ETS_BW_LIMIT_CREDIT_UPPER_BOUND); 1220 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 1221 ETS_BW_LIMIT_CREDIT_UPPER_BOUND); 1222 1223 /* ETS mode enabled*/ 1224 REG_WR(bp, PBF_REG_ETS_ENABLED, 1); 1225 1226 /* Defines the number of consecutive slots for the strict priority */ 1227 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); 1228 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves 1229 * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0 1230 * entry, 4 - COS1 entry. 1231 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT 1232 * bit4 bit3 bit2 bit1 bit0 1233 * MCP and debug are strict 1234 */ 1235 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); 1236 1237 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/ 1238 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 1239 ETS_BW_LIMIT_CREDIT_UPPER_BOUND); 1240 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 1241 ETS_BW_LIMIT_CREDIT_UPPER_BOUND); 1242 } 1243 1244 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw, 1245 const u32 cos1_bw) 1246 { 1247 /* ETS disabled configuration*/ 1248 struct bnx2x *bp = params->bp; 1249 const u32 total_bw = cos0_bw + cos1_bw; 1250 u32 cos0_credit_weight = 0; 1251 u32 cos1_credit_weight = 0; 1252 1253 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n"); 1254 1255 if ((!total_bw) || 1256 (!cos0_bw) || 1257 (!cos1_bw)) { 1258 DP(NETIF_MSG_LINK, "Total BW can't be zero\n"); 1259 return; 1260 } 1261 1262 cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/ 1263 total_bw; 1264 cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/ 1265 total_bw; 1266 1267 bnx2x_ets_bw_limit_common(params); 1268 1269 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight); 1270 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight); 1271 1272 REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight); 1273 REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight); 1274 } 1275 1276 int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos) 1277 { 1278 /* ETS disabled configuration*/ 1279 struct bnx2x *bp = params->bp; 1280 u32 val = 0; 1281 1282 DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n"); 1283 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves 1284 * as strict. Bits 0,1,2 - debug and management entries, 1285 * 3 - COS0 entry, 4 - COS1 entry. 1286 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT 1287 * bit4 bit3 bit2 bit1 bit0 1288 * MCP and debug are strict 1289 */ 1290 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F); 1291 /* For strict priority entries defines the number of consecutive slots 1292 * for the highest priority. 1293 */ 1294 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); 1295 /* ETS mode disable */ 1296 REG_WR(bp, PBF_REG_ETS_ENABLED, 0); 1297 /* Defines the number of consecutive slots for the strict priority */ 1298 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100); 1299 1300 /* Defines the number of consecutive slots for the strict priority */ 1301 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos); 1302 1303 /* Mapping between entry priority to client number (0,1,2 -debug and 1304 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST) 1305 * 3bits client num. 1306 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 1307 * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000 1308 * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000 1309 */ 1310 val = (!strict_cos) ? 0x2318 : 0x22E0; 1311 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val); 1312 1313 return 0; 1314 } 1315 1316 /******************************************************************/ 1317 /* PFC section */ 1318 /******************************************************************/ 1319 static void bnx2x_update_pfc_xmac(struct link_params *params, 1320 struct link_vars *vars, 1321 u8 is_lb) 1322 { 1323 struct bnx2x *bp = params->bp; 1324 u32 xmac_base; 1325 u32 pause_val, pfc0_val, pfc1_val; 1326 1327 /* XMAC base adrr */ 1328 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 1329 1330 /* Initialize pause and pfc registers */ 1331 pause_val = 0x18000; 1332 pfc0_val = 0xFFFF8000; 1333 pfc1_val = 0x2; 1334 1335 /* No PFC support */ 1336 if (!(params->feature_config_flags & 1337 FEATURE_CONFIG_PFC_ENABLED)) { 1338 1339 /* RX flow control - Process pause frame in receive direction 1340 */ 1341 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) 1342 pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN; 1343 1344 /* TX flow control - Send pause packet when buffer is full */ 1345 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) 1346 pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN; 1347 } else {/* PFC support */ 1348 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN | 1349 XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN | 1350 XMAC_PFC_CTRL_HI_REG_RX_PFC_EN | 1351 XMAC_PFC_CTRL_HI_REG_TX_PFC_EN | 1352 XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON; 1353 /* Write pause and PFC registers */ 1354 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); 1355 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); 1356 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); 1357 pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON; 1358 1359 } 1360 1361 /* Write pause and PFC registers */ 1362 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); 1363 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); 1364 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); 1365 1366 1367 /* Set MAC address for source TX Pause/PFC frames */ 1368 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO, 1369 ((params->mac_addr[2] << 24) | 1370 (params->mac_addr[3] << 16) | 1371 (params->mac_addr[4] << 8) | 1372 (params->mac_addr[5]))); 1373 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI, 1374 ((params->mac_addr[0] << 8) | 1375 (params->mac_addr[1]))); 1376 1377 udelay(30); 1378 } 1379 1380 1381 static void bnx2x_emac_get_pfc_stat(struct link_params *params, 1382 u32 pfc_frames_sent[2], 1383 u32 pfc_frames_received[2]) 1384 { 1385 /* Read pfc statistic */ 1386 struct bnx2x *bp = params->bp; 1387 u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 1388 u32 val_xon = 0; 1389 u32 val_xoff = 0; 1390 1391 DP(NETIF_MSG_LINK, "pfc statistic read from EMAC\n"); 1392 1393 /* PFC received frames */ 1394 val_xoff = REG_RD(bp, emac_base + 1395 EMAC_REG_RX_PFC_STATS_XOFF_RCVD); 1396 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT; 1397 val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD); 1398 val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT; 1399 1400 pfc_frames_received[0] = val_xon + val_xoff; 1401 1402 /* PFC received sent */ 1403 val_xoff = REG_RD(bp, emac_base + 1404 EMAC_REG_RX_PFC_STATS_XOFF_SENT); 1405 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT; 1406 val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT); 1407 val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT; 1408 1409 pfc_frames_sent[0] = val_xon + val_xoff; 1410 } 1411 1412 /* Read pfc statistic*/ 1413 void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars, 1414 u32 pfc_frames_sent[2], 1415 u32 pfc_frames_received[2]) 1416 { 1417 /* Read pfc statistic */ 1418 struct bnx2x *bp = params->bp; 1419 1420 DP(NETIF_MSG_LINK, "pfc statistic\n"); 1421 1422 if (!vars->link_up) 1423 return; 1424 1425 if (vars->mac_type == MAC_TYPE_EMAC) { 1426 DP(NETIF_MSG_LINK, "About to read PFC stats from EMAC\n"); 1427 bnx2x_emac_get_pfc_stat(params, pfc_frames_sent, 1428 pfc_frames_received); 1429 } 1430 } 1431 /******************************************************************/ 1432 /* MAC/PBF section */ 1433 /******************************************************************/ 1434 static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id, u8 port) 1435 { 1436 u32 mode, emac_base; 1437 /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz 1438 * (a value of 49==0x31) and make sure that the AUTO poll is off 1439 */ 1440 1441 if (CHIP_IS_E2(bp)) 1442 emac_base = GRCBASE_EMAC0; 1443 else 1444 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 1445 mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE); 1446 mode &= ~(EMAC_MDIO_MODE_AUTO_POLL | 1447 EMAC_MDIO_MODE_CLOCK_CNT); 1448 if (USES_WARPCORE(bp)) 1449 mode |= (74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT); 1450 else 1451 mode |= (49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT); 1452 1453 mode |= (EMAC_MDIO_MODE_CLAUSE_45); 1454 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, mode); 1455 1456 udelay(40); 1457 } 1458 static u8 bnx2x_is_4_port_mode(struct bnx2x *bp) 1459 { 1460 u32 port4mode_ovwr_val; 1461 /* Check 4-port override enabled */ 1462 port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); 1463 if (port4mode_ovwr_val & (1<<0)) { 1464 /* Return 4-port mode override value */ 1465 return ((port4mode_ovwr_val & (1<<1)) == (1<<1)); 1466 } 1467 /* Return 4-port mode from input pin */ 1468 return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN); 1469 } 1470 1471 static void bnx2x_emac_init(struct link_params *params, 1472 struct link_vars *vars) 1473 { 1474 /* reset and unreset the emac core */ 1475 struct bnx2x *bp = params->bp; 1476 u8 port = params->port; 1477 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 1478 u32 val; 1479 u16 timeout; 1480 1481 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1482 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port)); 1483 udelay(5); 1484 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 1485 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port)); 1486 1487 /* init emac - use read-modify-write */ 1488 /* self clear reset */ 1489 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); 1490 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET)); 1491 1492 timeout = 200; 1493 do { 1494 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); 1495 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val); 1496 if (!timeout) { 1497 DP(NETIF_MSG_LINK, "EMAC timeout!\n"); 1498 return; 1499 } 1500 timeout--; 1501 } while (val & EMAC_MODE_RESET); 1502 bnx2x_set_mdio_clk(bp, params->chip_id, port); 1503 /* Set mac address */ 1504 val = ((params->mac_addr[0] << 8) | 1505 params->mac_addr[1]); 1506 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val); 1507 1508 val = ((params->mac_addr[2] << 24) | 1509 (params->mac_addr[3] << 16) | 1510 (params->mac_addr[4] << 8) | 1511 params->mac_addr[5]); 1512 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val); 1513 } 1514 1515 static void bnx2x_set_xumac_nig(struct link_params *params, 1516 u16 tx_pause_en, 1517 u8 enable) 1518 { 1519 struct bnx2x *bp = params->bp; 1520 1521 REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN, 1522 enable); 1523 REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN, 1524 enable); 1525 REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN : 1526 NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en); 1527 } 1528 1529 static void bnx2x_set_umac_rxtx(struct link_params *params, u8 en) 1530 { 1531 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; 1532 u32 val; 1533 struct bnx2x *bp = params->bp; 1534 if (!(REG_RD(bp, MISC_REG_RESET_REG_2) & 1535 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port))) 1536 return; 1537 val = REG_RD(bp, umac_base + UMAC_REG_COMMAND_CONFIG); 1538 if (en) 1539 val |= (UMAC_COMMAND_CONFIG_REG_TX_ENA | 1540 UMAC_COMMAND_CONFIG_REG_RX_ENA); 1541 else 1542 val &= ~(UMAC_COMMAND_CONFIG_REG_TX_ENA | 1543 UMAC_COMMAND_CONFIG_REG_RX_ENA); 1544 /* Disable RX and TX */ 1545 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); 1546 } 1547 1548 static void bnx2x_umac_enable(struct link_params *params, 1549 struct link_vars *vars, u8 lb) 1550 { 1551 u32 val; 1552 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; 1553 struct bnx2x *bp = params->bp; 1554 /* Reset UMAC */ 1555 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1556 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)); 1557 usleep_range(1000, 2000); 1558 1559 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 1560 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)); 1561 1562 DP(NETIF_MSG_LINK, "enabling UMAC\n"); 1563 1564 /* This register opens the gate for the UMAC despite its name */ 1565 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); 1566 1567 val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN | 1568 UMAC_COMMAND_CONFIG_REG_PAD_EN | 1569 UMAC_COMMAND_CONFIG_REG_SW_RESET | 1570 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK; 1571 switch (vars->line_speed) { 1572 case SPEED_10: 1573 val |= (0<<2); 1574 break; 1575 case SPEED_100: 1576 val |= (1<<2); 1577 break; 1578 case SPEED_1000: 1579 val |= (2<<2); 1580 break; 1581 case SPEED_2500: 1582 val |= (3<<2); 1583 break; 1584 default: 1585 DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n", 1586 vars->line_speed); 1587 break; 1588 } 1589 if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) 1590 val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE; 1591 1592 if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)) 1593 val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE; 1594 1595 if (vars->duplex == DUPLEX_HALF) 1596 val |= UMAC_COMMAND_CONFIG_REG_HD_ENA; 1597 1598 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); 1599 udelay(50); 1600 1601 /* Configure UMAC for EEE */ 1602 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) { 1603 DP(NETIF_MSG_LINK, "configured UMAC for EEE\n"); 1604 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, 1605 UMAC_UMAC_EEE_CTRL_REG_EEE_EN); 1606 REG_WR(bp, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11); 1607 } else { 1608 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0); 1609 } 1610 1611 /* Set MAC address for source TX Pause/PFC frames (under SW reset) */ 1612 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0, 1613 ((params->mac_addr[2] << 24) | 1614 (params->mac_addr[3] << 16) | 1615 (params->mac_addr[4] << 8) | 1616 (params->mac_addr[5]))); 1617 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1, 1618 ((params->mac_addr[0] << 8) | 1619 (params->mac_addr[1]))); 1620 1621 /* Enable RX and TX */ 1622 val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN; 1623 val |= UMAC_COMMAND_CONFIG_REG_TX_ENA | 1624 UMAC_COMMAND_CONFIG_REG_RX_ENA; 1625 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); 1626 udelay(50); 1627 1628 /* Remove SW Reset */ 1629 val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET; 1630 1631 /* Check loopback mode */ 1632 if (lb) 1633 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA; 1634 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); 1635 1636 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame 1637 * length used by the MAC receive logic to check frames. 1638 */ 1639 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710); 1640 bnx2x_set_xumac_nig(params, 1641 ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1); 1642 vars->mac_type = MAC_TYPE_UMAC; 1643 1644 } 1645 1646 /* Define the XMAC mode */ 1647 static void bnx2x_xmac_init(struct link_params *params, u32 max_speed) 1648 { 1649 struct bnx2x *bp = params->bp; 1650 u32 is_port4mode = bnx2x_is_4_port_mode(bp); 1651 1652 /* In 4-port mode, need to set the mode only once, so if XMAC is 1653 * already out of reset, it means the mode has already been set, 1654 * and it must not* reset the XMAC again, since it controls both 1655 * ports of the path 1656 */ 1657 1658 if ((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) && 1659 (REG_RD(bp, MISC_REG_RESET_REG_2) & 1660 MISC_REGISTERS_RESET_REG_2_XMAC)) { 1661 DP(NETIF_MSG_LINK, 1662 "XMAC already out of reset in 4-port mode\n"); 1663 return; 1664 } 1665 1666 /* Hard reset */ 1667 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1668 MISC_REGISTERS_RESET_REG_2_XMAC); 1669 usleep_range(1000, 2000); 1670 1671 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 1672 MISC_REGISTERS_RESET_REG_2_XMAC); 1673 if (is_port4mode) { 1674 DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n"); 1675 1676 /* Set the number of ports on the system side to up to 2 */ 1677 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1); 1678 1679 /* Set the number of ports on the Warp Core to 10G */ 1680 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3); 1681 } else { 1682 /* Set the number of ports on the system side to 1 */ 1683 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0); 1684 if (max_speed == SPEED_10000) { 1685 DP(NETIF_MSG_LINK, 1686 "Init XMAC to 10G x 1 port per path\n"); 1687 /* Set the number of ports on the Warp Core to 10G */ 1688 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3); 1689 } else { 1690 DP(NETIF_MSG_LINK, 1691 "Init XMAC to 20G x 2 ports per path\n"); 1692 /* Set the number of ports on the Warp Core to 20G */ 1693 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1); 1694 } 1695 } 1696 /* Soft reset */ 1697 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1698 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT); 1699 usleep_range(1000, 2000); 1700 1701 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 1702 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT); 1703 1704 } 1705 1706 static void bnx2x_set_xmac_rxtx(struct link_params *params, u8 en) 1707 { 1708 u8 port = params->port; 1709 struct bnx2x *bp = params->bp; 1710 u32 pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 1711 u32 val; 1712 1713 if (REG_RD(bp, MISC_REG_RESET_REG_2) & 1714 MISC_REGISTERS_RESET_REG_2_XMAC) { 1715 /* Send an indication to change the state in the NIG back to XON 1716 * Clearing this bit enables the next set of this bit to get 1717 * rising edge 1718 */ 1719 pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI); 1720 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, 1721 (pfc_ctrl & ~(1<<1))); 1722 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, 1723 (pfc_ctrl | (1<<1))); 1724 DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port); 1725 val = REG_RD(bp, xmac_base + XMAC_REG_CTRL); 1726 if (en) 1727 val |= (XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN); 1728 else 1729 val &= ~(XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN); 1730 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val); 1731 } 1732 } 1733 1734 static int bnx2x_xmac_enable(struct link_params *params, 1735 struct link_vars *vars, u8 lb) 1736 { 1737 u32 val, xmac_base; 1738 struct bnx2x *bp = params->bp; 1739 DP(NETIF_MSG_LINK, "enabling XMAC\n"); 1740 1741 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 1742 1743 bnx2x_xmac_init(params, vars->line_speed); 1744 1745 /* This register determines on which events the MAC will assert 1746 * error on the i/f to the NIG along w/ EOP. 1747 */ 1748 1749 /* This register tells the NIG whether to send traffic to UMAC 1750 * or XMAC 1751 */ 1752 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0); 1753 1754 /* Set Max packet size */ 1755 REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710); 1756 1757 /* CRC append for Tx packets */ 1758 REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800); 1759 1760 /* update PFC */ 1761 bnx2x_update_pfc_xmac(params, vars, 0); 1762 1763 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) { 1764 DP(NETIF_MSG_LINK, "Setting XMAC for EEE\n"); 1765 REG_WR(bp, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008); 1766 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x1); 1767 } else { 1768 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x0); 1769 } 1770 1771 /* Enable TX and RX */ 1772 val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN; 1773 1774 /* Check loopback mode */ 1775 if (lb) 1776 val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK; 1777 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val); 1778 bnx2x_set_xumac_nig(params, 1779 ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1); 1780 1781 vars->mac_type = MAC_TYPE_XMAC; 1782 1783 return 0; 1784 } 1785 1786 static int bnx2x_emac_enable(struct link_params *params, 1787 struct link_vars *vars, u8 lb) 1788 { 1789 struct bnx2x *bp = params->bp; 1790 u8 port = params->port; 1791 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 1792 u32 val; 1793 1794 DP(NETIF_MSG_LINK, "enabling EMAC\n"); 1795 1796 /* Disable BMAC */ 1797 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1798 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 1799 1800 /* enable emac and not bmac */ 1801 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1); 1802 1803 /* ASIC */ 1804 if (vars->phy_flags & PHY_XGXS_FLAG) { 1805 u32 ser_lane = ((params->lane_config & 1806 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> 1807 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); 1808 1809 DP(NETIF_MSG_LINK, "XGXS\n"); 1810 /* select the master lanes (out of 0-3) */ 1811 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane); 1812 /* select XGXS */ 1813 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); 1814 1815 } else { /* SerDes */ 1816 DP(NETIF_MSG_LINK, "SerDes\n"); 1817 /* select SerDes */ 1818 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0); 1819 } 1820 1821 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE, 1822 EMAC_RX_MODE_RESET); 1823 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE, 1824 EMAC_TX_MODE_RESET); 1825 1826 /* pause enable/disable */ 1827 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE, 1828 EMAC_RX_MODE_FLOW_EN); 1829 1830 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE, 1831 (EMAC_TX_MODE_EXT_PAUSE_EN | 1832 EMAC_TX_MODE_FLOW_EN)); 1833 if (!(params->feature_config_flags & 1834 FEATURE_CONFIG_PFC_ENABLED)) { 1835 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) 1836 bnx2x_bits_en(bp, emac_base + 1837 EMAC_REG_EMAC_RX_MODE, 1838 EMAC_RX_MODE_FLOW_EN); 1839 1840 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) 1841 bnx2x_bits_en(bp, emac_base + 1842 EMAC_REG_EMAC_TX_MODE, 1843 (EMAC_TX_MODE_EXT_PAUSE_EN | 1844 EMAC_TX_MODE_FLOW_EN)); 1845 } else 1846 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE, 1847 EMAC_TX_MODE_FLOW_EN); 1848 1849 /* KEEP_VLAN_TAG, promiscuous */ 1850 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE); 1851 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS; 1852 1853 /* Setting this bit causes MAC control frames (except for pause 1854 * frames) to be passed on for processing. This setting has no 1855 * affect on the operation of the pause frames. This bit effects 1856 * all packets regardless of RX Parser packet sorting logic. 1857 * Turn the PFC off to make sure we are in Xon state before 1858 * enabling it. 1859 */ 1860 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0); 1861 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) { 1862 DP(NETIF_MSG_LINK, "PFC is enabled\n"); 1863 /* Enable PFC again */ 1864 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 1865 EMAC_REG_RX_PFC_MODE_RX_EN | 1866 EMAC_REG_RX_PFC_MODE_TX_EN | 1867 EMAC_REG_RX_PFC_MODE_PRIORITIES); 1868 1869 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM, 1870 ((0x0101 << 1871 EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) | 1872 (0x00ff << 1873 EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT))); 1874 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL; 1875 } 1876 EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val); 1877 1878 /* Set Loopback */ 1879 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); 1880 if (lb) 1881 val |= 0x810; 1882 else 1883 val &= ~0x810; 1884 EMAC_WR(bp, EMAC_REG_EMAC_MODE, val); 1885 1886 /* Enable emac */ 1887 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1); 1888 1889 /* Enable emac for jumbo packets */ 1890 EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE, 1891 (EMAC_RX_MTU_SIZE_JUMBO_ENA | 1892 (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD))); 1893 1894 /* Strip CRC */ 1895 REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1); 1896 1897 /* Disable the NIG in/out to the bmac */ 1898 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0); 1899 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0); 1900 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0); 1901 1902 /* Enable the NIG in/out to the emac */ 1903 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1); 1904 val = 0; 1905 if ((params->feature_config_flags & 1906 FEATURE_CONFIG_PFC_ENABLED) || 1907 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) 1908 val = 1; 1909 1910 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val); 1911 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1); 1912 1913 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0); 1914 1915 vars->mac_type = MAC_TYPE_EMAC; 1916 return 0; 1917 } 1918 1919 static void bnx2x_update_pfc_bmac1(struct link_params *params, 1920 struct link_vars *vars) 1921 { 1922 u32 wb_data[2]; 1923 struct bnx2x *bp = params->bp; 1924 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM : 1925 NIG_REG_INGRESS_BMAC0_MEM; 1926 1927 u32 val = 0x14; 1928 if ((!(params->feature_config_flags & 1929 FEATURE_CONFIG_PFC_ENABLED)) && 1930 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)) 1931 /* Enable BigMAC to react on received Pause packets */ 1932 val |= (1<<5); 1933 wb_data[0] = val; 1934 wb_data[1] = 0; 1935 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2); 1936 1937 /* TX control */ 1938 val = 0xc0; 1939 if (!(params->feature_config_flags & 1940 FEATURE_CONFIG_PFC_ENABLED) && 1941 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) 1942 val |= 0x800000; 1943 wb_data[0] = val; 1944 wb_data[1] = 0; 1945 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2); 1946 } 1947 1948 static void bnx2x_update_pfc_bmac2(struct link_params *params, 1949 struct link_vars *vars, 1950 u8 is_lb) 1951 { 1952 /* Set rx control: Strip CRC and enable BigMAC to relay 1953 * control packets to the system as well 1954 */ 1955 u32 wb_data[2]; 1956 struct bnx2x *bp = params->bp; 1957 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM : 1958 NIG_REG_INGRESS_BMAC0_MEM; 1959 u32 val = 0x14; 1960 1961 if ((!(params->feature_config_flags & 1962 FEATURE_CONFIG_PFC_ENABLED)) && 1963 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)) 1964 /* Enable BigMAC to react on received Pause packets */ 1965 val |= (1<<5); 1966 wb_data[0] = val; 1967 wb_data[1] = 0; 1968 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2); 1969 udelay(30); 1970 1971 /* Tx control */ 1972 val = 0xc0; 1973 if (!(params->feature_config_flags & 1974 FEATURE_CONFIG_PFC_ENABLED) && 1975 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) 1976 val |= 0x800000; 1977 wb_data[0] = val; 1978 wb_data[1] = 0; 1979 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2); 1980 1981 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) { 1982 DP(NETIF_MSG_LINK, "PFC is enabled\n"); 1983 /* Enable PFC RX & TX & STATS and set 8 COS */ 1984 wb_data[0] = 0x0; 1985 wb_data[0] |= (1<<0); /* RX */ 1986 wb_data[0] |= (1<<1); /* TX */ 1987 wb_data[0] |= (1<<2); /* Force initial Xon */ 1988 wb_data[0] |= (1<<3); /* 8 cos */ 1989 wb_data[0] |= (1<<5); /* STATS */ 1990 wb_data[1] = 0; 1991 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, 1992 wb_data, 2); 1993 /* Clear the force Xon */ 1994 wb_data[0] &= ~(1<<2); 1995 } else { 1996 DP(NETIF_MSG_LINK, "PFC is disabled\n"); 1997 /* Disable PFC RX & TX & STATS and set 8 COS */ 1998 wb_data[0] = 0x8; 1999 wb_data[1] = 0; 2000 } 2001 2002 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2); 2003 2004 /* Set Time (based unit is 512 bit time) between automatic 2005 * re-sending of PP packets amd enable automatic re-send of 2006 * Per-Priroity Packet as long as pp_gen is asserted and 2007 * pp_disable is low. 2008 */ 2009 val = 0x8000; 2010 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) 2011 val |= (1<<16); /* enable automatic re-send */ 2012 2013 wb_data[0] = val; 2014 wb_data[1] = 0; 2015 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL, 2016 wb_data, 2); 2017 2018 /* mac control */ 2019 val = 0x3; /* Enable RX and TX */ 2020 if (is_lb) { 2021 val |= 0x4; /* Local loopback */ 2022 DP(NETIF_MSG_LINK, "enable bmac loopback\n"); 2023 } 2024 /* When PFC enabled, Pass pause frames towards the NIG. */ 2025 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) 2026 val |= ((1<<6)|(1<<5)); 2027 2028 wb_data[0] = val; 2029 wb_data[1] = 0; 2030 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2); 2031 } 2032 2033 /****************************************************************************** 2034 * Description: 2035 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are 2036 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable. 2037 ******************************************************************************/ 2038 static int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp, 2039 u8 cos_entry, 2040 u32 priority_mask, u8 port) 2041 { 2042 u32 nig_reg_rx_priority_mask_add = 0; 2043 2044 switch (cos_entry) { 2045 case 0: 2046 nig_reg_rx_priority_mask_add = (port) ? 2047 NIG_REG_P1_RX_COS0_PRIORITY_MASK : 2048 NIG_REG_P0_RX_COS0_PRIORITY_MASK; 2049 break; 2050 case 1: 2051 nig_reg_rx_priority_mask_add = (port) ? 2052 NIG_REG_P1_RX_COS1_PRIORITY_MASK : 2053 NIG_REG_P0_RX_COS1_PRIORITY_MASK; 2054 break; 2055 case 2: 2056 nig_reg_rx_priority_mask_add = (port) ? 2057 NIG_REG_P1_RX_COS2_PRIORITY_MASK : 2058 NIG_REG_P0_RX_COS2_PRIORITY_MASK; 2059 break; 2060 case 3: 2061 if (port) 2062 return -EINVAL; 2063 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK; 2064 break; 2065 case 4: 2066 if (port) 2067 return -EINVAL; 2068 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK; 2069 break; 2070 case 5: 2071 if (port) 2072 return -EINVAL; 2073 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK; 2074 break; 2075 } 2076 2077 REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask); 2078 2079 return 0; 2080 } 2081 static void bnx2x_update_mng(struct link_params *params, u32 link_status) 2082 { 2083 struct bnx2x *bp = params->bp; 2084 2085 REG_WR(bp, params->shmem_base + 2086 offsetof(struct shmem_region, 2087 port_mb[params->port].link_status), link_status); 2088 } 2089 2090 static void bnx2x_update_pfc_nig(struct link_params *params, 2091 struct link_vars *vars, 2092 struct bnx2x_nig_brb_pfc_port_params *nig_params) 2093 { 2094 u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0; 2095 u32 llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0; 2096 u32 pkt_priority_to_cos = 0; 2097 struct bnx2x *bp = params->bp; 2098 u8 port = params->port; 2099 2100 int set_pfc = params->feature_config_flags & 2101 FEATURE_CONFIG_PFC_ENABLED; 2102 DP(NETIF_MSG_LINK, "updating pfc nig parameters\n"); 2103 2104 /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set 2105 * MAC control frames (that are not pause packets) 2106 * will be forwarded to the XCM. 2107 */ 2108 xcm_mask = REG_RD(bp, port ? NIG_REG_LLH1_XCM_MASK : 2109 NIG_REG_LLH0_XCM_MASK); 2110 /* NIG params will override non PFC params, since it's possible to 2111 * do transition from PFC to SAFC 2112 */ 2113 if (set_pfc) { 2114 pause_enable = 0; 2115 llfc_out_en = 0; 2116 llfc_enable = 0; 2117 if (CHIP_IS_E3(bp)) 2118 ppp_enable = 0; 2119 else 2120 ppp_enable = 1; 2121 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN : 2122 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN); 2123 xcm_out_en = 0; 2124 hwpfc_enable = 1; 2125 } else { 2126 if (nig_params) { 2127 llfc_out_en = nig_params->llfc_out_en; 2128 llfc_enable = nig_params->llfc_enable; 2129 pause_enable = nig_params->pause_enable; 2130 } else /* Default non PFC mode - PAUSE */ 2131 pause_enable = 1; 2132 2133 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN : 2134 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN); 2135 xcm_out_en = 1; 2136 } 2137 2138 if (CHIP_IS_E3(bp)) 2139 REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN : 2140 NIG_REG_BRB0_PAUSE_IN_EN, pause_enable); 2141 REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 : 2142 NIG_REG_LLFC_OUT_EN_0, llfc_out_en); 2143 REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 : 2144 NIG_REG_LLFC_ENABLE_0, llfc_enable); 2145 REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 : 2146 NIG_REG_PAUSE_ENABLE_0, pause_enable); 2147 2148 REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 : 2149 NIG_REG_PPP_ENABLE_0, ppp_enable); 2150 2151 REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK : 2152 NIG_REG_LLH0_XCM_MASK, xcm_mask); 2153 2154 REG_WR(bp, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 : 2155 NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7); 2156 2157 /* Output enable for RX_XCM # IF */ 2158 REG_WR(bp, port ? NIG_REG_XCM1_OUT_EN : 2159 NIG_REG_XCM0_OUT_EN, xcm_out_en); 2160 2161 /* HW PFC TX enable */ 2162 REG_WR(bp, port ? NIG_REG_P1_HWPFC_ENABLE : 2163 NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable); 2164 2165 if (nig_params) { 2166 u8 i = 0; 2167 pkt_priority_to_cos = nig_params->pkt_priority_to_cos; 2168 2169 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++) 2170 bnx2x_pfc_nig_rx_priority_mask(bp, i, 2171 nig_params->rx_cos_priority_mask[i], port); 2172 2173 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 : 2174 NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0, 2175 nig_params->llfc_high_priority_classes); 2176 2177 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 : 2178 NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0, 2179 nig_params->llfc_low_priority_classes); 2180 } 2181 REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS : 2182 NIG_REG_P0_PKT_PRIORITY_TO_COS, 2183 pkt_priority_to_cos); 2184 } 2185 2186 int bnx2x_update_pfc(struct link_params *params, 2187 struct link_vars *vars, 2188 struct bnx2x_nig_brb_pfc_port_params *pfc_params) 2189 { 2190 /* The PFC and pause are orthogonal to one another, meaning when 2191 * PFC is enabled, the pause are disabled, and when PFC is 2192 * disabled, pause are set according to the pause result. 2193 */ 2194 u32 val; 2195 struct bnx2x *bp = params->bp; 2196 int bnx2x_status = 0; 2197 u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC); 2198 2199 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) 2200 vars->link_status |= LINK_STATUS_PFC_ENABLED; 2201 else 2202 vars->link_status &= ~LINK_STATUS_PFC_ENABLED; 2203 2204 bnx2x_update_mng(params, vars->link_status); 2205 2206 /* Update NIG params */ 2207 bnx2x_update_pfc_nig(params, vars, pfc_params); 2208 2209 if (!vars->link_up) 2210 return bnx2x_status; 2211 2212 DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n"); 2213 2214 if (CHIP_IS_E3(bp)) { 2215 if (vars->mac_type == MAC_TYPE_XMAC) 2216 bnx2x_update_pfc_xmac(params, vars, 0); 2217 } else { 2218 val = REG_RD(bp, MISC_REG_RESET_REG_2); 2219 if ((val & 2220 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) 2221 == 0) { 2222 DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n"); 2223 bnx2x_emac_enable(params, vars, 0); 2224 return bnx2x_status; 2225 } 2226 if (CHIP_IS_E2(bp)) 2227 bnx2x_update_pfc_bmac2(params, vars, bmac_loopback); 2228 else 2229 bnx2x_update_pfc_bmac1(params, vars); 2230 2231 val = 0; 2232 if ((params->feature_config_flags & 2233 FEATURE_CONFIG_PFC_ENABLED) || 2234 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) 2235 val = 1; 2236 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val); 2237 } 2238 return bnx2x_status; 2239 } 2240 2241 2242 static int bnx2x_bmac1_enable(struct link_params *params, 2243 struct link_vars *vars, 2244 u8 is_lb) 2245 { 2246 struct bnx2x *bp = params->bp; 2247 u8 port = params->port; 2248 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : 2249 NIG_REG_INGRESS_BMAC0_MEM; 2250 u32 wb_data[2]; 2251 u32 val; 2252 2253 DP(NETIF_MSG_LINK, "Enabling BigMAC1\n"); 2254 2255 /* XGXS control */ 2256 wb_data[0] = 0x3c; 2257 wb_data[1] = 0; 2258 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL, 2259 wb_data, 2); 2260 2261 /* TX MAC SA */ 2262 wb_data[0] = ((params->mac_addr[2] << 24) | 2263 (params->mac_addr[3] << 16) | 2264 (params->mac_addr[4] << 8) | 2265 params->mac_addr[5]); 2266 wb_data[1] = ((params->mac_addr[0] << 8) | 2267 params->mac_addr[1]); 2268 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2); 2269 2270 /* MAC control */ 2271 val = 0x3; 2272 if (is_lb) { 2273 val |= 0x4; 2274 DP(NETIF_MSG_LINK, "enable bmac loopback\n"); 2275 } 2276 wb_data[0] = val; 2277 wb_data[1] = 0; 2278 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2); 2279 2280 /* Set rx mtu */ 2281 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; 2282 wb_data[1] = 0; 2283 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2); 2284 2285 bnx2x_update_pfc_bmac1(params, vars); 2286 2287 /* Set tx mtu */ 2288 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; 2289 wb_data[1] = 0; 2290 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2); 2291 2292 /* Set cnt max size */ 2293 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; 2294 wb_data[1] = 0; 2295 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2); 2296 2297 /* Configure SAFC */ 2298 wb_data[0] = 0x1000200; 2299 wb_data[1] = 0; 2300 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS, 2301 wb_data, 2); 2302 2303 return 0; 2304 } 2305 2306 static int bnx2x_bmac2_enable(struct link_params *params, 2307 struct link_vars *vars, 2308 u8 is_lb) 2309 { 2310 struct bnx2x *bp = params->bp; 2311 u8 port = params->port; 2312 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : 2313 NIG_REG_INGRESS_BMAC0_MEM; 2314 u32 wb_data[2]; 2315 2316 DP(NETIF_MSG_LINK, "Enabling BigMAC2\n"); 2317 2318 wb_data[0] = 0; 2319 wb_data[1] = 0; 2320 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2); 2321 udelay(30); 2322 2323 /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */ 2324 wb_data[0] = 0x3c; 2325 wb_data[1] = 0; 2326 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL, 2327 wb_data, 2); 2328 2329 udelay(30); 2330 2331 /* TX MAC SA */ 2332 wb_data[0] = ((params->mac_addr[2] << 24) | 2333 (params->mac_addr[3] << 16) | 2334 (params->mac_addr[4] << 8) | 2335 params->mac_addr[5]); 2336 wb_data[1] = ((params->mac_addr[0] << 8) | 2337 params->mac_addr[1]); 2338 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR, 2339 wb_data, 2); 2340 2341 udelay(30); 2342 2343 /* Configure SAFC */ 2344 wb_data[0] = 0x1000200; 2345 wb_data[1] = 0; 2346 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS, 2347 wb_data, 2); 2348 udelay(30); 2349 2350 /* Set RX MTU */ 2351 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; 2352 wb_data[1] = 0; 2353 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2); 2354 udelay(30); 2355 2356 /* Set TX MTU */ 2357 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; 2358 wb_data[1] = 0; 2359 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2); 2360 udelay(30); 2361 /* Set cnt max size */ 2362 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2; 2363 wb_data[1] = 0; 2364 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2); 2365 udelay(30); 2366 bnx2x_update_pfc_bmac2(params, vars, is_lb); 2367 2368 return 0; 2369 } 2370 2371 static int bnx2x_bmac_enable(struct link_params *params, 2372 struct link_vars *vars, 2373 u8 is_lb, u8 reset_bmac) 2374 { 2375 int rc = 0; 2376 u8 port = params->port; 2377 struct bnx2x *bp = params->bp; 2378 u32 val; 2379 /* Reset and unreset the BigMac */ 2380 if (reset_bmac) { 2381 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 2382 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 2383 usleep_range(1000, 2000); 2384 } 2385 2386 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 2387 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 2388 2389 /* Enable access for bmac registers */ 2390 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1); 2391 2392 /* Enable BMAC according to BMAC type*/ 2393 if (CHIP_IS_E2(bp)) 2394 rc = bnx2x_bmac2_enable(params, vars, is_lb); 2395 else 2396 rc = bnx2x_bmac1_enable(params, vars, is_lb); 2397 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1); 2398 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0); 2399 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0); 2400 val = 0; 2401 if ((params->feature_config_flags & 2402 FEATURE_CONFIG_PFC_ENABLED) || 2403 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) 2404 val = 1; 2405 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val); 2406 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0); 2407 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0); 2408 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0); 2409 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1); 2410 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1); 2411 2412 vars->mac_type = MAC_TYPE_BMAC; 2413 return rc; 2414 } 2415 2416 static void bnx2x_set_bmac_rx(struct bnx2x *bp, u32 chip_id, u8 port, u8 en) 2417 { 2418 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : 2419 NIG_REG_INGRESS_BMAC0_MEM; 2420 u32 wb_data[2]; 2421 u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4); 2422 2423 if (CHIP_IS_E2(bp)) 2424 bmac_addr += BIGMAC2_REGISTER_BMAC_CONTROL; 2425 else 2426 bmac_addr += BIGMAC_REGISTER_BMAC_CONTROL; 2427 /* Only if the bmac is out of reset */ 2428 if (REG_RD(bp, MISC_REG_RESET_REG_2) & 2429 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) && 2430 nig_bmac_enable) { 2431 /* Clear Rx Enable bit in BMAC_CONTROL register */ 2432 REG_RD_DMAE(bp, bmac_addr, wb_data, 2); 2433 if (en) 2434 wb_data[0] |= BMAC_CONTROL_RX_ENABLE; 2435 else 2436 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE; 2437 REG_WR_DMAE(bp, bmac_addr, wb_data, 2); 2438 usleep_range(1000, 2000); 2439 } 2440 } 2441 2442 static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl, 2443 u32 line_speed) 2444 { 2445 struct bnx2x *bp = params->bp; 2446 u8 port = params->port; 2447 u32 init_crd, crd; 2448 u32 count = 1000; 2449 2450 /* Disable port */ 2451 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1); 2452 2453 /* Wait for init credit */ 2454 init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4); 2455 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); 2456 DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd); 2457 2458 while ((init_crd != crd) && count) { 2459 usleep_range(5000, 10000); 2460 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); 2461 count--; 2462 } 2463 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); 2464 if (init_crd != crd) { 2465 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n", 2466 init_crd, crd); 2467 return -EINVAL; 2468 } 2469 2470 if (flow_ctrl & BNX2X_FLOW_CTRL_RX || 2471 line_speed == SPEED_10 || 2472 line_speed == SPEED_100 || 2473 line_speed == SPEED_1000 || 2474 line_speed == SPEED_2500) { 2475 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1); 2476 /* Update threshold */ 2477 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0); 2478 /* Update init credit */ 2479 init_crd = 778; /* (800-18-4) */ 2480 2481 } else { 2482 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE + 2483 ETH_OVREHEAD)/16; 2484 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); 2485 /* Update threshold */ 2486 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh); 2487 /* Update init credit */ 2488 switch (line_speed) { 2489 case SPEED_10000: 2490 init_crd = thresh + 553 - 22; 2491 break; 2492 default: 2493 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", 2494 line_speed); 2495 return -EINVAL; 2496 } 2497 } 2498 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd); 2499 DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n", 2500 line_speed, init_crd); 2501 2502 /* Probe the credit changes */ 2503 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1); 2504 usleep_range(5000, 10000); 2505 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0); 2506 2507 /* Enable port */ 2508 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0); 2509 return 0; 2510 } 2511 2512 /** 2513 * bnx2x_get_emac_base - retrive emac base address 2514 * 2515 * @bp: driver handle 2516 * @mdc_mdio_access: access type 2517 * @port: port id 2518 * 2519 * This function selects the MDC/MDIO access (through emac0 or 2520 * emac1) depend on the mdc_mdio_access, port, port swapped. Each 2521 * phy has a default access mode, which could also be overridden 2522 * by nvram configuration. This parameter, whether this is the 2523 * default phy configuration, or the nvram overrun 2524 * configuration, is passed here as mdc_mdio_access and selects 2525 * the emac_base for the CL45 read/writes operations 2526 */ 2527 static u32 bnx2x_get_emac_base(struct bnx2x *bp, 2528 u32 mdc_mdio_access, u8 port) 2529 { 2530 u32 emac_base = 0; 2531 switch (mdc_mdio_access) { 2532 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE: 2533 break; 2534 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0: 2535 if (REG_RD(bp, NIG_REG_PORT_SWAP)) 2536 emac_base = GRCBASE_EMAC1; 2537 else 2538 emac_base = GRCBASE_EMAC0; 2539 break; 2540 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1: 2541 if (REG_RD(bp, NIG_REG_PORT_SWAP)) 2542 emac_base = GRCBASE_EMAC0; 2543 else 2544 emac_base = GRCBASE_EMAC1; 2545 break; 2546 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH: 2547 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 2548 break; 2549 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED: 2550 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1; 2551 break; 2552 default: 2553 break; 2554 } 2555 return emac_base; 2556 2557 } 2558 2559 /******************************************************************/ 2560 /* CL22 access functions */ 2561 /******************************************************************/ 2562 static int bnx2x_cl22_write(struct bnx2x *bp, 2563 struct bnx2x_phy *phy, 2564 u16 reg, u16 val) 2565 { 2566 u32 tmp, mode; 2567 u8 i; 2568 int rc = 0; 2569 /* Switch to CL22 */ 2570 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); 2571 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, 2572 mode & ~EMAC_MDIO_MODE_CLAUSE_45); 2573 2574 /* Address */ 2575 tmp = ((phy->addr << 21) | (reg << 16) | val | 2576 EMAC_MDIO_COMM_COMMAND_WRITE_22 | 2577 EMAC_MDIO_COMM_START_BUSY); 2578 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); 2579 2580 for (i = 0; i < 50; i++) { 2581 udelay(10); 2582 2583 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); 2584 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { 2585 udelay(5); 2586 break; 2587 } 2588 } 2589 if (tmp & EMAC_MDIO_COMM_START_BUSY) { 2590 DP(NETIF_MSG_LINK, "write phy register failed\n"); 2591 rc = -EFAULT; 2592 } 2593 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); 2594 return rc; 2595 } 2596 2597 static int bnx2x_cl22_read(struct bnx2x *bp, 2598 struct bnx2x_phy *phy, 2599 u16 reg, u16 *ret_val) 2600 { 2601 u32 val, mode; 2602 u16 i; 2603 int rc = 0; 2604 2605 /* Switch to CL22 */ 2606 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); 2607 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, 2608 mode & ~EMAC_MDIO_MODE_CLAUSE_45); 2609 2610 /* Address */ 2611 val = ((phy->addr << 21) | (reg << 16) | 2612 EMAC_MDIO_COMM_COMMAND_READ_22 | 2613 EMAC_MDIO_COMM_START_BUSY); 2614 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); 2615 2616 for (i = 0; i < 50; i++) { 2617 udelay(10); 2618 2619 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); 2620 if (!(val & EMAC_MDIO_COMM_START_BUSY)) { 2621 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA); 2622 udelay(5); 2623 break; 2624 } 2625 } 2626 if (val & EMAC_MDIO_COMM_START_BUSY) { 2627 DP(NETIF_MSG_LINK, "read phy register failed\n"); 2628 2629 *ret_val = 0; 2630 rc = -EFAULT; 2631 } 2632 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); 2633 return rc; 2634 } 2635 2636 /******************************************************************/ 2637 /* CL45 access functions */ 2638 /******************************************************************/ 2639 static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy, 2640 u8 devad, u16 reg, u16 *ret_val) 2641 { 2642 u32 val; 2643 u16 i; 2644 int rc = 0; 2645 if (phy->flags & FLAGS_MDC_MDIO_WA_B0) 2646 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, 2647 EMAC_MDIO_STATUS_10MB); 2648 /* Address */ 2649 val = ((phy->addr << 21) | (devad << 16) | reg | 2650 EMAC_MDIO_COMM_COMMAND_ADDRESS | 2651 EMAC_MDIO_COMM_START_BUSY); 2652 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); 2653 2654 for (i = 0; i < 50; i++) { 2655 udelay(10); 2656 2657 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); 2658 if (!(val & EMAC_MDIO_COMM_START_BUSY)) { 2659 udelay(5); 2660 break; 2661 } 2662 } 2663 if (val & EMAC_MDIO_COMM_START_BUSY) { 2664 DP(NETIF_MSG_LINK, "read phy register failed\n"); 2665 netdev_err(bp->dev, "MDC/MDIO access timeout\n"); 2666 *ret_val = 0; 2667 rc = -EFAULT; 2668 } else { 2669 /* Data */ 2670 val = ((phy->addr << 21) | (devad << 16) | 2671 EMAC_MDIO_COMM_COMMAND_READ_45 | 2672 EMAC_MDIO_COMM_START_BUSY); 2673 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); 2674 2675 for (i = 0; i < 50; i++) { 2676 udelay(10); 2677 2678 val = REG_RD(bp, phy->mdio_ctrl + 2679 EMAC_REG_EMAC_MDIO_COMM); 2680 if (!(val & EMAC_MDIO_COMM_START_BUSY)) { 2681 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA); 2682 break; 2683 } 2684 } 2685 if (val & EMAC_MDIO_COMM_START_BUSY) { 2686 DP(NETIF_MSG_LINK, "read phy register failed\n"); 2687 netdev_err(bp->dev, "MDC/MDIO access timeout\n"); 2688 *ret_val = 0; 2689 rc = -EFAULT; 2690 } 2691 } 2692 /* Work around for E3 A0 */ 2693 if (phy->flags & FLAGS_MDC_MDIO_WA) { 2694 phy->flags ^= FLAGS_DUMMY_READ; 2695 if (phy->flags & FLAGS_DUMMY_READ) { 2696 u16 temp_val; 2697 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val); 2698 } 2699 } 2700 2701 if (phy->flags & FLAGS_MDC_MDIO_WA_B0) 2702 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, 2703 EMAC_MDIO_STATUS_10MB); 2704 return rc; 2705 } 2706 2707 static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy, 2708 u8 devad, u16 reg, u16 val) 2709 { 2710 u32 tmp; 2711 u8 i; 2712 int rc = 0; 2713 if (phy->flags & FLAGS_MDC_MDIO_WA_B0) 2714 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, 2715 EMAC_MDIO_STATUS_10MB); 2716 2717 /* Address */ 2718 tmp = ((phy->addr << 21) | (devad << 16) | reg | 2719 EMAC_MDIO_COMM_COMMAND_ADDRESS | 2720 EMAC_MDIO_COMM_START_BUSY); 2721 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); 2722 2723 for (i = 0; i < 50; i++) { 2724 udelay(10); 2725 2726 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); 2727 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { 2728 udelay(5); 2729 break; 2730 } 2731 } 2732 if (tmp & EMAC_MDIO_COMM_START_BUSY) { 2733 DP(NETIF_MSG_LINK, "write phy register failed\n"); 2734 netdev_err(bp->dev, "MDC/MDIO access timeout\n"); 2735 rc = -EFAULT; 2736 } else { 2737 /* Data */ 2738 tmp = ((phy->addr << 21) | (devad << 16) | val | 2739 EMAC_MDIO_COMM_COMMAND_WRITE_45 | 2740 EMAC_MDIO_COMM_START_BUSY); 2741 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); 2742 2743 for (i = 0; i < 50; i++) { 2744 udelay(10); 2745 2746 tmp = REG_RD(bp, phy->mdio_ctrl + 2747 EMAC_REG_EMAC_MDIO_COMM); 2748 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { 2749 udelay(5); 2750 break; 2751 } 2752 } 2753 if (tmp & EMAC_MDIO_COMM_START_BUSY) { 2754 DP(NETIF_MSG_LINK, "write phy register failed\n"); 2755 netdev_err(bp->dev, "MDC/MDIO access timeout\n"); 2756 rc = -EFAULT; 2757 } 2758 } 2759 /* Work around for E3 A0 */ 2760 if (phy->flags & FLAGS_MDC_MDIO_WA) { 2761 phy->flags ^= FLAGS_DUMMY_READ; 2762 if (phy->flags & FLAGS_DUMMY_READ) { 2763 u16 temp_val; 2764 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val); 2765 } 2766 } 2767 if (phy->flags & FLAGS_MDC_MDIO_WA_B0) 2768 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, 2769 EMAC_MDIO_STATUS_10MB); 2770 return rc; 2771 } 2772 2773 /******************************************************************/ 2774 /* EEE section */ 2775 /******************************************************************/ 2776 static u8 bnx2x_eee_has_cap(struct link_params *params) 2777 { 2778 struct bnx2x *bp = params->bp; 2779 2780 if (REG_RD(bp, params->shmem2_base) <= 2781 offsetof(struct shmem2_region, eee_status[params->port])) 2782 return 0; 2783 2784 return 1; 2785 } 2786 2787 static int bnx2x_eee_nvram_to_time(u32 nvram_mode, u32 *idle_timer) 2788 { 2789 switch (nvram_mode) { 2790 case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED: 2791 *idle_timer = EEE_MODE_NVRAM_BALANCED_TIME; 2792 break; 2793 case PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE: 2794 *idle_timer = EEE_MODE_NVRAM_AGGRESSIVE_TIME; 2795 break; 2796 case PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY: 2797 *idle_timer = EEE_MODE_NVRAM_LATENCY_TIME; 2798 break; 2799 default: 2800 *idle_timer = 0; 2801 break; 2802 } 2803 2804 return 0; 2805 } 2806 2807 static int bnx2x_eee_time_to_nvram(u32 idle_timer, u32 *nvram_mode) 2808 { 2809 switch (idle_timer) { 2810 case EEE_MODE_NVRAM_BALANCED_TIME: 2811 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED; 2812 break; 2813 case EEE_MODE_NVRAM_AGGRESSIVE_TIME: 2814 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE; 2815 break; 2816 case EEE_MODE_NVRAM_LATENCY_TIME: 2817 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY; 2818 break; 2819 default: 2820 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED; 2821 break; 2822 } 2823 2824 return 0; 2825 } 2826 2827 static u32 bnx2x_eee_calc_timer(struct link_params *params) 2828 { 2829 u32 eee_mode, eee_idle; 2830 struct bnx2x *bp = params->bp; 2831 2832 if (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) { 2833 if (params->eee_mode & EEE_MODE_OUTPUT_TIME) { 2834 /* time value in eee_mode --> used directly*/ 2835 eee_idle = params->eee_mode & EEE_MODE_TIMER_MASK; 2836 } else { 2837 /* hsi value in eee_mode --> time */ 2838 if (bnx2x_eee_nvram_to_time(params->eee_mode & 2839 EEE_MODE_NVRAM_MASK, 2840 &eee_idle)) 2841 return 0; 2842 } 2843 } else { 2844 /* hsi values in nvram --> time*/ 2845 eee_mode = ((REG_RD(bp, params->shmem_base + 2846 offsetof(struct shmem_region, dev_info. 2847 port_feature_config[params->port]. 2848 eee_power_mode)) & 2849 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >> 2850 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT); 2851 2852 if (bnx2x_eee_nvram_to_time(eee_mode, &eee_idle)) 2853 return 0; 2854 } 2855 2856 return eee_idle; 2857 } 2858 2859 static int bnx2x_eee_set_timers(struct link_params *params, 2860 struct link_vars *vars) 2861 { 2862 u32 eee_idle = 0, eee_mode; 2863 struct bnx2x *bp = params->bp; 2864 2865 eee_idle = bnx2x_eee_calc_timer(params); 2866 2867 if (eee_idle) { 2868 REG_WR(bp, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2), 2869 eee_idle); 2870 } else if ((params->eee_mode & EEE_MODE_ENABLE_LPI) && 2871 (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) && 2872 (params->eee_mode & EEE_MODE_OUTPUT_TIME)) { 2873 DP(NETIF_MSG_LINK, "Error: Tx LPI is enabled with timer 0\n"); 2874 return -EINVAL; 2875 } 2876 2877 vars->eee_status &= ~(SHMEM_EEE_TIMER_MASK | SHMEM_EEE_TIME_OUTPUT_BIT); 2878 if (params->eee_mode & EEE_MODE_OUTPUT_TIME) { 2879 /* eee_idle in 1u --> eee_status in 16u */ 2880 eee_idle >>= 4; 2881 vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) | 2882 SHMEM_EEE_TIME_OUTPUT_BIT; 2883 } else { 2884 if (bnx2x_eee_time_to_nvram(eee_idle, &eee_mode)) 2885 return -EINVAL; 2886 vars->eee_status |= eee_mode; 2887 } 2888 2889 return 0; 2890 } 2891 2892 static int bnx2x_eee_initial_config(struct link_params *params, 2893 struct link_vars *vars, u8 mode) 2894 { 2895 vars->eee_status |= ((u32) mode) << SHMEM_EEE_SUPPORTED_SHIFT; 2896 2897 /* Propogate params' bits --> vars (for migration exposure) */ 2898 if (params->eee_mode & EEE_MODE_ENABLE_LPI) 2899 vars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT; 2900 else 2901 vars->eee_status &= ~SHMEM_EEE_LPI_REQUESTED_BIT; 2902 2903 if (params->eee_mode & EEE_MODE_ADV_LPI) 2904 vars->eee_status |= SHMEM_EEE_REQUESTED_BIT; 2905 else 2906 vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT; 2907 2908 return bnx2x_eee_set_timers(params, vars); 2909 } 2910 2911 static int bnx2x_eee_disable(struct bnx2x_phy *phy, 2912 struct link_params *params, 2913 struct link_vars *vars) 2914 { 2915 struct bnx2x *bp = params->bp; 2916 2917 /* Make Certain LPI is disabled */ 2918 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0); 2919 2920 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0); 2921 2922 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK; 2923 2924 return 0; 2925 } 2926 2927 static int bnx2x_eee_advertise(struct bnx2x_phy *phy, 2928 struct link_params *params, 2929 struct link_vars *vars, u8 modes) 2930 { 2931 struct bnx2x *bp = params->bp; 2932 u16 val = 0; 2933 2934 /* Mask events preventing LPI generation */ 2935 REG_WR(bp, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20); 2936 2937 if (modes & SHMEM_EEE_10G_ADV) { 2938 DP(NETIF_MSG_LINK, "Advertise 10GBase-T EEE\n"); 2939 val |= 0x8; 2940 } 2941 if (modes & SHMEM_EEE_1G_ADV) { 2942 DP(NETIF_MSG_LINK, "Advertise 1GBase-T EEE\n"); 2943 val |= 0x4; 2944 } 2945 2946 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val); 2947 2948 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK; 2949 vars->eee_status |= (modes << SHMEM_EEE_ADV_STATUS_SHIFT); 2950 2951 return 0; 2952 } 2953 2954 static void bnx2x_update_mng_eee(struct link_params *params, u32 eee_status) 2955 { 2956 struct bnx2x *bp = params->bp; 2957 2958 if (bnx2x_eee_has_cap(params)) 2959 REG_WR(bp, params->shmem2_base + 2960 offsetof(struct shmem2_region, 2961 eee_status[params->port]), eee_status); 2962 } 2963 2964 static void bnx2x_eee_an_resolve(struct bnx2x_phy *phy, 2965 struct link_params *params, 2966 struct link_vars *vars) 2967 { 2968 struct bnx2x *bp = params->bp; 2969 u16 adv = 0, lp = 0; 2970 u32 lp_adv = 0; 2971 u8 neg = 0; 2972 2973 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv); 2974 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp); 2975 2976 if (lp & 0x2) { 2977 lp_adv |= SHMEM_EEE_100M_ADV; 2978 if (adv & 0x2) { 2979 if (vars->line_speed == SPEED_100) 2980 neg = 1; 2981 DP(NETIF_MSG_LINK, "EEE negotiated - 100M\n"); 2982 } 2983 } 2984 if (lp & 0x14) { 2985 lp_adv |= SHMEM_EEE_1G_ADV; 2986 if (adv & 0x14) { 2987 if (vars->line_speed == SPEED_1000) 2988 neg = 1; 2989 DP(NETIF_MSG_LINK, "EEE negotiated - 1G\n"); 2990 } 2991 } 2992 if (lp & 0x68) { 2993 lp_adv |= SHMEM_EEE_10G_ADV; 2994 if (adv & 0x68) { 2995 if (vars->line_speed == SPEED_10000) 2996 neg = 1; 2997 DP(NETIF_MSG_LINK, "EEE negotiated - 10G\n"); 2998 } 2999 } 3000 3001 vars->eee_status &= ~SHMEM_EEE_LP_ADV_STATUS_MASK; 3002 vars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT); 3003 3004 if (neg) { 3005 DP(NETIF_MSG_LINK, "EEE is active\n"); 3006 vars->eee_status |= SHMEM_EEE_ACTIVE_BIT; 3007 } 3008 3009 } 3010 3011 /******************************************************************/ 3012 /* BSC access functions from E3 */ 3013 /******************************************************************/ 3014 static void bnx2x_bsc_module_sel(struct link_params *params) 3015 { 3016 int idx; 3017 u32 board_cfg, sfp_ctrl; 3018 u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH]; 3019 struct bnx2x *bp = params->bp; 3020 u8 port = params->port; 3021 /* Read I2C output PINs */ 3022 board_cfg = REG_RD(bp, params->shmem_base + 3023 offsetof(struct shmem_region, 3024 dev_info.shared_hw_config.board)); 3025 i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK; 3026 i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >> 3027 SHARED_HW_CFG_E3_I2C_MUX1_SHIFT; 3028 3029 /* Read I2C output value */ 3030 sfp_ctrl = REG_RD(bp, params->shmem_base + 3031 offsetof(struct shmem_region, 3032 dev_info.port_hw_config[port].e3_cmn_pin_cfg)); 3033 i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0; 3034 i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0; 3035 DP(NETIF_MSG_LINK, "Setting BSC switch\n"); 3036 for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++) 3037 bnx2x_set_cfg_pin(bp, i2c_pins[idx], i2c_val[idx]); 3038 } 3039 3040 static int bnx2x_bsc_read(struct link_params *params, 3041 struct bnx2x_phy *phy, 3042 u8 sl_devid, 3043 u16 sl_addr, 3044 u8 lc_addr, 3045 u8 xfer_cnt, 3046 u32 *data_array) 3047 { 3048 u32 val, i; 3049 int rc = 0; 3050 struct bnx2x *bp = params->bp; 3051 3052 if ((sl_devid != 0xa0) && (sl_devid != 0xa2)) { 3053 DP(NETIF_MSG_LINK, "invalid sl_devid 0x%x\n", sl_devid); 3054 return -EINVAL; 3055 } 3056 3057 if (xfer_cnt > 16) { 3058 DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n", 3059 xfer_cnt); 3060 return -EINVAL; 3061 } 3062 bnx2x_bsc_module_sel(params); 3063 3064 xfer_cnt = 16 - lc_addr; 3065 3066 /* Enable the engine */ 3067 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); 3068 val |= MCPR_IMC_COMMAND_ENABLE; 3069 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); 3070 3071 /* Program slave device ID */ 3072 val = (sl_devid << 16) | sl_addr; 3073 REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val); 3074 3075 /* Start xfer with 0 byte to update the address pointer ???*/ 3076 val = (MCPR_IMC_COMMAND_ENABLE) | 3077 (MCPR_IMC_COMMAND_WRITE_OP << 3078 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) | 3079 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0); 3080 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); 3081 3082 /* Poll for completion */ 3083 i = 0; 3084 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); 3085 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) { 3086 udelay(10); 3087 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); 3088 if (i++ > 1000) { 3089 DP(NETIF_MSG_LINK, "wr 0 byte timed out after %d try\n", 3090 i); 3091 rc = -EFAULT; 3092 break; 3093 } 3094 } 3095 if (rc == -EFAULT) 3096 return rc; 3097 3098 /* Start xfer with read op */ 3099 val = (MCPR_IMC_COMMAND_ENABLE) | 3100 (MCPR_IMC_COMMAND_READ_OP << 3101 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) | 3102 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | 3103 (xfer_cnt); 3104 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); 3105 3106 /* Poll for completion */ 3107 i = 0; 3108 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); 3109 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) { 3110 udelay(10); 3111 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); 3112 if (i++ > 1000) { 3113 DP(NETIF_MSG_LINK, "rd op timed out after %d try\n", i); 3114 rc = -EFAULT; 3115 break; 3116 } 3117 } 3118 if (rc == -EFAULT) 3119 return rc; 3120 3121 for (i = (lc_addr >> 2); i < 4; i++) { 3122 data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4)); 3123 #ifdef __BIG_ENDIAN 3124 data_array[i] = ((data_array[i] & 0x000000ff) << 24) | 3125 ((data_array[i] & 0x0000ff00) << 8) | 3126 ((data_array[i] & 0x00ff0000) >> 8) | 3127 ((data_array[i] & 0xff000000) >> 24); 3128 #endif 3129 } 3130 return rc; 3131 } 3132 3133 static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy, 3134 u8 devad, u16 reg, u16 or_val) 3135 { 3136 u16 val; 3137 bnx2x_cl45_read(bp, phy, devad, reg, &val); 3138 bnx2x_cl45_write(bp, phy, devad, reg, val | or_val); 3139 } 3140 3141 int bnx2x_phy_read(struct link_params *params, u8 phy_addr, 3142 u8 devad, u16 reg, u16 *ret_val) 3143 { 3144 u8 phy_index; 3145 /* Probe for the phy according to the given phy_addr, and execute 3146 * the read request on it 3147 */ 3148 for (phy_index = 0; phy_index < params->num_phys; phy_index++) { 3149 if (params->phy[phy_index].addr == phy_addr) { 3150 return bnx2x_cl45_read(params->bp, 3151 ¶ms->phy[phy_index], devad, 3152 reg, ret_val); 3153 } 3154 } 3155 return -EINVAL; 3156 } 3157 3158 int bnx2x_phy_write(struct link_params *params, u8 phy_addr, 3159 u8 devad, u16 reg, u16 val) 3160 { 3161 u8 phy_index; 3162 /* Probe for the phy according to the given phy_addr, and execute 3163 * the write request on it 3164 */ 3165 for (phy_index = 0; phy_index < params->num_phys; phy_index++) { 3166 if (params->phy[phy_index].addr == phy_addr) { 3167 return bnx2x_cl45_write(params->bp, 3168 ¶ms->phy[phy_index], devad, 3169 reg, val); 3170 } 3171 } 3172 return -EINVAL; 3173 } 3174 static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy, 3175 struct link_params *params) 3176 { 3177 u8 lane = 0; 3178 struct bnx2x *bp = params->bp; 3179 u32 path_swap, path_swap_ovr; 3180 u8 path, port; 3181 3182 path = BP_PATH(bp); 3183 port = params->port; 3184 3185 if (bnx2x_is_4_port_mode(bp)) { 3186 u32 port_swap, port_swap_ovr; 3187 3188 /* Figure out path swap value */ 3189 path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR); 3190 if (path_swap_ovr & 0x1) 3191 path_swap = (path_swap_ovr & 0x2); 3192 else 3193 path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP); 3194 3195 if (path_swap) 3196 path = path ^ 1; 3197 3198 /* Figure out port swap value */ 3199 port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR); 3200 if (port_swap_ovr & 0x1) 3201 port_swap = (port_swap_ovr & 0x2); 3202 else 3203 port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP); 3204 3205 if (port_swap) 3206 port = port ^ 1; 3207 3208 lane = (port<<1) + path; 3209 } else { /* Two port mode - no port swap */ 3210 3211 /* Figure out path swap value */ 3212 path_swap_ovr = 3213 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR); 3214 if (path_swap_ovr & 0x1) { 3215 path_swap = (path_swap_ovr & 0x2); 3216 } else { 3217 path_swap = 3218 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP); 3219 } 3220 if (path_swap) 3221 path = path ^ 1; 3222 3223 lane = path << 1 ; 3224 } 3225 return lane; 3226 } 3227 3228 static void bnx2x_set_aer_mmd(struct link_params *params, 3229 struct bnx2x_phy *phy) 3230 { 3231 u32 ser_lane; 3232 u16 offset, aer_val; 3233 struct bnx2x *bp = params->bp; 3234 ser_lane = ((params->lane_config & 3235 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> 3236 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); 3237 3238 offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ? 3239 (phy->addr + ser_lane) : 0; 3240 3241 if (USES_WARPCORE(bp)) { 3242 aer_val = bnx2x_get_warpcore_lane(phy, params); 3243 /* In Dual-lane mode, two lanes are joined together, 3244 * so in order to configure them, the AER broadcast method is 3245 * used here. 3246 * 0x200 is the broadcast address for lanes 0,1 3247 * 0x201 is the broadcast address for lanes 2,3 3248 */ 3249 if (phy->flags & FLAGS_WC_DUAL_MODE) 3250 aer_val = (aer_val >> 1) | 0x200; 3251 } else if (CHIP_IS_E2(bp)) 3252 aer_val = 0x3800 + offset - 1; 3253 else 3254 aer_val = 0x3800 + offset; 3255 3256 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 3257 MDIO_AER_BLOCK_AER_REG, aer_val); 3258 3259 } 3260 3261 /******************************************************************/ 3262 /* Internal phy section */ 3263 /******************************************************************/ 3264 3265 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port) 3266 { 3267 u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 3268 3269 /* Set Clause 22 */ 3270 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1); 3271 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000); 3272 udelay(500); 3273 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f); 3274 udelay(500); 3275 /* Set Clause 45 */ 3276 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0); 3277 } 3278 3279 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port) 3280 { 3281 u32 val; 3282 3283 DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n"); 3284 3285 val = SERDES_RESET_BITS << (port*16); 3286 3287 /* Reset and unreset the SerDes/XGXS */ 3288 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); 3289 udelay(500); 3290 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); 3291 3292 bnx2x_set_serdes_access(bp, port); 3293 3294 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10, 3295 DEFAULT_PHY_DEV_ADDR); 3296 } 3297 3298 static void bnx2x_xgxs_deassert(struct link_params *params) 3299 { 3300 struct bnx2x *bp = params->bp; 3301 u8 port; 3302 u32 val; 3303 DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n"); 3304 port = params->port; 3305 3306 val = XGXS_RESET_BITS << (port*16); 3307 3308 /* Reset and unreset the SerDes/XGXS */ 3309 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); 3310 udelay(500); 3311 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); 3312 3313 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + port*0x18, 0); 3314 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 3315 params->phy[INT_PHY].def_md_devad); 3316 } 3317 3318 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy, 3319 struct link_params *params, u16 *ieee_fc) 3320 { 3321 struct bnx2x *bp = params->bp; 3322 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX; 3323 /* Resolve pause mode and advertisement Please refer to Table 3324 * 28B-3 of the 802.3ab-1999 spec 3325 */ 3326 3327 switch (phy->req_flow_ctrl) { 3328 case BNX2X_FLOW_CTRL_AUTO: 3329 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH) 3330 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; 3331 else 3332 *ieee_fc |= 3333 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; 3334 break; 3335 3336 case BNX2X_FLOW_CTRL_TX: 3337 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; 3338 break; 3339 3340 case BNX2X_FLOW_CTRL_RX: 3341 case BNX2X_FLOW_CTRL_BOTH: 3342 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; 3343 break; 3344 3345 case BNX2X_FLOW_CTRL_NONE: 3346 default: 3347 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE; 3348 break; 3349 } 3350 DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc); 3351 } 3352 3353 static void set_phy_vars(struct link_params *params, 3354 struct link_vars *vars) 3355 { 3356 struct bnx2x *bp = params->bp; 3357 u8 actual_phy_idx, phy_index, link_cfg_idx; 3358 u8 phy_config_swapped = params->multi_phy_config & 3359 PORT_HW_CFG_PHY_SWAPPED_ENABLED; 3360 for (phy_index = INT_PHY; phy_index < params->num_phys; 3361 phy_index++) { 3362 link_cfg_idx = LINK_CONFIG_IDX(phy_index); 3363 actual_phy_idx = phy_index; 3364 if (phy_config_swapped) { 3365 if (phy_index == EXT_PHY1) 3366 actual_phy_idx = EXT_PHY2; 3367 else if (phy_index == EXT_PHY2) 3368 actual_phy_idx = EXT_PHY1; 3369 } 3370 params->phy[actual_phy_idx].req_flow_ctrl = 3371 params->req_flow_ctrl[link_cfg_idx]; 3372 3373 params->phy[actual_phy_idx].req_line_speed = 3374 params->req_line_speed[link_cfg_idx]; 3375 3376 params->phy[actual_phy_idx].speed_cap_mask = 3377 params->speed_cap_mask[link_cfg_idx]; 3378 3379 params->phy[actual_phy_idx].req_duplex = 3380 params->req_duplex[link_cfg_idx]; 3381 3382 if (params->req_line_speed[link_cfg_idx] == 3383 SPEED_AUTO_NEG) 3384 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED; 3385 3386 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x," 3387 " speed_cap_mask %x\n", 3388 params->phy[actual_phy_idx].req_flow_ctrl, 3389 params->phy[actual_phy_idx].req_line_speed, 3390 params->phy[actual_phy_idx].speed_cap_mask); 3391 } 3392 } 3393 3394 static void bnx2x_ext_phy_set_pause(struct link_params *params, 3395 struct bnx2x_phy *phy, 3396 struct link_vars *vars) 3397 { 3398 u16 val; 3399 struct bnx2x *bp = params->bp; 3400 /* Read modify write pause advertizing */ 3401 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val); 3402 3403 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH; 3404 3405 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ 3406 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); 3407 if ((vars->ieee_fc & 3408 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == 3409 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) { 3410 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC; 3411 } 3412 if ((vars->ieee_fc & 3413 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == 3414 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) { 3415 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE; 3416 } 3417 DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val); 3418 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val); 3419 } 3420 3421 static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result) 3422 { /* LD LP */ 3423 switch (pause_result) { /* ASYM P ASYM P */ 3424 case 0xb: /* 1 0 1 1 */ 3425 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX; 3426 break; 3427 3428 case 0xe: /* 1 1 1 0 */ 3429 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX; 3430 break; 3431 3432 case 0x5: /* 0 1 0 1 */ 3433 case 0x7: /* 0 1 1 1 */ 3434 case 0xd: /* 1 1 0 1 */ 3435 case 0xf: /* 1 1 1 1 */ 3436 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH; 3437 break; 3438 3439 default: 3440 break; 3441 } 3442 if (pause_result & (1<<0)) 3443 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE; 3444 if (pause_result & (1<<1)) 3445 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE; 3446 3447 } 3448 3449 static void bnx2x_ext_phy_update_adv_fc(struct bnx2x_phy *phy, 3450 struct link_params *params, 3451 struct link_vars *vars) 3452 { 3453 u16 ld_pause; /* local */ 3454 u16 lp_pause; /* link partner */ 3455 u16 pause_result; 3456 struct bnx2x *bp = params->bp; 3457 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) { 3458 bnx2x_cl22_read(bp, phy, 0x4, &ld_pause); 3459 bnx2x_cl22_read(bp, phy, 0x5, &lp_pause); 3460 } else if (CHIP_IS_E3(bp) && 3461 SINGLE_MEDIA_DIRECT(params)) { 3462 u8 lane = bnx2x_get_warpcore_lane(phy, params); 3463 u16 gp_status, gp_mask; 3464 bnx2x_cl45_read(bp, phy, 3465 MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4, 3466 &gp_status); 3467 gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL | 3468 MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) << 3469 lane; 3470 if ((gp_status & gp_mask) == gp_mask) { 3471 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 3472 MDIO_AN_REG_ADV_PAUSE, &ld_pause); 3473 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 3474 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause); 3475 } else { 3476 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 3477 MDIO_AN_REG_CL37_FC_LD, &ld_pause); 3478 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 3479 MDIO_AN_REG_CL37_FC_LP, &lp_pause); 3480 ld_pause = ((ld_pause & 3481 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) 3482 << 3); 3483 lp_pause = ((lp_pause & 3484 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) 3485 << 3); 3486 } 3487 } else { 3488 bnx2x_cl45_read(bp, phy, 3489 MDIO_AN_DEVAD, 3490 MDIO_AN_REG_ADV_PAUSE, &ld_pause); 3491 bnx2x_cl45_read(bp, phy, 3492 MDIO_AN_DEVAD, 3493 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause); 3494 } 3495 pause_result = (ld_pause & 3496 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8; 3497 pause_result |= (lp_pause & 3498 MDIO_AN_REG_ADV_PAUSE_MASK) >> 10; 3499 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n", pause_result); 3500 bnx2x_pause_resolve(vars, pause_result); 3501 3502 } 3503 3504 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy, 3505 struct link_params *params, 3506 struct link_vars *vars) 3507 { 3508 u8 ret = 0; 3509 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 3510 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) { 3511 /* Update the advertised flow-controled of LD/LP in AN */ 3512 if (phy->req_line_speed == SPEED_AUTO_NEG) 3513 bnx2x_ext_phy_update_adv_fc(phy, params, vars); 3514 /* But set the flow-control result as the requested one */ 3515 vars->flow_ctrl = phy->req_flow_ctrl; 3516 } else if (phy->req_line_speed != SPEED_AUTO_NEG) 3517 vars->flow_ctrl = params->req_fc_auto_adv; 3518 else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 3519 ret = 1; 3520 bnx2x_ext_phy_update_adv_fc(phy, params, vars); 3521 } 3522 return ret; 3523 } 3524 /******************************************************************/ 3525 /* Warpcore section */ 3526 /******************************************************************/ 3527 /* The init_internal_warpcore should mirror the xgxs, 3528 * i.e. reset the lane (if needed), set aer for the 3529 * init configuration, and set/clear SGMII flag. Internal 3530 * phy init is done purely in phy_init stage. 3531 */ 3532 3533 static void bnx2x_warpcore_set_lpi_passthrough(struct bnx2x_phy *phy, 3534 struct link_params *params) 3535 { 3536 struct bnx2x *bp = params->bp; 3537 3538 DP(NETIF_MSG_LINK, "Configure WC for LPI pass through\n"); 3539 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3540 MDIO_WC_REG_EEE_COMBO_CONTROL0, 0x7c); 3541 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3542 MDIO_WC_REG_DIGITAL4_MISC5, 0xc000); 3543 } 3544 3545 static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy, 3546 struct link_params *params, 3547 struct link_vars *vars) { 3548 u16 val16 = 0, lane, i; 3549 struct bnx2x *bp = params->bp; 3550 static struct bnx2x_reg_set reg_set[] = { 3551 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7}, 3552 {MDIO_AN_DEVAD, MDIO_WC_REG_PAR_DET_10G_CTRL, 0}, 3553 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, 0}, 3554 {MDIO_WC_DEVAD, MDIO_WC_REG_XGXSBLK1_LANECTRL0, 0xff}, 3555 {MDIO_WC_DEVAD, MDIO_WC_REG_XGXSBLK1_LANECTRL1, 0x5555}, 3556 {MDIO_PMA_DEVAD, MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0}, 3557 {MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415}, 3558 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190}, 3559 /* Disable Autoneg: re-enable it after adv is done. */ 3560 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0} 3561 }; 3562 DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n"); 3563 /* Set to default registers that may be overriden by 10G force */ 3564 for (i = 0; i < sizeof(reg_set)/sizeof(struct bnx2x_reg_set); i++) 3565 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, 3566 reg_set[i].val); 3567 3568 /* Check adding advertisement for 1G KX */ 3569 if (((vars->line_speed == SPEED_AUTO_NEG) && 3570 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || 3571 (vars->line_speed == SPEED_1000)) { 3572 u32 addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2; 3573 val16 |= (1<<5); 3574 3575 /* Enable CL37 1G Parallel Detect */ 3576 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, addr, 0x1); 3577 DP(NETIF_MSG_LINK, "Advertize 1G\n"); 3578 } 3579 if (((vars->line_speed == SPEED_AUTO_NEG) && 3580 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) || 3581 (vars->line_speed == SPEED_10000)) { 3582 /* Check adding advertisement for 10G KR */ 3583 val16 |= (1<<7); 3584 /* Enable 10G Parallel Detect */ 3585 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 3586 MDIO_WC_REG_PAR_DET_10G_CTRL, 1); 3587 3588 DP(NETIF_MSG_LINK, "Advertize 10G\n"); 3589 } 3590 3591 /* Set Transmit PMD settings */ 3592 lane = bnx2x_get_warpcore_lane(phy, params); 3593 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3594 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 3595 ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | 3596 (0x06 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | 3597 (0x09 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET))); 3598 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3599 MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL, 3600 0x03f0); 3601 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3602 MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL, 3603 0x03f0); 3604 3605 /* Advertised speeds */ 3606 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 3607 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, val16); 3608 3609 /* Advertised and set FEC (Forward Error Correction) */ 3610 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 3611 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2, 3612 (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY | 3613 MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ)); 3614 3615 /* Enable CL37 BAM */ 3616 if (REG_RD(bp, params->shmem_base + 3617 offsetof(struct shmem_region, dev_info. 3618 port_hw_config[params->port].default_cfg)) & 3619 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) { 3620 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3621 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, 3622 1); 3623 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n"); 3624 } 3625 3626 /* Advertise pause */ 3627 bnx2x_ext_phy_set_pause(params, phy, vars); 3628 /* Set KR Autoneg Work-Around flag for Warpcore version older than D108 3629 */ 3630 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3631 MDIO_WC_REG_UC_INFO_B1_VERSION, &val16); 3632 if (val16 < 0xd108) { 3633 DP(NETIF_MSG_LINK, "Enable AN KR work-around\n"); 3634 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY; 3635 } 3636 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3637 MDIO_WC_REG_DIGITAL5_MISC7, 0x100); 3638 3639 /* Over 1G - AN local device user page 1 */ 3640 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3641 MDIO_WC_REG_DIGITAL3_UP1, 0x1f); 3642 3643 /* Enable Autoneg */ 3644 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 3645 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200); 3646 3647 } 3648 3649 static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy, 3650 struct link_params *params, 3651 struct link_vars *vars) 3652 { 3653 struct bnx2x *bp = params->bp; 3654 u16 i; 3655 static struct bnx2x_reg_set reg_set[] = { 3656 /* Disable Autoneg */ 3657 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7}, 3658 {MDIO_AN_DEVAD, MDIO_WC_REG_PAR_DET_10G_CTRL, 0}, 3659 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, 3660 0x3f00}, 3661 {MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0}, 3662 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0}, 3663 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1}, 3664 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa}, 3665 /* Disable CL36 PCS Tx */ 3666 {MDIO_WC_DEVAD, MDIO_WC_REG_XGXSBLK1_LANECTRL0, 0x0}, 3667 /* Double Wide Single Data Rate @ pll rate */ 3668 {MDIO_WC_DEVAD, MDIO_WC_REG_XGXSBLK1_LANECTRL1, 0xFFFF}, 3669 /* Leave cl72 training enable, needed for KR */ 3670 {MDIO_PMA_DEVAD, 3671 MDIO_WC_REG_PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150, 3672 0x2} 3673 }; 3674 3675 for (i = 0; i < sizeof(reg_set)/sizeof(struct bnx2x_reg_set); i++) 3676 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, 3677 reg_set[i].val); 3678 3679 /* Leave CL72 enabled */ 3680 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3681 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, 3682 0x3800); 3683 3684 /* Set speed via PMA/PMD register */ 3685 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 3686 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040); 3687 3688 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 3689 MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB); 3690 3691 /* Enable encoded forced speed */ 3692 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3693 MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30); 3694 3695 /* Turn TX scramble payload only the 64/66 scrambler */ 3696 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3697 MDIO_WC_REG_TX66_CONTROL, 0x9); 3698 3699 /* Turn RX scramble payload only the 64/66 scrambler */ 3700 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3701 MDIO_WC_REG_RX66_CONTROL, 0xF9); 3702 3703 /* Set and clear loopback to cause a reset to 64/66 decoder */ 3704 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3705 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000); 3706 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3707 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0); 3708 3709 } 3710 3711 static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy, 3712 struct link_params *params, 3713 u8 is_xfi) 3714 { 3715 struct bnx2x *bp = params->bp; 3716 u16 misc1_val, tap_val, tx_driver_val, lane, val; 3717 /* Hold rxSeqStart */ 3718 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3719 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000); 3720 3721 /* Hold tx_fifo_reset */ 3722 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3723 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x1); 3724 3725 /* Disable CL73 AN */ 3726 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0); 3727 3728 /* Disable 100FX Enable and Auto-Detect */ 3729 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3730 MDIO_WC_REG_FX100_CTRL1, &val); 3731 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3732 MDIO_WC_REG_FX100_CTRL1, (val & 0xFFFA)); 3733 3734 /* Disable 100FX Idle detect */ 3735 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3736 MDIO_WC_REG_FX100_CTRL3, 0x0080); 3737 3738 /* Set Block address to Remote PHY & Clear forced_speed[5] */ 3739 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3740 MDIO_WC_REG_DIGITAL4_MISC3, &val); 3741 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3742 MDIO_WC_REG_DIGITAL4_MISC3, (val & 0xFF7F)); 3743 3744 /* Turn off auto-detect & fiber mode */ 3745 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3746 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &val); 3747 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3748 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 3749 (val & 0xFFEE)); 3750 3751 /* Set filter_force_link, disable_false_link and parallel_detect */ 3752 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3753 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val); 3754 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3755 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 3756 ((val | 0x0006) & 0xFFFE)); 3757 3758 /* Set XFI / SFI */ 3759 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3760 MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val); 3761 3762 misc1_val &= ~(0x1f); 3763 3764 if (is_xfi) { 3765 misc1_val |= 0x5; 3766 tap_val = ((0x08 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | 3767 (0x37 << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | 3768 (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET)); 3769 tx_driver_val = 3770 ((0x00 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | 3771 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | 3772 (0x03 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)); 3773 3774 } else { 3775 misc1_val |= 0x9; 3776 tap_val = ((0x0f << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | 3777 (0x2b << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | 3778 (0x02 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET)); 3779 tx_driver_val = 3780 ((0x03 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | 3781 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | 3782 (0x06 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)); 3783 } 3784 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3785 MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val); 3786 3787 /* Set Transmit PMD settings */ 3788 lane = bnx2x_get_warpcore_lane(phy, params); 3789 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3790 MDIO_WC_REG_TX_FIR_TAP, 3791 tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE); 3792 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3793 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 3794 tx_driver_val); 3795 3796 /* Enable fiber mode, enable and invert sig_det */ 3797 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3798 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0xd); 3799 3800 /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */ 3801 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 3802 MDIO_WC_REG_DIGITAL4_MISC3, 0x8080); 3803 3804 bnx2x_warpcore_set_lpi_passthrough(phy, params); 3805 3806 /* 10G XFI Full Duplex */ 3807 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3808 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100); 3809 3810 /* Release tx_fifo_reset */ 3811 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3812 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, &val); 3813 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3814 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, val & 0xFFFE); 3815 3816 /* Release rxSeqStart */ 3817 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3818 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, &val); 3819 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3820 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, (val & 0x7FFF)); 3821 } 3822 3823 static void bnx2x_warpcore_set_20G_KR2(struct bnx2x *bp, 3824 struct bnx2x_phy *phy) 3825 { 3826 DP(NETIF_MSG_LINK, "KR2 still not supported !!!\n"); 3827 } 3828 3829 static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp, 3830 struct bnx2x_phy *phy, 3831 u16 lane) 3832 { 3833 /* Rx0 anaRxControl1G */ 3834 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3835 MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90); 3836 3837 /* Rx2 anaRxControl1G */ 3838 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3839 MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90); 3840 3841 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3842 MDIO_WC_REG_RX66_SCW0, 0xE070); 3843 3844 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3845 MDIO_WC_REG_RX66_SCW1, 0xC0D0); 3846 3847 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3848 MDIO_WC_REG_RX66_SCW2, 0xA0B0); 3849 3850 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3851 MDIO_WC_REG_RX66_SCW3, 0x8090); 3852 3853 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3854 MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0); 3855 3856 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3857 MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0); 3858 3859 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3860 MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0); 3861 3862 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3863 MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0); 3864 3865 /* Serdes Digital Misc1 */ 3866 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3867 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008); 3868 3869 /* Serdes Digital4 Misc3 */ 3870 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3871 MDIO_WC_REG_DIGITAL4_MISC3, 0x8088); 3872 3873 /* Set Transmit PMD settings */ 3874 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3875 MDIO_WC_REG_TX_FIR_TAP, 3876 ((0x12 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | 3877 (0x2d << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | 3878 (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET) | 3879 MDIO_WC_REG_TX_FIR_TAP_ENABLE)); 3880 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3881 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 3882 ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | 3883 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | 3884 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET))); 3885 } 3886 3887 static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy, 3888 struct link_params *params, 3889 u8 fiber_mode, 3890 u8 always_autoneg) 3891 { 3892 struct bnx2x *bp = params->bp; 3893 u16 val16, digctrl_kx1, digctrl_kx2; 3894 3895 /* Clear XFI clock comp in non-10G single lane mode. */ 3896 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3897 MDIO_WC_REG_RX66_CONTROL, &val16); 3898 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3899 MDIO_WC_REG_RX66_CONTROL, val16 & ~(3<<13)); 3900 3901 bnx2x_warpcore_set_lpi_passthrough(phy, params); 3902 3903 if (always_autoneg || phy->req_line_speed == SPEED_AUTO_NEG) { 3904 /* SGMII Autoneg */ 3905 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3906 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); 3907 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3908 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 3909 val16 | 0x1000); 3910 DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n"); 3911 } else { 3912 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3913 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); 3914 val16 &= 0xcebf; 3915 switch (phy->req_line_speed) { 3916 case SPEED_10: 3917 break; 3918 case SPEED_100: 3919 val16 |= 0x2000; 3920 break; 3921 case SPEED_1000: 3922 val16 |= 0x0040; 3923 break; 3924 default: 3925 DP(NETIF_MSG_LINK, 3926 "Speed not supported: 0x%x\n", phy->req_line_speed); 3927 return; 3928 } 3929 3930 if (phy->req_duplex == DUPLEX_FULL) 3931 val16 |= 0x0100; 3932 3933 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3934 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16); 3935 3936 DP(NETIF_MSG_LINK, "set SGMII force speed %d\n", 3937 phy->req_line_speed); 3938 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3939 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); 3940 DP(NETIF_MSG_LINK, " (readback) %x\n", val16); 3941 } 3942 3943 /* SGMII Slave mode and disable signal detect */ 3944 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3945 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1); 3946 if (fiber_mode) 3947 digctrl_kx1 = 1; 3948 else 3949 digctrl_kx1 &= 0xff4a; 3950 3951 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3952 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 3953 digctrl_kx1); 3954 3955 /* Turn off parallel detect */ 3956 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3957 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2); 3958 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3959 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 3960 (digctrl_kx2 & ~(1<<2))); 3961 3962 /* Re-enable parallel detect */ 3963 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3964 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 3965 (digctrl_kx2 | (1<<2))); 3966 3967 /* Enable autodet */ 3968 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3969 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 3970 (digctrl_kx1 | 0x10)); 3971 } 3972 3973 static void bnx2x_warpcore_reset_lane(struct bnx2x *bp, 3974 struct bnx2x_phy *phy, 3975 u8 reset) 3976 { 3977 u16 val; 3978 /* Take lane out of reset after configuration is finished */ 3979 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3980 MDIO_WC_REG_DIGITAL5_MISC6, &val); 3981 if (reset) 3982 val |= 0xC000; 3983 else 3984 val &= 0x3FFF; 3985 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3986 MDIO_WC_REG_DIGITAL5_MISC6, val); 3987 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3988 MDIO_WC_REG_DIGITAL5_MISC6, &val); 3989 } 3990 /* Clear SFI/XFI link settings registers */ 3991 static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy, 3992 struct link_params *params, 3993 u16 lane) 3994 { 3995 struct bnx2x *bp = params->bp; 3996 u16 i; 3997 static struct bnx2x_reg_set wc_regs[] = { 3998 {MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0}, 3999 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL1, 0x014a}, 4000 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800}, 4001 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008}, 4002 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 4003 0x0195}, 4004 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 4005 0x0007}, 4006 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 4007 0x0002}, 4008 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000}, 4009 {MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000}, 4010 {MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040}, 4011 {MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140} 4012 }; 4013 /* Set XFI clock comp as default. */ 4014 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4015 MDIO_WC_REG_RX66_CONTROL, (3<<13)); 4016 4017 for (i = 0; i < sizeof(wc_regs)/sizeof(struct bnx2x_reg_set); i++) 4018 bnx2x_cl45_write(bp, phy, wc_regs[i].devad, wc_regs[i].reg, 4019 wc_regs[i].val); 4020 4021 lane = bnx2x_get_warpcore_lane(phy, params); 4022 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4023 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990); 4024 4025 } 4026 4027 static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp, 4028 u32 chip_id, 4029 u32 shmem_base, u8 port, 4030 u8 *gpio_num, u8 *gpio_port) 4031 { 4032 u32 cfg_pin; 4033 *gpio_num = 0; 4034 *gpio_port = 0; 4035 if (CHIP_IS_E3(bp)) { 4036 cfg_pin = (REG_RD(bp, shmem_base + 4037 offsetof(struct shmem_region, 4038 dev_info.port_hw_config[port].e3_sfp_ctrl)) & 4039 PORT_HW_CFG_E3_MOD_ABS_MASK) >> 4040 PORT_HW_CFG_E3_MOD_ABS_SHIFT; 4041 4042 /* Should not happen. This function called upon interrupt 4043 * triggered by GPIO ( since EPIO can only generate interrupts 4044 * to MCP). 4045 * So if this function was called and none of the GPIOs was set, 4046 * it means the shit hit the fan. 4047 */ 4048 if ((cfg_pin < PIN_CFG_GPIO0_P0) || 4049 (cfg_pin > PIN_CFG_GPIO3_P1)) { 4050 DP(NETIF_MSG_LINK, 4051 "ERROR: Invalid cfg pin %x for module detect indication\n", 4052 cfg_pin); 4053 return -EINVAL; 4054 } 4055 4056 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3; 4057 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2; 4058 } else { 4059 *gpio_num = MISC_REGISTERS_GPIO_3; 4060 *gpio_port = port; 4061 } 4062 DP(NETIF_MSG_LINK, "MOD_ABS int GPIO%d_P%d\n", *gpio_num, *gpio_port); 4063 return 0; 4064 } 4065 4066 static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy, 4067 struct link_params *params) 4068 { 4069 struct bnx2x *bp = params->bp; 4070 u8 gpio_num, gpio_port; 4071 u32 gpio_val; 4072 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, 4073 params->shmem_base, params->port, 4074 &gpio_num, &gpio_port) != 0) 4075 return 0; 4076 gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port); 4077 4078 /* Call the handling function in case module is detected */ 4079 if (gpio_val == 0) 4080 return 1; 4081 else 4082 return 0; 4083 } 4084 static int bnx2x_warpcore_get_sigdet(struct bnx2x_phy *phy, 4085 struct link_params *params) 4086 { 4087 u16 gp2_status_reg0, lane; 4088 struct bnx2x *bp = params->bp; 4089 4090 lane = bnx2x_get_warpcore_lane(phy, params); 4091 4092 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0, 4093 &gp2_status_reg0); 4094 4095 return (gp2_status_reg0 >> (8+lane)) & 0x1; 4096 } 4097 4098 static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy, 4099 struct link_params *params, 4100 struct link_vars *vars) 4101 { 4102 struct bnx2x *bp = params->bp; 4103 u32 serdes_net_if; 4104 u16 gp_status1 = 0, lnkup = 0, lnkup_kr = 0; 4105 u16 lane = bnx2x_get_warpcore_lane(phy, params); 4106 4107 vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1; 4108 4109 if (!vars->turn_to_run_wc_rt) 4110 return; 4111 4112 /* Return if there is no link partner */ 4113 if (!(bnx2x_warpcore_get_sigdet(phy, params))) { 4114 DP(NETIF_MSG_LINK, "bnx2x_warpcore_get_sigdet false\n"); 4115 return; 4116 } 4117 4118 if (vars->rx_tx_asic_rst) { 4119 serdes_net_if = (REG_RD(bp, params->shmem_base + 4120 offsetof(struct shmem_region, dev_info. 4121 port_hw_config[params->port].default_cfg)) & 4122 PORT_HW_CFG_NET_SERDES_IF_MASK); 4123 4124 switch (serdes_net_if) { 4125 case PORT_HW_CFG_NET_SERDES_IF_KR: 4126 /* Do we get link yet? */ 4127 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 0x81d1, 4128 &gp_status1); 4129 lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */ 4130 /*10G KR*/ 4131 lnkup_kr = (gp_status1 >> (12+lane)) & 0x1; 4132 4133 DP(NETIF_MSG_LINK, 4134 "gp_status1 0x%x\n", gp_status1); 4135 4136 if (lnkup_kr || lnkup) { 4137 vars->rx_tx_asic_rst = 0; 4138 DP(NETIF_MSG_LINK, 4139 "link up, rx_tx_asic_rst 0x%x\n", 4140 vars->rx_tx_asic_rst); 4141 } else { 4142 /* Reset the lane to see if link comes up.*/ 4143 bnx2x_warpcore_reset_lane(bp, phy, 1); 4144 bnx2x_warpcore_reset_lane(bp, phy, 0); 4145 4146 /* Restart Autoneg */ 4147 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 4148 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200); 4149 4150 vars->rx_tx_asic_rst--; 4151 DP(NETIF_MSG_LINK, "0x%x retry left\n", 4152 vars->rx_tx_asic_rst); 4153 } 4154 break; 4155 4156 default: 4157 break; 4158 } 4159 4160 } /*params->rx_tx_asic_rst*/ 4161 4162 } 4163 static void bnx2x_warpcore_config_sfi(struct bnx2x_phy *phy, 4164 struct link_params *params) 4165 { 4166 u16 lane = bnx2x_get_warpcore_lane(phy, params); 4167 struct bnx2x *bp = params->bp; 4168 bnx2x_warpcore_clear_regs(phy, params, lane); 4169 if ((params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)] == 4170 SPEED_10000) && 4171 (phy->media_type != ETH_PHY_SFP_1G_FIBER)) { 4172 DP(NETIF_MSG_LINK, "Setting 10G SFI\n"); 4173 bnx2x_warpcore_set_10G_XFI(phy, params, 0); 4174 } else { 4175 DP(NETIF_MSG_LINK, "Setting 1G Fiber\n"); 4176 bnx2x_warpcore_set_sgmii_speed(phy, params, 1, 0); 4177 } 4178 } 4179 4180 static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy, 4181 struct link_params *params, 4182 struct link_vars *vars) 4183 { 4184 struct bnx2x *bp = params->bp; 4185 u32 serdes_net_if; 4186 u8 fiber_mode; 4187 u16 lane = bnx2x_get_warpcore_lane(phy, params); 4188 serdes_net_if = (REG_RD(bp, params->shmem_base + 4189 offsetof(struct shmem_region, dev_info. 4190 port_hw_config[params->port].default_cfg)) & 4191 PORT_HW_CFG_NET_SERDES_IF_MASK); 4192 DP(NETIF_MSG_LINK, "Begin Warpcore init, link_speed %d, " 4193 "serdes_net_if = 0x%x\n", 4194 vars->line_speed, serdes_net_if); 4195 bnx2x_set_aer_mmd(params, phy); 4196 bnx2x_warpcore_reset_lane(bp, phy, 1); 4197 vars->phy_flags |= PHY_XGXS_FLAG; 4198 if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) || 4199 (phy->req_line_speed && 4200 ((phy->req_line_speed == SPEED_100) || 4201 (phy->req_line_speed == SPEED_10)))) { 4202 vars->phy_flags |= PHY_SGMII_FLAG; 4203 DP(NETIF_MSG_LINK, "Setting SGMII mode\n"); 4204 bnx2x_warpcore_clear_regs(phy, params, lane); 4205 bnx2x_warpcore_set_sgmii_speed(phy, params, 0, 1); 4206 } else { 4207 switch (serdes_net_if) { 4208 case PORT_HW_CFG_NET_SERDES_IF_KR: 4209 /* Enable KR Auto Neg */ 4210 if (params->loopback_mode != LOOPBACK_EXT) 4211 bnx2x_warpcore_enable_AN_KR(phy, params, vars); 4212 else { 4213 DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n"); 4214 bnx2x_warpcore_set_10G_KR(phy, params, vars); 4215 } 4216 break; 4217 4218 case PORT_HW_CFG_NET_SERDES_IF_XFI: 4219 bnx2x_warpcore_clear_regs(phy, params, lane); 4220 if (vars->line_speed == SPEED_10000) { 4221 DP(NETIF_MSG_LINK, "Setting 10G XFI\n"); 4222 bnx2x_warpcore_set_10G_XFI(phy, params, 1); 4223 } else { 4224 if (SINGLE_MEDIA_DIRECT(params)) { 4225 DP(NETIF_MSG_LINK, "1G Fiber\n"); 4226 fiber_mode = 1; 4227 } else { 4228 DP(NETIF_MSG_LINK, "10/100/1G SGMII\n"); 4229 fiber_mode = 0; 4230 } 4231 bnx2x_warpcore_set_sgmii_speed(phy, 4232 params, 4233 fiber_mode, 4234 0); 4235 } 4236 4237 break; 4238 4239 case PORT_HW_CFG_NET_SERDES_IF_SFI: 4240 /* Issue Module detection */ 4241 if (bnx2x_is_sfp_module_plugged(phy, params)) 4242 bnx2x_sfp_module_detection(phy, params); 4243 4244 bnx2x_warpcore_config_sfi(phy, params); 4245 break; 4246 4247 case PORT_HW_CFG_NET_SERDES_IF_DXGXS: 4248 if (vars->line_speed != SPEED_20000) { 4249 DP(NETIF_MSG_LINK, "Speed not supported yet\n"); 4250 return; 4251 } 4252 DP(NETIF_MSG_LINK, "Setting 20G DXGXS\n"); 4253 bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane); 4254 /* Issue Module detection */ 4255 4256 bnx2x_sfp_module_detection(phy, params); 4257 break; 4258 4259 case PORT_HW_CFG_NET_SERDES_IF_KR2: 4260 if (vars->line_speed != SPEED_20000) { 4261 DP(NETIF_MSG_LINK, "Speed not supported yet\n"); 4262 return; 4263 } 4264 DP(NETIF_MSG_LINK, "Setting 20G KR2\n"); 4265 bnx2x_warpcore_set_20G_KR2(bp, phy); 4266 break; 4267 4268 default: 4269 DP(NETIF_MSG_LINK, 4270 "Unsupported Serdes Net Interface 0x%x\n", 4271 serdes_net_if); 4272 return; 4273 } 4274 } 4275 4276 /* Take lane out of reset after configuration is finished */ 4277 bnx2x_warpcore_reset_lane(bp, phy, 0); 4278 DP(NETIF_MSG_LINK, "Exit config init\n"); 4279 } 4280 4281 static void bnx2x_sfp_e3_set_transmitter(struct link_params *params, 4282 struct bnx2x_phy *phy, 4283 u8 tx_en) 4284 { 4285 struct bnx2x *bp = params->bp; 4286 u32 cfg_pin; 4287 u8 port = params->port; 4288 4289 cfg_pin = REG_RD(bp, params->shmem_base + 4290 offsetof(struct shmem_region, 4291 dev_info.port_hw_config[port].e3_sfp_ctrl)) & 4292 PORT_HW_CFG_TX_LASER_MASK; 4293 /* Set the !tx_en since this pin is DISABLE_TX_LASER */ 4294 DP(NETIF_MSG_LINK, "Setting WC TX to %d\n", tx_en); 4295 /* For 20G, the expected pin to be used is 3 pins after the current */ 4296 4297 bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1); 4298 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G) 4299 bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1); 4300 } 4301 4302 static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy, 4303 struct link_params *params) 4304 { 4305 struct bnx2x *bp = params->bp; 4306 u16 val16; 4307 bnx2x_sfp_e3_set_transmitter(params, phy, 0); 4308 bnx2x_set_mdio_clk(bp, params->chip_id, params->port); 4309 bnx2x_set_aer_mmd(params, phy); 4310 /* Global register */ 4311 bnx2x_warpcore_reset_lane(bp, phy, 1); 4312 4313 /* Clear loopback settings (if any) */ 4314 /* 10G & 20G */ 4315 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4316 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); 4317 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4318 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 & 4319 0xBFFF); 4320 4321 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4322 MDIO_WC_REG_IEEE0BLK_MIICNTL, &val16); 4323 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4324 MDIO_WC_REG_IEEE0BLK_MIICNTL, val16 & 0xfffe); 4325 4326 /* Update those 1-copy registers */ 4327 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 4328 MDIO_AER_BLOCK_AER_REG, 0); 4329 /* Enable 1G MDIO (1-copy) */ 4330 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4331 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, 4332 &val16); 4333 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4334 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, 4335 val16 & ~0x10); 4336 4337 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4338 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16); 4339 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4340 MDIO_WC_REG_XGXSBLK1_LANECTRL2, 4341 val16 & 0xff00); 4342 4343 } 4344 4345 static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy, 4346 struct link_params *params) 4347 { 4348 struct bnx2x *bp = params->bp; 4349 u16 val16; 4350 u32 lane; 4351 DP(NETIF_MSG_LINK, "Setting Warpcore loopback type %x, speed %d\n", 4352 params->loopback_mode, phy->req_line_speed); 4353 4354 if (phy->req_line_speed < SPEED_10000) { 4355 /* 10/100/1000 */ 4356 4357 /* Update those 1-copy registers */ 4358 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 4359 MDIO_AER_BLOCK_AER_REG, 0); 4360 /* Enable 1G MDIO (1-copy) */ 4361 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4362 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, 4363 0x10); 4364 /* Set 1G loopback based on lane (1-copy) */ 4365 lane = bnx2x_get_warpcore_lane(phy, params); 4366 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4367 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16); 4368 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4369 MDIO_WC_REG_XGXSBLK1_LANECTRL2, 4370 val16 | (1<<lane)); 4371 4372 /* Switch back to 4-copy registers */ 4373 bnx2x_set_aer_mmd(params, phy); 4374 } else { 4375 /* 10G & 20G */ 4376 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4377 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 4378 0x4000); 4379 4380 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, 4381 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1); 4382 } 4383 } 4384 4385 4386 4387 static void bnx2x_sync_link(struct link_params *params, 4388 struct link_vars *vars) 4389 { 4390 struct bnx2x *bp = params->bp; 4391 u8 link_10g_plus; 4392 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG) 4393 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG; 4394 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP); 4395 if (vars->link_up) { 4396 DP(NETIF_MSG_LINK, "phy link up\n"); 4397 4398 vars->phy_link_up = 1; 4399 vars->duplex = DUPLEX_FULL; 4400 switch (vars->link_status & 4401 LINK_STATUS_SPEED_AND_DUPLEX_MASK) { 4402 case LINK_10THD: 4403 vars->duplex = DUPLEX_HALF; 4404 /* Fall thru */ 4405 case LINK_10TFD: 4406 vars->line_speed = SPEED_10; 4407 break; 4408 4409 case LINK_100TXHD: 4410 vars->duplex = DUPLEX_HALF; 4411 /* Fall thru */ 4412 case LINK_100T4: 4413 case LINK_100TXFD: 4414 vars->line_speed = SPEED_100; 4415 break; 4416 4417 case LINK_1000THD: 4418 vars->duplex = DUPLEX_HALF; 4419 /* Fall thru */ 4420 case LINK_1000TFD: 4421 vars->line_speed = SPEED_1000; 4422 break; 4423 4424 case LINK_2500THD: 4425 vars->duplex = DUPLEX_HALF; 4426 /* Fall thru */ 4427 case LINK_2500TFD: 4428 vars->line_speed = SPEED_2500; 4429 break; 4430 4431 case LINK_10GTFD: 4432 vars->line_speed = SPEED_10000; 4433 break; 4434 case LINK_20GTFD: 4435 vars->line_speed = SPEED_20000; 4436 break; 4437 default: 4438 break; 4439 } 4440 vars->flow_ctrl = 0; 4441 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED) 4442 vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX; 4443 4444 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED) 4445 vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX; 4446 4447 if (!vars->flow_ctrl) 4448 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 4449 4450 if (vars->line_speed && 4451 ((vars->line_speed == SPEED_10) || 4452 (vars->line_speed == SPEED_100))) { 4453 vars->phy_flags |= PHY_SGMII_FLAG; 4454 } else { 4455 vars->phy_flags &= ~PHY_SGMII_FLAG; 4456 } 4457 if (vars->line_speed && 4458 USES_WARPCORE(bp) && 4459 (vars->line_speed == SPEED_1000)) 4460 vars->phy_flags |= PHY_SGMII_FLAG; 4461 /* Anything 10 and over uses the bmac */ 4462 link_10g_plus = (vars->line_speed >= SPEED_10000); 4463 4464 if (link_10g_plus) { 4465 if (USES_WARPCORE(bp)) 4466 vars->mac_type = MAC_TYPE_XMAC; 4467 else 4468 vars->mac_type = MAC_TYPE_BMAC; 4469 } else { 4470 if (USES_WARPCORE(bp)) 4471 vars->mac_type = MAC_TYPE_UMAC; 4472 else 4473 vars->mac_type = MAC_TYPE_EMAC; 4474 } 4475 } else { /* Link down */ 4476 DP(NETIF_MSG_LINK, "phy link down\n"); 4477 4478 vars->phy_link_up = 0; 4479 4480 vars->line_speed = 0; 4481 vars->duplex = DUPLEX_FULL; 4482 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 4483 4484 /* Indicate no mac active */ 4485 vars->mac_type = MAC_TYPE_NONE; 4486 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG) 4487 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; 4488 if (vars->link_status & LINK_STATUS_SFP_TX_FAULT) 4489 vars->phy_flags |= PHY_SFP_TX_FAULT_FLAG; 4490 } 4491 } 4492 4493 void bnx2x_link_status_update(struct link_params *params, 4494 struct link_vars *vars) 4495 { 4496 struct bnx2x *bp = params->bp; 4497 u8 port = params->port; 4498 u32 sync_offset, media_types; 4499 /* Update PHY configuration */ 4500 set_phy_vars(params, vars); 4501 4502 vars->link_status = REG_RD(bp, params->shmem_base + 4503 offsetof(struct shmem_region, 4504 port_mb[port].link_status)); 4505 if (bnx2x_eee_has_cap(params)) 4506 vars->eee_status = REG_RD(bp, params->shmem2_base + 4507 offsetof(struct shmem2_region, 4508 eee_status[params->port])); 4509 4510 vars->phy_flags = PHY_XGXS_FLAG; 4511 bnx2x_sync_link(params, vars); 4512 /* Sync media type */ 4513 sync_offset = params->shmem_base + 4514 offsetof(struct shmem_region, 4515 dev_info.port_hw_config[port].media_type); 4516 media_types = REG_RD(bp, sync_offset); 4517 4518 params->phy[INT_PHY].media_type = 4519 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >> 4520 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT; 4521 params->phy[EXT_PHY1].media_type = 4522 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >> 4523 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT; 4524 params->phy[EXT_PHY2].media_type = 4525 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >> 4526 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT; 4527 DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types); 4528 4529 /* Sync AEU offset */ 4530 sync_offset = params->shmem_base + 4531 offsetof(struct shmem_region, 4532 dev_info.port_hw_config[port].aeu_int_mask); 4533 4534 vars->aeu_int_mask = REG_RD(bp, sync_offset); 4535 4536 /* Sync PFC status */ 4537 if (vars->link_status & LINK_STATUS_PFC_ENABLED) 4538 params->feature_config_flags |= 4539 FEATURE_CONFIG_PFC_ENABLED; 4540 else 4541 params->feature_config_flags &= 4542 ~FEATURE_CONFIG_PFC_ENABLED; 4543 4544 DP(NETIF_MSG_LINK, "link_status 0x%x phy_link_up %x int_mask 0x%x\n", 4545 vars->link_status, vars->phy_link_up, vars->aeu_int_mask); 4546 DP(NETIF_MSG_LINK, "line_speed %x duplex %x flow_ctrl 0x%x\n", 4547 vars->line_speed, vars->duplex, vars->flow_ctrl); 4548 } 4549 4550 static void bnx2x_set_master_ln(struct link_params *params, 4551 struct bnx2x_phy *phy) 4552 { 4553 struct bnx2x *bp = params->bp; 4554 u16 new_master_ln, ser_lane; 4555 ser_lane = ((params->lane_config & 4556 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> 4557 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); 4558 4559 /* Set the master_ln for AN */ 4560 CL22_RD_OVER_CL45(bp, phy, 4561 MDIO_REG_BANK_XGXS_BLOCK2, 4562 MDIO_XGXS_BLOCK2_TEST_MODE_LANE, 4563 &new_master_ln); 4564 4565 CL22_WR_OVER_CL45(bp, phy, 4566 MDIO_REG_BANK_XGXS_BLOCK2 , 4567 MDIO_XGXS_BLOCK2_TEST_MODE_LANE, 4568 (new_master_ln | ser_lane)); 4569 } 4570 4571 static int bnx2x_reset_unicore(struct link_params *params, 4572 struct bnx2x_phy *phy, 4573 u8 set_serdes) 4574 { 4575 struct bnx2x *bp = params->bp; 4576 u16 mii_control; 4577 u16 i; 4578 CL22_RD_OVER_CL45(bp, phy, 4579 MDIO_REG_BANK_COMBO_IEEE0, 4580 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control); 4581 4582 /* Reset the unicore */ 4583 CL22_WR_OVER_CL45(bp, phy, 4584 MDIO_REG_BANK_COMBO_IEEE0, 4585 MDIO_COMBO_IEEE0_MII_CONTROL, 4586 (mii_control | 4587 MDIO_COMBO_IEEO_MII_CONTROL_RESET)); 4588 if (set_serdes) 4589 bnx2x_set_serdes_access(bp, params->port); 4590 4591 /* Wait for the reset to self clear */ 4592 for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) { 4593 udelay(5); 4594 4595 /* The reset erased the previous bank value */ 4596 CL22_RD_OVER_CL45(bp, phy, 4597 MDIO_REG_BANK_COMBO_IEEE0, 4598 MDIO_COMBO_IEEE0_MII_CONTROL, 4599 &mii_control); 4600 4601 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) { 4602 udelay(5); 4603 return 0; 4604 } 4605 } 4606 4607 netdev_err(bp->dev, "Warning: PHY was not initialized," 4608 " Port %d\n", 4609 params->port); 4610 DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n"); 4611 return -EINVAL; 4612 4613 } 4614 4615 static void bnx2x_set_swap_lanes(struct link_params *params, 4616 struct bnx2x_phy *phy) 4617 { 4618 struct bnx2x *bp = params->bp; 4619 /* Each two bits represents a lane number: 4620 * No swap is 0123 => 0x1b no need to enable the swap 4621 */ 4622 u16 rx_lane_swap, tx_lane_swap; 4623 4624 rx_lane_swap = ((params->lane_config & 4625 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >> 4626 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT); 4627 tx_lane_swap = ((params->lane_config & 4628 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >> 4629 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT); 4630 4631 if (rx_lane_swap != 0x1b) { 4632 CL22_WR_OVER_CL45(bp, phy, 4633 MDIO_REG_BANK_XGXS_BLOCK2, 4634 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 4635 (rx_lane_swap | 4636 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE | 4637 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE)); 4638 } else { 4639 CL22_WR_OVER_CL45(bp, phy, 4640 MDIO_REG_BANK_XGXS_BLOCK2, 4641 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0); 4642 } 4643 4644 if (tx_lane_swap != 0x1b) { 4645 CL22_WR_OVER_CL45(bp, phy, 4646 MDIO_REG_BANK_XGXS_BLOCK2, 4647 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 4648 (tx_lane_swap | 4649 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE)); 4650 } else { 4651 CL22_WR_OVER_CL45(bp, phy, 4652 MDIO_REG_BANK_XGXS_BLOCK2, 4653 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0); 4654 } 4655 } 4656 4657 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy, 4658 struct link_params *params) 4659 { 4660 struct bnx2x *bp = params->bp; 4661 u16 control2; 4662 CL22_RD_OVER_CL45(bp, phy, 4663 MDIO_REG_BANK_SERDES_DIGITAL, 4664 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, 4665 &control2); 4666 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) 4667 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN; 4668 else 4669 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN; 4670 DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n", 4671 phy->speed_cap_mask, control2); 4672 CL22_WR_OVER_CL45(bp, phy, 4673 MDIO_REG_BANK_SERDES_DIGITAL, 4674 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, 4675 control2); 4676 4677 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) && 4678 (phy->speed_cap_mask & 4679 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { 4680 DP(NETIF_MSG_LINK, "XGXS\n"); 4681 4682 CL22_WR_OVER_CL45(bp, phy, 4683 MDIO_REG_BANK_10G_PARALLEL_DETECT, 4684 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK, 4685 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT); 4686 4687 CL22_RD_OVER_CL45(bp, phy, 4688 MDIO_REG_BANK_10G_PARALLEL_DETECT, 4689 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL, 4690 &control2); 4691 4692 4693 control2 |= 4694 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN; 4695 4696 CL22_WR_OVER_CL45(bp, phy, 4697 MDIO_REG_BANK_10G_PARALLEL_DETECT, 4698 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL, 4699 control2); 4700 4701 /* Disable parallel detection of HiG */ 4702 CL22_WR_OVER_CL45(bp, phy, 4703 MDIO_REG_BANK_XGXS_BLOCK2, 4704 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G, 4705 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS | 4706 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS); 4707 } 4708 } 4709 4710 static void bnx2x_set_autoneg(struct bnx2x_phy *phy, 4711 struct link_params *params, 4712 struct link_vars *vars, 4713 u8 enable_cl73) 4714 { 4715 struct bnx2x *bp = params->bp; 4716 u16 reg_val; 4717 4718 /* CL37 Autoneg */ 4719 CL22_RD_OVER_CL45(bp, phy, 4720 MDIO_REG_BANK_COMBO_IEEE0, 4721 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val); 4722 4723 /* CL37 Autoneg Enabled */ 4724 if (vars->line_speed == SPEED_AUTO_NEG) 4725 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN; 4726 else /* CL37 Autoneg Disabled */ 4727 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | 4728 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN); 4729 4730 CL22_WR_OVER_CL45(bp, phy, 4731 MDIO_REG_BANK_COMBO_IEEE0, 4732 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val); 4733 4734 /* Enable/Disable Autodetection */ 4735 4736 CL22_RD_OVER_CL45(bp, phy, 4737 MDIO_REG_BANK_SERDES_DIGITAL, 4738 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val); 4739 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN | 4740 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT); 4741 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE; 4742 if (vars->line_speed == SPEED_AUTO_NEG) 4743 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; 4744 else 4745 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; 4746 4747 CL22_WR_OVER_CL45(bp, phy, 4748 MDIO_REG_BANK_SERDES_DIGITAL, 4749 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val); 4750 4751 /* Enable TetonII and BAM autoneg */ 4752 CL22_RD_OVER_CL45(bp, phy, 4753 MDIO_REG_BANK_BAM_NEXT_PAGE, 4754 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, 4755 ®_val); 4756 if (vars->line_speed == SPEED_AUTO_NEG) { 4757 /* Enable BAM aneg Mode and TetonII aneg Mode */ 4758 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE | 4759 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN); 4760 } else { 4761 /* TetonII and BAM Autoneg Disabled */ 4762 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE | 4763 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN); 4764 } 4765 CL22_WR_OVER_CL45(bp, phy, 4766 MDIO_REG_BANK_BAM_NEXT_PAGE, 4767 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, 4768 reg_val); 4769 4770 if (enable_cl73) { 4771 /* Enable Cl73 FSM status bits */ 4772 CL22_WR_OVER_CL45(bp, phy, 4773 MDIO_REG_BANK_CL73_USERB0, 4774 MDIO_CL73_USERB0_CL73_UCTRL, 4775 0xe); 4776 4777 /* Enable BAM Station Manager*/ 4778 CL22_WR_OVER_CL45(bp, phy, 4779 MDIO_REG_BANK_CL73_USERB0, 4780 MDIO_CL73_USERB0_CL73_BAM_CTRL1, 4781 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN | 4782 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN | 4783 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN); 4784 4785 /* Advertise CL73 link speeds */ 4786 CL22_RD_OVER_CL45(bp, phy, 4787 MDIO_REG_BANK_CL73_IEEEB1, 4788 MDIO_CL73_IEEEB1_AN_ADV2, 4789 ®_val); 4790 if (phy->speed_cap_mask & 4791 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 4792 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4; 4793 if (phy->speed_cap_mask & 4794 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) 4795 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX; 4796 4797 CL22_WR_OVER_CL45(bp, phy, 4798 MDIO_REG_BANK_CL73_IEEEB1, 4799 MDIO_CL73_IEEEB1_AN_ADV2, 4800 reg_val); 4801 4802 /* CL73 Autoneg Enabled */ 4803 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN; 4804 4805 } else /* CL73 Autoneg Disabled */ 4806 reg_val = 0; 4807 4808 CL22_WR_OVER_CL45(bp, phy, 4809 MDIO_REG_BANK_CL73_IEEEB0, 4810 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val); 4811 } 4812 4813 /* Program SerDes, forced speed */ 4814 static void bnx2x_program_serdes(struct bnx2x_phy *phy, 4815 struct link_params *params, 4816 struct link_vars *vars) 4817 { 4818 struct bnx2x *bp = params->bp; 4819 u16 reg_val; 4820 4821 /* Program duplex, disable autoneg and sgmii*/ 4822 CL22_RD_OVER_CL45(bp, phy, 4823 MDIO_REG_BANK_COMBO_IEEE0, 4824 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val); 4825 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX | 4826 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | 4827 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK); 4828 if (phy->req_duplex == DUPLEX_FULL) 4829 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX; 4830 CL22_WR_OVER_CL45(bp, phy, 4831 MDIO_REG_BANK_COMBO_IEEE0, 4832 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val); 4833 4834 /* Program speed 4835 * - needed only if the speed is greater than 1G (2.5G or 10G) 4836 */ 4837 CL22_RD_OVER_CL45(bp, phy, 4838 MDIO_REG_BANK_SERDES_DIGITAL, 4839 MDIO_SERDES_DIGITAL_MISC1, ®_val); 4840 /* Clearing the speed value before setting the right speed */ 4841 DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val); 4842 4843 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK | 4844 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL); 4845 4846 if (!((vars->line_speed == SPEED_1000) || 4847 (vars->line_speed == SPEED_100) || 4848 (vars->line_speed == SPEED_10))) { 4849 4850 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M | 4851 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL); 4852 if (vars->line_speed == SPEED_10000) 4853 reg_val |= 4854 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4; 4855 } 4856 4857 CL22_WR_OVER_CL45(bp, phy, 4858 MDIO_REG_BANK_SERDES_DIGITAL, 4859 MDIO_SERDES_DIGITAL_MISC1, reg_val); 4860 4861 } 4862 4863 static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy, 4864 struct link_params *params) 4865 { 4866 struct bnx2x *bp = params->bp; 4867 u16 val = 0; 4868 4869 /* Set extended capabilities */ 4870 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) 4871 val |= MDIO_OVER_1G_UP1_2_5G; 4872 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 4873 val |= MDIO_OVER_1G_UP1_10G; 4874 CL22_WR_OVER_CL45(bp, phy, 4875 MDIO_REG_BANK_OVER_1G, 4876 MDIO_OVER_1G_UP1, val); 4877 4878 CL22_WR_OVER_CL45(bp, phy, 4879 MDIO_REG_BANK_OVER_1G, 4880 MDIO_OVER_1G_UP3, 0x400); 4881 } 4882 4883 static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy, 4884 struct link_params *params, 4885 u16 ieee_fc) 4886 { 4887 struct bnx2x *bp = params->bp; 4888 u16 val; 4889 /* For AN, we are always publishing full duplex */ 4890 4891 CL22_WR_OVER_CL45(bp, phy, 4892 MDIO_REG_BANK_COMBO_IEEE0, 4893 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc); 4894 CL22_RD_OVER_CL45(bp, phy, 4895 MDIO_REG_BANK_CL73_IEEEB1, 4896 MDIO_CL73_IEEEB1_AN_ADV1, &val); 4897 val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH; 4898 val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK); 4899 CL22_WR_OVER_CL45(bp, phy, 4900 MDIO_REG_BANK_CL73_IEEEB1, 4901 MDIO_CL73_IEEEB1_AN_ADV1, val); 4902 } 4903 4904 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy, 4905 struct link_params *params, 4906 u8 enable_cl73) 4907 { 4908 struct bnx2x *bp = params->bp; 4909 u16 mii_control; 4910 4911 DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n"); 4912 /* Enable and restart BAM/CL37 aneg */ 4913 4914 if (enable_cl73) { 4915 CL22_RD_OVER_CL45(bp, phy, 4916 MDIO_REG_BANK_CL73_IEEEB0, 4917 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 4918 &mii_control); 4919 4920 CL22_WR_OVER_CL45(bp, phy, 4921 MDIO_REG_BANK_CL73_IEEEB0, 4922 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 4923 (mii_control | 4924 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN | 4925 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN)); 4926 } else { 4927 4928 CL22_RD_OVER_CL45(bp, phy, 4929 MDIO_REG_BANK_COMBO_IEEE0, 4930 MDIO_COMBO_IEEE0_MII_CONTROL, 4931 &mii_control); 4932 DP(NETIF_MSG_LINK, 4933 "bnx2x_restart_autoneg mii_control before = 0x%x\n", 4934 mii_control); 4935 CL22_WR_OVER_CL45(bp, phy, 4936 MDIO_REG_BANK_COMBO_IEEE0, 4937 MDIO_COMBO_IEEE0_MII_CONTROL, 4938 (mii_control | 4939 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | 4940 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN)); 4941 } 4942 } 4943 4944 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy, 4945 struct link_params *params, 4946 struct link_vars *vars) 4947 { 4948 struct bnx2x *bp = params->bp; 4949 u16 control1; 4950 4951 /* In SGMII mode, the unicore is always slave */ 4952 4953 CL22_RD_OVER_CL45(bp, phy, 4954 MDIO_REG_BANK_SERDES_DIGITAL, 4955 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, 4956 &control1); 4957 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT; 4958 /* Set sgmii mode (and not fiber) */ 4959 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE | 4960 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET | 4961 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE); 4962 CL22_WR_OVER_CL45(bp, phy, 4963 MDIO_REG_BANK_SERDES_DIGITAL, 4964 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, 4965 control1); 4966 4967 /* If forced speed */ 4968 if (!(vars->line_speed == SPEED_AUTO_NEG)) { 4969 /* Set speed, disable autoneg */ 4970 u16 mii_control; 4971 4972 CL22_RD_OVER_CL45(bp, phy, 4973 MDIO_REG_BANK_COMBO_IEEE0, 4974 MDIO_COMBO_IEEE0_MII_CONTROL, 4975 &mii_control); 4976 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | 4977 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK| 4978 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX); 4979 4980 switch (vars->line_speed) { 4981 case SPEED_100: 4982 mii_control |= 4983 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100; 4984 break; 4985 case SPEED_1000: 4986 mii_control |= 4987 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000; 4988 break; 4989 case SPEED_10: 4990 /* There is nothing to set for 10M */ 4991 break; 4992 default: 4993 /* Invalid speed for SGMII */ 4994 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", 4995 vars->line_speed); 4996 break; 4997 } 4998 4999 /* Setting the full duplex */ 5000 if (phy->req_duplex == DUPLEX_FULL) 5001 mii_control |= 5002 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX; 5003 CL22_WR_OVER_CL45(bp, phy, 5004 MDIO_REG_BANK_COMBO_IEEE0, 5005 MDIO_COMBO_IEEE0_MII_CONTROL, 5006 mii_control); 5007 5008 } else { /* AN mode */ 5009 /* Enable and restart AN */ 5010 bnx2x_restart_autoneg(phy, params, 0); 5011 } 5012 } 5013 5014 /* Link management 5015 */ 5016 static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy, 5017 struct link_params *params) 5018 { 5019 struct bnx2x *bp = params->bp; 5020 u16 pd_10g, status2_1000x; 5021 if (phy->req_line_speed != SPEED_AUTO_NEG) 5022 return 0; 5023 CL22_RD_OVER_CL45(bp, phy, 5024 MDIO_REG_BANK_SERDES_DIGITAL, 5025 MDIO_SERDES_DIGITAL_A_1000X_STATUS2, 5026 &status2_1000x); 5027 CL22_RD_OVER_CL45(bp, phy, 5028 MDIO_REG_BANK_SERDES_DIGITAL, 5029 MDIO_SERDES_DIGITAL_A_1000X_STATUS2, 5030 &status2_1000x); 5031 if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) { 5032 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n", 5033 params->port); 5034 return 1; 5035 } 5036 5037 CL22_RD_OVER_CL45(bp, phy, 5038 MDIO_REG_BANK_10G_PARALLEL_DETECT, 5039 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS, 5040 &pd_10g); 5041 5042 if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) { 5043 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n", 5044 params->port); 5045 return 1; 5046 } 5047 return 0; 5048 } 5049 5050 static void bnx2x_update_adv_fc(struct bnx2x_phy *phy, 5051 struct link_params *params, 5052 struct link_vars *vars, 5053 u32 gp_status) 5054 { 5055 u16 ld_pause; /* local driver */ 5056 u16 lp_pause; /* link partner */ 5057 u16 pause_result; 5058 struct bnx2x *bp = params->bp; 5059 if ((gp_status & 5060 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | 5061 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) == 5062 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | 5063 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) { 5064 5065 CL22_RD_OVER_CL45(bp, phy, 5066 MDIO_REG_BANK_CL73_IEEEB1, 5067 MDIO_CL73_IEEEB1_AN_ADV1, 5068 &ld_pause); 5069 CL22_RD_OVER_CL45(bp, phy, 5070 MDIO_REG_BANK_CL73_IEEEB1, 5071 MDIO_CL73_IEEEB1_AN_LP_ADV1, 5072 &lp_pause); 5073 pause_result = (ld_pause & 5074 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8; 5075 pause_result |= (lp_pause & 5076 MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10; 5077 DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n", pause_result); 5078 } else { 5079 CL22_RD_OVER_CL45(bp, phy, 5080 MDIO_REG_BANK_COMBO_IEEE0, 5081 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, 5082 &ld_pause); 5083 CL22_RD_OVER_CL45(bp, phy, 5084 MDIO_REG_BANK_COMBO_IEEE0, 5085 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1, 5086 &lp_pause); 5087 pause_result = (ld_pause & 5088 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5; 5089 pause_result |= (lp_pause & 5090 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7; 5091 DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n", pause_result); 5092 } 5093 bnx2x_pause_resolve(vars, pause_result); 5094 5095 } 5096 5097 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy, 5098 struct link_params *params, 5099 struct link_vars *vars, 5100 u32 gp_status) 5101 { 5102 struct bnx2x *bp = params->bp; 5103 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 5104 5105 /* Resolve from gp_status in case of AN complete and not sgmii */ 5106 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) { 5107 /* Update the advertised flow-controled of LD/LP in AN */ 5108 if (phy->req_line_speed == SPEED_AUTO_NEG) 5109 bnx2x_update_adv_fc(phy, params, vars, gp_status); 5110 /* But set the flow-control result as the requested one */ 5111 vars->flow_ctrl = phy->req_flow_ctrl; 5112 } else if (phy->req_line_speed != SPEED_AUTO_NEG) 5113 vars->flow_ctrl = params->req_fc_auto_adv; 5114 else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) && 5115 (!(vars->phy_flags & PHY_SGMII_FLAG))) { 5116 if (bnx2x_direct_parallel_detect_used(phy, params)) { 5117 vars->flow_ctrl = params->req_fc_auto_adv; 5118 return; 5119 } 5120 bnx2x_update_adv_fc(phy, params, vars, gp_status); 5121 } 5122 DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl); 5123 } 5124 5125 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy, 5126 struct link_params *params) 5127 { 5128 struct bnx2x *bp = params->bp; 5129 u16 rx_status, ustat_val, cl37_fsm_received; 5130 DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n"); 5131 /* Step 1: Make sure signal is detected */ 5132 CL22_RD_OVER_CL45(bp, phy, 5133 MDIO_REG_BANK_RX0, 5134 MDIO_RX0_RX_STATUS, 5135 &rx_status); 5136 if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) != 5137 (MDIO_RX0_RX_STATUS_SIGDET)) { 5138 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73." 5139 "rx_status(0x80b0) = 0x%x\n", rx_status); 5140 CL22_WR_OVER_CL45(bp, phy, 5141 MDIO_REG_BANK_CL73_IEEEB0, 5142 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 5143 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN); 5144 return; 5145 } 5146 /* Step 2: Check CL73 state machine */ 5147 CL22_RD_OVER_CL45(bp, phy, 5148 MDIO_REG_BANK_CL73_USERB0, 5149 MDIO_CL73_USERB0_CL73_USTAT1, 5150 &ustat_val); 5151 if ((ustat_val & 5152 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK | 5153 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) != 5154 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK | 5155 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) { 5156 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. " 5157 "ustat_val(0x8371) = 0x%x\n", ustat_val); 5158 return; 5159 } 5160 /* Step 3: Check CL37 Message Pages received to indicate LP 5161 * supports only CL37 5162 */ 5163 CL22_RD_OVER_CL45(bp, phy, 5164 MDIO_REG_BANK_REMOTE_PHY, 5165 MDIO_REMOTE_PHY_MISC_RX_STATUS, 5166 &cl37_fsm_received); 5167 if ((cl37_fsm_received & 5168 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG | 5169 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) != 5170 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG | 5171 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) { 5172 DP(NETIF_MSG_LINK, "No CL37 FSM were received. " 5173 "misc_rx_status(0x8330) = 0x%x\n", 5174 cl37_fsm_received); 5175 return; 5176 } 5177 /* The combined cl37/cl73 fsm state information indicating that 5178 * we are connected to a device which does not support cl73, but 5179 * does support cl37 BAM. In this case we disable cl73 and 5180 * restart cl37 auto-neg 5181 */ 5182 5183 /* Disable CL73 */ 5184 CL22_WR_OVER_CL45(bp, phy, 5185 MDIO_REG_BANK_CL73_IEEEB0, 5186 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 5187 0); 5188 /* Restart CL37 autoneg */ 5189 bnx2x_restart_autoneg(phy, params, 0); 5190 DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n"); 5191 } 5192 5193 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy, 5194 struct link_params *params, 5195 struct link_vars *vars, 5196 u32 gp_status) 5197 { 5198 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) 5199 vars->link_status |= 5200 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 5201 5202 if (bnx2x_direct_parallel_detect_used(phy, params)) 5203 vars->link_status |= 5204 LINK_STATUS_PARALLEL_DETECTION_USED; 5205 } 5206 static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy, 5207 struct link_params *params, 5208 struct link_vars *vars, 5209 u16 is_link_up, 5210 u16 speed_mask, 5211 u16 is_duplex) 5212 { 5213 struct bnx2x *bp = params->bp; 5214 if (phy->req_line_speed == SPEED_AUTO_NEG) 5215 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED; 5216 if (is_link_up) { 5217 DP(NETIF_MSG_LINK, "phy link up\n"); 5218 5219 vars->phy_link_up = 1; 5220 vars->link_status |= LINK_STATUS_LINK_UP; 5221 5222 switch (speed_mask) { 5223 case GP_STATUS_10M: 5224 vars->line_speed = SPEED_10; 5225 if (is_duplex == DUPLEX_FULL) 5226 vars->link_status |= LINK_10TFD; 5227 else 5228 vars->link_status |= LINK_10THD; 5229 break; 5230 5231 case GP_STATUS_100M: 5232 vars->line_speed = SPEED_100; 5233 if (is_duplex == DUPLEX_FULL) 5234 vars->link_status |= LINK_100TXFD; 5235 else 5236 vars->link_status |= LINK_100TXHD; 5237 break; 5238 5239 case GP_STATUS_1G: 5240 case GP_STATUS_1G_KX: 5241 vars->line_speed = SPEED_1000; 5242 if (is_duplex == DUPLEX_FULL) 5243 vars->link_status |= LINK_1000TFD; 5244 else 5245 vars->link_status |= LINK_1000THD; 5246 break; 5247 5248 case GP_STATUS_2_5G: 5249 vars->line_speed = SPEED_2500; 5250 if (is_duplex == DUPLEX_FULL) 5251 vars->link_status |= LINK_2500TFD; 5252 else 5253 vars->link_status |= LINK_2500THD; 5254 break; 5255 5256 case GP_STATUS_5G: 5257 case GP_STATUS_6G: 5258 DP(NETIF_MSG_LINK, 5259 "link speed unsupported gp_status 0x%x\n", 5260 speed_mask); 5261 return -EINVAL; 5262 5263 case GP_STATUS_10G_KX4: 5264 case GP_STATUS_10G_HIG: 5265 case GP_STATUS_10G_CX4: 5266 case GP_STATUS_10G_KR: 5267 case GP_STATUS_10G_SFI: 5268 case GP_STATUS_10G_XFI: 5269 vars->line_speed = SPEED_10000; 5270 vars->link_status |= LINK_10GTFD; 5271 break; 5272 case GP_STATUS_20G_DXGXS: 5273 vars->line_speed = SPEED_20000; 5274 vars->link_status |= LINK_20GTFD; 5275 break; 5276 default: 5277 DP(NETIF_MSG_LINK, 5278 "link speed unsupported gp_status 0x%x\n", 5279 speed_mask); 5280 return -EINVAL; 5281 } 5282 } else { /* link_down */ 5283 DP(NETIF_MSG_LINK, "phy link down\n"); 5284 5285 vars->phy_link_up = 0; 5286 5287 vars->duplex = DUPLEX_FULL; 5288 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 5289 vars->mac_type = MAC_TYPE_NONE; 5290 } 5291 DP(NETIF_MSG_LINK, " phy_link_up %x line_speed %d\n", 5292 vars->phy_link_up, vars->line_speed); 5293 return 0; 5294 } 5295 5296 static int bnx2x_link_settings_status(struct bnx2x_phy *phy, 5297 struct link_params *params, 5298 struct link_vars *vars) 5299 { 5300 struct bnx2x *bp = params->bp; 5301 5302 u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask; 5303 int rc = 0; 5304 5305 /* Read gp_status */ 5306 CL22_RD_OVER_CL45(bp, phy, 5307 MDIO_REG_BANK_GP_STATUS, 5308 MDIO_GP_STATUS_TOP_AN_STATUS1, 5309 &gp_status); 5310 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS) 5311 duplex = DUPLEX_FULL; 5312 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) 5313 link_up = 1; 5314 speed_mask = gp_status & GP_STATUS_SPEED_MASK; 5315 DP(NETIF_MSG_LINK, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n", 5316 gp_status, link_up, speed_mask); 5317 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask, 5318 duplex); 5319 if (rc == -EINVAL) 5320 return rc; 5321 5322 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) { 5323 if (SINGLE_MEDIA_DIRECT(params)) { 5324 vars->duplex = duplex; 5325 bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status); 5326 if (phy->req_line_speed == SPEED_AUTO_NEG) 5327 bnx2x_xgxs_an_resolve(phy, params, vars, 5328 gp_status); 5329 } 5330 } else { /* Link_down */ 5331 if ((phy->req_line_speed == SPEED_AUTO_NEG) && 5332 SINGLE_MEDIA_DIRECT(params)) { 5333 /* Check signal is detected */ 5334 bnx2x_check_fallback_to_cl37(phy, params); 5335 } 5336 } 5337 5338 /* Read LP advertised speeds*/ 5339 if (SINGLE_MEDIA_DIRECT(params) && 5340 (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) { 5341 u16 val; 5342 5343 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_CL73_IEEEB1, 5344 MDIO_CL73_IEEEB1_AN_LP_ADV2, &val); 5345 5346 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX) 5347 vars->link_status |= 5348 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 5349 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 | 5350 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR)) 5351 vars->link_status |= 5352 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 5353 5354 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_OVER_1G, 5355 MDIO_OVER_1G_LP_UP1, &val); 5356 5357 if (val & MDIO_OVER_1G_UP1_2_5G) 5358 vars->link_status |= 5359 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE; 5360 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH)) 5361 vars->link_status |= 5362 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 5363 } 5364 5365 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n", 5366 vars->duplex, vars->flow_ctrl, vars->link_status); 5367 return rc; 5368 } 5369 5370 static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy, 5371 struct link_params *params, 5372 struct link_vars *vars) 5373 { 5374 struct bnx2x *bp = params->bp; 5375 u8 lane; 5376 u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL; 5377 int rc = 0; 5378 lane = bnx2x_get_warpcore_lane(phy, params); 5379 /* Read gp_status */ 5380 if (phy->req_line_speed > SPEED_10000) { 5381 u16 temp_link_up; 5382 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5383 1, &temp_link_up); 5384 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5385 1, &link_up); 5386 DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n", 5387 temp_link_up, link_up); 5388 link_up &= (1<<2); 5389 if (link_up) 5390 bnx2x_ext_phy_resolve_fc(phy, params, vars); 5391 } else { 5392 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5393 MDIO_WC_REG_GP2_STATUS_GP_2_1, &gp_status1); 5394 DP(NETIF_MSG_LINK, "0x81d1 = 0x%x\n", gp_status1); 5395 /* Check for either KR or generic link up. */ 5396 gp_status1 = ((gp_status1 >> 8) & 0xf) | 5397 ((gp_status1 >> 12) & 0xf); 5398 link_up = gp_status1 & (1 << lane); 5399 if (link_up && SINGLE_MEDIA_DIRECT(params)) { 5400 u16 pd, gp_status4; 5401 if (phy->req_line_speed == SPEED_AUTO_NEG) { 5402 /* Check Autoneg complete */ 5403 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5404 MDIO_WC_REG_GP2_STATUS_GP_2_4, 5405 &gp_status4); 5406 if (gp_status4 & ((1<<12)<<lane)) 5407 vars->link_status |= 5408 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 5409 5410 /* Check parallel detect used */ 5411 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5412 MDIO_WC_REG_PAR_DET_10G_STATUS, 5413 &pd); 5414 if (pd & (1<<15)) 5415 vars->link_status |= 5416 LINK_STATUS_PARALLEL_DETECTION_USED; 5417 } 5418 bnx2x_ext_phy_resolve_fc(phy, params, vars); 5419 vars->duplex = duplex; 5420 } 5421 } 5422 5423 if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) && 5424 SINGLE_MEDIA_DIRECT(params)) { 5425 u16 val; 5426 5427 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 5428 MDIO_AN_REG_LP_AUTO_NEG2, &val); 5429 5430 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX) 5431 vars->link_status |= 5432 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 5433 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 | 5434 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR)) 5435 vars->link_status |= 5436 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 5437 5438 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5439 MDIO_WC_REG_DIGITAL3_LP_UP1, &val); 5440 5441 if (val & MDIO_OVER_1G_UP1_2_5G) 5442 vars->link_status |= 5443 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE; 5444 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH)) 5445 vars->link_status |= 5446 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 5447 5448 } 5449 5450 5451 if (lane < 2) { 5452 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5453 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed); 5454 } else { 5455 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 5456 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed); 5457 } 5458 DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed); 5459 5460 if ((lane & 1) == 0) 5461 gp_speed <<= 8; 5462 gp_speed &= 0x3f00; 5463 5464 5465 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed, 5466 duplex); 5467 5468 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n", 5469 vars->duplex, vars->flow_ctrl, vars->link_status); 5470 return rc; 5471 } 5472 static void bnx2x_set_gmii_tx_driver(struct link_params *params) 5473 { 5474 struct bnx2x *bp = params->bp; 5475 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; 5476 u16 lp_up2; 5477 u16 tx_driver; 5478 u16 bank; 5479 5480 /* Read precomp */ 5481 CL22_RD_OVER_CL45(bp, phy, 5482 MDIO_REG_BANK_OVER_1G, 5483 MDIO_OVER_1G_LP_UP2, &lp_up2); 5484 5485 /* Bits [10:7] at lp_up2, positioned at [15:12] */ 5486 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >> 5487 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) << 5488 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT); 5489 5490 if (lp_up2 == 0) 5491 return; 5492 5493 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3; 5494 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) { 5495 CL22_RD_OVER_CL45(bp, phy, 5496 bank, 5497 MDIO_TX0_TX_DRIVER, &tx_driver); 5498 5499 /* Replace tx_driver bits [15:12] */ 5500 if (lp_up2 != 5501 (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) { 5502 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK; 5503 tx_driver |= lp_up2; 5504 CL22_WR_OVER_CL45(bp, phy, 5505 bank, 5506 MDIO_TX0_TX_DRIVER, tx_driver); 5507 } 5508 } 5509 } 5510 5511 static int bnx2x_emac_program(struct link_params *params, 5512 struct link_vars *vars) 5513 { 5514 struct bnx2x *bp = params->bp; 5515 u8 port = params->port; 5516 u16 mode = 0; 5517 5518 DP(NETIF_MSG_LINK, "setting link speed & duplex\n"); 5519 bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 + 5520 EMAC_REG_EMAC_MODE, 5521 (EMAC_MODE_25G_MODE | 5522 EMAC_MODE_PORT_MII_10M | 5523 EMAC_MODE_HALF_DUPLEX)); 5524 switch (vars->line_speed) { 5525 case SPEED_10: 5526 mode |= EMAC_MODE_PORT_MII_10M; 5527 break; 5528 5529 case SPEED_100: 5530 mode |= EMAC_MODE_PORT_MII; 5531 break; 5532 5533 case SPEED_1000: 5534 mode |= EMAC_MODE_PORT_GMII; 5535 break; 5536 5537 case SPEED_2500: 5538 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII); 5539 break; 5540 5541 default: 5542 /* 10G not valid for EMAC */ 5543 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", 5544 vars->line_speed); 5545 return -EINVAL; 5546 } 5547 5548 if (vars->duplex == DUPLEX_HALF) 5549 mode |= EMAC_MODE_HALF_DUPLEX; 5550 bnx2x_bits_en(bp, 5551 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE, 5552 mode); 5553 5554 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed); 5555 return 0; 5556 } 5557 5558 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy, 5559 struct link_params *params) 5560 { 5561 5562 u16 bank, i = 0; 5563 struct bnx2x *bp = params->bp; 5564 5565 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3; 5566 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) { 5567 CL22_WR_OVER_CL45(bp, phy, 5568 bank, 5569 MDIO_RX0_RX_EQ_BOOST, 5570 phy->rx_preemphasis[i]); 5571 } 5572 5573 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3; 5574 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) { 5575 CL22_WR_OVER_CL45(bp, phy, 5576 bank, 5577 MDIO_TX0_TX_DRIVER, 5578 phy->tx_preemphasis[i]); 5579 } 5580 } 5581 5582 static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy, 5583 struct link_params *params, 5584 struct link_vars *vars) 5585 { 5586 struct bnx2x *bp = params->bp; 5587 u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) || 5588 (params->loopback_mode == LOOPBACK_XGXS)); 5589 if (!(vars->phy_flags & PHY_SGMII_FLAG)) { 5590 if (SINGLE_MEDIA_DIRECT(params) && 5591 (params->feature_config_flags & 5592 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) 5593 bnx2x_set_preemphasis(phy, params); 5594 5595 /* Forced speed requested? */ 5596 if (vars->line_speed != SPEED_AUTO_NEG || 5597 (SINGLE_MEDIA_DIRECT(params) && 5598 params->loopback_mode == LOOPBACK_EXT)) { 5599 DP(NETIF_MSG_LINK, "not SGMII, no AN\n"); 5600 5601 /* Disable autoneg */ 5602 bnx2x_set_autoneg(phy, params, vars, 0); 5603 5604 /* Program speed and duplex */ 5605 bnx2x_program_serdes(phy, params, vars); 5606 5607 } else { /* AN_mode */ 5608 DP(NETIF_MSG_LINK, "not SGMII, AN\n"); 5609 5610 /* AN enabled */ 5611 bnx2x_set_brcm_cl37_advertisement(phy, params); 5612 5613 /* Program duplex & pause advertisement (for aneg) */ 5614 bnx2x_set_ieee_aneg_advertisement(phy, params, 5615 vars->ieee_fc); 5616 5617 /* Enable autoneg */ 5618 bnx2x_set_autoneg(phy, params, vars, enable_cl73); 5619 5620 /* Enable and restart AN */ 5621 bnx2x_restart_autoneg(phy, params, enable_cl73); 5622 } 5623 5624 } else { /* SGMII mode */ 5625 DP(NETIF_MSG_LINK, "SGMII\n"); 5626 5627 bnx2x_initialize_sgmii_process(phy, params, vars); 5628 } 5629 } 5630 5631 static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy, 5632 struct link_params *params, 5633 struct link_vars *vars) 5634 { 5635 int rc; 5636 vars->phy_flags |= PHY_XGXS_FLAG; 5637 if ((phy->req_line_speed && 5638 ((phy->req_line_speed == SPEED_100) || 5639 (phy->req_line_speed == SPEED_10))) || 5640 (!phy->req_line_speed && 5641 (phy->speed_cap_mask >= 5642 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) && 5643 (phy->speed_cap_mask < 5644 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || 5645 (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD)) 5646 vars->phy_flags |= PHY_SGMII_FLAG; 5647 else 5648 vars->phy_flags &= ~PHY_SGMII_FLAG; 5649 5650 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); 5651 bnx2x_set_aer_mmd(params, phy); 5652 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) 5653 bnx2x_set_master_ln(params, phy); 5654 5655 rc = bnx2x_reset_unicore(params, phy, 0); 5656 /* Reset the SerDes and wait for reset bit return low */ 5657 if (rc) 5658 return rc; 5659 5660 bnx2x_set_aer_mmd(params, phy); 5661 /* Setting the masterLn_def again after the reset */ 5662 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) { 5663 bnx2x_set_master_ln(params, phy); 5664 bnx2x_set_swap_lanes(params, phy); 5665 } 5666 5667 return rc; 5668 } 5669 5670 static u16 bnx2x_wait_reset_complete(struct bnx2x *bp, 5671 struct bnx2x_phy *phy, 5672 struct link_params *params) 5673 { 5674 u16 cnt, ctrl; 5675 /* Wait for soft reset to get cleared up to 1 sec */ 5676 for (cnt = 0; cnt < 1000; cnt++) { 5677 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) 5678 bnx2x_cl22_read(bp, phy, 5679 MDIO_PMA_REG_CTRL, &ctrl); 5680 else 5681 bnx2x_cl45_read(bp, phy, 5682 MDIO_PMA_DEVAD, 5683 MDIO_PMA_REG_CTRL, &ctrl); 5684 if (!(ctrl & (1<<15))) 5685 break; 5686 usleep_range(1000, 2000); 5687 } 5688 5689 if (cnt == 1000) 5690 netdev_err(bp->dev, "Warning: PHY was not initialized," 5691 " Port %d\n", 5692 params->port); 5693 DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt); 5694 return cnt; 5695 } 5696 5697 static void bnx2x_link_int_enable(struct link_params *params) 5698 { 5699 u8 port = params->port; 5700 u32 mask; 5701 struct bnx2x *bp = params->bp; 5702 5703 /* Setting the status to report on link up for either XGXS or SerDes */ 5704 if (CHIP_IS_E3(bp)) { 5705 mask = NIG_MASK_XGXS0_LINK_STATUS; 5706 if (!(SINGLE_MEDIA_DIRECT(params))) 5707 mask |= NIG_MASK_MI_INT; 5708 } else if (params->switch_cfg == SWITCH_CFG_10G) { 5709 mask = (NIG_MASK_XGXS0_LINK10G | 5710 NIG_MASK_XGXS0_LINK_STATUS); 5711 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n"); 5712 if (!(SINGLE_MEDIA_DIRECT(params)) && 5713 params->phy[INT_PHY].type != 5714 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) { 5715 mask |= NIG_MASK_MI_INT; 5716 DP(NETIF_MSG_LINK, "enabled external phy int\n"); 5717 } 5718 5719 } else { /* SerDes */ 5720 mask = NIG_MASK_SERDES0_LINK_STATUS; 5721 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n"); 5722 if (!(SINGLE_MEDIA_DIRECT(params)) && 5723 params->phy[INT_PHY].type != 5724 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) { 5725 mask |= NIG_MASK_MI_INT; 5726 DP(NETIF_MSG_LINK, "enabled external phy int\n"); 5727 } 5728 } 5729 bnx2x_bits_en(bp, 5730 NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 5731 mask); 5732 5733 DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port, 5734 (params->switch_cfg == SWITCH_CFG_10G), 5735 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4)); 5736 DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n", 5737 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), 5738 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18), 5739 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c)); 5740 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n", 5741 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), 5742 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); 5743 } 5744 5745 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port, 5746 u8 exp_mi_int) 5747 { 5748 u32 latch_status = 0; 5749 5750 /* Disable the MI INT ( external phy int ) by writing 1 to the 5751 * status register. Link down indication is high-active-signal, 5752 * so in this case we need to write the status to clear the XOR 5753 */ 5754 /* Read Latched signals */ 5755 latch_status = REG_RD(bp, 5756 NIG_REG_LATCH_STATUS_0 + port*8); 5757 DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status); 5758 /* Handle only those with latched-signal=up.*/ 5759 if (exp_mi_int) 5760 bnx2x_bits_en(bp, 5761 NIG_REG_STATUS_INTERRUPT_PORT0 5762 + port*4, 5763 NIG_STATUS_EMAC0_MI_INT); 5764 else 5765 bnx2x_bits_dis(bp, 5766 NIG_REG_STATUS_INTERRUPT_PORT0 5767 + port*4, 5768 NIG_STATUS_EMAC0_MI_INT); 5769 5770 if (latch_status & 1) { 5771 5772 /* For all latched-signal=up : Re-Arm Latch signals */ 5773 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8, 5774 (latch_status & 0xfffe) | (latch_status & 1)); 5775 } 5776 /* For all latched-signal=up,Write original_signal to status */ 5777 } 5778 5779 static void bnx2x_link_int_ack(struct link_params *params, 5780 struct link_vars *vars, u8 is_10g_plus) 5781 { 5782 struct bnx2x *bp = params->bp; 5783 u8 port = params->port; 5784 u32 mask; 5785 /* First reset all status we assume only one line will be 5786 * change at a time 5787 */ 5788 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, 5789 (NIG_STATUS_XGXS0_LINK10G | 5790 NIG_STATUS_XGXS0_LINK_STATUS | 5791 NIG_STATUS_SERDES0_LINK_STATUS)); 5792 if (vars->phy_link_up) { 5793 if (USES_WARPCORE(bp)) 5794 mask = NIG_STATUS_XGXS0_LINK_STATUS; 5795 else { 5796 if (is_10g_plus) 5797 mask = NIG_STATUS_XGXS0_LINK10G; 5798 else if (params->switch_cfg == SWITCH_CFG_10G) { 5799 /* Disable the link interrupt by writing 1 to 5800 * the relevant lane in the status register 5801 */ 5802 u32 ser_lane = 5803 ((params->lane_config & 5804 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> 5805 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); 5806 mask = ((1 << ser_lane) << 5807 NIG_STATUS_XGXS0_LINK_STATUS_SIZE); 5808 } else 5809 mask = NIG_STATUS_SERDES0_LINK_STATUS; 5810 } 5811 DP(NETIF_MSG_LINK, "Ack link up interrupt with mask 0x%x\n", 5812 mask); 5813 bnx2x_bits_en(bp, 5814 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, 5815 mask); 5816 } 5817 } 5818 5819 static int bnx2x_format_ver(u32 num, u8 *str, u16 *len) 5820 { 5821 u8 *str_ptr = str; 5822 u32 mask = 0xf0000000; 5823 u8 shift = 8*4; 5824 u8 digit; 5825 u8 remove_leading_zeros = 1; 5826 if (*len < 10) { 5827 /* Need more than 10chars for this format */ 5828 *str_ptr = '\0'; 5829 (*len)--; 5830 return -EINVAL; 5831 } 5832 while (shift > 0) { 5833 5834 shift -= 4; 5835 digit = ((num & mask) >> shift); 5836 if (digit == 0 && remove_leading_zeros) { 5837 mask = mask >> 4; 5838 continue; 5839 } else if (digit < 0xa) 5840 *str_ptr = digit + '0'; 5841 else 5842 *str_ptr = digit - 0xa + 'a'; 5843 remove_leading_zeros = 0; 5844 str_ptr++; 5845 (*len)--; 5846 mask = mask >> 4; 5847 if (shift == 4*4) { 5848 *str_ptr = '.'; 5849 str_ptr++; 5850 (*len)--; 5851 remove_leading_zeros = 1; 5852 } 5853 } 5854 return 0; 5855 } 5856 5857 5858 static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len) 5859 { 5860 str[0] = '\0'; 5861 (*len)--; 5862 return 0; 5863 } 5864 5865 int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 *version, 5866 u16 len) 5867 { 5868 struct bnx2x *bp; 5869 u32 spirom_ver = 0; 5870 int status = 0; 5871 u8 *ver_p = version; 5872 u16 remain_len = len; 5873 if (version == NULL || params == NULL) 5874 return -EINVAL; 5875 bp = params->bp; 5876 5877 /* Extract first external phy*/ 5878 version[0] = '\0'; 5879 spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr); 5880 5881 if (params->phy[EXT_PHY1].format_fw_ver) { 5882 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver, 5883 ver_p, 5884 &remain_len); 5885 ver_p += (len - remain_len); 5886 } 5887 if ((params->num_phys == MAX_PHYS) && 5888 (params->phy[EXT_PHY2].ver_addr != 0)) { 5889 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr); 5890 if (params->phy[EXT_PHY2].format_fw_ver) { 5891 *ver_p = '/'; 5892 ver_p++; 5893 remain_len--; 5894 status |= params->phy[EXT_PHY2].format_fw_ver( 5895 spirom_ver, 5896 ver_p, 5897 &remain_len); 5898 ver_p = version + (len - remain_len); 5899 } 5900 } 5901 *ver_p = '\0'; 5902 return status; 5903 } 5904 5905 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy, 5906 struct link_params *params) 5907 { 5908 u8 port = params->port; 5909 struct bnx2x *bp = params->bp; 5910 5911 if (phy->req_line_speed != SPEED_1000) { 5912 u32 md_devad = 0; 5913 5914 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n"); 5915 5916 if (!CHIP_IS_E3(bp)) { 5917 /* Change the uni_phy_addr in the nig */ 5918 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD + 5919 port*0x18)); 5920 5921 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 5922 0x5); 5923 } 5924 5925 bnx2x_cl45_write(bp, phy, 5926 5, 5927 (MDIO_REG_BANK_AER_BLOCK + 5928 (MDIO_AER_BLOCK_AER_REG & 0xf)), 5929 0x2800); 5930 5931 bnx2x_cl45_write(bp, phy, 5932 5, 5933 (MDIO_REG_BANK_CL73_IEEEB0 + 5934 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)), 5935 0x6041); 5936 msleep(200); 5937 /* Set aer mmd back */ 5938 bnx2x_set_aer_mmd(params, phy); 5939 5940 if (!CHIP_IS_E3(bp)) { 5941 /* And md_devad */ 5942 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 5943 md_devad); 5944 } 5945 } else { 5946 u16 mii_ctrl; 5947 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n"); 5948 bnx2x_cl45_read(bp, phy, 5, 5949 (MDIO_REG_BANK_COMBO_IEEE0 + 5950 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)), 5951 &mii_ctrl); 5952 bnx2x_cl45_write(bp, phy, 5, 5953 (MDIO_REG_BANK_COMBO_IEEE0 + 5954 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)), 5955 mii_ctrl | 5956 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK); 5957 } 5958 } 5959 5960 int bnx2x_set_led(struct link_params *params, 5961 struct link_vars *vars, u8 mode, u32 speed) 5962 { 5963 u8 port = params->port; 5964 u16 hw_led_mode = params->hw_led_mode; 5965 int rc = 0; 5966 u8 phy_idx; 5967 u32 tmp; 5968 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 5969 struct bnx2x *bp = params->bp; 5970 DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode); 5971 DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n", 5972 speed, hw_led_mode); 5973 /* In case */ 5974 for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) { 5975 if (params->phy[phy_idx].set_link_led) { 5976 params->phy[phy_idx].set_link_led( 5977 ¶ms->phy[phy_idx], params, mode); 5978 } 5979 } 5980 5981 switch (mode) { 5982 case LED_MODE_FRONT_PANEL_OFF: 5983 case LED_MODE_OFF: 5984 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0); 5985 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 5986 SHARED_HW_CFG_LED_MAC1); 5987 5988 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); 5989 if (params->phy[EXT_PHY1].type == 5990 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) 5991 tmp &= ~(EMAC_LED_1000MB_OVERRIDE | 5992 EMAC_LED_100MB_OVERRIDE | 5993 EMAC_LED_10MB_OVERRIDE); 5994 else 5995 tmp |= EMAC_LED_OVERRIDE; 5996 5997 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp); 5998 break; 5999 6000 case LED_MODE_OPER: 6001 /* For all other phys, OPER mode is same as ON, so in case 6002 * link is down, do nothing 6003 */ 6004 if (!vars->link_up) 6005 break; 6006 case LED_MODE_ON: 6007 if (((params->phy[EXT_PHY1].type == 6008 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) || 6009 (params->phy[EXT_PHY1].type == 6010 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) && 6011 CHIP_IS_E2(bp) && params->num_phys == 2) { 6012 /* This is a work-around for E2+8727 Configurations */ 6013 if (mode == LED_MODE_ON || 6014 speed == SPEED_10000){ 6015 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); 6016 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1); 6017 6018 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); 6019 EMAC_WR(bp, EMAC_REG_EMAC_LED, 6020 (tmp | EMAC_LED_OVERRIDE)); 6021 /* Return here without enabling traffic 6022 * LED blink and setting rate in ON mode. 6023 * In oper mode, enabling LED blink 6024 * and setting rate is needed. 6025 */ 6026 if (mode == LED_MODE_ON) 6027 return rc; 6028 } 6029 } else if (SINGLE_MEDIA_DIRECT(params)) { 6030 /* This is a work-around for HW issue found when link 6031 * is up in CL73 6032 */ 6033 if ((!CHIP_IS_E3(bp)) || 6034 (CHIP_IS_E3(bp) && 6035 mode == LED_MODE_ON)) 6036 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1); 6037 6038 if (CHIP_IS_E1x(bp) || 6039 CHIP_IS_E2(bp) || 6040 (mode == LED_MODE_ON)) 6041 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); 6042 else 6043 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 6044 hw_led_mode); 6045 } else if ((params->phy[EXT_PHY1].type == 6046 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) && 6047 (mode == LED_MODE_ON)) { 6048 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); 6049 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); 6050 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp | 6051 EMAC_LED_OVERRIDE | EMAC_LED_1000MB_OVERRIDE); 6052 /* Break here; otherwise, it'll disable the 6053 * intended override. 6054 */ 6055 break; 6056 } else 6057 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 6058 hw_led_mode); 6059 6060 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0); 6061 /* Set blinking rate to ~15.9Hz */ 6062 if (CHIP_IS_E3(bp)) 6063 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, 6064 LED_BLINK_RATE_VAL_E3); 6065 else 6066 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, 6067 LED_BLINK_RATE_VAL_E1X_E2); 6068 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 + 6069 port*4, 1); 6070 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); 6071 EMAC_WR(bp, EMAC_REG_EMAC_LED, 6072 (tmp & (~EMAC_LED_OVERRIDE))); 6073 6074 if (CHIP_IS_E1(bp) && 6075 ((speed == SPEED_2500) || 6076 (speed == SPEED_1000) || 6077 (speed == SPEED_100) || 6078 (speed == SPEED_10))) { 6079 /* For speeds less than 10G LED scheme is different */ 6080 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 6081 + port*4, 1); 6082 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 + 6083 port*4, 0); 6084 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 + 6085 port*4, 1); 6086 } 6087 break; 6088 6089 default: 6090 rc = -EINVAL; 6091 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n", 6092 mode); 6093 break; 6094 } 6095 return rc; 6096 6097 } 6098 6099 /* This function comes to reflect the actual link state read DIRECTLY from the 6100 * HW 6101 */ 6102 int bnx2x_test_link(struct link_params *params, struct link_vars *vars, 6103 u8 is_serdes) 6104 { 6105 struct bnx2x *bp = params->bp; 6106 u16 gp_status = 0, phy_index = 0; 6107 u8 ext_phy_link_up = 0, serdes_phy_type; 6108 struct link_vars temp_vars; 6109 struct bnx2x_phy *int_phy = ¶ms->phy[INT_PHY]; 6110 6111 if (CHIP_IS_E3(bp)) { 6112 u16 link_up; 6113 if (params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)] 6114 > SPEED_10000) { 6115 /* Check 20G link */ 6116 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD, 6117 1, &link_up); 6118 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD, 6119 1, &link_up); 6120 link_up &= (1<<2); 6121 } else { 6122 /* Check 10G link and below*/ 6123 u8 lane = bnx2x_get_warpcore_lane(int_phy, params); 6124 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD, 6125 MDIO_WC_REG_GP2_STATUS_GP_2_1, 6126 &gp_status); 6127 gp_status = ((gp_status >> 8) & 0xf) | 6128 ((gp_status >> 12) & 0xf); 6129 link_up = gp_status & (1 << lane); 6130 } 6131 if (!link_up) 6132 return -ESRCH; 6133 } else { 6134 CL22_RD_OVER_CL45(bp, int_phy, 6135 MDIO_REG_BANK_GP_STATUS, 6136 MDIO_GP_STATUS_TOP_AN_STATUS1, 6137 &gp_status); 6138 /* Link is up only if both local phy and external phy are up */ 6139 if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)) 6140 return -ESRCH; 6141 } 6142 /* In XGXS loopback mode, do not check external PHY */ 6143 if (params->loopback_mode == LOOPBACK_XGXS) 6144 return 0; 6145 6146 switch (params->num_phys) { 6147 case 1: 6148 /* No external PHY */ 6149 return 0; 6150 case 2: 6151 ext_phy_link_up = params->phy[EXT_PHY1].read_status( 6152 ¶ms->phy[EXT_PHY1], 6153 params, &temp_vars); 6154 break; 6155 case 3: /* Dual Media */ 6156 for (phy_index = EXT_PHY1; phy_index < params->num_phys; 6157 phy_index++) { 6158 serdes_phy_type = ((params->phy[phy_index].media_type == 6159 ETH_PHY_SFPP_10G_FIBER) || 6160 (params->phy[phy_index].media_type == 6161 ETH_PHY_SFP_1G_FIBER) || 6162 (params->phy[phy_index].media_type == 6163 ETH_PHY_XFP_FIBER) || 6164 (params->phy[phy_index].media_type == 6165 ETH_PHY_DA_TWINAX)); 6166 6167 if (is_serdes != serdes_phy_type) 6168 continue; 6169 if (params->phy[phy_index].read_status) { 6170 ext_phy_link_up |= 6171 params->phy[phy_index].read_status( 6172 ¶ms->phy[phy_index], 6173 params, &temp_vars); 6174 } 6175 } 6176 break; 6177 } 6178 if (ext_phy_link_up) 6179 return 0; 6180 return -ESRCH; 6181 } 6182 6183 static int bnx2x_link_initialize(struct link_params *params, 6184 struct link_vars *vars) 6185 { 6186 int rc = 0; 6187 u8 phy_index, non_ext_phy; 6188 struct bnx2x *bp = params->bp; 6189 /* In case of external phy existence, the line speed would be the 6190 * line speed linked up by the external phy. In case it is direct 6191 * only, then the line_speed during initialization will be 6192 * equal to the req_line_speed 6193 */ 6194 vars->line_speed = params->phy[INT_PHY].req_line_speed; 6195 6196 /* Initialize the internal phy in case this is a direct board 6197 * (no external phys), or this board has external phy which requires 6198 * to first. 6199 */ 6200 if (!USES_WARPCORE(bp)) 6201 bnx2x_prepare_xgxs(¶ms->phy[INT_PHY], params, vars); 6202 /* init ext phy and enable link state int */ 6203 non_ext_phy = (SINGLE_MEDIA_DIRECT(params) || 6204 (params->loopback_mode == LOOPBACK_XGXS)); 6205 6206 if (non_ext_phy || 6207 (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) || 6208 (params->loopback_mode == LOOPBACK_EXT_PHY)) { 6209 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; 6210 if (vars->line_speed == SPEED_AUTO_NEG && 6211 (CHIP_IS_E1x(bp) || 6212 CHIP_IS_E2(bp))) 6213 bnx2x_set_parallel_detection(phy, params); 6214 if (params->phy[INT_PHY].config_init) 6215 params->phy[INT_PHY].config_init(phy, 6216 params, 6217 vars); 6218 } 6219 6220 /* Init external phy*/ 6221 if (non_ext_phy) { 6222 if (params->phy[INT_PHY].supported & 6223 SUPPORTED_FIBRE) 6224 vars->link_status |= LINK_STATUS_SERDES_LINK; 6225 } else { 6226 for (phy_index = EXT_PHY1; phy_index < params->num_phys; 6227 phy_index++) { 6228 /* No need to initialize second phy in case of first 6229 * phy only selection. In case of second phy, we do 6230 * need to initialize the first phy, since they are 6231 * connected. 6232 */ 6233 if (params->phy[phy_index].supported & 6234 SUPPORTED_FIBRE) 6235 vars->link_status |= LINK_STATUS_SERDES_LINK; 6236 6237 if (phy_index == EXT_PHY2 && 6238 (bnx2x_phy_selection(params) == 6239 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) { 6240 DP(NETIF_MSG_LINK, 6241 "Not initializing second phy\n"); 6242 continue; 6243 } 6244 params->phy[phy_index].config_init( 6245 ¶ms->phy[phy_index], 6246 params, vars); 6247 } 6248 } 6249 /* Reset the interrupt indication after phy was initialized */ 6250 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + 6251 params->port*4, 6252 (NIG_STATUS_XGXS0_LINK10G | 6253 NIG_STATUS_XGXS0_LINK_STATUS | 6254 NIG_STATUS_SERDES0_LINK_STATUS | 6255 NIG_MASK_MI_INT)); 6256 return rc; 6257 } 6258 6259 static void bnx2x_int_link_reset(struct bnx2x_phy *phy, 6260 struct link_params *params) 6261 { 6262 /* Reset the SerDes/XGXS */ 6263 REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, 6264 (0x1ff << (params->port*16))); 6265 } 6266 6267 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy, 6268 struct link_params *params) 6269 { 6270 struct bnx2x *bp = params->bp; 6271 u8 gpio_port; 6272 /* HW reset */ 6273 if (CHIP_IS_E2(bp)) 6274 gpio_port = BP_PATH(bp); 6275 else 6276 gpio_port = params->port; 6277 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 6278 MISC_REGISTERS_GPIO_OUTPUT_LOW, 6279 gpio_port); 6280 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 6281 MISC_REGISTERS_GPIO_OUTPUT_LOW, 6282 gpio_port); 6283 DP(NETIF_MSG_LINK, "reset external PHY\n"); 6284 } 6285 6286 static int bnx2x_update_link_down(struct link_params *params, 6287 struct link_vars *vars) 6288 { 6289 struct bnx2x *bp = params->bp; 6290 u8 port = params->port; 6291 6292 DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port); 6293 bnx2x_set_led(params, vars, LED_MODE_OFF, 0); 6294 vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG; 6295 /* Indicate no mac active */ 6296 vars->mac_type = MAC_TYPE_NONE; 6297 6298 /* Update shared memory */ 6299 vars->link_status &= ~(LINK_STATUS_SPEED_AND_DUPLEX_MASK | 6300 LINK_STATUS_LINK_UP | 6301 LINK_STATUS_PHYSICAL_LINK_FLAG | 6302 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE | 6303 LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK | 6304 LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK | 6305 LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK | 6306 LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE | 6307 LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE); 6308 vars->line_speed = 0; 6309 bnx2x_update_mng(params, vars->link_status); 6310 6311 /* Activate nig drain */ 6312 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); 6313 6314 /* Disable emac */ 6315 if (!CHIP_IS_E3(bp)) 6316 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); 6317 6318 usleep_range(10000, 20000); 6319 /* Reset BigMac/Xmac */ 6320 if (CHIP_IS_E1x(bp) || 6321 CHIP_IS_E2(bp)) 6322 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0); 6323 6324 if (CHIP_IS_E3(bp)) { 6325 /* Prevent LPI Generation by chip */ 6326 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 6327 0); 6328 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2), 6329 0); 6330 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK | 6331 SHMEM_EEE_ACTIVE_BIT); 6332 6333 bnx2x_update_mng_eee(params, vars->eee_status); 6334 bnx2x_set_xmac_rxtx(params, 0); 6335 bnx2x_set_umac_rxtx(params, 0); 6336 } 6337 6338 return 0; 6339 } 6340 6341 static int bnx2x_update_link_up(struct link_params *params, 6342 struct link_vars *vars, 6343 u8 link_10g) 6344 { 6345 struct bnx2x *bp = params->bp; 6346 u8 phy_idx, port = params->port; 6347 int rc = 0; 6348 6349 vars->link_status |= (LINK_STATUS_LINK_UP | 6350 LINK_STATUS_PHYSICAL_LINK_FLAG); 6351 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG; 6352 6353 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) 6354 vars->link_status |= 6355 LINK_STATUS_TX_FLOW_CONTROL_ENABLED; 6356 6357 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) 6358 vars->link_status |= 6359 LINK_STATUS_RX_FLOW_CONTROL_ENABLED; 6360 if (USES_WARPCORE(bp)) { 6361 if (link_10g) { 6362 if (bnx2x_xmac_enable(params, vars, 0) == 6363 -ESRCH) { 6364 DP(NETIF_MSG_LINK, "Found errors on XMAC\n"); 6365 vars->link_up = 0; 6366 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; 6367 vars->link_status &= ~LINK_STATUS_LINK_UP; 6368 } 6369 } else 6370 bnx2x_umac_enable(params, vars, 0); 6371 bnx2x_set_led(params, vars, 6372 LED_MODE_OPER, vars->line_speed); 6373 6374 if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) && 6375 (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) { 6376 DP(NETIF_MSG_LINK, "Enabling LPI assertion\n"); 6377 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + 6378 (params->port << 2), 1); 6379 REG_WR(bp, MISC_REG_CPMU_LP_DR_ENABLE, 1); 6380 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + 6381 (params->port << 2), 0xfc20); 6382 } 6383 } 6384 if ((CHIP_IS_E1x(bp) || 6385 CHIP_IS_E2(bp))) { 6386 if (link_10g) { 6387 if (bnx2x_bmac_enable(params, vars, 0, 1) == 6388 -ESRCH) { 6389 DP(NETIF_MSG_LINK, "Found errors on BMAC\n"); 6390 vars->link_up = 0; 6391 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; 6392 vars->link_status &= ~LINK_STATUS_LINK_UP; 6393 } 6394 6395 bnx2x_set_led(params, vars, 6396 LED_MODE_OPER, SPEED_10000); 6397 } else { 6398 rc = bnx2x_emac_program(params, vars); 6399 bnx2x_emac_enable(params, vars, 0); 6400 6401 /* AN complete? */ 6402 if ((vars->link_status & 6403 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) 6404 && (!(vars->phy_flags & PHY_SGMII_FLAG)) && 6405 SINGLE_MEDIA_DIRECT(params)) 6406 bnx2x_set_gmii_tx_driver(params); 6407 } 6408 } 6409 6410 /* PBF - link up */ 6411 if (CHIP_IS_E1x(bp)) 6412 rc |= bnx2x_pbf_update(params, vars->flow_ctrl, 6413 vars->line_speed); 6414 6415 /* Disable drain */ 6416 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0); 6417 6418 /* Update shared memory */ 6419 bnx2x_update_mng(params, vars->link_status); 6420 bnx2x_update_mng_eee(params, vars->eee_status); 6421 /* Check remote fault */ 6422 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) { 6423 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) { 6424 bnx2x_check_half_open_conn(params, vars, 0); 6425 break; 6426 } 6427 } 6428 msleep(20); 6429 return rc; 6430 } 6431 /* The bnx2x_link_update function should be called upon link 6432 * interrupt. 6433 * Link is considered up as follows: 6434 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs 6435 * to be up 6436 * - SINGLE_MEDIA - The link between the 577xx and the external 6437 * phy (XGXS) need to up as well as the external link of the 6438 * phy (PHY_EXT1) 6439 * - DUAL_MEDIA - The link between the 577xx and the first 6440 * external phy needs to be up, and at least one of the 2 6441 * external phy link must be up. 6442 */ 6443 int bnx2x_link_update(struct link_params *params, struct link_vars *vars) 6444 { 6445 struct bnx2x *bp = params->bp; 6446 struct link_vars phy_vars[MAX_PHYS]; 6447 u8 port = params->port; 6448 u8 link_10g_plus, phy_index; 6449 u8 ext_phy_link_up = 0, cur_link_up; 6450 int rc = 0; 6451 u8 is_mi_int = 0; 6452 u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed; 6453 u8 active_external_phy = INT_PHY; 6454 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG; 6455 for (phy_index = INT_PHY; phy_index < params->num_phys; 6456 phy_index++) { 6457 phy_vars[phy_index].flow_ctrl = 0; 6458 phy_vars[phy_index].link_status = 0; 6459 phy_vars[phy_index].line_speed = 0; 6460 phy_vars[phy_index].duplex = DUPLEX_FULL; 6461 phy_vars[phy_index].phy_link_up = 0; 6462 phy_vars[phy_index].link_up = 0; 6463 phy_vars[phy_index].fault_detected = 0; 6464 /* different consideration, since vars holds inner state */ 6465 phy_vars[phy_index].eee_status = vars->eee_status; 6466 } 6467 6468 if (USES_WARPCORE(bp)) 6469 bnx2x_set_aer_mmd(params, ¶ms->phy[INT_PHY]); 6470 6471 DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n", 6472 port, (vars->phy_flags & PHY_XGXS_FLAG), 6473 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4)); 6474 6475 is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + 6476 port*0x18) > 0); 6477 DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n", 6478 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), 6479 is_mi_int, 6480 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c)); 6481 6482 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n", 6483 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), 6484 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); 6485 6486 /* Disable emac */ 6487 if (!CHIP_IS_E3(bp)) 6488 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); 6489 6490 /* Step 1: 6491 * Check external link change only for external phys, and apply 6492 * priority selection between them in case the link on both phys 6493 * is up. Note that instead of the common vars, a temporary 6494 * vars argument is used since each phy may have different link/ 6495 * speed/duplex result 6496 */ 6497 for (phy_index = EXT_PHY1; phy_index < params->num_phys; 6498 phy_index++) { 6499 struct bnx2x_phy *phy = ¶ms->phy[phy_index]; 6500 if (!phy->read_status) 6501 continue; 6502 /* Read link status and params of this ext phy */ 6503 cur_link_up = phy->read_status(phy, params, 6504 &phy_vars[phy_index]); 6505 if (cur_link_up) { 6506 DP(NETIF_MSG_LINK, "phy in index %d link is up\n", 6507 phy_index); 6508 } else { 6509 DP(NETIF_MSG_LINK, "phy in index %d link is down\n", 6510 phy_index); 6511 continue; 6512 } 6513 6514 if (!ext_phy_link_up) { 6515 ext_phy_link_up = 1; 6516 active_external_phy = phy_index; 6517 } else { 6518 switch (bnx2x_phy_selection(params)) { 6519 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT: 6520 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: 6521 /* In this option, the first PHY makes sure to pass the 6522 * traffic through itself only. 6523 * Its not clear how to reset the link on the second phy 6524 */ 6525 active_external_phy = EXT_PHY1; 6526 break; 6527 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: 6528 /* In this option, the first PHY makes sure to pass the 6529 * traffic through the second PHY. 6530 */ 6531 active_external_phy = EXT_PHY2; 6532 break; 6533 default: 6534 /* Link indication on both PHYs with the following cases 6535 * is invalid: 6536 * - FIRST_PHY means that second phy wasn't initialized, 6537 * hence its link is expected to be down 6538 * - SECOND_PHY means that first phy should not be able 6539 * to link up by itself (using configuration) 6540 * - DEFAULT should be overriden during initialiazation 6541 */ 6542 DP(NETIF_MSG_LINK, "Invalid link indication" 6543 "mpc=0x%x. DISABLING LINK !!!\n", 6544 params->multi_phy_config); 6545 ext_phy_link_up = 0; 6546 break; 6547 } 6548 } 6549 } 6550 prev_line_speed = vars->line_speed; 6551 /* Step 2: 6552 * Read the status of the internal phy. In case of 6553 * DIRECT_SINGLE_MEDIA board, this link is the external link, 6554 * otherwise this is the link between the 577xx and the first 6555 * external phy 6556 */ 6557 if (params->phy[INT_PHY].read_status) 6558 params->phy[INT_PHY].read_status( 6559 ¶ms->phy[INT_PHY], 6560 params, vars); 6561 /* The INT_PHY flow control reside in the vars. This include the 6562 * case where the speed or flow control are not set to AUTO. 6563 * Otherwise, the active external phy flow control result is set 6564 * to the vars. The ext_phy_line_speed is needed to check if the 6565 * speed is different between the internal phy and external phy. 6566 * This case may be result of intermediate link speed change. 6567 */ 6568 if (active_external_phy > INT_PHY) { 6569 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl; 6570 /* Link speed is taken from the XGXS. AN and FC result from 6571 * the external phy. 6572 */ 6573 vars->link_status |= phy_vars[active_external_phy].link_status; 6574 6575 /* if active_external_phy is first PHY and link is up - disable 6576 * disable TX on second external PHY 6577 */ 6578 if (active_external_phy == EXT_PHY1) { 6579 if (params->phy[EXT_PHY2].phy_specific_func) { 6580 DP(NETIF_MSG_LINK, 6581 "Disabling TX on EXT_PHY2\n"); 6582 params->phy[EXT_PHY2].phy_specific_func( 6583 ¶ms->phy[EXT_PHY2], 6584 params, DISABLE_TX); 6585 } 6586 } 6587 6588 ext_phy_line_speed = phy_vars[active_external_phy].line_speed; 6589 vars->duplex = phy_vars[active_external_phy].duplex; 6590 if (params->phy[active_external_phy].supported & 6591 SUPPORTED_FIBRE) 6592 vars->link_status |= LINK_STATUS_SERDES_LINK; 6593 else 6594 vars->link_status &= ~LINK_STATUS_SERDES_LINK; 6595 6596 vars->eee_status = phy_vars[active_external_phy].eee_status; 6597 6598 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n", 6599 active_external_phy); 6600 } 6601 6602 for (phy_index = EXT_PHY1; phy_index < params->num_phys; 6603 phy_index++) { 6604 if (params->phy[phy_index].flags & 6605 FLAGS_REARM_LATCH_SIGNAL) { 6606 bnx2x_rearm_latch_signal(bp, port, 6607 phy_index == 6608 active_external_phy); 6609 break; 6610 } 6611 } 6612 DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x," 6613 " ext_phy_line_speed = %d\n", vars->flow_ctrl, 6614 vars->link_status, ext_phy_line_speed); 6615 /* Upon link speed change set the NIG into drain mode. Comes to 6616 * deals with possible FIFO glitch due to clk change when speed 6617 * is decreased without link down indicator 6618 */ 6619 6620 if (vars->phy_link_up) { 6621 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up && 6622 (ext_phy_line_speed != vars->line_speed)) { 6623 DP(NETIF_MSG_LINK, "Internal link speed %d is" 6624 " different than the external" 6625 " link speed %d\n", vars->line_speed, 6626 ext_phy_line_speed); 6627 vars->phy_link_up = 0; 6628 } else if (prev_line_speed != vars->line_speed) { 6629 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 6630 0); 6631 usleep_range(1000, 2000); 6632 } 6633 } 6634 6635 /* Anything 10 and over uses the bmac */ 6636 link_10g_plus = (vars->line_speed >= SPEED_10000); 6637 6638 bnx2x_link_int_ack(params, vars, link_10g_plus); 6639 6640 /* In case external phy link is up, and internal link is down 6641 * (not initialized yet probably after link initialization, it 6642 * needs to be initialized. 6643 * Note that after link down-up as result of cable plug, the xgxs 6644 * link would probably become up again without the need 6645 * initialize it 6646 */ 6647 if (!(SINGLE_MEDIA_DIRECT(params))) { 6648 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d," 6649 " init_preceding = %d\n", ext_phy_link_up, 6650 vars->phy_link_up, 6651 params->phy[EXT_PHY1].flags & 6652 FLAGS_INIT_XGXS_FIRST); 6653 if (!(params->phy[EXT_PHY1].flags & 6654 FLAGS_INIT_XGXS_FIRST) 6655 && ext_phy_link_up && !vars->phy_link_up) { 6656 vars->line_speed = ext_phy_line_speed; 6657 if (vars->line_speed < SPEED_1000) 6658 vars->phy_flags |= PHY_SGMII_FLAG; 6659 else 6660 vars->phy_flags &= ~PHY_SGMII_FLAG; 6661 6662 if (params->phy[INT_PHY].config_init) 6663 params->phy[INT_PHY].config_init( 6664 ¶ms->phy[INT_PHY], params, 6665 vars); 6666 } 6667 } 6668 /* Link is up only if both local phy and external phy (in case of 6669 * non-direct board) are up and no fault detected on active PHY. 6670 */ 6671 vars->link_up = (vars->phy_link_up && 6672 (ext_phy_link_up || 6673 SINGLE_MEDIA_DIRECT(params)) && 6674 (phy_vars[active_external_phy].fault_detected == 0)); 6675 6676 /* Update the PFC configuration in case it was changed */ 6677 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) 6678 vars->link_status |= LINK_STATUS_PFC_ENABLED; 6679 else 6680 vars->link_status &= ~LINK_STATUS_PFC_ENABLED; 6681 6682 if (vars->link_up) 6683 rc = bnx2x_update_link_up(params, vars, link_10g_plus); 6684 else 6685 rc = bnx2x_update_link_down(params, vars); 6686 6687 /* Update MCP link status was changed */ 6688 if (params->feature_config_flags & FEATURE_CONFIG_BC_SUPPORTS_AFEX) 6689 bnx2x_fw_command(bp, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0); 6690 6691 return rc; 6692 } 6693 6694 /*****************************************************************************/ 6695 /* External Phy section */ 6696 /*****************************************************************************/ 6697 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port) 6698 { 6699 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 6700 MISC_REGISTERS_GPIO_OUTPUT_LOW, port); 6701 usleep_range(1000, 2000); 6702 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 6703 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port); 6704 } 6705 6706 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port, 6707 u32 spirom_ver, u32 ver_addr) 6708 { 6709 DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n", 6710 (u16)(spirom_ver>>16), (u16)spirom_ver, port); 6711 6712 if (ver_addr) 6713 REG_WR(bp, ver_addr, spirom_ver); 6714 } 6715 6716 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp, 6717 struct bnx2x_phy *phy, 6718 u8 port) 6719 { 6720 u16 fw_ver1, fw_ver2; 6721 6722 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 6723 MDIO_PMA_REG_ROM_VER1, &fw_ver1); 6724 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 6725 MDIO_PMA_REG_ROM_VER2, &fw_ver2); 6726 bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2), 6727 phy->ver_addr); 6728 } 6729 6730 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp, 6731 struct bnx2x_phy *phy, 6732 struct link_vars *vars) 6733 { 6734 u16 val; 6735 bnx2x_cl45_read(bp, phy, 6736 MDIO_AN_DEVAD, 6737 MDIO_AN_REG_STATUS, &val); 6738 bnx2x_cl45_read(bp, phy, 6739 MDIO_AN_DEVAD, 6740 MDIO_AN_REG_STATUS, &val); 6741 if (val & (1<<5)) 6742 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 6743 if ((val & (1<<0)) == 0) 6744 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED; 6745 } 6746 6747 /******************************************************************/ 6748 /* common BCM8073/BCM8727 PHY SECTION */ 6749 /******************************************************************/ 6750 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy, 6751 struct link_params *params, 6752 struct link_vars *vars) 6753 { 6754 struct bnx2x *bp = params->bp; 6755 if (phy->req_line_speed == SPEED_10 || 6756 phy->req_line_speed == SPEED_100) { 6757 vars->flow_ctrl = phy->req_flow_ctrl; 6758 return; 6759 } 6760 6761 if (bnx2x_ext_phy_resolve_fc(phy, params, vars) && 6762 (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) { 6763 u16 pause_result; 6764 u16 ld_pause; /* local */ 6765 u16 lp_pause; /* link partner */ 6766 bnx2x_cl45_read(bp, phy, 6767 MDIO_AN_DEVAD, 6768 MDIO_AN_REG_CL37_FC_LD, &ld_pause); 6769 6770 bnx2x_cl45_read(bp, phy, 6771 MDIO_AN_DEVAD, 6772 MDIO_AN_REG_CL37_FC_LP, &lp_pause); 6773 pause_result = (ld_pause & 6774 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5; 6775 pause_result |= (lp_pause & 6776 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7; 6777 6778 bnx2x_pause_resolve(vars, pause_result); 6779 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n", 6780 pause_result); 6781 } 6782 } 6783 static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp, 6784 struct bnx2x_phy *phy, 6785 u8 port) 6786 { 6787 u32 count = 0; 6788 u16 fw_ver1, fw_msgout; 6789 int rc = 0; 6790 6791 /* Boot port from external ROM */ 6792 /* EDC grst */ 6793 bnx2x_cl45_write(bp, phy, 6794 MDIO_PMA_DEVAD, 6795 MDIO_PMA_REG_GEN_CTRL, 6796 0x0001); 6797 6798 /* Ucode reboot and rst */ 6799 bnx2x_cl45_write(bp, phy, 6800 MDIO_PMA_DEVAD, 6801 MDIO_PMA_REG_GEN_CTRL, 6802 0x008c); 6803 6804 bnx2x_cl45_write(bp, phy, 6805 MDIO_PMA_DEVAD, 6806 MDIO_PMA_REG_MISC_CTRL1, 0x0001); 6807 6808 /* Reset internal microprocessor */ 6809 bnx2x_cl45_write(bp, phy, 6810 MDIO_PMA_DEVAD, 6811 MDIO_PMA_REG_GEN_CTRL, 6812 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); 6813 6814 /* Release srst bit */ 6815 bnx2x_cl45_write(bp, phy, 6816 MDIO_PMA_DEVAD, 6817 MDIO_PMA_REG_GEN_CTRL, 6818 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); 6819 6820 /* Delay 100ms per the PHY specifications */ 6821 msleep(100); 6822 6823 /* 8073 sometimes taking longer to download */ 6824 do { 6825 count++; 6826 if (count > 300) { 6827 DP(NETIF_MSG_LINK, 6828 "bnx2x_8073_8727_external_rom_boot port %x:" 6829 "Download failed. fw version = 0x%x\n", 6830 port, fw_ver1); 6831 rc = -EINVAL; 6832 break; 6833 } 6834 6835 bnx2x_cl45_read(bp, phy, 6836 MDIO_PMA_DEVAD, 6837 MDIO_PMA_REG_ROM_VER1, &fw_ver1); 6838 bnx2x_cl45_read(bp, phy, 6839 MDIO_PMA_DEVAD, 6840 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout); 6841 6842 usleep_range(1000, 2000); 6843 } while (fw_ver1 == 0 || fw_ver1 == 0x4321 || 6844 ((fw_msgout & 0xff) != 0x03 && (phy->type == 6845 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073))); 6846 6847 /* Clear ser_boot_ctl bit */ 6848 bnx2x_cl45_write(bp, phy, 6849 MDIO_PMA_DEVAD, 6850 MDIO_PMA_REG_MISC_CTRL1, 0x0000); 6851 bnx2x_save_bcm_spirom_ver(bp, phy, port); 6852 6853 DP(NETIF_MSG_LINK, 6854 "bnx2x_8073_8727_external_rom_boot port %x:" 6855 "Download complete. fw version = 0x%x\n", 6856 port, fw_ver1); 6857 6858 return rc; 6859 } 6860 6861 /******************************************************************/ 6862 /* BCM8073 PHY SECTION */ 6863 /******************************************************************/ 6864 static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy) 6865 { 6866 /* This is only required for 8073A1, version 102 only */ 6867 u16 val; 6868 6869 /* Read 8073 HW revision*/ 6870 bnx2x_cl45_read(bp, phy, 6871 MDIO_PMA_DEVAD, 6872 MDIO_PMA_REG_8073_CHIP_REV, &val); 6873 6874 if (val != 1) { 6875 /* No need to workaround in 8073 A1 */ 6876 return 0; 6877 } 6878 6879 bnx2x_cl45_read(bp, phy, 6880 MDIO_PMA_DEVAD, 6881 MDIO_PMA_REG_ROM_VER2, &val); 6882 6883 /* SNR should be applied only for version 0x102 */ 6884 if (val != 0x102) 6885 return 0; 6886 6887 return 1; 6888 } 6889 6890 static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy) 6891 { 6892 u16 val, cnt, cnt1 ; 6893 6894 bnx2x_cl45_read(bp, phy, 6895 MDIO_PMA_DEVAD, 6896 MDIO_PMA_REG_8073_CHIP_REV, &val); 6897 6898 if (val > 0) { 6899 /* No need to workaround in 8073 A1 */ 6900 return 0; 6901 } 6902 /* XAUI workaround in 8073 A0: */ 6903 6904 /* After loading the boot ROM and restarting Autoneg, poll 6905 * Dev1, Reg $C820: 6906 */ 6907 6908 for (cnt = 0; cnt < 1000; cnt++) { 6909 bnx2x_cl45_read(bp, phy, 6910 MDIO_PMA_DEVAD, 6911 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, 6912 &val); 6913 /* If bit [14] = 0 or bit [13] = 0, continue on with 6914 * system initialization (XAUI work-around not required, as 6915 * these bits indicate 2.5G or 1G link up). 6916 */ 6917 if (!(val & (1<<14)) || !(val & (1<<13))) { 6918 DP(NETIF_MSG_LINK, "XAUI work-around not required\n"); 6919 return 0; 6920 } else if (!(val & (1<<15))) { 6921 DP(NETIF_MSG_LINK, "bit 15 went off\n"); 6922 /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's 6923 * MSB (bit15) goes to 1 (indicating that the XAUI 6924 * workaround has completed), then continue on with 6925 * system initialization. 6926 */ 6927 for (cnt1 = 0; cnt1 < 1000; cnt1++) { 6928 bnx2x_cl45_read(bp, phy, 6929 MDIO_PMA_DEVAD, 6930 MDIO_PMA_REG_8073_XAUI_WA, &val); 6931 if (val & (1<<15)) { 6932 DP(NETIF_MSG_LINK, 6933 "XAUI workaround has completed\n"); 6934 return 0; 6935 } 6936 usleep_range(3000, 6000); 6937 } 6938 break; 6939 } 6940 usleep_range(3000, 6000); 6941 } 6942 DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n"); 6943 return -EINVAL; 6944 } 6945 6946 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy) 6947 { 6948 /* Force KR or KX */ 6949 bnx2x_cl45_write(bp, phy, 6950 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040); 6951 bnx2x_cl45_write(bp, phy, 6952 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b); 6953 bnx2x_cl45_write(bp, phy, 6954 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000); 6955 bnx2x_cl45_write(bp, phy, 6956 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000); 6957 } 6958 6959 static void bnx2x_8073_set_pause_cl37(struct link_params *params, 6960 struct bnx2x_phy *phy, 6961 struct link_vars *vars) 6962 { 6963 u16 cl37_val; 6964 struct bnx2x *bp = params->bp; 6965 bnx2x_cl45_read(bp, phy, 6966 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val); 6967 6968 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; 6969 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ 6970 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); 6971 if ((vars->ieee_fc & 6972 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) == 6973 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) { 6974 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC; 6975 } 6976 if ((vars->ieee_fc & 6977 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == 6978 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) { 6979 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; 6980 } 6981 if ((vars->ieee_fc & 6982 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == 6983 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) { 6984 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; 6985 } 6986 DP(NETIF_MSG_LINK, 6987 "Ext phy AN advertize cl37 0x%x\n", cl37_val); 6988 6989 bnx2x_cl45_write(bp, phy, 6990 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val); 6991 msleep(500); 6992 } 6993 6994 static void bnx2x_8073_specific_func(struct bnx2x_phy *phy, 6995 struct link_params *params, 6996 u32 action) 6997 { 6998 struct bnx2x *bp = params->bp; 6999 switch (action) { 7000 case PHY_INIT: 7001 /* Enable LASI */ 7002 bnx2x_cl45_write(bp, phy, 7003 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2)); 7004 bnx2x_cl45_write(bp, phy, 7005 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004); 7006 break; 7007 } 7008 } 7009 7010 static int bnx2x_8073_config_init(struct bnx2x_phy *phy, 7011 struct link_params *params, 7012 struct link_vars *vars) 7013 { 7014 struct bnx2x *bp = params->bp; 7015 u16 val = 0, tmp1; 7016 u8 gpio_port; 7017 DP(NETIF_MSG_LINK, "Init 8073\n"); 7018 7019 if (CHIP_IS_E2(bp)) 7020 gpio_port = BP_PATH(bp); 7021 else 7022 gpio_port = params->port; 7023 /* Restore normal power mode*/ 7024 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 7025 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port); 7026 7027 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 7028 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port); 7029 7030 bnx2x_8073_specific_func(phy, params, PHY_INIT); 7031 bnx2x_8073_set_pause_cl37(params, phy, vars); 7032 7033 bnx2x_cl45_read(bp, phy, 7034 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1); 7035 7036 bnx2x_cl45_read(bp, phy, 7037 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1); 7038 7039 DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1); 7040 7041 /* Swap polarity if required - Must be done only in non-1G mode */ 7042 if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) { 7043 /* Configure the 8073 to swap _P and _N of the KR lines */ 7044 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n"); 7045 /* 10G Rx/Tx and 1G Tx signal polarity swap */ 7046 bnx2x_cl45_read(bp, phy, 7047 MDIO_PMA_DEVAD, 7048 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val); 7049 bnx2x_cl45_write(bp, phy, 7050 MDIO_PMA_DEVAD, 7051 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, 7052 (val | (3<<9))); 7053 } 7054 7055 7056 /* Enable CL37 BAM */ 7057 if (REG_RD(bp, params->shmem_base + 7058 offsetof(struct shmem_region, dev_info. 7059 port_hw_config[params->port].default_cfg)) & 7060 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) { 7061 7062 bnx2x_cl45_read(bp, phy, 7063 MDIO_AN_DEVAD, 7064 MDIO_AN_REG_8073_BAM, &val); 7065 bnx2x_cl45_write(bp, phy, 7066 MDIO_AN_DEVAD, 7067 MDIO_AN_REG_8073_BAM, val | 1); 7068 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n"); 7069 } 7070 if (params->loopback_mode == LOOPBACK_EXT) { 7071 bnx2x_807x_force_10G(bp, phy); 7072 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n"); 7073 return 0; 7074 } else { 7075 bnx2x_cl45_write(bp, phy, 7076 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002); 7077 } 7078 if (phy->req_line_speed != SPEED_AUTO_NEG) { 7079 if (phy->req_line_speed == SPEED_10000) { 7080 val = (1<<7); 7081 } else if (phy->req_line_speed == SPEED_2500) { 7082 val = (1<<5); 7083 /* Note that 2.5G works only when used with 1G 7084 * advertisement 7085 */ 7086 } else 7087 val = (1<<5); 7088 } else { 7089 val = 0; 7090 if (phy->speed_cap_mask & 7091 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 7092 val |= (1<<7); 7093 7094 /* Note that 2.5G works only when used with 1G advertisement */ 7095 if (phy->speed_cap_mask & 7096 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G | 7097 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) 7098 val |= (1<<5); 7099 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val); 7100 } 7101 7102 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val); 7103 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1); 7104 7105 if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) && 7106 (phy->req_line_speed == SPEED_AUTO_NEG)) || 7107 (phy->req_line_speed == SPEED_2500)) { 7108 u16 phy_ver; 7109 /* Allow 2.5G for A1 and above */ 7110 bnx2x_cl45_read(bp, phy, 7111 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, 7112 &phy_ver); 7113 DP(NETIF_MSG_LINK, "Add 2.5G\n"); 7114 if (phy_ver > 0) 7115 tmp1 |= 1; 7116 else 7117 tmp1 &= 0xfffe; 7118 } else { 7119 DP(NETIF_MSG_LINK, "Disable 2.5G\n"); 7120 tmp1 &= 0xfffe; 7121 } 7122 7123 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1); 7124 /* Add support for CL37 (passive mode) II */ 7125 7126 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1); 7127 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 7128 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ? 7129 0x20 : 0x40))); 7130 7131 /* Add support for CL37 (passive mode) III */ 7132 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); 7133 7134 /* The SNR will improve about 2db by changing BW and FEE main 7135 * tap. Rest commands are executed after link is up 7136 * Change FFE main cursor to 5 in EDC register 7137 */ 7138 if (bnx2x_8073_is_snr_needed(bp, phy)) 7139 bnx2x_cl45_write(bp, phy, 7140 MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN, 7141 0xFB0C); 7142 7143 /* Enable FEC (Forware Error Correction) Request in the AN */ 7144 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1); 7145 tmp1 |= (1<<15); 7146 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1); 7147 7148 bnx2x_ext_phy_set_pause(params, phy, vars); 7149 7150 /* Restart autoneg */ 7151 msleep(500); 7152 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); 7153 DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n", 7154 ((val & (1<<5)) > 0), ((val & (1<<7)) > 0)); 7155 return 0; 7156 } 7157 7158 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy, 7159 struct link_params *params, 7160 struct link_vars *vars) 7161 { 7162 struct bnx2x *bp = params->bp; 7163 u8 link_up = 0; 7164 u16 val1, val2; 7165 u16 link_status = 0; 7166 u16 an1000_status = 0; 7167 7168 bnx2x_cl45_read(bp, phy, 7169 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); 7170 7171 DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1); 7172 7173 /* Clear the interrupt LASI status register */ 7174 bnx2x_cl45_read(bp, phy, 7175 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2); 7176 bnx2x_cl45_read(bp, phy, 7177 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1); 7178 DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1); 7179 /* Clear MSG-OUT */ 7180 bnx2x_cl45_read(bp, phy, 7181 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1); 7182 7183 /* Check the LASI */ 7184 bnx2x_cl45_read(bp, phy, 7185 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2); 7186 7187 DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2); 7188 7189 /* Check the link status */ 7190 bnx2x_cl45_read(bp, phy, 7191 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2); 7192 DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2); 7193 7194 bnx2x_cl45_read(bp, phy, 7195 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); 7196 bnx2x_cl45_read(bp, phy, 7197 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); 7198 link_up = ((val1 & 4) == 4); 7199 DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1); 7200 7201 if (link_up && 7202 ((phy->req_line_speed != SPEED_10000))) { 7203 if (bnx2x_8073_xaui_wa(bp, phy) != 0) 7204 return 0; 7205 } 7206 bnx2x_cl45_read(bp, phy, 7207 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status); 7208 bnx2x_cl45_read(bp, phy, 7209 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status); 7210 7211 /* Check the link status on 1.1.2 */ 7212 bnx2x_cl45_read(bp, phy, 7213 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); 7214 bnx2x_cl45_read(bp, phy, 7215 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); 7216 DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x," 7217 "an_link_status=0x%x\n", val2, val1, an1000_status); 7218 7219 link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1))); 7220 if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) { 7221 /* The SNR will improve about 2dbby changing the BW and FEE main 7222 * tap. The 1st write to change FFE main tap is set before 7223 * restart AN. Change PLL Bandwidth in EDC register 7224 */ 7225 bnx2x_cl45_write(bp, phy, 7226 MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH, 7227 0x26BC); 7228 7229 /* Change CDR Bandwidth in EDC register */ 7230 bnx2x_cl45_write(bp, phy, 7231 MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH, 7232 0x0333); 7233 } 7234 bnx2x_cl45_read(bp, phy, 7235 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS, 7236 &link_status); 7237 7238 /* Bits 0..2 --> speed detected, bits 13..15--> link is down */ 7239 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) { 7240 link_up = 1; 7241 vars->line_speed = SPEED_10000; 7242 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n", 7243 params->port); 7244 } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) { 7245 link_up = 1; 7246 vars->line_speed = SPEED_2500; 7247 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n", 7248 params->port); 7249 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) { 7250 link_up = 1; 7251 vars->line_speed = SPEED_1000; 7252 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n", 7253 params->port); 7254 } else { 7255 link_up = 0; 7256 DP(NETIF_MSG_LINK, "port %x: External link is down\n", 7257 params->port); 7258 } 7259 7260 if (link_up) { 7261 /* Swap polarity if required */ 7262 if (params->lane_config & 7263 PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) { 7264 /* Configure the 8073 to swap P and N of the KR lines */ 7265 bnx2x_cl45_read(bp, phy, 7266 MDIO_XS_DEVAD, 7267 MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1); 7268 /* Set bit 3 to invert Rx in 1G mode and clear this bit 7269 * when it`s in 10G mode. 7270 */ 7271 if (vars->line_speed == SPEED_1000) { 7272 DP(NETIF_MSG_LINK, "Swapping 1G polarity for" 7273 "the 8073\n"); 7274 val1 |= (1<<3); 7275 } else 7276 val1 &= ~(1<<3); 7277 7278 bnx2x_cl45_write(bp, phy, 7279 MDIO_XS_DEVAD, 7280 MDIO_XS_REG_8073_RX_CTRL_PCIE, 7281 val1); 7282 } 7283 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); 7284 bnx2x_8073_resolve_fc(phy, params, vars); 7285 vars->duplex = DUPLEX_FULL; 7286 } 7287 7288 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 7289 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 7290 MDIO_AN_REG_LP_AUTO_NEG2, &val1); 7291 7292 if (val1 & (1<<5)) 7293 vars->link_status |= 7294 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 7295 if (val1 & (1<<7)) 7296 vars->link_status |= 7297 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 7298 } 7299 7300 return link_up; 7301 } 7302 7303 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy, 7304 struct link_params *params) 7305 { 7306 struct bnx2x *bp = params->bp; 7307 u8 gpio_port; 7308 if (CHIP_IS_E2(bp)) 7309 gpio_port = BP_PATH(bp); 7310 else 7311 gpio_port = params->port; 7312 DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n", 7313 gpio_port); 7314 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 7315 MISC_REGISTERS_GPIO_OUTPUT_LOW, 7316 gpio_port); 7317 } 7318 7319 /******************************************************************/ 7320 /* BCM8705 PHY SECTION */ 7321 /******************************************************************/ 7322 static int bnx2x_8705_config_init(struct bnx2x_phy *phy, 7323 struct link_params *params, 7324 struct link_vars *vars) 7325 { 7326 struct bnx2x *bp = params->bp; 7327 DP(NETIF_MSG_LINK, "init 8705\n"); 7328 /* Restore normal power mode*/ 7329 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 7330 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); 7331 /* HW reset */ 7332 bnx2x_ext_phy_hw_reset(bp, params->port); 7333 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); 7334 bnx2x_wait_reset_complete(bp, phy, params); 7335 7336 bnx2x_cl45_write(bp, phy, 7337 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288); 7338 bnx2x_cl45_write(bp, phy, 7339 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf); 7340 bnx2x_cl45_write(bp, phy, 7341 MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100); 7342 bnx2x_cl45_write(bp, phy, 7343 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1); 7344 /* BCM8705 doesn't have microcode, hence the 0 */ 7345 bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0); 7346 return 0; 7347 } 7348 7349 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy, 7350 struct link_params *params, 7351 struct link_vars *vars) 7352 { 7353 u8 link_up = 0; 7354 u16 val1, rx_sd; 7355 struct bnx2x *bp = params->bp; 7356 DP(NETIF_MSG_LINK, "read status 8705\n"); 7357 bnx2x_cl45_read(bp, phy, 7358 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1); 7359 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1); 7360 7361 bnx2x_cl45_read(bp, phy, 7362 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1); 7363 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1); 7364 7365 bnx2x_cl45_read(bp, phy, 7366 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd); 7367 7368 bnx2x_cl45_read(bp, phy, 7369 MDIO_PMA_DEVAD, 0xc809, &val1); 7370 bnx2x_cl45_read(bp, phy, 7371 MDIO_PMA_DEVAD, 0xc809, &val1); 7372 7373 DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1); 7374 link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0)); 7375 if (link_up) { 7376 vars->line_speed = SPEED_10000; 7377 bnx2x_ext_phy_resolve_fc(phy, params, vars); 7378 } 7379 return link_up; 7380 } 7381 7382 /******************************************************************/ 7383 /* SFP+ module Section */ 7384 /******************************************************************/ 7385 static void bnx2x_set_disable_pmd_transmit(struct link_params *params, 7386 struct bnx2x_phy *phy, 7387 u8 pmd_dis) 7388 { 7389 struct bnx2x *bp = params->bp; 7390 /* Disable transmitter only for bootcodes which can enable it afterwards 7391 * (for D3 link) 7392 */ 7393 if (pmd_dis) { 7394 if (params->feature_config_flags & 7395 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED) 7396 DP(NETIF_MSG_LINK, "Disabling PMD transmitter\n"); 7397 else { 7398 DP(NETIF_MSG_LINK, "NOT disabling PMD transmitter\n"); 7399 return; 7400 } 7401 } else 7402 DP(NETIF_MSG_LINK, "Enabling PMD transmitter\n"); 7403 bnx2x_cl45_write(bp, phy, 7404 MDIO_PMA_DEVAD, 7405 MDIO_PMA_REG_TX_DISABLE, pmd_dis); 7406 } 7407 7408 static u8 bnx2x_get_gpio_port(struct link_params *params) 7409 { 7410 u8 gpio_port; 7411 u32 swap_val, swap_override; 7412 struct bnx2x *bp = params->bp; 7413 if (CHIP_IS_E2(bp)) 7414 gpio_port = BP_PATH(bp); 7415 else 7416 gpio_port = params->port; 7417 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); 7418 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); 7419 return gpio_port ^ (swap_val && swap_override); 7420 } 7421 7422 static void bnx2x_sfp_e1e2_set_transmitter(struct link_params *params, 7423 struct bnx2x_phy *phy, 7424 u8 tx_en) 7425 { 7426 u16 val; 7427 u8 port = params->port; 7428 struct bnx2x *bp = params->bp; 7429 u32 tx_en_mode; 7430 7431 /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/ 7432 tx_en_mode = REG_RD(bp, params->shmem_base + 7433 offsetof(struct shmem_region, 7434 dev_info.port_hw_config[port].sfp_ctrl)) & 7435 PORT_HW_CFG_TX_LASER_MASK; 7436 DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x " 7437 "mode = %x\n", tx_en, port, tx_en_mode); 7438 switch (tx_en_mode) { 7439 case PORT_HW_CFG_TX_LASER_MDIO: 7440 7441 bnx2x_cl45_read(bp, phy, 7442 MDIO_PMA_DEVAD, 7443 MDIO_PMA_REG_PHY_IDENTIFIER, 7444 &val); 7445 7446 if (tx_en) 7447 val &= ~(1<<15); 7448 else 7449 val |= (1<<15); 7450 7451 bnx2x_cl45_write(bp, phy, 7452 MDIO_PMA_DEVAD, 7453 MDIO_PMA_REG_PHY_IDENTIFIER, 7454 val); 7455 break; 7456 case PORT_HW_CFG_TX_LASER_GPIO0: 7457 case PORT_HW_CFG_TX_LASER_GPIO1: 7458 case PORT_HW_CFG_TX_LASER_GPIO2: 7459 case PORT_HW_CFG_TX_LASER_GPIO3: 7460 { 7461 u16 gpio_pin; 7462 u8 gpio_port, gpio_mode; 7463 if (tx_en) 7464 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH; 7465 else 7466 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW; 7467 7468 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0; 7469 gpio_port = bnx2x_get_gpio_port(params); 7470 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port); 7471 break; 7472 } 7473 default: 7474 DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode); 7475 break; 7476 } 7477 } 7478 7479 static void bnx2x_sfp_set_transmitter(struct link_params *params, 7480 struct bnx2x_phy *phy, 7481 u8 tx_en) 7482 { 7483 struct bnx2x *bp = params->bp; 7484 DP(NETIF_MSG_LINK, "Setting SFP+ transmitter to %d\n", tx_en); 7485 if (CHIP_IS_E3(bp)) 7486 bnx2x_sfp_e3_set_transmitter(params, phy, tx_en); 7487 else 7488 bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en); 7489 } 7490 7491 static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy, 7492 struct link_params *params, 7493 u16 addr, u8 byte_cnt, u8 *o_buf) 7494 { 7495 struct bnx2x *bp = params->bp; 7496 u16 val = 0; 7497 u16 i; 7498 if (byte_cnt > SFP_EEPROM_PAGE_SIZE) { 7499 DP(NETIF_MSG_LINK, 7500 "Reading from eeprom is limited to 0xf\n"); 7501 return -EINVAL; 7502 } 7503 /* Set the read command byte count */ 7504 bnx2x_cl45_write(bp, phy, 7505 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT, 7506 (byte_cnt | 0xa000)); 7507 7508 /* Set the read command address */ 7509 bnx2x_cl45_write(bp, phy, 7510 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, 7511 addr); 7512 7513 /* Activate read command */ 7514 bnx2x_cl45_write(bp, phy, 7515 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 7516 0x2c0f); 7517 7518 /* Wait up to 500us for command complete status */ 7519 for (i = 0; i < 100; i++) { 7520 bnx2x_cl45_read(bp, phy, 7521 MDIO_PMA_DEVAD, 7522 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 7523 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 7524 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) 7525 break; 7526 udelay(5); 7527 } 7528 7529 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) != 7530 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) { 7531 DP(NETIF_MSG_LINK, 7532 "Got bad status 0x%x when reading from SFP+ EEPROM\n", 7533 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK)); 7534 return -EINVAL; 7535 } 7536 7537 /* Read the buffer */ 7538 for (i = 0; i < byte_cnt; i++) { 7539 bnx2x_cl45_read(bp, phy, 7540 MDIO_PMA_DEVAD, 7541 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val); 7542 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK); 7543 } 7544 7545 for (i = 0; i < 100; i++) { 7546 bnx2x_cl45_read(bp, phy, 7547 MDIO_PMA_DEVAD, 7548 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 7549 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 7550 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE) 7551 return 0; 7552 usleep_range(1000, 2000); 7553 } 7554 return -EINVAL; 7555 } 7556 7557 static void bnx2x_warpcore_power_module(struct link_params *params, 7558 struct bnx2x_phy *phy, 7559 u8 power) 7560 { 7561 u32 pin_cfg; 7562 struct bnx2x *bp = params->bp; 7563 7564 pin_cfg = (REG_RD(bp, params->shmem_base + 7565 offsetof(struct shmem_region, 7566 dev_info.port_hw_config[params->port].e3_sfp_ctrl)) & 7567 PORT_HW_CFG_E3_PWR_DIS_MASK) >> 7568 PORT_HW_CFG_E3_PWR_DIS_SHIFT; 7569 7570 if (pin_cfg == PIN_CFG_NA) 7571 return; 7572 DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n", 7573 power, pin_cfg); 7574 /* Low ==> corresponding SFP+ module is powered 7575 * high ==> the SFP+ module is powered down 7576 */ 7577 bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1); 7578 } 7579 static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy, 7580 struct link_params *params, 7581 u16 addr, u8 byte_cnt, 7582 u8 *o_buf) 7583 { 7584 int rc = 0; 7585 u8 i, j = 0, cnt = 0; 7586 u32 data_array[4]; 7587 u16 addr32; 7588 struct bnx2x *bp = params->bp; 7589 7590 if (byte_cnt > SFP_EEPROM_PAGE_SIZE) { 7591 DP(NETIF_MSG_LINK, 7592 "Reading from eeprom is limited to 16 bytes\n"); 7593 return -EINVAL; 7594 } 7595 7596 /* 4 byte aligned address */ 7597 addr32 = addr & (~0x3); 7598 do { 7599 if (cnt == I2C_WA_PWR_ITER) { 7600 bnx2x_warpcore_power_module(params, phy, 0); 7601 /* Note that 100us are not enough here */ 7602 usleep_range(1000,1000); 7603 bnx2x_warpcore_power_module(params, phy, 1); 7604 } 7605 rc = bnx2x_bsc_read(params, phy, 0xa0, addr32, 0, byte_cnt, 7606 data_array); 7607 } while ((rc != 0) && (++cnt < I2C_WA_RETRY_CNT)); 7608 7609 if (rc == 0) { 7610 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) { 7611 o_buf[j] = *((u8 *)data_array + i); 7612 j++; 7613 } 7614 } 7615 7616 return rc; 7617 } 7618 7619 static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy, 7620 struct link_params *params, 7621 u16 addr, u8 byte_cnt, u8 *o_buf) 7622 { 7623 struct bnx2x *bp = params->bp; 7624 u16 val, i; 7625 7626 if (byte_cnt > SFP_EEPROM_PAGE_SIZE) { 7627 DP(NETIF_MSG_LINK, 7628 "Reading from eeprom is limited to 0xf\n"); 7629 return -EINVAL; 7630 } 7631 7632 /* Need to read from 1.8000 to clear it */ 7633 bnx2x_cl45_read(bp, phy, 7634 MDIO_PMA_DEVAD, 7635 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 7636 &val); 7637 7638 /* Set the read command byte count */ 7639 bnx2x_cl45_write(bp, phy, 7640 MDIO_PMA_DEVAD, 7641 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT, 7642 ((byte_cnt < 2) ? 2 : byte_cnt)); 7643 7644 /* Set the read command address */ 7645 bnx2x_cl45_write(bp, phy, 7646 MDIO_PMA_DEVAD, 7647 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, 7648 addr); 7649 /* Set the destination address */ 7650 bnx2x_cl45_write(bp, phy, 7651 MDIO_PMA_DEVAD, 7652 0x8004, 7653 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF); 7654 7655 /* Activate read command */ 7656 bnx2x_cl45_write(bp, phy, 7657 MDIO_PMA_DEVAD, 7658 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 7659 0x8002); 7660 /* Wait appropriate time for two-wire command to finish before 7661 * polling the status register 7662 */ 7663 usleep_range(1000, 2000); 7664 7665 /* Wait up to 500us for command complete status */ 7666 for (i = 0; i < 100; i++) { 7667 bnx2x_cl45_read(bp, phy, 7668 MDIO_PMA_DEVAD, 7669 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 7670 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 7671 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) 7672 break; 7673 udelay(5); 7674 } 7675 7676 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) != 7677 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) { 7678 DP(NETIF_MSG_LINK, 7679 "Got bad status 0x%x when reading from SFP+ EEPROM\n", 7680 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK)); 7681 return -EFAULT; 7682 } 7683 7684 /* Read the buffer */ 7685 for (i = 0; i < byte_cnt; i++) { 7686 bnx2x_cl45_read(bp, phy, 7687 MDIO_PMA_DEVAD, 7688 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val); 7689 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK); 7690 } 7691 7692 for (i = 0; i < 100; i++) { 7693 bnx2x_cl45_read(bp, phy, 7694 MDIO_PMA_DEVAD, 7695 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 7696 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 7697 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE) 7698 return 0; 7699 usleep_range(1000, 2000); 7700 } 7701 7702 return -EINVAL; 7703 } 7704 7705 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy, 7706 struct link_params *params, u16 addr, 7707 u8 byte_cnt, u8 *o_buf) 7708 { 7709 int rc = -EOPNOTSUPP; 7710 switch (phy->type) { 7711 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 7712 rc = bnx2x_8726_read_sfp_module_eeprom(phy, params, addr, 7713 byte_cnt, o_buf); 7714 break; 7715 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 7716 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 7717 rc = bnx2x_8727_read_sfp_module_eeprom(phy, params, addr, 7718 byte_cnt, o_buf); 7719 break; 7720 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: 7721 rc = bnx2x_warpcore_read_sfp_module_eeprom(phy, params, addr, 7722 byte_cnt, o_buf); 7723 break; 7724 } 7725 return rc; 7726 } 7727 7728 static int bnx2x_get_edc_mode(struct bnx2x_phy *phy, 7729 struct link_params *params, 7730 u16 *edc_mode) 7731 { 7732 struct bnx2x *bp = params->bp; 7733 u32 sync_offset = 0, phy_idx, media_types; 7734 u8 val[2], check_limiting_mode = 0; 7735 *edc_mode = EDC_MODE_LIMITING; 7736 7737 phy->media_type = ETH_PHY_UNSPECIFIED; 7738 /* First check for copper cable */ 7739 if (bnx2x_read_sfp_module_eeprom(phy, 7740 params, 7741 SFP_EEPROM_CON_TYPE_ADDR, 7742 2, 7743 (u8 *)val) != 0) { 7744 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n"); 7745 return -EINVAL; 7746 } 7747 7748 switch (val[0]) { 7749 case SFP_EEPROM_CON_TYPE_VAL_COPPER: 7750 { 7751 u8 copper_module_type; 7752 phy->media_type = ETH_PHY_DA_TWINAX; 7753 /* Check if its active cable (includes SFP+ module) 7754 * of passive cable 7755 */ 7756 if (bnx2x_read_sfp_module_eeprom(phy, 7757 params, 7758 SFP_EEPROM_FC_TX_TECH_ADDR, 7759 1, 7760 &copper_module_type) != 0) { 7761 DP(NETIF_MSG_LINK, 7762 "Failed to read copper-cable-type" 7763 " from SFP+ EEPROM\n"); 7764 return -EINVAL; 7765 } 7766 7767 if (copper_module_type & 7768 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) { 7769 DP(NETIF_MSG_LINK, "Active Copper cable detected\n"); 7770 check_limiting_mode = 1; 7771 } else if (copper_module_type & 7772 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) { 7773 DP(NETIF_MSG_LINK, 7774 "Passive Copper cable detected\n"); 7775 *edc_mode = 7776 EDC_MODE_PASSIVE_DAC; 7777 } else { 7778 DP(NETIF_MSG_LINK, 7779 "Unknown copper-cable-type 0x%x !!!\n", 7780 copper_module_type); 7781 return -EINVAL; 7782 } 7783 break; 7784 } 7785 case SFP_EEPROM_CON_TYPE_VAL_LC: 7786 check_limiting_mode = 1; 7787 if ((val[1] & (SFP_EEPROM_COMP_CODE_SR_MASK | 7788 SFP_EEPROM_COMP_CODE_LR_MASK | 7789 SFP_EEPROM_COMP_CODE_LRM_MASK)) == 0) { 7790 DP(NETIF_MSG_LINK, "1G Optic module detected\n"); 7791 phy->media_type = ETH_PHY_SFP_1G_FIBER; 7792 phy->req_line_speed = SPEED_1000; 7793 } else { 7794 int idx, cfg_idx = 0; 7795 DP(NETIF_MSG_LINK, "10G Optic module detected\n"); 7796 for (idx = INT_PHY; idx < MAX_PHYS; idx++) { 7797 if (params->phy[idx].type == phy->type) { 7798 cfg_idx = LINK_CONFIG_IDX(idx); 7799 break; 7800 } 7801 } 7802 phy->media_type = ETH_PHY_SFPP_10G_FIBER; 7803 phy->req_line_speed = params->req_line_speed[cfg_idx]; 7804 } 7805 break; 7806 default: 7807 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n", 7808 val[0]); 7809 return -EINVAL; 7810 } 7811 sync_offset = params->shmem_base + 7812 offsetof(struct shmem_region, 7813 dev_info.port_hw_config[params->port].media_type); 7814 media_types = REG_RD(bp, sync_offset); 7815 /* Update media type for non-PMF sync */ 7816 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) { 7817 if (&(params->phy[phy_idx]) == phy) { 7818 media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK << 7819 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx)); 7820 media_types |= ((phy->media_type & 7821 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) << 7822 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx)); 7823 break; 7824 } 7825 } 7826 REG_WR(bp, sync_offset, media_types); 7827 if (check_limiting_mode) { 7828 u8 options[SFP_EEPROM_OPTIONS_SIZE]; 7829 if (bnx2x_read_sfp_module_eeprom(phy, 7830 params, 7831 SFP_EEPROM_OPTIONS_ADDR, 7832 SFP_EEPROM_OPTIONS_SIZE, 7833 options) != 0) { 7834 DP(NETIF_MSG_LINK, 7835 "Failed to read Option field from module EEPROM\n"); 7836 return -EINVAL; 7837 } 7838 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK)) 7839 *edc_mode = EDC_MODE_LINEAR; 7840 else 7841 *edc_mode = EDC_MODE_LIMITING; 7842 } 7843 DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode); 7844 return 0; 7845 } 7846 /* This function read the relevant field from the module (SFP+), and verify it 7847 * is compliant with this board 7848 */ 7849 static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy, 7850 struct link_params *params) 7851 { 7852 struct bnx2x *bp = params->bp; 7853 u32 val, cmd; 7854 u32 fw_resp, fw_cmd_param; 7855 char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1]; 7856 char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1]; 7857 phy->flags &= ~FLAGS_SFP_NOT_APPROVED; 7858 val = REG_RD(bp, params->shmem_base + 7859 offsetof(struct shmem_region, dev_info. 7860 port_feature_config[params->port].config)); 7861 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == 7862 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) { 7863 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n"); 7864 return 0; 7865 } 7866 7867 if (params->feature_config_flags & 7868 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) { 7869 /* Use specific phy request */ 7870 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL; 7871 } else if (params->feature_config_flags & 7872 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) { 7873 /* Use first phy request only in case of non-dual media*/ 7874 if (DUAL_MEDIA(params)) { 7875 DP(NETIF_MSG_LINK, 7876 "FW does not support OPT MDL verification\n"); 7877 return -EINVAL; 7878 } 7879 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL; 7880 } else { 7881 /* No support in OPT MDL detection */ 7882 DP(NETIF_MSG_LINK, 7883 "FW does not support OPT MDL verification\n"); 7884 return -EINVAL; 7885 } 7886 7887 fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl); 7888 fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param); 7889 if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) { 7890 DP(NETIF_MSG_LINK, "Approved module\n"); 7891 return 0; 7892 } 7893 7894 /* Format the warning message */ 7895 if (bnx2x_read_sfp_module_eeprom(phy, 7896 params, 7897 SFP_EEPROM_VENDOR_NAME_ADDR, 7898 SFP_EEPROM_VENDOR_NAME_SIZE, 7899 (u8 *)vendor_name)) 7900 vendor_name[0] = '\0'; 7901 else 7902 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0'; 7903 if (bnx2x_read_sfp_module_eeprom(phy, 7904 params, 7905 SFP_EEPROM_PART_NO_ADDR, 7906 SFP_EEPROM_PART_NO_SIZE, 7907 (u8 *)vendor_pn)) 7908 vendor_pn[0] = '\0'; 7909 else 7910 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0'; 7911 7912 netdev_err(bp->dev, "Warning: Unqualified SFP+ module detected," 7913 " Port %d from %s part number %s\n", 7914 params->port, vendor_name, vendor_pn); 7915 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) != 7916 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG) 7917 phy->flags |= FLAGS_SFP_NOT_APPROVED; 7918 return -EINVAL; 7919 } 7920 7921 static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy, 7922 struct link_params *params) 7923 7924 { 7925 u8 val; 7926 struct bnx2x *bp = params->bp; 7927 u16 timeout; 7928 /* Initialization time after hot-plug may take up to 300ms for 7929 * some phys type ( e.g. JDSU ) 7930 */ 7931 7932 for (timeout = 0; timeout < 60; timeout++) { 7933 if (bnx2x_read_sfp_module_eeprom(phy, params, 1, 1, &val) 7934 == 0) { 7935 DP(NETIF_MSG_LINK, 7936 "SFP+ module initialization took %d ms\n", 7937 timeout * 5); 7938 return 0; 7939 } 7940 usleep_range(5000, 10000); 7941 } 7942 return -EINVAL; 7943 } 7944 7945 static void bnx2x_8727_power_module(struct bnx2x *bp, 7946 struct bnx2x_phy *phy, 7947 u8 is_power_up) { 7948 /* Make sure GPIOs are not using for LED mode */ 7949 u16 val; 7950 /* In the GPIO register, bit 4 is use to determine if the GPIOs are 7951 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for 7952 * output 7953 * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0 7954 * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1 7955 * where the 1st bit is the over-current(only input), and 2nd bit is 7956 * for power( only output ) 7957 * 7958 * In case of NOC feature is disabled and power is up, set GPIO control 7959 * as input to enable listening of over-current indication 7960 */ 7961 if (phy->flags & FLAGS_NOC) 7962 return; 7963 if (is_power_up) 7964 val = (1<<4); 7965 else 7966 /* Set GPIO control to OUTPUT, and set the power bit 7967 * to according to the is_power_up 7968 */ 7969 val = (1<<1); 7970 7971 bnx2x_cl45_write(bp, phy, 7972 MDIO_PMA_DEVAD, 7973 MDIO_PMA_REG_8727_GPIO_CTRL, 7974 val); 7975 } 7976 7977 static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp, 7978 struct bnx2x_phy *phy, 7979 u16 edc_mode) 7980 { 7981 u16 cur_limiting_mode; 7982 7983 bnx2x_cl45_read(bp, phy, 7984 MDIO_PMA_DEVAD, 7985 MDIO_PMA_REG_ROM_VER2, 7986 &cur_limiting_mode); 7987 DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n", 7988 cur_limiting_mode); 7989 7990 if (edc_mode == EDC_MODE_LIMITING) { 7991 DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n"); 7992 bnx2x_cl45_write(bp, phy, 7993 MDIO_PMA_DEVAD, 7994 MDIO_PMA_REG_ROM_VER2, 7995 EDC_MODE_LIMITING); 7996 } else { /* LRM mode ( default )*/ 7997 7998 DP(NETIF_MSG_LINK, "Setting LRM MODE\n"); 7999 8000 /* Changing to LRM mode takes quite few seconds. So do it only 8001 * if current mode is limiting (default is LRM) 8002 */ 8003 if (cur_limiting_mode != EDC_MODE_LIMITING) 8004 return 0; 8005 8006 bnx2x_cl45_write(bp, phy, 8007 MDIO_PMA_DEVAD, 8008 MDIO_PMA_REG_LRM_MODE, 8009 0); 8010 bnx2x_cl45_write(bp, phy, 8011 MDIO_PMA_DEVAD, 8012 MDIO_PMA_REG_ROM_VER2, 8013 0x128); 8014 bnx2x_cl45_write(bp, phy, 8015 MDIO_PMA_DEVAD, 8016 MDIO_PMA_REG_MISC_CTRL0, 8017 0x4008); 8018 bnx2x_cl45_write(bp, phy, 8019 MDIO_PMA_DEVAD, 8020 MDIO_PMA_REG_LRM_MODE, 8021 0xaaaa); 8022 } 8023 return 0; 8024 } 8025 8026 static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp, 8027 struct bnx2x_phy *phy, 8028 u16 edc_mode) 8029 { 8030 u16 phy_identifier; 8031 u16 rom_ver2_val; 8032 bnx2x_cl45_read(bp, phy, 8033 MDIO_PMA_DEVAD, 8034 MDIO_PMA_REG_PHY_IDENTIFIER, 8035 &phy_identifier); 8036 8037 bnx2x_cl45_write(bp, phy, 8038 MDIO_PMA_DEVAD, 8039 MDIO_PMA_REG_PHY_IDENTIFIER, 8040 (phy_identifier & ~(1<<9))); 8041 8042 bnx2x_cl45_read(bp, phy, 8043 MDIO_PMA_DEVAD, 8044 MDIO_PMA_REG_ROM_VER2, 8045 &rom_ver2_val); 8046 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */ 8047 bnx2x_cl45_write(bp, phy, 8048 MDIO_PMA_DEVAD, 8049 MDIO_PMA_REG_ROM_VER2, 8050 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff)); 8051 8052 bnx2x_cl45_write(bp, phy, 8053 MDIO_PMA_DEVAD, 8054 MDIO_PMA_REG_PHY_IDENTIFIER, 8055 (phy_identifier | (1<<9))); 8056 8057 return 0; 8058 } 8059 8060 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy, 8061 struct link_params *params, 8062 u32 action) 8063 { 8064 struct bnx2x *bp = params->bp; 8065 u16 val; 8066 switch (action) { 8067 case DISABLE_TX: 8068 bnx2x_sfp_set_transmitter(params, phy, 0); 8069 break; 8070 case ENABLE_TX: 8071 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) 8072 bnx2x_sfp_set_transmitter(params, phy, 1); 8073 break; 8074 case PHY_INIT: 8075 bnx2x_cl45_write(bp, phy, 8076 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 8077 (1<<2) | (1<<5)); 8078 bnx2x_cl45_write(bp, phy, 8079 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, 8080 0); 8081 bnx2x_cl45_write(bp, phy, 8082 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0006); 8083 /* Make MOD_ABS give interrupt on change */ 8084 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 8085 MDIO_PMA_REG_8727_PCS_OPT_CTRL, 8086 &val); 8087 val |= (1<<12); 8088 if (phy->flags & FLAGS_NOC) 8089 val |= (3<<5); 8090 /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0 8091 * status which reflect SFP+ module over-current 8092 */ 8093 if (!(phy->flags & FLAGS_NOC)) 8094 val &= 0xff8f; /* Reset bits 4-6 */ 8095 bnx2x_cl45_write(bp, phy, 8096 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, 8097 val); 8098 8099 /* Set 2-wire transfer rate of SFP+ module EEPROM 8100 * to 100Khz since some DACs(direct attached cables) do 8101 * not work at 400Khz. 8102 */ 8103 bnx2x_cl45_write(bp, phy, 8104 MDIO_PMA_DEVAD, 8105 MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR, 8106 0xa001); 8107 break; 8108 default: 8109 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n", 8110 action); 8111 return; 8112 } 8113 } 8114 8115 static void bnx2x_set_e1e2_module_fault_led(struct link_params *params, 8116 u8 gpio_mode) 8117 { 8118 struct bnx2x *bp = params->bp; 8119 8120 u32 fault_led_gpio = REG_RD(bp, params->shmem_base + 8121 offsetof(struct shmem_region, 8122 dev_info.port_hw_config[params->port].sfp_ctrl)) & 8123 PORT_HW_CFG_FAULT_MODULE_LED_MASK; 8124 switch (fault_led_gpio) { 8125 case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED: 8126 return; 8127 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0: 8128 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1: 8129 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2: 8130 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3: 8131 { 8132 u8 gpio_port = bnx2x_get_gpio_port(params); 8133 u16 gpio_pin = fault_led_gpio - 8134 PORT_HW_CFG_FAULT_MODULE_LED_GPIO0; 8135 DP(NETIF_MSG_LINK, "Set fault module-detected led " 8136 "pin %x port %x mode %x\n", 8137 gpio_pin, gpio_port, gpio_mode); 8138 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port); 8139 } 8140 break; 8141 default: 8142 DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n", 8143 fault_led_gpio); 8144 } 8145 } 8146 8147 static void bnx2x_set_e3_module_fault_led(struct link_params *params, 8148 u8 gpio_mode) 8149 { 8150 u32 pin_cfg; 8151 u8 port = params->port; 8152 struct bnx2x *bp = params->bp; 8153 pin_cfg = (REG_RD(bp, params->shmem_base + 8154 offsetof(struct shmem_region, 8155 dev_info.port_hw_config[port].e3_sfp_ctrl)) & 8156 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >> 8157 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT; 8158 DP(NETIF_MSG_LINK, "Setting Fault LED to %d using pin cfg %d\n", 8159 gpio_mode, pin_cfg); 8160 bnx2x_set_cfg_pin(bp, pin_cfg, gpio_mode); 8161 } 8162 8163 static void bnx2x_set_sfp_module_fault_led(struct link_params *params, 8164 u8 gpio_mode) 8165 { 8166 struct bnx2x *bp = params->bp; 8167 DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode); 8168 if (CHIP_IS_E3(bp)) { 8169 /* Low ==> if SFP+ module is supported otherwise 8170 * High ==> if SFP+ module is not on the approved vendor list 8171 */ 8172 bnx2x_set_e3_module_fault_led(params, gpio_mode); 8173 } else 8174 bnx2x_set_e1e2_module_fault_led(params, gpio_mode); 8175 } 8176 8177 static void bnx2x_warpcore_hw_reset(struct bnx2x_phy *phy, 8178 struct link_params *params) 8179 { 8180 struct bnx2x *bp = params->bp; 8181 bnx2x_warpcore_power_module(params, phy, 0); 8182 /* Put Warpcore in low power mode */ 8183 REG_WR(bp, MISC_REG_WC0_RESET, 0x0c0e); 8184 8185 /* Put LCPLL in low power mode */ 8186 REG_WR(bp, MISC_REG_LCPLL_E40_PWRDWN, 1); 8187 REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_ANA, 0); 8188 REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_DIG, 0); 8189 } 8190 8191 static void bnx2x_power_sfp_module(struct link_params *params, 8192 struct bnx2x_phy *phy, 8193 u8 power) 8194 { 8195 struct bnx2x *bp = params->bp; 8196 DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power); 8197 8198 switch (phy->type) { 8199 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 8200 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 8201 bnx2x_8727_power_module(params->bp, phy, power); 8202 break; 8203 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: 8204 bnx2x_warpcore_power_module(params, phy, power); 8205 break; 8206 default: 8207 break; 8208 } 8209 } 8210 static void bnx2x_warpcore_set_limiting_mode(struct link_params *params, 8211 struct bnx2x_phy *phy, 8212 u16 edc_mode) 8213 { 8214 u16 val = 0; 8215 u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT; 8216 struct bnx2x *bp = params->bp; 8217 8218 u8 lane = bnx2x_get_warpcore_lane(phy, params); 8219 /* This is a global register which controls all lanes */ 8220 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 8221 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val); 8222 val &= ~(0xf << (lane << 2)); 8223 8224 switch (edc_mode) { 8225 case EDC_MODE_LINEAR: 8226 case EDC_MODE_LIMITING: 8227 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT; 8228 break; 8229 case EDC_MODE_PASSIVE_DAC: 8230 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC; 8231 break; 8232 default: 8233 break; 8234 } 8235 8236 val |= (mode << (lane << 2)); 8237 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 8238 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val); 8239 /* A must read */ 8240 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 8241 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val); 8242 8243 /* Restart microcode to re-read the new mode */ 8244 bnx2x_warpcore_reset_lane(bp, phy, 1); 8245 bnx2x_warpcore_reset_lane(bp, phy, 0); 8246 8247 } 8248 8249 static void bnx2x_set_limiting_mode(struct link_params *params, 8250 struct bnx2x_phy *phy, 8251 u16 edc_mode) 8252 { 8253 switch (phy->type) { 8254 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 8255 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode); 8256 break; 8257 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 8258 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 8259 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode); 8260 break; 8261 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: 8262 bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode); 8263 break; 8264 } 8265 } 8266 8267 int bnx2x_sfp_module_detection(struct bnx2x_phy *phy, 8268 struct link_params *params) 8269 { 8270 struct bnx2x *bp = params->bp; 8271 u16 edc_mode; 8272 int rc = 0; 8273 8274 u32 val = REG_RD(bp, params->shmem_base + 8275 offsetof(struct shmem_region, dev_info. 8276 port_feature_config[params->port].config)); 8277 8278 DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n", 8279 params->port); 8280 /* Power up module */ 8281 bnx2x_power_sfp_module(params, phy, 1); 8282 if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) { 8283 DP(NETIF_MSG_LINK, "Failed to get valid module type\n"); 8284 return -EINVAL; 8285 } else if (bnx2x_verify_sfp_module(phy, params) != 0) { 8286 /* Check SFP+ module compatibility */ 8287 DP(NETIF_MSG_LINK, "Module verification failed!!\n"); 8288 rc = -EINVAL; 8289 /* Turn on fault module-detected led */ 8290 bnx2x_set_sfp_module_fault_led(params, 8291 MISC_REGISTERS_GPIO_HIGH); 8292 8293 /* Check if need to power down the SFP+ module */ 8294 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == 8295 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) { 8296 DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n"); 8297 bnx2x_power_sfp_module(params, phy, 0); 8298 return rc; 8299 } 8300 } else { 8301 /* Turn off fault module-detected led */ 8302 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW); 8303 } 8304 8305 /* Check and set limiting mode / LRM mode on 8726. On 8727 it 8306 * is done automatically 8307 */ 8308 bnx2x_set_limiting_mode(params, phy, edc_mode); 8309 8310 /* Enable transmit for this module if the module is approved, or 8311 * if unapproved modules should also enable the Tx laser 8312 */ 8313 if (rc == 0 || 8314 (val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) != 8315 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) 8316 bnx2x_sfp_set_transmitter(params, phy, 1); 8317 else 8318 bnx2x_sfp_set_transmitter(params, phy, 0); 8319 8320 return rc; 8321 } 8322 8323 void bnx2x_handle_module_detect_int(struct link_params *params) 8324 { 8325 struct bnx2x *bp = params->bp; 8326 struct bnx2x_phy *phy; 8327 u32 gpio_val; 8328 u8 gpio_num, gpio_port; 8329 if (CHIP_IS_E3(bp)) 8330 phy = ¶ms->phy[INT_PHY]; 8331 else 8332 phy = ¶ms->phy[EXT_PHY1]; 8333 8334 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base, 8335 params->port, &gpio_num, &gpio_port) == 8336 -EINVAL) { 8337 DP(NETIF_MSG_LINK, "Failed to get MOD_ABS interrupt config\n"); 8338 return; 8339 } 8340 8341 /* Set valid module led off */ 8342 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH); 8343 8344 /* Get current gpio val reflecting module plugged in / out*/ 8345 gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port); 8346 8347 /* Call the handling function in case module is detected */ 8348 if (gpio_val == 0) { 8349 bnx2x_set_mdio_clk(bp, params->chip_id, params->port); 8350 bnx2x_set_aer_mmd(params, phy); 8351 8352 bnx2x_power_sfp_module(params, phy, 1); 8353 bnx2x_set_gpio_int(bp, gpio_num, 8354 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR, 8355 gpio_port); 8356 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) { 8357 bnx2x_sfp_module_detection(phy, params); 8358 if (CHIP_IS_E3(bp)) { 8359 u16 rx_tx_in_reset; 8360 /* In case WC is out of reset, reconfigure the 8361 * link speed while taking into account 1G 8362 * module limitation. 8363 */ 8364 bnx2x_cl45_read(bp, phy, 8365 MDIO_WC_DEVAD, 8366 MDIO_WC_REG_DIGITAL5_MISC6, 8367 &rx_tx_in_reset); 8368 if (!rx_tx_in_reset) { 8369 bnx2x_warpcore_reset_lane(bp, phy, 1); 8370 bnx2x_warpcore_config_sfi(phy, params); 8371 bnx2x_warpcore_reset_lane(bp, phy, 0); 8372 } 8373 } 8374 } else { 8375 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n"); 8376 } 8377 } else { 8378 u32 val = REG_RD(bp, params->shmem_base + 8379 offsetof(struct shmem_region, dev_info. 8380 port_feature_config[params->port]. 8381 config)); 8382 bnx2x_set_gpio_int(bp, gpio_num, 8383 MISC_REGISTERS_GPIO_INT_OUTPUT_SET, 8384 gpio_port); 8385 /* Module was plugged out. 8386 * Disable transmit for this module 8387 */ 8388 phy->media_type = ETH_PHY_NOT_PRESENT; 8389 if (((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == 8390 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) || 8391 CHIP_IS_E3(bp)) 8392 bnx2x_sfp_set_transmitter(params, phy, 0); 8393 } 8394 } 8395 8396 /******************************************************************/ 8397 /* Used by 8706 and 8727 */ 8398 /******************************************************************/ 8399 static void bnx2x_sfp_mask_fault(struct bnx2x *bp, 8400 struct bnx2x_phy *phy, 8401 u16 alarm_status_offset, 8402 u16 alarm_ctrl_offset) 8403 { 8404 u16 alarm_status, val; 8405 bnx2x_cl45_read(bp, phy, 8406 MDIO_PMA_DEVAD, alarm_status_offset, 8407 &alarm_status); 8408 bnx2x_cl45_read(bp, phy, 8409 MDIO_PMA_DEVAD, alarm_status_offset, 8410 &alarm_status); 8411 /* Mask or enable the fault event. */ 8412 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val); 8413 if (alarm_status & (1<<0)) 8414 val &= ~(1<<0); 8415 else 8416 val |= (1<<0); 8417 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val); 8418 } 8419 /******************************************************************/ 8420 /* common BCM8706/BCM8726 PHY SECTION */ 8421 /******************************************************************/ 8422 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy, 8423 struct link_params *params, 8424 struct link_vars *vars) 8425 { 8426 u8 link_up = 0; 8427 u16 val1, val2, rx_sd, pcs_status; 8428 struct bnx2x *bp = params->bp; 8429 DP(NETIF_MSG_LINK, "XGXS 8706/8726\n"); 8430 /* Clear RX Alarm*/ 8431 bnx2x_cl45_read(bp, phy, 8432 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2); 8433 8434 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT, 8435 MDIO_PMA_LASI_TXCTRL); 8436 8437 /* Clear LASI indication*/ 8438 bnx2x_cl45_read(bp, phy, 8439 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); 8440 bnx2x_cl45_read(bp, phy, 8441 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2); 8442 DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2); 8443 8444 bnx2x_cl45_read(bp, phy, 8445 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd); 8446 bnx2x_cl45_read(bp, phy, 8447 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status); 8448 bnx2x_cl45_read(bp, phy, 8449 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2); 8450 bnx2x_cl45_read(bp, phy, 8451 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2); 8452 8453 DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps" 8454 " link_status 0x%x\n", rx_sd, pcs_status, val2); 8455 /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status 8456 * are set, or if the autoneg bit 1 is set 8457 */ 8458 link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1))); 8459 if (link_up) { 8460 if (val2 & (1<<1)) 8461 vars->line_speed = SPEED_1000; 8462 else 8463 vars->line_speed = SPEED_10000; 8464 bnx2x_ext_phy_resolve_fc(phy, params, vars); 8465 vars->duplex = DUPLEX_FULL; 8466 } 8467 8468 /* Capture 10G link fault. Read twice to clear stale value. */ 8469 if (vars->line_speed == SPEED_10000) { 8470 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 8471 MDIO_PMA_LASI_TXSTAT, &val1); 8472 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 8473 MDIO_PMA_LASI_TXSTAT, &val1); 8474 if (val1 & (1<<0)) 8475 vars->fault_detected = 1; 8476 } 8477 8478 return link_up; 8479 } 8480 8481 /******************************************************************/ 8482 /* BCM8706 PHY SECTION */ 8483 /******************************************************************/ 8484 static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy, 8485 struct link_params *params, 8486 struct link_vars *vars) 8487 { 8488 u32 tx_en_mode; 8489 u16 cnt, val, tmp1; 8490 struct bnx2x *bp = params->bp; 8491 8492 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 8493 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); 8494 /* HW reset */ 8495 bnx2x_ext_phy_hw_reset(bp, params->port); 8496 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); 8497 bnx2x_wait_reset_complete(bp, phy, params); 8498 8499 /* Wait until fw is loaded */ 8500 for (cnt = 0; cnt < 100; cnt++) { 8501 bnx2x_cl45_read(bp, phy, 8502 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val); 8503 if (val) 8504 break; 8505 usleep_range(10000, 20000); 8506 } 8507 DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt); 8508 if ((params->feature_config_flags & 8509 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { 8510 u8 i; 8511 u16 reg; 8512 for (i = 0; i < 4; i++) { 8513 reg = MDIO_XS_8706_REG_BANK_RX0 + 8514 i*(MDIO_XS_8706_REG_BANK_RX1 - 8515 MDIO_XS_8706_REG_BANK_RX0); 8516 bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val); 8517 /* Clear first 3 bits of the control */ 8518 val &= ~0x7; 8519 /* Set control bits according to configuration */ 8520 val |= (phy->rx_preemphasis[i] & 0x7); 8521 DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706" 8522 " reg 0x%x <-- val 0x%x\n", reg, val); 8523 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val); 8524 } 8525 } 8526 /* Force speed */ 8527 if (phy->req_line_speed == SPEED_10000) { 8528 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n"); 8529 8530 bnx2x_cl45_write(bp, phy, 8531 MDIO_PMA_DEVAD, 8532 MDIO_PMA_REG_DIGITAL_CTRL, 0x400); 8533 bnx2x_cl45_write(bp, phy, 8534 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, 8535 0); 8536 /* Arm LASI for link and Tx fault. */ 8537 bnx2x_cl45_write(bp, phy, 8538 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3); 8539 } else { 8540 /* Force 1Gbps using autoneg with 1G advertisement */ 8541 8542 /* Allow CL37 through CL73 */ 8543 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n"); 8544 bnx2x_cl45_write(bp, phy, 8545 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c); 8546 8547 /* Enable Full-Duplex advertisement on CL37 */ 8548 bnx2x_cl45_write(bp, phy, 8549 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020); 8550 /* Enable CL37 AN */ 8551 bnx2x_cl45_write(bp, phy, 8552 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); 8553 /* 1G support */ 8554 bnx2x_cl45_write(bp, phy, 8555 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5)); 8556 8557 /* Enable clause 73 AN */ 8558 bnx2x_cl45_write(bp, phy, 8559 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); 8560 bnx2x_cl45_write(bp, phy, 8561 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 8562 0x0400); 8563 bnx2x_cl45_write(bp, phy, 8564 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 8565 0x0004); 8566 } 8567 bnx2x_save_bcm_spirom_ver(bp, phy, params->port); 8568 8569 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low 8570 * power mode, if TX Laser is disabled 8571 */ 8572 8573 tx_en_mode = REG_RD(bp, params->shmem_base + 8574 offsetof(struct shmem_region, 8575 dev_info.port_hw_config[params->port].sfp_ctrl)) 8576 & PORT_HW_CFG_TX_LASER_MASK; 8577 8578 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) { 8579 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n"); 8580 bnx2x_cl45_read(bp, phy, 8581 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1); 8582 tmp1 |= 0x1; 8583 bnx2x_cl45_write(bp, phy, 8584 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1); 8585 } 8586 8587 return 0; 8588 } 8589 8590 static int bnx2x_8706_read_status(struct bnx2x_phy *phy, 8591 struct link_params *params, 8592 struct link_vars *vars) 8593 { 8594 return bnx2x_8706_8726_read_status(phy, params, vars); 8595 } 8596 8597 /******************************************************************/ 8598 /* BCM8726 PHY SECTION */ 8599 /******************************************************************/ 8600 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy, 8601 struct link_params *params) 8602 { 8603 struct bnx2x *bp = params->bp; 8604 DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n"); 8605 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001); 8606 } 8607 8608 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy, 8609 struct link_params *params) 8610 { 8611 struct bnx2x *bp = params->bp; 8612 /* Need to wait 100ms after reset */ 8613 msleep(100); 8614 8615 /* Micro controller re-boot */ 8616 bnx2x_cl45_write(bp, phy, 8617 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B); 8618 8619 /* Set soft reset */ 8620 bnx2x_cl45_write(bp, phy, 8621 MDIO_PMA_DEVAD, 8622 MDIO_PMA_REG_GEN_CTRL, 8623 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); 8624 8625 bnx2x_cl45_write(bp, phy, 8626 MDIO_PMA_DEVAD, 8627 MDIO_PMA_REG_MISC_CTRL1, 0x0001); 8628 8629 bnx2x_cl45_write(bp, phy, 8630 MDIO_PMA_DEVAD, 8631 MDIO_PMA_REG_GEN_CTRL, 8632 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); 8633 8634 /* Wait for 150ms for microcode load */ 8635 msleep(150); 8636 8637 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */ 8638 bnx2x_cl45_write(bp, phy, 8639 MDIO_PMA_DEVAD, 8640 MDIO_PMA_REG_MISC_CTRL1, 0x0000); 8641 8642 msleep(200); 8643 bnx2x_save_bcm_spirom_ver(bp, phy, params->port); 8644 } 8645 8646 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy, 8647 struct link_params *params, 8648 struct link_vars *vars) 8649 { 8650 struct bnx2x *bp = params->bp; 8651 u16 val1; 8652 u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars); 8653 if (link_up) { 8654 bnx2x_cl45_read(bp, phy, 8655 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 8656 &val1); 8657 if (val1 & (1<<15)) { 8658 DP(NETIF_MSG_LINK, "Tx is disabled\n"); 8659 link_up = 0; 8660 vars->line_speed = 0; 8661 } 8662 } 8663 return link_up; 8664 } 8665 8666 8667 static int bnx2x_8726_config_init(struct bnx2x_phy *phy, 8668 struct link_params *params, 8669 struct link_vars *vars) 8670 { 8671 struct bnx2x *bp = params->bp; 8672 DP(NETIF_MSG_LINK, "Initializing BCM8726\n"); 8673 8674 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); 8675 bnx2x_wait_reset_complete(bp, phy, params); 8676 8677 bnx2x_8726_external_rom_boot(phy, params); 8678 8679 /* Need to call module detected on initialization since the module 8680 * detection triggered by actual module insertion might occur before 8681 * driver is loaded, and when driver is loaded, it reset all 8682 * registers, including the transmitter 8683 */ 8684 bnx2x_sfp_module_detection(phy, params); 8685 8686 if (phy->req_line_speed == SPEED_1000) { 8687 DP(NETIF_MSG_LINK, "Setting 1G force\n"); 8688 bnx2x_cl45_write(bp, phy, 8689 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40); 8690 bnx2x_cl45_write(bp, phy, 8691 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD); 8692 bnx2x_cl45_write(bp, phy, 8693 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5); 8694 bnx2x_cl45_write(bp, phy, 8695 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 8696 0x400); 8697 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) && 8698 (phy->speed_cap_mask & 8699 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) && 8700 ((phy->speed_cap_mask & 8701 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) != 8702 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { 8703 DP(NETIF_MSG_LINK, "Setting 1G clause37\n"); 8704 /* Set Flow control */ 8705 bnx2x_ext_phy_set_pause(params, phy, vars); 8706 bnx2x_cl45_write(bp, phy, 8707 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20); 8708 bnx2x_cl45_write(bp, phy, 8709 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c); 8710 bnx2x_cl45_write(bp, phy, 8711 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020); 8712 bnx2x_cl45_write(bp, phy, 8713 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); 8714 bnx2x_cl45_write(bp, phy, 8715 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); 8716 /* Enable RX-ALARM control to receive interrupt for 1G speed 8717 * change 8718 */ 8719 bnx2x_cl45_write(bp, phy, 8720 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4); 8721 bnx2x_cl45_write(bp, phy, 8722 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 8723 0x400); 8724 8725 } else { /* Default 10G. Set only LASI control */ 8726 bnx2x_cl45_write(bp, phy, 8727 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1); 8728 } 8729 8730 /* Set TX PreEmphasis if needed */ 8731 if ((params->feature_config_flags & 8732 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { 8733 DP(NETIF_MSG_LINK, 8734 "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n", 8735 phy->tx_preemphasis[0], 8736 phy->tx_preemphasis[1]); 8737 bnx2x_cl45_write(bp, phy, 8738 MDIO_PMA_DEVAD, 8739 MDIO_PMA_REG_8726_TX_CTRL1, 8740 phy->tx_preemphasis[0]); 8741 8742 bnx2x_cl45_write(bp, phy, 8743 MDIO_PMA_DEVAD, 8744 MDIO_PMA_REG_8726_TX_CTRL2, 8745 phy->tx_preemphasis[1]); 8746 } 8747 8748 return 0; 8749 8750 } 8751 8752 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy, 8753 struct link_params *params) 8754 { 8755 struct bnx2x *bp = params->bp; 8756 DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port); 8757 /* Set serial boot control for external load */ 8758 bnx2x_cl45_write(bp, phy, 8759 MDIO_PMA_DEVAD, 8760 MDIO_PMA_REG_GEN_CTRL, 0x0001); 8761 } 8762 8763 /******************************************************************/ 8764 /* BCM8727 PHY SECTION */ 8765 /******************************************************************/ 8766 8767 static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy, 8768 struct link_params *params, u8 mode) 8769 { 8770 struct bnx2x *bp = params->bp; 8771 u16 led_mode_bitmask = 0; 8772 u16 gpio_pins_bitmask = 0; 8773 u16 val; 8774 /* Only NOC flavor requires to set the LED specifically */ 8775 if (!(phy->flags & FLAGS_NOC)) 8776 return; 8777 switch (mode) { 8778 case LED_MODE_FRONT_PANEL_OFF: 8779 case LED_MODE_OFF: 8780 led_mode_bitmask = 0; 8781 gpio_pins_bitmask = 0x03; 8782 break; 8783 case LED_MODE_ON: 8784 led_mode_bitmask = 0; 8785 gpio_pins_bitmask = 0x02; 8786 break; 8787 case LED_MODE_OPER: 8788 led_mode_bitmask = 0x60; 8789 gpio_pins_bitmask = 0x11; 8790 break; 8791 } 8792 bnx2x_cl45_read(bp, phy, 8793 MDIO_PMA_DEVAD, 8794 MDIO_PMA_REG_8727_PCS_OPT_CTRL, 8795 &val); 8796 val &= 0xff8f; 8797 val |= led_mode_bitmask; 8798 bnx2x_cl45_write(bp, phy, 8799 MDIO_PMA_DEVAD, 8800 MDIO_PMA_REG_8727_PCS_OPT_CTRL, 8801 val); 8802 bnx2x_cl45_read(bp, phy, 8803 MDIO_PMA_DEVAD, 8804 MDIO_PMA_REG_8727_GPIO_CTRL, 8805 &val); 8806 val &= 0xffe0; 8807 val |= gpio_pins_bitmask; 8808 bnx2x_cl45_write(bp, phy, 8809 MDIO_PMA_DEVAD, 8810 MDIO_PMA_REG_8727_GPIO_CTRL, 8811 val); 8812 } 8813 static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy, 8814 struct link_params *params) { 8815 u32 swap_val, swap_override; 8816 u8 port; 8817 /* The PHY reset is controlled by GPIO 1. Fake the port number 8818 * to cancel the swap done in set_gpio() 8819 */ 8820 struct bnx2x *bp = params->bp; 8821 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); 8822 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); 8823 port = (swap_val && swap_override) ^ 1; 8824 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 8825 MISC_REGISTERS_GPIO_OUTPUT_LOW, port); 8826 } 8827 8828 static void bnx2x_8727_config_speed(struct bnx2x_phy *phy, 8829 struct link_params *params) 8830 { 8831 struct bnx2x *bp = params->bp; 8832 u16 tmp1, val; 8833 /* Set option 1G speed */ 8834 if ((phy->req_line_speed == SPEED_1000) || 8835 (phy->media_type == ETH_PHY_SFP_1G_FIBER)) { 8836 DP(NETIF_MSG_LINK, "Setting 1G force\n"); 8837 bnx2x_cl45_write(bp, phy, 8838 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40); 8839 bnx2x_cl45_write(bp, phy, 8840 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD); 8841 bnx2x_cl45_read(bp, phy, 8842 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1); 8843 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1); 8844 /* Power down the XAUI until link is up in case of dual-media 8845 * and 1G 8846 */ 8847 if (DUAL_MEDIA(params)) { 8848 bnx2x_cl45_read(bp, phy, 8849 MDIO_PMA_DEVAD, 8850 MDIO_PMA_REG_8727_PCS_GP, &val); 8851 val |= (3<<10); 8852 bnx2x_cl45_write(bp, phy, 8853 MDIO_PMA_DEVAD, 8854 MDIO_PMA_REG_8727_PCS_GP, val); 8855 } 8856 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) && 8857 ((phy->speed_cap_mask & 8858 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) && 8859 ((phy->speed_cap_mask & 8860 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) != 8861 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { 8862 8863 DP(NETIF_MSG_LINK, "Setting 1G clause37\n"); 8864 bnx2x_cl45_write(bp, phy, 8865 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0); 8866 bnx2x_cl45_write(bp, phy, 8867 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300); 8868 } else { 8869 /* Since the 8727 has only single reset pin, need to set the 10G 8870 * registers although it is default 8871 */ 8872 bnx2x_cl45_write(bp, phy, 8873 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 8874 0x0020); 8875 bnx2x_cl45_write(bp, phy, 8876 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100); 8877 bnx2x_cl45_write(bp, phy, 8878 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040); 8879 bnx2x_cl45_write(bp, phy, 8880 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 8881 0x0008); 8882 } 8883 } 8884 8885 static int bnx2x_8727_config_init(struct bnx2x_phy *phy, 8886 struct link_params *params, 8887 struct link_vars *vars) 8888 { 8889 u32 tx_en_mode; 8890 u16 tmp1, mod_abs, tmp2; 8891 struct bnx2x *bp = params->bp; 8892 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */ 8893 8894 bnx2x_wait_reset_complete(bp, phy, params); 8895 8896 DP(NETIF_MSG_LINK, "Initializing BCM8727\n"); 8897 8898 bnx2x_8727_specific_func(phy, params, PHY_INIT); 8899 /* Initially configure MOD_ABS to interrupt when module is 8900 * presence( bit 8) 8901 */ 8902 bnx2x_cl45_read(bp, phy, 8903 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs); 8904 /* Set EDC off by setting OPTXLOS signal input to low (bit 9). 8905 * When the EDC is off it locks onto a reference clock and avoids 8906 * becoming 'lost' 8907 */ 8908 mod_abs &= ~(1<<8); 8909 if (!(phy->flags & FLAGS_NOC)) 8910 mod_abs &= ~(1<<9); 8911 bnx2x_cl45_write(bp, phy, 8912 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); 8913 8914 /* Enable/Disable PHY transmitter output */ 8915 bnx2x_set_disable_pmd_transmit(params, phy, 0); 8916 8917 bnx2x_8727_power_module(bp, phy, 1); 8918 8919 bnx2x_cl45_read(bp, phy, 8920 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1); 8921 8922 bnx2x_cl45_read(bp, phy, 8923 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1); 8924 8925 bnx2x_8727_config_speed(phy, params); 8926 8927 8928 /* Set TX PreEmphasis if needed */ 8929 if ((params->feature_config_flags & 8930 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { 8931 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n", 8932 phy->tx_preemphasis[0], 8933 phy->tx_preemphasis[1]); 8934 bnx2x_cl45_write(bp, phy, 8935 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1, 8936 phy->tx_preemphasis[0]); 8937 8938 bnx2x_cl45_write(bp, phy, 8939 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2, 8940 phy->tx_preemphasis[1]); 8941 } 8942 8943 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low 8944 * power mode, if TX Laser is disabled 8945 */ 8946 tx_en_mode = REG_RD(bp, params->shmem_base + 8947 offsetof(struct shmem_region, 8948 dev_info.port_hw_config[params->port].sfp_ctrl)) 8949 & PORT_HW_CFG_TX_LASER_MASK; 8950 8951 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) { 8952 8953 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n"); 8954 bnx2x_cl45_read(bp, phy, 8955 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2); 8956 tmp2 |= 0x1000; 8957 tmp2 &= 0xFFEF; 8958 bnx2x_cl45_write(bp, phy, 8959 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2); 8960 bnx2x_cl45_read(bp, phy, 8961 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 8962 &tmp2); 8963 bnx2x_cl45_write(bp, phy, 8964 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 8965 (tmp2 & 0x7fff)); 8966 } 8967 8968 return 0; 8969 } 8970 8971 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy, 8972 struct link_params *params) 8973 { 8974 struct bnx2x *bp = params->bp; 8975 u16 mod_abs, rx_alarm_status; 8976 u32 val = REG_RD(bp, params->shmem_base + 8977 offsetof(struct shmem_region, dev_info. 8978 port_feature_config[params->port]. 8979 config)); 8980 bnx2x_cl45_read(bp, phy, 8981 MDIO_PMA_DEVAD, 8982 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs); 8983 if (mod_abs & (1<<8)) { 8984 8985 /* Module is absent */ 8986 DP(NETIF_MSG_LINK, 8987 "MOD_ABS indication show module is absent\n"); 8988 phy->media_type = ETH_PHY_NOT_PRESENT; 8989 /* 1. Set mod_abs to detect next module 8990 * presence event 8991 * 2. Set EDC off by setting OPTXLOS signal input to low 8992 * (bit 9). 8993 * When the EDC is off it locks onto a reference clock and 8994 * avoids becoming 'lost'. 8995 */ 8996 mod_abs &= ~(1<<8); 8997 if (!(phy->flags & FLAGS_NOC)) 8998 mod_abs &= ~(1<<9); 8999 bnx2x_cl45_write(bp, phy, 9000 MDIO_PMA_DEVAD, 9001 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); 9002 9003 /* Clear RX alarm since it stays up as long as 9004 * the mod_abs wasn't changed 9005 */ 9006 bnx2x_cl45_read(bp, phy, 9007 MDIO_PMA_DEVAD, 9008 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); 9009 9010 } else { 9011 /* Module is present */ 9012 DP(NETIF_MSG_LINK, 9013 "MOD_ABS indication show module is present\n"); 9014 /* First disable transmitter, and if the module is ok, the 9015 * module_detection will enable it 9016 * 1. Set mod_abs to detect next module absent event ( bit 8) 9017 * 2. Restore the default polarity of the OPRXLOS signal and 9018 * this signal will then correctly indicate the presence or 9019 * absence of the Rx signal. (bit 9) 9020 */ 9021 mod_abs |= (1<<8); 9022 if (!(phy->flags & FLAGS_NOC)) 9023 mod_abs |= (1<<9); 9024 bnx2x_cl45_write(bp, phy, 9025 MDIO_PMA_DEVAD, 9026 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); 9027 9028 /* Clear RX alarm since it stays up as long as the mod_abs 9029 * wasn't changed. This is need to be done before calling the 9030 * module detection, otherwise it will clear* the link update 9031 * alarm 9032 */ 9033 bnx2x_cl45_read(bp, phy, 9034 MDIO_PMA_DEVAD, 9035 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); 9036 9037 9038 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == 9039 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) 9040 bnx2x_sfp_set_transmitter(params, phy, 0); 9041 9042 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) 9043 bnx2x_sfp_module_detection(phy, params); 9044 else 9045 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n"); 9046 9047 /* Reconfigure link speed based on module type limitations */ 9048 bnx2x_8727_config_speed(phy, params); 9049 } 9050 9051 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", 9052 rx_alarm_status); 9053 /* No need to check link status in case of module plugged in/out */ 9054 } 9055 9056 static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy, 9057 struct link_params *params, 9058 struct link_vars *vars) 9059 9060 { 9061 struct bnx2x *bp = params->bp; 9062 u8 link_up = 0, oc_port = params->port; 9063 u16 link_status = 0; 9064 u16 rx_alarm_status, lasi_ctrl, val1; 9065 9066 /* If PHY is not initialized, do not check link status */ 9067 bnx2x_cl45_read(bp, phy, 9068 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 9069 &lasi_ctrl); 9070 if (!lasi_ctrl) 9071 return 0; 9072 9073 /* Check the LASI on Rx */ 9074 bnx2x_cl45_read(bp, phy, 9075 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, 9076 &rx_alarm_status); 9077 vars->line_speed = 0; 9078 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status); 9079 9080 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT, 9081 MDIO_PMA_LASI_TXCTRL); 9082 9083 bnx2x_cl45_read(bp, phy, 9084 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); 9085 9086 DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1); 9087 9088 /* Clear MSG-OUT */ 9089 bnx2x_cl45_read(bp, phy, 9090 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1); 9091 9092 /* If a module is present and there is need to check 9093 * for over current 9094 */ 9095 if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) { 9096 /* Check over-current using 8727 GPIO0 input*/ 9097 bnx2x_cl45_read(bp, phy, 9098 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, 9099 &val1); 9100 9101 if ((val1 & (1<<8)) == 0) { 9102 if (!CHIP_IS_E1x(bp)) 9103 oc_port = BP_PATH(bp) + (params->port << 1); 9104 DP(NETIF_MSG_LINK, 9105 "8727 Power fault has been detected on port %d\n", 9106 oc_port); 9107 netdev_err(bp->dev, "Error: Power fault on Port %d has " 9108 "been detected and the power to " 9109 "that SFP+ module has been removed " 9110 "to prevent failure of the card. " 9111 "Please remove the SFP+ module and " 9112 "restart the system to clear this " 9113 "error.\n", 9114 oc_port); 9115 /* Disable all RX_ALARMs except for mod_abs */ 9116 bnx2x_cl45_write(bp, phy, 9117 MDIO_PMA_DEVAD, 9118 MDIO_PMA_LASI_RXCTRL, (1<<5)); 9119 9120 bnx2x_cl45_read(bp, phy, 9121 MDIO_PMA_DEVAD, 9122 MDIO_PMA_REG_PHY_IDENTIFIER, &val1); 9123 /* Wait for module_absent_event */ 9124 val1 |= (1<<8); 9125 bnx2x_cl45_write(bp, phy, 9126 MDIO_PMA_DEVAD, 9127 MDIO_PMA_REG_PHY_IDENTIFIER, val1); 9128 /* Clear RX alarm */ 9129 bnx2x_cl45_read(bp, phy, 9130 MDIO_PMA_DEVAD, 9131 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); 9132 return 0; 9133 } 9134 } /* Over current check */ 9135 9136 /* When module absent bit is set, check module */ 9137 if (rx_alarm_status & (1<<5)) { 9138 bnx2x_8727_handle_mod_abs(phy, params); 9139 /* Enable all mod_abs and link detection bits */ 9140 bnx2x_cl45_write(bp, phy, 9141 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 9142 ((1<<5) | (1<<2))); 9143 } 9144 9145 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) { 9146 DP(NETIF_MSG_LINK, "Enabling 8727 TX laser\n"); 9147 bnx2x_sfp_set_transmitter(params, phy, 1); 9148 } else { 9149 DP(NETIF_MSG_LINK, "Tx is disabled\n"); 9150 return 0; 9151 } 9152 9153 bnx2x_cl45_read(bp, phy, 9154 MDIO_PMA_DEVAD, 9155 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status); 9156 9157 /* Bits 0..2 --> speed detected, 9158 * Bits 13..15--> link is down 9159 */ 9160 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) { 9161 link_up = 1; 9162 vars->line_speed = SPEED_10000; 9163 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n", 9164 params->port); 9165 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) { 9166 link_up = 1; 9167 vars->line_speed = SPEED_1000; 9168 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n", 9169 params->port); 9170 } else { 9171 link_up = 0; 9172 DP(NETIF_MSG_LINK, "port %x: External link is down\n", 9173 params->port); 9174 } 9175 9176 /* Capture 10G link fault. */ 9177 if (vars->line_speed == SPEED_10000) { 9178 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 9179 MDIO_PMA_LASI_TXSTAT, &val1); 9180 9181 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 9182 MDIO_PMA_LASI_TXSTAT, &val1); 9183 9184 if (val1 & (1<<0)) { 9185 vars->fault_detected = 1; 9186 } 9187 } 9188 9189 if (link_up) { 9190 bnx2x_ext_phy_resolve_fc(phy, params, vars); 9191 vars->duplex = DUPLEX_FULL; 9192 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex); 9193 } 9194 9195 if ((DUAL_MEDIA(params)) && 9196 (phy->req_line_speed == SPEED_1000)) { 9197 bnx2x_cl45_read(bp, phy, 9198 MDIO_PMA_DEVAD, 9199 MDIO_PMA_REG_8727_PCS_GP, &val1); 9200 /* In case of dual-media board and 1G, power up the XAUI side, 9201 * otherwise power it down. For 10G it is done automatically 9202 */ 9203 if (link_up) 9204 val1 &= ~(3<<10); 9205 else 9206 val1 |= (3<<10); 9207 bnx2x_cl45_write(bp, phy, 9208 MDIO_PMA_DEVAD, 9209 MDIO_PMA_REG_8727_PCS_GP, val1); 9210 } 9211 return link_up; 9212 } 9213 9214 static void bnx2x_8727_link_reset(struct bnx2x_phy *phy, 9215 struct link_params *params) 9216 { 9217 struct bnx2x *bp = params->bp; 9218 9219 /* Enable/Disable PHY transmitter output */ 9220 bnx2x_set_disable_pmd_transmit(params, phy, 1); 9221 9222 /* Disable Transmitter */ 9223 bnx2x_sfp_set_transmitter(params, phy, 0); 9224 /* Clear LASI */ 9225 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0); 9226 9227 } 9228 9229 /******************************************************************/ 9230 /* BCM8481/BCM84823/BCM84833 PHY SECTION */ 9231 /******************************************************************/ 9232 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy, 9233 struct bnx2x *bp, 9234 u8 port) 9235 { 9236 u16 val, fw_ver1, fw_ver2, cnt; 9237 9238 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) { 9239 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1); 9240 bnx2x_save_spirom_version(bp, port, fw_ver1 & 0xfff, 9241 phy->ver_addr); 9242 } else { 9243 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */ 9244 /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */ 9245 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0014); 9246 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200); 9247 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81B, 0x0000); 9248 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81C, 0x0300); 9249 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x0009); 9250 9251 for (cnt = 0; cnt < 100; cnt++) { 9252 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val); 9253 if (val & 1) 9254 break; 9255 udelay(5); 9256 } 9257 if (cnt == 100) { 9258 DP(NETIF_MSG_LINK, "Unable to read 848xx " 9259 "phy fw version(1)\n"); 9260 bnx2x_save_spirom_version(bp, port, 0, 9261 phy->ver_addr); 9262 return; 9263 } 9264 9265 9266 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */ 9267 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000); 9268 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200); 9269 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A); 9270 for (cnt = 0; cnt < 100; cnt++) { 9271 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val); 9272 if (val & 1) 9273 break; 9274 udelay(5); 9275 } 9276 if (cnt == 100) { 9277 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw " 9278 "version(2)\n"); 9279 bnx2x_save_spirom_version(bp, port, 0, 9280 phy->ver_addr); 9281 return; 9282 } 9283 9284 /* lower 16 bits of the register SPI_FW_STATUS */ 9285 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1); 9286 /* upper 16 bits of register SPI_FW_STATUS */ 9287 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2); 9288 9289 bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1, 9290 phy->ver_addr); 9291 } 9292 9293 } 9294 static void bnx2x_848xx_set_led(struct bnx2x *bp, 9295 struct bnx2x_phy *phy) 9296 { 9297 u16 val, offset; 9298 9299 /* PHYC_CTL_LED_CTL */ 9300 bnx2x_cl45_read(bp, phy, 9301 MDIO_PMA_DEVAD, 9302 MDIO_PMA_REG_8481_LINK_SIGNAL, &val); 9303 val &= 0xFE00; 9304 val |= 0x0092; 9305 9306 bnx2x_cl45_write(bp, phy, 9307 MDIO_PMA_DEVAD, 9308 MDIO_PMA_REG_8481_LINK_SIGNAL, val); 9309 9310 bnx2x_cl45_write(bp, phy, 9311 MDIO_PMA_DEVAD, 9312 MDIO_PMA_REG_8481_LED1_MASK, 9313 0x80); 9314 9315 bnx2x_cl45_write(bp, phy, 9316 MDIO_PMA_DEVAD, 9317 MDIO_PMA_REG_8481_LED2_MASK, 9318 0x18); 9319 9320 /* Select activity source by Tx and Rx, as suggested by PHY AE */ 9321 bnx2x_cl45_write(bp, phy, 9322 MDIO_PMA_DEVAD, 9323 MDIO_PMA_REG_8481_LED3_MASK, 9324 0x0006); 9325 9326 /* Select the closest activity blink rate to that in 10/100/1000 */ 9327 bnx2x_cl45_write(bp, phy, 9328 MDIO_PMA_DEVAD, 9329 MDIO_PMA_REG_8481_LED3_BLINK, 9330 0); 9331 9332 /* Configure the blink rate to ~15.9 Hz */ 9333 bnx2x_cl45_write(bp, phy, 9334 MDIO_PMA_DEVAD, 9335 MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH, 9336 MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ); 9337 9338 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) 9339 offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1; 9340 else 9341 offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1; 9342 9343 bnx2x_cl45_read(bp, phy, 9344 MDIO_PMA_DEVAD, offset, &val); 9345 val |= MDIO_PMA_REG_84823_LED3_STRETCH_EN; /* stretch_en for LED3*/ 9346 bnx2x_cl45_write(bp, phy, 9347 MDIO_PMA_DEVAD, offset, val); 9348 9349 /* 'Interrupt Mask' */ 9350 bnx2x_cl45_write(bp, phy, 9351 MDIO_AN_DEVAD, 9352 0xFFFB, 0xFFFD); 9353 } 9354 9355 static void bnx2x_848xx_specific_func(struct bnx2x_phy *phy, 9356 struct link_params *params, 9357 u32 action) 9358 { 9359 struct bnx2x *bp = params->bp; 9360 switch (action) { 9361 case PHY_INIT: 9362 if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) { 9363 /* Save spirom version */ 9364 bnx2x_save_848xx_spirom_version(phy, bp, params->port); 9365 } 9366 /* This phy uses the NIG latch mechanism since link indication 9367 * arrives through its LED4 and not via its LASI signal, so we 9368 * get steady signal instead of clear on read 9369 */ 9370 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4, 9371 1 << NIG_LATCH_BC_ENABLE_MI_INT); 9372 9373 bnx2x_848xx_set_led(bp, phy); 9374 break; 9375 } 9376 } 9377 9378 static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy, 9379 struct link_params *params, 9380 struct link_vars *vars) 9381 { 9382 struct bnx2x *bp = params->bp; 9383 u16 autoneg_val, an_1000_val, an_10_100_val, an_10g_val; 9384 9385 bnx2x_848xx_specific_func(phy, params, PHY_INIT); 9386 bnx2x_cl45_write(bp, phy, 9387 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000); 9388 9389 /* set 1000 speed advertisement */ 9390 bnx2x_cl45_read(bp, phy, 9391 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL, 9392 &an_1000_val); 9393 9394 bnx2x_ext_phy_set_pause(params, phy, vars); 9395 bnx2x_cl45_read(bp, phy, 9396 MDIO_AN_DEVAD, 9397 MDIO_AN_REG_8481_LEGACY_AN_ADV, 9398 &an_10_100_val); 9399 bnx2x_cl45_read(bp, phy, 9400 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL, 9401 &autoneg_val); 9402 /* Disable forced speed */ 9403 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13)); 9404 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8)); 9405 9406 if (((phy->req_line_speed == SPEED_AUTO_NEG) && 9407 (phy->speed_cap_mask & 9408 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || 9409 (phy->req_line_speed == SPEED_1000)) { 9410 an_1000_val |= (1<<8); 9411 autoneg_val |= (1<<9 | 1<<12); 9412 if (phy->req_duplex == DUPLEX_FULL) 9413 an_1000_val |= (1<<9); 9414 DP(NETIF_MSG_LINK, "Advertising 1G\n"); 9415 } else 9416 an_1000_val &= ~((1<<8) | (1<<9)); 9417 9418 bnx2x_cl45_write(bp, phy, 9419 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL, 9420 an_1000_val); 9421 9422 /* set 100 speed advertisement */ 9423 if ((phy->req_line_speed == SPEED_AUTO_NEG) && 9424 (phy->speed_cap_mask & 9425 (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL | 9426 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))) { 9427 an_10_100_val |= (1<<7); 9428 /* Enable autoneg and restart autoneg for legacy speeds */ 9429 autoneg_val |= (1<<9 | 1<<12); 9430 9431 if (phy->req_duplex == DUPLEX_FULL) 9432 an_10_100_val |= (1<<8); 9433 DP(NETIF_MSG_LINK, "Advertising 100M\n"); 9434 } 9435 /* set 10 speed advertisement */ 9436 if (((phy->req_line_speed == SPEED_AUTO_NEG) && 9437 (phy->speed_cap_mask & 9438 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL | 9439 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) && 9440 (phy->supported & 9441 (SUPPORTED_10baseT_Half | 9442 SUPPORTED_10baseT_Full)))) { 9443 an_10_100_val |= (1<<5); 9444 autoneg_val |= (1<<9 | 1<<12); 9445 if (phy->req_duplex == DUPLEX_FULL) 9446 an_10_100_val |= (1<<6); 9447 DP(NETIF_MSG_LINK, "Advertising 10M\n"); 9448 } 9449 9450 /* Only 10/100 are allowed to work in FORCE mode */ 9451 if ((phy->req_line_speed == SPEED_100) && 9452 (phy->supported & 9453 (SUPPORTED_100baseT_Half | 9454 SUPPORTED_100baseT_Full))) { 9455 autoneg_val |= (1<<13); 9456 /* Enabled AUTO-MDIX when autoneg is disabled */ 9457 bnx2x_cl45_write(bp, phy, 9458 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL, 9459 (1<<15 | 1<<9 | 7<<0)); 9460 /* The PHY needs this set even for forced link. */ 9461 an_10_100_val |= (1<<8) | (1<<7); 9462 DP(NETIF_MSG_LINK, "Setting 100M force\n"); 9463 } 9464 if ((phy->req_line_speed == SPEED_10) && 9465 (phy->supported & 9466 (SUPPORTED_10baseT_Half | 9467 SUPPORTED_10baseT_Full))) { 9468 /* Enabled AUTO-MDIX when autoneg is disabled */ 9469 bnx2x_cl45_write(bp, phy, 9470 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL, 9471 (1<<15 | 1<<9 | 7<<0)); 9472 DP(NETIF_MSG_LINK, "Setting 10M force\n"); 9473 } 9474 9475 bnx2x_cl45_write(bp, phy, 9476 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV, 9477 an_10_100_val); 9478 9479 if (phy->req_duplex == DUPLEX_FULL) 9480 autoneg_val |= (1<<8); 9481 9482 /* Always write this if this is not 84833. 9483 * For 84833, write it only when it's a forced speed. 9484 */ 9485 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || 9486 ((autoneg_val & (1<<12)) == 0)) 9487 bnx2x_cl45_write(bp, phy, 9488 MDIO_AN_DEVAD, 9489 MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val); 9490 9491 if (((phy->req_line_speed == SPEED_AUTO_NEG) && 9492 (phy->speed_cap_mask & 9493 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) || 9494 (phy->req_line_speed == SPEED_10000)) { 9495 DP(NETIF_MSG_LINK, "Advertising 10G\n"); 9496 /* Restart autoneg for 10G*/ 9497 9498 bnx2x_cl45_read(bp, phy, 9499 MDIO_AN_DEVAD, 9500 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, 9501 &an_10g_val); 9502 bnx2x_cl45_write(bp, phy, 9503 MDIO_AN_DEVAD, 9504 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, 9505 an_10g_val | 0x1000); 9506 bnx2x_cl45_write(bp, phy, 9507 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 9508 0x3200); 9509 } else 9510 bnx2x_cl45_write(bp, phy, 9511 MDIO_AN_DEVAD, 9512 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, 9513 1); 9514 9515 return 0; 9516 } 9517 9518 static int bnx2x_8481_config_init(struct bnx2x_phy *phy, 9519 struct link_params *params, 9520 struct link_vars *vars) 9521 { 9522 struct bnx2x *bp = params->bp; 9523 /* Restore normal power mode*/ 9524 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 9525 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); 9526 9527 /* HW reset */ 9528 bnx2x_ext_phy_hw_reset(bp, params->port); 9529 bnx2x_wait_reset_complete(bp, phy, params); 9530 9531 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); 9532 return bnx2x_848xx_cmn_config_init(phy, params, vars); 9533 } 9534 9535 #define PHY84833_CMDHDLR_WAIT 300 9536 #define PHY84833_CMDHDLR_MAX_ARGS 5 9537 static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy, 9538 struct link_params *params, 9539 u16 fw_cmd, 9540 u16 cmd_args[], int argc) 9541 { 9542 int idx; 9543 u16 val; 9544 struct bnx2x *bp = params->bp; 9545 /* Write CMD_OPEN_OVERRIDE to STATUS reg */ 9546 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, 9547 MDIO_84833_CMD_HDLR_STATUS, 9548 PHY84833_STATUS_CMD_OPEN_OVERRIDE); 9549 for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) { 9550 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 9551 MDIO_84833_CMD_HDLR_STATUS, &val); 9552 if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS) 9553 break; 9554 usleep_range(1000, 2000); 9555 } 9556 if (idx >= PHY84833_CMDHDLR_WAIT) { 9557 DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n"); 9558 return -EINVAL; 9559 } 9560 9561 /* Prepare argument(s) and issue command */ 9562 for (idx = 0; idx < argc; idx++) { 9563 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, 9564 MDIO_84833_CMD_HDLR_DATA1 + idx, 9565 cmd_args[idx]); 9566 } 9567 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, 9568 MDIO_84833_CMD_HDLR_COMMAND, fw_cmd); 9569 for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) { 9570 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 9571 MDIO_84833_CMD_HDLR_STATUS, &val); 9572 if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) || 9573 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) 9574 break; 9575 usleep_range(1000, 2000); 9576 } 9577 if ((idx >= PHY84833_CMDHDLR_WAIT) || 9578 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) { 9579 DP(NETIF_MSG_LINK, "FW cmd failed.\n"); 9580 return -EINVAL; 9581 } 9582 /* Gather returning data */ 9583 for (idx = 0; idx < argc; idx++) { 9584 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 9585 MDIO_84833_CMD_HDLR_DATA1 + idx, 9586 &cmd_args[idx]); 9587 } 9588 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, 9589 MDIO_84833_CMD_HDLR_STATUS, 9590 PHY84833_STATUS_CMD_CLEAR_COMPLETE); 9591 return 0; 9592 } 9593 9594 9595 static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy, 9596 struct link_params *params, 9597 struct link_vars *vars) 9598 { 9599 u32 pair_swap; 9600 u16 data[PHY84833_CMDHDLR_MAX_ARGS]; 9601 int status; 9602 struct bnx2x *bp = params->bp; 9603 9604 /* Check for configuration. */ 9605 pair_swap = REG_RD(bp, params->shmem_base + 9606 offsetof(struct shmem_region, 9607 dev_info.port_hw_config[params->port].xgbt_phy_cfg)) & 9608 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK; 9609 9610 if (pair_swap == 0) 9611 return 0; 9612 9613 /* Only the second argument is used for this command */ 9614 data[1] = (u16)pair_swap; 9615 9616 status = bnx2x_84833_cmd_hdlr(phy, params, 9617 PHY84833_CMD_SET_PAIR_SWAP, data, PHY84833_CMDHDLR_MAX_ARGS); 9618 if (status == 0) 9619 DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data[1]); 9620 9621 return status; 9622 } 9623 9624 static u8 bnx2x_84833_get_reset_gpios(struct bnx2x *bp, 9625 u32 shmem_base_path[], 9626 u32 chip_id) 9627 { 9628 u32 reset_pin[2]; 9629 u32 idx; 9630 u8 reset_gpios; 9631 if (CHIP_IS_E3(bp)) { 9632 /* Assume that these will be GPIOs, not EPIOs. */ 9633 for (idx = 0; idx < 2; idx++) { 9634 /* Map config param to register bit. */ 9635 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] + 9636 offsetof(struct shmem_region, 9637 dev_info.port_hw_config[0].e3_cmn_pin_cfg)); 9638 reset_pin[idx] = (reset_pin[idx] & 9639 PORT_HW_CFG_E3_PHY_RESET_MASK) >> 9640 PORT_HW_CFG_E3_PHY_RESET_SHIFT; 9641 reset_pin[idx] -= PIN_CFG_GPIO0_P0; 9642 reset_pin[idx] = (1 << reset_pin[idx]); 9643 } 9644 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]); 9645 } else { 9646 /* E2, look from diff place of shmem. */ 9647 for (idx = 0; idx < 2; idx++) { 9648 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] + 9649 offsetof(struct shmem_region, 9650 dev_info.port_hw_config[0].default_cfg)); 9651 reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK; 9652 reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0; 9653 reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT; 9654 reset_pin[idx] = (1 << reset_pin[idx]); 9655 } 9656 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]); 9657 } 9658 9659 return reset_gpios; 9660 } 9661 9662 static int bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy, 9663 struct link_params *params) 9664 { 9665 struct bnx2x *bp = params->bp; 9666 u8 reset_gpios; 9667 u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base + 9668 offsetof(struct shmem2_region, 9669 other_shmem_base_addr)); 9670 9671 u32 shmem_base_path[2]; 9672 9673 /* Work around for 84833 LED failure inside RESET status */ 9674 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 9675 MDIO_AN_REG_8481_LEGACY_MII_CTRL, 9676 MDIO_AN_REG_8481_MII_CTRL_FORCE_1G); 9677 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 9678 MDIO_AN_REG_8481_1G_100T_EXT_CTRL, 9679 MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF); 9680 9681 shmem_base_path[0] = params->shmem_base; 9682 shmem_base_path[1] = other_shmem_base_addr; 9683 9684 reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, 9685 params->chip_id); 9686 9687 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW); 9688 udelay(10); 9689 DP(NETIF_MSG_LINK, "84833 hw reset on pin values 0x%x\n", 9690 reset_gpios); 9691 9692 return 0; 9693 } 9694 9695 static int bnx2x_8483x_disable_eee(struct bnx2x_phy *phy, 9696 struct link_params *params, 9697 struct link_vars *vars) 9698 { 9699 int rc; 9700 struct bnx2x *bp = params->bp; 9701 u16 cmd_args = 0; 9702 9703 DP(NETIF_MSG_LINK, "Don't Advertise 10GBase-T EEE\n"); 9704 9705 /* Prevent Phy from working in EEE and advertising it */ 9706 rc = bnx2x_84833_cmd_hdlr(phy, params, 9707 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1); 9708 if (rc) { 9709 DP(NETIF_MSG_LINK, "EEE disable failed.\n"); 9710 return rc; 9711 } 9712 9713 return bnx2x_eee_disable(phy, params, vars); 9714 } 9715 9716 static int bnx2x_8483x_enable_eee(struct bnx2x_phy *phy, 9717 struct link_params *params, 9718 struct link_vars *vars) 9719 { 9720 int rc; 9721 struct bnx2x *bp = params->bp; 9722 u16 cmd_args = 1; 9723 9724 rc = bnx2x_84833_cmd_hdlr(phy, params, 9725 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1); 9726 if (rc) { 9727 DP(NETIF_MSG_LINK, "EEE enable failed.\n"); 9728 return rc; 9729 } 9730 9731 return bnx2x_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV); 9732 } 9733 9734 #define PHY84833_CONSTANT_LATENCY 1193 9735 static int bnx2x_848x3_config_init(struct bnx2x_phy *phy, 9736 struct link_params *params, 9737 struct link_vars *vars) 9738 { 9739 struct bnx2x *bp = params->bp; 9740 u8 port, initialize = 1; 9741 u16 val; 9742 u32 actual_phy_selection, cms_enable; 9743 u16 cmd_args[PHY84833_CMDHDLR_MAX_ARGS]; 9744 int rc = 0; 9745 9746 usleep_range(1000, 2000); 9747 9748 if (!(CHIP_IS_E1x(bp))) 9749 port = BP_PATH(bp); 9750 else 9751 port = params->port; 9752 9753 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { 9754 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3, 9755 MISC_REGISTERS_GPIO_OUTPUT_HIGH, 9756 port); 9757 } else { 9758 /* MDIO reset */ 9759 bnx2x_cl45_write(bp, phy, 9760 MDIO_PMA_DEVAD, 9761 MDIO_PMA_REG_CTRL, 0x8000); 9762 } 9763 9764 bnx2x_wait_reset_complete(bp, phy, params); 9765 9766 /* Wait for GPHY to come out of reset */ 9767 msleep(50); 9768 if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) { 9769 /* BCM84823 requires that XGXS links up first @ 10G for normal 9770 * behavior. 9771 */ 9772 u16 temp; 9773 temp = vars->line_speed; 9774 vars->line_speed = SPEED_10000; 9775 bnx2x_set_autoneg(¶ms->phy[INT_PHY], params, vars, 0); 9776 bnx2x_program_serdes(¶ms->phy[INT_PHY], params, vars); 9777 vars->line_speed = temp; 9778 } 9779 9780 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 9781 MDIO_CTL_REG_84823_MEDIA, &val); 9782 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK | 9783 MDIO_CTL_REG_84823_MEDIA_LINE_MASK | 9784 MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN | 9785 MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK | 9786 MDIO_CTL_REG_84823_MEDIA_FIBER_1G); 9787 9788 if (CHIP_IS_E3(bp)) { 9789 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK | 9790 MDIO_CTL_REG_84823_MEDIA_LINE_MASK); 9791 } else { 9792 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI | 9793 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L); 9794 } 9795 9796 actual_phy_selection = bnx2x_phy_selection(params); 9797 9798 switch (actual_phy_selection) { 9799 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT: 9800 /* Do nothing. Essentially this is like the priority copper */ 9801 break; 9802 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: 9803 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER; 9804 break; 9805 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: 9806 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER; 9807 break; 9808 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY: 9809 /* Do nothing here. The first PHY won't be initialized at all */ 9810 break; 9811 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY: 9812 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN; 9813 initialize = 0; 9814 break; 9815 } 9816 if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000) 9817 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G; 9818 9819 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, 9820 MDIO_CTL_REG_84823_MEDIA, val); 9821 DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n", 9822 params->multi_phy_config, val); 9823 9824 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) { 9825 bnx2x_84833_pair_swap_cfg(phy, params, vars); 9826 9827 /* Keep AutogrEEEn disabled. */ 9828 cmd_args[0] = 0x0; 9829 cmd_args[1] = 0x0; 9830 cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1; 9831 cmd_args[3] = PHY84833_CONSTANT_LATENCY; 9832 rc = bnx2x_84833_cmd_hdlr(phy, params, 9833 PHY84833_CMD_SET_EEE_MODE, cmd_args, 9834 PHY84833_CMDHDLR_MAX_ARGS); 9835 if (rc) 9836 DP(NETIF_MSG_LINK, "Cfg AutogrEEEn failed.\n"); 9837 } 9838 if (initialize) 9839 rc = bnx2x_848xx_cmn_config_init(phy, params, vars); 9840 else 9841 bnx2x_save_848xx_spirom_version(phy, bp, params->port); 9842 /* 84833 PHY has a better feature and doesn't need to support this. */ 9843 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { 9844 cms_enable = REG_RD(bp, params->shmem_base + 9845 offsetof(struct shmem_region, 9846 dev_info.port_hw_config[params->port].default_cfg)) & 9847 PORT_HW_CFG_ENABLE_CMS_MASK; 9848 9849 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 9850 MDIO_CTL_REG_84823_USER_CTRL_REG, &val); 9851 if (cms_enable) 9852 val |= MDIO_CTL_REG_84823_USER_CTRL_CMS; 9853 else 9854 val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS; 9855 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, 9856 MDIO_CTL_REG_84823_USER_CTRL_REG, val); 9857 } 9858 9859 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 9860 MDIO_84833_TOP_CFG_FW_REV, &val); 9861 9862 /* Configure EEE support */ 9863 if ((val >= MDIO_84833_TOP_CFG_FW_EEE) && 9864 (val != MDIO_84833_TOP_CFG_FW_NO_EEE) && 9865 bnx2x_eee_has_cap(params)) { 9866 rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_10G_ADV); 9867 if (rc) { 9868 DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n"); 9869 bnx2x_8483x_disable_eee(phy, params, vars); 9870 return rc; 9871 } 9872 9873 if ((params->req_duplex[actual_phy_selection] == DUPLEX_FULL) && 9874 (params->eee_mode & EEE_MODE_ADV_LPI) && 9875 (bnx2x_eee_calc_timer(params) || 9876 !(params->eee_mode & EEE_MODE_ENABLE_LPI))) 9877 rc = bnx2x_8483x_enable_eee(phy, params, vars); 9878 else 9879 rc = bnx2x_8483x_disable_eee(phy, params, vars); 9880 if (rc) { 9881 DP(NETIF_MSG_LINK, "Failed to set EEE advertisment\n"); 9882 return rc; 9883 } 9884 } else { 9885 vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK; 9886 } 9887 9888 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) { 9889 /* Bring PHY out of super isolate mode as the final step. */ 9890 bnx2x_cl45_read(bp, phy, 9891 MDIO_CTL_DEVAD, 9892 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val); 9893 val &= ~MDIO_84833_SUPER_ISOLATE; 9894 bnx2x_cl45_write(bp, phy, 9895 MDIO_CTL_DEVAD, 9896 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val); 9897 } 9898 return rc; 9899 } 9900 9901 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy, 9902 struct link_params *params, 9903 struct link_vars *vars) 9904 { 9905 struct bnx2x *bp = params->bp; 9906 u16 val, val1, val2; 9907 u8 link_up = 0; 9908 9909 9910 /* Check 10G-BaseT link status */ 9911 /* Check PMD signal ok */ 9912 bnx2x_cl45_read(bp, phy, 9913 MDIO_AN_DEVAD, 0xFFFA, &val1); 9914 bnx2x_cl45_read(bp, phy, 9915 MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL, 9916 &val2); 9917 DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2); 9918 9919 /* Check link 10G */ 9920 if (val2 & (1<<11)) { 9921 vars->line_speed = SPEED_10000; 9922 vars->duplex = DUPLEX_FULL; 9923 link_up = 1; 9924 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); 9925 } else { /* Check Legacy speed link */ 9926 u16 legacy_status, legacy_speed; 9927 9928 /* Enable expansion register 0x42 (Operation mode status) */ 9929 bnx2x_cl45_write(bp, phy, 9930 MDIO_AN_DEVAD, 9931 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42); 9932 9933 /* Get legacy speed operation status */ 9934 bnx2x_cl45_read(bp, phy, 9935 MDIO_AN_DEVAD, 9936 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW, 9937 &legacy_status); 9938 9939 DP(NETIF_MSG_LINK, "Legacy speed status = 0x%x\n", 9940 legacy_status); 9941 link_up = ((legacy_status & (1<<11)) == (1<<11)); 9942 legacy_speed = (legacy_status & (3<<9)); 9943 if (legacy_speed == (0<<9)) 9944 vars->line_speed = SPEED_10; 9945 else if (legacy_speed == (1<<9)) 9946 vars->line_speed = SPEED_100; 9947 else if (legacy_speed == (2<<9)) 9948 vars->line_speed = SPEED_1000; 9949 else { /* Should not happen: Treat as link down */ 9950 vars->line_speed = 0; 9951 link_up = 0; 9952 } 9953 9954 if (link_up) { 9955 if (legacy_status & (1<<8)) 9956 vars->duplex = DUPLEX_FULL; 9957 else 9958 vars->duplex = DUPLEX_HALF; 9959 9960 DP(NETIF_MSG_LINK, 9961 "Link is up in %dMbps, is_duplex_full= %d\n", 9962 vars->line_speed, 9963 (vars->duplex == DUPLEX_FULL)); 9964 /* Check legacy speed AN resolution */ 9965 bnx2x_cl45_read(bp, phy, 9966 MDIO_AN_DEVAD, 9967 MDIO_AN_REG_8481_LEGACY_MII_STATUS, 9968 &val); 9969 if (val & (1<<5)) 9970 vars->link_status |= 9971 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 9972 bnx2x_cl45_read(bp, phy, 9973 MDIO_AN_DEVAD, 9974 MDIO_AN_REG_8481_LEGACY_AN_EXPANSION, 9975 &val); 9976 if ((val & (1<<0)) == 0) 9977 vars->link_status |= 9978 LINK_STATUS_PARALLEL_DETECTION_USED; 9979 } 9980 } 9981 if (link_up) { 9982 DP(NETIF_MSG_LINK, "BCM848x3: link speed is %d\n", 9983 vars->line_speed); 9984 bnx2x_ext_phy_resolve_fc(phy, params, vars); 9985 9986 /* Read LP advertised speeds */ 9987 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 9988 MDIO_AN_REG_CL37_FC_LP, &val); 9989 if (val & (1<<5)) 9990 vars->link_status |= 9991 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE; 9992 if (val & (1<<6)) 9993 vars->link_status |= 9994 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE; 9995 if (val & (1<<7)) 9996 vars->link_status |= 9997 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE; 9998 if (val & (1<<8)) 9999 vars->link_status |= 10000 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE; 10001 if (val & (1<<9)) 10002 vars->link_status |= 10003 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE; 10004 10005 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 10006 MDIO_AN_REG_1000T_STATUS, &val); 10007 10008 if (val & (1<<10)) 10009 vars->link_status |= 10010 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE; 10011 if (val & (1<<11)) 10012 vars->link_status |= 10013 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 10014 10015 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, 10016 MDIO_AN_REG_MASTER_STATUS, &val); 10017 10018 if (val & (1<<11)) 10019 vars->link_status |= 10020 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 10021 10022 /* Determine if EEE was negotiated */ 10023 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) 10024 bnx2x_eee_an_resolve(phy, params, vars); 10025 } 10026 10027 return link_up; 10028 } 10029 10030 10031 static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len) 10032 { 10033 int status = 0; 10034 u32 spirom_ver; 10035 spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F); 10036 status = bnx2x_format_ver(spirom_ver, str, len); 10037 return status; 10038 } 10039 10040 static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy, 10041 struct link_params *params) 10042 { 10043 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, 10044 MISC_REGISTERS_GPIO_OUTPUT_LOW, 0); 10045 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, 10046 MISC_REGISTERS_GPIO_OUTPUT_LOW, 1); 10047 } 10048 10049 static void bnx2x_8481_link_reset(struct bnx2x_phy *phy, 10050 struct link_params *params) 10051 { 10052 bnx2x_cl45_write(params->bp, phy, 10053 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000); 10054 bnx2x_cl45_write(params->bp, phy, 10055 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1); 10056 } 10057 10058 static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy, 10059 struct link_params *params) 10060 { 10061 struct bnx2x *bp = params->bp; 10062 u8 port; 10063 u16 val16; 10064 10065 if (!(CHIP_IS_E1x(bp))) 10066 port = BP_PATH(bp); 10067 else 10068 port = params->port; 10069 10070 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { 10071 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3, 10072 MISC_REGISTERS_GPIO_OUTPUT_LOW, 10073 port); 10074 } else { 10075 bnx2x_cl45_read(bp, phy, 10076 MDIO_CTL_DEVAD, 10077 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16); 10078 val16 |= MDIO_84833_SUPER_ISOLATE; 10079 bnx2x_cl45_write(bp, phy, 10080 MDIO_CTL_DEVAD, 10081 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16); 10082 } 10083 } 10084 10085 static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy, 10086 struct link_params *params, u8 mode) 10087 { 10088 struct bnx2x *bp = params->bp; 10089 u16 val; 10090 u8 port; 10091 10092 if (!(CHIP_IS_E1x(bp))) 10093 port = BP_PATH(bp); 10094 else 10095 port = params->port; 10096 10097 switch (mode) { 10098 case LED_MODE_OFF: 10099 10100 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port); 10101 10102 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == 10103 SHARED_HW_CFG_LED_EXTPHY1) { 10104 10105 /* Set LED masks */ 10106 bnx2x_cl45_write(bp, phy, 10107 MDIO_PMA_DEVAD, 10108 MDIO_PMA_REG_8481_LED1_MASK, 10109 0x0); 10110 10111 bnx2x_cl45_write(bp, phy, 10112 MDIO_PMA_DEVAD, 10113 MDIO_PMA_REG_8481_LED2_MASK, 10114 0x0); 10115 10116 bnx2x_cl45_write(bp, phy, 10117 MDIO_PMA_DEVAD, 10118 MDIO_PMA_REG_8481_LED3_MASK, 10119 0x0); 10120 10121 bnx2x_cl45_write(bp, phy, 10122 MDIO_PMA_DEVAD, 10123 MDIO_PMA_REG_8481_LED5_MASK, 10124 0x0); 10125 10126 } else { 10127 bnx2x_cl45_write(bp, phy, 10128 MDIO_PMA_DEVAD, 10129 MDIO_PMA_REG_8481_LED1_MASK, 10130 0x0); 10131 } 10132 break; 10133 case LED_MODE_FRONT_PANEL_OFF: 10134 10135 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n", 10136 port); 10137 10138 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == 10139 SHARED_HW_CFG_LED_EXTPHY1) { 10140 10141 /* Set LED masks */ 10142 bnx2x_cl45_write(bp, phy, 10143 MDIO_PMA_DEVAD, 10144 MDIO_PMA_REG_8481_LED1_MASK, 10145 0x0); 10146 10147 bnx2x_cl45_write(bp, phy, 10148 MDIO_PMA_DEVAD, 10149 MDIO_PMA_REG_8481_LED2_MASK, 10150 0x0); 10151 10152 bnx2x_cl45_write(bp, phy, 10153 MDIO_PMA_DEVAD, 10154 MDIO_PMA_REG_8481_LED3_MASK, 10155 0x0); 10156 10157 bnx2x_cl45_write(bp, phy, 10158 MDIO_PMA_DEVAD, 10159 MDIO_PMA_REG_8481_LED5_MASK, 10160 0x20); 10161 10162 } else { 10163 bnx2x_cl45_write(bp, phy, 10164 MDIO_PMA_DEVAD, 10165 MDIO_PMA_REG_8481_LED1_MASK, 10166 0x0); 10167 } 10168 break; 10169 case LED_MODE_ON: 10170 10171 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port); 10172 10173 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == 10174 SHARED_HW_CFG_LED_EXTPHY1) { 10175 /* Set control reg */ 10176 bnx2x_cl45_read(bp, phy, 10177 MDIO_PMA_DEVAD, 10178 MDIO_PMA_REG_8481_LINK_SIGNAL, 10179 &val); 10180 val &= 0x8000; 10181 val |= 0x2492; 10182 10183 bnx2x_cl45_write(bp, phy, 10184 MDIO_PMA_DEVAD, 10185 MDIO_PMA_REG_8481_LINK_SIGNAL, 10186 val); 10187 10188 /* Set LED masks */ 10189 bnx2x_cl45_write(bp, phy, 10190 MDIO_PMA_DEVAD, 10191 MDIO_PMA_REG_8481_LED1_MASK, 10192 0x0); 10193 10194 bnx2x_cl45_write(bp, phy, 10195 MDIO_PMA_DEVAD, 10196 MDIO_PMA_REG_8481_LED2_MASK, 10197 0x20); 10198 10199 bnx2x_cl45_write(bp, phy, 10200 MDIO_PMA_DEVAD, 10201 MDIO_PMA_REG_8481_LED3_MASK, 10202 0x20); 10203 10204 bnx2x_cl45_write(bp, phy, 10205 MDIO_PMA_DEVAD, 10206 MDIO_PMA_REG_8481_LED5_MASK, 10207 0x0); 10208 } else { 10209 bnx2x_cl45_write(bp, phy, 10210 MDIO_PMA_DEVAD, 10211 MDIO_PMA_REG_8481_LED1_MASK, 10212 0x20); 10213 } 10214 break; 10215 10216 case LED_MODE_OPER: 10217 10218 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port); 10219 10220 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == 10221 SHARED_HW_CFG_LED_EXTPHY1) { 10222 10223 /* Set control reg */ 10224 bnx2x_cl45_read(bp, phy, 10225 MDIO_PMA_DEVAD, 10226 MDIO_PMA_REG_8481_LINK_SIGNAL, 10227 &val); 10228 10229 if (!((val & 10230 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK) 10231 >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) { 10232 DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n"); 10233 bnx2x_cl45_write(bp, phy, 10234 MDIO_PMA_DEVAD, 10235 MDIO_PMA_REG_8481_LINK_SIGNAL, 10236 0xa492); 10237 } 10238 10239 /* Set LED masks */ 10240 bnx2x_cl45_write(bp, phy, 10241 MDIO_PMA_DEVAD, 10242 MDIO_PMA_REG_8481_LED1_MASK, 10243 0x10); 10244 10245 bnx2x_cl45_write(bp, phy, 10246 MDIO_PMA_DEVAD, 10247 MDIO_PMA_REG_8481_LED2_MASK, 10248 0x80); 10249 10250 bnx2x_cl45_write(bp, phy, 10251 MDIO_PMA_DEVAD, 10252 MDIO_PMA_REG_8481_LED3_MASK, 10253 0x98); 10254 10255 bnx2x_cl45_write(bp, phy, 10256 MDIO_PMA_DEVAD, 10257 MDIO_PMA_REG_8481_LED5_MASK, 10258 0x40); 10259 10260 } else { 10261 bnx2x_cl45_write(bp, phy, 10262 MDIO_PMA_DEVAD, 10263 MDIO_PMA_REG_8481_LED1_MASK, 10264 0x80); 10265 10266 /* Tell LED3 to blink on source */ 10267 bnx2x_cl45_read(bp, phy, 10268 MDIO_PMA_DEVAD, 10269 MDIO_PMA_REG_8481_LINK_SIGNAL, 10270 &val); 10271 val &= ~(7<<6); 10272 val |= (1<<6); /* A83B[8:6]= 1 */ 10273 bnx2x_cl45_write(bp, phy, 10274 MDIO_PMA_DEVAD, 10275 MDIO_PMA_REG_8481_LINK_SIGNAL, 10276 val); 10277 } 10278 break; 10279 } 10280 10281 /* This is a workaround for E3+84833 until autoneg 10282 * restart is fixed in f/w 10283 */ 10284 if (CHIP_IS_E3(bp)) { 10285 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 10286 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val); 10287 } 10288 } 10289 10290 /******************************************************************/ 10291 /* 54618SE PHY SECTION */ 10292 /******************************************************************/ 10293 static void bnx2x_54618se_specific_func(struct bnx2x_phy *phy, 10294 struct link_params *params, 10295 u32 action) 10296 { 10297 struct bnx2x *bp = params->bp; 10298 u16 temp; 10299 switch (action) { 10300 case PHY_INIT: 10301 /* Configure LED4: set to INTR (0x6). */ 10302 /* Accessing shadow register 0xe. */ 10303 bnx2x_cl22_write(bp, phy, 10304 MDIO_REG_GPHY_SHADOW, 10305 MDIO_REG_GPHY_SHADOW_LED_SEL2); 10306 bnx2x_cl22_read(bp, phy, 10307 MDIO_REG_GPHY_SHADOW, 10308 &temp); 10309 temp &= ~(0xf << 4); 10310 temp |= (0x6 << 4); 10311 bnx2x_cl22_write(bp, phy, 10312 MDIO_REG_GPHY_SHADOW, 10313 MDIO_REG_GPHY_SHADOW_WR_ENA | temp); 10314 /* Configure INTR based on link status change. */ 10315 bnx2x_cl22_write(bp, phy, 10316 MDIO_REG_INTR_MASK, 10317 ~MDIO_REG_INTR_MASK_LINK_STATUS); 10318 break; 10319 } 10320 } 10321 10322 static int bnx2x_54618se_config_init(struct bnx2x_phy *phy, 10323 struct link_params *params, 10324 struct link_vars *vars) 10325 { 10326 struct bnx2x *bp = params->bp; 10327 u8 port; 10328 u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp; 10329 u32 cfg_pin; 10330 10331 DP(NETIF_MSG_LINK, "54618SE cfg init\n"); 10332 usleep_range(1000, 2000); 10333 10334 /* This works with E3 only, no need to check the chip 10335 * before determining the port. 10336 */ 10337 port = params->port; 10338 10339 cfg_pin = (REG_RD(bp, params->shmem_base + 10340 offsetof(struct shmem_region, 10341 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & 10342 PORT_HW_CFG_E3_PHY_RESET_MASK) >> 10343 PORT_HW_CFG_E3_PHY_RESET_SHIFT; 10344 10345 /* Drive pin high to bring the GPHY out of reset. */ 10346 bnx2x_set_cfg_pin(bp, cfg_pin, 1); 10347 10348 /* wait for GPHY to reset */ 10349 msleep(50); 10350 10351 /* reset phy */ 10352 bnx2x_cl22_write(bp, phy, 10353 MDIO_PMA_REG_CTRL, 0x8000); 10354 bnx2x_wait_reset_complete(bp, phy, params); 10355 10356 /* Wait for GPHY to reset */ 10357 msleep(50); 10358 10359 10360 bnx2x_54618se_specific_func(phy, params, PHY_INIT); 10361 /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */ 10362 bnx2x_cl22_write(bp, phy, 10363 MDIO_REG_GPHY_SHADOW, 10364 MDIO_REG_GPHY_SHADOW_AUTO_DET_MED); 10365 bnx2x_cl22_read(bp, phy, 10366 MDIO_REG_GPHY_SHADOW, 10367 &temp); 10368 temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD; 10369 bnx2x_cl22_write(bp, phy, 10370 MDIO_REG_GPHY_SHADOW, 10371 MDIO_REG_GPHY_SHADOW_WR_ENA | temp); 10372 10373 /* Set up fc */ 10374 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ 10375 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); 10376 fc_val = 0; 10377 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == 10378 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) 10379 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC; 10380 10381 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == 10382 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) 10383 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE; 10384 10385 /* Read all advertisement */ 10386 bnx2x_cl22_read(bp, phy, 10387 0x09, 10388 &an_1000_val); 10389 10390 bnx2x_cl22_read(bp, phy, 10391 0x04, 10392 &an_10_100_val); 10393 10394 bnx2x_cl22_read(bp, phy, 10395 MDIO_PMA_REG_CTRL, 10396 &autoneg_val); 10397 10398 /* Disable forced speed */ 10399 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13)); 10400 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) | 10401 (1<<11)); 10402 10403 if (((phy->req_line_speed == SPEED_AUTO_NEG) && 10404 (phy->speed_cap_mask & 10405 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || 10406 (phy->req_line_speed == SPEED_1000)) { 10407 an_1000_val |= (1<<8); 10408 autoneg_val |= (1<<9 | 1<<12); 10409 if (phy->req_duplex == DUPLEX_FULL) 10410 an_1000_val |= (1<<9); 10411 DP(NETIF_MSG_LINK, "Advertising 1G\n"); 10412 } else 10413 an_1000_val &= ~((1<<8) | (1<<9)); 10414 10415 bnx2x_cl22_write(bp, phy, 10416 0x09, 10417 an_1000_val); 10418 bnx2x_cl22_read(bp, phy, 10419 0x09, 10420 &an_1000_val); 10421 10422 /* Set 100 speed advertisement */ 10423 if (((phy->req_line_speed == SPEED_AUTO_NEG) && 10424 (phy->speed_cap_mask & 10425 (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL | 10426 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) { 10427 an_10_100_val |= (1<<7); 10428 /* Enable autoneg and restart autoneg for legacy speeds */ 10429 autoneg_val |= (1<<9 | 1<<12); 10430 10431 if (phy->req_duplex == DUPLEX_FULL) 10432 an_10_100_val |= (1<<8); 10433 DP(NETIF_MSG_LINK, "Advertising 100M\n"); 10434 } 10435 10436 /* Set 10 speed advertisement */ 10437 if (((phy->req_line_speed == SPEED_AUTO_NEG) && 10438 (phy->speed_cap_mask & 10439 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL | 10440 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) { 10441 an_10_100_val |= (1<<5); 10442 autoneg_val |= (1<<9 | 1<<12); 10443 if (phy->req_duplex == DUPLEX_FULL) 10444 an_10_100_val |= (1<<6); 10445 DP(NETIF_MSG_LINK, "Advertising 10M\n"); 10446 } 10447 10448 /* Only 10/100 are allowed to work in FORCE mode */ 10449 if (phy->req_line_speed == SPEED_100) { 10450 autoneg_val |= (1<<13); 10451 /* Enabled AUTO-MDIX when autoneg is disabled */ 10452 bnx2x_cl22_write(bp, phy, 10453 0x18, 10454 (1<<15 | 1<<9 | 7<<0)); 10455 DP(NETIF_MSG_LINK, "Setting 100M force\n"); 10456 } 10457 if (phy->req_line_speed == SPEED_10) { 10458 /* Enabled AUTO-MDIX when autoneg is disabled */ 10459 bnx2x_cl22_write(bp, phy, 10460 0x18, 10461 (1<<15 | 1<<9 | 7<<0)); 10462 DP(NETIF_MSG_LINK, "Setting 10M force\n"); 10463 } 10464 10465 if ((phy->flags & FLAGS_EEE) && bnx2x_eee_has_cap(params)) { 10466 int rc; 10467 10468 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS, 10469 MDIO_REG_GPHY_EXP_ACCESS_TOP | 10470 MDIO_REG_GPHY_EXP_TOP_2K_BUF); 10471 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp); 10472 temp &= 0xfffe; 10473 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp); 10474 10475 rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_1G_ADV); 10476 if (rc) { 10477 DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n"); 10478 bnx2x_eee_disable(phy, params, vars); 10479 } else if ((params->eee_mode & EEE_MODE_ADV_LPI) && 10480 (phy->req_duplex == DUPLEX_FULL) && 10481 (bnx2x_eee_calc_timer(params) || 10482 !(params->eee_mode & EEE_MODE_ENABLE_LPI))) { 10483 /* Need to advertise EEE only when requested, 10484 * and either no LPI assertion was requested, 10485 * or it was requested and a valid timer was set. 10486 * Also notice full duplex is required for EEE. 10487 */ 10488 bnx2x_eee_advertise(phy, params, vars, 10489 SHMEM_EEE_1G_ADV); 10490 } else { 10491 DP(NETIF_MSG_LINK, "Don't Advertise 1GBase-T EEE\n"); 10492 bnx2x_eee_disable(phy, params, vars); 10493 } 10494 } else { 10495 vars->eee_status &= ~SHMEM_EEE_1G_ADV << 10496 SHMEM_EEE_SUPPORTED_SHIFT; 10497 10498 if (phy->flags & FLAGS_EEE) { 10499 /* Handle legacy auto-grEEEn */ 10500 if (params->feature_config_flags & 10501 FEATURE_CONFIG_AUTOGREEEN_ENABLED) { 10502 temp = 6; 10503 DP(NETIF_MSG_LINK, "Enabling Auto-GrEEEn\n"); 10504 } else { 10505 temp = 0; 10506 DP(NETIF_MSG_LINK, "Don't Adv. EEE\n"); 10507 } 10508 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 10509 MDIO_AN_REG_EEE_ADV, temp); 10510 } 10511 } 10512 10513 bnx2x_cl22_write(bp, phy, 10514 0x04, 10515 an_10_100_val | fc_val); 10516 10517 if (phy->req_duplex == DUPLEX_FULL) 10518 autoneg_val |= (1<<8); 10519 10520 bnx2x_cl22_write(bp, phy, 10521 MDIO_PMA_REG_CTRL, autoneg_val); 10522 10523 return 0; 10524 } 10525 10526 10527 static void bnx2x_5461x_set_link_led(struct bnx2x_phy *phy, 10528 struct link_params *params, u8 mode) 10529 { 10530 struct bnx2x *bp = params->bp; 10531 u16 temp; 10532 10533 bnx2x_cl22_write(bp, phy, 10534 MDIO_REG_GPHY_SHADOW, 10535 MDIO_REG_GPHY_SHADOW_LED_SEL1); 10536 bnx2x_cl22_read(bp, phy, 10537 MDIO_REG_GPHY_SHADOW, 10538 &temp); 10539 temp &= 0xff00; 10540 10541 DP(NETIF_MSG_LINK, "54618x set link led (mode=%x)\n", mode); 10542 switch (mode) { 10543 case LED_MODE_FRONT_PANEL_OFF: 10544 case LED_MODE_OFF: 10545 temp |= 0x00ee; 10546 break; 10547 case LED_MODE_OPER: 10548 temp |= 0x0001; 10549 break; 10550 case LED_MODE_ON: 10551 temp |= 0x00ff; 10552 break; 10553 default: 10554 break; 10555 } 10556 bnx2x_cl22_write(bp, phy, 10557 MDIO_REG_GPHY_SHADOW, 10558 MDIO_REG_GPHY_SHADOW_WR_ENA | temp); 10559 return; 10560 } 10561 10562 10563 static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy, 10564 struct link_params *params) 10565 { 10566 struct bnx2x *bp = params->bp; 10567 u32 cfg_pin; 10568 u8 port; 10569 10570 /* In case of no EPIO routed to reset the GPHY, put it 10571 * in low power mode. 10572 */ 10573 bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800); 10574 /* This works with E3 only, no need to check the chip 10575 * before determining the port. 10576 */ 10577 port = params->port; 10578 cfg_pin = (REG_RD(bp, params->shmem_base + 10579 offsetof(struct shmem_region, 10580 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & 10581 PORT_HW_CFG_E3_PHY_RESET_MASK) >> 10582 PORT_HW_CFG_E3_PHY_RESET_SHIFT; 10583 10584 /* Drive pin low to put GPHY in reset. */ 10585 bnx2x_set_cfg_pin(bp, cfg_pin, 0); 10586 } 10587 10588 static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy, 10589 struct link_params *params, 10590 struct link_vars *vars) 10591 { 10592 struct bnx2x *bp = params->bp; 10593 u16 val; 10594 u8 link_up = 0; 10595 u16 legacy_status, legacy_speed; 10596 10597 /* Get speed operation status */ 10598 bnx2x_cl22_read(bp, phy, 10599 MDIO_REG_GPHY_AUX_STATUS, 10600 &legacy_status); 10601 DP(NETIF_MSG_LINK, "54618SE read_status: 0x%x\n", legacy_status); 10602 10603 /* Read status to clear the PHY interrupt. */ 10604 bnx2x_cl22_read(bp, phy, 10605 MDIO_REG_INTR_STATUS, 10606 &val); 10607 10608 link_up = ((legacy_status & (1<<2)) == (1<<2)); 10609 10610 if (link_up) { 10611 legacy_speed = (legacy_status & (7<<8)); 10612 if (legacy_speed == (7<<8)) { 10613 vars->line_speed = SPEED_1000; 10614 vars->duplex = DUPLEX_FULL; 10615 } else if (legacy_speed == (6<<8)) { 10616 vars->line_speed = SPEED_1000; 10617 vars->duplex = DUPLEX_HALF; 10618 } else if (legacy_speed == (5<<8)) { 10619 vars->line_speed = SPEED_100; 10620 vars->duplex = DUPLEX_FULL; 10621 } 10622 /* Omitting 100Base-T4 for now */ 10623 else if (legacy_speed == (3<<8)) { 10624 vars->line_speed = SPEED_100; 10625 vars->duplex = DUPLEX_HALF; 10626 } else if (legacy_speed == (2<<8)) { 10627 vars->line_speed = SPEED_10; 10628 vars->duplex = DUPLEX_FULL; 10629 } else if (legacy_speed == (1<<8)) { 10630 vars->line_speed = SPEED_10; 10631 vars->duplex = DUPLEX_HALF; 10632 } else /* Should not happen */ 10633 vars->line_speed = 0; 10634 10635 DP(NETIF_MSG_LINK, 10636 "Link is up in %dMbps, is_duplex_full= %d\n", 10637 vars->line_speed, 10638 (vars->duplex == DUPLEX_FULL)); 10639 10640 /* Check legacy speed AN resolution */ 10641 bnx2x_cl22_read(bp, phy, 10642 0x01, 10643 &val); 10644 if (val & (1<<5)) 10645 vars->link_status |= 10646 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 10647 bnx2x_cl22_read(bp, phy, 10648 0x06, 10649 &val); 10650 if ((val & (1<<0)) == 0) 10651 vars->link_status |= 10652 LINK_STATUS_PARALLEL_DETECTION_USED; 10653 10654 DP(NETIF_MSG_LINK, "BCM54618SE: link speed is %d\n", 10655 vars->line_speed); 10656 10657 bnx2x_ext_phy_resolve_fc(phy, params, vars); 10658 10659 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 10660 /* Report LP advertised speeds */ 10661 bnx2x_cl22_read(bp, phy, 0x5, &val); 10662 10663 if (val & (1<<5)) 10664 vars->link_status |= 10665 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE; 10666 if (val & (1<<6)) 10667 vars->link_status |= 10668 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE; 10669 if (val & (1<<7)) 10670 vars->link_status |= 10671 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE; 10672 if (val & (1<<8)) 10673 vars->link_status |= 10674 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE; 10675 if (val & (1<<9)) 10676 vars->link_status |= 10677 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE; 10678 10679 bnx2x_cl22_read(bp, phy, 0xa, &val); 10680 if (val & (1<<10)) 10681 vars->link_status |= 10682 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE; 10683 if (val & (1<<11)) 10684 vars->link_status |= 10685 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 10686 10687 if ((phy->flags & FLAGS_EEE) && 10688 bnx2x_eee_has_cap(params)) 10689 bnx2x_eee_an_resolve(phy, params, vars); 10690 } 10691 } 10692 return link_up; 10693 } 10694 10695 static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy, 10696 struct link_params *params) 10697 { 10698 struct bnx2x *bp = params->bp; 10699 u16 val; 10700 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; 10701 10702 DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54618se\n"); 10703 10704 /* Enable master/slave manual mmode and set to master */ 10705 /* mii write 9 [bits set 11 12] */ 10706 bnx2x_cl22_write(bp, phy, 0x09, 3<<11); 10707 10708 /* forced 1G and disable autoneg */ 10709 /* set val [mii read 0] */ 10710 /* set val [expr $val & [bits clear 6 12 13]] */ 10711 /* set val [expr $val | [bits set 6 8]] */ 10712 /* mii write 0 $val */ 10713 bnx2x_cl22_read(bp, phy, 0x00, &val); 10714 val &= ~((1<<6) | (1<<12) | (1<<13)); 10715 val |= (1<<6) | (1<<8); 10716 bnx2x_cl22_write(bp, phy, 0x00, val); 10717 10718 /* Set external loopback and Tx using 6dB coding */ 10719 /* mii write 0x18 7 */ 10720 /* set val [mii read 0x18] */ 10721 /* mii write 0x18 [expr $val | [bits set 10 15]] */ 10722 bnx2x_cl22_write(bp, phy, 0x18, 7); 10723 bnx2x_cl22_read(bp, phy, 0x18, &val); 10724 bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15)); 10725 10726 /* This register opens the gate for the UMAC despite its name */ 10727 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); 10728 10729 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame 10730 * length used by the MAC receive logic to check frames. 10731 */ 10732 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710); 10733 } 10734 10735 /******************************************************************/ 10736 /* SFX7101 PHY SECTION */ 10737 /******************************************************************/ 10738 static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy, 10739 struct link_params *params) 10740 { 10741 struct bnx2x *bp = params->bp; 10742 /* SFX7101_XGXS_TEST1 */ 10743 bnx2x_cl45_write(bp, phy, 10744 MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100); 10745 } 10746 10747 static int bnx2x_7101_config_init(struct bnx2x_phy *phy, 10748 struct link_params *params, 10749 struct link_vars *vars) 10750 { 10751 u16 fw_ver1, fw_ver2, val; 10752 struct bnx2x *bp = params->bp; 10753 DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n"); 10754 10755 /* Restore normal power mode*/ 10756 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 10757 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); 10758 /* HW reset */ 10759 bnx2x_ext_phy_hw_reset(bp, params->port); 10760 bnx2x_wait_reset_complete(bp, phy, params); 10761 10762 bnx2x_cl45_write(bp, phy, 10763 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1); 10764 DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n"); 10765 bnx2x_cl45_write(bp, phy, 10766 MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3)); 10767 10768 bnx2x_ext_phy_set_pause(params, phy, vars); 10769 /* Restart autoneg */ 10770 bnx2x_cl45_read(bp, phy, 10771 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val); 10772 val |= 0x200; 10773 bnx2x_cl45_write(bp, phy, 10774 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val); 10775 10776 /* Save spirom version */ 10777 bnx2x_cl45_read(bp, phy, 10778 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1); 10779 10780 bnx2x_cl45_read(bp, phy, 10781 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2); 10782 bnx2x_save_spirom_version(bp, params->port, 10783 (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr); 10784 return 0; 10785 } 10786 10787 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy, 10788 struct link_params *params, 10789 struct link_vars *vars) 10790 { 10791 struct bnx2x *bp = params->bp; 10792 u8 link_up; 10793 u16 val1, val2; 10794 bnx2x_cl45_read(bp, phy, 10795 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2); 10796 bnx2x_cl45_read(bp, phy, 10797 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); 10798 DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n", 10799 val2, val1); 10800 bnx2x_cl45_read(bp, phy, 10801 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); 10802 bnx2x_cl45_read(bp, phy, 10803 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); 10804 DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n", 10805 val2, val1); 10806 link_up = ((val1 & 4) == 4); 10807 /* If link is up print the AN outcome of the SFX7101 PHY */ 10808 if (link_up) { 10809 bnx2x_cl45_read(bp, phy, 10810 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS, 10811 &val2); 10812 vars->line_speed = SPEED_10000; 10813 vars->duplex = DUPLEX_FULL; 10814 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n", 10815 val2, (val2 & (1<<14))); 10816 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); 10817 bnx2x_ext_phy_resolve_fc(phy, params, vars); 10818 10819 /* Read LP advertised speeds */ 10820 if (val2 & (1<<11)) 10821 vars->link_status |= 10822 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 10823 } 10824 return link_up; 10825 } 10826 10827 static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len) 10828 { 10829 if (*len < 5) 10830 return -EINVAL; 10831 str[0] = (spirom_ver & 0xFF); 10832 str[1] = (spirom_ver & 0xFF00) >> 8; 10833 str[2] = (spirom_ver & 0xFF0000) >> 16; 10834 str[3] = (spirom_ver & 0xFF000000) >> 24; 10835 str[4] = '\0'; 10836 *len -= 5; 10837 return 0; 10838 } 10839 10840 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy) 10841 { 10842 u16 val, cnt; 10843 10844 bnx2x_cl45_read(bp, phy, 10845 MDIO_PMA_DEVAD, 10846 MDIO_PMA_REG_7101_RESET, &val); 10847 10848 for (cnt = 0; cnt < 10; cnt++) { 10849 msleep(50); 10850 /* Writes a self-clearing reset */ 10851 bnx2x_cl45_write(bp, phy, 10852 MDIO_PMA_DEVAD, 10853 MDIO_PMA_REG_7101_RESET, 10854 (val | (1<<15))); 10855 /* Wait for clear */ 10856 bnx2x_cl45_read(bp, phy, 10857 MDIO_PMA_DEVAD, 10858 MDIO_PMA_REG_7101_RESET, &val); 10859 10860 if ((val & (1<<15)) == 0) 10861 break; 10862 } 10863 } 10864 10865 static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy, 10866 struct link_params *params) { 10867 /* Low power mode is controlled by GPIO 2 */ 10868 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2, 10869 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port); 10870 /* The PHY reset is controlled by GPIO 1 */ 10871 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, 10872 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port); 10873 } 10874 10875 static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy, 10876 struct link_params *params, u8 mode) 10877 { 10878 u16 val = 0; 10879 struct bnx2x *bp = params->bp; 10880 switch (mode) { 10881 case LED_MODE_FRONT_PANEL_OFF: 10882 case LED_MODE_OFF: 10883 val = 2; 10884 break; 10885 case LED_MODE_ON: 10886 val = 1; 10887 break; 10888 case LED_MODE_OPER: 10889 val = 0; 10890 break; 10891 } 10892 bnx2x_cl45_write(bp, phy, 10893 MDIO_PMA_DEVAD, 10894 MDIO_PMA_REG_7107_LINK_LED_CNTL, 10895 val); 10896 } 10897 10898 /******************************************************************/ 10899 /* STATIC PHY DECLARATION */ 10900 /******************************************************************/ 10901 10902 static struct bnx2x_phy phy_null = { 10903 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN, 10904 .addr = 0, 10905 .def_md_devad = 0, 10906 .flags = FLAGS_INIT_XGXS_FIRST, 10907 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 10908 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 10909 .mdio_ctrl = 0, 10910 .supported = 0, 10911 .media_type = ETH_PHY_NOT_PRESENT, 10912 .ver_addr = 0, 10913 .req_flow_ctrl = 0, 10914 .req_line_speed = 0, 10915 .speed_cap_mask = 0, 10916 .req_duplex = 0, 10917 .rsrv = 0, 10918 .config_init = (config_init_t)NULL, 10919 .read_status = (read_status_t)NULL, 10920 .link_reset = (link_reset_t)NULL, 10921 .config_loopback = (config_loopback_t)NULL, 10922 .format_fw_ver = (format_fw_ver_t)NULL, 10923 .hw_reset = (hw_reset_t)NULL, 10924 .set_link_led = (set_link_led_t)NULL, 10925 .phy_specific_func = (phy_specific_func_t)NULL 10926 }; 10927 10928 static struct bnx2x_phy phy_serdes = { 10929 .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT, 10930 .addr = 0xff, 10931 .def_md_devad = 0, 10932 .flags = 0, 10933 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 10934 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 10935 .mdio_ctrl = 0, 10936 .supported = (SUPPORTED_10baseT_Half | 10937 SUPPORTED_10baseT_Full | 10938 SUPPORTED_100baseT_Half | 10939 SUPPORTED_100baseT_Full | 10940 SUPPORTED_1000baseT_Full | 10941 SUPPORTED_2500baseX_Full | 10942 SUPPORTED_TP | 10943 SUPPORTED_Autoneg | 10944 SUPPORTED_Pause | 10945 SUPPORTED_Asym_Pause), 10946 .media_type = ETH_PHY_BASE_T, 10947 .ver_addr = 0, 10948 .req_flow_ctrl = 0, 10949 .req_line_speed = 0, 10950 .speed_cap_mask = 0, 10951 .req_duplex = 0, 10952 .rsrv = 0, 10953 .config_init = (config_init_t)bnx2x_xgxs_config_init, 10954 .read_status = (read_status_t)bnx2x_link_settings_status, 10955 .link_reset = (link_reset_t)bnx2x_int_link_reset, 10956 .config_loopback = (config_loopback_t)NULL, 10957 .format_fw_ver = (format_fw_ver_t)NULL, 10958 .hw_reset = (hw_reset_t)NULL, 10959 .set_link_led = (set_link_led_t)NULL, 10960 .phy_specific_func = (phy_specific_func_t)NULL 10961 }; 10962 10963 static struct bnx2x_phy phy_xgxs = { 10964 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT, 10965 .addr = 0xff, 10966 .def_md_devad = 0, 10967 .flags = 0, 10968 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 10969 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 10970 .mdio_ctrl = 0, 10971 .supported = (SUPPORTED_10baseT_Half | 10972 SUPPORTED_10baseT_Full | 10973 SUPPORTED_100baseT_Half | 10974 SUPPORTED_100baseT_Full | 10975 SUPPORTED_1000baseT_Full | 10976 SUPPORTED_2500baseX_Full | 10977 SUPPORTED_10000baseT_Full | 10978 SUPPORTED_FIBRE | 10979 SUPPORTED_Autoneg | 10980 SUPPORTED_Pause | 10981 SUPPORTED_Asym_Pause), 10982 .media_type = ETH_PHY_CX4, 10983 .ver_addr = 0, 10984 .req_flow_ctrl = 0, 10985 .req_line_speed = 0, 10986 .speed_cap_mask = 0, 10987 .req_duplex = 0, 10988 .rsrv = 0, 10989 .config_init = (config_init_t)bnx2x_xgxs_config_init, 10990 .read_status = (read_status_t)bnx2x_link_settings_status, 10991 .link_reset = (link_reset_t)bnx2x_int_link_reset, 10992 .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback, 10993 .format_fw_ver = (format_fw_ver_t)NULL, 10994 .hw_reset = (hw_reset_t)NULL, 10995 .set_link_led = (set_link_led_t)NULL, 10996 .phy_specific_func = (phy_specific_func_t)NULL 10997 }; 10998 static struct bnx2x_phy phy_warpcore = { 10999 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT, 11000 .addr = 0xff, 11001 .def_md_devad = 0, 11002 .flags = (FLAGS_HW_LOCK_REQUIRED | 11003 FLAGS_TX_ERROR_CHECK), 11004 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11005 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11006 .mdio_ctrl = 0, 11007 .supported = (SUPPORTED_10baseT_Half | 11008 SUPPORTED_10baseT_Full | 11009 SUPPORTED_100baseT_Half | 11010 SUPPORTED_100baseT_Full | 11011 SUPPORTED_1000baseT_Full | 11012 SUPPORTED_10000baseT_Full | 11013 SUPPORTED_20000baseKR2_Full | 11014 SUPPORTED_20000baseMLD2_Full | 11015 SUPPORTED_FIBRE | 11016 SUPPORTED_Autoneg | 11017 SUPPORTED_Pause | 11018 SUPPORTED_Asym_Pause), 11019 .media_type = ETH_PHY_UNSPECIFIED, 11020 .ver_addr = 0, 11021 .req_flow_ctrl = 0, 11022 .req_line_speed = 0, 11023 .speed_cap_mask = 0, 11024 /* req_duplex = */0, 11025 /* rsrv = */0, 11026 .config_init = (config_init_t)bnx2x_warpcore_config_init, 11027 .read_status = (read_status_t)bnx2x_warpcore_read_status, 11028 .link_reset = (link_reset_t)bnx2x_warpcore_link_reset, 11029 .config_loopback = (config_loopback_t)bnx2x_set_warpcore_loopback, 11030 .format_fw_ver = (format_fw_ver_t)NULL, 11031 .hw_reset = (hw_reset_t)bnx2x_warpcore_hw_reset, 11032 .set_link_led = (set_link_led_t)NULL, 11033 .phy_specific_func = (phy_specific_func_t)NULL 11034 }; 11035 11036 11037 static struct bnx2x_phy phy_7101 = { 11038 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101, 11039 .addr = 0xff, 11040 .def_md_devad = 0, 11041 .flags = FLAGS_FAN_FAILURE_DET_REQ, 11042 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11043 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11044 .mdio_ctrl = 0, 11045 .supported = (SUPPORTED_10000baseT_Full | 11046 SUPPORTED_TP | 11047 SUPPORTED_Autoneg | 11048 SUPPORTED_Pause | 11049 SUPPORTED_Asym_Pause), 11050 .media_type = ETH_PHY_BASE_T, 11051 .ver_addr = 0, 11052 .req_flow_ctrl = 0, 11053 .req_line_speed = 0, 11054 .speed_cap_mask = 0, 11055 .req_duplex = 0, 11056 .rsrv = 0, 11057 .config_init = (config_init_t)bnx2x_7101_config_init, 11058 .read_status = (read_status_t)bnx2x_7101_read_status, 11059 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset, 11060 .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback, 11061 .format_fw_ver = (format_fw_ver_t)bnx2x_7101_format_ver, 11062 .hw_reset = (hw_reset_t)bnx2x_7101_hw_reset, 11063 .set_link_led = (set_link_led_t)bnx2x_7101_set_link_led, 11064 .phy_specific_func = (phy_specific_func_t)NULL 11065 }; 11066 static struct bnx2x_phy phy_8073 = { 11067 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, 11068 .addr = 0xff, 11069 .def_md_devad = 0, 11070 .flags = FLAGS_HW_LOCK_REQUIRED, 11071 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11072 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11073 .mdio_ctrl = 0, 11074 .supported = (SUPPORTED_10000baseT_Full | 11075 SUPPORTED_2500baseX_Full | 11076 SUPPORTED_1000baseT_Full | 11077 SUPPORTED_FIBRE | 11078 SUPPORTED_Autoneg | 11079 SUPPORTED_Pause | 11080 SUPPORTED_Asym_Pause), 11081 .media_type = ETH_PHY_KR, 11082 .ver_addr = 0, 11083 .req_flow_ctrl = 0, 11084 .req_line_speed = 0, 11085 .speed_cap_mask = 0, 11086 .req_duplex = 0, 11087 .rsrv = 0, 11088 .config_init = (config_init_t)bnx2x_8073_config_init, 11089 .read_status = (read_status_t)bnx2x_8073_read_status, 11090 .link_reset = (link_reset_t)bnx2x_8073_link_reset, 11091 .config_loopback = (config_loopback_t)NULL, 11092 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, 11093 .hw_reset = (hw_reset_t)NULL, 11094 .set_link_led = (set_link_led_t)NULL, 11095 .phy_specific_func = (phy_specific_func_t)bnx2x_8073_specific_func 11096 }; 11097 static struct bnx2x_phy phy_8705 = { 11098 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705, 11099 .addr = 0xff, 11100 .def_md_devad = 0, 11101 .flags = FLAGS_INIT_XGXS_FIRST, 11102 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11103 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11104 .mdio_ctrl = 0, 11105 .supported = (SUPPORTED_10000baseT_Full | 11106 SUPPORTED_FIBRE | 11107 SUPPORTED_Pause | 11108 SUPPORTED_Asym_Pause), 11109 .media_type = ETH_PHY_XFP_FIBER, 11110 .ver_addr = 0, 11111 .req_flow_ctrl = 0, 11112 .req_line_speed = 0, 11113 .speed_cap_mask = 0, 11114 .req_duplex = 0, 11115 .rsrv = 0, 11116 .config_init = (config_init_t)bnx2x_8705_config_init, 11117 .read_status = (read_status_t)bnx2x_8705_read_status, 11118 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset, 11119 .config_loopback = (config_loopback_t)NULL, 11120 .format_fw_ver = (format_fw_ver_t)bnx2x_null_format_ver, 11121 .hw_reset = (hw_reset_t)NULL, 11122 .set_link_led = (set_link_led_t)NULL, 11123 .phy_specific_func = (phy_specific_func_t)NULL 11124 }; 11125 static struct bnx2x_phy phy_8706 = { 11126 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706, 11127 .addr = 0xff, 11128 .def_md_devad = 0, 11129 .flags = FLAGS_INIT_XGXS_FIRST, 11130 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11131 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11132 .mdio_ctrl = 0, 11133 .supported = (SUPPORTED_10000baseT_Full | 11134 SUPPORTED_1000baseT_Full | 11135 SUPPORTED_FIBRE | 11136 SUPPORTED_Pause | 11137 SUPPORTED_Asym_Pause), 11138 .media_type = ETH_PHY_SFPP_10G_FIBER, 11139 .ver_addr = 0, 11140 .req_flow_ctrl = 0, 11141 .req_line_speed = 0, 11142 .speed_cap_mask = 0, 11143 .req_duplex = 0, 11144 .rsrv = 0, 11145 .config_init = (config_init_t)bnx2x_8706_config_init, 11146 .read_status = (read_status_t)bnx2x_8706_read_status, 11147 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset, 11148 .config_loopback = (config_loopback_t)NULL, 11149 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, 11150 .hw_reset = (hw_reset_t)NULL, 11151 .set_link_led = (set_link_led_t)NULL, 11152 .phy_specific_func = (phy_specific_func_t)NULL 11153 }; 11154 11155 static struct bnx2x_phy phy_8726 = { 11156 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726, 11157 .addr = 0xff, 11158 .def_md_devad = 0, 11159 .flags = (FLAGS_HW_LOCK_REQUIRED | 11160 FLAGS_INIT_XGXS_FIRST | 11161 FLAGS_TX_ERROR_CHECK), 11162 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11163 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11164 .mdio_ctrl = 0, 11165 .supported = (SUPPORTED_10000baseT_Full | 11166 SUPPORTED_1000baseT_Full | 11167 SUPPORTED_Autoneg | 11168 SUPPORTED_FIBRE | 11169 SUPPORTED_Pause | 11170 SUPPORTED_Asym_Pause), 11171 .media_type = ETH_PHY_NOT_PRESENT, 11172 .ver_addr = 0, 11173 .req_flow_ctrl = 0, 11174 .req_line_speed = 0, 11175 .speed_cap_mask = 0, 11176 .req_duplex = 0, 11177 .rsrv = 0, 11178 .config_init = (config_init_t)bnx2x_8726_config_init, 11179 .read_status = (read_status_t)bnx2x_8726_read_status, 11180 .link_reset = (link_reset_t)bnx2x_8726_link_reset, 11181 .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback, 11182 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, 11183 .hw_reset = (hw_reset_t)NULL, 11184 .set_link_led = (set_link_led_t)NULL, 11185 .phy_specific_func = (phy_specific_func_t)NULL 11186 }; 11187 11188 static struct bnx2x_phy phy_8727 = { 11189 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727, 11190 .addr = 0xff, 11191 .def_md_devad = 0, 11192 .flags = (FLAGS_FAN_FAILURE_DET_REQ | 11193 FLAGS_TX_ERROR_CHECK), 11194 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11195 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11196 .mdio_ctrl = 0, 11197 .supported = (SUPPORTED_10000baseT_Full | 11198 SUPPORTED_1000baseT_Full | 11199 SUPPORTED_FIBRE | 11200 SUPPORTED_Pause | 11201 SUPPORTED_Asym_Pause), 11202 .media_type = ETH_PHY_NOT_PRESENT, 11203 .ver_addr = 0, 11204 .req_flow_ctrl = 0, 11205 .req_line_speed = 0, 11206 .speed_cap_mask = 0, 11207 .req_duplex = 0, 11208 .rsrv = 0, 11209 .config_init = (config_init_t)bnx2x_8727_config_init, 11210 .read_status = (read_status_t)bnx2x_8727_read_status, 11211 .link_reset = (link_reset_t)bnx2x_8727_link_reset, 11212 .config_loopback = (config_loopback_t)NULL, 11213 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, 11214 .hw_reset = (hw_reset_t)bnx2x_8727_hw_reset, 11215 .set_link_led = (set_link_led_t)bnx2x_8727_set_link_led, 11216 .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func 11217 }; 11218 static struct bnx2x_phy phy_8481 = { 11219 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, 11220 .addr = 0xff, 11221 .def_md_devad = 0, 11222 .flags = FLAGS_FAN_FAILURE_DET_REQ | 11223 FLAGS_REARM_LATCH_SIGNAL, 11224 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11225 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11226 .mdio_ctrl = 0, 11227 .supported = (SUPPORTED_10baseT_Half | 11228 SUPPORTED_10baseT_Full | 11229 SUPPORTED_100baseT_Half | 11230 SUPPORTED_100baseT_Full | 11231 SUPPORTED_1000baseT_Full | 11232 SUPPORTED_10000baseT_Full | 11233 SUPPORTED_TP | 11234 SUPPORTED_Autoneg | 11235 SUPPORTED_Pause | 11236 SUPPORTED_Asym_Pause), 11237 .media_type = ETH_PHY_BASE_T, 11238 .ver_addr = 0, 11239 .req_flow_ctrl = 0, 11240 .req_line_speed = 0, 11241 .speed_cap_mask = 0, 11242 .req_duplex = 0, 11243 .rsrv = 0, 11244 .config_init = (config_init_t)bnx2x_8481_config_init, 11245 .read_status = (read_status_t)bnx2x_848xx_read_status, 11246 .link_reset = (link_reset_t)bnx2x_8481_link_reset, 11247 .config_loopback = (config_loopback_t)NULL, 11248 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver, 11249 .hw_reset = (hw_reset_t)bnx2x_8481_hw_reset, 11250 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led, 11251 .phy_specific_func = (phy_specific_func_t)NULL 11252 }; 11253 11254 static struct bnx2x_phy phy_84823 = { 11255 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823, 11256 .addr = 0xff, 11257 .def_md_devad = 0, 11258 .flags = (FLAGS_FAN_FAILURE_DET_REQ | 11259 FLAGS_REARM_LATCH_SIGNAL | 11260 FLAGS_TX_ERROR_CHECK), 11261 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11262 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11263 .mdio_ctrl = 0, 11264 .supported = (SUPPORTED_10baseT_Half | 11265 SUPPORTED_10baseT_Full | 11266 SUPPORTED_100baseT_Half | 11267 SUPPORTED_100baseT_Full | 11268 SUPPORTED_1000baseT_Full | 11269 SUPPORTED_10000baseT_Full | 11270 SUPPORTED_TP | 11271 SUPPORTED_Autoneg | 11272 SUPPORTED_Pause | 11273 SUPPORTED_Asym_Pause), 11274 .media_type = ETH_PHY_BASE_T, 11275 .ver_addr = 0, 11276 .req_flow_ctrl = 0, 11277 .req_line_speed = 0, 11278 .speed_cap_mask = 0, 11279 .req_duplex = 0, 11280 .rsrv = 0, 11281 .config_init = (config_init_t)bnx2x_848x3_config_init, 11282 .read_status = (read_status_t)bnx2x_848xx_read_status, 11283 .link_reset = (link_reset_t)bnx2x_848x3_link_reset, 11284 .config_loopback = (config_loopback_t)NULL, 11285 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver, 11286 .hw_reset = (hw_reset_t)NULL, 11287 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led, 11288 .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func 11289 }; 11290 11291 static struct bnx2x_phy phy_84833 = { 11292 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833, 11293 .addr = 0xff, 11294 .def_md_devad = 0, 11295 .flags = (FLAGS_FAN_FAILURE_DET_REQ | 11296 FLAGS_REARM_LATCH_SIGNAL | 11297 FLAGS_TX_ERROR_CHECK), 11298 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11299 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11300 .mdio_ctrl = 0, 11301 .supported = (SUPPORTED_100baseT_Half | 11302 SUPPORTED_100baseT_Full | 11303 SUPPORTED_1000baseT_Full | 11304 SUPPORTED_10000baseT_Full | 11305 SUPPORTED_TP | 11306 SUPPORTED_Autoneg | 11307 SUPPORTED_Pause | 11308 SUPPORTED_Asym_Pause), 11309 .media_type = ETH_PHY_BASE_T, 11310 .ver_addr = 0, 11311 .req_flow_ctrl = 0, 11312 .req_line_speed = 0, 11313 .speed_cap_mask = 0, 11314 .req_duplex = 0, 11315 .rsrv = 0, 11316 .config_init = (config_init_t)bnx2x_848x3_config_init, 11317 .read_status = (read_status_t)bnx2x_848xx_read_status, 11318 .link_reset = (link_reset_t)bnx2x_848x3_link_reset, 11319 .config_loopback = (config_loopback_t)NULL, 11320 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver, 11321 .hw_reset = (hw_reset_t)bnx2x_84833_hw_reset_phy, 11322 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led, 11323 .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func 11324 }; 11325 11326 static struct bnx2x_phy phy_54618se = { 11327 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE, 11328 .addr = 0xff, 11329 .def_md_devad = 0, 11330 .flags = FLAGS_INIT_XGXS_FIRST, 11331 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11332 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 11333 .mdio_ctrl = 0, 11334 .supported = (SUPPORTED_10baseT_Half | 11335 SUPPORTED_10baseT_Full | 11336 SUPPORTED_100baseT_Half | 11337 SUPPORTED_100baseT_Full | 11338 SUPPORTED_1000baseT_Full | 11339 SUPPORTED_TP | 11340 SUPPORTED_Autoneg | 11341 SUPPORTED_Pause | 11342 SUPPORTED_Asym_Pause), 11343 .media_type = ETH_PHY_BASE_T, 11344 .ver_addr = 0, 11345 .req_flow_ctrl = 0, 11346 .req_line_speed = 0, 11347 .speed_cap_mask = 0, 11348 /* req_duplex = */0, 11349 /* rsrv = */0, 11350 .config_init = (config_init_t)bnx2x_54618se_config_init, 11351 .read_status = (read_status_t)bnx2x_54618se_read_status, 11352 .link_reset = (link_reset_t)bnx2x_54618se_link_reset, 11353 .config_loopback = (config_loopback_t)bnx2x_54618se_config_loopback, 11354 .format_fw_ver = (format_fw_ver_t)NULL, 11355 .hw_reset = (hw_reset_t)NULL, 11356 .set_link_led = (set_link_led_t)bnx2x_5461x_set_link_led, 11357 .phy_specific_func = (phy_specific_func_t)bnx2x_54618se_specific_func 11358 }; 11359 /*****************************************************************/ 11360 /* */ 11361 /* Populate the phy according. Main function: bnx2x_populate_phy */ 11362 /* */ 11363 /*****************************************************************/ 11364 11365 static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base, 11366 struct bnx2x_phy *phy, u8 port, 11367 u8 phy_index) 11368 { 11369 /* Get the 4 lanes xgxs config rx and tx */ 11370 u32 rx = 0, tx = 0, i; 11371 for (i = 0; i < 2; i++) { 11372 /* INT_PHY and EXT_PHY1 share the same value location in 11373 * the shmem. When num_phys is greater than 1, than this value 11374 * applies only to EXT_PHY1 11375 */ 11376 if (phy_index == INT_PHY || phy_index == EXT_PHY1) { 11377 rx = REG_RD(bp, shmem_base + 11378 offsetof(struct shmem_region, 11379 dev_info.port_hw_config[port].xgxs_config_rx[i<<1])); 11380 11381 tx = REG_RD(bp, shmem_base + 11382 offsetof(struct shmem_region, 11383 dev_info.port_hw_config[port].xgxs_config_tx[i<<1])); 11384 } else { 11385 rx = REG_RD(bp, shmem_base + 11386 offsetof(struct shmem_region, 11387 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1])); 11388 11389 tx = REG_RD(bp, shmem_base + 11390 offsetof(struct shmem_region, 11391 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1])); 11392 } 11393 11394 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff); 11395 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff); 11396 11397 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff); 11398 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff); 11399 } 11400 } 11401 11402 static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base, 11403 u8 phy_index, u8 port) 11404 { 11405 u32 ext_phy_config = 0; 11406 switch (phy_index) { 11407 case EXT_PHY1: 11408 ext_phy_config = REG_RD(bp, shmem_base + 11409 offsetof(struct shmem_region, 11410 dev_info.port_hw_config[port].external_phy_config)); 11411 break; 11412 case EXT_PHY2: 11413 ext_phy_config = REG_RD(bp, shmem_base + 11414 offsetof(struct shmem_region, 11415 dev_info.port_hw_config[port].external_phy_config2)); 11416 break; 11417 default: 11418 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index); 11419 return -EINVAL; 11420 } 11421 11422 return ext_phy_config; 11423 } 11424 static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port, 11425 struct bnx2x_phy *phy) 11426 { 11427 u32 phy_addr; 11428 u32 chip_id; 11429 u32 switch_cfg = (REG_RD(bp, shmem_base + 11430 offsetof(struct shmem_region, 11431 dev_info.port_feature_config[port].link_config)) & 11432 PORT_FEATURE_CONNECTED_SWITCH_MASK); 11433 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) | 11434 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12); 11435 11436 DP(NETIF_MSG_LINK, ":chip_id = 0x%x\n", chip_id); 11437 if (USES_WARPCORE(bp)) { 11438 u32 serdes_net_if; 11439 phy_addr = REG_RD(bp, 11440 MISC_REG_WC0_CTRL_PHY_ADDR); 11441 *phy = phy_warpcore; 11442 if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3) 11443 phy->flags |= FLAGS_4_PORT_MODE; 11444 else 11445 phy->flags &= ~FLAGS_4_PORT_MODE; 11446 /* Check Dual mode */ 11447 serdes_net_if = (REG_RD(bp, shmem_base + 11448 offsetof(struct shmem_region, dev_info. 11449 port_hw_config[port].default_cfg)) & 11450 PORT_HW_CFG_NET_SERDES_IF_MASK); 11451 /* Set the appropriate supported and flags indications per 11452 * interface type of the chip 11453 */ 11454 switch (serdes_net_if) { 11455 case PORT_HW_CFG_NET_SERDES_IF_SGMII: 11456 phy->supported &= (SUPPORTED_10baseT_Half | 11457 SUPPORTED_10baseT_Full | 11458 SUPPORTED_100baseT_Half | 11459 SUPPORTED_100baseT_Full | 11460 SUPPORTED_1000baseT_Full | 11461 SUPPORTED_FIBRE | 11462 SUPPORTED_Autoneg | 11463 SUPPORTED_Pause | 11464 SUPPORTED_Asym_Pause); 11465 phy->media_type = ETH_PHY_BASE_T; 11466 break; 11467 case PORT_HW_CFG_NET_SERDES_IF_XFI: 11468 phy->media_type = ETH_PHY_XFP_FIBER; 11469 break; 11470 case PORT_HW_CFG_NET_SERDES_IF_SFI: 11471 phy->supported &= (SUPPORTED_1000baseT_Full | 11472 SUPPORTED_10000baseT_Full | 11473 SUPPORTED_FIBRE | 11474 SUPPORTED_Pause | 11475 SUPPORTED_Asym_Pause); 11476 phy->media_type = ETH_PHY_SFPP_10G_FIBER; 11477 break; 11478 case PORT_HW_CFG_NET_SERDES_IF_KR: 11479 phy->media_type = ETH_PHY_KR; 11480 phy->supported &= (SUPPORTED_1000baseT_Full | 11481 SUPPORTED_10000baseT_Full | 11482 SUPPORTED_FIBRE | 11483 SUPPORTED_Autoneg | 11484 SUPPORTED_Pause | 11485 SUPPORTED_Asym_Pause); 11486 break; 11487 case PORT_HW_CFG_NET_SERDES_IF_DXGXS: 11488 phy->media_type = ETH_PHY_KR; 11489 phy->flags |= FLAGS_WC_DUAL_MODE; 11490 phy->supported &= (SUPPORTED_20000baseMLD2_Full | 11491 SUPPORTED_FIBRE | 11492 SUPPORTED_Pause | 11493 SUPPORTED_Asym_Pause); 11494 break; 11495 case PORT_HW_CFG_NET_SERDES_IF_KR2: 11496 phy->media_type = ETH_PHY_KR; 11497 phy->flags |= FLAGS_WC_DUAL_MODE; 11498 phy->supported &= (SUPPORTED_20000baseKR2_Full | 11499 SUPPORTED_FIBRE | 11500 SUPPORTED_Pause | 11501 SUPPORTED_Asym_Pause); 11502 break; 11503 default: 11504 DP(NETIF_MSG_LINK, "Unknown WC interface type 0x%x\n", 11505 serdes_net_if); 11506 break; 11507 } 11508 11509 /* Enable MDC/MDIO work-around for E3 A0 since free running MDC 11510 * was not set as expected. For B0, ECO will be enabled so there 11511 * won't be an issue there 11512 */ 11513 if (CHIP_REV(bp) == CHIP_REV_Ax) 11514 phy->flags |= FLAGS_MDC_MDIO_WA; 11515 else 11516 phy->flags |= FLAGS_MDC_MDIO_WA_B0; 11517 } else { 11518 switch (switch_cfg) { 11519 case SWITCH_CFG_1G: 11520 phy_addr = REG_RD(bp, 11521 NIG_REG_SERDES0_CTRL_PHY_ADDR + 11522 port * 0x10); 11523 *phy = phy_serdes; 11524 break; 11525 case SWITCH_CFG_10G: 11526 phy_addr = REG_RD(bp, 11527 NIG_REG_XGXS0_CTRL_PHY_ADDR + 11528 port * 0x18); 11529 *phy = phy_xgxs; 11530 break; 11531 default: 11532 DP(NETIF_MSG_LINK, "Invalid switch_cfg\n"); 11533 return -EINVAL; 11534 } 11535 } 11536 phy->addr = (u8)phy_addr; 11537 phy->mdio_ctrl = bnx2x_get_emac_base(bp, 11538 SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH, 11539 port); 11540 if (CHIP_IS_E2(bp)) 11541 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR; 11542 else 11543 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR; 11544 11545 DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n", 11546 port, phy->addr, phy->mdio_ctrl); 11547 11548 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY); 11549 return 0; 11550 } 11551 11552 static int bnx2x_populate_ext_phy(struct bnx2x *bp, 11553 u8 phy_index, 11554 u32 shmem_base, 11555 u32 shmem2_base, 11556 u8 port, 11557 struct bnx2x_phy *phy) 11558 { 11559 u32 ext_phy_config, phy_type, config2; 11560 u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH; 11561 ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base, 11562 phy_index, port); 11563 phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); 11564 /* Select the phy type */ 11565 switch (phy_type) { 11566 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: 11567 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED; 11568 *phy = phy_8073; 11569 break; 11570 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705: 11571 *phy = phy_8705; 11572 break; 11573 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706: 11574 *phy = phy_8706; 11575 break; 11576 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 11577 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; 11578 *phy = phy_8726; 11579 break; 11580 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC: 11581 /* BCM8727_NOC => BCM8727 no over current */ 11582 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; 11583 *phy = phy_8727; 11584 phy->flags |= FLAGS_NOC; 11585 break; 11586 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 11587 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 11588 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; 11589 *phy = phy_8727; 11590 break; 11591 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481: 11592 *phy = phy_8481; 11593 break; 11594 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823: 11595 *phy = phy_84823; 11596 break; 11597 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833: 11598 *phy = phy_84833; 11599 break; 11600 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616: 11601 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE: 11602 *phy = phy_54618se; 11603 if (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) 11604 phy->flags |= FLAGS_EEE; 11605 break; 11606 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: 11607 *phy = phy_7101; 11608 break; 11609 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: 11610 *phy = phy_null; 11611 return -EINVAL; 11612 default: 11613 *phy = phy_null; 11614 /* In case external PHY wasn't found */ 11615 if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) && 11616 (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) 11617 return -EINVAL; 11618 return 0; 11619 } 11620 11621 phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config); 11622 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index); 11623 11624 /* The shmem address of the phy version is located on different 11625 * structures. In case this structure is too old, do not set 11626 * the address 11627 */ 11628 config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region, 11629 dev_info.shared_hw_config.config2)); 11630 if (phy_index == EXT_PHY1) { 11631 phy->ver_addr = shmem_base + offsetof(struct shmem_region, 11632 port_mb[port].ext_phy_fw_version); 11633 11634 /* Check specific mdc mdio settings */ 11635 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK) 11636 mdc_mdio_access = config2 & 11637 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK; 11638 } else { 11639 u32 size = REG_RD(bp, shmem2_base); 11640 11641 if (size > 11642 offsetof(struct shmem2_region, ext_phy_fw_version2)) { 11643 phy->ver_addr = shmem2_base + 11644 offsetof(struct shmem2_region, 11645 ext_phy_fw_version2[port]); 11646 } 11647 /* Check specific mdc mdio settings */ 11648 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) 11649 mdc_mdio_access = (config2 & 11650 SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >> 11651 (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT - 11652 SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT); 11653 } 11654 phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port); 11655 11656 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) && 11657 (phy->ver_addr)) { 11658 /* Remove 100Mb link supported for BCM84833 when phy fw 11659 * version lower than or equal to 1.39 11660 */ 11661 u32 raw_ver = REG_RD(bp, phy->ver_addr); 11662 if (((raw_ver & 0x7F) <= 39) && 11663 (((raw_ver & 0xF80) >> 7) <= 1)) 11664 phy->supported &= ~(SUPPORTED_100baseT_Half | 11665 SUPPORTED_100baseT_Full); 11666 } 11667 11668 /* In case mdc/mdio_access of the external phy is different than the 11669 * mdc/mdio access of the XGXS, a HW lock must be taken in each access 11670 * to prevent one port interfere with another port's CL45 operations. 11671 */ 11672 if (mdc_mdio_access != SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH) 11673 phy->flags |= FLAGS_HW_LOCK_REQUIRED; 11674 DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n", 11675 phy_type, port, phy_index); 11676 DP(NETIF_MSG_LINK, " addr=0x%x, mdio_ctl=0x%x\n", 11677 phy->addr, phy->mdio_ctrl); 11678 return 0; 11679 } 11680 11681 static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base, 11682 u32 shmem2_base, u8 port, struct bnx2x_phy *phy) 11683 { 11684 int status = 0; 11685 phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN; 11686 if (phy_index == INT_PHY) 11687 return bnx2x_populate_int_phy(bp, shmem_base, port, phy); 11688 status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base, 11689 port, phy); 11690 return status; 11691 } 11692 11693 static void bnx2x_phy_def_cfg(struct link_params *params, 11694 struct bnx2x_phy *phy, 11695 u8 phy_index) 11696 { 11697 struct bnx2x *bp = params->bp; 11698 u32 link_config; 11699 /* Populate the default phy configuration for MF mode */ 11700 if (phy_index == EXT_PHY2) { 11701 link_config = REG_RD(bp, params->shmem_base + 11702 offsetof(struct shmem_region, dev_info. 11703 port_feature_config[params->port].link_config2)); 11704 phy->speed_cap_mask = REG_RD(bp, params->shmem_base + 11705 offsetof(struct shmem_region, 11706 dev_info. 11707 port_hw_config[params->port].speed_capability_mask2)); 11708 } else { 11709 link_config = REG_RD(bp, params->shmem_base + 11710 offsetof(struct shmem_region, dev_info. 11711 port_feature_config[params->port].link_config)); 11712 phy->speed_cap_mask = REG_RD(bp, params->shmem_base + 11713 offsetof(struct shmem_region, 11714 dev_info. 11715 port_hw_config[params->port].speed_capability_mask)); 11716 } 11717 DP(NETIF_MSG_LINK, 11718 "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n", 11719 phy_index, link_config, phy->speed_cap_mask); 11720 11721 phy->req_duplex = DUPLEX_FULL; 11722 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { 11723 case PORT_FEATURE_LINK_SPEED_10M_HALF: 11724 phy->req_duplex = DUPLEX_HALF; 11725 case PORT_FEATURE_LINK_SPEED_10M_FULL: 11726 phy->req_line_speed = SPEED_10; 11727 break; 11728 case PORT_FEATURE_LINK_SPEED_100M_HALF: 11729 phy->req_duplex = DUPLEX_HALF; 11730 case PORT_FEATURE_LINK_SPEED_100M_FULL: 11731 phy->req_line_speed = SPEED_100; 11732 break; 11733 case PORT_FEATURE_LINK_SPEED_1G: 11734 phy->req_line_speed = SPEED_1000; 11735 break; 11736 case PORT_FEATURE_LINK_SPEED_2_5G: 11737 phy->req_line_speed = SPEED_2500; 11738 break; 11739 case PORT_FEATURE_LINK_SPEED_10G_CX4: 11740 phy->req_line_speed = SPEED_10000; 11741 break; 11742 default: 11743 phy->req_line_speed = SPEED_AUTO_NEG; 11744 break; 11745 } 11746 11747 switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) { 11748 case PORT_FEATURE_FLOW_CONTROL_AUTO: 11749 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO; 11750 break; 11751 case PORT_FEATURE_FLOW_CONTROL_TX: 11752 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX; 11753 break; 11754 case PORT_FEATURE_FLOW_CONTROL_RX: 11755 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX; 11756 break; 11757 case PORT_FEATURE_FLOW_CONTROL_BOTH: 11758 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH; 11759 break; 11760 default: 11761 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE; 11762 break; 11763 } 11764 } 11765 11766 u32 bnx2x_phy_selection(struct link_params *params) 11767 { 11768 u32 phy_config_swapped, prio_cfg; 11769 u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT; 11770 11771 phy_config_swapped = params->multi_phy_config & 11772 PORT_HW_CFG_PHY_SWAPPED_ENABLED; 11773 11774 prio_cfg = params->multi_phy_config & 11775 PORT_HW_CFG_PHY_SELECTION_MASK; 11776 11777 if (phy_config_swapped) { 11778 switch (prio_cfg) { 11779 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: 11780 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY; 11781 break; 11782 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: 11783 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY; 11784 break; 11785 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY: 11786 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; 11787 break; 11788 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY: 11789 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; 11790 break; 11791 } 11792 } else 11793 return_cfg = prio_cfg; 11794 11795 return return_cfg; 11796 } 11797 11798 11799 int bnx2x_phy_probe(struct link_params *params) 11800 { 11801 u8 phy_index, actual_phy_idx; 11802 u32 phy_config_swapped, sync_offset, media_types; 11803 struct bnx2x *bp = params->bp; 11804 struct bnx2x_phy *phy; 11805 params->num_phys = 0; 11806 DP(NETIF_MSG_LINK, "Begin phy probe\n"); 11807 phy_config_swapped = params->multi_phy_config & 11808 PORT_HW_CFG_PHY_SWAPPED_ENABLED; 11809 11810 for (phy_index = INT_PHY; phy_index < MAX_PHYS; 11811 phy_index++) { 11812 actual_phy_idx = phy_index; 11813 if (phy_config_swapped) { 11814 if (phy_index == EXT_PHY1) 11815 actual_phy_idx = EXT_PHY2; 11816 else if (phy_index == EXT_PHY2) 11817 actual_phy_idx = EXT_PHY1; 11818 } 11819 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x," 11820 " actual_phy_idx %x\n", phy_config_swapped, 11821 phy_index, actual_phy_idx); 11822 phy = ¶ms->phy[actual_phy_idx]; 11823 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base, 11824 params->shmem2_base, params->port, 11825 phy) != 0) { 11826 params->num_phys = 0; 11827 DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n", 11828 phy_index); 11829 for (phy_index = INT_PHY; 11830 phy_index < MAX_PHYS; 11831 phy_index++) 11832 *phy = phy_null; 11833 return -EINVAL; 11834 } 11835 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN) 11836 break; 11837 11838 if (params->feature_config_flags & 11839 FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET) 11840 phy->flags &= ~FLAGS_TX_ERROR_CHECK; 11841 11842 sync_offset = params->shmem_base + 11843 offsetof(struct shmem_region, 11844 dev_info.port_hw_config[params->port].media_type); 11845 media_types = REG_RD(bp, sync_offset); 11846 11847 /* Update media type for non-PMF sync only for the first time 11848 * In case the media type changes afterwards, it will be updated 11849 * using the update_status function 11850 */ 11851 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK << 11852 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * 11853 actual_phy_idx))) == 0) { 11854 media_types |= ((phy->media_type & 11855 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) << 11856 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * 11857 actual_phy_idx)); 11858 } 11859 REG_WR(bp, sync_offset, media_types); 11860 11861 bnx2x_phy_def_cfg(params, phy, phy_index); 11862 params->num_phys++; 11863 } 11864 11865 DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys); 11866 return 0; 11867 } 11868 11869 void bnx2x_init_bmac_loopback(struct link_params *params, 11870 struct link_vars *vars) 11871 { 11872 struct bnx2x *bp = params->bp; 11873 vars->link_up = 1; 11874 vars->line_speed = SPEED_10000; 11875 vars->duplex = DUPLEX_FULL; 11876 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 11877 vars->mac_type = MAC_TYPE_BMAC; 11878 11879 vars->phy_flags = PHY_XGXS_FLAG; 11880 11881 bnx2x_xgxs_deassert(params); 11882 11883 /* set bmac loopback */ 11884 bnx2x_bmac_enable(params, vars, 1, 1); 11885 11886 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 11887 } 11888 11889 void bnx2x_init_emac_loopback(struct link_params *params, 11890 struct link_vars *vars) 11891 { 11892 struct bnx2x *bp = params->bp; 11893 vars->link_up = 1; 11894 vars->line_speed = SPEED_1000; 11895 vars->duplex = DUPLEX_FULL; 11896 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 11897 vars->mac_type = MAC_TYPE_EMAC; 11898 11899 vars->phy_flags = PHY_XGXS_FLAG; 11900 11901 bnx2x_xgxs_deassert(params); 11902 /* set bmac loopback */ 11903 bnx2x_emac_enable(params, vars, 1); 11904 bnx2x_emac_program(params, vars); 11905 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 11906 } 11907 11908 void bnx2x_init_xmac_loopback(struct link_params *params, 11909 struct link_vars *vars) 11910 { 11911 struct bnx2x *bp = params->bp; 11912 vars->link_up = 1; 11913 if (!params->req_line_speed[0]) 11914 vars->line_speed = SPEED_10000; 11915 else 11916 vars->line_speed = params->req_line_speed[0]; 11917 vars->duplex = DUPLEX_FULL; 11918 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 11919 vars->mac_type = MAC_TYPE_XMAC; 11920 vars->phy_flags = PHY_XGXS_FLAG; 11921 /* Set WC to loopback mode since link is required to provide clock 11922 * to the XMAC in 20G mode 11923 */ 11924 bnx2x_set_aer_mmd(params, ¶ms->phy[0]); 11925 bnx2x_warpcore_reset_lane(bp, ¶ms->phy[0], 0); 11926 params->phy[INT_PHY].config_loopback( 11927 ¶ms->phy[INT_PHY], 11928 params); 11929 11930 bnx2x_xmac_enable(params, vars, 1); 11931 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 11932 } 11933 11934 void bnx2x_init_umac_loopback(struct link_params *params, 11935 struct link_vars *vars) 11936 { 11937 struct bnx2x *bp = params->bp; 11938 vars->link_up = 1; 11939 vars->line_speed = SPEED_1000; 11940 vars->duplex = DUPLEX_FULL; 11941 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 11942 vars->mac_type = MAC_TYPE_UMAC; 11943 vars->phy_flags = PHY_XGXS_FLAG; 11944 bnx2x_umac_enable(params, vars, 1); 11945 11946 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 11947 } 11948 11949 void bnx2x_init_xgxs_loopback(struct link_params *params, 11950 struct link_vars *vars) 11951 { 11952 struct bnx2x *bp = params->bp; 11953 vars->link_up = 1; 11954 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 11955 vars->duplex = DUPLEX_FULL; 11956 if (params->req_line_speed[0] == SPEED_1000) 11957 vars->line_speed = SPEED_1000; 11958 else 11959 vars->line_speed = SPEED_10000; 11960 11961 if (!USES_WARPCORE(bp)) 11962 bnx2x_xgxs_deassert(params); 11963 bnx2x_link_initialize(params, vars); 11964 11965 if (params->req_line_speed[0] == SPEED_1000) { 11966 if (USES_WARPCORE(bp)) 11967 bnx2x_umac_enable(params, vars, 0); 11968 else { 11969 bnx2x_emac_program(params, vars); 11970 bnx2x_emac_enable(params, vars, 0); 11971 } 11972 } else { 11973 if (USES_WARPCORE(bp)) 11974 bnx2x_xmac_enable(params, vars, 0); 11975 else 11976 bnx2x_bmac_enable(params, vars, 0, 1); 11977 } 11978 11979 if (params->loopback_mode == LOOPBACK_XGXS) { 11980 /* set 10G XGXS loopback */ 11981 params->phy[INT_PHY].config_loopback( 11982 ¶ms->phy[INT_PHY], 11983 params); 11984 11985 } else { 11986 /* set external phy loopback */ 11987 u8 phy_index; 11988 for (phy_index = EXT_PHY1; 11989 phy_index < params->num_phys; phy_index++) { 11990 if (params->phy[phy_index].config_loopback) 11991 params->phy[phy_index].config_loopback( 11992 ¶ms->phy[phy_index], 11993 params); 11994 } 11995 } 11996 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 11997 11998 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed); 11999 } 12000 12001 static void bnx2x_set_rx_filter(struct link_params *params, u8 en) 12002 { 12003 struct bnx2x *bp = params->bp; 12004 u8 val = en * 0x1F; 12005 12006 /* Open the gate between the NIG to the BRB */ 12007 if (!CHIP_IS_E1x(bp)) 12008 val |= en * 0x20; 12009 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val); 12010 12011 if (!CHIP_IS_E1(bp)) { 12012 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4, 12013 en*0x3); 12014 } 12015 12016 REG_WR(bp, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP : 12017 NIG_REG_LLH0_BRB1_NOT_MCP), en); 12018 } 12019 static int bnx2x_avoid_link_flap(struct link_params *params, 12020 struct link_vars *vars) 12021 { 12022 u32 phy_idx; 12023 u32 dont_clear_stat, lfa_sts; 12024 struct bnx2x *bp = params->bp; 12025 12026 /* Sync the link parameters */ 12027 bnx2x_link_status_update(params, vars); 12028 12029 /* 12030 * The module verification was already done by previous link owner, 12031 * so this call is meant only to get warning message 12032 */ 12033 12034 for (phy_idx = INT_PHY; phy_idx < params->num_phys; phy_idx++) { 12035 struct bnx2x_phy *phy = ¶ms->phy[phy_idx]; 12036 if (phy->phy_specific_func) { 12037 DP(NETIF_MSG_LINK, "Calling PHY specific func\n"); 12038 phy->phy_specific_func(phy, params, PHY_INIT); 12039 } 12040 if ((phy->media_type == ETH_PHY_SFPP_10G_FIBER) || 12041 (phy->media_type == ETH_PHY_SFP_1G_FIBER) || 12042 (phy->media_type == ETH_PHY_DA_TWINAX)) 12043 bnx2x_verify_sfp_module(phy, params); 12044 } 12045 lfa_sts = REG_RD(bp, params->lfa_base + 12046 offsetof(struct shmem_lfa, 12047 lfa_sts)); 12048 12049 dont_clear_stat = lfa_sts & SHMEM_LFA_DONT_CLEAR_STAT; 12050 12051 /* Re-enable the NIG/MAC */ 12052 if (CHIP_IS_E3(bp)) { 12053 if (!dont_clear_stat) { 12054 REG_WR(bp, GRCBASE_MISC + 12055 MISC_REGISTERS_RESET_REG_2_CLEAR, 12056 (MISC_REGISTERS_RESET_REG_2_MSTAT0 << 12057 params->port)); 12058 REG_WR(bp, GRCBASE_MISC + 12059 MISC_REGISTERS_RESET_REG_2_SET, 12060 (MISC_REGISTERS_RESET_REG_2_MSTAT0 << 12061 params->port)); 12062 } 12063 if (vars->line_speed < SPEED_10000) 12064 bnx2x_umac_enable(params, vars, 0); 12065 else 12066 bnx2x_xmac_enable(params, vars, 0); 12067 } else { 12068 if (vars->line_speed < SPEED_10000) 12069 bnx2x_emac_enable(params, vars, 0); 12070 else 12071 bnx2x_bmac_enable(params, vars, 0, !dont_clear_stat); 12072 } 12073 12074 /* Increment LFA count */ 12075 lfa_sts = ((lfa_sts & ~LINK_FLAP_AVOIDANCE_COUNT_MASK) | 12076 (((((lfa_sts & LINK_FLAP_AVOIDANCE_COUNT_MASK) >> 12077 LINK_FLAP_AVOIDANCE_COUNT_OFFSET) + 1) & 0xff) 12078 << LINK_FLAP_AVOIDANCE_COUNT_OFFSET)); 12079 /* Clear link flap reason */ 12080 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK; 12081 12082 REG_WR(bp, params->lfa_base + 12083 offsetof(struct shmem_lfa, lfa_sts), lfa_sts); 12084 12085 /* Disable NIG DRAIN */ 12086 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 12087 12088 /* Enable interrupts */ 12089 bnx2x_link_int_enable(params); 12090 return 0; 12091 } 12092 12093 static void bnx2x_cannot_avoid_link_flap(struct link_params *params, 12094 struct link_vars *vars, 12095 int lfa_status) 12096 { 12097 u32 lfa_sts, cfg_idx, tmp_val; 12098 struct bnx2x *bp = params->bp; 12099 12100 bnx2x_link_reset(params, vars, 1); 12101 12102 if (!params->lfa_base) 12103 return; 12104 /* Store the new link parameters */ 12105 REG_WR(bp, params->lfa_base + 12106 offsetof(struct shmem_lfa, req_duplex), 12107 params->req_duplex[0] | (params->req_duplex[1] << 16)); 12108 12109 REG_WR(bp, params->lfa_base + 12110 offsetof(struct shmem_lfa, req_flow_ctrl), 12111 params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16)); 12112 12113 REG_WR(bp, params->lfa_base + 12114 offsetof(struct shmem_lfa, req_line_speed), 12115 params->req_line_speed[0] | (params->req_line_speed[1] << 16)); 12116 12117 for (cfg_idx = 0; cfg_idx < SHMEM_LINK_CONFIG_SIZE; cfg_idx++) { 12118 REG_WR(bp, params->lfa_base + 12119 offsetof(struct shmem_lfa, 12120 speed_cap_mask[cfg_idx]), 12121 params->speed_cap_mask[cfg_idx]); 12122 } 12123 12124 tmp_val = REG_RD(bp, params->lfa_base + 12125 offsetof(struct shmem_lfa, additional_config)); 12126 tmp_val &= ~REQ_FC_AUTO_ADV_MASK; 12127 tmp_val |= params->req_fc_auto_adv; 12128 12129 REG_WR(bp, params->lfa_base + 12130 offsetof(struct shmem_lfa, additional_config), tmp_val); 12131 12132 lfa_sts = REG_RD(bp, params->lfa_base + 12133 offsetof(struct shmem_lfa, lfa_sts)); 12134 12135 /* Clear the "Don't Clear Statistics" bit, and set reason */ 12136 lfa_sts &= ~SHMEM_LFA_DONT_CLEAR_STAT; 12137 12138 /* Set link flap reason */ 12139 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK; 12140 lfa_sts |= ((lfa_status & LFA_LINK_FLAP_REASON_MASK) << 12141 LFA_LINK_FLAP_REASON_OFFSET); 12142 12143 /* Increment link flap counter */ 12144 lfa_sts = ((lfa_sts & ~LINK_FLAP_COUNT_MASK) | 12145 (((((lfa_sts & LINK_FLAP_COUNT_MASK) >> 12146 LINK_FLAP_COUNT_OFFSET) + 1) & 0xff) 12147 << LINK_FLAP_COUNT_OFFSET)); 12148 REG_WR(bp, params->lfa_base + 12149 offsetof(struct shmem_lfa, lfa_sts), lfa_sts); 12150 /* Proceed with regular link initialization */ 12151 } 12152 12153 int bnx2x_phy_init(struct link_params *params, struct link_vars *vars) 12154 { 12155 int lfa_status; 12156 struct bnx2x *bp = params->bp; 12157 DP(NETIF_MSG_LINK, "Phy Initialization started\n"); 12158 DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n", 12159 params->req_line_speed[0], params->req_flow_ctrl[0]); 12160 DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n", 12161 params->req_line_speed[1], params->req_flow_ctrl[1]); 12162 vars->link_status = 0; 12163 vars->phy_link_up = 0; 12164 vars->link_up = 0; 12165 vars->line_speed = 0; 12166 vars->duplex = DUPLEX_FULL; 12167 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 12168 vars->mac_type = MAC_TYPE_NONE; 12169 vars->phy_flags = 0; 12170 /* Driver opens NIG-BRB filters */ 12171 bnx2x_set_rx_filter(params, 1); 12172 /* Check if link flap can be avoided */ 12173 lfa_status = bnx2x_check_lfa(params); 12174 12175 if (lfa_status == 0) { 12176 DP(NETIF_MSG_LINK, "Link Flap Avoidance in progress\n"); 12177 return bnx2x_avoid_link_flap(params, vars); 12178 } 12179 12180 DP(NETIF_MSG_LINK, "Cannot avoid link flap lfa_sta=0x%x\n", 12181 lfa_status); 12182 bnx2x_cannot_avoid_link_flap(params, vars, lfa_status); 12183 12184 /* Disable attentions */ 12185 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4, 12186 (NIG_MASK_XGXS0_LINK_STATUS | 12187 NIG_MASK_XGXS0_LINK10G | 12188 NIG_MASK_SERDES0_LINK_STATUS | 12189 NIG_MASK_MI_INT)); 12190 12191 bnx2x_emac_init(params, vars); 12192 12193 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) 12194 vars->link_status |= LINK_STATUS_PFC_ENABLED; 12195 12196 if (params->num_phys == 0) { 12197 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n"); 12198 return -EINVAL; 12199 } 12200 set_phy_vars(params, vars); 12201 12202 DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys); 12203 switch (params->loopback_mode) { 12204 case LOOPBACK_BMAC: 12205 bnx2x_init_bmac_loopback(params, vars); 12206 break; 12207 case LOOPBACK_EMAC: 12208 bnx2x_init_emac_loopback(params, vars); 12209 break; 12210 case LOOPBACK_XMAC: 12211 bnx2x_init_xmac_loopback(params, vars); 12212 break; 12213 case LOOPBACK_UMAC: 12214 bnx2x_init_umac_loopback(params, vars); 12215 break; 12216 case LOOPBACK_XGXS: 12217 case LOOPBACK_EXT_PHY: 12218 bnx2x_init_xgxs_loopback(params, vars); 12219 break; 12220 default: 12221 if (!CHIP_IS_E3(bp)) { 12222 if (params->switch_cfg == SWITCH_CFG_10G) 12223 bnx2x_xgxs_deassert(params); 12224 else 12225 bnx2x_serdes_deassert(bp, params->port); 12226 } 12227 bnx2x_link_initialize(params, vars); 12228 msleep(30); 12229 bnx2x_link_int_enable(params); 12230 break; 12231 } 12232 bnx2x_update_mng(params, vars->link_status); 12233 12234 bnx2x_update_mng_eee(params, vars->eee_status); 12235 return 0; 12236 } 12237 12238 int bnx2x_link_reset(struct link_params *params, struct link_vars *vars, 12239 u8 reset_ext_phy) 12240 { 12241 struct bnx2x *bp = params->bp; 12242 u8 phy_index, port = params->port, clear_latch_ind = 0; 12243 DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port); 12244 /* Disable attentions */ 12245 vars->link_status = 0; 12246 bnx2x_update_mng(params, vars->link_status); 12247 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK | 12248 SHMEM_EEE_ACTIVE_BIT); 12249 bnx2x_update_mng_eee(params, vars->eee_status); 12250 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 12251 (NIG_MASK_XGXS0_LINK_STATUS | 12252 NIG_MASK_XGXS0_LINK10G | 12253 NIG_MASK_SERDES0_LINK_STATUS | 12254 NIG_MASK_MI_INT)); 12255 12256 /* Activate nig drain */ 12257 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); 12258 12259 /* Disable nig egress interface */ 12260 if (!CHIP_IS_E3(bp)) { 12261 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0); 12262 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0); 12263 } 12264 12265 if (!CHIP_IS_E3(bp)) { 12266 bnx2x_set_bmac_rx(bp, params->chip_id, port, 0); 12267 } else { 12268 bnx2x_set_xmac_rxtx(params, 0); 12269 bnx2x_set_umac_rxtx(params, 0); 12270 } 12271 /* Disable emac */ 12272 if (!CHIP_IS_E3(bp)) 12273 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); 12274 12275 usleep_range(10000, 20000); 12276 /* The PHY reset is controlled by GPIO 1 12277 * Hold it as vars low 12278 */ 12279 /* Clear link led */ 12280 bnx2x_set_mdio_clk(bp, params->chip_id, port); 12281 bnx2x_set_led(params, vars, LED_MODE_OFF, 0); 12282 12283 if (reset_ext_phy) { 12284 for (phy_index = EXT_PHY1; phy_index < params->num_phys; 12285 phy_index++) { 12286 if (params->phy[phy_index].link_reset) { 12287 bnx2x_set_aer_mmd(params, 12288 ¶ms->phy[phy_index]); 12289 params->phy[phy_index].link_reset( 12290 ¶ms->phy[phy_index], 12291 params); 12292 } 12293 if (params->phy[phy_index].flags & 12294 FLAGS_REARM_LATCH_SIGNAL) 12295 clear_latch_ind = 1; 12296 } 12297 } 12298 12299 if (clear_latch_ind) { 12300 /* Clear latching indication */ 12301 bnx2x_rearm_latch_signal(bp, port, 0); 12302 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4, 12303 1 << NIG_LATCH_BC_ENABLE_MI_INT); 12304 } 12305 if (params->phy[INT_PHY].link_reset) 12306 params->phy[INT_PHY].link_reset( 12307 ¶ms->phy[INT_PHY], params); 12308 12309 /* Disable nig ingress interface */ 12310 if (!CHIP_IS_E3(bp)) { 12311 /* Reset BigMac */ 12312 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 12313 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 12314 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0); 12315 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0); 12316 } else { 12317 u32 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 12318 bnx2x_set_xumac_nig(params, 0, 0); 12319 if (REG_RD(bp, MISC_REG_RESET_REG_2) & 12320 MISC_REGISTERS_RESET_REG_2_XMAC) 12321 REG_WR(bp, xmac_base + XMAC_REG_CTRL, 12322 XMAC_CTRL_REG_SOFT_RESET); 12323 } 12324 vars->link_up = 0; 12325 vars->phy_flags = 0; 12326 return 0; 12327 } 12328 int bnx2x_lfa_reset(struct link_params *params, 12329 struct link_vars *vars) 12330 { 12331 struct bnx2x *bp = params->bp; 12332 vars->link_up = 0; 12333 vars->phy_flags = 0; 12334 if (!params->lfa_base) 12335 return bnx2x_link_reset(params, vars, 1); 12336 /* 12337 * Activate NIG drain so that during this time the device won't send 12338 * anything while it is unable to response. 12339 */ 12340 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1); 12341 12342 /* 12343 * Close gracefully the gate from BMAC to NIG such that no half packets 12344 * are passed. 12345 */ 12346 if (!CHIP_IS_E3(bp)) 12347 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0); 12348 12349 if (CHIP_IS_E3(bp)) { 12350 bnx2x_set_xmac_rxtx(params, 0); 12351 bnx2x_set_umac_rxtx(params, 0); 12352 } 12353 /* Wait 10ms for the pipe to clean up*/ 12354 usleep_range(10000, 20000); 12355 12356 /* Clean the NIG-BRB using the network filters in a way that will 12357 * not cut a packet in the middle. 12358 */ 12359 bnx2x_set_rx_filter(params, 0); 12360 12361 /* 12362 * Re-open the gate between the BMAC and the NIG, after verifying the 12363 * gate to the BRB is closed, otherwise packets may arrive to the 12364 * firmware before driver had initialized it. The target is to achieve 12365 * minimum management protocol down time. 12366 */ 12367 if (!CHIP_IS_E3(bp)) 12368 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 1); 12369 12370 if (CHIP_IS_E3(bp)) { 12371 bnx2x_set_xmac_rxtx(params, 1); 12372 bnx2x_set_umac_rxtx(params, 1); 12373 } 12374 /* Disable NIG drain */ 12375 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 12376 return 0; 12377 } 12378 12379 /****************************************************************************/ 12380 /* Common function */ 12381 /****************************************************************************/ 12382 static int bnx2x_8073_common_init_phy(struct bnx2x *bp, 12383 u32 shmem_base_path[], 12384 u32 shmem2_base_path[], u8 phy_index, 12385 u32 chip_id) 12386 { 12387 struct bnx2x_phy phy[PORT_MAX]; 12388 struct bnx2x_phy *phy_blk[PORT_MAX]; 12389 u16 val; 12390 s8 port = 0; 12391 s8 port_of_path = 0; 12392 u32 swap_val, swap_override; 12393 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); 12394 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); 12395 port ^= (swap_val && swap_override); 12396 bnx2x_ext_phy_hw_reset(bp, port); 12397 /* PART1 - Reset both phys */ 12398 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 12399 u32 shmem_base, shmem2_base; 12400 /* In E2, same phy is using for port0 of the two paths */ 12401 if (CHIP_IS_E1x(bp)) { 12402 shmem_base = shmem_base_path[0]; 12403 shmem2_base = shmem2_base_path[0]; 12404 port_of_path = port; 12405 } else { 12406 shmem_base = shmem_base_path[port]; 12407 shmem2_base = shmem2_base_path[port]; 12408 port_of_path = 0; 12409 } 12410 12411 /* Extract the ext phy address for the port */ 12412 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, 12413 port_of_path, &phy[port]) != 12414 0) { 12415 DP(NETIF_MSG_LINK, "populate_phy failed\n"); 12416 return -EINVAL; 12417 } 12418 /* Disable attentions */ 12419 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + 12420 port_of_path*4, 12421 (NIG_MASK_XGXS0_LINK_STATUS | 12422 NIG_MASK_XGXS0_LINK10G | 12423 NIG_MASK_SERDES0_LINK_STATUS | 12424 NIG_MASK_MI_INT)); 12425 12426 /* Need to take the phy out of low power mode in order 12427 * to write to access its registers 12428 */ 12429 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 12430 MISC_REGISTERS_GPIO_OUTPUT_HIGH, 12431 port); 12432 12433 /* Reset the phy */ 12434 bnx2x_cl45_write(bp, &phy[port], 12435 MDIO_PMA_DEVAD, 12436 MDIO_PMA_REG_CTRL, 12437 1<<15); 12438 } 12439 12440 /* Add delay of 150ms after reset */ 12441 msleep(150); 12442 12443 if (phy[PORT_0].addr & 0x1) { 12444 phy_blk[PORT_0] = &(phy[PORT_1]); 12445 phy_blk[PORT_1] = &(phy[PORT_0]); 12446 } else { 12447 phy_blk[PORT_0] = &(phy[PORT_0]); 12448 phy_blk[PORT_1] = &(phy[PORT_1]); 12449 } 12450 12451 /* PART2 - Download firmware to both phys */ 12452 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 12453 if (CHIP_IS_E1x(bp)) 12454 port_of_path = port; 12455 else 12456 port_of_path = 0; 12457 12458 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n", 12459 phy_blk[port]->addr); 12460 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port], 12461 port_of_path)) 12462 return -EINVAL; 12463 12464 /* Only set bit 10 = 1 (Tx power down) */ 12465 bnx2x_cl45_read(bp, phy_blk[port], 12466 MDIO_PMA_DEVAD, 12467 MDIO_PMA_REG_TX_POWER_DOWN, &val); 12468 12469 /* Phase1 of TX_POWER_DOWN reset */ 12470 bnx2x_cl45_write(bp, phy_blk[port], 12471 MDIO_PMA_DEVAD, 12472 MDIO_PMA_REG_TX_POWER_DOWN, 12473 (val | 1<<10)); 12474 } 12475 12476 /* Toggle Transmitter: Power down and then up with 600ms delay 12477 * between 12478 */ 12479 msleep(600); 12480 12481 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */ 12482 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 12483 /* Phase2 of POWER_DOWN_RESET */ 12484 /* Release bit 10 (Release Tx power down) */ 12485 bnx2x_cl45_read(bp, phy_blk[port], 12486 MDIO_PMA_DEVAD, 12487 MDIO_PMA_REG_TX_POWER_DOWN, &val); 12488 12489 bnx2x_cl45_write(bp, phy_blk[port], 12490 MDIO_PMA_DEVAD, 12491 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10)))); 12492 usleep_range(15000, 30000); 12493 12494 /* Read modify write the SPI-ROM version select register */ 12495 bnx2x_cl45_read(bp, phy_blk[port], 12496 MDIO_PMA_DEVAD, 12497 MDIO_PMA_REG_EDC_FFE_MAIN, &val); 12498 bnx2x_cl45_write(bp, phy_blk[port], 12499 MDIO_PMA_DEVAD, 12500 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12))); 12501 12502 /* set GPIO2 back to LOW */ 12503 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 12504 MISC_REGISTERS_GPIO_OUTPUT_LOW, port); 12505 } 12506 return 0; 12507 } 12508 static int bnx2x_8726_common_init_phy(struct bnx2x *bp, 12509 u32 shmem_base_path[], 12510 u32 shmem2_base_path[], u8 phy_index, 12511 u32 chip_id) 12512 { 12513 u32 val; 12514 s8 port; 12515 struct bnx2x_phy phy; 12516 /* Use port1 because of the static port-swap */ 12517 /* Enable the module detection interrupt */ 12518 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN); 12519 val |= ((1<<MISC_REGISTERS_GPIO_3)| 12520 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT))); 12521 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val); 12522 12523 bnx2x_ext_phy_hw_reset(bp, 0); 12524 usleep_range(5000, 10000); 12525 for (port = 0; port < PORT_MAX; port++) { 12526 u32 shmem_base, shmem2_base; 12527 12528 /* In E2, same phy is using for port0 of the two paths */ 12529 if (CHIP_IS_E1x(bp)) { 12530 shmem_base = shmem_base_path[0]; 12531 shmem2_base = shmem2_base_path[0]; 12532 } else { 12533 shmem_base = shmem_base_path[port]; 12534 shmem2_base = shmem2_base_path[port]; 12535 } 12536 /* Extract the ext phy address for the port */ 12537 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, 12538 port, &phy) != 12539 0) { 12540 DP(NETIF_MSG_LINK, "populate phy failed\n"); 12541 return -EINVAL; 12542 } 12543 12544 /* Reset phy*/ 12545 bnx2x_cl45_write(bp, &phy, 12546 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001); 12547 12548 12549 /* Set fault module detected LED on */ 12550 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, 12551 MISC_REGISTERS_GPIO_HIGH, 12552 port); 12553 } 12554 12555 return 0; 12556 } 12557 static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base, 12558 u8 *io_gpio, u8 *io_port) 12559 { 12560 12561 u32 phy_gpio_reset = REG_RD(bp, shmem_base + 12562 offsetof(struct shmem_region, 12563 dev_info.port_hw_config[PORT_0].default_cfg)); 12564 switch (phy_gpio_reset) { 12565 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0: 12566 *io_gpio = 0; 12567 *io_port = 0; 12568 break; 12569 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0: 12570 *io_gpio = 1; 12571 *io_port = 0; 12572 break; 12573 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0: 12574 *io_gpio = 2; 12575 *io_port = 0; 12576 break; 12577 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0: 12578 *io_gpio = 3; 12579 *io_port = 0; 12580 break; 12581 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1: 12582 *io_gpio = 0; 12583 *io_port = 1; 12584 break; 12585 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1: 12586 *io_gpio = 1; 12587 *io_port = 1; 12588 break; 12589 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1: 12590 *io_gpio = 2; 12591 *io_port = 1; 12592 break; 12593 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1: 12594 *io_gpio = 3; 12595 *io_port = 1; 12596 break; 12597 default: 12598 /* Don't override the io_gpio and io_port */ 12599 break; 12600 } 12601 } 12602 12603 static int bnx2x_8727_common_init_phy(struct bnx2x *bp, 12604 u32 shmem_base_path[], 12605 u32 shmem2_base_path[], u8 phy_index, 12606 u32 chip_id) 12607 { 12608 s8 port, reset_gpio; 12609 u32 swap_val, swap_override; 12610 struct bnx2x_phy phy[PORT_MAX]; 12611 struct bnx2x_phy *phy_blk[PORT_MAX]; 12612 s8 port_of_path; 12613 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); 12614 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); 12615 12616 reset_gpio = MISC_REGISTERS_GPIO_1; 12617 port = 1; 12618 12619 /* Retrieve the reset gpio/port which control the reset. 12620 * Default is GPIO1, PORT1 12621 */ 12622 bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0], 12623 (u8 *)&reset_gpio, (u8 *)&port); 12624 12625 /* Calculate the port based on port swap */ 12626 port ^= (swap_val && swap_override); 12627 12628 /* Initiate PHY reset*/ 12629 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW, 12630 port); 12631 usleep_range(1000, 2000); 12632 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH, 12633 port); 12634 12635 usleep_range(5000, 10000); 12636 12637 /* PART1 - Reset both phys */ 12638 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 12639 u32 shmem_base, shmem2_base; 12640 12641 /* In E2, same phy is using for port0 of the two paths */ 12642 if (CHIP_IS_E1x(bp)) { 12643 shmem_base = shmem_base_path[0]; 12644 shmem2_base = shmem2_base_path[0]; 12645 port_of_path = port; 12646 } else { 12647 shmem_base = shmem_base_path[port]; 12648 shmem2_base = shmem2_base_path[port]; 12649 port_of_path = 0; 12650 } 12651 12652 /* Extract the ext phy address for the port */ 12653 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, 12654 port_of_path, &phy[port]) != 12655 0) { 12656 DP(NETIF_MSG_LINK, "populate phy failed\n"); 12657 return -EINVAL; 12658 } 12659 /* disable attentions */ 12660 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + 12661 port_of_path*4, 12662 (NIG_MASK_XGXS0_LINK_STATUS | 12663 NIG_MASK_XGXS0_LINK10G | 12664 NIG_MASK_SERDES0_LINK_STATUS | 12665 NIG_MASK_MI_INT)); 12666 12667 12668 /* Reset the phy */ 12669 bnx2x_cl45_write(bp, &phy[port], 12670 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); 12671 } 12672 12673 /* Add delay of 150ms after reset */ 12674 msleep(150); 12675 if (phy[PORT_0].addr & 0x1) { 12676 phy_blk[PORT_0] = &(phy[PORT_1]); 12677 phy_blk[PORT_1] = &(phy[PORT_0]); 12678 } else { 12679 phy_blk[PORT_0] = &(phy[PORT_0]); 12680 phy_blk[PORT_1] = &(phy[PORT_1]); 12681 } 12682 /* PART2 - Download firmware to both phys */ 12683 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 12684 if (CHIP_IS_E1x(bp)) 12685 port_of_path = port; 12686 else 12687 port_of_path = 0; 12688 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n", 12689 phy_blk[port]->addr); 12690 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port], 12691 port_of_path)) 12692 return -EINVAL; 12693 /* Disable PHY transmitter output */ 12694 bnx2x_cl45_write(bp, phy_blk[port], 12695 MDIO_PMA_DEVAD, 12696 MDIO_PMA_REG_TX_DISABLE, 1); 12697 12698 } 12699 return 0; 12700 } 12701 12702 static int bnx2x_84833_common_init_phy(struct bnx2x *bp, 12703 u32 shmem_base_path[], 12704 u32 shmem2_base_path[], 12705 u8 phy_index, 12706 u32 chip_id) 12707 { 12708 u8 reset_gpios; 12709 reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, chip_id); 12710 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW); 12711 udelay(10); 12712 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH); 12713 DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n", 12714 reset_gpios); 12715 return 0; 12716 } 12717 12718 static int bnx2x_84833_pre_init_phy(struct bnx2x *bp, 12719 struct bnx2x_phy *phy) 12720 { 12721 u16 val, cnt; 12722 /* Wait for FW completing its initialization. */ 12723 for (cnt = 0; cnt < 1500; cnt++) { 12724 bnx2x_cl45_read(bp, phy, 12725 MDIO_PMA_DEVAD, 12726 MDIO_PMA_REG_CTRL, &val); 12727 if (!(val & (1<<15))) 12728 break; 12729 usleep_range(1000, 2000); 12730 } 12731 if (cnt >= 1500) { 12732 DP(NETIF_MSG_LINK, "84833 reset timeout\n"); 12733 return -EINVAL; 12734 } 12735 12736 /* Put the port in super isolate mode. */ 12737 bnx2x_cl45_read(bp, phy, 12738 MDIO_CTL_DEVAD, 12739 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val); 12740 val |= MDIO_84833_SUPER_ISOLATE; 12741 bnx2x_cl45_write(bp, phy, 12742 MDIO_CTL_DEVAD, 12743 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val); 12744 12745 /* Save spirom version */ 12746 bnx2x_save_848xx_spirom_version(phy, bp, PORT_0); 12747 return 0; 12748 } 12749 12750 int bnx2x_pre_init_phy(struct bnx2x *bp, 12751 u32 shmem_base, 12752 u32 shmem2_base, 12753 u32 chip_id) 12754 { 12755 int rc = 0; 12756 struct bnx2x_phy phy; 12757 bnx2x_set_mdio_clk(bp, chip_id, PORT_0); 12758 if (bnx2x_populate_phy(bp, EXT_PHY1, shmem_base, shmem2_base, 12759 PORT_0, &phy)) { 12760 DP(NETIF_MSG_LINK, "populate_phy failed\n"); 12761 return -EINVAL; 12762 } 12763 switch (phy.type) { 12764 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833: 12765 rc = bnx2x_84833_pre_init_phy(bp, &phy); 12766 break; 12767 default: 12768 break; 12769 } 12770 return rc; 12771 } 12772 12773 static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[], 12774 u32 shmem2_base_path[], u8 phy_index, 12775 u32 ext_phy_type, u32 chip_id) 12776 { 12777 int rc = 0; 12778 12779 switch (ext_phy_type) { 12780 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: 12781 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path, 12782 shmem2_base_path, 12783 phy_index, chip_id); 12784 break; 12785 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 12786 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 12787 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC: 12788 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path, 12789 shmem2_base_path, 12790 phy_index, chip_id); 12791 break; 12792 12793 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 12794 /* GPIO1 affects both ports, so there's need to pull 12795 * it for single port alone 12796 */ 12797 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path, 12798 shmem2_base_path, 12799 phy_index, chip_id); 12800 break; 12801 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833: 12802 /* GPIO3's are linked, and so both need to be toggled 12803 * to obtain required 2us pulse. 12804 */ 12805 rc = bnx2x_84833_common_init_phy(bp, shmem_base_path, 12806 shmem2_base_path, 12807 phy_index, chip_id); 12808 break; 12809 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: 12810 rc = -EINVAL; 12811 break; 12812 default: 12813 DP(NETIF_MSG_LINK, 12814 "ext_phy 0x%x common init not required\n", 12815 ext_phy_type); 12816 break; 12817 } 12818 12819 if (rc) 12820 netdev_err(bp->dev, "Warning: PHY was not initialized," 12821 " Port %d\n", 12822 0); 12823 return rc; 12824 } 12825 12826 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[], 12827 u32 shmem2_base_path[], u32 chip_id) 12828 { 12829 int rc = 0; 12830 u32 phy_ver, val; 12831 u8 phy_index = 0; 12832 u32 ext_phy_type, ext_phy_config; 12833 bnx2x_set_mdio_clk(bp, chip_id, PORT_0); 12834 bnx2x_set_mdio_clk(bp, chip_id, PORT_1); 12835 DP(NETIF_MSG_LINK, "Begin common phy init\n"); 12836 if (CHIP_IS_E3(bp)) { 12837 /* Enable EPIO */ 12838 val = REG_RD(bp, MISC_REG_GEN_PURP_HWG); 12839 REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1); 12840 } 12841 /* Check if common init was already done */ 12842 phy_ver = REG_RD(bp, shmem_base_path[0] + 12843 offsetof(struct shmem_region, 12844 port_mb[PORT_0].ext_phy_fw_version)); 12845 if (phy_ver) { 12846 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n", 12847 phy_ver); 12848 return 0; 12849 } 12850 12851 /* Read the ext_phy_type for arbitrary port(0) */ 12852 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS; 12853 phy_index++) { 12854 ext_phy_config = bnx2x_get_ext_phy_config(bp, 12855 shmem_base_path[0], 12856 phy_index, 0); 12857 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); 12858 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path, 12859 shmem2_base_path, 12860 phy_index, ext_phy_type, 12861 chip_id); 12862 } 12863 return rc; 12864 } 12865 12866 static void bnx2x_check_over_curr(struct link_params *params, 12867 struct link_vars *vars) 12868 { 12869 struct bnx2x *bp = params->bp; 12870 u32 cfg_pin; 12871 u8 port = params->port; 12872 u32 pin_val; 12873 12874 cfg_pin = (REG_RD(bp, params->shmem_base + 12875 offsetof(struct shmem_region, 12876 dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) & 12877 PORT_HW_CFG_E3_OVER_CURRENT_MASK) >> 12878 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT; 12879 12880 /* Ignore check if no external input PIN available */ 12881 if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0) 12882 return; 12883 12884 if (!pin_val) { 12885 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) { 12886 netdev_err(bp->dev, "Error: Power fault on Port %d has" 12887 " been detected and the power to " 12888 "that SFP+ module has been removed" 12889 " to prevent failure of the card." 12890 " Please remove the SFP+ module and" 12891 " restart the system to clear this" 12892 " error.\n", 12893 params->port); 12894 vars->phy_flags |= PHY_OVER_CURRENT_FLAG; 12895 } 12896 } else 12897 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG; 12898 } 12899 12900 /* Returns 0 if no change occured since last check; 1 otherwise. */ 12901 static u8 bnx2x_analyze_link_error(struct link_params *params, 12902 struct link_vars *vars, u32 status, 12903 u32 phy_flag, u32 link_flag, u8 notify) 12904 { 12905 struct bnx2x *bp = params->bp; 12906 /* Compare new value with previous value */ 12907 u8 led_mode; 12908 u32 old_status = (vars->phy_flags & phy_flag) ? 1 : 0; 12909 12910 if ((status ^ old_status) == 0) 12911 return 0; 12912 12913 /* If values differ */ 12914 switch (phy_flag) { 12915 case PHY_HALF_OPEN_CONN_FLAG: 12916 DP(NETIF_MSG_LINK, "Analyze Remote Fault\n"); 12917 break; 12918 case PHY_SFP_TX_FAULT_FLAG: 12919 DP(NETIF_MSG_LINK, "Analyze TX Fault\n"); 12920 break; 12921 default: 12922 DP(NETIF_MSG_LINK, "Analyze UNKOWN\n"); 12923 } 12924 DP(NETIF_MSG_LINK, "Link changed:[%x %x]->%x\n", vars->link_up, 12925 old_status, status); 12926 12927 /* a. Update shmem->link_status accordingly 12928 * b. Update link_vars->link_up 12929 */ 12930 if (status) { 12931 vars->link_status &= ~LINK_STATUS_LINK_UP; 12932 vars->link_status |= link_flag; 12933 vars->link_up = 0; 12934 vars->phy_flags |= phy_flag; 12935 12936 /* activate nig drain */ 12937 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1); 12938 /* Set LED mode to off since the PHY doesn't know about these 12939 * errors 12940 */ 12941 led_mode = LED_MODE_OFF; 12942 } else { 12943 vars->link_status |= LINK_STATUS_LINK_UP; 12944 vars->link_status &= ~link_flag; 12945 vars->link_up = 1; 12946 vars->phy_flags &= ~phy_flag; 12947 led_mode = LED_MODE_OPER; 12948 12949 /* Clear nig drain */ 12950 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 12951 } 12952 bnx2x_sync_link(params, vars); 12953 /* Update the LED according to the link state */ 12954 bnx2x_set_led(params, vars, led_mode, SPEED_10000); 12955 12956 /* Update link status in the shared memory */ 12957 bnx2x_update_mng(params, vars->link_status); 12958 12959 /* C. Trigger General Attention */ 12960 vars->periodic_flags |= PERIODIC_FLAGS_LINK_EVENT; 12961 if (notify) 12962 bnx2x_notify_link_changed(bp); 12963 12964 return 1; 12965 } 12966 12967 /****************************************************************************** 12968 * Description: 12969 * This function checks for half opened connection change indication. 12970 * When such change occurs, it calls the bnx2x_analyze_link_error 12971 * to check if Remote Fault is set or cleared. Reception of remote fault 12972 * status message in the MAC indicates that the peer's MAC has detected 12973 * a fault, for example, due to break in the TX side of fiber. 12974 * 12975 ******************************************************************************/ 12976 int bnx2x_check_half_open_conn(struct link_params *params, 12977 struct link_vars *vars, 12978 u8 notify) 12979 { 12980 struct bnx2x *bp = params->bp; 12981 u32 lss_status = 0; 12982 u32 mac_base; 12983 /* In case link status is physically up @ 10G do */ 12984 if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) || 12985 (REG_RD(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4))) 12986 return 0; 12987 12988 if (CHIP_IS_E3(bp) && 12989 (REG_RD(bp, MISC_REG_RESET_REG_2) & 12990 (MISC_REGISTERS_RESET_REG_2_XMAC))) { 12991 /* Check E3 XMAC */ 12992 /* Note that link speed cannot be queried here, since it may be 12993 * zero while link is down. In case UMAC is active, LSS will 12994 * simply not be set 12995 */ 12996 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 12997 12998 /* Clear stick bits (Requires rising edge) */ 12999 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); 13000 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 13001 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS | 13002 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS); 13003 if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS)) 13004 lss_status = 1; 13005 13006 bnx2x_analyze_link_error(params, vars, lss_status, 13007 PHY_HALF_OPEN_CONN_FLAG, 13008 LINK_STATUS_NONE, notify); 13009 } else if (REG_RD(bp, MISC_REG_RESET_REG_2) & 13010 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) { 13011 /* Check E1X / E2 BMAC */ 13012 u32 lss_status_reg; 13013 u32 wb_data[2]; 13014 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM : 13015 NIG_REG_INGRESS_BMAC0_MEM; 13016 /* Read BIGMAC_REGISTER_RX_LSS_STATUS */ 13017 if (CHIP_IS_E2(bp)) 13018 lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT; 13019 else 13020 lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS; 13021 13022 REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2); 13023 lss_status = (wb_data[0] > 0); 13024 13025 bnx2x_analyze_link_error(params, vars, lss_status, 13026 PHY_HALF_OPEN_CONN_FLAG, 13027 LINK_STATUS_NONE, notify); 13028 } 13029 return 0; 13030 } 13031 static void bnx2x_sfp_tx_fault_detection(struct bnx2x_phy *phy, 13032 struct link_params *params, 13033 struct link_vars *vars) 13034 { 13035 struct bnx2x *bp = params->bp; 13036 u32 cfg_pin, value = 0; 13037 u8 led_change, port = params->port; 13038 13039 /* Get The SFP+ TX_Fault controlling pin ([eg]pio) */ 13040 cfg_pin = (REG_RD(bp, params->shmem_base + offsetof(struct shmem_region, 13041 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & 13042 PORT_HW_CFG_E3_TX_FAULT_MASK) >> 13043 PORT_HW_CFG_E3_TX_FAULT_SHIFT; 13044 13045 if (bnx2x_get_cfg_pin(bp, cfg_pin, &value)) { 13046 DP(NETIF_MSG_LINK, "Failed to read pin 0x%02x\n", cfg_pin); 13047 return; 13048 } 13049 13050 led_change = bnx2x_analyze_link_error(params, vars, value, 13051 PHY_SFP_TX_FAULT_FLAG, 13052 LINK_STATUS_SFP_TX_FAULT, 1); 13053 13054 if (led_change) { 13055 /* Change TX_Fault led, set link status for further syncs */ 13056 u8 led_mode; 13057 13058 if (vars->phy_flags & PHY_SFP_TX_FAULT_FLAG) { 13059 led_mode = MISC_REGISTERS_GPIO_HIGH; 13060 vars->link_status |= LINK_STATUS_SFP_TX_FAULT; 13061 } else { 13062 led_mode = MISC_REGISTERS_GPIO_LOW; 13063 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT; 13064 } 13065 13066 /* If module is unapproved, led should be on regardless */ 13067 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) { 13068 DP(NETIF_MSG_LINK, "Change TX_Fault LED: ->%x\n", 13069 led_mode); 13070 bnx2x_set_e3_module_fault_led(params, led_mode); 13071 } 13072 } 13073 } 13074 void bnx2x_period_func(struct link_params *params, struct link_vars *vars) 13075 { 13076 u16 phy_idx; 13077 struct bnx2x *bp = params->bp; 13078 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) { 13079 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) { 13080 bnx2x_set_aer_mmd(params, ¶ms->phy[phy_idx]); 13081 if (bnx2x_check_half_open_conn(params, vars, 1) != 13082 0) 13083 DP(NETIF_MSG_LINK, "Fault detection failed\n"); 13084 break; 13085 } 13086 } 13087 13088 if (CHIP_IS_E3(bp)) { 13089 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; 13090 bnx2x_set_aer_mmd(params, phy); 13091 bnx2x_check_over_curr(params, vars); 13092 if (vars->rx_tx_asic_rst) 13093 bnx2x_warpcore_config_runtime(phy, params, vars); 13094 13095 if ((REG_RD(bp, params->shmem_base + 13096 offsetof(struct shmem_region, dev_info. 13097 port_hw_config[params->port].default_cfg)) 13098 & PORT_HW_CFG_NET_SERDES_IF_MASK) == 13099 PORT_HW_CFG_NET_SERDES_IF_SFI) { 13100 if (bnx2x_is_sfp_module_plugged(phy, params)) { 13101 bnx2x_sfp_tx_fault_detection(phy, params, vars); 13102 } else if (vars->link_status & 13103 LINK_STATUS_SFP_TX_FAULT) { 13104 /* Clean trail, interrupt corrects the leds */ 13105 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT; 13106 vars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG; 13107 /* Update link status in the shared memory */ 13108 bnx2x_update_mng(params, vars->link_status); 13109 } 13110 } 13111 13112 } 13113 13114 } 13115 13116 u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base, u32 shmem2_base) 13117 { 13118 u8 phy_index; 13119 struct bnx2x_phy phy; 13120 for (phy_index = INT_PHY; phy_index < MAX_PHYS; 13121 phy_index++) { 13122 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, 13123 0, &phy) != 0) { 13124 DP(NETIF_MSG_LINK, "populate phy failed\n"); 13125 return 0; 13126 } 13127 13128 if (phy.flags & FLAGS_HW_LOCK_REQUIRED) 13129 return 1; 13130 } 13131 return 0; 13132 } 13133 13134 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp, 13135 u32 shmem_base, 13136 u32 shmem2_base, 13137 u8 port) 13138 { 13139 u8 phy_index, fan_failure_det_req = 0; 13140 struct bnx2x_phy phy; 13141 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS; 13142 phy_index++) { 13143 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, 13144 port, &phy) 13145 != 0) { 13146 DP(NETIF_MSG_LINK, "populate phy failed\n"); 13147 return 0; 13148 } 13149 fan_failure_det_req |= (phy.flags & 13150 FLAGS_FAN_FAILURE_DET_REQ); 13151 } 13152 return fan_failure_det_req; 13153 } 13154 13155 void bnx2x_hw_reset_phy(struct link_params *params) 13156 { 13157 u8 phy_index; 13158 struct bnx2x *bp = params->bp; 13159 bnx2x_update_mng(params, 0); 13160 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4, 13161 (NIG_MASK_XGXS0_LINK_STATUS | 13162 NIG_MASK_XGXS0_LINK10G | 13163 NIG_MASK_SERDES0_LINK_STATUS | 13164 NIG_MASK_MI_INT)); 13165 13166 for (phy_index = INT_PHY; phy_index < MAX_PHYS; 13167 phy_index++) { 13168 if (params->phy[phy_index].hw_reset) { 13169 params->phy[phy_index].hw_reset( 13170 ¶ms->phy[phy_index], 13171 params); 13172 params->phy[phy_index] = phy_null; 13173 } 13174 } 13175 } 13176 13177 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars, 13178 u32 chip_id, u32 shmem_base, u32 shmem2_base, 13179 u8 port) 13180 { 13181 u8 gpio_num = 0xff, gpio_port = 0xff, phy_index; 13182 u32 val; 13183 u32 offset, aeu_mask, swap_val, swap_override, sync_offset; 13184 if (CHIP_IS_E3(bp)) { 13185 if (bnx2x_get_mod_abs_int_cfg(bp, chip_id, 13186 shmem_base, 13187 port, 13188 &gpio_num, 13189 &gpio_port) != 0) 13190 return; 13191 } else { 13192 struct bnx2x_phy phy; 13193 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS; 13194 phy_index++) { 13195 if (bnx2x_populate_phy(bp, phy_index, shmem_base, 13196 shmem2_base, port, &phy) 13197 != 0) { 13198 DP(NETIF_MSG_LINK, "populate phy failed\n"); 13199 return; 13200 } 13201 if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) { 13202 gpio_num = MISC_REGISTERS_GPIO_3; 13203 gpio_port = port; 13204 break; 13205 } 13206 } 13207 } 13208 13209 if (gpio_num == 0xff) 13210 return; 13211 13212 /* Set GPIO3 to trigger SFP+ module insertion/removal */ 13213 bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port); 13214 13215 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); 13216 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); 13217 gpio_port ^= (swap_val && swap_override); 13218 13219 vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 << 13220 (gpio_num + (gpio_port << 2)); 13221 13222 sync_offset = shmem_base + 13223 offsetof(struct shmem_region, 13224 dev_info.port_hw_config[port].aeu_int_mask); 13225 REG_WR(bp, sync_offset, vars->aeu_int_mask); 13226 13227 DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n", 13228 gpio_num, gpio_port, vars->aeu_int_mask); 13229 13230 if (port == 0) 13231 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0; 13232 else 13233 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0; 13234 13235 /* Open appropriate AEU for interrupts */ 13236 aeu_mask = REG_RD(bp, offset); 13237 aeu_mask |= vars->aeu_int_mask; 13238 REG_WR(bp, offset, aeu_mask); 13239 13240 /* Enable the GPIO to trigger interrupt */ 13241 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN); 13242 val |= 1 << (gpio_num + (gpio_port << 2)); 13243 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val); 13244 } 13245