1 /* bnx2x_hsi.h: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2012 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 */ 9 #ifndef BNX2X_HSI_H 10 #define BNX2X_HSI_H 11 12 #include "bnx2x_fw_defs.h" 13 #include "bnx2x_mfw_req.h" 14 15 #define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e 16 17 struct license_key { 18 u32 reserved[6]; 19 20 u32 max_iscsi_conn; 21 #define BNX2X_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF 22 #define BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT 0 23 #define BNX2X_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000 24 #define BNX2X_MAX_ISCSI_INIT_CONN_SHIFT 16 25 26 u32 reserved_a; 27 28 u32 max_fcoe_conn; 29 #define BNX2X_MAX_FCOE_TRGT_CONN_MASK 0xFFFF 30 #define BNX2X_MAX_FCOE_TRGT_CONN_SHIFT 0 31 #define BNX2X_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000 32 #define BNX2X_MAX_FCOE_INIT_CONN_SHIFT 16 33 34 u32 reserved_b[4]; 35 }; 36 37 /**************************************************************************** 38 * Shared HW configuration * 39 ****************************************************************************/ 40 #define PIN_CFG_NA 0x00000000 41 #define PIN_CFG_GPIO0_P0 0x00000001 42 #define PIN_CFG_GPIO1_P0 0x00000002 43 #define PIN_CFG_GPIO2_P0 0x00000003 44 #define PIN_CFG_GPIO3_P0 0x00000004 45 #define PIN_CFG_GPIO0_P1 0x00000005 46 #define PIN_CFG_GPIO1_P1 0x00000006 47 #define PIN_CFG_GPIO2_P1 0x00000007 48 #define PIN_CFG_GPIO3_P1 0x00000008 49 #define PIN_CFG_EPIO0 0x00000009 50 #define PIN_CFG_EPIO1 0x0000000a 51 #define PIN_CFG_EPIO2 0x0000000b 52 #define PIN_CFG_EPIO3 0x0000000c 53 #define PIN_CFG_EPIO4 0x0000000d 54 #define PIN_CFG_EPIO5 0x0000000e 55 #define PIN_CFG_EPIO6 0x0000000f 56 #define PIN_CFG_EPIO7 0x00000010 57 #define PIN_CFG_EPIO8 0x00000011 58 #define PIN_CFG_EPIO9 0x00000012 59 #define PIN_CFG_EPIO10 0x00000013 60 #define PIN_CFG_EPIO11 0x00000014 61 #define PIN_CFG_EPIO12 0x00000015 62 #define PIN_CFG_EPIO13 0x00000016 63 #define PIN_CFG_EPIO14 0x00000017 64 #define PIN_CFG_EPIO15 0x00000018 65 #define PIN_CFG_EPIO16 0x00000019 66 #define PIN_CFG_EPIO17 0x0000001a 67 #define PIN_CFG_EPIO18 0x0000001b 68 #define PIN_CFG_EPIO19 0x0000001c 69 #define PIN_CFG_EPIO20 0x0000001d 70 #define PIN_CFG_EPIO21 0x0000001e 71 #define PIN_CFG_EPIO22 0x0000001f 72 #define PIN_CFG_EPIO23 0x00000020 73 #define PIN_CFG_EPIO24 0x00000021 74 #define PIN_CFG_EPIO25 0x00000022 75 #define PIN_CFG_EPIO26 0x00000023 76 #define PIN_CFG_EPIO27 0x00000024 77 #define PIN_CFG_EPIO28 0x00000025 78 #define PIN_CFG_EPIO29 0x00000026 79 #define PIN_CFG_EPIO30 0x00000027 80 #define PIN_CFG_EPIO31 0x00000028 81 82 /* EPIO definition */ 83 #define EPIO_CFG_NA 0x00000000 84 #define EPIO_CFG_EPIO0 0x00000001 85 #define EPIO_CFG_EPIO1 0x00000002 86 #define EPIO_CFG_EPIO2 0x00000003 87 #define EPIO_CFG_EPIO3 0x00000004 88 #define EPIO_CFG_EPIO4 0x00000005 89 #define EPIO_CFG_EPIO5 0x00000006 90 #define EPIO_CFG_EPIO6 0x00000007 91 #define EPIO_CFG_EPIO7 0x00000008 92 #define EPIO_CFG_EPIO8 0x00000009 93 #define EPIO_CFG_EPIO9 0x0000000a 94 #define EPIO_CFG_EPIO10 0x0000000b 95 #define EPIO_CFG_EPIO11 0x0000000c 96 #define EPIO_CFG_EPIO12 0x0000000d 97 #define EPIO_CFG_EPIO13 0x0000000e 98 #define EPIO_CFG_EPIO14 0x0000000f 99 #define EPIO_CFG_EPIO15 0x00000010 100 #define EPIO_CFG_EPIO16 0x00000011 101 #define EPIO_CFG_EPIO17 0x00000012 102 #define EPIO_CFG_EPIO18 0x00000013 103 #define EPIO_CFG_EPIO19 0x00000014 104 #define EPIO_CFG_EPIO20 0x00000015 105 #define EPIO_CFG_EPIO21 0x00000016 106 #define EPIO_CFG_EPIO22 0x00000017 107 #define EPIO_CFG_EPIO23 0x00000018 108 #define EPIO_CFG_EPIO24 0x00000019 109 #define EPIO_CFG_EPIO25 0x0000001a 110 #define EPIO_CFG_EPIO26 0x0000001b 111 #define EPIO_CFG_EPIO27 0x0000001c 112 #define EPIO_CFG_EPIO28 0x0000001d 113 #define EPIO_CFG_EPIO29 0x0000001e 114 #define EPIO_CFG_EPIO30 0x0000001f 115 #define EPIO_CFG_EPIO31 0x00000020 116 117 118 struct shared_hw_cfg { /* NVRAM Offset */ 119 /* Up to 16 bytes of NULL-terminated string */ 120 u8 part_num[16]; /* 0x104 */ 121 122 u32 config; /* 0x114 */ 123 #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001 124 #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0 125 #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000 126 #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001 127 #define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN 0x00000002 128 129 #define SHARED_HW_CFG_PORT_SWAP 0x00000004 130 131 #define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008 132 133 #define SHARED_HW_CFG_PCIE_GEN3_DISABLED 0x00000000 134 #define SHARED_HW_CFG_PCIE_GEN3_ENABLED 0x00000010 135 136 #define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700 137 #define SHARED_HW_CFG_MFW_SELECT_SHIFT 8 138 /* Whatever MFW found in NVM 139 (if multiple found, priority order is: NC-SI, UMP, IPMI) */ 140 #define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000 141 #define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100 142 #define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200 143 #define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300 144 /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI 145 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 146 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400 147 /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI 148 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 149 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500 150 /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP 151 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 152 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600 153 154 #define SHARED_HW_CFG_LED_MODE_MASK 0x000f0000 155 #define SHARED_HW_CFG_LED_MODE_SHIFT 16 156 #define SHARED_HW_CFG_LED_MAC1 0x00000000 157 #define SHARED_HW_CFG_LED_PHY1 0x00010000 158 #define SHARED_HW_CFG_LED_PHY2 0x00020000 159 #define SHARED_HW_CFG_LED_PHY3 0x00030000 160 #define SHARED_HW_CFG_LED_MAC2 0x00040000 161 #define SHARED_HW_CFG_LED_PHY4 0x00050000 162 #define SHARED_HW_CFG_LED_PHY5 0x00060000 163 #define SHARED_HW_CFG_LED_PHY6 0x00070000 164 #define SHARED_HW_CFG_LED_MAC3 0x00080000 165 #define SHARED_HW_CFG_LED_PHY7 0x00090000 166 #define SHARED_HW_CFG_LED_PHY9 0x000a0000 167 #define SHARED_HW_CFG_LED_PHY11 0x000b0000 168 #define SHARED_HW_CFG_LED_MAC4 0x000c0000 169 #define SHARED_HW_CFG_LED_PHY8 0x000d0000 170 #define SHARED_HW_CFG_LED_EXTPHY1 0x000e0000 171 172 173 #define SHARED_HW_CFG_AN_ENABLE_MASK 0x3f000000 174 #define SHARED_HW_CFG_AN_ENABLE_SHIFT 24 175 #define SHARED_HW_CFG_AN_ENABLE_CL37 0x01000000 176 #define SHARED_HW_CFG_AN_ENABLE_CL73 0x02000000 177 #define SHARED_HW_CFG_AN_ENABLE_BAM 0x04000000 178 #define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 0x08000000 179 #define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 0x10000000 180 #define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 0x20000000 181 182 #define SHARED_HW_CFG_SRIOV_MASK 0x40000000 183 #define SHARED_HW_CFG_SRIOV_DISABLED 0x00000000 184 #define SHARED_HW_CFG_SRIOV_ENABLED 0x40000000 185 186 #define SHARED_HW_CFG_ATC_MASK 0x80000000 187 #define SHARED_HW_CFG_ATC_DISABLED 0x00000000 188 #define SHARED_HW_CFG_ATC_ENABLED 0x80000000 189 190 u32 config2; /* 0x118 */ 191 /* one time auto detect grace period (in sec) */ 192 #define SHARED_HW_CFG_GRACE_PERIOD_MASK 0x000000ff 193 #define SHARED_HW_CFG_GRACE_PERIOD_SHIFT 0 194 195 #define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100 196 #define SHARED_HW_CFG_PCIE_GEN2_DISABLED 0x00000000 197 198 /* The default value for the core clock is 250MHz and it is 199 achieved by setting the clock change to 4 */ 200 #define SHARED_HW_CFG_CLOCK_CHANGE_MASK 0x00000e00 201 #define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT 9 202 203 #define SHARED_HW_CFG_SMBUS_TIMING_MASK 0x00001000 204 #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000 205 #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000 206 207 #define SHARED_HW_CFG_HIDE_PORT1 0x00002000 208 209 #define SHARED_HW_CFG_WOL_CAPABLE_MASK 0x00004000 210 #define SHARED_HW_CFG_WOL_CAPABLE_DISABLED 0x00000000 211 #define SHARED_HW_CFG_WOL_CAPABLE_ENABLED 0x00004000 212 213 /* Output low when PERST is asserted */ 214 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_MASK 0x00008000 215 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_DISABLED 0x00000000 216 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_ENABLED 0x00008000 217 218 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_MASK 0x00070000 219 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_SHIFT 16 220 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_HW 0x00000000 221 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_0DB 0x00010000 222 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_3_5DB 0x00020000 223 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_6_0DB 0x00030000 224 225 /* The fan failure mechanism is usually related to the PHY type 226 since the power consumption of the board is determined by the PHY. 227 Currently, fan is required for most designs with SFX7101, BCM8727 228 and BCM8481. If a fan is not required for a board which uses one 229 of those PHYs, this field should be set to "Disabled". If a fan is 230 required for a different PHY type, this option should be set to 231 "Enabled". The fan failure indication is expected on SPIO5 */ 232 #define SHARED_HW_CFG_FAN_FAILURE_MASK 0x00180000 233 #define SHARED_HW_CFG_FAN_FAILURE_SHIFT 19 234 #define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE 0x00000000 235 #define SHARED_HW_CFG_FAN_FAILURE_DISABLED 0x00080000 236 #define SHARED_HW_CFG_FAN_FAILURE_ENABLED 0x00100000 237 238 /* ASPM Power Management support */ 239 #define SHARED_HW_CFG_ASPM_SUPPORT_MASK 0x00600000 240 #define SHARED_HW_CFG_ASPM_SUPPORT_SHIFT 21 241 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_ENABLED 0x00000000 242 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_DISABLED 0x00200000 243 #define SHARED_HW_CFG_ASPM_SUPPORT_L1_DISABLED 0x00400000 244 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_DISABLED 0x00600000 245 246 /* The value of PM_TL_IGNORE_REQS (bit0) in PCI register 247 tl_control_0 (register 0x2800) */ 248 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_MASK 0x00800000 249 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_DISABLED 0x00000000 250 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_ENABLED 0x00800000 251 252 #define SHARED_HW_CFG_PORT_MODE_MASK 0x01000000 253 #define SHARED_HW_CFG_PORT_MODE_2 0x00000000 254 #define SHARED_HW_CFG_PORT_MODE_4 0x01000000 255 256 #define SHARED_HW_CFG_PATH_SWAP_MASK 0x02000000 257 #define SHARED_HW_CFG_PATH_SWAP_DISABLED 0x00000000 258 #define SHARED_HW_CFG_PATH_SWAP_ENABLED 0x02000000 259 260 /* Set the MDC/MDIO access for the first external phy */ 261 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK 0x1C000000 262 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT 26 263 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE 0x00000000 264 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0 0x04000000 265 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1 0x08000000 266 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH 0x0c000000 267 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED 0x10000000 268 269 /* Set the MDC/MDIO access for the second external phy */ 270 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK 0xE0000000 271 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT 29 272 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE 0x00000000 273 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0 0x20000000 274 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1 0x40000000 275 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH 0x60000000 276 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED 0x80000000 277 278 279 u32 power_dissipated; /* 0x11c */ 280 #define SHARED_HW_CFG_POWER_MGNT_SCALE_MASK 0x00ff0000 281 #define SHARED_HW_CFG_POWER_MGNT_SCALE_SHIFT 16 282 #define SHARED_HW_CFG_POWER_MGNT_UNKNOWN_SCALE 0x00000000 283 #define SHARED_HW_CFG_POWER_MGNT_DOT_1_WATT 0x00010000 284 #define SHARED_HW_CFG_POWER_MGNT_DOT_01_WATT 0x00020000 285 #define SHARED_HW_CFG_POWER_MGNT_DOT_001_WATT 0x00030000 286 287 #define SHARED_HW_CFG_POWER_DIS_CMN_MASK 0xff000000 288 #define SHARED_HW_CFG_POWER_DIS_CMN_SHIFT 24 289 290 u32 ump_nc_si_config; /* 0x120 */ 291 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003 292 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0 293 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000 294 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001 295 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000 296 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002 297 298 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK 0x00000f00 299 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT 8 300 301 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK 0x00ff0000 302 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT 16 303 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE 0x00000000 304 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000 305 306 u32 board; /* 0x124 */ 307 #define SHARED_HW_CFG_E3_I2C_MUX0_MASK 0x0000003F 308 #define SHARED_HW_CFG_E3_I2C_MUX0_SHIFT 0 309 #define SHARED_HW_CFG_E3_I2C_MUX1_MASK 0x00000FC0 310 #define SHARED_HW_CFG_E3_I2C_MUX1_SHIFT 6 311 /* Use the PIN_CFG_XXX defines on top */ 312 #define SHARED_HW_CFG_BOARD_REV_MASK 0x00ff0000 313 #define SHARED_HW_CFG_BOARD_REV_SHIFT 16 314 315 #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0x0f000000 316 #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 24 317 318 #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0xf0000000 319 #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 28 320 321 u32 wc_lane_config; /* 0x128 */ 322 #define SHARED_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF 323 #define SHARED_HW_CFG_LANE_SWAP_CFG_SHIFT 0 324 #define SHARED_HW_CFG_LANE_SWAP_CFG_32103210 0x00001b1b 325 #define SHARED_HW_CFG_LANE_SWAP_CFG_32100123 0x00001be4 326 #define SHARED_HW_CFG_LANE_SWAP_CFG_01233210 0x0000e41b 327 #define SHARED_HW_CFG_LANE_SWAP_CFG_01230123 0x0000e4e4 328 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF 329 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0 330 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00 331 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8 332 333 /* TX lane Polarity swap */ 334 #define SHARED_HW_CFG_TX_LANE0_POL_FLIP_ENABLED 0x00010000 335 #define SHARED_HW_CFG_TX_LANE1_POL_FLIP_ENABLED 0x00020000 336 #define SHARED_HW_CFG_TX_LANE2_POL_FLIP_ENABLED 0x00040000 337 #define SHARED_HW_CFG_TX_LANE3_POL_FLIP_ENABLED 0x00080000 338 /* TX lane Polarity swap */ 339 #define SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED 0x00100000 340 #define SHARED_HW_CFG_RX_LANE1_POL_FLIP_ENABLED 0x00200000 341 #define SHARED_HW_CFG_RX_LANE2_POL_FLIP_ENABLED 0x00400000 342 #define SHARED_HW_CFG_RX_LANE3_POL_FLIP_ENABLED 0x00800000 343 344 /* Selects the port layout of the board */ 345 #define SHARED_HW_CFG_E3_PORT_LAYOUT_MASK 0x0F000000 346 #define SHARED_HW_CFG_E3_PORT_LAYOUT_SHIFT 24 347 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01 0x00000000 348 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_10 0x01000000 349 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_0123 0x02000000 350 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_1032 0x03000000 351 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_2301 0x04000000 352 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_3210 0x05000000 353 }; 354 355 356 /**************************************************************************** 357 * Port HW configuration * 358 ****************************************************************************/ 359 struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */ 360 361 u32 pci_id; 362 #define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xffff0000 363 #define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000ffff 364 365 u32 pci_sub_id; 366 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xffff0000 367 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000ffff 368 369 u32 power_dissipated; 370 #define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000ff 371 #define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0 372 #define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000ff00 373 #define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8 374 #define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00ff0000 375 #define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16 376 #define PORT_HW_CFG_POWER_DIS_D3_MASK 0xff000000 377 #define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24 378 379 u32 power_consumed; 380 #define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000ff 381 #define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0 382 #define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000ff00 383 #define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8 384 #define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00ff0000 385 #define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16 386 #define PORT_HW_CFG_POWER_CONS_D3_MASK 0xff000000 387 #define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24 388 389 u32 mac_upper; 390 #define PORT_HW_CFG_UPPERMAC_MASK 0x0000ffff 391 #define PORT_HW_CFG_UPPERMAC_SHIFT 0 392 u32 mac_lower; 393 394 u32 iscsi_mac_upper; /* Upper 16 bits are always zeroes */ 395 u32 iscsi_mac_lower; 396 397 u32 rdma_mac_upper; /* Upper 16 bits are always zeroes */ 398 u32 rdma_mac_lower; 399 400 u32 serdes_config; 401 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000ffff 402 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0 403 404 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xffff0000 405 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 16 406 407 408 /* Default values: 2P-64, 4P-32 */ 409 u32 pf_config; /* 0x158 */ 410 #define PORT_HW_CFG_PF_NUM_VF_MASK 0x0000007F 411 #define PORT_HW_CFG_PF_NUM_VF_SHIFT 0 412 413 /* Default values: 17 */ 414 #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_MASK 0x00007F00 415 #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_SHIFT 8 416 417 #define PORT_HW_CFG_ENABLE_FLR_MASK 0x00010000 418 #define PORT_HW_CFG_FLR_ENABLED 0x00010000 419 420 u32 vf_config; /* 0x15C */ 421 #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_MASK 0x0000007F 422 #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_SHIFT 0 423 424 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_MASK 0xFFFF0000 425 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_SHIFT 16 426 427 u32 mf_pci_id; /* 0x160 */ 428 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_MASK 0x0000FFFF 429 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_SHIFT 0 430 431 /* Controls the TX laser of the SFP+ module */ 432 u32 sfp_ctrl; /* 0x164 */ 433 #define PORT_HW_CFG_TX_LASER_MASK 0x000000FF 434 #define PORT_HW_CFG_TX_LASER_SHIFT 0 435 #define PORT_HW_CFG_TX_LASER_MDIO 0x00000000 436 #define PORT_HW_CFG_TX_LASER_GPIO0 0x00000001 437 #define PORT_HW_CFG_TX_LASER_GPIO1 0x00000002 438 #define PORT_HW_CFG_TX_LASER_GPIO2 0x00000003 439 #define PORT_HW_CFG_TX_LASER_GPIO3 0x00000004 440 441 /* Controls the fault module LED of the SFP+ */ 442 #define PORT_HW_CFG_FAULT_MODULE_LED_MASK 0x0000FF00 443 #define PORT_HW_CFG_FAULT_MODULE_LED_SHIFT 8 444 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO0 0x00000000 445 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO1 0x00000100 446 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO2 0x00000200 447 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO3 0x00000300 448 #define PORT_HW_CFG_FAULT_MODULE_LED_DISABLED 0x00000400 449 450 /* The output pin TX_DIS that controls the TX laser of the SFP+ 451 module. Use the PIN_CFG_XXX defines on top */ 452 u32 e3_sfp_ctrl; /* 0x168 */ 453 #define PORT_HW_CFG_E3_TX_LASER_MASK 0x000000FF 454 #define PORT_HW_CFG_E3_TX_LASER_SHIFT 0 455 456 /* The output pin for SFPP_TYPE which turns on the Fault module LED */ 457 #define PORT_HW_CFG_E3_FAULT_MDL_LED_MASK 0x0000FF00 458 #define PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT 8 459 460 /* The input pin MOD_ABS that indicates whether SFP+ module is 461 present or not. Use the PIN_CFG_XXX defines on top */ 462 #define PORT_HW_CFG_E3_MOD_ABS_MASK 0x00FF0000 463 #define PORT_HW_CFG_E3_MOD_ABS_SHIFT 16 464 465 /* The output pin PWRDIS_SFP_X which disable the power of the SFP+ 466 module. Use the PIN_CFG_XXX defines on top */ 467 #define PORT_HW_CFG_E3_PWR_DIS_MASK 0xFF000000 468 #define PORT_HW_CFG_E3_PWR_DIS_SHIFT 24 469 470 /* 471 * The input pin which signals module transmit fault. Use the 472 * PIN_CFG_XXX defines on top 473 */ 474 u32 e3_cmn_pin_cfg; /* 0x16C */ 475 #define PORT_HW_CFG_E3_TX_FAULT_MASK 0x000000FF 476 #define PORT_HW_CFG_E3_TX_FAULT_SHIFT 0 477 478 /* The output pin which reset the PHY. Use the PIN_CFG_XXX defines on 479 top */ 480 #define PORT_HW_CFG_E3_PHY_RESET_MASK 0x0000FF00 481 #define PORT_HW_CFG_E3_PHY_RESET_SHIFT 8 482 483 /* 484 * The output pin which powers down the PHY. Use the PIN_CFG_XXX 485 * defines on top 486 */ 487 #define PORT_HW_CFG_E3_PWR_DOWN_MASK 0x00FF0000 488 #define PORT_HW_CFG_E3_PWR_DOWN_SHIFT 16 489 490 /* The output pin values BSC_SEL which selects the I2C for this port 491 in the I2C Mux */ 492 #define PORT_HW_CFG_E3_I2C_MUX0_MASK 0x01000000 493 #define PORT_HW_CFG_E3_I2C_MUX1_MASK 0x02000000 494 495 496 /* 497 * The input pin I_FAULT which indicate over-current has occurred. 498 * Use the PIN_CFG_XXX defines on top 499 */ 500 u32 e3_cmn_pin_cfg1; /* 0x170 */ 501 #define PORT_HW_CFG_E3_OVER_CURRENT_MASK 0x000000FF 502 #define PORT_HW_CFG_E3_OVER_CURRENT_SHIFT 0 503 504 /* pause on host ring */ 505 u32 generic_features; /* 0x174 */ 506 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_MASK 0x00000001 507 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_SHIFT 0 508 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_DISABLED 0x00000000 509 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED 0x00000001 510 511 u32 reserved0[6]; /* 0x178 */ 512 513 u32 aeu_int_mask; /* 0x190 */ 514 515 u32 media_type; /* 0x194 */ 516 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK 0x000000FF 517 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT 0 518 519 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK 0x0000FF00 520 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT 8 521 522 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK 0x00FF0000 523 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT 16 524 525 /* 4 times 16 bits for all 4 lanes. In case external PHY is present 526 (not direct mode), those values will not take effect on the 4 XGXS 527 lanes. For some external PHYs (such as 8706 and 8726) the values 528 will be used to configure the external PHY in those cases, not 529 all 4 values are needed. */ 530 u16 xgxs_config_rx[4]; /* 0x198 */ 531 u16 xgxs_config_tx[4]; /* 0x1A0 */ 532 533 /* For storing FCOE mac on shared memory */ 534 u32 fcoe_fip_mac_upper; 535 #define PORT_HW_CFG_FCOE_UPPERMAC_MASK 0x0000ffff 536 #define PORT_HW_CFG_FCOE_UPPERMAC_SHIFT 0 537 u32 fcoe_fip_mac_lower; 538 539 u32 fcoe_wwn_port_name_upper; 540 u32 fcoe_wwn_port_name_lower; 541 542 u32 fcoe_wwn_node_name_upper; 543 u32 fcoe_wwn_node_name_lower; 544 545 u32 Reserved1[49]; /* 0x1C0 */ 546 547 /* Enable RJ45 magjack pair swapping on 10GBase-T PHY (0=default), 548 84833 only */ 549 u32 xgbt_phy_cfg; /* 0x284 */ 550 #define PORT_HW_CFG_RJ45_PAIR_SWAP_MASK 0x000000FF 551 #define PORT_HW_CFG_RJ45_PAIR_SWAP_SHIFT 0 552 553 u32 default_cfg; /* 0x288 */ 554 #define PORT_HW_CFG_GPIO0_CONFIG_MASK 0x00000003 555 #define PORT_HW_CFG_GPIO0_CONFIG_SHIFT 0 556 #define PORT_HW_CFG_GPIO0_CONFIG_NA 0x00000000 557 #define PORT_HW_CFG_GPIO0_CONFIG_LOW 0x00000001 558 #define PORT_HW_CFG_GPIO0_CONFIG_HIGH 0x00000002 559 #define PORT_HW_CFG_GPIO0_CONFIG_INPUT 0x00000003 560 561 #define PORT_HW_CFG_GPIO1_CONFIG_MASK 0x0000000C 562 #define PORT_HW_CFG_GPIO1_CONFIG_SHIFT 2 563 #define PORT_HW_CFG_GPIO1_CONFIG_NA 0x00000000 564 #define PORT_HW_CFG_GPIO1_CONFIG_LOW 0x00000004 565 #define PORT_HW_CFG_GPIO1_CONFIG_HIGH 0x00000008 566 #define PORT_HW_CFG_GPIO1_CONFIG_INPUT 0x0000000c 567 568 #define PORT_HW_CFG_GPIO2_CONFIG_MASK 0x00000030 569 #define PORT_HW_CFG_GPIO2_CONFIG_SHIFT 4 570 #define PORT_HW_CFG_GPIO2_CONFIG_NA 0x00000000 571 #define PORT_HW_CFG_GPIO2_CONFIG_LOW 0x00000010 572 #define PORT_HW_CFG_GPIO2_CONFIG_HIGH 0x00000020 573 #define PORT_HW_CFG_GPIO2_CONFIG_INPUT 0x00000030 574 575 #define PORT_HW_CFG_GPIO3_CONFIG_MASK 0x000000C0 576 #define PORT_HW_CFG_GPIO3_CONFIG_SHIFT 6 577 #define PORT_HW_CFG_GPIO3_CONFIG_NA 0x00000000 578 #define PORT_HW_CFG_GPIO3_CONFIG_LOW 0x00000040 579 #define PORT_HW_CFG_GPIO3_CONFIG_HIGH 0x00000080 580 #define PORT_HW_CFG_GPIO3_CONFIG_INPUT 0x000000c0 581 582 /* When KR link is required to be set to force which is not 583 KR-compliant, this parameter determine what is the trigger for it. 584 When GPIO is selected, low input will force the speed. Currently 585 default speed is 1G. In the future, it may be widen to select the 586 forced speed in with another parameter. Note when force-1G is 587 enabled, it override option 56: Link Speed option. */ 588 #define PORT_HW_CFG_FORCE_KR_ENABLER_MASK 0x00000F00 589 #define PORT_HW_CFG_FORCE_KR_ENABLER_SHIFT 8 590 #define PORT_HW_CFG_FORCE_KR_ENABLER_NOT_FORCED 0x00000000 591 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P0 0x00000100 592 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P0 0x00000200 593 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P0 0x00000300 594 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P0 0x00000400 595 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P1 0x00000500 596 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P1 0x00000600 597 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P1 0x00000700 598 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P1 0x00000800 599 #define PORT_HW_CFG_FORCE_KR_ENABLER_FORCED 0x00000900 600 /* Enable to determine with which GPIO to reset the external phy */ 601 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK 0x000F0000 602 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT 16 603 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_PHY_TYPE 0x00000000 604 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0 0x00010000 605 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0 0x00020000 606 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0 0x00030000 607 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0 0x00040000 608 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1 0x00050000 609 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1 0x00060000 610 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1 0x00070000 611 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1 0x00080000 612 613 /* Enable BAM on KR */ 614 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK 0x00100000 615 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT 20 616 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED 0x00000000 617 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED 0x00100000 618 619 /* Enable Common Mode Sense */ 620 #define PORT_HW_CFG_ENABLE_CMS_MASK 0x00200000 621 #define PORT_HW_CFG_ENABLE_CMS_SHIFT 21 622 #define PORT_HW_CFG_ENABLE_CMS_DISABLED 0x00000000 623 #define PORT_HW_CFG_ENABLE_CMS_ENABLED 0x00200000 624 625 /* Determine the Serdes electrical interface */ 626 #define PORT_HW_CFG_NET_SERDES_IF_MASK 0x0F000000 627 #define PORT_HW_CFG_NET_SERDES_IF_SHIFT 24 628 #define PORT_HW_CFG_NET_SERDES_IF_SGMII 0x00000000 629 #define PORT_HW_CFG_NET_SERDES_IF_XFI 0x01000000 630 #define PORT_HW_CFG_NET_SERDES_IF_SFI 0x02000000 631 #define PORT_HW_CFG_NET_SERDES_IF_KR 0x03000000 632 #define PORT_HW_CFG_NET_SERDES_IF_DXGXS 0x04000000 633 #define PORT_HW_CFG_NET_SERDES_IF_KR2 0x05000000 634 635 636 u32 speed_capability_mask2; /* 0x28C */ 637 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK 0x0000FFFF 638 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0 639 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL 0x00000001 640 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3__ 0x00000002 641 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3___ 0x00000004 642 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL 0x00000008 643 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G 0x00000010 644 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_DOT_5G 0x00000020 645 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G 0x00000040 646 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_20G 0x00000080 647 648 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK 0xFFFF0000 649 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT 16 650 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL 0x00010000 651 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0__ 0x00020000 652 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0___ 0x00040000 653 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL 0x00080000 654 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G 0x00100000 655 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_DOT_5G 0x00200000 656 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G 0x00400000 657 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G 0x00800000 658 659 660 /* In the case where two media types (e.g. copper and fiber) are 661 present and electrically active at the same time, PHY Selection 662 will determine which of the two PHYs will be designated as the 663 Active PHY and used for a connection to the network. */ 664 u32 multi_phy_config; /* 0x290 */ 665 #define PORT_HW_CFG_PHY_SELECTION_MASK 0x00000007 666 #define PORT_HW_CFG_PHY_SELECTION_SHIFT 0 667 #define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT 0x00000000 668 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY 0x00000001 669 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY 0x00000002 670 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003 671 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004 672 673 /* When enabled, all second phy nvram parameters will be swapped 674 with the first phy parameters */ 675 #define PORT_HW_CFG_PHY_SWAPPED_MASK 0x00000008 676 #define PORT_HW_CFG_PHY_SWAPPED_SHIFT 3 677 #define PORT_HW_CFG_PHY_SWAPPED_DISABLED 0x00000000 678 #define PORT_HW_CFG_PHY_SWAPPED_ENABLED 0x00000008 679 680 681 /* Address of the second external phy */ 682 u32 external_phy_config2; /* 0x294 */ 683 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK 0x000000FF 684 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT 0 685 686 /* The second XGXS external PHY type */ 687 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK 0x0000FF00 688 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT 8 689 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT 0x00000000 690 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071 0x00000100 691 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072 0x00000200 692 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073 0x00000300 693 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705 0x00000400 694 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706 0x00000500 695 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726 0x00000600 696 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481 0x00000700 697 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101 0x00000800 698 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727 0x00000900 699 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC 0x00000a00 700 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823 0x00000b00 701 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640 0x00000c00 702 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833 0x00000d00 703 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54618SE 0x00000e00 704 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8722 0x00000f00 705 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54616 0x00001000 706 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84834 0x00001100 707 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00 708 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00 709 710 711 /* 4 times 16 bits for all 4 lanes. For some external PHYs (such as 712 8706, 8726 and 8727) not all 4 values are needed. */ 713 u16 xgxs_config2_rx[4]; /* 0x296 */ 714 u16 xgxs_config2_tx[4]; /* 0x2A0 */ 715 716 u32 lane_config; 717 #define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000ffff 718 #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0 719 /* AN and forced */ 720 #define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b 721 /* forced only */ 722 #define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4 723 /* forced only */ 724 #define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8 725 /* forced only */ 726 #define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4 727 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000ff 728 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0 729 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000ff00 730 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8 731 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000c000 732 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14 733 734 /* Indicate whether to swap the external phy polarity */ 735 #define PORT_HW_CFG_SWAP_PHY_POLARITY_MASK 0x00010000 736 #define PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED 0x00000000 737 #define PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED 0x00010000 738 739 740 u32 external_phy_config; 741 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000ff 742 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0 743 744 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000ff00 745 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8 746 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000 747 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100 748 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200 749 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300 750 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400 751 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500 752 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726 0x00000600 753 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700 754 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800 755 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 0x00000900 756 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00 757 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823 0x00000b00 758 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54640 0x00000c00 759 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833 0x00000d00 760 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE 0x00000e00 761 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722 0x00000f00 762 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616 0x00001000 763 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834 0x00001100 764 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC 0x0000fc00 765 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00 766 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00 767 768 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00ff0000 769 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16 770 771 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xff000000 772 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24 773 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000 774 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000 775 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD 0x02000000 776 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000 777 778 u32 speed_capability_mask; 779 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000ffff 780 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0 781 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001 782 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002 783 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004 784 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008 785 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010 786 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020 787 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040 788 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_20G 0x00000080 789 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000 790 791 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xffff0000 792 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16 793 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000 794 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000 795 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000 796 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000 797 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000 798 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000 799 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000 800 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_20G 0x00800000 801 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000 802 803 /* A place to hold the original MAC address as a backup */ 804 u32 backup_mac_upper; /* 0x2B4 */ 805 u32 backup_mac_lower; /* 0x2B8 */ 806 807 }; 808 809 810 /**************************************************************************** 811 * Shared Feature configuration * 812 ****************************************************************************/ 813 struct shared_feat_cfg { /* NVRAM Offset */ 814 815 u32 config; /* 0x450 */ 816 #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001 817 818 /* Use NVRAM values instead of HW default values */ 819 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_MASK \ 820 0x00000002 821 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED \ 822 0x00000000 823 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED \ 824 0x00000002 825 826 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_MASK 0x00000008 827 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_SPIO 0x00000000 828 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_NVRAM 0x00000008 829 830 #define SHARED_FEAT_CFG_NCSI_ID_MASK 0x00000030 831 #define SHARED_FEAT_CFG_NCSI_ID_SHIFT 4 832 833 /* Override the OTP back to single function mode. When using GPIO, 834 high means only SF, 0 is according to CLP configuration */ 835 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK 0x00000700 836 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT 8 837 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED 0x00000000 838 #define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF 0x00000100 839 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4 0x00000200 840 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT 0x00000300 841 #define SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE 0x00000400 842 843 /* The interval in seconds between sending LLDP packets. Set to zero 844 to disable the feature */ 845 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_MASK 0x00ff0000 846 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_SHIFT 16 847 848 /* The assigned device type ID for LLDP usage */ 849 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_MASK 0xff000000 850 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_SHIFT 24 851 852 }; 853 854 855 /**************************************************************************** 856 * Port Feature configuration * 857 ****************************************************************************/ 858 struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */ 859 860 u32 config; 861 #define PORT_FEATURE_BAR1_SIZE_MASK 0x0000000f 862 #define PORT_FEATURE_BAR1_SIZE_SHIFT 0 863 #define PORT_FEATURE_BAR1_SIZE_DISABLED 0x00000000 864 #define PORT_FEATURE_BAR1_SIZE_64K 0x00000001 865 #define PORT_FEATURE_BAR1_SIZE_128K 0x00000002 866 #define PORT_FEATURE_BAR1_SIZE_256K 0x00000003 867 #define PORT_FEATURE_BAR1_SIZE_512K 0x00000004 868 #define PORT_FEATURE_BAR1_SIZE_1M 0x00000005 869 #define PORT_FEATURE_BAR1_SIZE_2M 0x00000006 870 #define PORT_FEATURE_BAR1_SIZE_4M 0x00000007 871 #define PORT_FEATURE_BAR1_SIZE_8M 0x00000008 872 #define PORT_FEATURE_BAR1_SIZE_16M 0x00000009 873 #define PORT_FEATURE_BAR1_SIZE_32M 0x0000000a 874 #define PORT_FEATURE_BAR1_SIZE_64M 0x0000000b 875 #define PORT_FEATURE_BAR1_SIZE_128M 0x0000000c 876 #define PORT_FEATURE_BAR1_SIZE_256M 0x0000000d 877 #define PORT_FEATURE_BAR1_SIZE_512M 0x0000000e 878 #define PORT_FEATURE_BAR1_SIZE_1G 0x0000000f 879 #define PORT_FEATURE_BAR2_SIZE_MASK 0x000000f0 880 #define PORT_FEATURE_BAR2_SIZE_SHIFT 4 881 #define PORT_FEATURE_BAR2_SIZE_DISABLED 0x00000000 882 #define PORT_FEATURE_BAR2_SIZE_64K 0x00000010 883 #define PORT_FEATURE_BAR2_SIZE_128K 0x00000020 884 #define PORT_FEATURE_BAR2_SIZE_256K 0x00000030 885 #define PORT_FEATURE_BAR2_SIZE_512K 0x00000040 886 #define PORT_FEATURE_BAR2_SIZE_1M 0x00000050 887 #define PORT_FEATURE_BAR2_SIZE_2M 0x00000060 888 #define PORT_FEATURE_BAR2_SIZE_4M 0x00000070 889 #define PORT_FEATURE_BAR2_SIZE_8M 0x00000080 890 #define PORT_FEATURE_BAR2_SIZE_16M 0x00000090 891 #define PORT_FEATURE_BAR2_SIZE_32M 0x000000a0 892 #define PORT_FEATURE_BAR2_SIZE_64M 0x000000b0 893 #define PORT_FEATURE_BAR2_SIZE_128M 0x000000c0 894 #define PORT_FEATURE_BAR2_SIZE_256M 0x000000d0 895 #define PORT_FEATURE_BAR2_SIZE_512M 0x000000e0 896 #define PORT_FEATURE_BAR2_SIZE_1G 0x000000f0 897 898 #define PORT_FEAT_CFG_DCBX_MASK 0x00000100 899 #define PORT_FEAT_CFG_DCBX_DISABLED 0x00000000 900 #define PORT_FEAT_CFG_DCBX_ENABLED 0x00000100 901 902 #define PORT_FEATURE_EN_SIZE_MASK 0x0f000000 903 #define PORT_FEATURE_EN_SIZE_SHIFT 24 904 #define PORT_FEATURE_WOL_ENABLED 0x01000000 905 #define PORT_FEATURE_MBA_ENABLED 0x02000000 906 #define PORT_FEATURE_MFW_ENABLED 0x04000000 907 908 /* Advertise expansion ROM even if MBA is disabled */ 909 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_MASK 0x08000000 910 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED 0x00000000 911 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED 0x08000000 912 913 /* Check the optic vendor via i2c against a list of approved modules 914 in a separate nvram image */ 915 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK 0xe0000000 916 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT 29 917 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT \ 918 0x00000000 919 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER \ 920 0x20000000 921 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG 0x40000000 922 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN 0x60000000 923 924 u32 wol_config; 925 /* Default is used when driver sets to "auto" mode */ 926 #define PORT_FEATURE_WOL_DEFAULT_MASK 0x00000003 927 #define PORT_FEATURE_WOL_DEFAULT_SHIFT 0 928 #define PORT_FEATURE_WOL_DEFAULT_DISABLE 0x00000000 929 #define PORT_FEATURE_WOL_DEFAULT_MAGIC 0x00000001 930 #define PORT_FEATURE_WOL_DEFAULT_ACPI 0x00000002 931 #define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x00000003 932 #define PORT_FEATURE_WOL_RES_PAUSE_CAP 0x00000004 933 #define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP 0x00000008 934 #define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010 935 936 u32 mba_config; 937 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000007 938 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0 939 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000 940 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001 941 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002 942 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003 943 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT 0x00000004 944 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE 0x00000007 945 946 #define PORT_FEATURE_MBA_BOOT_RETRY_MASK 0x00000038 947 #define PORT_FEATURE_MBA_BOOT_RETRY_SHIFT 3 948 949 #define PORT_FEATURE_MBA_RES_PAUSE_CAP 0x00000100 950 #define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP 0x00000200 951 #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400 952 #define PORT_FEATURE_MBA_HOTKEY_MASK 0x00000800 953 #define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000 954 #define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800 955 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000ff000 956 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12 957 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000 958 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000 959 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000 960 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000 961 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000 962 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000 963 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000 964 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000 965 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000 966 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000 967 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000 968 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000 969 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000 970 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000 971 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000 972 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000 973 #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00f00000 974 #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20 975 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000 976 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24 977 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000 978 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000 979 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000 980 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000 981 #define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c000000 982 #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26 983 #define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000 984 #define PORT_FEATURE_MBA_LINK_SPEED_10HD 0x04000000 985 #define PORT_FEATURE_MBA_LINK_SPEED_10FD 0x08000000 986 #define PORT_FEATURE_MBA_LINK_SPEED_100HD 0x0c000000 987 #define PORT_FEATURE_MBA_LINK_SPEED_100FD 0x10000000 988 #define PORT_FEATURE_MBA_LINK_SPEED_1GBPS 0x14000000 989 #define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS 0x18000000 990 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4 0x1c000000 991 #define PORT_FEATURE_MBA_LINK_SPEED_20GBPS 0x20000000 992 u32 bmc_config; 993 #define PORT_FEATURE_BMC_LINK_OVERRIDE_MASK 0x00000001 994 #define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT 0x00000000 995 #define PORT_FEATURE_BMC_LINK_OVERRIDE_EN 0x00000001 996 997 u32 mba_vlan_cfg; 998 #define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000ffff 999 #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0 1000 #define PORT_FEATURE_MBA_VLAN_EN 0x00010000 1001 1002 u32 resource_cfg; 1003 #define PORT_FEATURE_RESOURCE_CFG_VALID 0x00000001 1004 #define PORT_FEATURE_RESOURCE_CFG_DIAG 0x00000002 1005 #define PORT_FEATURE_RESOURCE_CFG_L2 0x00000004 1006 #define PORT_FEATURE_RESOURCE_CFG_ISCSI 0x00000008 1007 #define PORT_FEATURE_RESOURCE_CFG_RDMA 0x00000010 1008 1009 u32 smbus_config; 1010 #define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe 1011 #define PORT_FEATURE_SMBUS_ADDR_SHIFT 1 1012 1013 u32 vf_config; 1014 #define PORT_FEAT_CFG_VF_BAR2_SIZE_MASK 0x0000000f 1015 #define PORT_FEAT_CFG_VF_BAR2_SIZE_SHIFT 0 1016 #define PORT_FEAT_CFG_VF_BAR2_SIZE_DISABLED 0x00000000 1017 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4K 0x00000001 1018 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8K 0x00000002 1019 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16K 0x00000003 1020 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32K 0x00000004 1021 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64K 0x00000005 1022 #define PORT_FEAT_CFG_VF_BAR2_SIZE_128K 0x00000006 1023 #define PORT_FEAT_CFG_VF_BAR2_SIZE_256K 0x00000007 1024 #define PORT_FEAT_CFG_VF_BAR2_SIZE_512K 0x00000008 1025 #define PORT_FEAT_CFG_VF_BAR2_SIZE_1M 0x00000009 1026 #define PORT_FEAT_CFG_VF_BAR2_SIZE_2M 0x0000000a 1027 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4M 0x0000000b 1028 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8M 0x0000000c 1029 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16M 0x0000000d 1030 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32M 0x0000000e 1031 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64M 0x0000000f 1032 1033 u32 link_config; /* Used as HW defaults for the driver */ 1034 #define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000 1035 #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24 1036 /* (forced) low speed switch (< 10G) */ 1037 #define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000 1038 /* (forced) high speed switch (>= 10G) */ 1039 #define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000 1040 #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000 1041 #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000 1042 1043 #define PORT_FEATURE_LINK_SPEED_MASK 0x000f0000 1044 #define PORT_FEATURE_LINK_SPEED_SHIFT 16 1045 #define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000 1046 #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00010000 1047 #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00020000 1048 #define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000 1049 #define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000 1050 #define PORT_FEATURE_LINK_SPEED_1G 0x00050000 1051 #define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000 1052 #define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000 1053 #define PORT_FEATURE_LINK_SPEED_20G 0x00080000 1054 1055 #define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700 1056 #define PORT_FEATURE_FLOW_CONTROL_SHIFT 8 1057 #define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000 1058 #define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100 1059 #define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200 1060 #define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300 1061 #define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400 1062 1063 /* The default for MCP link configuration, 1064 uses the same defines as link_config */ 1065 u32 mfw_wol_link_cfg; 1066 1067 /* The default for the driver of the second external phy, 1068 uses the same defines as link_config */ 1069 u32 link_config2; /* 0x47C */ 1070 1071 /* The default for MCP of the second external phy, 1072 uses the same defines as link_config */ 1073 u32 mfw_wol_link_cfg2; /* 0x480 */ 1074 1075 1076 /* EEE power saving mode */ 1077 u32 eee_power_mode; /* 0x484 */ 1078 #define PORT_FEAT_CFG_EEE_POWER_MODE_MASK 0x000000FF 1079 #define PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT 0 1080 #define PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED 0x00000000 1081 #define PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED 0x00000001 1082 #define PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE 0x00000002 1083 #define PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY 0x00000003 1084 1085 1086 u32 Reserved2[16]; /* 0x488 */ 1087 }; 1088 1089 1090 /**************************************************************************** 1091 * Device Information * 1092 ****************************************************************************/ 1093 struct shm_dev_info { /* size */ 1094 1095 u32 bc_rev; /* 8 bits each: major, minor, build */ /* 4 */ 1096 1097 struct shared_hw_cfg shared_hw_config; /* 40 */ 1098 1099 struct port_hw_cfg port_hw_config[PORT_MAX]; /* 400*2=800 */ 1100 1101 struct shared_feat_cfg shared_feature_config; /* 4 */ 1102 1103 struct port_feat_cfg port_feature_config[PORT_MAX];/* 116*2=232 */ 1104 1105 }; 1106 1107 1108 #if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN) 1109 #error "Missing either LITTLE_ENDIAN or BIG_ENDIAN definition." 1110 #endif 1111 1112 #define FUNC_0 0 1113 #define FUNC_1 1 1114 #define FUNC_2 2 1115 #define FUNC_3 3 1116 #define FUNC_4 4 1117 #define FUNC_5 5 1118 #define FUNC_6 6 1119 #define FUNC_7 7 1120 #define E1_FUNC_MAX 2 1121 #define E1H_FUNC_MAX 8 1122 #define E2_FUNC_MAX 4 /* per path */ 1123 1124 #define VN_0 0 1125 #define VN_1 1 1126 #define VN_2 2 1127 #define VN_3 3 1128 #define E1VN_MAX 1 1129 #define E1HVN_MAX 4 1130 1131 #define E2_VF_MAX 64 /* HC_REG_VF_CONFIGURATION_SIZE */ 1132 /* This value (in milliseconds) determines the frequency of the driver 1133 * issuing the PULSE message code. The firmware monitors this periodic 1134 * pulse to determine when to switch to an OS-absent mode. */ 1135 #define DRV_PULSE_PERIOD_MS 250 1136 1137 /* This value (in milliseconds) determines how long the driver should 1138 * wait for an acknowledgement from the firmware before timing out. Once 1139 * the firmware has timed out, the driver will assume there is no firmware 1140 * running and there won't be any firmware-driver synchronization during a 1141 * driver reset. */ 1142 #define FW_ACK_TIME_OUT_MS 5000 1143 1144 #define FW_ACK_POLL_TIME_MS 1 1145 1146 #define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS) 1147 1148 #define MFW_TRACE_SIGNATURE 0x54524342 1149 1150 /**************************************************************************** 1151 * Driver <-> FW Mailbox * 1152 ****************************************************************************/ 1153 struct drv_port_mb { 1154 1155 u32 link_status; 1156 /* Driver should update this field on any link change event */ 1157 1158 #define LINK_STATUS_NONE (0<<0) 1159 #define LINK_STATUS_LINK_FLAG_MASK 0x00000001 1160 #define LINK_STATUS_LINK_UP 0x00000001 1161 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E 1162 #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1) 1163 #define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1) 1164 #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1) 1165 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1) 1166 #define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1) 1167 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1) 1168 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1) 1169 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1) 1170 #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1) 1171 #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1) 1172 #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1) 1173 #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1) 1174 #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1) 1175 #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1) 1176 #define LINK_STATUS_SPEED_AND_DUPLEX_20GTFD (11<<1) 1177 #define LINK_STATUS_SPEED_AND_DUPLEX_20GXFD (11<<1) 1178 1179 #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020 1180 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020 1181 1182 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040 1183 #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080 1184 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080 1185 1186 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200 1187 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400 1188 #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800 1189 #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000 1190 #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000 1191 #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000 1192 #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000 1193 1194 #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000 1195 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000 1196 1197 #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000 1198 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000 1199 1200 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000 1201 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18) 1202 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18) 1203 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18) 1204 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18) 1205 1206 #define LINK_STATUS_SERDES_LINK 0x00100000 1207 1208 #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000 1209 #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000 1210 #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000 1211 #define LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE 0x10000000 1212 1213 #define LINK_STATUS_PFC_ENABLED 0x20000000 1214 1215 #define LINK_STATUS_PHYSICAL_LINK_FLAG 0x40000000 1216 #define LINK_STATUS_SFP_TX_FAULT 0x80000000 1217 1218 u32 port_stx; 1219 1220 u32 stat_nig_timer; 1221 1222 /* MCP firmware does not use this field */ 1223 u32 ext_phy_fw_version; 1224 1225 }; 1226 1227 1228 struct drv_func_mb { 1229 1230 u32 drv_mb_header; 1231 #define DRV_MSG_CODE_MASK 0xffff0000 1232 #define DRV_MSG_CODE_LOAD_REQ 0x10000000 1233 #define DRV_MSG_CODE_LOAD_DONE 0x11000000 1234 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000 1235 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000 1236 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000 1237 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000 1238 #define DRV_MSG_CODE_DCC_OK 0x30000000 1239 #define DRV_MSG_CODE_DCC_FAILURE 0x31000000 1240 #define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000 1241 #define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000 1242 #define DRV_MSG_CODE_VALIDATE_KEY 0x70000000 1243 #define DRV_MSG_CODE_GET_CURR_KEY 0x80000000 1244 #define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000 1245 #define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000 1246 #define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000 1247 /* 1248 * The optic module verification command requires bootcode 1249 * v5.0.6 or later, te specific optic module verification command 1250 * requires bootcode v5.2.12 or later 1251 */ 1252 #define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL 0xa0000000 1253 #define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL 0x00050006 1254 #define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL 0xa1000000 1255 #define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL 0x00050234 1256 #define DRV_MSG_CODE_VRFY_AFEX_SUPPORTED 0xa2000000 1257 #define REQ_BC_VER_4_VRFY_AFEX_SUPPORTED 0x00070002 1258 #define REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED 0x00070014 1259 #define REQ_BC_VER_4_MT_SUPPORTED 0x00070201 1260 #define REQ_BC_VER_4_PFC_STATS_SUPPORTED 0x00070201 1261 #define REQ_BC_VER_4_FCOE_FEATURES 0x00070209 1262 1263 #define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG 0xb0000000 1264 #define DRV_MSG_CODE_DCBX_PMF_DRV_OK 0xb2000000 1265 #define REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF 0x00070401 1266 1267 #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000 1268 1269 #define DRV_MSG_CODE_AFEX_DRIVER_SETMAC 0xd0000000 1270 #define DRV_MSG_CODE_AFEX_LISTGET_ACK 0xd1000000 1271 #define DRV_MSG_CODE_AFEX_LISTSET_ACK 0xd2000000 1272 #define DRV_MSG_CODE_AFEX_STATSGET_ACK 0xd3000000 1273 #define DRV_MSG_CODE_AFEX_VIFSET_ACK 0xd4000000 1274 1275 #define DRV_MSG_CODE_DRV_INFO_ACK 0xd8000000 1276 #define DRV_MSG_CODE_DRV_INFO_NACK 0xd9000000 1277 1278 #define DRV_MSG_CODE_EEE_RESULTS_ACK 0xda000000 1279 1280 #define DRV_MSG_CODE_SET_MF_BW 0xe0000000 1281 #define REQ_BC_VER_4_SET_MF_BW 0x00060202 1282 #define DRV_MSG_CODE_SET_MF_BW_ACK 0xe1000000 1283 1284 #define DRV_MSG_CODE_LINK_STATUS_CHANGED 0x01000000 1285 1286 #define DRV_MSG_CODE_INITIATE_FLR 0x02000000 1287 #define REQ_BC_VER_4_INITIATE_FLR 0x00070213 1288 1289 #define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000 1290 #define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000 1291 #define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000 1292 #define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000 1293 1294 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff 1295 1296 u32 drv_mb_param; 1297 #define DRV_MSG_CODE_SET_MF_BW_MIN_MASK 0x00ff0000 1298 #define DRV_MSG_CODE_SET_MF_BW_MAX_MASK 0xff000000 1299 1300 #define DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET 0x00000002 1301 1302 #define DRV_MSG_CODE_LOAD_REQ_WITH_LFA 0x0000100a 1303 u32 fw_mb_header; 1304 #define FW_MSG_CODE_MASK 0xffff0000 1305 #define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000 1306 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000 1307 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000 1308 /* Load common chip is supported from bc 6.0.0 */ 1309 #define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP 0x00060000 1310 #define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 0x10130000 1311 1312 #define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000 1313 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000 1314 #define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000 1315 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000 1316 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000 1317 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000 1318 #define FW_MSG_CODE_DCC_DONE 0x30100000 1319 #define FW_MSG_CODE_LLDP_DONE 0x40100000 1320 #define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000 1321 #define FW_MSG_CODE_DIAG_REFUSE 0x50200000 1322 #define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000 1323 #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000 1324 #define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000 1325 #define FW_MSG_CODE_GET_KEY_DONE 0x80100000 1326 #define FW_MSG_CODE_NO_KEY 0x80f00000 1327 #define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000 1328 #define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000 1329 #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000 1330 #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000 1331 #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000 1332 #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000 1333 #define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS 0xa0100000 1334 #define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG 0xa0200000 1335 #define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED 0xa0300000 1336 #define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000 1337 #define FW_MSG_CODE_HW_SET_INVALID_IMAGE 0xb0100000 1338 1339 #define FW_MSG_CODE_AFEX_DRIVER_SETMAC_DONE 0xd0100000 1340 #define FW_MSG_CODE_AFEX_LISTGET_ACK 0xd1100000 1341 #define FW_MSG_CODE_AFEX_LISTSET_ACK 0xd2100000 1342 #define FW_MSG_CODE_AFEX_STATSGET_ACK 0xd3100000 1343 #define FW_MSG_CODE_AFEX_VIFSET_ACK 0xd4100000 1344 1345 #define FW_MSG_CODE_DRV_INFO_ACK 0xd8100000 1346 #define FW_MSG_CODE_DRV_INFO_NACK 0xd9100000 1347 1348 #define FW_MSG_CODE_EEE_RESULS_ACK 0xda100000 1349 1350 #define FW_MSG_CODE_SET_MF_BW_SENT 0xe0000000 1351 #define FW_MSG_CODE_SET_MF_BW_DONE 0xe1000000 1352 1353 #define FW_MSG_CODE_LINK_CHANGED_ACK 0x01100000 1354 1355 #define FW_MSG_CODE_LIC_CHALLENGE 0xff010000 1356 #define FW_MSG_CODE_LIC_RESPONSE 0xff020000 1357 #define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000 1358 #define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000 1359 1360 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff 1361 1362 u32 fw_mb_param; 1363 1364 u32 drv_pulse_mb; 1365 #define DRV_PULSE_SEQ_MASK 0x00007fff 1366 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000 1367 /* 1368 * The system time is in the format of 1369 * (year-2001)*12*32 + month*32 + day. 1370 */ 1371 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000 1372 /* 1373 * Indicate to the firmware not to go into the 1374 * OS-absent when it is not getting driver pulse. 1375 * This is used for debugging as well for PXE(MBA). 1376 */ 1377 1378 u32 mcp_pulse_mb; 1379 #define MCP_PULSE_SEQ_MASK 0x00007fff 1380 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000 1381 /* Indicates to the driver not to assert due to lack 1382 * of MCP response */ 1383 #define MCP_EVENT_MASK 0xffff0000 1384 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000 1385 1386 u32 iscsi_boot_signature; 1387 u32 iscsi_boot_block_offset; 1388 1389 u32 drv_status; 1390 #define DRV_STATUS_PMF 0x00000001 1391 #define DRV_STATUS_VF_DISABLED 0x00000002 1392 #define DRV_STATUS_SET_MF_BW 0x00000004 1393 #define DRV_STATUS_LINK_EVENT 0x00000008 1394 1395 #define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00 1396 #define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100 1397 #define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200 1398 #define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS 0x00000400 1399 #define DRV_STATUS_DCC_RESERVED1 0x00000800 1400 #define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000 1401 #define DRV_STATUS_DCC_SET_PRIORITY 0x00002000 1402 1403 #define DRV_STATUS_DCBX_EVENT_MASK 0x000f0000 1404 #define DRV_STATUS_DCBX_NEGOTIATION_RESULTS 0x00010000 1405 #define DRV_STATUS_AFEX_EVENT_MASK 0x03f00000 1406 #define DRV_STATUS_AFEX_LISTGET_REQ 0x00100000 1407 #define DRV_STATUS_AFEX_LISTSET_REQ 0x00200000 1408 #define DRV_STATUS_AFEX_STATSGET_REQ 0x00400000 1409 #define DRV_STATUS_AFEX_VIFSET_REQ 0x00800000 1410 1411 #define DRV_STATUS_DRV_INFO_REQ 0x04000000 1412 1413 #define DRV_STATUS_EEE_NEGOTIATION_RESULTS 0x08000000 1414 1415 u32 virt_mac_upper; 1416 #define VIRT_MAC_SIGN_MASK 0xffff0000 1417 #define VIRT_MAC_SIGNATURE 0x564d0000 1418 u32 virt_mac_lower; 1419 1420 }; 1421 1422 1423 /**************************************************************************** 1424 * Management firmware state * 1425 ****************************************************************************/ 1426 /* Allocate 440 bytes for management firmware */ 1427 #define MGMTFW_STATE_WORD_SIZE 110 1428 1429 struct mgmtfw_state { 1430 u32 opaque[MGMTFW_STATE_WORD_SIZE]; 1431 }; 1432 1433 1434 /**************************************************************************** 1435 * Multi-Function configuration * 1436 ****************************************************************************/ 1437 struct shared_mf_cfg { 1438 1439 u32 clp_mb; 1440 #define SHARED_MF_CLP_SET_DEFAULT 0x00000000 1441 /* set by CLP */ 1442 #define SHARED_MF_CLP_EXIT 0x00000001 1443 /* set by MCP */ 1444 #define SHARED_MF_CLP_EXIT_DONE 0x00010000 1445 1446 }; 1447 1448 struct port_mf_cfg { 1449 1450 u32 dynamic_cfg; /* device control channel */ 1451 #define PORT_MF_CFG_E1HOV_TAG_MASK 0x0000ffff 1452 #define PORT_MF_CFG_E1HOV_TAG_SHIFT 0 1453 #define PORT_MF_CFG_E1HOV_TAG_DEFAULT PORT_MF_CFG_E1HOV_TAG_MASK 1454 1455 u32 reserved[1]; 1456 1457 }; 1458 1459 struct func_mf_cfg { 1460 1461 u32 config; 1462 /* E/R/I/D */ 1463 /* function 0 of each port cannot be hidden */ 1464 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001 1465 1466 #define FUNC_MF_CFG_PROTOCOL_MASK 0x00000006 1467 #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000000 1468 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002 1469 #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004 1470 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006 1471 #define FUNC_MF_CFG_PROTOCOL_DEFAULT \ 1472 FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 1473 1474 #define FUNC_MF_CFG_FUNC_DISABLED 0x00000008 1475 #define FUNC_MF_CFG_FUNC_DELETED 0x00000010 1476 1477 /* PRI */ 1478 /* 0 - low priority, 3 - high priority */ 1479 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300 1480 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8 1481 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000 1482 1483 /* MINBW, MAXBW */ 1484 /* value range - 0..100, increments in 100Mbps */ 1485 #define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000 1486 #define FUNC_MF_CFG_MIN_BW_SHIFT 16 1487 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000 1488 #define FUNC_MF_CFG_MAX_BW_MASK 0xff000000 1489 #define FUNC_MF_CFG_MAX_BW_SHIFT 24 1490 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000 1491 1492 u32 mac_upper; /* MAC */ 1493 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff 1494 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0 1495 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK 1496 u32 mac_lower; 1497 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff 1498 1499 u32 e1hov_tag; /* VNI */ 1500 #define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff 1501 #define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0 1502 #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK 1503 1504 /* afex default VLAN ID - 12 bits */ 1505 #define FUNC_MF_CFG_AFEX_VLAN_MASK 0x0fff0000 1506 #define FUNC_MF_CFG_AFEX_VLAN_SHIFT 16 1507 1508 u32 afex_config; 1509 #define FUNC_MF_CFG_AFEX_COS_FILTER_MASK 0x000000ff 1510 #define FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT 0 1511 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK 0x0000ff00 1512 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT 8 1513 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_VAL 0x00000100 1514 #define FUNC_MF_CFG_AFEX_VLAN_MODE_MASK 0x000f0000 1515 #define FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT 16 1516 1517 u32 reserved; 1518 }; 1519 1520 enum mf_cfg_afex_vlan_mode { 1521 FUNC_MF_CFG_AFEX_VLAN_TRUNK_MODE = 0, 1522 FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE, 1523 FUNC_MF_CFG_AFEX_VLAN_TRUNK_TAG_NATIVE_MODE 1524 }; 1525 1526 /* This structure is not applicable and should not be accessed on 57711 */ 1527 struct func_ext_cfg { 1528 u32 func_cfg; 1529 #define MACP_FUNC_CFG_FLAGS_MASK 0x0000007F 1530 #define MACP_FUNC_CFG_FLAGS_SHIFT 0 1531 #define MACP_FUNC_CFG_FLAGS_ENABLED 0x00000001 1532 #define MACP_FUNC_CFG_FLAGS_ETHERNET 0x00000002 1533 #define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD 0x00000004 1534 #define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD 0x00000008 1535 #define MACP_FUNC_CFG_PAUSE_ON_HOST_RING 0x00000080 1536 1537 u32 iscsi_mac_addr_upper; 1538 u32 iscsi_mac_addr_lower; 1539 1540 u32 fcoe_mac_addr_upper; 1541 u32 fcoe_mac_addr_lower; 1542 1543 u32 fcoe_wwn_port_name_upper; 1544 u32 fcoe_wwn_port_name_lower; 1545 1546 u32 fcoe_wwn_node_name_upper; 1547 u32 fcoe_wwn_node_name_lower; 1548 1549 u32 preserve_data; 1550 #define MF_FUNC_CFG_PRESERVE_L2_MAC (1<<0) 1551 #define MF_FUNC_CFG_PRESERVE_ISCSI_MAC (1<<1) 1552 #define MF_FUNC_CFG_PRESERVE_FCOE_MAC (1<<2) 1553 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_P (1<<3) 1554 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_N (1<<4) 1555 #define MF_FUNC_CFG_PRESERVE_TX_BW (1<<5) 1556 }; 1557 1558 struct mf_cfg { 1559 1560 struct shared_mf_cfg shared_mf_config; /* 0x4 */ 1561 /* 0x8*2*2=0x20 */ 1562 struct port_mf_cfg port_mf_config[NVM_PATH_MAX][PORT_MAX]; 1563 /* for all chips, there are 8 mf functions */ 1564 struct func_mf_cfg func_mf_config[E1H_FUNC_MAX]; /* 0x18 * 8 = 0xc0 */ 1565 /* 1566 * Extended configuration per function - this array does not exist and 1567 * should not be accessed on 57711 1568 */ 1569 struct func_ext_cfg func_ext_config[E1H_FUNC_MAX]; /* 0x28 * 8 = 0x140*/ 1570 }; /* 0x224 */ 1571 1572 /**************************************************************************** 1573 * Shared Memory Region * 1574 ****************************************************************************/ 1575 struct shmem_region { /* SharedMem Offset (size) */ 1576 1577 u32 validity_map[PORT_MAX]; /* 0x0 (4*2 = 0x8) */ 1578 #define SHR_MEM_FORMAT_REV_MASK 0xff000000 1579 #define SHR_MEM_FORMAT_REV_ID ('A'<<24) 1580 /* validity bits */ 1581 #define SHR_MEM_VALIDITY_PCI_CFG 0x00100000 1582 #define SHR_MEM_VALIDITY_MB 0x00200000 1583 #define SHR_MEM_VALIDITY_DEV_INFO 0x00400000 1584 #define SHR_MEM_VALIDITY_RESERVED 0x00000007 1585 /* One licensing bit should be set */ 1586 #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038 1587 #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008 1588 #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010 1589 #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020 1590 /* Active MFW */ 1591 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000 1592 #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0 1593 #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040 1594 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080 1595 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0 1596 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0 1597 1598 struct shm_dev_info dev_info; /* 0x8 (0x438) */ 1599 1600 struct license_key drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */ 1601 1602 /* FW information (for internal FW use) */ 1603 u32 fw_info_fio_offset; /* 0x4a8 (0x4) */ 1604 struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */ 1605 1606 struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */ 1607 1608 #ifdef BMAPI 1609 /* This is a variable length array */ 1610 /* the number of function depends on the chip type */ 1611 struct drv_func_mb func_mb[1]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */ 1612 #else 1613 /* the number of function depends on the chip type */ 1614 struct drv_func_mb func_mb[]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */ 1615 #endif /* BMAPI */ 1616 1617 }; /* 57710 = 0x6dc | 57711 = 0x7E4 | 57712 = 0x734 */ 1618 1619 /**************************************************************************** 1620 * Shared Memory 2 Region * 1621 ****************************************************************************/ 1622 /* The fw_flr_ack is actually built in the following way: */ 1623 /* 8 bit: PF ack */ 1624 /* 64 bit: VF ack */ 1625 /* 8 bit: ios_dis_ack */ 1626 /* In order to maintain endianity in the mailbox hsi, we want to keep using */ 1627 /* u32. The fw must have the VF right after the PF since this is how it */ 1628 /* access arrays(it expects always the VF to reside after the PF, and that */ 1629 /* makes the calculation much easier for it. ) */ 1630 /* In order to answer both limitations, and keep the struct small, the code */ 1631 /* will abuse the structure defined here to achieve the actual partition */ 1632 /* above */ 1633 /****************************************************************************/ 1634 struct fw_flr_ack { 1635 u32 pf_ack; 1636 u32 vf_ack[1]; 1637 u32 iov_dis_ack; 1638 }; 1639 1640 struct fw_flr_mb { 1641 u32 aggint; 1642 u32 opgen_addr; 1643 struct fw_flr_ack ack; 1644 }; 1645 1646 struct eee_remote_vals { 1647 u32 tx_tw; 1648 u32 rx_tw; 1649 }; 1650 1651 /**** SUPPORT FOR SHMEM ARRRAYS *** 1652 * The SHMEM HSI is aligned on 32 bit boundaries which makes it difficult to 1653 * define arrays with storage types smaller then unsigned dwords. 1654 * The macros below add generic support for SHMEM arrays with numeric elements 1655 * that can span 2,4,8 or 16 bits. The array underlying type is a 32 bit dword 1656 * array with individual bit-filed elements accessed using shifts and masks. 1657 * 1658 */ 1659 1660 /* eb is the bitwidth of a single element */ 1661 #define SHMEM_ARRAY_MASK(eb) ((1<<(eb))-1) 1662 #define SHMEM_ARRAY_ENTRY(i, eb) ((i)/(32/(eb))) 1663 1664 /* the bit-position macro allows the used to flip the order of the arrays 1665 * elements on a per byte or word boundary. 1666 * 1667 * example: an array with 8 entries each 4 bit wide. This array will fit into 1668 * a single dword. The diagrmas below show the array order of the nibbles. 1669 * 1670 * SHMEM_ARRAY_BITPOS(i, 4, 4) defines the stadard ordering: 1671 * 1672 * | | | | 1673 * 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 1674 * | | | | 1675 * 1676 * SHMEM_ARRAY_BITPOS(i, 4, 8) defines a flip ordering per byte: 1677 * 1678 * | | | | 1679 * 1 | 0 | 3 | 2 | 5 | 4 | 7 | 6 | 1680 * | | | | 1681 * 1682 * SHMEM_ARRAY_BITPOS(i, 4, 16) defines a flip ordering per word: 1683 * 1684 * | | | | 1685 * 3 | 2 | 1 | 0 | 7 | 6 | 5 | 4 | 1686 * | | | | 1687 */ 1688 #define SHMEM_ARRAY_BITPOS(i, eb, fb) \ 1689 ((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \ 1690 (((i)%((fb)/(eb))) * (eb))) 1691 1692 #define SHMEM_ARRAY_GET(a, i, eb, fb) \ 1693 ((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) & \ 1694 SHMEM_ARRAY_MASK(eb)) 1695 1696 #define SHMEM_ARRAY_SET(a, i, eb, fb, val) \ 1697 do { \ 1698 a[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) << \ 1699 SHMEM_ARRAY_BITPOS(i, eb, fb)); \ 1700 a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) << \ 1701 SHMEM_ARRAY_BITPOS(i, eb, fb)); \ 1702 } while (0) 1703 1704 1705 /****START OF DCBX STRUCTURES DECLARATIONS****/ 1706 #define DCBX_MAX_NUM_PRI_PG_ENTRIES 8 1707 #define DCBX_PRI_PG_BITWIDTH 4 1708 #define DCBX_PRI_PG_FBITS 8 1709 #define DCBX_PRI_PG_GET(a, i) \ 1710 SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS) 1711 #define DCBX_PRI_PG_SET(a, i, val) \ 1712 SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val) 1713 #define DCBX_MAX_NUM_PG_BW_ENTRIES 8 1714 #define DCBX_BW_PG_BITWIDTH 8 1715 #define DCBX_PG_BW_GET(a, i) \ 1716 SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH) 1717 #define DCBX_PG_BW_SET(a, i, val) \ 1718 SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val) 1719 #define DCBX_STRICT_PRI_PG 15 1720 #define DCBX_MAX_APP_PROTOCOL 16 1721 #define FCOE_APP_IDX 0 1722 #define ISCSI_APP_IDX 1 1723 #define PREDEFINED_APP_IDX_MAX 2 1724 1725 1726 /* Big/Little endian have the same representation. */ 1727 struct dcbx_ets_feature { 1728 /* 1729 * For Admin MIB - is this feature supported by the 1730 * driver | For Local MIB - should this feature be enabled. 1731 */ 1732 u32 enabled; 1733 u32 pg_bw_tbl[2]; 1734 u32 pri_pg_tbl[1]; 1735 }; 1736 1737 /* Driver structure in LE */ 1738 struct dcbx_pfc_feature { 1739 #ifdef __BIG_ENDIAN 1740 u8 pri_en_bitmap; 1741 #define DCBX_PFC_PRI_0 0x01 1742 #define DCBX_PFC_PRI_1 0x02 1743 #define DCBX_PFC_PRI_2 0x04 1744 #define DCBX_PFC_PRI_3 0x08 1745 #define DCBX_PFC_PRI_4 0x10 1746 #define DCBX_PFC_PRI_5 0x20 1747 #define DCBX_PFC_PRI_6 0x40 1748 #define DCBX_PFC_PRI_7 0x80 1749 u8 pfc_caps; 1750 u8 reserved; 1751 u8 enabled; 1752 #elif defined(__LITTLE_ENDIAN) 1753 u8 enabled; 1754 u8 reserved; 1755 u8 pfc_caps; 1756 u8 pri_en_bitmap; 1757 #define DCBX_PFC_PRI_0 0x01 1758 #define DCBX_PFC_PRI_1 0x02 1759 #define DCBX_PFC_PRI_2 0x04 1760 #define DCBX_PFC_PRI_3 0x08 1761 #define DCBX_PFC_PRI_4 0x10 1762 #define DCBX_PFC_PRI_5 0x20 1763 #define DCBX_PFC_PRI_6 0x40 1764 #define DCBX_PFC_PRI_7 0x80 1765 #endif 1766 }; 1767 1768 struct dcbx_app_priority_entry { 1769 #ifdef __BIG_ENDIAN 1770 u16 app_id; 1771 u8 pri_bitmap; 1772 u8 appBitfield; 1773 #define DCBX_APP_ENTRY_VALID 0x01 1774 #define DCBX_APP_ENTRY_SF_MASK 0x30 1775 #define DCBX_APP_ENTRY_SF_SHIFT 4 1776 #define DCBX_APP_SF_ETH_TYPE 0x10 1777 #define DCBX_APP_SF_PORT 0x20 1778 #elif defined(__LITTLE_ENDIAN) 1779 u8 appBitfield; 1780 #define DCBX_APP_ENTRY_VALID 0x01 1781 #define DCBX_APP_ENTRY_SF_MASK 0x30 1782 #define DCBX_APP_ENTRY_SF_SHIFT 4 1783 #define DCBX_APP_SF_ETH_TYPE 0x10 1784 #define DCBX_APP_SF_PORT 0x20 1785 u8 pri_bitmap; 1786 u16 app_id; 1787 #endif 1788 }; 1789 1790 1791 /* FW structure in BE */ 1792 struct dcbx_app_priority_feature { 1793 #ifdef __BIG_ENDIAN 1794 u8 reserved; 1795 u8 default_pri; 1796 u8 tc_supported; 1797 u8 enabled; 1798 #elif defined(__LITTLE_ENDIAN) 1799 u8 enabled; 1800 u8 tc_supported; 1801 u8 default_pri; 1802 u8 reserved; 1803 #endif 1804 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL]; 1805 }; 1806 1807 /* FW structure in BE */ 1808 struct dcbx_features { 1809 /* PG feature */ 1810 struct dcbx_ets_feature ets; 1811 /* PFC feature */ 1812 struct dcbx_pfc_feature pfc; 1813 /* APP feature */ 1814 struct dcbx_app_priority_feature app; 1815 }; 1816 1817 /* LLDP protocol parameters */ 1818 /* FW structure in BE */ 1819 struct lldp_params { 1820 #ifdef __BIG_ENDIAN 1821 u8 msg_fast_tx_interval; 1822 u8 msg_tx_hold; 1823 u8 msg_tx_interval; 1824 u8 admin_status; 1825 #define LLDP_TX_ONLY 0x01 1826 #define LLDP_RX_ONLY 0x02 1827 #define LLDP_TX_RX 0x03 1828 #define LLDP_DISABLED 0x04 1829 u8 reserved1; 1830 u8 tx_fast; 1831 u8 tx_crd_max; 1832 u8 tx_crd; 1833 #elif defined(__LITTLE_ENDIAN) 1834 u8 admin_status; 1835 #define LLDP_TX_ONLY 0x01 1836 #define LLDP_RX_ONLY 0x02 1837 #define LLDP_TX_RX 0x03 1838 #define LLDP_DISABLED 0x04 1839 u8 msg_tx_interval; 1840 u8 msg_tx_hold; 1841 u8 msg_fast_tx_interval; 1842 u8 tx_crd; 1843 u8 tx_crd_max; 1844 u8 tx_fast; 1845 u8 reserved1; 1846 #endif 1847 #define REM_CHASSIS_ID_STAT_LEN 4 1848 #define REM_PORT_ID_STAT_LEN 4 1849 /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */ 1850 u32 peer_chassis_id[REM_CHASSIS_ID_STAT_LEN]; 1851 /* Holds remote Port ID TLV header, subtype and 9B of payload. */ 1852 u32 peer_port_id[REM_PORT_ID_STAT_LEN]; 1853 }; 1854 1855 struct lldp_dcbx_stat { 1856 #define LOCAL_CHASSIS_ID_STAT_LEN 2 1857 #define LOCAL_PORT_ID_STAT_LEN 2 1858 /* Holds local Chassis ID 8B payload of constant subtype 4. */ 1859 u32 local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN]; 1860 /* Holds local Port ID 8B payload of constant subtype 3. */ 1861 u32 local_port_id[LOCAL_PORT_ID_STAT_LEN]; 1862 /* Number of DCBX frames transmitted. */ 1863 u32 num_tx_dcbx_pkts; 1864 /* Number of DCBX frames received. */ 1865 u32 num_rx_dcbx_pkts; 1866 }; 1867 1868 /* ADMIN MIB - DCBX local machine default configuration. */ 1869 struct lldp_admin_mib { 1870 u32 ver_cfg_flags; 1871 #define DCBX_ETS_CONFIG_TX_ENABLED 0x00000001 1872 #define DCBX_PFC_CONFIG_TX_ENABLED 0x00000002 1873 #define DCBX_APP_CONFIG_TX_ENABLED 0x00000004 1874 #define DCBX_ETS_RECO_TX_ENABLED 0x00000008 1875 #define DCBX_ETS_RECO_VALID 0x00000010 1876 #define DCBX_ETS_WILLING 0x00000020 1877 #define DCBX_PFC_WILLING 0x00000040 1878 #define DCBX_APP_WILLING 0x00000080 1879 #define DCBX_VERSION_CEE 0x00000100 1880 #define DCBX_VERSION_IEEE 0x00000200 1881 #define DCBX_DCBX_ENABLED 0x00000400 1882 #define DCBX_CEE_VERSION_MASK 0x0000f000 1883 #define DCBX_CEE_VERSION_SHIFT 12 1884 #define DCBX_CEE_MAX_VERSION_MASK 0x000f0000 1885 #define DCBX_CEE_MAX_VERSION_SHIFT 16 1886 struct dcbx_features features; 1887 }; 1888 1889 /* REMOTE MIB - remote machine DCBX configuration. */ 1890 struct lldp_remote_mib { 1891 u32 prefix_seq_num; 1892 u32 flags; 1893 #define DCBX_ETS_TLV_RX 0x00000001 1894 #define DCBX_PFC_TLV_RX 0x00000002 1895 #define DCBX_APP_TLV_RX 0x00000004 1896 #define DCBX_ETS_RX_ERROR 0x00000010 1897 #define DCBX_PFC_RX_ERROR 0x00000020 1898 #define DCBX_APP_RX_ERROR 0x00000040 1899 #define DCBX_ETS_REM_WILLING 0x00000100 1900 #define DCBX_PFC_REM_WILLING 0x00000200 1901 #define DCBX_APP_REM_WILLING 0x00000400 1902 #define DCBX_REMOTE_ETS_RECO_VALID 0x00001000 1903 #define DCBX_REMOTE_MIB_VALID 0x00002000 1904 struct dcbx_features features; 1905 u32 suffix_seq_num; 1906 }; 1907 1908 /* LOCAL MIB - operational DCBX configuration - transmitted on Tx LLDPDU. */ 1909 struct lldp_local_mib { 1910 u32 prefix_seq_num; 1911 /* Indicates if there is mismatch with negotiation results. */ 1912 u32 error; 1913 #define DCBX_LOCAL_ETS_ERROR 0x00000001 1914 #define DCBX_LOCAL_PFC_ERROR 0x00000002 1915 #define DCBX_LOCAL_APP_ERROR 0x00000004 1916 #define DCBX_LOCAL_PFC_MISMATCH 0x00000010 1917 #define DCBX_LOCAL_APP_MISMATCH 0x00000020 1918 #define DCBX_REMOTE_MIB_ERROR 0x00000040 1919 #define DCBX_REMOTE_ETS_TLV_NOT_FOUND 0x00000080 1920 #define DCBX_REMOTE_PFC_TLV_NOT_FOUND 0x00000100 1921 #define DCBX_REMOTE_APP_TLV_NOT_FOUND 0x00000200 1922 struct dcbx_features features; 1923 u32 suffix_seq_num; 1924 }; 1925 /***END OF DCBX STRUCTURES DECLARATIONS***/ 1926 1927 /***********************************************************/ 1928 /* Elink section */ 1929 /***********************************************************/ 1930 #define SHMEM_LINK_CONFIG_SIZE 2 1931 struct shmem_lfa { 1932 u32 req_duplex; 1933 #define REQ_DUPLEX_PHY0_MASK 0x0000ffff 1934 #define REQ_DUPLEX_PHY0_SHIFT 0 1935 #define REQ_DUPLEX_PHY1_MASK 0xffff0000 1936 #define REQ_DUPLEX_PHY1_SHIFT 16 1937 u32 req_flow_ctrl; 1938 #define REQ_FLOW_CTRL_PHY0_MASK 0x0000ffff 1939 #define REQ_FLOW_CTRL_PHY0_SHIFT 0 1940 #define REQ_FLOW_CTRL_PHY1_MASK 0xffff0000 1941 #define REQ_FLOW_CTRL_PHY1_SHIFT 16 1942 u32 req_line_speed; /* Also determine AutoNeg */ 1943 #define REQ_LINE_SPD_PHY0_MASK 0x0000ffff 1944 #define REQ_LINE_SPD_PHY0_SHIFT 0 1945 #define REQ_LINE_SPD_PHY1_MASK 0xffff0000 1946 #define REQ_LINE_SPD_PHY1_SHIFT 16 1947 u32 speed_cap_mask[SHMEM_LINK_CONFIG_SIZE]; 1948 u32 additional_config; 1949 #define REQ_FC_AUTO_ADV_MASK 0x0000ffff 1950 #define REQ_FC_AUTO_ADV0_SHIFT 0 1951 #define NO_LFA_DUE_TO_DCC_MASK 0x00010000 1952 u32 lfa_sts; 1953 #define LFA_LINK_FLAP_REASON_OFFSET 0 1954 #define LFA_LINK_FLAP_REASON_MASK 0x000000ff 1955 #define LFA_LINK_DOWN 0x1 1956 #define LFA_LOOPBACK_ENABLED 0x2 1957 #define LFA_DUPLEX_MISMATCH 0x3 1958 #define LFA_MFW_IS_TOO_OLD 0x4 1959 #define LFA_LINK_SPEED_MISMATCH 0x5 1960 #define LFA_FLOW_CTRL_MISMATCH 0x6 1961 #define LFA_SPEED_CAP_MISMATCH 0x7 1962 #define LFA_DCC_LFA_DISABLED 0x8 1963 #define LFA_EEE_MISMATCH 0x9 1964 1965 #define LINK_FLAP_AVOIDANCE_COUNT_OFFSET 8 1966 #define LINK_FLAP_AVOIDANCE_COUNT_MASK 0x0000ff00 1967 1968 #define LINK_FLAP_COUNT_OFFSET 16 1969 #define LINK_FLAP_COUNT_MASK 0x00ff0000 1970 1971 #define LFA_FLAGS_MASK 0xff000000 1972 #define SHMEM_LFA_DONT_CLEAR_STAT (1<<24) 1973 }; 1974 1975 struct ncsi_oem_fcoe_features { 1976 u32 fcoe_features1; 1977 #define FCOE_FEATURES1_IOS_PER_CONNECTION_MASK 0x0000FFFF 1978 #define FCOE_FEATURES1_IOS_PER_CONNECTION_OFFSET 0 1979 1980 #define FCOE_FEATURES1_LOGINS_PER_PORT_MASK 0xFFFF0000 1981 #define FCOE_FEATURES1_LOGINS_PER_PORT_OFFSET 16 1982 1983 u32 fcoe_features2; 1984 #define FCOE_FEATURES2_EXCHANGES_MASK 0x0000FFFF 1985 #define FCOE_FEATURES2_EXCHANGES_OFFSET 0 1986 1987 #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_MASK 0xFFFF0000 1988 #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_OFFSET 16 1989 1990 u32 fcoe_features3; 1991 #define FCOE_FEATURES3_TARGETS_SUPPORTED_MASK 0x0000FFFF 1992 #define FCOE_FEATURES3_TARGETS_SUPPORTED_OFFSET 0 1993 1994 #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_MASK 0xFFFF0000 1995 #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_OFFSET 16 1996 1997 u32 fcoe_features4; 1998 #define FCOE_FEATURES4_FEATURE_SETTINGS_MASK 0x0000000F 1999 #define FCOE_FEATURES4_FEATURE_SETTINGS_OFFSET 0 2000 }; 2001 2002 struct ncsi_oem_data { 2003 u32 driver_version[4]; 2004 struct ncsi_oem_fcoe_features ncsi_oem_fcoe_features; 2005 }; 2006 2007 struct shmem2_region { 2008 2009 u32 size; /* 0x0000 */ 2010 2011 u32 dcc_support; /* 0x0004 */ 2012 #define SHMEM_DCC_SUPPORT_NONE 0x00000000 2013 #define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV 0x00000001 2014 #define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV 0x00000004 2015 #define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV 0x00000008 2016 #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040 2017 #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080 2018 2019 u32 ext_phy_fw_version2[PORT_MAX]; /* 0x0008 */ 2020 /* 2021 * For backwards compatibility, if the mf_cfg_addr does not exist 2022 * (the size filed is smaller than 0xc) the mf_cfg resides at the 2023 * end of struct shmem_region 2024 */ 2025 u32 mf_cfg_addr; /* 0x0010 */ 2026 #define SHMEM_MF_CFG_ADDR_NONE 0x00000000 2027 2028 struct fw_flr_mb flr_mb; /* 0x0014 */ 2029 u32 dcbx_lldp_params_offset; /* 0x0028 */ 2030 #define SHMEM_LLDP_DCBX_PARAMS_NONE 0x00000000 2031 u32 dcbx_neg_res_offset; /* 0x002c */ 2032 #define SHMEM_DCBX_NEG_RES_NONE 0x00000000 2033 u32 dcbx_remote_mib_offset; /* 0x0030 */ 2034 #define SHMEM_DCBX_REMOTE_MIB_NONE 0x00000000 2035 /* 2036 * The other shmemX_base_addr holds the other path's shmem address 2037 * required for example in case of common phy init, or for path1 to know 2038 * the address of mcp debug trace which is located in offset from shmem 2039 * of path0 2040 */ 2041 u32 other_shmem_base_addr; /* 0x0034 */ 2042 u32 other_shmem2_base_addr; /* 0x0038 */ 2043 /* 2044 * mcp_vf_disabled is set by the MCP to indicate the driver about VFs 2045 * which were disabled/flred 2046 */ 2047 u32 mcp_vf_disabled[E2_VF_MAX / 32]; /* 0x003c */ 2048 2049 /* 2050 * drv_ack_vf_disabled is set by the PF driver to ack handled disabled 2051 * VFs 2052 */ 2053 u32 drv_ack_vf_disabled[E2_FUNC_MAX][E2_VF_MAX / 32]; /* 0x0044 */ 2054 2055 u32 dcbx_lldp_dcbx_stat_offset; /* 0x0064 */ 2056 #define SHMEM_LLDP_DCBX_STAT_NONE 0x00000000 2057 2058 /* 2059 * edebug_driver_if field is used to transfer messages between edebug 2060 * app to the driver through shmem2. 2061 * 2062 * message format: 2063 * bits 0-2 - function number / instance of driver to perform request 2064 * bits 3-5 - op code / is_ack? 2065 * bits 6-63 - data 2066 */ 2067 u32 edebug_driver_if[2]; /* 0x0068 */ 2068 #define EDEBUG_DRIVER_IF_OP_CODE_GET_PHYS_ADDR 1 2069 #define EDEBUG_DRIVER_IF_OP_CODE_GET_BUS_ADDR 2 2070 #define EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT 3 2071 2072 u32 nvm_retain_bitmap_addr; /* 0x0070 */ 2073 2074 /* afex support of that driver */ 2075 u32 afex_driver_support; /* 0x0074 */ 2076 #define SHMEM_AFEX_VERSION_MASK 0x100f 2077 #define SHMEM_AFEX_SUPPORTED_VERSION_ONE 0x1001 2078 #define SHMEM_AFEX_REDUCED_DRV_LOADED 0x8000 2079 2080 /* driver receives addr in scratchpad to which it should respond */ 2081 u32 afex_scratchpad_addr_to_write[E2_FUNC_MAX]; 2082 2083 /* generic params from MCP to driver (value depends on the msg sent 2084 * to driver 2085 */ 2086 u32 afex_param1_to_driver[E2_FUNC_MAX]; /* 0x0088 */ 2087 u32 afex_param2_to_driver[E2_FUNC_MAX]; /* 0x0098 */ 2088 2089 u32 swim_base_addr; /* 0x0108 */ 2090 u32 swim_funcs; 2091 u32 swim_main_cb; 2092 2093 /* bitmap notifying which VIF profiles stored in nvram are enabled by 2094 * switch 2095 */ 2096 u32 afex_profiles_enabled[2]; 2097 2098 /* generic flags controlled by the driver */ 2099 u32 drv_flags; 2100 #define DRV_FLAGS_DCB_CONFIGURED 0x0 2101 #define DRV_FLAGS_DCB_CONFIGURATION_ABORTED 0x1 2102 #define DRV_FLAGS_DCB_MFW_CONFIGURED 0x2 2103 2104 #define DRV_FLAGS_PORT_MASK ((1 << DRV_FLAGS_DCB_CONFIGURED) | \ 2105 (1 << DRV_FLAGS_DCB_CONFIGURATION_ABORTED) | \ 2106 (1 << DRV_FLAGS_DCB_MFW_CONFIGURED)) 2107 /* pointer to extended dev_info shared data copied from nvm image */ 2108 u32 extended_dev_info_shared_addr; 2109 u32 ncsi_oem_data_addr; 2110 2111 u32 ocsd_host_addr; /* initialized by option ROM */ 2112 u32 ocbb_host_addr; /* initialized by option ROM */ 2113 u32 ocsd_req_update_interval; /* initialized by option ROM */ 2114 u32 temperature_in_half_celsius; 2115 u32 glob_struct_in_host; 2116 2117 u32 dcbx_neg_res_ext_offset; 2118 #define SHMEM_DCBX_NEG_RES_EXT_NONE 0x00000000 2119 2120 u32 drv_capabilities_flag[E2_FUNC_MAX]; 2121 #define DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED 0x00000001 2122 #define DRV_FLAGS_CAPABILITIES_LOADED_L2 0x00000002 2123 #define DRV_FLAGS_CAPABILITIES_LOADED_FCOE 0x00000004 2124 #define DRV_FLAGS_CAPABILITIES_LOADED_ISCSI 0x00000008 2125 2126 u32 extended_dev_info_shared_cfg_size; 2127 2128 u32 dcbx_en[PORT_MAX]; 2129 2130 /* The offset points to the multi threaded meta structure */ 2131 u32 multi_thread_data_offset; 2132 2133 /* address of DMAable host address holding values from the drivers */ 2134 u32 drv_info_host_addr_lo; 2135 u32 drv_info_host_addr_hi; 2136 2137 /* general values written by the MFW (such as current version) */ 2138 u32 drv_info_control; 2139 #define DRV_INFO_CONTROL_VER_MASK 0x000000ff 2140 #define DRV_INFO_CONTROL_VER_SHIFT 0 2141 #define DRV_INFO_CONTROL_OP_CODE_MASK 0x0000ff00 2142 #define DRV_INFO_CONTROL_OP_CODE_SHIFT 8 2143 u32 ibft_host_addr; /* initialized by option ROM */ 2144 struct eee_remote_vals eee_remote_vals[PORT_MAX]; 2145 u32 reserved[E2_FUNC_MAX]; 2146 2147 2148 /* the status of EEE auto-negotiation 2149 * bits 15:0 the configured tx-lpi entry timer value. Depends on bit 31. 2150 * bits 19:16 the supported modes for EEE. 2151 * bits 23:20 the speeds advertised for EEE. 2152 * bits 27:24 the speeds the Link partner advertised for EEE. 2153 * The supported/adv. modes in bits 27:19 originate from the 2154 * SHMEM_EEE_XXX_ADV definitions (where XXX is replaced by speed). 2155 * bit 28 when 1'b1 EEE was requested. 2156 * bit 29 when 1'b1 tx lpi was requested. 2157 * bit 30 when 1'b1 EEE was negotiated. Tx lpi will be asserted iff 2158 * 30:29 are 2'b11. 2159 * bit 31 when 1'b0 bits 15:0 contain a PORT_FEAT_CFG_EEE_ define as 2160 * value. When 1'b1 those bits contains a value times 16 microseconds. 2161 */ 2162 u32 eee_status[PORT_MAX]; 2163 #define SHMEM_EEE_TIMER_MASK 0x0000ffff 2164 #define SHMEM_EEE_SUPPORTED_MASK 0x000f0000 2165 #define SHMEM_EEE_SUPPORTED_SHIFT 16 2166 #define SHMEM_EEE_ADV_STATUS_MASK 0x00f00000 2167 #define SHMEM_EEE_100M_ADV (1<<0) 2168 #define SHMEM_EEE_1G_ADV (1<<1) 2169 #define SHMEM_EEE_10G_ADV (1<<2) 2170 #define SHMEM_EEE_ADV_STATUS_SHIFT 20 2171 #define SHMEM_EEE_LP_ADV_STATUS_MASK 0x0f000000 2172 #define SHMEM_EEE_LP_ADV_STATUS_SHIFT 24 2173 #define SHMEM_EEE_REQUESTED_BIT 0x10000000 2174 #define SHMEM_EEE_LPI_REQUESTED_BIT 0x20000000 2175 #define SHMEM_EEE_ACTIVE_BIT 0x40000000 2176 #define SHMEM_EEE_TIME_OUTPUT_BIT 0x80000000 2177 2178 u32 sizeof_port_stats; 2179 2180 /* Link Flap Avoidance */ 2181 u32 lfa_host_addr[PORT_MAX]; 2182 u32 reserved1; 2183 2184 u32 reserved2; /* Offset 0x148 */ 2185 u32 reserved3; /* Offset 0x14C */ 2186 u32 reserved4; /* Offset 0x150 */ 2187 u32 link_attr_sync[PORT_MAX]; /* Offset 0x154 */ 2188 #define LINK_ATTR_SYNC_KR2_ENABLE (1<<0) 2189 }; 2190 2191 2192 struct emac_stats { 2193 u32 rx_stat_ifhcinoctets; 2194 u32 rx_stat_ifhcinbadoctets; 2195 u32 rx_stat_etherstatsfragments; 2196 u32 rx_stat_ifhcinucastpkts; 2197 u32 rx_stat_ifhcinmulticastpkts; 2198 u32 rx_stat_ifhcinbroadcastpkts; 2199 u32 rx_stat_dot3statsfcserrors; 2200 u32 rx_stat_dot3statsalignmenterrors; 2201 u32 rx_stat_dot3statscarriersenseerrors; 2202 u32 rx_stat_xonpauseframesreceived; 2203 u32 rx_stat_xoffpauseframesreceived; 2204 u32 rx_stat_maccontrolframesreceived; 2205 u32 rx_stat_xoffstateentered; 2206 u32 rx_stat_dot3statsframestoolong; 2207 u32 rx_stat_etherstatsjabbers; 2208 u32 rx_stat_etherstatsundersizepkts; 2209 u32 rx_stat_etherstatspkts64octets; 2210 u32 rx_stat_etherstatspkts65octetsto127octets; 2211 u32 rx_stat_etherstatspkts128octetsto255octets; 2212 u32 rx_stat_etherstatspkts256octetsto511octets; 2213 u32 rx_stat_etherstatspkts512octetsto1023octets; 2214 u32 rx_stat_etherstatspkts1024octetsto1522octets; 2215 u32 rx_stat_etherstatspktsover1522octets; 2216 2217 u32 rx_stat_falsecarriererrors; 2218 2219 u32 tx_stat_ifhcoutoctets; 2220 u32 tx_stat_ifhcoutbadoctets; 2221 u32 tx_stat_etherstatscollisions; 2222 u32 tx_stat_outxonsent; 2223 u32 tx_stat_outxoffsent; 2224 u32 tx_stat_flowcontroldone; 2225 u32 tx_stat_dot3statssinglecollisionframes; 2226 u32 tx_stat_dot3statsmultiplecollisionframes; 2227 u32 tx_stat_dot3statsdeferredtransmissions; 2228 u32 tx_stat_dot3statsexcessivecollisions; 2229 u32 tx_stat_dot3statslatecollisions; 2230 u32 tx_stat_ifhcoutucastpkts; 2231 u32 tx_stat_ifhcoutmulticastpkts; 2232 u32 tx_stat_ifhcoutbroadcastpkts; 2233 u32 tx_stat_etherstatspkts64octets; 2234 u32 tx_stat_etherstatspkts65octetsto127octets; 2235 u32 tx_stat_etherstatspkts128octetsto255octets; 2236 u32 tx_stat_etherstatspkts256octetsto511octets; 2237 u32 tx_stat_etherstatspkts512octetsto1023octets; 2238 u32 tx_stat_etherstatspkts1024octetsto1522octets; 2239 u32 tx_stat_etherstatspktsover1522octets; 2240 u32 tx_stat_dot3statsinternalmactransmiterrors; 2241 }; 2242 2243 2244 struct bmac1_stats { 2245 u32 tx_stat_gtpkt_lo; 2246 u32 tx_stat_gtpkt_hi; 2247 u32 tx_stat_gtxpf_lo; 2248 u32 tx_stat_gtxpf_hi; 2249 u32 tx_stat_gtfcs_lo; 2250 u32 tx_stat_gtfcs_hi; 2251 u32 tx_stat_gtmca_lo; 2252 u32 tx_stat_gtmca_hi; 2253 u32 tx_stat_gtbca_lo; 2254 u32 tx_stat_gtbca_hi; 2255 u32 tx_stat_gtfrg_lo; 2256 u32 tx_stat_gtfrg_hi; 2257 u32 tx_stat_gtovr_lo; 2258 u32 tx_stat_gtovr_hi; 2259 u32 tx_stat_gt64_lo; 2260 u32 tx_stat_gt64_hi; 2261 u32 tx_stat_gt127_lo; 2262 u32 tx_stat_gt127_hi; 2263 u32 tx_stat_gt255_lo; 2264 u32 tx_stat_gt255_hi; 2265 u32 tx_stat_gt511_lo; 2266 u32 tx_stat_gt511_hi; 2267 u32 tx_stat_gt1023_lo; 2268 u32 tx_stat_gt1023_hi; 2269 u32 tx_stat_gt1518_lo; 2270 u32 tx_stat_gt1518_hi; 2271 u32 tx_stat_gt2047_lo; 2272 u32 tx_stat_gt2047_hi; 2273 u32 tx_stat_gt4095_lo; 2274 u32 tx_stat_gt4095_hi; 2275 u32 tx_stat_gt9216_lo; 2276 u32 tx_stat_gt9216_hi; 2277 u32 tx_stat_gt16383_lo; 2278 u32 tx_stat_gt16383_hi; 2279 u32 tx_stat_gtmax_lo; 2280 u32 tx_stat_gtmax_hi; 2281 u32 tx_stat_gtufl_lo; 2282 u32 tx_stat_gtufl_hi; 2283 u32 tx_stat_gterr_lo; 2284 u32 tx_stat_gterr_hi; 2285 u32 tx_stat_gtbyt_lo; 2286 u32 tx_stat_gtbyt_hi; 2287 2288 u32 rx_stat_gr64_lo; 2289 u32 rx_stat_gr64_hi; 2290 u32 rx_stat_gr127_lo; 2291 u32 rx_stat_gr127_hi; 2292 u32 rx_stat_gr255_lo; 2293 u32 rx_stat_gr255_hi; 2294 u32 rx_stat_gr511_lo; 2295 u32 rx_stat_gr511_hi; 2296 u32 rx_stat_gr1023_lo; 2297 u32 rx_stat_gr1023_hi; 2298 u32 rx_stat_gr1518_lo; 2299 u32 rx_stat_gr1518_hi; 2300 u32 rx_stat_gr2047_lo; 2301 u32 rx_stat_gr2047_hi; 2302 u32 rx_stat_gr4095_lo; 2303 u32 rx_stat_gr4095_hi; 2304 u32 rx_stat_gr9216_lo; 2305 u32 rx_stat_gr9216_hi; 2306 u32 rx_stat_gr16383_lo; 2307 u32 rx_stat_gr16383_hi; 2308 u32 rx_stat_grmax_lo; 2309 u32 rx_stat_grmax_hi; 2310 u32 rx_stat_grpkt_lo; 2311 u32 rx_stat_grpkt_hi; 2312 u32 rx_stat_grfcs_lo; 2313 u32 rx_stat_grfcs_hi; 2314 u32 rx_stat_grmca_lo; 2315 u32 rx_stat_grmca_hi; 2316 u32 rx_stat_grbca_lo; 2317 u32 rx_stat_grbca_hi; 2318 u32 rx_stat_grxcf_lo; 2319 u32 rx_stat_grxcf_hi; 2320 u32 rx_stat_grxpf_lo; 2321 u32 rx_stat_grxpf_hi; 2322 u32 rx_stat_grxuo_lo; 2323 u32 rx_stat_grxuo_hi; 2324 u32 rx_stat_grjbr_lo; 2325 u32 rx_stat_grjbr_hi; 2326 u32 rx_stat_grovr_lo; 2327 u32 rx_stat_grovr_hi; 2328 u32 rx_stat_grflr_lo; 2329 u32 rx_stat_grflr_hi; 2330 u32 rx_stat_grmeg_lo; 2331 u32 rx_stat_grmeg_hi; 2332 u32 rx_stat_grmeb_lo; 2333 u32 rx_stat_grmeb_hi; 2334 u32 rx_stat_grbyt_lo; 2335 u32 rx_stat_grbyt_hi; 2336 u32 rx_stat_grund_lo; 2337 u32 rx_stat_grund_hi; 2338 u32 rx_stat_grfrg_lo; 2339 u32 rx_stat_grfrg_hi; 2340 u32 rx_stat_grerb_lo; 2341 u32 rx_stat_grerb_hi; 2342 u32 rx_stat_grfre_lo; 2343 u32 rx_stat_grfre_hi; 2344 u32 rx_stat_gripj_lo; 2345 u32 rx_stat_gripj_hi; 2346 }; 2347 2348 struct bmac2_stats { 2349 u32 tx_stat_gtpk_lo; /* gtpok */ 2350 u32 tx_stat_gtpk_hi; /* gtpok */ 2351 u32 tx_stat_gtxpf_lo; /* gtpf */ 2352 u32 tx_stat_gtxpf_hi; /* gtpf */ 2353 u32 tx_stat_gtpp_lo; /* NEW BMAC2 */ 2354 u32 tx_stat_gtpp_hi; /* NEW BMAC2 */ 2355 u32 tx_stat_gtfcs_lo; 2356 u32 tx_stat_gtfcs_hi; 2357 u32 tx_stat_gtuca_lo; /* NEW BMAC2 */ 2358 u32 tx_stat_gtuca_hi; /* NEW BMAC2 */ 2359 u32 tx_stat_gtmca_lo; 2360 u32 tx_stat_gtmca_hi; 2361 u32 tx_stat_gtbca_lo; 2362 u32 tx_stat_gtbca_hi; 2363 u32 tx_stat_gtovr_lo; 2364 u32 tx_stat_gtovr_hi; 2365 u32 tx_stat_gtfrg_lo; 2366 u32 tx_stat_gtfrg_hi; 2367 u32 tx_stat_gtpkt1_lo; /* gtpkt */ 2368 u32 tx_stat_gtpkt1_hi; /* gtpkt */ 2369 u32 tx_stat_gt64_lo; 2370 u32 tx_stat_gt64_hi; 2371 u32 tx_stat_gt127_lo; 2372 u32 tx_stat_gt127_hi; 2373 u32 tx_stat_gt255_lo; 2374 u32 tx_stat_gt255_hi; 2375 u32 tx_stat_gt511_lo; 2376 u32 tx_stat_gt511_hi; 2377 u32 tx_stat_gt1023_lo; 2378 u32 tx_stat_gt1023_hi; 2379 u32 tx_stat_gt1518_lo; 2380 u32 tx_stat_gt1518_hi; 2381 u32 tx_stat_gt2047_lo; 2382 u32 tx_stat_gt2047_hi; 2383 u32 tx_stat_gt4095_lo; 2384 u32 tx_stat_gt4095_hi; 2385 u32 tx_stat_gt9216_lo; 2386 u32 tx_stat_gt9216_hi; 2387 u32 tx_stat_gt16383_lo; 2388 u32 tx_stat_gt16383_hi; 2389 u32 tx_stat_gtmax_lo; 2390 u32 tx_stat_gtmax_hi; 2391 u32 tx_stat_gtufl_lo; 2392 u32 tx_stat_gtufl_hi; 2393 u32 tx_stat_gterr_lo; 2394 u32 tx_stat_gterr_hi; 2395 u32 tx_stat_gtbyt_lo; 2396 u32 tx_stat_gtbyt_hi; 2397 2398 u32 rx_stat_gr64_lo; 2399 u32 rx_stat_gr64_hi; 2400 u32 rx_stat_gr127_lo; 2401 u32 rx_stat_gr127_hi; 2402 u32 rx_stat_gr255_lo; 2403 u32 rx_stat_gr255_hi; 2404 u32 rx_stat_gr511_lo; 2405 u32 rx_stat_gr511_hi; 2406 u32 rx_stat_gr1023_lo; 2407 u32 rx_stat_gr1023_hi; 2408 u32 rx_stat_gr1518_lo; 2409 u32 rx_stat_gr1518_hi; 2410 u32 rx_stat_gr2047_lo; 2411 u32 rx_stat_gr2047_hi; 2412 u32 rx_stat_gr4095_lo; 2413 u32 rx_stat_gr4095_hi; 2414 u32 rx_stat_gr9216_lo; 2415 u32 rx_stat_gr9216_hi; 2416 u32 rx_stat_gr16383_lo; 2417 u32 rx_stat_gr16383_hi; 2418 u32 rx_stat_grmax_lo; 2419 u32 rx_stat_grmax_hi; 2420 u32 rx_stat_grpkt_lo; 2421 u32 rx_stat_grpkt_hi; 2422 u32 rx_stat_grfcs_lo; 2423 u32 rx_stat_grfcs_hi; 2424 u32 rx_stat_gruca_lo; 2425 u32 rx_stat_gruca_hi; 2426 u32 rx_stat_grmca_lo; 2427 u32 rx_stat_grmca_hi; 2428 u32 rx_stat_grbca_lo; 2429 u32 rx_stat_grbca_hi; 2430 u32 rx_stat_grxpf_lo; /* grpf */ 2431 u32 rx_stat_grxpf_hi; /* grpf */ 2432 u32 rx_stat_grpp_lo; 2433 u32 rx_stat_grpp_hi; 2434 u32 rx_stat_grxuo_lo; /* gruo */ 2435 u32 rx_stat_grxuo_hi; /* gruo */ 2436 u32 rx_stat_grjbr_lo; 2437 u32 rx_stat_grjbr_hi; 2438 u32 rx_stat_grovr_lo; 2439 u32 rx_stat_grovr_hi; 2440 u32 rx_stat_grxcf_lo; /* grcf */ 2441 u32 rx_stat_grxcf_hi; /* grcf */ 2442 u32 rx_stat_grflr_lo; 2443 u32 rx_stat_grflr_hi; 2444 u32 rx_stat_grpok_lo; 2445 u32 rx_stat_grpok_hi; 2446 u32 rx_stat_grmeg_lo; 2447 u32 rx_stat_grmeg_hi; 2448 u32 rx_stat_grmeb_lo; 2449 u32 rx_stat_grmeb_hi; 2450 u32 rx_stat_grbyt_lo; 2451 u32 rx_stat_grbyt_hi; 2452 u32 rx_stat_grund_lo; 2453 u32 rx_stat_grund_hi; 2454 u32 rx_stat_grfrg_lo; 2455 u32 rx_stat_grfrg_hi; 2456 u32 rx_stat_grerb_lo; /* grerrbyt */ 2457 u32 rx_stat_grerb_hi; /* grerrbyt */ 2458 u32 rx_stat_grfre_lo; /* grfrerr */ 2459 u32 rx_stat_grfre_hi; /* grfrerr */ 2460 u32 rx_stat_gripj_lo; 2461 u32 rx_stat_gripj_hi; 2462 }; 2463 2464 struct mstat_stats { 2465 struct { 2466 /* OTE MSTAT on E3 has a bug where this register's contents are 2467 * actually tx_gtxpok + tx_gtxpf + (possibly)tx_gtxpp 2468 */ 2469 u32 tx_gtxpok_lo; 2470 u32 tx_gtxpok_hi; 2471 u32 tx_gtxpf_lo; 2472 u32 tx_gtxpf_hi; 2473 u32 tx_gtxpp_lo; 2474 u32 tx_gtxpp_hi; 2475 u32 tx_gtfcs_lo; 2476 u32 tx_gtfcs_hi; 2477 u32 tx_gtuca_lo; 2478 u32 tx_gtuca_hi; 2479 u32 tx_gtmca_lo; 2480 u32 tx_gtmca_hi; 2481 u32 tx_gtgca_lo; 2482 u32 tx_gtgca_hi; 2483 u32 tx_gtpkt_lo; 2484 u32 tx_gtpkt_hi; 2485 u32 tx_gt64_lo; 2486 u32 tx_gt64_hi; 2487 u32 tx_gt127_lo; 2488 u32 tx_gt127_hi; 2489 u32 tx_gt255_lo; 2490 u32 tx_gt255_hi; 2491 u32 tx_gt511_lo; 2492 u32 tx_gt511_hi; 2493 u32 tx_gt1023_lo; 2494 u32 tx_gt1023_hi; 2495 u32 tx_gt1518_lo; 2496 u32 tx_gt1518_hi; 2497 u32 tx_gt2047_lo; 2498 u32 tx_gt2047_hi; 2499 u32 tx_gt4095_lo; 2500 u32 tx_gt4095_hi; 2501 u32 tx_gt9216_lo; 2502 u32 tx_gt9216_hi; 2503 u32 tx_gt16383_lo; 2504 u32 tx_gt16383_hi; 2505 u32 tx_gtufl_lo; 2506 u32 tx_gtufl_hi; 2507 u32 tx_gterr_lo; 2508 u32 tx_gterr_hi; 2509 u32 tx_gtbyt_lo; 2510 u32 tx_gtbyt_hi; 2511 u32 tx_collisions_lo; 2512 u32 tx_collisions_hi; 2513 u32 tx_singlecollision_lo; 2514 u32 tx_singlecollision_hi; 2515 u32 tx_multiplecollisions_lo; 2516 u32 tx_multiplecollisions_hi; 2517 u32 tx_deferred_lo; 2518 u32 tx_deferred_hi; 2519 u32 tx_excessivecollisions_lo; 2520 u32 tx_excessivecollisions_hi; 2521 u32 tx_latecollisions_lo; 2522 u32 tx_latecollisions_hi; 2523 } stats_tx; 2524 2525 struct { 2526 u32 rx_gr64_lo; 2527 u32 rx_gr64_hi; 2528 u32 rx_gr127_lo; 2529 u32 rx_gr127_hi; 2530 u32 rx_gr255_lo; 2531 u32 rx_gr255_hi; 2532 u32 rx_gr511_lo; 2533 u32 rx_gr511_hi; 2534 u32 rx_gr1023_lo; 2535 u32 rx_gr1023_hi; 2536 u32 rx_gr1518_lo; 2537 u32 rx_gr1518_hi; 2538 u32 rx_gr2047_lo; 2539 u32 rx_gr2047_hi; 2540 u32 rx_gr4095_lo; 2541 u32 rx_gr4095_hi; 2542 u32 rx_gr9216_lo; 2543 u32 rx_gr9216_hi; 2544 u32 rx_gr16383_lo; 2545 u32 rx_gr16383_hi; 2546 u32 rx_grpkt_lo; 2547 u32 rx_grpkt_hi; 2548 u32 rx_grfcs_lo; 2549 u32 rx_grfcs_hi; 2550 u32 rx_gruca_lo; 2551 u32 rx_gruca_hi; 2552 u32 rx_grmca_lo; 2553 u32 rx_grmca_hi; 2554 u32 rx_grbca_lo; 2555 u32 rx_grbca_hi; 2556 u32 rx_grxpf_lo; 2557 u32 rx_grxpf_hi; 2558 u32 rx_grxpp_lo; 2559 u32 rx_grxpp_hi; 2560 u32 rx_grxuo_lo; 2561 u32 rx_grxuo_hi; 2562 u32 rx_grovr_lo; 2563 u32 rx_grovr_hi; 2564 u32 rx_grxcf_lo; 2565 u32 rx_grxcf_hi; 2566 u32 rx_grflr_lo; 2567 u32 rx_grflr_hi; 2568 u32 rx_grpok_lo; 2569 u32 rx_grpok_hi; 2570 u32 rx_grbyt_lo; 2571 u32 rx_grbyt_hi; 2572 u32 rx_grund_lo; 2573 u32 rx_grund_hi; 2574 u32 rx_grfrg_lo; 2575 u32 rx_grfrg_hi; 2576 u32 rx_grerb_lo; 2577 u32 rx_grerb_hi; 2578 u32 rx_grfre_lo; 2579 u32 rx_grfre_hi; 2580 2581 u32 rx_alignmenterrors_lo; 2582 u32 rx_alignmenterrors_hi; 2583 u32 rx_falsecarrier_lo; 2584 u32 rx_falsecarrier_hi; 2585 u32 rx_llfcmsgcnt_lo; 2586 u32 rx_llfcmsgcnt_hi; 2587 } stats_rx; 2588 }; 2589 2590 union mac_stats { 2591 struct emac_stats emac_stats; 2592 struct bmac1_stats bmac1_stats; 2593 struct bmac2_stats bmac2_stats; 2594 struct mstat_stats mstat_stats; 2595 }; 2596 2597 2598 struct mac_stx { 2599 /* in_bad_octets */ 2600 u32 rx_stat_ifhcinbadoctets_hi; 2601 u32 rx_stat_ifhcinbadoctets_lo; 2602 2603 /* out_bad_octets */ 2604 u32 tx_stat_ifhcoutbadoctets_hi; 2605 u32 tx_stat_ifhcoutbadoctets_lo; 2606 2607 /* crc_receive_errors */ 2608 u32 rx_stat_dot3statsfcserrors_hi; 2609 u32 rx_stat_dot3statsfcserrors_lo; 2610 /* alignment_errors */ 2611 u32 rx_stat_dot3statsalignmenterrors_hi; 2612 u32 rx_stat_dot3statsalignmenterrors_lo; 2613 /* carrier_sense_errors */ 2614 u32 rx_stat_dot3statscarriersenseerrors_hi; 2615 u32 rx_stat_dot3statscarriersenseerrors_lo; 2616 /* false_carrier_detections */ 2617 u32 rx_stat_falsecarriererrors_hi; 2618 u32 rx_stat_falsecarriererrors_lo; 2619 2620 /* runt_packets_received */ 2621 u32 rx_stat_etherstatsundersizepkts_hi; 2622 u32 rx_stat_etherstatsundersizepkts_lo; 2623 /* jabber_packets_received */ 2624 u32 rx_stat_dot3statsframestoolong_hi; 2625 u32 rx_stat_dot3statsframestoolong_lo; 2626 2627 /* error_runt_packets_received */ 2628 u32 rx_stat_etherstatsfragments_hi; 2629 u32 rx_stat_etherstatsfragments_lo; 2630 /* error_jabber_packets_received */ 2631 u32 rx_stat_etherstatsjabbers_hi; 2632 u32 rx_stat_etherstatsjabbers_lo; 2633 2634 /* control_frames_received */ 2635 u32 rx_stat_maccontrolframesreceived_hi; 2636 u32 rx_stat_maccontrolframesreceived_lo; 2637 u32 rx_stat_mac_xpf_hi; 2638 u32 rx_stat_mac_xpf_lo; 2639 u32 rx_stat_mac_xcf_hi; 2640 u32 rx_stat_mac_xcf_lo; 2641 2642 /* xoff_state_entered */ 2643 u32 rx_stat_xoffstateentered_hi; 2644 u32 rx_stat_xoffstateentered_lo; 2645 /* pause_xon_frames_received */ 2646 u32 rx_stat_xonpauseframesreceived_hi; 2647 u32 rx_stat_xonpauseframesreceived_lo; 2648 /* pause_xoff_frames_received */ 2649 u32 rx_stat_xoffpauseframesreceived_hi; 2650 u32 rx_stat_xoffpauseframesreceived_lo; 2651 /* pause_xon_frames_transmitted */ 2652 u32 tx_stat_outxonsent_hi; 2653 u32 tx_stat_outxonsent_lo; 2654 /* pause_xoff_frames_transmitted */ 2655 u32 tx_stat_outxoffsent_hi; 2656 u32 tx_stat_outxoffsent_lo; 2657 /* flow_control_done */ 2658 u32 tx_stat_flowcontroldone_hi; 2659 u32 tx_stat_flowcontroldone_lo; 2660 2661 /* ether_stats_collisions */ 2662 u32 tx_stat_etherstatscollisions_hi; 2663 u32 tx_stat_etherstatscollisions_lo; 2664 /* single_collision_transmit_frames */ 2665 u32 tx_stat_dot3statssinglecollisionframes_hi; 2666 u32 tx_stat_dot3statssinglecollisionframes_lo; 2667 /* multiple_collision_transmit_frames */ 2668 u32 tx_stat_dot3statsmultiplecollisionframes_hi; 2669 u32 tx_stat_dot3statsmultiplecollisionframes_lo; 2670 /* deferred_transmissions */ 2671 u32 tx_stat_dot3statsdeferredtransmissions_hi; 2672 u32 tx_stat_dot3statsdeferredtransmissions_lo; 2673 /* excessive_collision_frames */ 2674 u32 tx_stat_dot3statsexcessivecollisions_hi; 2675 u32 tx_stat_dot3statsexcessivecollisions_lo; 2676 /* late_collision_frames */ 2677 u32 tx_stat_dot3statslatecollisions_hi; 2678 u32 tx_stat_dot3statslatecollisions_lo; 2679 2680 /* frames_transmitted_64_bytes */ 2681 u32 tx_stat_etherstatspkts64octets_hi; 2682 u32 tx_stat_etherstatspkts64octets_lo; 2683 /* frames_transmitted_65_127_bytes */ 2684 u32 tx_stat_etherstatspkts65octetsto127octets_hi; 2685 u32 tx_stat_etherstatspkts65octetsto127octets_lo; 2686 /* frames_transmitted_128_255_bytes */ 2687 u32 tx_stat_etherstatspkts128octetsto255octets_hi; 2688 u32 tx_stat_etherstatspkts128octetsto255octets_lo; 2689 /* frames_transmitted_256_511_bytes */ 2690 u32 tx_stat_etherstatspkts256octetsto511octets_hi; 2691 u32 tx_stat_etherstatspkts256octetsto511octets_lo; 2692 /* frames_transmitted_512_1023_bytes */ 2693 u32 tx_stat_etherstatspkts512octetsto1023octets_hi; 2694 u32 tx_stat_etherstatspkts512octetsto1023octets_lo; 2695 /* frames_transmitted_1024_1522_bytes */ 2696 u32 tx_stat_etherstatspkts1024octetsto1522octets_hi; 2697 u32 tx_stat_etherstatspkts1024octetsto1522octets_lo; 2698 /* frames_transmitted_1523_9022_bytes */ 2699 u32 tx_stat_etherstatspktsover1522octets_hi; 2700 u32 tx_stat_etherstatspktsover1522octets_lo; 2701 u32 tx_stat_mac_2047_hi; 2702 u32 tx_stat_mac_2047_lo; 2703 u32 tx_stat_mac_4095_hi; 2704 u32 tx_stat_mac_4095_lo; 2705 u32 tx_stat_mac_9216_hi; 2706 u32 tx_stat_mac_9216_lo; 2707 u32 tx_stat_mac_16383_hi; 2708 u32 tx_stat_mac_16383_lo; 2709 2710 /* internal_mac_transmit_errors */ 2711 u32 tx_stat_dot3statsinternalmactransmiterrors_hi; 2712 u32 tx_stat_dot3statsinternalmactransmiterrors_lo; 2713 2714 /* if_out_discards */ 2715 u32 tx_stat_mac_ufl_hi; 2716 u32 tx_stat_mac_ufl_lo; 2717 }; 2718 2719 2720 #define MAC_STX_IDX_MAX 2 2721 2722 struct host_port_stats { 2723 u32 host_port_stats_counter; 2724 2725 struct mac_stx mac_stx[MAC_STX_IDX_MAX]; 2726 2727 u32 brb_drop_hi; 2728 u32 brb_drop_lo; 2729 2730 u32 not_used; /* obsolete */ 2731 u32 pfc_frames_tx_hi; 2732 u32 pfc_frames_tx_lo; 2733 u32 pfc_frames_rx_hi; 2734 u32 pfc_frames_rx_lo; 2735 2736 u32 eee_lpi_count_hi; 2737 u32 eee_lpi_count_lo; 2738 }; 2739 2740 2741 struct host_func_stats { 2742 u32 host_func_stats_start; 2743 2744 u32 total_bytes_received_hi; 2745 u32 total_bytes_received_lo; 2746 2747 u32 total_bytes_transmitted_hi; 2748 u32 total_bytes_transmitted_lo; 2749 2750 u32 total_unicast_packets_received_hi; 2751 u32 total_unicast_packets_received_lo; 2752 2753 u32 total_multicast_packets_received_hi; 2754 u32 total_multicast_packets_received_lo; 2755 2756 u32 total_broadcast_packets_received_hi; 2757 u32 total_broadcast_packets_received_lo; 2758 2759 u32 total_unicast_packets_transmitted_hi; 2760 u32 total_unicast_packets_transmitted_lo; 2761 2762 u32 total_multicast_packets_transmitted_hi; 2763 u32 total_multicast_packets_transmitted_lo; 2764 2765 u32 total_broadcast_packets_transmitted_hi; 2766 u32 total_broadcast_packets_transmitted_lo; 2767 2768 u32 valid_bytes_received_hi; 2769 u32 valid_bytes_received_lo; 2770 2771 u32 host_func_stats_end; 2772 }; 2773 2774 /* VIC definitions */ 2775 #define VICSTATST_UIF_INDEX 2 2776 2777 2778 /* stats collected for afex. 2779 * NOTE: structure is exactly as expected to be received by the switch. 2780 * order must remain exactly as is unless protocol changes ! 2781 */ 2782 struct afex_stats { 2783 u32 tx_unicast_frames_hi; 2784 u32 tx_unicast_frames_lo; 2785 u32 tx_unicast_bytes_hi; 2786 u32 tx_unicast_bytes_lo; 2787 u32 tx_multicast_frames_hi; 2788 u32 tx_multicast_frames_lo; 2789 u32 tx_multicast_bytes_hi; 2790 u32 tx_multicast_bytes_lo; 2791 u32 tx_broadcast_frames_hi; 2792 u32 tx_broadcast_frames_lo; 2793 u32 tx_broadcast_bytes_hi; 2794 u32 tx_broadcast_bytes_lo; 2795 u32 tx_frames_discarded_hi; 2796 u32 tx_frames_discarded_lo; 2797 u32 tx_frames_dropped_hi; 2798 u32 tx_frames_dropped_lo; 2799 2800 u32 rx_unicast_frames_hi; 2801 u32 rx_unicast_frames_lo; 2802 u32 rx_unicast_bytes_hi; 2803 u32 rx_unicast_bytes_lo; 2804 u32 rx_multicast_frames_hi; 2805 u32 rx_multicast_frames_lo; 2806 u32 rx_multicast_bytes_hi; 2807 u32 rx_multicast_bytes_lo; 2808 u32 rx_broadcast_frames_hi; 2809 u32 rx_broadcast_frames_lo; 2810 u32 rx_broadcast_bytes_hi; 2811 u32 rx_broadcast_bytes_lo; 2812 u32 rx_frames_discarded_hi; 2813 u32 rx_frames_discarded_lo; 2814 u32 rx_frames_dropped_hi; 2815 u32 rx_frames_dropped_lo; 2816 }; 2817 2818 #define BCM_5710_FW_MAJOR_VERSION 7 2819 #define BCM_5710_FW_MINOR_VERSION 8 2820 #define BCM_5710_FW_REVISION_VERSION 2 2821 #define BCM_5710_FW_ENGINEERING_VERSION 0 2822 #define BCM_5710_FW_COMPILE_FLAGS 1 2823 2824 2825 /* 2826 * attention bits 2827 */ 2828 struct atten_sp_status_block { 2829 __le32 attn_bits; 2830 __le32 attn_bits_ack; 2831 u8 status_block_id; 2832 u8 reserved0; 2833 __le16 attn_bits_index; 2834 __le32 reserved1; 2835 }; 2836 2837 2838 /* 2839 * The eth aggregative context of Cstorm 2840 */ 2841 struct cstorm_eth_ag_context { 2842 u32 __reserved0[10]; 2843 }; 2844 2845 2846 /* 2847 * dmae command structure 2848 */ 2849 struct dmae_command { 2850 u32 opcode; 2851 #define DMAE_COMMAND_SRC (0x1<<0) 2852 #define DMAE_COMMAND_SRC_SHIFT 0 2853 #define DMAE_COMMAND_DST (0x3<<1) 2854 #define DMAE_COMMAND_DST_SHIFT 1 2855 #define DMAE_COMMAND_C_DST (0x1<<3) 2856 #define DMAE_COMMAND_C_DST_SHIFT 3 2857 #define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4) 2858 #define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4 2859 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5) 2860 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5 2861 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6) 2862 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6 2863 #define DMAE_COMMAND_ENDIANITY (0x3<<9) 2864 #define DMAE_COMMAND_ENDIANITY_SHIFT 9 2865 #define DMAE_COMMAND_PORT (0x1<<11) 2866 #define DMAE_COMMAND_PORT_SHIFT 11 2867 #define DMAE_COMMAND_CRC_RESET (0x1<<12) 2868 #define DMAE_COMMAND_CRC_RESET_SHIFT 12 2869 #define DMAE_COMMAND_SRC_RESET (0x1<<13) 2870 #define DMAE_COMMAND_SRC_RESET_SHIFT 13 2871 #define DMAE_COMMAND_DST_RESET (0x1<<14) 2872 #define DMAE_COMMAND_DST_RESET_SHIFT 14 2873 #define DMAE_COMMAND_E1HVN (0x3<<15) 2874 #define DMAE_COMMAND_E1HVN_SHIFT 15 2875 #define DMAE_COMMAND_DST_VN (0x3<<17) 2876 #define DMAE_COMMAND_DST_VN_SHIFT 17 2877 #define DMAE_COMMAND_C_FUNC (0x1<<19) 2878 #define DMAE_COMMAND_C_FUNC_SHIFT 19 2879 #define DMAE_COMMAND_ERR_POLICY (0x3<<20) 2880 #define DMAE_COMMAND_ERR_POLICY_SHIFT 20 2881 #define DMAE_COMMAND_RESERVED0 (0x3FF<<22) 2882 #define DMAE_COMMAND_RESERVED0_SHIFT 22 2883 u32 src_addr_lo; 2884 u32 src_addr_hi; 2885 u32 dst_addr_lo; 2886 u32 dst_addr_hi; 2887 #if defined(__BIG_ENDIAN) 2888 u16 opcode_iov; 2889 #define DMAE_COMMAND_SRC_VFID (0x3F<<0) 2890 #define DMAE_COMMAND_SRC_VFID_SHIFT 0 2891 #define DMAE_COMMAND_SRC_VFPF (0x1<<6) 2892 #define DMAE_COMMAND_SRC_VFPF_SHIFT 6 2893 #define DMAE_COMMAND_RESERVED1 (0x1<<7) 2894 #define DMAE_COMMAND_RESERVED1_SHIFT 7 2895 #define DMAE_COMMAND_DST_VFID (0x3F<<8) 2896 #define DMAE_COMMAND_DST_VFID_SHIFT 8 2897 #define DMAE_COMMAND_DST_VFPF (0x1<<14) 2898 #define DMAE_COMMAND_DST_VFPF_SHIFT 14 2899 #define DMAE_COMMAND_RESERVED2 (0x1<<15) 2900 #define DMAE_COMMAND_RESERVED2_SHIFT 15 2901 u16 len; 2902 #elif defined(__LITTLE_ENDIAN) 2903 u16 len; 2904 u16 opcode_iov; 2905 #define DMAE_COMMAND_SRC_VFID (0x3F<<0) 2906 #define DMAE_COMMAND_SRC_VFID_SHIFT 0 2907 #define DMAE_COMMAND_SRC_VFPF (0x1<<6) 2908 #define DMAE_COMMAND_SRC_VFPF_SHIFT 6 2909 #define DMAE_COMMAND_RESERVED1 (0x1<<7) 2910 #define DMAE_COMMAND_RESERVED1_SHIFT 7 2911 #define DMAE_COMMAND_DST_VFID (0x3F<<8) 2912 #define DMAE_COMMAND_DST_VFID_SHIFT 8 2913 #define DMAE_COMMAND_DST_VFPF (0x1<<14) 2914 #define DMAE_COMMAND_DST_VFPF_SHIFT 14 2915 #define DMAE_COMMAND_RESERVED2 (0x1<<15) 2916 #define DMAE_COMMAND_RESERVED2_SHIFT 15 2917 #endif 2918 u32 comp_addr_lo; 2919 u32 comp_addr_hi; 2920 u32 comp_val; 2921 u32 crc32; 2922 u32 crc32_c; 2923 #if defined(__BIG_ENDIAN) 2924 u16 crc16_c; 2925 u16 crc16; 2926 #elif defined(__LITTLE_ENDIAN) 2927 u16 crc16; 2928 u16 crc16_c; 2929 #endif 2930 #if defined(__BIG_ENDIAN) 2931 u16 reserved3; 2932 u16 crc_t10; 2933 #elif defined(__LITTLE_ENDIAN) 2934 u16 crc_t10; 2935 u16 reserved3; 2936 #endif 2937 #if defined(__BIG_ENDIAN) 2938 u16 xsum8; 2939 u16 xsum16; 2940 #elif defined(__LITTLE_ENDIAN) 2941 u16 xsum16; 2942 u16 xsum8; 2943 #endif 2944 }; 2945 2946 2947 /* 2948 * common data for all protocols 2949 */ 2950 struct doorbell_hdr { 2951 u8 header; 2952 #define DOORBELL_HDR_RX (0x1<<0) 2953 #define DOORBELL_HDR_RX_SHIFT 0 2954 #define DOORBELL_HDR_DB_TYPE (0x1<<1) 2955 #define DOORBELL_HDR_DB_TYPE_SHIFT 1 2956 #define DOORBELL_HDR_DPM_SIZE (0x3<<2) 2957 #define DOORBELL_HDR_DPM_SIZE_SHIFT 2 2958 #define DOORBELL_HDR_CONN_TYPE (0xF<<4) 2959 #define DOORBELL_HDR_CONN_TYPE_SHIFT 4 2960 }; 2961 2962 /* 2963 * Ethernet doorbell 2964 */ 2965 struct eth_tx_doorbell { 2966 #if defined(__BIG_ENDIAN) 2967 u16 npackets; 2968 u8 params; 2969 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) 2970 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0 2971 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) 2972 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6 2973 #define ETH_TX_DOORBELL_SPARE (0x1<<7) 2974 #define ETH_TX_DOORBELL_SPARE_SHIFT 7 2975 struct doorbell_hdr hdr; 2976 #elif defined(__LITTLE_ENDIAN) 2977 struct doorbell_hdr hdr; 2978 u8 params; 2979 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) 2980 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0 2981 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) 2982 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6 2983 #define ETH_TX_DOORBELL_SPARE (0x1<<7) 2984 #define ETH_TX_DOORBELL_SPARE_SHIFT 7 2985 u16 npackets; 2986 #endif 2987 }; 2988 2989 2990 /* 2991 * 3 lines. status block 2992 */ 2993 struct hc_status_block_e1x { 2994 __le16 index_values[HC_SB_MAX_INDICES_E1X]; 2995 __le16 running_index[HC_SB_MAX_SM]; 2996 __le32 rsrv[11]; 2997 }; 2998 2999 /* 3000 * host status block 3001 */ 3002 struct host_hc_status_block_e1x { 3003 struct hc_status_block_e1x sb; 3004 }; 3005 3006 3007 /* 3008 * 3 lines. status block 3009 */ 3010 struct hc_status_block_e2 { 3011 __le16 index_values[HC_SB_MAX_INDICES_E2]; 3012 __le16 running_index[HC_SB_MAX_SM]; 3013 __le32 reserved[11]; 3014 }; 3015 3016 /* 3017 * host status block 3018 */ 3019 struct host_hc_status_block_e2 { 3020 struct hc_status_block_e2 sb; 3021 }; 3022 3023 3024 /* 3025 * 5 lines. slow-path status block 3026 */ 3027 struct hc_sp_status_block { 3028 __le16 index_values[HC_SP_SB_MAX_INDICES]; 3029 __le16 running_index; 3030 __le16 rsrv; 3031 u32 rsrv1; 3032 }; 3033 3034 /* 3035 * host status block 3036 */ 3037 struct host_sp_status_block { 3038 struct atten_sp_status_block atten_status_block; 3039 struct hc_sp_status_block sp_sb; 3040 }; 3041 3042 3043 /* 3044 * IGU driver acknowledgment register 3045 */ 3046 struct igu_ack_register { 3047 #if defined(__BIG_ENDIAN) 3048 u16 sb_id_and_flags; 3049 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) 3050 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0 3051 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5) 3052 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5 3053 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) 3054 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8 3055 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) 3056 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9 3057 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11) 3058 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11 3059 u16 status_block_index; 3060 #elif defined(__LITTLE_ENDIAN) 3061 u16 status_block_index; 3062 u16 sb_id_and_flags; 3063 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) 3064 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0 3065 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5) 3066 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5 3067 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) 3068 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8 3069 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) 3070 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9 3071 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11) 3072 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11 3073 #endif 3074 }; 3075 3076 3077 /* 3078 * IGU driver acknowledgement register 3079 */ 3080 struct igu_backward_compatible { 3081 u32 sb_id_and_flags; 3082 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0) 3083 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0 3084 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16) 3085 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16 3086 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21) 3087 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21 3088 #define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24) 3089 #define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24 3090 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25) 3091 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25 3092 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27) 3093 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27 3094 u32 reserved_2; 3095 }; 3096 3097 3098 /* 3099 * IGU driver acknowledgement register 3100 */ 3101 struct igu_regular { 3102 u32 sb_id_and_flags; 3103 #define IGU_REGULAR_SB_INDEX (0xFFFFF<<0) 3104 #define IGU_REGULAR_SB_INDEX_SHIFT 0 3105 #define IGU_REGULAR_RESERVED0 (0x1<<20) 3106 #define IGU_REGULAR_RESERVED0_SHIFT 20 3107 #define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21) 3108 #define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21 3109 #define IGU_REGULAR_BUPDATE (0x1<<24) 3110 #define IGU_REGULAR_BUPDATE_SHIFT 24 3111 #define IGU_REGULAR_ENABLE_INT (0x3<<25) 3112 #define IGU_REGULAR_ENABLE_INT_SHIFT 25 3113 #define IGU_REGULAR_RESERVED_1 (0x1<<27) 3114 #define IGU_REGULAR_RESERVED_1_SHIFT 27 3115 #define IGU_REGULAR_CLEANUP_TYPE (0x3<<28) 3116 #define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28 3117 #define IGU_REGULAR_CLEANUP_SET (0x1<<30) 3118 #define IGU_REGULAR_CLEANUP_SET_SHIFT 30 3119 #define IGU_REGULAR_BCLEANUP (0x1<<31) 3120 #define IGU_REGULAR_BCLEANUP_SHIFT 31 3121 u32 reserved_2; 3122 }; 3123 3124 /* 3125 * IGU driver acknowledgement register 3126 */ 3127 union igu_consprod_reg { 3128 struct igu_regular regular; 3129 struct igu_backward_compatible backward_compatible; 3130 }; 3131 3132 3133 /* 3134 * Igu control commands 3135 */ 3136 enum igu_ctrl_cmd { 3137 IGU_CTRL_CMD_TYPE_RD, 3138 IGU_CTRL_CMD_TYPE_WR, 3139 MAX_IGU_CTRL_CMD 3140 }; 3141 3142 3143 /* 3144 * Control register for the IGU command register 3145 */ 3146 struct igu_ctrl_reg { 3147 u32 ctrl_data; 3148 #define IGU_CTRL_REG_ADDRESS (0xFFF<<0) 3149 #define IGU_CTRL_REG_ADDRESS_SHIFT 0 3150 #define IGU_CTRL_REG_FID (0x7F<<12) 3151 #define IGU_CTRL_REG_FID_SHIFT 12 3152 #define IGU_CTRL_REG_RESERVED (0x1<<19) 3153 #define IGU_CTRL_REG_RESERVED_SHIFT 19 3154 #define IGU_CTRL_REG_TYPE (0x1<<20) 3155 #define IGU_CTRL_REG_TYPE_SHIFT 20 3156 #define IGU_CTRL_REG_UNUSED (0x7FF<<21) 3157 #define IGU_CTRL_REG_UNUSED_SHIFT 21 3158 }; 3159 3160 3161 /* 3162 * Igu interrupt command 3163 */ 3164 enum igu_int_cmd { 3165 IGU_INT_ENABLE, 3166 IGU_INT_DISABLE, 3167 IGU_INT_NOP, 3168 IGU_INT_NOP2, 3169 MAX_IGU_INT_CMD 3170 }; 3171 3172 3173 /* 3174 * Igu segments 3175 */ 3176 enum igu_seg_access { 3177 IGU_SEG_ACCESS_NORM, 3178 IGU_SEG_ACCESS_DEF, 3179 IGU_SEG_ACCESS_ATTN, 3180 MAX_IGU_SEG_ACCESS 3181 }; 3182 3183 3184 /* 3185 * Parser parsing flags field 3186 */ 3187 struct parsing_flags { 3188 __le16 flags; 3189 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0) 3190 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0 3191 #define PARSING_FLAGS_VLAN (0x1<<1) 3192 #define PARSING_FLAGS_VLAN_SHIFT 1 3193 #define PARSING_FLAGS_EXTRA_VLAN (0x1<<2) 3194 #define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2 3195 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3) 3196 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3 3197 #define PARSING_FLAGS_IP_OPTIONS (0x1<<5) 3198 #define PARSING_FLAGS_IP_OPTIONS_SHIFT 5 3199 #define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6) 3200 #define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6 3201 #define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7) 3202 #define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7 3203 #define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9) 3204 #define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9 3205 #define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10) 3206 #define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10 3207 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11) 3208 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11 3209 #define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12) 3210 #define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12 3211 #define PARSING_FLAGS_LLC_SNAP (0x1<<13) 3212 #define PARSING_FLAGS_LLC_SNAP_SHIFT 13 3213 #define PARSING_FLAGS_RESERVED0 (0x3<<14) 3214 #define PARSING_FLAGS_RESERVED0_SHIFT 14 3215 }; 3216 3217 3218 /* 3219 * Parsing flags for TCP ACK type 3220 */ 3221 enum prs_flags_ack_type { 3222 PRS_FLAG_PUREACK_PIGGY, 3223 PRS_FLAG_PUREACK_PURE, 3224 MAX_PRS_FLAGS_ACK_TYPE 3225 }; 3226 3227 3228 /* 3229 * Parsing flags for Ethernet address type 3230 */ 3231 enum prs_flags_eth_addr_type { 3232 PRS_FLAG_ETHTYPE_NON_UNICAST, 3233 PRS_FLAG_ETHTYPE_UNICAST, 3234 MAX_PRS_FLAGS_ETH_ADDR_TYPE 3235 }; 3236 3237 3238 /* 3239 * Parsing flags for over-ethernet protocol 3240 */ 3241 enum prs_flags_over_eth { 3242 PRS_FLAG_OVERETH_UNKNOWN, 3243 PRS_FLAG_OVERETH_IPV4, 3244 PRS_FLAG_OVERETH_IPV6, 3245 PRS_FLAG_OVERETH_LLCSNAP_UNKNOWN, 3246 MAX_PRS_FLAGS_OVER_ETH 3247 }; 3248 3249 3250 /* 3251 * Parsing flags for over-IP protocol 3252 */ 3253 enum prs_flags_over_ip { 3254 PRS_FLAG_OVERIP_UNKNOWN, 3255 PRS_FLAG_OVERIP_TCP, 3256 PRS_FLAG_OVERIP_UDP, 3257 MAX_PRS_FLAGS_OVER_IP 3258 }; 3259 3260 3261 /* 3262 * SDM operation gen command (generate aggregative interrupt) 3263 */ 3264 struct sdm_op_gen { 3265 __le32 command; 3266 #define SDM_OP_GEN_COMP_PARAM (0x1F<<0) 3267 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0 3268 #define SDM_OP_GEN_COMP_TYPE (0x7<<5) 3269 #define SDM_OP_GEN_COMP_TYPE_SHIFT 5 3270 #define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8) 3271 #define SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8 3272 #define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16) 3273 #define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16 3274 #define SDM_OP_GEN_RESERVED (0x7FFF<<17) 3275 #define SDM_OP_GEN_RESERVED_SHIFT 17 3276 }; 3277 3278 3279 /* 3280 * Timers connection context 3281 */ 3282 struct timers_block_context { 3283 u32 __reserved_0; 3284 u32 __reserved_1; 3285 u32 __reserved_2; 3286 u32 flags; 3287 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0) 3288 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0 3289 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2) 3290 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2 3291 #define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3) 3292 #define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3 3293 }; 3294 3295 3296 /* 3297 * The eth aggregative context of Tstorm 3298 */ 3299 struct tstorm_eth_ag_context { 3300 u32 __reserved0[14]; 3301 }; 3302 3303 3304 /* 3305 * The eth aggregative context of Ustorm 3306 */ 3307 struct ustorm_eth_ag_context { 3308 u32 __reserved0; 3309 #if defined(__BIG_ENDIAN) 3310 u8 cdu_usage; 3311 u8 __reserved2; 3312 u16 __reserved1; 3313 #elif defined(__LITTLE_ENDIAN) 3314 u16 __reserved1; 3315 u8 __reserved2; 3316 u8 cdu_usage; 3317 #endif 3318 u32 __reserved3[6]; 3319 }; 3320 3321 3322 /* 3323 * The eth aggregative context of Xstorm 3324 */ 3325 struct xstorm_eth_ag_context { 3326 u32 reserved0; 3327 #if defined(__BIG_ENDIAN) 3328 u8 cdu_reserved; 3329 u8 reserved2; 3330 u16 reserved1; 3331 #elif defined(__LITTLE_ENDIAN) 3332 u16 reserved1; 3333 u8 reserved2; 3334 u8 cdu_reserved; 3335 #endif 3336 u32 reserved3[30]; 3337 }; 3338 3339 3340 /* 3341 * doorbell message sent to the chip 3342 */ 3343 struct doorbell { 3344 #if defined(__BIG_ENDIAN) 3345 u16 zero_fill2; 3346 u8 zero_fill1; 3347 struct doorbell_hdr header; 3348 #elif defined(__LITTLE_ENDIAN) 3349 struct doorbell_hdr header; 3350 u8 zero_fill1; 3351 u16 zero_fill2; 3352 #endif 3353 }; 3354 3355 3356 /* 3357 * doorbell message sent to the chip 3358 */ 3359 struct doorbell_set_prod { 3360 #if defined(__BIG_ENDIAN) 3361 u16 prod; 3362 u8 zero_fill1; 3363 struct doorbell_hdr header; 3364 #elif defined(__LITTLE_ENDIAN) 3365 struct doorbell_hdr header; 3366 u8 zero_fill1; 3367 u16 prod; 3368 #endif 3369 }; 3370 3371 3372 struct regpair { 3373 __le32 lo; 3374 __le32 hi; 3375 }; 3376 3377 3378 /* 3379 * Classify rule opcodes in E2/E3 3380 */ 3381 enum classify_rule { 3382 CLASSIFY_RULE_OPCODE_MAC, 3383 CLASSIFY_RULE_OPCODE_VLAN, 3384 CLASSIFY_RULE_OPCODE_PAIR, 3385 MAX_CLASSIFY_RULE 3386 }; 3387 3388 3389 /* 3390 * Classify rule types in E2/E3 3391 */ 3392 enum classify_rule_action_type { 3393 CLASSIFY_RULE_REMOVE, 3394 CLASSIFY_RULE_ADD, 3395 MAX_CLASSIFY_RULE_ACTION_TYPE 3396 }; 3397 3398 3399 /* 3400 * client init ramrod data 3401 */ 3402 struct client_init_general_data { 3403 u8 client_id; 3404 u8 statistics_counter_id; 3405 u8 statistics_en_flg; 3406 u8 is_fcoe_flg; 3407 u8 activate_flg; 3408 u8 sp_client_id; 3409 __le16 mtu; 3410 u8 statistics_zero_flg; 3411 u8 func_id; 3412 u8 cos; 3413 u8 traffic_type; 3414 u32 reserved0; 3415 }; 3416 3417 3418 /* 3419 * client init rx data 3420 */ 3421 struct client_init_rx_data { 3422 u8 tpa_en; 3423 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1<<0) 3424 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4_SHIFT 0 3425 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1<<1) 3426 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6_SHIFT 1 3427 #define CLIENT_INIT_RX_DATA_TPA_MODE (0x1<<2) 3428 #define CLIENT_INIT_RX_DATA_TPA_MODE_SHIFT 2 3429 #define CLIENT_INIT_RX_DATA_RESERVED5 (0x1F<<3) 3430 #define CLIENT_INIT_RX_DATA_RESERVED5_SHIFT 3 3431 u8 vmqueue_mode_en_flg; 3432 u8 extra_data_over_sgl_en_flg; 3433 u8 cache_line_alignment_log_size; 3434 u8 enable_dynamic_hc; 3435 u8 max_sges_for_packet; 3436 u8 client_qzone_id; 3437 u8 drop_ip_cs_err_flg; 3438 u8 drop_tcp_cs_err_flg; 3439 u8 drop_ttl0_flg; 3440 u8 drop_udp_cs_err_flg; 3441 u8 inner_vlan_removal_enable_flg; 3442 u8 outer_vlan_removal_enable_flg; 3443 u8 status_block_id; 3444 u8 rx_sb_index_number; 3445 u8 dont_verify_rings_pause_thr_flg; 3446 u8 max_tpa_queues; 3447 u8 silent_vlan_removal_flg; 3448 __le16 max_bytes_on_bd; 3449 __le16 sge_buff_size; 3450 u8 approx_mcast_engine_id; 3451 u8 rss_engine_id; 3452 struct regpair bd_page_base; 3453 struct regpair sge_page_base; 3454 struct regpair cqe_page_base; 3455 u8 is_leading_rss; 3456 u8 is_approx_mcast; 3457 __le16 max_agg_size; 3458 __le16 state; 3459 #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1<<0) 3460 #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL_SHIFT 0 3461 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1<<1) 3462 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL_SHIFT 1 3463 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1<<2) 3464 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED_SHIFT 2 3465 #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1<<3) 3466 #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL_SHIFT 3 3467 #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1<<4) 3468 #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL_SHIFT 4 3469 #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1<<5) 3470 #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL_SHIFT 5 3471 #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1<<6) 3472 #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN_SHIFT 6 3473 #define CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF<<7) 3474 #define CLIENT_INIT_RX_DATA_RESERVED2_SHIFT 7 3475 __le16 cqe_pause_thr_low; 3476 __le16 cqe_pause_thr_high; 3477 __le16 bd_pause_thr_low; 3478 __le16 bd_pause_thr_high; 3479 __le16 sge_pause_thr_low; 3480 __le16 sge_pause_thr_high; 3481 __le16 rx_cos_mask; 3482 __le16 silent_vlan_value; 3483 __le16 silent_vlan_mask; 3484 __le32 reserved6[2]; 3485 }; 3486 3487 /* 3488 * client init tx data 3489 */ 3490 struct client_init_tx_data { 3491 u8 enforce_security_flg; 3492 u8 tx_status_block_id; 3493 u8 tx_sb_index_number; 3494 u8 tss_leading_client_id; 3495 u8 tx_switching_flg; 3496 u8 anti_spoofing_flg; 3497 __le16 default_vlan; 3498 struct regpair tx_bd_page_base; 3499 __le16 state; 3500 #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1<<0) 3501 #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL_SHIFT 0 3502 #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1<<1) 3503 #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL_SHIFT 1 3504 #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1<<2) 3505 #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL_SHIFT 2 3506 #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1<<3) 3507 #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN_SHIFT 3 3508 #define CLIENT_INIT_TX_DATA_RESERVED1 (0xFFF<<4) 3509 #define CLIENT_INIT_TX_DATA_RESERVED1_SHIFT 4 3510 u8 default_vlan_flg; 3511 u8 force_default_pri_flg; 3512 __le32 reserved3; 3513 }; 3514 3515 /* 3516 * client init ramrod data 3517 */ 3518 struct client_init_ramrod_data { 3519 struct client_init_general_data general; 3520 struct client_init_rx_data rx; 3521 struct client_init_tx_data tx; 3522 }; 3523 3524 3525 /* 3526 * client update ramrod data 3527 */ 3528 struct client_update_ramrod_data { 3529 u8 client_id; 3530 u8 func_id; 3531 u8 inner_vlan_removal_enable_flg; 3532 u8 inner_vlan_removal_change_flg; 3533 u8 outer_vlan_removal_enable_flg; 3534 u8 outer_vlan_removal_change_flg; 3535 u8 anti_spoofing_enable_flg; 3536 u8 anti_spoofing_change_flg; 3537 u8 activate_flg; 3538 u8 activate_change_flg; 3539 __le16 default_vlan; 3540 u8 default_vlan_enable_flg; 3541 u8 default_vlan_change_flg; 3542 __le16 silent_vlan_value; 3543 __le16 silent_vlan_mask; 3544 u8 silent_vlan_removal_flg; 3545 u8 silent_vlan_change_flg; 3546 __le32 echo; 3547 }; 3548 3549 3550 /* 3551 * The eth storm context of Cstorm 3552 */ 3553 struct cstorm_eth_st_context { 3554 u32 __reserved0[4]; 3555 }; 3556 3557 3558 struct double_regpair { 3559 u32 regpair0_lo; 3560 u32 regpair0_hi; 3561 u32 regpair1_lo; 3562 u32 regpair1_hi; 3563 }; 3564 3565 3566 /* 3567 * Ethernet address typesm used in ethernet tx BDs 3568 */ 3569 enum eth_addr_type { 3570 UNKNOWN_ADDRESS, 3571 UNICAST_ADDRESS, 3572 MULTICAST_ADDRESS, 3573 BROADCAST_ADDRESS, 3574 MAX_ETH_ADDR_TYPE 3575 }; 3576 3577 3578 /* 3579 * 3580 */ 3581 struct eth_classify_cmd_header { 3582 u8 cmd_general_data; 3583 #define ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1<<0) 3584 #define ETH_CLASSIFY_CMD_HEADER_RX_CMD_SHIFT 0 3585 #define ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1<<1) 3586 #define ETH_CLASSIFY_CMD_HEADER_TX_CMD_SHIFT 1 3587 #define ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3<<2) 3588 #define ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT 2 3589 #define ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1<<4) 3590 #define ETH_CLASSIFY_CMD_HEADER_IS_ADD_SHIFT 4 3591 #define ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7<<5) 3592 #define ETH_CLASSIFY_CMD_HEADER_RESERVED0_SHIFT 5 3593 u8 func_id; 3594 u8 client_id; 3595 u8 reserved1; 3596 }; 3597 3598 3599 /* 3600 * header for eth classification config ramrod 3601 */ 3602 struct eth_classify_header { 3603 u8 rule_cnt; 3604 u8 reserved0; 3605 __le16 reserved1; 3606 __le32 echo; 3607 }; 3608 3609 3610 /* 3611 * Command for adding/removing a MAC classification rule 3612 */ 3613 struct eth_classify_mac_cmd { 3614 struct eth_classify_cmd_header header; 3615 __le32 reserved0; 3616 __le16 mac_lsb; 3617 __le16 mac_mid; 3618 __le16 mac_msb; 3619 __le16 reserved1; 3620 }; 3621 3622 3623 /* 3624 * Command for adding/removing a MAC-VLAN pair classification rule 3625 */ 3626 struct eth_classify_pair_cmd { 3627 struct eth_classify_cmd_header header; 3628 __le32 reserved0; 3629 __le16 mac_lsb; 3630 __le16 mac_mid; 3631 __le16 mac_msb; 3632 __le16 vlan; 3633 }; 3634 3635 3636 /* 3637 * Command for adding/removing a VLAN classification rule 3638 */ 3639 struct eth_classify_vlan_cmd { 3640 struct eth_classify_cmd_header header; 3641 __le32 reserved0; 3642 __le32 reserved1; 3643 __le16 reserved2; 3644 __le16 vlan; 3645 }; 3646 3647 /* 3648 * union for eth classification rule 3649 */ 3650 union eth_classify_rule_cmd { 3651 struct eth_classify_mac_cmd mac; 3652 struct eth_classify_vlan_cmd vlan; 3653 struct eth_classify_pair_cmd pair; 3654 }; 3655 3656 /* 3657 * parameters for eth classification configuration ramrod 3658 */ 3659 struct eth_classify_rules_ramrod_data { 3660 struct eth_classify_header header; 3661 union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT]; 3662 }; 3663 3664 3665 /* 3666 * The data contain client ID need to the ramrod 3667 */ 3668 struct eth_common_ramrod_data { 3669 __le32 client_id; 3670 __le32 reserved1; 3671 }; 3672 3673 3674 /* 3675 * The eth storm context of Ustorm 3676 */ 3677 struct ustorm_eth_st_context { 3678 u32 reserved0[52]; 3679 }; 3680 3681 /* 3682 * The eth storm context of Tstorm 3683 */ 3684 struct tstorm_eth_st_context { 3685 u32 __reserved0[28]; 3686 }; 3687 3688 /* 3689 * The eth storm context of Xstorm 3690 */ 3691 struct xstorm_eth_st_context { 3692 u32 reserved0[60]; 3693 }; 3694 3695 /* 3696 * Ethernet connection context 3697 */ 3698 struct eth_context { 3699 struct ustorm_eth_st_context ustorm_st_context; 3700 struct tstorm_eth_st_context tstorm_st_context; 3701 struct xstorm_eth_ag_context xstorm_ag_context; 3702 struct tstorm_eth_ag_context tstorm_ag_context; 3703 struct cstorm_eth_ag_context cstorm_ag_context; 3704 struct ustorm_eth_ag_context ustorm_ag_context; 3705 struct timers_block_context timers_context; 3706 struct xstorm_eth_st_context xstorm_st_context; 3707 struct cstorm_eth_st_context cstorm_st_context; 3708 }; 3709 3710 3711 /* 3712 * union for sgl and raw data. 3713 */ 3714 union eth_sgl_or_raw_data { 3715 __le16 sgl[8]; 3716 u32 raw_data[4]; 3717 }; 3718 3719 /* 3720 * eth FP end aggregation CQE parameters struct 3721 */ 3722 struct eth_end_agg_rx_cqe { 3723 u8 type_error_flags; 3724 #define ETH_END_AGG_RX_CQE_TYPE (0x3<<0) 3725 #define ETH_END_AGG_RX_CQE_TYPE_SHIFT 0 3726 #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1<<2) 3727 #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL_SHIFT 2 3728 #define ETH_END_AGG_RX_CQE_RESERVED0 (0x1F<<3) 3729 #define ETH_END_AGG_RX_CQE_RESERVED0_SHIFT 3 3730 u8 reserved1; 3731 u8 queue_index; 3732 u8 reserved2; 3733 __le32 timestamp_delta; 3734 __le16 num_of_coalesced_segs; 3735 __le16 pkt_len; 3736 u8 pure_ack_count; 3737 u8 reserved3; 3738 __le16 reserved4; 3739 union eth_sgl_or_raw_data sgl_or_raw_data; 3740 __le32 reserved5[8]; 3741 }; 3742 3743 3744 /* 3745 * regular eth FP CQE parameters struct 3746 */ 3747 struct eth_fast_path_rx_cqe { 3748 u8 type_error_flags; 3749 #define ETH_FAST_PATH_RX_CQE_TYPE (0x3<<0) 3750 #define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0 3751 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1<<2) 3752 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 2 3753 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<3) 3754 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 3 3755 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<4) 3756 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 4 3757 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<5) 3758 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 5 3759 #define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6) 3760 #define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6 3761 u8 status_flags; 3762 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0) 3763 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0 3764 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3) 3765 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3 3766 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4) 3767 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4 3768 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5) 3769 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5 3770 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6) 3771 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6 3772 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7) 3773 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7 3774 u8 queue_index; 3775 u8 placement_offset; 3776 __le32 rss_hash_result; 3777 __le16 vlan_tag; 3778 __le16 pkt_len_or_gro_seg_len; 3779 __le16 len_on_bd; 3780 struct parsing_flags pars_flags; 3781 union eth_sgl_or_raw_data sgl_or_raw_data; 3782 __le32 reserved1[8]; 3783 }; 3784 3785 3786 /* 3787 * Command for setting classification flags for a client 3788 */ 3789 struct eth_filter_rules_cmd { 3790 u8 cmd_general_data; 3791 #define ETH_FILTER_RULES_CMD_RX_CMD (0x1<<0) 3792 #define ETH_FILTER_RULES_CMD_RX_CMD_SHIFT 0 3793 #define ETH_FILTER_RULES_CMD_TX_CMD (0x1<<1) 3794 #define ETH_FILTER_RULES_CMD_TX_CMD_SHIFT 1 3795 #define ETH_FILTER_RULES_CMD_RESERVED0 (0x3F<<2) 3796 #define ETH_FILTER_RULES_CMD_RESERVED0_SHIFT 2 3797 u8 func_id; 3798 u8 client_id; 3799 u8 reserved1; 3800 __le16 state; 3801 #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1<<0) 3802 #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL_SHIFT 0 3803 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1<<1) 3804 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL_SHIFT 1 3805 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1<<2) 3806 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED_SHIFT 2 3807 #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1<<3) 3808 #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL_SHIFT 3 3809 #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1<<4) 3810 #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL_SHIFT 4 3811 #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1<<5) 3812 #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL_SHIFT 5 3813 #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1<<6) 3814 #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN_SHIFT 6 3815 #define ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF<<7) 3816 #define ETH_FILTER_RULES_CMD_RESERVED2_SHIFT 7 3817 __le16 reserved3; 3818 struct regpair reserved4; 3819 }; 3820 3821 3822 /* 3823 * parameters for eth classification filters ramrod 3824 */ 3825 struct eth_filter_rules_ramrod_data { 3826 struct eth_classify_header header; 3827 struct eth_filter_rules_cmd rules[FILTER_RULES_COUNT]; 3828 }; 3829 3830 3831 /* 3832 * parameters for eth classification configuration ramrod 3833 */ 3834 struct eth_general_rules_ramrod_data { 3835 struct eth_classify_header header; 3836 union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT]; 3837 }; 3838 3839 3840 /* 3841 * The data for Halt ramrod 3842 */ 3843 struct eth_halt_ramrod_data { 3844 __le32 client_id; 3845 __le32 reserved0; 3846 }; 3847 3848 3849 /* 3850 * Command for setting multicast classification for a client 3851 */ 3852 struct eth_multicast_rules_cmd { 3853 u8 cmd_general_data; 3854 #define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1<<0) 3855 #define ETH_MULTICAST_RULES_CMD_RX_CMD_SHIFT 0 3856 #define ETH_MULTICAST_RULES_CMD_TX_CMD (0x1<<1) 3857 #define ETH_MULTICAST_RULES_CMD_TX_CMD_SHIFT 1 3858 #define ETH_MULTICAST_RULES_CMD_IS_ADD (0x1<<2) 3859 #define ETH_MULTICAST_RULES_CMD_IS_ADD_SHIFT 2 3860 #define ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F<<3) 3861 #define ETH_MULTICAST_RULES_CMD_RESERVED0_SHIFT 3 3862 u8 func_id; 3863 u8 bin_id; 3864 u8 engine_id; 3865 __le32 reserved2; 3866 struct regpair reserved3; 3867 }; 3868 3869 3870 /* 3871 * parameters for multicast classification ramrod 3872 */ 3873 struct eth_multicast_rules_ramrod_data { 3874 struct eth_classify_header header; 3875 struct eth_multicast_rules_cmd rules[MULTICAST_RULES_COUNT]; 3876 }; 3877 3878 3879 /* 3880 * Place holder for ramrods protocol specific data 3881 */ 3882 struct ramrod_data { 3883 __le32 data_lo; 3884 __le32 data_hi; 3885 }; 3886 3887 /* 3888 * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits) 3889 */ 3890 union eth_ramrod_data { 3891 struct ramrod_data general; 3892 }; 3893 3894 3895 /* 3896 * RSS toeplitz hash type, as reported in CQE 3897 */ 3898 enum eth_rss_hash_type { 3899 DEFAULT_HASH_TYPE, 3900 IPV4_HASH_TYPE, 3901 TCP_IPV4_HASH_TYPE, 3902 IPV6_HASH_TYPE, 3903 TCP_IPV6_HASH_TYPE, 3904 VLAN_PRI_HASH_TYPE, 3905 E1HOV_PRI_HASH_TYPE, 3906 DSCP_HASH_TYPE, 3907 MAX_ETH_RSS_HASH_TYPE 3908 }; 3909 3910 3911 /* 3912 * Ethernet RSS mode 3913 */ 3914 enum eth_rss_mode { 3915 ETH_RSS_MODE_DISABLED, 3916 ETH_RSS_MODE_REGULAR, 3917 ETH_RSS_MODE_VLAN_PRI, 3918 ETH_RSS_MODE_E1HOV_PRI, 3919 ETH_RSS_MODE_IP_DSCP, 3920 MAX_ETH_RSS_MODE 3921 }; 3922 3923 3924 /* 3925 * parameters for RSS update ramrod (E2) 3926 */ 3927 struct eth_rss_update_ramrod_data { 3928 u8 rss_engine_id; 3929 u8 capabilities; 3930 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1<<0) 3931 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY_SHIFT 0 3932 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1<<1) 3933 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY_SHIFT 1 3934 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1<<2) 3935 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY_SHIFT 2 3936 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<3) 3937 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 3 3938 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<4) 3939 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 4 3940 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<5) 3941 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 5 3942 #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<7) 3943 #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 7 3944 u8 rss_result_mask; 3945 u8 rss_mode; 3946 __le32 __reserved2; 3947 u8 indirection_table[T_ETH_INDIRECTION_TABLE_SIZE]; 3948 __le32 rss_key[T_ETH_RSS_KEY]; 3949 __le32 echo; 3950 __le32 reserved3; 3951 }; 3952 3953 3954 /* 3955 * The eth Rx Buffer Descriptor 3956 */ 3957 struct eth_rx_bd { 3958 __le32 addr_lo; 3959 __le32 addr_hi; 3960 }; 3961 3962 3963 /* 3964 * Eth Rx Cqe structure- general structure for ramrods 3965 */ 3966 struct common_ramrod_eth_rx_cqe { 3967 u8 ramrod_type; 3968 #define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3<<0) 3969 #define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0 3970 #define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<2) 3971 #define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 2 3972 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F<<3) 3973 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 3 3974 u8 conn_type; 3975 __le16 reserved1; 3976 __le32 conn_and_cmd_data; 3977 #define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0) 3978 #define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0 3979 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24) 3980 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24 3981 struct ramrod_data protocol_data; 3982 __le32 echo; 3983 __le32 reserved2[11]; 3984 }; 3985 3986 /* 3987 * Rx Last CQE in page (in ETH) 3988 */ 3989 struct eth_rx_cqe_next_page { 3990 __le32 addr_lo; 3991 __le32 addr_hi; 3992 __le32 reserved[14]; 3993 }; 3994 3995 /* 3996 * union for all eth rx cqe types (fix their sizes) 3997 */ 3998 union eth_rx_cqe { 3999 struct eth_fast_path_rx_cqe fast_path_cqe; 4000 struct common_ramrod_eth_rx_cqe ramrod_cqe; 4001 struct eth_rx_cqe_next_page next_page_cqe; 4002 struct eth_end_agg_rx_cqe end_agg_cqe; 4003 }; 4004 4005 4006 /* 4007 * Values for RX ETH CQE type field 4008 */ 4009 enum eth_rx_cqe_type { 4010 RX_ETH_CQE_TYPE_ETH_FASTPATH, 4011 RX_ETH_CQE_TYPE_ETH_RAMROD, 4012 RX_ETH_CQE_TYPE_ETH_START_AGG, 4013 RX_ETH_CQE_TYPE_ETH_STOP_AGG, 4014 MAX_ETH_RX_CQE_TYPE 4015 }; 4016 4017 4018 /* 4019 * Type of SGL/Raw field in ETH RX fast path CQE 4020 */ 4021 enum eth_rx_fp_sel { 4022 ETH_FP_CQE_REGULAR, 4023 ETH_FP_CQE_RAW, 4024 MAX_ETH_RX_FP_SEL 4025 }; 4026 4027 4028 /* 4029 * The eth Rx SGE Descriptor 4030 */ 4031 struct eth_rx_sge { 4032 __le32 addr_lo; 4033 __le32 addr_hi; 4034 }; 4035 4036 4037 /* 4038 * common data for all protocols 4039 */ 4040 struct spe_hdr { 4041 __le32 conn_and_cmd_data; 4042 #define SPE_HDR_CID (0xFFFFFF<<0) 4043 #define SPE_HDR_CID_SHIFT 0 4044 #define SPE_HDR_CMD_ID (0xFF<<24) 4045 #define SPE_HDR_CMD_ID_SHIFT 24 4046 __le16 type; 4047 #define SPE_HDR_CONN_TYPE (0xFF<<0) 4048 #define SPE_HDR_CONN_TYPE_SHIFT 0 4049 #define SPE_HDR_FUNCTION_ID (0xFF<<8) 4050 #define SPE_HDR_FUNCTION_ID_SHIFT 8 4051 __le16 reserved1; 4052 }; 4053 4054 /* 4055 * specific data for ethernet slow path element 4056 */ 4057 union eth_specific_data { 4058 u8 protocol_data[8]; 4059 struct regpair client_update_ramrod_data; 4060 struct regpair client_init_ramrod_init_data; 4061 struct eth_halt_ramrod_data halt_ramrod_data; 4062 struct regpair update_data_addr; 4063 struct eth_common_ramrod_data common_ramrod_data; 4064 struct regpair classify_cfg_addr; 4065 struct regpair filter_cfg_addr; 4066 struct regpair mcast_cfg_addr; 4067 }; 4068 4069 /* 4070 * Ethernet slow path element 4071 */ 4072 struct eth_spe { 4073 struct spe_hdr hdr; 4074 union eth_specific_data data; 4075 }; 4076 4077 4078 /* 4079 * Ethernet command ID for slow path elements 4080 */ 4081 enum eth_spqe_cmd_id { 4082 RAMROD_CMD_ID_ETH_UNUSED, 4083 RAMROD_CMD_ID_ETH_CLIENT_SETUP, 4084 RAMROD_CMD_ID_ETH_HALT, 4085 RAMROD_CMD_ID_ETH_FORWARD_SETUP, 4086 RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP, 4087 RAMROD_CMD_ID_ETH_CLIENT_UPDATE, 4088 RAMROD_CMD_ID_ETH_EMPTY, 4089 RAMROD_CMD_ID_ETH_TERMINATE, 4090 RAMROD_CMD_ID_ETH_TPA_UPDATE, 4091 RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES, 4092 RAMROD_CMD_ID_ETH_FILTER_RULES, 4093 RAMROD_CMD_ID_ETH_MULTICAST_RULES, 4094 RAMROD_CMD_ID_ETH_RSS_UPDATE, 4095 RAMROD_CMD_ID_ETH_SET_MAC, 4096 MAX_ETH_SPQE_CMD_ID 4097 }; 4098 4099 4100 /* 4101 * eth tpa update command 4102 */ 4103 enum eth_tpa_update_command { 4104 TPA_UPDATE_NONE_COMMAND, 4105 TPA_UPDATE_ENABLE_COMMAND, 4106 TPA_UPDATE_DISABLE_COMMAND, 4107 MAX_ETH_TPA_UPDATE_COMMAND 4108 }; 4109 4110 4111 /* 4112 * Tx regular BD structure 4113 */ 4114 struct eth_tx_bd { 4115 __le32 addr_lo; 4116 __le32 addr_hi; 4117 __le16 total_pkt_bytes; 4118 __le16 nbytes; 4119 u8 reserved[4]; 4120 }; 4121 4122 4123 /* 4124 * structure for easy accessibility to assembler 4125 */ 4126 struct eth_tx_bd_flags { 4127 u8 as_bitfield; 4128 #define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0) 4129 #define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0 4130 #define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1) 4131 #define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1 4132 #define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2) 4133 #define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2 4134 #define ETH_TX_BD_FLAGS_START_BD (0x1<<4) 4135 #define ETH_TX_BD_FLAGS_START_BD_SHIFT 4 4136 #define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5) 4137 #define ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5 4138 #define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6) 4139 #define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6 4140 #define ETH_TX_BD_FLAGS_IPV6 (0x1<<7) 4141 #define ETH_TX_BD_FLAGS_IPV6_SHIFT 7 4142 }; 4143 4144 /* 4145 * The eth Tx Buffer Descriptor 4146 */ 4147 struct eth_tx_start_bd { 4148 __le32 addr_lo; 4149 __le32 addr_hi; 4150 __le16 nbd; 4151 __le16 nbytes; 4152 __le16 vlan_or_ethertype; 4153 struct eth_tx_bd_flags bd_flags; 4154 u8 general_data; 4155 #define ETH_TX_START_BD_HDR_NBDS (0xF<<0) 4156 #define ETH_TX_START_BD_HDR_NBDS_SHIFT 0 4157 #define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4) 4158 #define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4 4159 #define ETH_TX_START_BD_PARSE_NBDS (0x3<<5) 4160 #define ETH_TX_START_BD_PARSE_NBDS_SHIFT 5 4161 #define ETH_TX_START_BD_RESREVED (0x1<<7) 4162 #define ETH_TX_START_BD_RESREVED_SHIFT 7 4163 }; 4164 4165 /* 4166 * Tx parsing BD structure for ETH E1/E1h 4167 */ 4168 struct eth_tx_parse_bd_e1x { 4169 __le16 global_data; 4170 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0) 4171 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0 4172 #define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE (0x3<<4) 4173 #define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE_SHIFT 4 4174 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<6) 4175 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 6 4176 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<7) 4177 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 7 4178 #define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<8) 4179 #define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 8 4180 #define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x7F<<9) 4181 #define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 9 4182 u8 tcp_flags; 4183 #define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0) 4184 #define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0 4185 #define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1) 4186 #define ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1 4187 #define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2) 4188 #define ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2 4189 #define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3) 4190 #define ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3 4191 #define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4) 4192 #define ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4 4193 #define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5) 4194 #define ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5 4195 #define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6) 4196 #define ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6 4197 #define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7) 4198 #define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7 4199 u8 ip_hlen_w; 4200 __le16 total_hlen_w; 4201 __le16 tcp_pseudo_csum; 4202 __le16 lso_mss; 4203 __le16 ip_id; 4204 __le32 tcp_send_seq; 4205 }; 4206 4207 /* 4208 * Tx parsing BD structure for ETH E2 4209 */ 4210 struct eth_tx_parse_bd_e2 { 4211 __le16 dst_mac_addr_lo; 4212 __le16 dst_mac_addr_mid; 4213 __le16 dst_mac_addr_hi; 4214 __le16 src_mac_addr_lo; 4215 __le16 src_mac_addr_mid; 4216 __le16 src_mac_addr_hi; 4217 __le32 parsing_data; 4218 #define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W (0x7FF<<0) 4219 #define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W_SHIFT 0 4220 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<11) 4221 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 11 4222 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<15) 4223 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 15 4224 #define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<16) 4225 #define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 16 4226 #define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE (0x3<<30) 4227 #define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT 30 4228 }; 4229 4230 /* 4231 * The last BD in the BD memory will hold a pointer to the next BD memory 4232 */ 4233 struct eth_tx_next_bd { 4234 __le32 addr_lo; 4235 __le32 addr_hi; 4236 u8 reserved[8]; 4237 }; 4238 4239 /* 4240 * union for 4 Bd types 4241 */ 4242 union eth_tx_bd_types { 4243 struct eth_tx_start_bd start_bd; 4244 struct eth_tx_bd reg_bd; 4245 struct eth_tx_parse_bd_e1x parse_bd_e1x; 4246 struct eth_tx_parse_bd_e2 parse_bd_e2; 4247 struct eth_tx_next_bd next_bd; 4248 }; 4249 4250 /* 4251 * array of 13 bds as appears in the eth xstorm context 4252 */ 4253 struct eth_tx_bds_array { 4254 union eth_tx_bd_types bds[13]; 4255 }; 4256 4257 4258 /* 4259 * VLAN mode on TX BDs 4260 */ 4261 enum eth_tx_vlan_type { 4262 X_ETH_NO_VLAN, 4263 X_ETH_OUTBAND_VLAN, 4264 X_ETH_INBAND_VLAN, 4265 X_ETH_FW_ADDED_VLAN, 4266 MAX_ETH_TX_VLAN_TYPE 4267 }; 4268 4269 4270 /* 4271 * Ethernet VLAN filtering mode in E1x 4272 */ 4273 enum eth_vlan_filter_mode { 4274 ETH_VLAN_FILTER_ANY_VLAN, 4275 ETH_VLAN_FILTER_SPECIFIC_VLAN, 4276 ETH_VLAN_FILTER_CLASSIFY, 4277 MAX_ETH_VLAN_FILTER_MODE 4278 }; 4279 4280 4281 /* 4282 * MAC filtering configuration command header 4283 */ 4284 struct mac_configuration_hdr { 4285 u8 length; 4286 u8 offset; 4287 __le16 client_id; 4288 __le32 echo; 4289 }; 4290 4291 /* 4292 * MAC address in list for ramrod 4293 */ 4294 struct mac_configuration_entry { 4295 __le16 lsb_mac_addr; 4296 __le16 middle_mac_addr; 4297 __le16 msb_mac_addr; 4298 __le16 vlan_id; 4299 u8 pf_id; 4300 u8 flags; 4301 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0) 4302 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0 4303 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1) 4304 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 1 4305 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2) 4306 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 2 4307 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4) 4308 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 4 4309 #define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5) 4310 #define MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 5 4311 #define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6) 4312 #define MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 6 4313 __le16 reserved0; 4314 __le32 clients_bit_vector; 4315 }; 4316 4317 /* 4318 * MAC filtering configuration command 4319 */ 4320 struct mac_configuration_cmd { 4321 struct mac_configuration_hdr hdr; 4322 struct mac_configuration_entry config_table[64]; 4323 }; 4324 4325 4326 /* 4327 * Set-MAC command type (in E1x) 4328 */ 4329 enum set_mac_action_type { 4330 T_ETH_MAC_COMMAND_INVALIDATE, 4331 T_ETH_MAC_COMMAND_SET, 4332 MAX_SET_MAC_ACTION_TYPE 4333 }; 4334 4335 4336 /* 4337 * Ethernet TPA Modes 4338 */ 4339 enum tpa_mode { 4340 TPA_LRO, 4341 TPA_GRO, 4342 MAX_TPA_MODE}; 4343 4344 4345 /* 4346 * tpa update ramrod data 4347 */ 4348 struct tpa_update_ramrod_data { 4349 u8 update_ipv4; 4350 u8 update_ipv6; 4351 u8 client_id; 4352 u8 max_tpa_queues; 4353 u8 max_sges_for_packet; 4354 u8 complete_on_both_clients; 4355 u8 dont_verify_rings_pause_thr_flg; 4356 u8 tpa_mode; 4357 __le16 sge_buff_size; 4358 __le16 max_agg_size; 4359 __le32 sge_page_base_lo; 4360 __le32 sge_page_base_hi; 4361 __le16 sge_pause_thr_low; 4362 __le16 sge_pause_thr_high; 4363 }; 4364 4365 4366 /* 4367 * approximate-match multicast filtering for E1H per function in Tstorm 4368 */ 4369 struct tstorm_eth_approximate_match_multicast_filtering { 4370 u32 mcast_add_hash_bit_array[8]; 4371 }; 4372 4373 4374 /* 4375 * Common configuration parameters per function in Tstorm 4376 */ 4377 struct tstorm_eth_function_common_config { 4378 __le16 config_flags; 4379 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0) 4380 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0 4381 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1) 4382 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1 4383 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2) 4384 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2 4385 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3) 4386 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3 4387 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4) 4388 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4 4389 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<7) 4390 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 7 4391 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0xFF<<8) 4392 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 8 4393 u8 rss_result_mask; 4394 u8 reserved1; 4395 __le16 vlan_id[2]; 4396 }; 4397 4398 4399 /* 4400 * MAC filtering configuration parameters per port in Tstorm 4401 */ 4402 struct tstorm_eth_mac_filter_config { 4403 __le32 ucast_drop_all; 4404 __le32 ucast_accept_all; 4405 __le32 mcast_drop_all; 4406 __le32 mcast_accept_all; 4407 __le32 bcast_accept_all; 4408 __le32 vlan_filter[2]; 4409 __le32 unmatched_unicast; 4410 }; 4411 4412 4413 /* 4414 * tx only queue init ramrod data 4415 */ 4416 struct tx_queue_init_ramrod_data { 4417 struct client_init_general_data general; 4418 struct client_init_tx_data tx; 4419 }; 4420 4421 4422 /* 4423 * Three RX producers for ETH 4424 */ 4425 struct ustorm_eth_rx_producers { 4426 #if defined(__BIG_ENDIAN) 4427 u16 bd_prod; 4428 u16 cqe_prod; 4429 #elif defined(__LITTLE_ENDIAN) 4430 u16 cqe_prod; 4431 u16 bd_prod; 4432 #endif 4433 #if defined(__BIG_ENDIAN) 4434 u16 reserved; 4435 u16 sge_prod; 4436 #elif defined(__LITTLE_ENDIAN) 4437 u16 sge_prod; 4438 u16 reserved; 4439 #endif 4440 }; 4441 4442 4443 /* 4444 * FCoE RX statistics parameters section#0 4445 */ 4446 struct fcoe_rx_stat_params_section0 { 4447 __le32 fcoe_rx_pkt_cnt; 4448 __le32 fcoe_rx_byte_cnt; 4449 }; 4450 4451 4452 /* 4453 * FCoE RX statistics parameters section#1 4454 */ 4455 struct fcoe_rx_stat_params_section1 { 4456 __le32 fcoe_ver_cnt; 4457 __le32 fcoe_rx_drop_pkt_cnt; 4458 }; 4459 4460 4461 /* 4462 * FCoE RX statistics parameters section#2 4463 */ 4464 struct fcoe_rx_stat_params_section2 { 4465 __le32 fc_crc_cnt; 4466 __le32 eofa_del_cnt; 4467 __le32 miss_frame_cnt; 4468 __le32 seq_timeout_cnt; 4469 __le32 drop_seq_cnt; 4470 __le32 fcoe_rx_drop_pkt_cnt; 4471 __le32 fcp_rx_pkt_cnt; 4472 __le32 reserved0; 4473 }; 4474 4475 4476 /* 4477 * FCoE TX statistics parameters 4478 */ 4479 struct fcoe_tx_stat_params { 4480 __le32 fcoe_tx_pkt_cnt; 4481 __le32 fcoe_tx_byte_cnt; 4482 __le32 fcp_tx_pkt_cnt; 4483 __le32 reserved0; 4484 }; 4485 4486 /* 4487 * FCoE statistics parameters 4488 */ 4489 struct fcoe_statistics_params { 4490 struct fcoe_tx_stat_params tx_stat; 4491 struct fcoe_rx_stat_params_section0 rx_stat0; 4492 struct fcoe_rx_stat_params_section1 rx_stat1; 4493 struct fcoe_rx_stat_params_section2 rx_stat2; 4494 }; 4495 4496 4497 /* 4498 * The data afex vif list ramrod need 4499 */ 4500 struct afex_vif_list_ramrod_data { 4501 u8 afex_vif_list_command; 4502 u8 func_bit_map; 4503 __le16 vif_list_index; 4504 u8 func_to_clear; 4505 u8 echo; 4506 __le16 reserved1; 4507 }; 4508 4509 4510 /* 4511 * cfc delete event data 4512 */ 4513 struct cfc_del_event_data { 4514 u32 cid; 4515 u32 reserved0; 4516 u32 reserved1; 4517 }; 4518 4519 4520 /* 4521 * per-port SAFC demo variables 4522 */ 4523 struct cmng_flags_per_port { 4524 u32 cmng_enables; 4525 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0) 4526 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0 4527 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1) 4528 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1 4529 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<2) 4530 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 2 4531 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<3) 4532 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 3 4533 #define __CMNG_FLAGS_PER_PORT_RESERVED0 (0xFFFFFFF<<4) 4534 #define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 4 4535 u32 __reserved1; 4536 }; 4537 4538 4539 /* 4540 * per-port rate shaping variables 4541 */ 4542 struct rate_shaping_vars_per_port { 4543 u32 rs_periodic_timeout; 4544 u32 rs_threshold; 4545 }; 4546 4547 /* 4548 * per-port fairness variables 4549 */ 4550 struct fairness_vars_per_port { 4551 u32 upper_bound; 4552 u32 fair_threshold; 4553 u32 fairness_timeout; 4554 u32 reserved0; 4555 }; 4556 4557 /* 4558 * per-port SAFC variables 4559 */ 4560 struct safc_struct_per_port { 4561 #if defined(__BIG_ENDIAN) 4562 u16 __reserved1; 4563 u8 __reserved0; 4564 u8 safc_timeout_usec; 4565 #elif defined(__LITTLE_ENDIAN) 4566 u8 safc_timeout_usec; 4567 u8 __reserved0; 4568 u16 __reserved1; 4569 #endif 4570 u8 cos_to_traffic_types[MAX_COS_NUMBER]; 4571 u16 cos_to_pause_mask[NUM_OF_SAFC_BITS]; 4572 }; 4573 4574 /* 4575 * Per-port congestion management variables 4576 */ 4577 struct cmng_struct_per_port { 4578 struct rate_shaping_vars_per_port rs_vars; 4579 struct fairness_vars_per_port fair_vars; 4580 struct safc_struct_per_port safc_vars; 4581 struct cmng_flags_per_port flags; 4582 }; 4583 4584 /* 4585 * a single rate shaping counter. can be used as protocol or vnic counter 4586 */ 4587 struct rate_shaping_counter { 4588 u32 quota; 4589 #if defined(__BIG_ENDIAN) 4590 u16 __reserved0; 4591 u16 rate; 4592 #elif defined(__LITTLE_ENDIAN) 4593 u16 rate; 4594 u16 __reserved0; 4595 #endif 4596 }; 4597 4598 /* 4599 * per-vnic rate shaping variables 4600 */ 4601 struct rate_shaping_vars_per_vn { 4602 struct rate_shaping_counter vn_counter; 4603 }; 4604 4605 /* 4606 * per-vnic fairness variables 4607 */ 4608 struct fairness_vars_per_vn { 4609 u32 cos_credit_delta[MAX_COS_NUMBER]; 4610 u32 vn_credit_delta; 4611 u32 __reserved0; 4612 }; 4613 4614 /* 4615 * cmng port init state 4616 */ 4617 struct cmng_vnic { 4618 struct rate_shaping_vars_per_vn vnic_max_rate[4]; 4619 struct fairness_vars_per_vn vnic_min_rate[4]; 4620 }; 4621 4622 /* 4623 * cmng port init state 4624 */ 4625 struct cmng_init { 4626 struct cmng_struct_per_port port; 4627 struct cmng_vnic vnic; 4628 }; 4629 4630 4631 /* 4632 * driver parameters for congestion management init, all rates are in Mbps 4633 */ 4634 struct cmng_init_input { 4635 u32 port_rate; 4636 u16 vnic_min_rate[4]; 4637 u16 vnic_max_rate[4]; 4638 u16 cos_min_rate[MAX_COS_NUMBER]; 4639 u16 cos_to_pause_mask[MAX_COS_NUMBER]; 4640 struct cmng_flags_per_port flags; 4641 }; 4642 4643 4644 /* 4645 * Protocol-common command ID for slow path elements 4646 */ 4647 enum common_spqe_cmd_id { 4648 RAMROD_CMD_ID_COMMON_UNUSED, 4649 RAMROD_CMD_ID_COMMON_FUNCTION_START, 4650 RAMROD_CMD_ID_COMMON_FUNCTION_STOP, 4651 RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE, 4652 RAMROD_CMD_ID_COMMON_CFC_DEL, 4653 RAMROD_CMD_ID_COMMON_CFC_DEL_WB, 4654 RAMROD_CMD_ID_COMMON_STAT_QUERY, 4655 RAMROD_CMD_ID_COMMON_STOP_TRAFFIC, 4656 RAMROD_CMD_ID_COMMON_START_TRAFFIC, 4657 RAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS, 4658 MAX_COMMON_SPQE_CMD_ID 4659 }; 4660 4661 4662 /* 4663 * Per-protocol connection types 4664 */ 4665 enum connection_type { 4666 ETH_CONNECTION_TYPE, 4667 TOE_CONNECTION_TYPE, 4668 RDMA_CONNECTION_TYPE, 4669 ISCSI_CONNECTION_TYPE, 4670 FCOE_CONNECTION_TYPE, 4671 RESERVED_CONNECTION_TYPE_0, 4672 RESERVED_CONNECTION_TYPE_1, 4673 RESERVED_CONNECTION_TYPE_2, 4674 NONE_CONNECTION_TYPE, 4675 MAX_CONNECTION_TYPE 4676 }; 4677 4678 4679 /* 4680 * Cos modes 4681 */ 4682 enum cos_mode { 4683 OVERRIDE_COS, 4684 STATIC_COS, 4685 FW_WRR, 4686 MAX_COS_MODE 4687 }; 4688 4689 4690 /* 4691 * Dynamic HC counters set by the driver 4692 */ 4693 struct hc_dynamic_drv_counter { 4694 u32 val[HC_SB_MAX_DYNAMIC_INDICES]; 4695 }; 4696 4697 /* 4698 * zone A per-queue data 4699 */ 4700 struct cstorm_queue_zone_data { 4701 struct hc_dynamic_drv_counter hc_dyn_drv_cnt; 4702 struct regpair reserved[2]; 4703 }; 4704 4705 4706 /* 4707 * Vf-PF channel data in cstorm ram (non-triggered zone) 4708 */ 4709 struct vf_pf_channel_zone_data { 4710 u32 msg_addr_lo; 4711 u32 msg_addr_hi; 4712 }; 4713 4714 /* 4715 * zone for VF non-triggered data 4716 */ 4717 struct non_trigger_vf_zone { 4718 struct vf_pf_channel_zone_data vf_pf_channel; 4719 }; 4720 4721 /* 4722 * Vf-PF channel trigger zone in cstorm ram 4723 */ 4724 struct vf_pf_channel_zone_trigger { 4725 u8 addr_valid; 4726 }; 4727 4728 /* 4729 * zone that triggers the in-bound interrupt 4730 */ 4731 struct trigger_vf_zone { 4732 #if defined(__BIG_ENDIAN) 4733 u16 reserved1; 4734 u8 reserved0; 4735 struct vf_pf_channel_zone_trigger vf_pf_channel; 4736 #elif defined(__LITTLE_ENDIAN) 4737 struct vf_pf_channel_zone_trigger vf_pf_channel; 4738 u8 reserved0; 4739 u16 reserved1; 4740 #endif 4741 u32 reserved2; 4742 }; 4743 4744 /* 4745 * zone B per-VF data 4746 */ 4747 struct cstorm_vf_zone_data { 4748 struct non_trigger_vf_zone non_trigger; 4749 struct trigger_vf_zone trigger; 4750 }; 4751 4752 4753 /* 4754 * Dynamic host coalescing init parameters, per state machine 4755 */ 4756 struct dynamic_hc_sm_config { 4757 u32 threshold[3]; 4758 u8 shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES]; 4759 u8 hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES]; 4760 u8 hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES]; 4761 u8 hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES]; 4762 u8 hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES]; 4763 }; 4764 4765 /* 4766 * Dynamic host coalescing init parameters 4767 */ 4768 struct dynamic_hc_config { 4769 struct dynamic_hc_sm_config sm_config[HC_SB_MAX_SM]; 4770 }; 4771 4772 4773 struct e2_integ_data { 4774 #if defined(__BIG_ENDIAN) 4775 u8 flags; 4776 #define E2_INTEG_DATA_TESTING_EN (0x1<<0) 4777 #define E2_INTEG_DATA_TESTING_EN_SHIFT 0 4778 #define E2_INTEG_DATA_LB_TX (0x1<<1) 4779 #define E2_INTEG_DATA_LB_TX_SHIFT 1 4780 #define E2_INTEG_DATA_COS_TX (0x1<<2) 4781 #define E2_INTEG_DATA_COS_TX_SHIFT 2 4782 #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) 4783 #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3 4784 #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) 4785 #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4 4786 #define E2_INTEG_DATA_RESERVED (0x7<<5) 4787 #define E2_INTEG_DATA_RESERVED_SHIFT 5 4788 u8 cos; 4789 u8 voq; 4790 u8 pbf_queue; 4791 #elif defined(__LITTLE_ENDIAN) 4792 u8 pbf_queue; 4793 u8 voq; 4794 u8 cos; 4795 u8 flags; 4796 #define E2_INTEG_DATA_TESTING_EN (0x1<<0) 4797 #define E2_INTEG_DATA_TESTING_EN_SHIFT 0 4798 #define E2_INTEG_DATA_LB_TX (0x1<<1) 4799 #define E2_INTEG_DATA_LB_TX_SHIFT 1 4800 #define E2_INTEG_DATA_COS_TX (0x1<<2) 4801 #define E2_INTEG_DATA_COS_TX_SHIFT 2 4802 #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) 4803 #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3 4804 #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) 4805 #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4 4806 #define E2_INTEG_DATA_RESERVED (0x7<<5) 4807 #define E2_INTEG_DATA_RESERVED_SHIFT 5 4808 #endif 4809 #if defined(__BIG_ENDIAN) 4810 u16 reserved3; 4811 u8 reserved2; 4812 u8 ramEn; 4813 #elif defined(__LITTLE_ENDIAN) 4814 u8 ramEn; 4815 u8 reserved2; 4816 u16 reserved3; 4817 #endif 4818 }; 4819 4820 4821 /* 4822 * set mac event data 4823 */ 4824 struct eth_event_data { 4825 u32 echo; 4826 u32 reserved0; 4827 u32 reserved1; 4828 }; 4829 4830 4831 /* 4832 * pf-vf event data 4833 */ 4834 struct vf_pf_event_data { 4835 u8 vf_id; 4836 u8 reserved0; 4837 u16 reserved1; 4838 u32 msg_addr_lo; 4839 u32 msg_addr_hi; 4840 }; 4841 4842 /* 4843 * VF FLR event data 4844 */ 4845 struct vf_flr_event_data { 4846 u8 vf_id; 4847 u8 reserved0; 4848 u16 reserved1; 4849 u32 reserved2; 4850 u32 reserved3; 4851 }; 4852 4853 /* 4854 * malicious VF event data 4855 */ 4856 struct malicious_vf_event_data { 4857 u8 vf_id; 4858 u8 reserved0; 4859 u16 reserved1; 4860 u32 reserved2; 4861 u32 reserved3; 4862 }; 4863 4864 /* 4865 * vif list event data 4866 */ 4867 struct vif_list_event_data { 4868 u8 func_bit_map; 4869 u8 echo; 4870 __le16 reserved0; 4871 __le32 reserved1; 4872 __le32 reserved2; 4873 }; 4874 4875 /* function update event data */ 4876 struct function_update_event_data { 4877 u8 echo; 4878 u8 reserved; 4879 __le16 reserved0; 4880 __le32 reserved1; 4881 __le32 reserved2; 4882 }; 4883 4884 4885 /* union for all event ring message types */ 4886 union event_data { 4887 struct vf_pf_event_data vf_pf_event; 4888 struct eth_event_data eth_event; 4889 struct cfc_del_event_data cfc_del_event; 4890 struct vf_flr_event_data vf_flr_event; 4891 struct malicious_vf_event_data malicious_vf_event; 4892 struct vif_list_event_data vif_list_event; 4893 struct function_update_event_data function_update_event; 4894 }; 4895 4896 4897 /* 4898 * per PF event ring data 4899 */ 4900 struct event_ring_data { 4901 struct regpair base_addr; 4902 #if defined(__BIG_ENDIAN) 4903 u8 index_id; 4904 u8 sb_id; 4905 u16 producer; 4906 #elif defined(__LITTLE_ENDIAN) 4907 u16 producer; 4908 u8 sb_id; 4909 u8 index_id; 4910 #endif 4911 u32 reserved0; 4912 }; 4913 4914 4915 /* 4916 * event ring message element (each element is 128 bits) 4917 */ 4918 struct event_ring_msg { 4919 u8 opcode; 4920 u8 error; 4921 u16 reserved1; 4922 union event_data data; 4923 }; 4924 4925 /* 4926 * event ring next page element (128 bits) 4927 */ 4928 struct event_ring_next { 4929 struct regpair addr; 4930 u32 reserved[2]; 4931 }; 4932 4933 /* 4934 * union for event ring element types (each element is 128 bits) 4935 */ 4936 union event_ring_elem { 4937 struct event_ring_msg message; 4938 struct event_ring_next next_page; 4939 }; 4940 4941 4942 /* 4943 * Common event ring opcodes 4944 */ 4945 enum event_ring_opcode { 4946 EVENT_RING_OPCODE_VF_PF_CHANNEL, 4947 EVENT_RING_OPCODE_FUNCTION_START, 4948 EVENT_RING_OPCODE_FUNCTION_STOP, 4949 EVENT_RING_OPCODE_CFC_DEL, 4950 EVENT_RING_OPCODE_CFC_DEL_WB, 4951 EVENT_RING_OPCODE_STAT_QUERY, 4952 EVENT_RING_OPCODE_STOP_TRAFFIC, 4953 EVENT_RING_OPCODE_START_TRAFFIC, 4954 EVENT_RING_OPCODE_VF_FLR, 4955 EVENT_RING_OPCODE_MALICIOUS_VF, 4956 EVENT_RING_OPCODE_FORWARD_SETUP, 4957 EVENT_RING_OPCODE_RSS_UPDATE_RULES, 4958 EVENT_RING_OPCODE_FUNCTION_UPDATE, 4959 EVENT_RING_OPCODE_AFEX_VIF_LISTS, 4960 EVENT_RING_OPCODE_SET_MAC, 4961 EVENT_RING_OPCODE_CLASSIFICATION_RULES, 4962 EVENT_RING_OPCODE_FILTERS_RULES, 4963 EVENT_RING_OPCODE_MULTICAST_RULES, 4964 MAX_EVENT_RING_OPCODE 4965 }; 4966 4967 4968 /* 4969 * Modes for fairness algorithm 4970 */ 4971 enum fairness_mode { 4972 FAIRNESS_COS_WRR_MODE, 4973 FAIRNESS_COS_ETS_MODE, 4974 MAX_FAIRNESS_MODE 4975 }; 4976 4977 4978 /* 4979 * Priority and cos 4980 */ 4981 struct priority_cos { 4982 u8 priority; 4983 u8 cos; 4984 __le16 reserved1; 4985 }; 4986 4987 /* 4988 * The data for flow control configuration 4989 */ 4990 struct flow_control_configuration { 4991 struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES]; 4992 u8 dcb_enabled; 4993 u8 dcb_version; 4994 u8 dont_add_pri_0_en; 4995 u8 reserved1; 4996 __le32 reserved2; 4997 }; 4998 4999 5000 /* 5001 * 5002 */ 5003 struct function_start_data { 5004 u8 function_mode; 5005 u8 reserved; 5006 __le16 sd_vlan_tag; 5007 __le16 vif_id; 5008 u8 path_id; 5009 u8 network_cos_mode; 5010 }; 5011 5012 5013 struct function_update_data { 5014 u8 vif_id_change_flg; 5015 u8 afex_default_vlan_change_flg; 5016 u8 allowed_priorities_change_flg; 5017 u8 network_cos_mode_change_flg; 5018 __le16 vif_id; 5019 __le16 afex_default_vlan; 5020 u8 allowed_priorities; 5021 u8 network_cos_mode; 5022 u8 lb_mode_en; 5023 u8 tx_switch_suspend_change_flg; 5024 u8 tx_switch_suspend; 5025 u8 echo; 5026 __le16 reserved1; 5027 }; 5028 5029 5030 /* 5031 * FW version stored in the Xstorm RAM 5032 */ 5033 struct fw_version { 5034 #if defined(__BIG_ENDIAN) 5035 u8 engineering; 5036 u8 revision; 5037 u8 minor; 5038 u8 major; 5039 #elif defined(__LITTLE_ENDIAN) 5040 u8 major; 5041 u8 minor; 5042 u8 revision; 5043 u8 engineering; 5044 #endif 5045 u32 flags; 5046 #define FW_VERSION_OPTIMIZED (0x1<<0) 5047 #define FW_VERSION_OPTIMIZED_SHIFT 0 5048 #define FW_VERSION_BIG_ENDIEN (0x1<<1) 5049 #define FW_VERSION_BIG_ENDIEN_SHIFT 1 5050 #define FW_VERSION_CHIP_VERSION (0x3<<2) 5051 #define FW_VERSION_CHIP_VERSION_SHIFT 2 5052 #define __FW_VERSION_RESERVED (0xFFFFFFF<<4) 5053 #define __FW_VERSION_RESERVED_SHIFT 4 5054 }; 5055 5056 5057 /* 5058 * Dynamic Host-Coalescing - Driver(host) counters 5059 */ 5060 struct hc_dynamic_sb_drv_counters { 5061 u32 dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES]; 5062 }; 5063 5064 5065 /* 5066 * 2 bytes. configuration/state parameters for a single protocol index 5067 */ 5068 struct hc_index_data { 5069 #if defined(__BIG_ENDIAN) 5070 u8 flags; 5071 #define HC_INDEX_DATA_SM_ID (0x1<<0) 5072 #define HC_INDEX_DATA_SM_ID_SHIFT 0 5073 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1) 5074 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1 5075 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) 5076 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2 5077 #define HC_INDEX_DATA_RESERVE (0x1F<<3) 5078 #define HC_INDEX_DATA_RESERVE_SHIFT 3 5079 u8 timeout; 5080 #elif defined(__LITTLE_ENDIAN) 5081 u8 timeout; 5082 u8 flags; 5083 #define HC_INDEX_DATA_SM_ID (0x1<<0) 5084 #define HC_INDEX_DATA_SM_ID_SHIFT 0 5085 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1) 5086 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1 5087 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) 5088 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2 5089 #define HC_INDEX_DATA_RESERVE (0x1F<<3) 5090 #define HC_INDEX_DATA_RESERVE_SHIFT 3 5091 #endif 5092 }; 5093 5094 5095 /* 5096 * HC state-machine 5097 */ 5098 struct hc_status_block_sm { 5099 #if defined(__BIG_ENDIAN) 5100 u8 igu_seg_id; 5101 u8 igu_sb_id; 5102 u8 timer_value; 5103 u8 __flags; 5104 #elif defined(__LITTLE_ENDIAN) 5105 u8 __flags; 5106 u8 timer_value; 5107 u8 igu_sb_id; 5108 u8 igu_seg_id; 5109 #endif 5110 u32 time_to_expire; 5111 }; 5112 5113 /* 5114 * hold PCI identification variables- used in various places in firmware 5115 */ 5116 struct pci_entity { 5117 #if defined(__BIG_ENDIAN) 5118 u8 vf_valid; 5119 u8 vf_id; 5120 u8 vnic_id; 5121 u8 pf_id; 5122 #elif defined(__LITTLE_ENDIAN) 5123 u8 pf_id; 5124 u8 vnic_id; 5125 u8 vf_id; 5126 u8 vf_valid; 5127 #endif 5128 }; 5129 5130 /* 5131 * The fast-path status block meta-data, common to all chips 5132 */ 5133 struct hc_sb_data { 5134 struct regpair host_sb_addr; 5135 struct hc_status_block_sm state_machine[HC_SB_MAX_SM]; 5136 struct pci_entity p_func; 5137 #if defined(__BIG_ENDIAN) 5138 u8 rsrv0; 5139 u8 state; 5140 u8 dhc_qzone_id; 5141 u8 same_igu_sb_1b; 5142 #elif defined(__LITTLE_ENDIAN) 5143 u8 same_igu_sb_1b; 5144 u8 dhc_qzone_id; 5145 u8 state; 5146 u8 rsrv0; 5147 #endif 5148 struct regpair rsrv1[2]; 5149 }; 5150 5151 5152 /* 5153 * Segment types for host coaslescing 5154 */ 5155 enum hc_segment { 5156 HC_REGULAR_SEGMENT, 5157 HC_DEFAULT_SEGMENT, 5158 MAX_HC_SEGMENT 5159 }; 5160 5161 5162 /* 5163 * The fast-path status block meta-data 5164 */ 5165 struct hc_sp_status_block_data { 5166 struct regpair host_sb_addr; 5167 #if defined(__BIG_ENDIAN) 5168 u8 rsrv1; 5169 u8 state; 5170 u8 igu_seg_id; 5171 u8 igu_sb_id; 5172 #elif defined(__LITTLE_ENDIAN) 5173 u8 igu_sb_id; 5174 u8 igu_seg_id; 5175 u8 state; 5176 u8 rsrv1; 5177 #endif 5178 struct pci_entity p_func; 5179 }; 5180 5181 5182 /* 5183 * The fast-path status block meta-data 5184 */ 5185 struct hc_status_block_data_e1x { 5186 struct hc_index_data index_data[HC_SB_MAX_INDICES_E1X]; 5187 struct hc_sb_data common; 5188 }; 5189 5190 5191 /* 5192 * The fast-path status block meta-data 5193 */ 5194 struct hc_status_block_data_e2 { 5195 struct hc_index_data index_data[HC_SB_MAX_INDICES_E2]; 5196 struct hc_sb_data common; 5197 }; 5198 5199 5200 /* 5201 * IGU block operartion modes (in Everest2) 5202 */ 5203 enum igu_mode { 5204 HC_IGU_BC_MODE, 5205 HC_IGU_NBC_MODE, 5206 MAX_IGU_MODE 5207 }; 5208 5209 5210 /* 5211 * IP versions 5212 */ 5213 enum ip_ver { 5214 IP_V4, 5215 IP_V6, 5216 MAX_IP_VER 5217 }; 5218 5219 5220 /* 5221 * Multi-function modes 5222 */ 5223 enum mf_mode { 5224 SINGLE_FUNCTION, 5225 MULTI_FUNCTION_SD, 5226 MULTI_FUNCTION_SI, 5227 MULTI_FUNCTION_AFEX, 5228 MAX_MF_MODE 5229 }; 5230 5231 /* 5232 * Protocol-common statistics collected by the Tstorm (per pf) 5233 */ 5234 struct tstorm_per_pf_stats { 5235 struct regpair rcv_error_bytes; 5236 }; 5237 5238 /* 5239 * 5240 */ 5241 struct per_pf_stats { 5242 struct tstorm_per_pf_stats tstorm_pf_statistics; 5243 }; 5244 5245 5246 /* 5247 * Protocol-common statistics collected by the Tstorm (per port) 5248 */ 5249 struct tstorm_per_port_stats { 5250 __le32 mac_discard; 5251 __le32 mac_filter_discard; 5252 __le32 brb_truncate_discard; 5253 __le32 mf_tag_discard; 5254 __le32 packet_drop; 5255 __le32 reserved; 5256 }; 5257 5258 /* 5259 * 5260 */ 5261 struct per_port_stats { 5262 struct tstorm_per_port_stats tstorm_port_statistics; 5263 }; 5264 5265 5266 /* 5267 * Protocol-common statistics collected by the Tstorm (per client) 5268 */ 5269 struct tstorm_per_queue_stats { 5270 struct regpair rcv_ucast_bytes; 5271 __le32 rcv_ucast_pkts; 5272 __le32 checksum_discard; 5273 struct regpair rcv_bcast_bytes; 5274 __le32 rcv_bcast_pkts; 5275 __le32 pkts_too_big_discard; 5276 struct regpair rcv_mcast_bytes; 5277 __le32 rcv_mcast_pkts; 5278 __le32 ttl0_discard; 5279 __le16 no_buff_discard; 5280 __le16 reserved0; 5281 __le32 reserved1; 5282 }; 5283 5284 /* 5285 * Protocol-common statistics collected by the Ustorm (per client) 5286 */ 5287 struct ustorm_per_queue_stats { 5288 struct regpair ucast_no_buff_bytes; 5289 struct regpair mcast_no_buff_bytes; 5290 struct regpair bcast_no_buff_bytes; 5291 __le32 ucast_no_buff_pkts; 5292 __le32 mcast_no_buff_pkts; 5293 __le32 bcast_no_buff_pkts; 5294 __le32 coalesced_pkts; 5295 struct regpair coalesced_bytes; 5296 __le32 coalesced_events; 5297 __le32 coalesced_aborts; 5298 }; 5299 5300 /* 5301 * Protocol-common statistics collected by the Xstorm (per client) 5302 */ 5303 struct xstorm_per_queue_stats { 5304 struct regpair ucast_bytes_sent; 5305 struct regpair mcast_bytes_sent; 5306 struct regpair bcast_bytes_sent; 5307 __le32 ucast_pkts_sent; 5308 __le32 mcast_pkts_sent; 5309 __le32 bcast_pkts_sent; 5310 __le32 error_drop_pkts; 5311 }; 5312 5313 /* 5314 * 5315 */ 5316 struct per_queue_stats { 5317 struct tstorm_per_queue_stats tstorm_queue_statistics; 5318 struct ustorm_per_queue_stats ustorm_queue_statistics; 5319 struct xstorm_per_queue_stats xstorm_queue_statistics; 5320 }; 5321 5322 5323 /* 5324 * FW version stored in first line of pram 5325 */ 5326 struct pram_fw_version { 5327 u8 major; 5328 u8 minor; 5329 u8 revision; 5330 u8 engineering; 5331 u8 flags; 5332 #define PRAM_FW_VERSION_OPTIMIZED (0x1<<0) 5333 #define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0 5334 #define PRAM_FW_VERSION_STORM_ID (0x3<<1) 5335 #define PRAM_FW_VERSION_STORM_ID_SHIFT 1 5336 #define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3) 5337 #define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3 5338 #define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4) 5339 #define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4 5340 #define __PRAM_FW_VERSION_RESERVED0 (0x3<<6) 5341 #define __PRAM_FW_VERSION_RESERVED0_SHIFT 6 5342 }; 5343 5344 5345 /* 5346 * Ethernet slow path element 5347 */ 5348 union protocol_common_specific_data { 5349 u8 protocol_data[8]; 5350 struct regpair phy_address; 5351 struct regpair mac_config_addr; 5352 struct afex_vif_list_ramrod_data afex_vif_list_data; 5353 }; 5354 5355 /* 5356 * The send queue element 5357 */ 5358 struct protocol_common_spe { 5359 struct spe_hdr hdr; 5360 union protocol_common_specific_data data; 5361 }; 5362 5363 5364 /* 5365 * The send queue element 5366 */ 5367 struct slow_path_element { 5368 struct spe_hdr hdr; 5369 struct regpair protocol_data; 5370 }; 5371 5372 5373 /* 5374 * Protocol-common statistics counter 5375 */ 5376 struct stats_counter { 5377 __le16 xstats_counter; 5378 __le16 reserved0; 5379 __le32 reserved1; 5380 __le16 tstats_counter; 5381 __le16 reserved2; 5382 __le32 reserved3; 5383 __le16 ustats_counter; 5384 __le16 reserved4; 5385 __le32 reserved5; 5386 __le16 cstats_counter; 5387 __le16 reserved6; 5388 __le32 reserved7; 5389 }; 5390 5391 5392 /* 5393 * 5394 */ 5395 struct stats_query_entry { 5396 u8 kind; 5397 u8 index; 5398 __le16 funcID; 5399 __le32 reserved; 5400 struct regpair address; 5401 }; 5402 5403 /* 5404 * statistic command 5405 */ 5406 struct stats_query_cmd_group { 5407 struct stats_query_entry query[STATS_QUERY_CMD_COUNT]; 5408 }; 5409 5410 5411 /* 5412 * statistic command header 5413 */ 5414 struct stats_query_header { 5415 u8 cmd_num; 5416 u8 reserved0; 5417 __le16 drv_stats_counter; 5418 __le32 reserved1; 5419 struct regpair stats_counters_addrs; 5420 }; 5421 5422 5423 /* 5424 * Types of statistcis query entry 5425 */ 5426 enum stats_query_type { 5427 STATS_TYPE_QUEUE, 5428 STATS_TYPE_PORT, 5429 STATS_TYPE_PF, 5430 STATS_TYPE_TOE, 5431 STATS_TYPE_FCOE, 5432 MAX_STATS_QUERY_TYPE 5433 }; 5434 5435 5436 /* 5437 * Indicate of the function status block state 5438 */ 5439 enum status_block_state { 5440 SB_DISABLED, 5441 SB_ENABLED, 5442 SB_CLEANED, 5443 MAX_STATUS_BLOCK_STATE 5444 }; 5445 5446 5447 /* 5448 * Storm IDs (including attentions for IGU related enums) 5449 */ 5450 enum storm_id { 5451 USTORM_ID, 5452 CSTORM_ID, 5453 XSTORM_ID, 5454 TSTORM_ID, 5455 ATTENTION_ID, 5456 MAX_STORM_ID 5457 }; 5458 5459 5460 /* 5461 * Taffic types used in ETS and flow control algorithms 5462 */ 5463 enum traffic_type { 5464 LLFC_TRAFFIC_TYPE_NW, 5465 LLFC_TRAFFIC_TYPE_FCOE, 5466 LLFC_TRAFFIC_TYPE_ISCSI, 5467 MAX_TRAFFIC_TYPE 5468 }; 5469 5470 5471 /* 5472 * zone A per-queue data 5473 */ 5474 struct tstorm_queue_zone_data { 5475 struct regpair reserved[4]; 5476 }; 5477 5478 5479 /* 5480 * zone B per-VF data 5481 */ 5482 struct tstorm_vf_zone_data { 5483 struct regpair reserved; 5484 }; 5485 5486 5487 /* 5488 * zone A per-queue data 5489 */ 5490 struct ustorm_queue_zone_data { 5491 struct ustorm_eth_rx_producers eth_rx_producers; 5492 struct regpair reserved[3]; 5493 }; 5494 5495 5496 /* 5497 * zone B per-VF data 5498 */ 5499 struct ustorm_vf_zone_data { 5500 struct regpair reserved; 5501 }; 5502 5503 5504 /* 5505 * data per VF-PF channel 5506 */ 5507 struct vf_pf_channel_data { 5508 #if defined(__BIG_ENDIAN) 5509 u16 reserved0; 5510 u8 valid; 5511 u8 state; 5512 #elif defined(__LITTLE_ENDIAN) 5513 u8 state; 5514 u8 valid; 5515 u16 reserved0; 5516 #endif 5517 u32 reserved1; 5518 }; 5519 5520 5521 /* 5522 * State of VF-PF channel 5523 */ 5524 enum vf_pf_channel_state { 5525 VF_PF_CHANNEL_STATE_READY, 5526 VF_PF_CHANNEL_STATE_WAITING_FOR_ACK, 5527 MAX_VF_PF_CHANNEL_STATE 5528 }; 5529 5530 5531 /* 5532 * vif_list_rule_kind 5533 */ 5534 enum vif_list_rule_kind { 5535 VIF_LIST_RULE_SET, 5536 VIF_LIST_RULE_GET, 5537 VIF_LIST_RULE_CLEAR_ALL, 5538 VIF_LIST_RULE_CLEAR_FUNC, 5539 MAX_VIF_LIST_RULE_KIND 5540 }; 5541 5542 5543 /* 5544 * zone A per-queue data 5545 */ 5546 struct xstorm_queue_zone_data { 5547 struct regpair reserved[4]; 5548 }; 5549 5550 5551 /* 5552 * zone B per-VF data 5553 */ 5554 struct xstorm_vf_zone_data { 5555 struct regpair reserved; 5556 }; 5557 5558 #endif /* BNX2X_HSI_H */ 5559