1 /* bnx2x_hsi.h: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2011 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 */ 9 #ifndef BNX2X_HSI_H 10 #define BNX2X_HSI_H 11 12 #include "bnx2x_fw_defs.h" 13 14 #define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e 15 16 struct license_key { 17 u32 reserved[6]; 18 19 u32 max_iscsi_conn; 20 #define BNX2X_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF 21 #define BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT 0 22 #define BNX2X_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000 23 #define BNX2X_MAX_ISCSI_INIT_CONN_SHIFT 16 24 25 u32 reserved_a; 26 27 u32 max_fcoe_conn; 28 #define BNX2X_MAX_FCOE_TRGT_CONN_MASK 0xFFFF 29 #define BNX2X_MAX_FCOE_TRGT_CONN_SHIFT 0 30 #define BNX2X_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000 31 #define BNX2X_MAX_FCOE_INIT_CONN_SHIFT 16 32 33 u32 reserved_b[4]; 34 }; 35 36 37 #define PORT_0 0 38 #define PORT_1 1 39 #define PORT_MAX 2 40 41 /**************************************************************************** 42 * Shared HW configuration * 43 ****************************************************************************/ 44 #define PIN_CFG_NA 0x00000000 45 #define PIN_CFG_GPIO0_P0 0x00000001 46 #define PIN_CFG_GPIO1_P0 0x00000002 47 #define PIN_CFG_GPIO2_P0 0x00000003 48 #define PIN_CFG_GPIO3_P0 0x00000004 49 #define PIN_CFG_GPIO0_P1 0x00000005 50 #define PIN_CFG_GPIO1_P1 0x00000006 51 #define PIN_CFG_GPIO2_P1 0x00000007 52 #define PIN_CFG_GPIO3_P1 0x00000008 53 #define PIN_CFG_EPIO0 0x00000009 54 #define PIN_CFG_EPIO1 0x0000000a 55 #define PIN_CFG_EPIO2 0x0000000b 56 #define PIN_CFG_EPIO3 0x0000000c 57 #define PIN_CFG_EPIO4 0x0000000d 58 #define PIN_CFG_EPIO5 0x0000000e 59 #define PIN_CFG_EPIO6 0x0000000f 60 #define PIN_CFG_EPIO7 0x00000010 61 #define PIN_CFG_EPIO8 0x00000011 62 #define PIN_CFG_EPIO9 0x00000012 63 #define PIN_CFG_EPIO10 0x00000013 64 #define PIN_CFG_EPIO11 0x00000014 65 #define PIN_CFG_EPIO12 0x00000015 66 #define PIN_CFG_EPIO13 0x00000016 67 #define PIN_CFG_EPIO14 0x00000017 68 #define PIN_CFG_EPIO15 0x00000018 69 #define PIN_CFG_EPIO16 0x00000019 70 #define PIN_CFG_EPIO17 0x0000001a 71 #define PIN_CFG_EPIO18 0x0000001b 72 #define PIN_CFG_EPIO19 0x0000001c 73 #define PIN_CFG_EPIO20 0x0000001d 74 #define PIN_CFG_EPIO21 0x0000001e 75 #define PIN_CFG_EPIO22 0x0000001f 76 #define PIN_CFG_EPIO23 0x00000020 77 #define PIN_CFG_EPIO24 0x00000021 78 #define PIN_CFG_EPIO25 0x00000022 79 #define PIN_CFG_EPIO26 0x00000023 80 #define PIN_CFG_EPIO27 0x00000024 81 #define PIN_CFG_EPIO28 0x00000025 82 #define PIN_CFG_EPIO29 0x00000026 83 #define PIN_CFG_EPIO30 0x00000027 84 #define PIN_CFG_EPIO31 0x00000028 85 86 /* EPIO definition */ 87 #define EPIO_CFG_NA 0x00000000 88 #define EPIO_CFG_EPIO0 0x00000001 89 #define EPIO_CFG_EPIO1 0x00000002 90 #define EPIO_CFG_EPIO2 0x00000003 91 #define EPIO_CFG_EPIO3 0x00000004 92 #define EPIO_CFG_EPIO4 0x00000005 93 #define EPIO_CFG_EPIO5 0x00000006 94 #define EPIO_CFG_EPIO6 0x00000007 95 #define EPIO_CFG_EPIO7 0x00000008 96 #define EPIO_CFG_EPIO8 0x00000009 97 #define EPIO_CFG_EPIO9 0x0000000a 98 #define EPIO_CFG_EPIO10 0x0000000b 99 #define EPIO_CFG_EPIO11 0x0000000c 100 #define EPIO_CFG_EPIO12 0x0000000d 101 #define EPIO_CFG_EPIO13 0x0000000e 102 #define EPIO_CFG_EPIO14 0x0000000f 103 #define EPIO_CFG_EPIO15 0x00000010 104 #define EPIO_CFG_EPIO16 0x00000011 105 #define EPIO_CFG_EPIO17 0x00000012 106 #define EPIO_CFG_EPIO18 0x00000013 107 #define EPIO_CFG_EPIO19 0x00000014 108 #define EPIO_CFG_EPIO20 0x00000015 109 #define EPIO_CFG_EPIO21 0x00000016 110 #define EPIO_CFG_EPIO22 0x00000017 111 #define EPIO_CFG_EPIO23 0x00000018 112 #define EPIO_CFG_EPIO24 0x00000019 113 #define EPIO_CFG_EPIO25 0x0000001a 114 #define EPIO_CFG_EPIO26 0x0000001b 115 #define EPIO_CFG_EPIO27 0x0000001c 116 #define EPIO_CFG_EPIO28 0x0000001d 117 #define EPIO_CFG_EPIO29 0x0000001e 118 #define EPIO_CFG_EPIO30 0x0000001f 119 #define EPIO_CFG_EPIO31 0x00000020 120 121 122 struct shared_hw_cfg { /* NVRAM Offset */ 123 /* Up to 16 bytes of NULL-terminated string */ 124 u8 part_num[16]; /* 0x104 */ 125 126 u32 config; /* 0x114 */ 127 #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001 128 #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0 129 #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000 130 #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001 131 #define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN 0x00000002 132 133 #define SHARED_HW_CFG_PORT_SWAP 0x00000004 134 135 #define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008 136 137 #define SHARED_HW_CFG_PCIE_GEN3_DISABLED 0x00000000 138 #define SHARED_HW_CFG_PCIE_GEN3_ENABLED 0x00000010 139 140 #define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700 141 #define SHARED_HW_CFG_MFW_SELECT_SHIFT 8 142 /* Whatever MFW found in NVM 143 (if multiple found, priority order is: NC-SI, UMP, IPMI) */ 144 #define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000 145 #define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100 146 #define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200 147 #define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300 148 /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI 149 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 150 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400 151 /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI 152 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 153 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500 154 /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP 155 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 156 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600 157 158 #define SHARED_HW_CFG_LED_MODE_MASK 0x000f0000 159 #define SHARED_HW_CFG_LED_MODE_SHIFT 16 160 #define SHARED_HW_CFG_LED_MAC1 0x00000000 161 #define SHARED_HW_CFG_LED_PHY1 0x00010000 162 #define SHARED_HW_CFG_LED_PHY2 0x00020000 163 #define SHARED_HW_CFG_LED_PHY3 0x00030000 164 #define SHARED_HW_CFG_LED_MAC2 0x00040000 165 #define SHARED_HW_CFG_LED_PHY4 0x00050000 166 #define SHARED_HW_CFG_LED_PHY5 0x00060000 167 #define SHARED_HW_CFG_LED_PHY6 0x00070000 168 #define SHARED_HW_CFG_LED_MAC3 0x00080000 169 #define SHARED_HW_CFG_LED_PHY7 0x00090000 170 #define SHARED_HW_CFG_LED_PHY9 0x000a0000 171 #define SHARED_HW_CFG_LED_PHY11 0x000b0000 172 #define SHARED_HW_CFG_LED_MAC4 0x000c0000 173 #define SHARED_HW_CFG_LED_PHY8 0x000d0000 174 #define SHARED_HW_CFG_LED_EXTPHY1 0x000e0000 175 176 177 #define SHARED_HW_CFG_AN_ENABLE_MASK 0x3f000000 178 #define SHARED_HW_CFG_AN_ENABLE_SHIFT 24 179 #define SHARED_HW_CFG_AN_ENABLE_CL37 0x01000000 180 #define SHARED_HW_CFG_AN_ENABLE_CL73 0x02000000 181 #define SHARED_HW_CFG_AN_ENABLE_BAM 0x04000000 182 #define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 0x08000000 183 #define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 0x10000000 184 #define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 0x20000000 185 186 #define SHARED_HW_CFG_SRIOV_MASK 0x40000000 187 #define SHARED_HW_CFG_SRIOV_DISABLED 0x00000000 188 #define SHARED_HW_CFG_SRIOV_ENABLED 0x40000000 189 190 #define SHARED_HW_CFG_ATC_MASK 0x80000000 191 #define SHARED_HW_CFG_ATC_DISABLED 0x00000000 192 #define SHARED_HW_CFG_ATC_ENABLED 0x80000000 193 194 u32 config2; /* 0x118 */ 195 /* one time auto detect grace period (in sec) */ 196 #define SHARED_HW_CFG_GRACE_PERIOD_MASK 0x000000ff 197 #define SHARED_HW_CFG_GRACE_PERIOD_SHIFT 0 198 199 #define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100 200 #define SHARED_HW_CFG_PCIE_GEN2_DISABLED 0x00000000 201 202 /* The default value for the core clock is 250MHz and it is 203 achieved by setting the clock change to 4 */ 204 #define SHARED_HW_CFG_CLOCK_CHANGE_MASK 0x00000e00 205 #define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT 9 206 207 #define SHARED_HW_CFG_SMBUS_TIMING_MASK 0x00001000 208 #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000 209 #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000 210 211 #define SHARED_HW_CFG_HIDE_PORT1 0x00002000 212 213 #define SHARED_HW_CFG_WOL_CAPABLE_MASK 0x00004000 214 #define SHARED_HW_CFG_WOL_CAPABLE_DISABLED 0x00000000 215 #define SHARED_HW_CFG_WOL_CAPABLE_ENABLED 0x00004000 216 217 /* Output low when PERST is asserted */ 218 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_MASK 0x00008000 219 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_DISABLED 0x00000000 220 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_ENABLED 0x00008000 221 222 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_MASK 0x00070000 223 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_SHIFT 16 224 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_HW 0x00000000 225 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_0DB 0x00010000 226 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_3_5DB 0x00020000 227 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_6_0DB 0x00030000 228 229 /* The fan failure mechanism is usually related to the PHY type 230 since the power consumption of the board is determined by the PHY. 231 Currently, fan is required for most designs with SFX7101, BCM8727 232 and BCM8481. If a fan is not required for a board which uses one 233 of those PHYs, this field should be set to "Disabled". If a fan is 234 required for a different PHY type, this option should be set to 235 "Enabled". The fan failure indication is expected on SPIO5 */ 236 #define SHARED_HW_CFG_FAN_FAILURE_MASK 0x00180000 237 #define SHARED_HW_CFG_FAN_FAILURE_SHIFT 19 238 #define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE 0x00000000 239 #define SHARED_HW_CFG_FAN_FAILURE_DISABLED 0x00080000 240 #define SHARED_HW_CFG_FAN_FAILURE_ENABLED 0x00100000 241 242 /* ASPM Power Management support */ 243 #define SHARED_HW_CFG_ASPM_SUPPORT_MASK 0x00600000 244 #define SHARED_HW_CFG_ASPM_SUPPORT_SHIFT 21 245 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_ENABLED 0x00000000 246 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_DISABLED 0x00200000 247 #define SHARED_HW_CFG_ASPM_SUPPORT_L1_DISABLED 0x00400000 248 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_DISABLED 0x00600000 249 250 /* The value of PM_TL_IGNORE_REQS (bit0) in PCI register 251 tl_control_0 (register 0x2800) */ 252 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_MASK 0x00800000 253 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_DISABLED 0x00000000 254 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_ENABLED 0x00800000 255 256 #define SHARED_HW_CFG_PORT_MODE_MASK 0x01000000 257 #define SHARED_HW_CFG_PORT_MODE_2 0x00000000 258 #define SHARED_HW_CFG_PORT_MODE_4 0x01000000 259 260 #define SHARED_HW_CFG_PATH_SWAP_MASK 0x02000000 261 #define SHARED_HW_CFG_PATH_SWAP_DISABLED 0x00000000 262 #define SHARED_HW_CFG_PATH_SWAP_ENABLED 0x02000000 263 264 /* Set the MDC/MDIO access for the first external phy */ 265 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK 0x1C000000 266 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT 26 267 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE 0x00000000 268 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0 0x04000000 269 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1 0x08000000 270 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH 0x0c000000 271 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED 0x10000000 272 273 /* Set the MDC/MDIO access for the second external phy */ 274 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK 0xE0000000 275 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT 29 276 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE 0x00000000 277 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0 0x20000000 278 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1 0x40000000 279 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH 0x60000000 280 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED 0x80000000 281 282 283 u32 power_dissipated; /* 0x11c */ 284 #define SHARED_HW_CFG_POWER_MGNT_SCALE_MASK 0x00ff0000 285 #define SHARED_HW_CFG_POWER_MGNT_SCALE_SHIFT 16 286 #define SHARED_HW_CFG_POWER_MGNT_UNKNOWN_SCALE 0x00000000 287 #define SHARED_HW_CFG_POWER_MGNT_DOT_1_WATT 0x00010000 288 #define SHARED_HW_CFG_POWER_MGNT_DOT_01_WATT 0x00020000 289 #define SHARED_HW_CFG_POWER_MGNT_DOT_001_WATT 0x00030000 290 291 #define SHARED_HW_CFG_POWER_DIS_CMN_MASK 0xff000000 292 #define SHARED_HW_CFG_POWER_DIS_CMN_SHIFT 24 293 294 u32 ump_nc_si_config; /* 0x120 */ 295 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003 296 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0 297 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000 298 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001 299 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000 300 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002 301 302 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK 0x00000f00 303 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT 8 304 305 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK 0x00ff0000 306 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT 16 307 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE 0x00000000 308 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000 309 310 u32 board; /* 0x124 */ 311 #define SHARED_HW_CFG_E3_I2C_MUX0_MASK 0x0000003F 312 #define SHARED_HW_CFG_E3_I2C_MUX0_SHIFT 0 313 #define SHARED_HW_CFG_E3_I2C_MUX1_MASK 0x00000FC0 314 #define SHARED_HW_CFG_E3_I2C_MUX1_SHIFT 6 315 /* Use the PIN_CFG_XXX defines on top */ 316 #define SHARED_HW_CFG_BOARD_REV_MASK 0x00ff0000 317 #define SHARED_HW_CFG_BOARD_REV_SHIFT 16 318 319 #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0x0f000000 320 #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 24 321 322 #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0xf0000000 323 #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 28 324 325 u32 wc_lane_config; /* 0x128 */ 326 #define SHARED_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF 327 #define SHARED_HW_CFG_LANE_SWAP_CFG_SHIFT 0 328 #define SHARED_HW_CFG_LANE_SWAP_CFG_32103210 0x00001b1b 329 #define SHARED_HW_CFG_LANE_SWAP_CFG_32100123 0x00001be4 330 #define SHARED_HW_CFG_LANE_SWAP_CFG_01233210 0x0000e41b 331 #define SHARED_HW_CFG_LANE_SWAP_CFG_01230123 0x0000e4e4 332 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF 333 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0 334 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00 335 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8 336 337 /* TX lane Polarity swap */ 338 #define SHARED_HW_CFG_TX_LANE0_POL_FLIP_ENABLED 0x00010000 339 #define SHARED_HW_CFG_TX_LANE1_POL_FLIP_ENABLED 0x00020000 340 #define SHARED_HW_CFG_TX_LANE2_POL_FLIP_ENABLED 0x00040000 341 #define SHARED_HW_CFG_TX_LANE3_POL_FLIP_ENABLED 0x00080000 342 /* TX lane Polarity swap */ 343 #define SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED 0x00100000 344 #define SHARED_HW_CFG_RX_LANE1_POL_FLIP_ENABLED 0x00200000 345 #define SHARED_HW_CFG_RX_LANE2_POL_FLIP_ENABLED 0x00400000 346 #define SHARED_HW_CFG_RX_LANE3_POL_FLIP_ENABLED 0x00800000 347 348 /* Selects the port layout of the board */ 349 #define SHARED_HW_CFG_E3_PORT_LAYOUT_MASK 0x0F000000 350 #define SHARED_HW_CFG_E3_PORT_LAYOUT_SHIFT 24 351 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01 0x00000000 352 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_10 0x01000000 353 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_0123 0x02000000 354 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_1032 0x03000000 355 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_2301 0x04000000 356 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_3210 0x05000000 357 }; 358 359 360 /**************************************************************************** 361 * Port HW configuration * 362 ****************************************************************************/ 363 struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */ 364 365 u32 pci_id; 366 #define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xffff0000 367 #define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000ffff 368 369 u32 pci_sub_id; 370 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xffff0000 371 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000ffff 372 373 u32 power_dissipated; 374 #define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000ff 375 #define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0 376 #define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000ff00 377 #define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8 378 #define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00ff0000 379 #define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16 380 #define PORT_HW_CFG_POWER_DIS_D3_MASK 0xff000000 381 #define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24 382 383 u32 power_consumed; 384 #define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000ff 385 #define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0 386 #define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000ff00 387 #define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8 388 #define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00ff0000 389 #define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16 390 #define PORT_HW_CFG_POWER_CONS_D3_MASK 0xff000000 391 #define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24 392 393 u32 mac_upper; 394 #define PORT_HW_CFG_UPPERMAC_MASK 0x0000ffff 395 #define PORT_HW_CFG_UPPERMAC_SHIFT 0 396 u32 mac_lower; 397 398 u32 iscsi_mac_upper; /* Upper 16 bits are always zeroes */ 399 u32 iscsi_mac_lower; 400 401 u32 rdma_mac_upper; /* Upper 16 bits are always zeroes */ 402 u32 rdma_mac_lower; 403 404 u32 serdes_config; 405 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000ffff 406 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0 407 408 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xffff0000 409 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 16 410 411 412 /* Default values: 2P-64, 4P-32 */ 413 u32 pf_config; /* 0x158 */ 414 #define PORT_HW_CFG_PF_NUM_VF_MASK 0x0000007F 415 #define PORT_HW_CFG_PF_NUM_VF_SHIFT 0 416 417 /* Default values: 17 */ 418 #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_MASK 0x00007F00 419 #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_SHIFT 8 420 421 #define PORT_HW_CFG_ENABLE_FLR_MASK 0x00010000 422 #define PORT_HW_CFG_FLR_ENABLED 0x00010000 423 424 u32 vf_config; /* 0x15C */ 425 #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_MASK 0x0000007F 426 #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_SHIFT 0 427 428 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_MASK 0xFFFF0000 429 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_SHIFT 16 430 431 u32 mf_pci_id; /* 0x160 */ 432 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_MASK 0x0000FFFF 433 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_SHIFT 0 434 435 /* Controls the TX laser of the SFP+ module */ 436 u32 sfp_ctrl; /* 0x164 */ 437 #define PORT_HW_CFG_TX_LASER_MASK 0x000000FF 438 #define PORT_HW_CFG_TX_LASER_SHIFT 0 439 #define PORT_HW_CFG_TX_LASER_MDIO 0x00000000 440 #define PORT_HW_CFG_TX_LASER_GPIO0 0x00000001 441 #define PORT_HW_CFG_TX_LASER_GPIO1 0x00000002 442 #define PORT_HW_CFG_TX_LASER_GPIO2 0x00000003 443 #define PORT_HW_CFG_TX_LASER_GPIO3 0x00000004 444 445 /* Controls the fault module LED of the SFP+ */ 446 #define PORT_HW_CFG_FAULT_MODULE_LED_MASK 0x0000FF00 447 #define PORT_HW_CFG_FAULT_MODULE_LED_SHIFT 8 448 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO0 0x00000000 449 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO1 0x00000100 450 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO2 0x00000200 451 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO3 0x00000300 452 #define PORT_HW_CFG_FAULT_MODULE_LED_DISABLED 0x00000400 453 454 /* The output pin TX_DIS that controls the TX laser of the SFP+ 455 module. Use the PIN_CFG_XXX defines on top */ 456 u32 e3_sfp_ctrl; /* 0x168 */ 457 #define PORT_HW_CFG_E3_TX_LASER_MASK 0x000000FF 458 #define PORT_HW_CFG_E3_TX_LASER_SHIFT 0 459 460 /* The output pin for SFPP_TYPE which turns on the Fault module LED */ 461 #define PORT_HW_CFG_E3_FAULT_MDL_LED_MASK 0x0000FF00 462 #define PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT 8 463 464 /* The input pin MOD_ABS that indicates whether SFP+ module is 465 present or not. Use the PIN_CFG_XXX defines on top */ 466 #define PORT_HW_CFG_E3_MOD_ABS_MASK 0x00FF0000 467 #define PORT_HW_CFG_E3_MOD_ABS_SHIFT 16 468 469 /* The output pin PWRDIS_SFP_X which disable the power of the SFP+ 470 module. Use the PIN_CFG_XXX defines on top */ 471 #define PORT_HW_CFG_E3_PWR_DIS_MASK 0xFF000000 472 #define PORT_HW_CFG_E3_PWR_DIS_SHIFT 24 473 474 /* 475 * The input pin which signals module transmit fault. Use the 476 * PIN_CFG_XXX defines on top 477 */ 478 u32 e3_cmn_pin_cfg; /* 0x16C */ 479 #define PORT_HW_CFG_E3_TX_FAULT_MASK 0x000000FF 480 #define PORT_HW_CFG_E3_TX_FAULT_SHIFT 0 481 482 /* The output pin which reset the PHY. Use the PIN_CFG_XXX defines on 483 top */ 484 #define PORT_HW_CFG_E3_PHY_RESET_MASK 0x0000FF00 485 #define PORT_HW_CFG_E3_PHY_RESET_SHIFT 8 486 487 /* 488 * The output pin which powers down the PHY. Use the PIN_CFG_XXX 489 * defines on top 490 */ 491 #define PORT_HW_CFG_E3_PWR_DOWN_MASK 0x00FF0000 492 #define PORT_HW_CFG_E3_PWR_DOWN_SHIFT 16 493 494 /* The output pin values BSC_SEL which selects the I2C for this port 495 in the I2C Mux */ 496 #define PORT_HW_CFG_E3_I2C_MUX0_MASK 0x01000000 497 #define PORT_HW_CFG_E3_I2C_MUX1_MASK 0x02000000 498 499 500 /* 501 * The input pin I_FAULT which indicate over-current has occurred. 502 * Use the PIN_CFG_XXX defines on top 503 */ 504 u32 e3_cmn_pin_cfg1; /* 0x170 */ 505 #define PORT_HW_CFG_E3_OVER_CURRENT_MASK 0x000000FF 506 #define PORT_HW_CFG_E3_OVER_CURRENT_SHIFT 0 507 u32 reserved0[7]; /* 0x174 */ 508 509 u32 aeu_int_mask; /* 0x190 */ 510 511 u32 media_type; /* 0x194 */ 512 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK 0x000000FF 513 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT 0 514 515 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK 0x0000FF00 516 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT 8 517 518 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK 0x00FF0000 519 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT 16 520 521 /* 4 times 16 bits for all 4 lanes. In case external PHY is present 522 (not direct mode), those values will not take effect on the 4 XGXS 523 lanes. For some external PHYs (such as 8706 and 8726) the values 524 will be used to configure the external PHY in those cases, not 525 all 4 values are needed. */ 526 u16 xgxs_config_rx[4]; /* 0x198 */ 527 u16 xgxs_config_tx[4]; /* 0x1A0 */ 528 529 /* For storing FCOE mac on shared memory */ 530 u32 fcoe_fip_mac_upper; 531 #define PORT_HW_CFG_FCOE_UPPERMAC_MASK 0x0000ffff 532 #define PORT_HW_CFG_FCOE_UPPERMAC_SHIFT 0 533 u32 fcoe_fip_mac_lower; 534 535 u32 fcoe_wwn_port_name_upper; 536 u32 fcoe_wwn_port_name_lower; 537 538 u32 fcoe_wwn_node_name_upper; 539 u32 fcoe_wwn_node_name_lower; 540 541 u32 Reserved1[49]; /* 0x1C0 */ 542 543 /* Enable RJ45 magjack pair swapping on 10GBase-T PHY (0=default), 544 84833 only */ 545 u32 xgbt_phy_cfg; /* 0x284 */ 546 #define PORT_HW_CFG_RJ45_PAIR_SWAP_MASK 0x000000FF 547 #define PORT_HW_CFG_RJ45_PAIR_SWAP_SHIFT 0 548 549 u32 default_cfg; /* 0x288 */ 550 #define PORT_HW_CFG_GPIO0_CONFIG_MASK 0x00000003 551 #define PORT_HW_CFG_GPIO0_CONFIG_SHIFT 0 552 #define PORT_HW_CFG_GPIO0_CONFIG_NA 0x00000000 553 #define PORT_HW_CFG_GPIO0_CONFIG_LOW 0x00000001 554 #define PORT_HW_CFG_GPIO0_CONFIG_HIGH 0x00000002 555 #define PORT_HW_CFG_GPIO0_CONFIG_INPUT 0x00000003 556 557 #define PORT_HW_CFG_GPIO1_CONFIG_MASK 0x0000000C 558 #define PORT_HW_CFG_GPIO1_CONFIG_SHIFT 2 559 #define PORT_HW_CFG_GPIO1_CONFIG_NA 0x00000000 560 #define PORT_HW_CFG_GPIO1_CONFIG_LOW 0x00000004 561 #define PORT_HW_CFG_GPIO1_CONFIG_HIGH 0x00000008 562 #define PORT_HW_CFG_GPIO1_CONFIG_INPUT 0x0000000c 563 564 #define PORT_HW_CFG_GPIO2_CONFIG_MASK 0x00000030 565 #define PORT_HW_CFG_GPIO2_CONFIG_SHIFT 4 566 #define PORT_HW_CFG_GPIO2_CONFIG_NA 0x00000000 567 #define PORT_HW_CFG_GPIO2_CONFIG_LOW 0x00000010 568 #define PORT_HW_CFG_GPIO2_CONFIG_HIGH 0x00000020 569 #define PORT_HW_CFG_GPIO2_CONFIG_INPUT 0x00000030 570 571 #define PORT_HW_CFG_GPIO3_CONFIG_MASK 0x000000C0 572 #define PORT_HW_CFG_GPIO3_CONFIG_SHIFT 6 573 #define PORT_HW_CFG_GPIO3_CONFIG_NA 0x00000000 574 #define PORT_HW_CFG_GPIO3_CONFIG_LOW 0x00000040 575 #define PORT_HW_CFG_GPIO3_CONFIG_HIGH 0x00000080 576 #define PORT_HW_CFG_GPIO3_CONFIG_INPUT 0x000000c0 577 578 /* When KR link is required to be set to force which is not 579 KR-compliant, this parameter determine what is the trigger for it. 580 When GPIO is selected, low input will force the speed. Currently 581 default speed is 1G. In the future, it may be widen to select the 582 forced speed in with another parameter. Note when force-1G is 583 enabled, it override option 56: Link Speed option. */ 584 #define PORT_HW_CFG_FORCE_KR_ENABLER_MASK 0x00000F00 585 #define PORT_HW_CFG_FORCE_KR_ENABLER_SHIFT 8 586 #define PORT_HW_CFG_FORCE_KR_ENABLER_NOT_FORCED 0x00000000 587 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P0 0x00000100 588 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P0 0x00000200 589 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P0 0x00000300 590 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P0 0x00000400 591 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P1 0x00000500 592 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P1 0x00000600 593 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P1 0x00000700 594 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P1 0x00000800 595 #define PORT_HW_CFG_FORCE_KR_ENABLER_FORCED 0x00000900 596 /* Enable to determine with which GPIO to reset the external phy */ 597 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK 0x000F0000 598 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT 16 599 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_PHY_TYPE 0x00000000 600 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0 0x00010000 601 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0 0x00020000 602 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0 0x00030000 603 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0 0x00040000 604 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1 0x00050000 605 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1 0x00060000 606 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1 0x00070000 607 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1 0x00080000 608 609 /* Enable BAM on KR */ 610 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK 0x00100000 611 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT 20 612 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED 0x00000000 613 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED 0x00100000 614 615 /* Enable Common Mode Sense */ 616 #define PORT_HW_CFG_ENABLE_CMS_MASK 0x00200000 617 #define PORT_HW_CFG_ENABLE_CMS_SHIFT 21 618 #define PORT_HW_CFG_ENABLE_CMS_DISABLED 0x00000000 619 #define PORT_HW_CFG_ENABLE_CMS_ENABLED 0x00200000 620 621 /* Enable RJ45 magjack pair swapping on 10GBase-T PHY, 84833 only */ 622 #define PORT_HW_CFG_RJ45_PR_SWP_MASK 0x00400000 623 #define PORT_HW_CFG_RJ45_PR_SWP_SHIFT 22 624 #define PORT_HW_CFG_RJ45_PR_SWP_DISABLED 0x00000000 625 #define PORT_HW_CFG_RJ45_PR_SWP_ENABLED 0x00400000 626 627 /* Determine the Serdes electrical interface */ 628 #define PORT_HW_CFG_NET_SERDES_IF_MASK 0x0F000000 629 #define PORT_HW_CFG_NET_SERDES_IF_SHIFT 24 630 #define PORT_HW_CFG_NET_SERDES_IF_SGMII 0x00000000 631 #define PORT_HW_CFG_NET_SERDES_IF_XFI 0x01000000 632 #define PORT_HW_CFG_NET_SERDES_IF_SFI 0x02000000 633 #define PORT_HW_CFG_NET_SERDES_IF_KR 0x03000000 634 #define PORT_HW_CFG_NET_SERDES_IF_DXGXS 0x04000000 635 #define PORT_HW_CFG_NET_SERDES_IF_KR2 0x05000000 636 637 638 u32 speed_capability_mask2; /* 0x28C */ 639 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK 0x0000FFFF 640 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0 641 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL 0x00000001 642 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3__ 0x00000002 643 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3___ 0x00000004 644 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL 0x00000008 645 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G 0x00000010 646 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_DOT_5G 0x00000020 647 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G 0x00000040 648 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_20G 0x00000080 649 650 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK 0xFFFF0000 651 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT 16 652 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL 0x00010000 653 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0__ 0x00020000 654 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0___ 0x00040000 655 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL 0x00080000 656 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G 0x00100000 657 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_DOT_5G 0x00200000 658 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G 0x00400000 659 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G 0x00800000 660 661 662 /* In the case where two media types (e.g. copper and fiber) are 663 present and electrically active at the same time, PHY Selection 664 will determine which of the two PHYs will be designated as the 665 Active PHY and used for a connection to the network. */ 666 u32 multi_phy_config; /* 0x290 */ 667 #define PORT_HW_CFG_PHY_SELECTION_MASK 0x00000007 668 #define PORT_HW_CFG_PHY_SELECTION_SHIFT 0 669 #define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT 0x00000000 670 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY 0x00000001 671 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY 0x00000002 672 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003 673 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004 674 675 /* When enabled, all second phy nvram parameters will be swapped 676 with the first phy parameters */ 677 #define PORT_HW_CFG_PHY_SWAPPED_MASK 0x00000008 678 #define PORT_HW_CFG_PHY_SWAPPED_SHIFT 3 679 #define PORT_HW_CFG_PHY_SWAPPED_DISABLED 0x00000000 680 #define PORT_HW_CFG_PHY_SWAPPED_ENABLED 0x00000008 681 682 683 /* Address of the second external phy */ 684 u32 external_phy_config2; /* 0x294 */ 685 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK 0x000000FF 686 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT 0 687 688 /* The second XGXS external PHY type */ 689 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK 0x0000FF00 690 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT 8 691 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT 0x00000000 692 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071 0x00000100 693 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072 0x00000200 694 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073 0x00000300 695 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705 0x00000400 696 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706 0x00000500 697 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726 0x00000600 698 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481 0x00000700 699 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101 0x00000800 700 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727 0x00000900 701 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC 0x00000a00 702 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823 0x00000b00 703 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640 0x00000c00 704 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833 0x00000d00 705 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54618SE 0x00000e00 706 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8722 0x00000f00 707 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54616 0x00001000 708 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00 709 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00 710 711 712 /* 4 times 16 bits for all 4 lanes. For some external PHYs (such as 713 8706, 8726 and 8727) not all 4 values are needed. */ 714 u16 xgxs_config2_rx[4]; /* 0x296 */ 715 u16 xgxs_config2_tx[4]; /* 0x2A0 */ 716 717 u32 lane_config; 718 #define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000ffff 719 #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0 720 /* AN and forced */ 721 #define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b 722 /* forced only */ 723 #define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4 724 /* forced only */ 725 #define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8 726 /* forced only */ 727 #define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4 728 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000ff 729 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0 730 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000ff00 731 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8 732 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000c000 733 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14 734 735 /* Indicate whether to swap the external phy polarity */ 736 #define PORT_HW_CFG_SWAP_PHY_POLARITY_MASK 0x00010000 737 #define PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED 0x00000000 738 #define PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED 0x00010000 739 740 741 u32 external_phy_config; 742 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000ff 743 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0 744 745 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000ff00 746 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8 747 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000 748 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100 749 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200 750 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300 751 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400 752 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500 753 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726 0x00000600 754 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700 755 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800 756 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 0x00000900 757 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00 758 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823 0x00000b00 759 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54640 0x00000c00 760 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833 0x00000d00 761 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE 0x00000e00 762 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722 0x00000f00 763 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616 0x00001000 764 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC 0x0000fc00 765 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00 766 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00 767 768 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00ff0000 769 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16 770 771 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xff000000 772 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24 773 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000 774 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000 775 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD 0x02000000 776 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000 777 778 u32 speed_capability_mask; 779 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000ffff 780 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0 781 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001 782 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002 783 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004 784 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008 785 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010 786 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020 787 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040 788 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_20G 0x00000080 789 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000 790 791 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xffff0000 792 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16 793 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000 794 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000 795 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000 796 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000 797 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000 798 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000 799 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000 800 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_20G 0x00800000 801 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000 802 803 /* A place to hold the original MAC address as a backup */ 804 u32 backup_mac_upper; /* 0x2B4 */ 805 u32 backup_mac_lower; /* 0x2B8 */ 806 807 }; 808 809 810 /**************************************************************************** 811 * Shared Feature configuration * 812 ****************************************************************************/ 813 struct shared_feat_cfg { /* NVRAM Offset */ 814 815 u32 config; /* 0x450 */ 816 #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001 817 818 /* Use NVRAM values instead of HW default values */ 819 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_MASK \ 820 0x00000002 821 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED \ 822 0x00000000 823 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED \ 824 0x00000002 825 826 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_MASK 0x00000008 827 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_SPIO 0x00000000 828 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_NVRAM 0x00000008 829 830 #define SHARED_FEAT_CFG_NCSI_ID_MASK 0x00000030 831 #define SHARED_FEAT_CFG_NCSI_ID_SHIFT 4 832 833 /* Override the OTP back to single function mode. When using GPIO, 834 high means only SF, 0 is according to CLP configuration */ 835 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK 0x00000700 836 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT 8 837 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED 0x00000000 838 #define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF 0x00000100 839 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4 0x00000200 840 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT 0x00000300 841 842 /* The interval in seconds between sending LLDP packets. Set to zero 843 to disable the feature */ 844 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_MASK 0x00ff0000 845 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_SHIFT 16 846 847 /* The assigned device type ID for LLDP usage */ 848 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_MASK 0xff000000 849 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_SHIFT 24 850 851 }; 852 853 854 /**************************************************************************** 855 * Port Feature configuration * 856 ****************************************************************************/ 857 struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */ 858 859 u32 config; 860 #define PORT_FEATURE_BAR1_SIZE_MASK 0x0000000f 861 #define PORT_FEATURE_BAR1_SIZE_SHIFT 0 862 #define PORT_FEATURE_BAR1_SIZE_DISABLED 0x00000000 863 #define PORT_FEATURE_BAR1_SIZE_64K 0x00000001 864 #define PORT_FEATURE_BAR1_SIZE_128K 0x00000002 865 #define PORT_FEATURE_BAR1_SIZE_256K 0x00000003 866 #define PORT_FEATURE_BAR1_SIZE_512K 0x00000004 867 #define PORT_FEATURE_BAR1_SIZE_1M 0x00000005 868 #define PORT_FEATURE_BAR1_SIZE_2M 0x00000006 869 #define PORT_FEATURE_BAR1_SIZE_4M 0x00000007 870 #define PORT_FEATURE_BAR1_SIZE_8M 0x00000008 871 #define PORT_FEATURE_BAR1_SIZE_16M 0x00000009 872 #define PORT_FEATURE_BAR1_SIZE_32M 0x0000000a 873 #define PORT_FEATURE_BAR1_SIZE_64M 0x0000000b 874 #define PORT_FEATURE_BAR1_SIZE_128M 0x0000000c 875 #define PORT_FEATURE_BAR1_SIZE_256M 0x0000000d 876 #define PORT_FEATURE_BAR1_SIZE_512M 0x0000000e 877 #define PORT_FEATURE_BAR1_SIZE_1G 0x0000000f 878 #define PORT_FEATURE_BAR2_SIZE_MASK 0x000000f0 879 #define PORT_FEATURE_BAR2_SIZE_SHIFT 4 880 #define PORT_FEATURE_BAR2_SIZE_DISABLED 0x00000000 881 #define PORT_FEATURE_BAR2_SIZE_64K 0x00000010 882 #define PORT_FEATURE_BAR2_SIZE_128K 0x00000020 883 #define PORT_FEATURE_BAR2_SIZE_256K 0x00000030 884 #define PORT_FEATURE_BAR2_SIZE_512K 0x00000040 885 #define PORT_FEATURE_BAR2_SIZE_1M 0x00000050 886 #define PORT_FEATURE_BAR2_SIZE_2M 0x00000060 887 #define PORT_FEATURE_BAR2_SIZE_4M 0x00000070 888 #define PORT_FEATURE_BAR2_SIZE_8M 0x00000080 889 #define PORT_FEATURE_BAR2_SIZE_16M 0x00000090 890 #define PORT_FEATURE_BAR2_SIZE_32M 0x000000a0 891 #define PORT_FEATURE_BAR2_SIZE_64M 0x000000b0 892 #define PORT_FEATURE_BAR2_SIZE_128M 0x000000c0 893 #define PORT_FEATURE_BAR2_SIZE_256M 0x000000d0 894 #define PORT_FEATURE_BAR2_SIZE_512M 0x000000e0 895 #define PORT_FEATURE_BAR2_SIZE_1G 0x000000f0 896 897 #define PORT_FEAT_CFG_DCBX_MASK 0x00000100 898 #define PORT_FEAT_CFG_DCBX_DISABLED 0x00000000 899 #define PORT_FEAT_CFG_DCBX_ENABLED 0x00000100 900 901 #define PORT_FEAT_CFG_AUTOGREEN_MASK 0x00000200 902 #define PORT_FEAT_CFG_AUTOGREEN_SHIFT 9 903 #define PORT_FEAT_CFG_AUTOGREEN_DISABLED 0x00000000 904 #define PORT_FEAT_CFG_AUTOGREEN_ENABLED 0x00000200 905 906 #define PORT_FEATURE_EN_SIZE_MASK 0x0f000000 907 #define PORT_FEATURE_EN_SIZE_SHIFT 24 908 #define PORT_FEATURE_WOL_ENABLED 0x01000000 909 #define PORT_FEATURE_MBA_ENABLED 0x02000000 910 #define PORT_FEATURE_MFW_ENABLED 0x04000000 911 912 /* Advertise expansion ROM even if MBA is disabled */ 913 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_MASK 0x08000000 914 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED 0x00000000 915 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED 0x08000000 916 917 /* Check the optic vendor via i2c against a list of approved modules 918 in a separate nvram image */ 919 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK 0xe0000000 920 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT 29 921 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT \ 922 0x00000000 923 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER \ 924 0x20000000 925 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG 0x40000000 926 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN 0x60000000 927 928 u32 wol_config; 929 /* Default is used when driver sets to "auto" mode */ 930 #define PORT_FEATURE_WOL_DEFAULT_MASK 0x00000003 931 #define PORT_FEATURE_WOL_DEFAULT_SHIFT 0 932 #define PORT_FEATURE_WOL_DEFAULT_DISABLE 0x00000000 933 #define PORT_FEATURE_WOL_DEFAULT_MAGIC 0x00000001 934 #define PORT_FEATURE_WOL_DEFAULT_ACPI 0x00000002 935 #define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x00000003 936 #define PORT_FEATURE_WOL_RES_PAUSE_CAP 0x00000004 937 #define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP 0x00000008 938 #define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010 939 940 u32 mba_config; 941 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000007 942 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0 943 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000 944 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001 945 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002 946 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003 947 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT 0x00000004 948 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE 0x00000007 949 950 #define PORT_FEATURE_MBA_BOOT_RETRY_MASK 0x00000038 951 #define PORT_FEATURE_MBA_BOOT_RETRY_SHIFT 3 952 953 #define PORT_FEATURE_MBA_RES_PAUSE_CAP 0x00000100 954 #define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP 0x00000200 955 #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400 956 #define PORT_FEATURE_MBA_HOTKEY_MASK 0x00000800 957 #define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000 958 #define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800 959 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000ff000 960 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12 961 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000 962 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000 963 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000 964 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000 965 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000 966 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000 967 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000 968 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000 969 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000 970 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000 971 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000 972 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000 973 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000 974 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000 975 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000 976 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000 977 #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00f00000 978 #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20 979 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000 980 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24 981 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000 982 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000 983 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000 984 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000 985 #define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c000000 986 #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26 987 #define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000 988 #define PORT_FEATURE_MBA_LINK_SPEED_10HD 0x04000000 989 #define PORT_FEATURE_MBA_LINK_SPEED_10FD 0x08000000 990 #define PORT_FEATURE_MBA_LINK_SPEED_100HD 0x0c000000 991 #define PORT_FEATURE_MBA_LINK_SPEED_100FD 0x10000000 992 #define PORT_FEATURE_MBA_LINK_SPEED_1GBPS 0x14000000 993 #define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS 0x18000000 994 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4 0x1c000000 995 #define PORT_FEATURE_MBA_LINK_SPEED_20GBPS 0x20000000 996 u32 bmc_config; 997 #define PORT_FEATURE_BMC_LINK_OVERRIDE_MASK 0x00000001 998 #define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT 0x00000000 999 #define PORT_FEATURE_BMC_LINK_OVERRIDE_EN 0x00000001 1000 1001 u32 mba_vlan_cfg; 1002 #define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000ffff 1003 #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0 1004 #define PORT_FEATURE_MBA_VLAN_EN 0x00010000 1005 1006 u32 resource_cfg; 1007 #define PORT_FEATURE_RESOURCE_CFG_VALID 0x00000001 1008 #define PORT_FEATURE_RESOURCE_CFG_DIAG 0x00000002 1009 #define PORT_FEATURE_RESOURCE_CFG_L2 0x00000004 1010 #define PORT_FEATURE_RESOURCE_CFG_ISCSI 0x00000008 1011 #define PORT_FEATURE_RESOURCE_CFG_RDMA 0x00000010 1012 1013 u32 smbus_config; 1014 #define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe 1015 #define PORT_FEATURE_SMBUS_ADDR_SHIFT 1 1016 1017 u32 vf_config; 1018 #define PORT_FEAT_CFG_VF_BAR2_SIZE_MASK 0x0000000f 1019 #define PORT_FEAT_CFG_VF_BAR2_SIZE_SHIFT 0 1020 #define PORT_FEAT_CFG_VF_BAR2_SIZE_DISABLED 0x00000000 1021 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4K 0x00000001 1022 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8K 0x00000002 1023 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16K 0x00000003 1024 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32K 0x00000004 1025 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64K 0x00000005 1026 #define PORT_FEAT_CFG_VF_BAR2_SIZE_128K 0x00000006 1027 #define PORT_FEAT_CFG_VF_BAR2_SIZE_256K 0x00000007 1028 #define PORT_FEAT_CFG_VF_BAR2_SIZE_512K 0x00000008 1029 #define PORT_FEAT_CFG_VF_BAR2_SIZE_1M 0x00000009 1030 #define PORT_FEAT_CFG_VF_BAR2_SIZE_2M 0x0000000a 1031 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4M 0x0000000b 1032 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8M 0x0000000c 1033 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16M 0x0000000d 1034 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32M 0x0000000e 1035 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64M 0x0000000f 1036 1037 u32 link_config; /* Used as HW defaults for the driver */ 1038 #define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000 1039 #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24 1040 /* (forced) low speed switch (< 10G) */ 1041 #define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000 1042 /* (forced) high speed switch (>= 10G) */ 1043 #define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000 1044 #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000 1045 #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000 1046 1047 #define PORT_FEATURE_LINK_SPEED_MASK 0x000f0000 1048 #define PORT_FEATURE_LINK_SPEED_SHIFT 16 1049 #define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000 1050 #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00010000 1051 #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00020000 1052 #define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000 1053 #define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000 1054 #define PORT_FEATURE_LINK_SPEED_1G 0x00050000 1055 #define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000 1056 #define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000 1057 #define PORT_FEATURE_LINK_SPEED_20G 0x00080000 1058 1059 #define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700 1060 #define PORT_FEATURE_FLOW_CONTROL_SHIFT 8 1061 #define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000 1062 #define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100 1063 #define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200 1064 #define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300 1065 #define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400 1066 1067 /* The default for MCP link configuration, 1068 uses the same defines as link_config */ 1069 u32 mfw_wol_link_cfg; 1070 1071 /* The default for the driver of the second external phy, 1072 uses the same defines as link_config */ 1073 u32 link_config2; /* 0x47C */ 1074 1075 /* The default for MCP of the second external phy, 1076 uses the same defines as link_config */ 1077 u32 mfw_wol_link_cfg2; /* 0x480 */ 1078 1079 u32 Reserved2[17]; /* 0x484 */ 1080 1081 }; 1082 1083 1084 /**************************************************************************** 1085 * Device Information * 1086 ****************************************************************************/ 1087 struct shm_dev_info { /* size */ 1088 1089 u32 bc_rev; /* 8 bits each: major, minor, build */ /* 4 */ 1090 1091 struct shared_hw_cfg shared_hw_config; /* 40 */ 1092 1093 struct port_hw_cfg port_hw_config[PORT_MAX]; /* 400*2=800 */ 1094 1095 struct shared_feat_cfg shared_feature_config; /* 4 */ 1096 1097 struct port_feat_cfg port_feature_config[PORT_MAX];/* 116*2=232 */ 1098 1099 }; 1100 1101 1102 #if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN) 1103 #error "Missing either LITTLE_ENDIAN or BIG_ENDIAN definition." 1104 #endif 1105 1106 #define FUNC_0 0 1107 #define FUNC_1 1 1108 #define FUNC_2 2 1109 #define FUNC_3 3 1110 #define FUNC_4 4 1111 #define FUNC_5 5 1112 #define FUNC_6 6 1113 #define FUNC_7 7 1114 #define E1_FUNC_MAX 2 1115 #define E1H_FUNC_MAX 8 1116 #define E2_FUNC_MAX 4 /* per path */ 1117 1118 #define VN_0 0 1119 #define VN_1 1 1120 #define VN_2 2 1121 #define VN_3 3 1122 #define E1VN_MAX 1 1123 #define E1HVN_MAX 4 1124 1125 #define E2_VF_MAX 64 /* HC_REG_VF_CONFIGURATION_SIZE */ 1126 /* This value (in milliseconds) determines the frequency of the driver 1127 * issuing the PULSE message code. The firmware monitors this periodic 1128 * pulse to determine when to switch to an OS-absent mode. */ 1129 #define DRV_PULSE_PERIOD_MS 250 1130 1131 /* This value (in milliseconds) determines how long the driver should 1132 * wait for an acknowledgement from the firmware before timing out. Once 1133 * the firmware has timed out, the driver will assume there is no firmware 1134 * running and there won't be any firmware-driver synchronization during a 1135 * driver reset. */ 1136 #define FW_ACK_TIME_OUT_MS 5000 1137 1138 #define FW_ACK_POLL_TIME_MS 1 1139 1140 #define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS) 1141 1142 /* LED Blink rate that will achieve ~15.9Hz */ 1143 #define LED_BLINK_RATE_VAL 480 1144 1145 /**************************************************************************** 1146 * Driver <-> FW Mailbox * 1147 ****************************************************************************/ 1148 struct drv_port_mb { 1149 1150 u32 link_status; 1151 /* Driver should update this field on any link change event */ 1152 1153 #define LINK_STATUS_LINK_FLAG_MASK 0x00000001 1154 #define LINK_STATUS_LINK_UP 0x00000001 1155 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E 1156 #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1) 1157 #define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1) 1158 #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1) 1159 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1) 1160 #define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1) 1161 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1) 1162 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1) 1163 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1) 1164 #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1) 1165 #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1) 1166 #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1) 1167 #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1) 1168 #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1) 1169 #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1) 1170 #define LINK_STATUS_SPEED_AND_DUPLEX_20GTFD (11<<1) 1171 #define LINK_STATUS_SPEED_AND_DUPLEX_20GXFD (11<<1) 1172 1173 #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020 1174 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020 1175 1176 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040 1177 #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080 1178 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080 1179 1180 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200 1181 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400 1182 #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800 1183 #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000 1184 #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000 1185 #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000 1186 #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000 1187 1188 #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000 1189 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000 1190 1191 #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000 1192 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000 1193 1194 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000 1195 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18) 1196 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18) 1197 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18) 1198 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18) 1199 1200 #define LINK_STATUS_SERDES_LINK 0x00100000 1201 1202 #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000 1203 #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000 1204 #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000 1205 #define LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE 0x10000000 1206 1207 #define LINK_STATUS_PFC_ENABLED 0x20000000 1208 1209 #define LINK_STATUS_PHYSICAL_LINK_FLAG 0x40000000 1210 1211 u32 port_stx; 1212 1213 u32 stat_nig_timer; 1214 1215 /* MCP firmware does not use this field */ 1216 u32 ext_phy_fw_version; 1217 1218 }; 1219 1220 1221 struct drv_func_mb { 1222 1223 u32 drv_mb_header; 1224 #define DRV_MSG_CODE_MASK 0xffff0000 1225 #define DRV_MSG_CODE_LOAD_REQ 0x10000000 1226 #define DRV_MSG_CODE_LOAD_DONE 0x11000000 1227 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000 1228 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000 1229 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000 1230 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000 1231 #define DRV_MSG_CODE_DCC_OK 0x30000000 1232 #define DRV_MSG_CODE_DCC_FAILURE 0x31000000 1233 #define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000 1234 #define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000 1235 #define DRV_MSG_CODE_VALIDATE_KEY 0x70000000 1236 #define DRV_MSG_CODE_GET_CURR_KEY 0x80000000 1237 #define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000 1238 #define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000 1239 #define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000 1240 /* 1241 * The optic module verification command requires bootcode 1242 * v5.0.6 or later, te specific optic module verification command 1243 * requires bootcode v5.2.12 or later 1244 */ 1245 #define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL 0xa0000000 1246 #define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL 0x00050006 1247 #define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL 0xa1000000 1248 #define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL 0x00050234 1249 #define REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED 0x00070014 1250 #define REQ_BC_VER_4_PFC_STATS_SUPPORTED 0x00070201 1251 1252 #define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG 0xb0000000 1253 #define DRV_MSG_CODE_DCBX_PMF_DRV_OK 0xb2000000 1254 1255 #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000 1256 #define DRV_MSG_CODE_DRV_INFO_ACK 0xd8000000 1257 #define DRV_MSG_CODE_DRV_INFO_NACK 0xd9000000 1258 1259 #define DRV_MSG_CODE_SET_MF_BW 0xe0000000 1260 #define REQ_BC_VER_4_SET_MF_BW 0x00060202 1261 #define DRV_MSG_CODE_SET_MF_BW_ACK 0xe1000000 1262 1263 #define DRV_MSG_CODE_LINK_STATUS_CHANGED 0x01000000 1264 1265 #define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000 1266 #define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000 1267 #define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000 1268 #define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000 1269 1270 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff 1271 1272 u32 drv_mb_param; 1273 #define DRV_MSG_CODE_SET_MF_BW_MIN_MASK 0x00ff0000 1274 #define DRV_MSG_CODE_SET_MF_BW_MAX_MASK 0xff000000 1275 1276 u32 fw_mb_header; 1277 #define FW_MSG_CODE_MASK 0xffff0000 1278 #define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000 1279 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000 1280 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000 1281 /* Load common chip is supported from bc 6.0.0 */ 1282 #define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP 0x00060000 1283 #define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 0x10130000 1284 1285 #define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000 1286 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000 1287 #define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000 1288 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000 1289 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000 1290 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000 1291 #define FW_MSG_CODE_DCC_DONE 0x30100000 1292 #define FW_MSG_CODE_LLDP_DONE 0x40100000 1293 #define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000 1294 #define FW_MSG_CODE_DIAG_REFUSE 0x50200000 1295 #define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000 1296 #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000 1297 #define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000 1298 #define FW_MSG_CODE_GET_KEY_DONE 0x80100000 1299 #define FW_MSG_CODE_NO_KEY 0x80f00000 1300 #define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000 1301 #define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000 1302 #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000 1303 #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000 1304 #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000 1305 #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000 1306 #define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS 0xa0100000 1307 #define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG 0xa0200000 1308 #define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED 0xa0300000 1309 #define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000 1310 #define FW_MSG_CODE_DRV_INFO_ACK 0xd8100000 1311 #define FW_MSG_CODE_DRV_INFO_NACK 0xd9100000 1312 1313 #define FW_MSG_CODE_SET_MF_BW_SENT 0xe0000000 1314 #define FW_MSG_CODE_SET_MF_BW_DONE 0xe1000000 1315 1316 #define FW_MSG_CODE_LINK_CHANGED_ACK 0x01100000 1317 1318 #define FW_MSG_CODE_LIC_CHALLENGE 0xff010000 1319 #define FW_MSG_CODE_LIC_RESPONSE 0xff020000 1320 #define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000 1321 #define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000 1322 1323 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff 1324 1325 u32 fw_mb_param; 1326 1327 u32 drv_pulse_mb; 1328 #define DRV_PULSE_SEQ_MASK 0x00007fff 1329 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000 1330 /* 1331 * The system time is in the format of 1332 * (year-2001)*12*32 + month*32 + day. 1333 */ 1334 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000 1335 /* 1336 * Indicate to the firmware not to go into the 1337 * OS-absent when it is not getting driver pulse. 1338 * This is used for debugging as well for PXE(MBA). 1339 */ 1340 1341 u32 mcp_pulse_mb; 1342 #define MCP_PULSE_SEQ_MASK 0x00007fff 1343 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000 1344 /* Indicates to the driver not to assert due to lack 1345 * of MCP response */ 1346 #define MCP_EVENT_MASK 0xffff0000 1347 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000 1348 1349 u32 iscsi_boot_signature; 1350 u32 iscsi_boot_block_offset; 1351 1352 u32 drv_status; 1353 #define DRV_STATUS_PMF 0x00000001 1354 #define DRV_STATUS_VF_DISABLED 0x00000002 1355 #define DRV_STATUS_SET_MF_BW 0x00000004 1356 #define DRV_STATUS_LINK_EVENT 0x00000008 1357 1358 #define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00 1359 #define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100 1360 #define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200 1361 #define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS 0x00000400 1362 #define DRV_STATUS_DCC_RESERVED1 0x00000800 1363 #define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000 1364 #define DRV_STATUS_DCC_SET_PRIORITY 0x00002000 1365 1366 #define DRV_STATUS_DCBX_EVENT_MASK 0x000f0000 1367 #define DRV_STATUS_DCBX_NEGOTIATION_RESULTS 0x00010000 1368 #define DRV_STATUS_DRV_INFO_REQ 0x04000000 1369 1370 u32 virt_mac_upper; 1371 #define VIRT_MAC_SIGN_MASK 0xffff0000 1372 #define VIRT_MAC_SIGNATURE 0x564d0000 1373 u32 virt_mac_lower; 1374 1375 }; 1376 1377 1378 /**************************************************************************** 1379 * Management firmware state * 1380 ****************************************************************************/ 1381 /* Allocate 440 bytes for management firmware */ 1382 #define MGMTFW_STATE_WORD_SIZE 110 1383 1384 struct mgmtfw_state { 1385 u32 opaque[MGMTFW_STATE_WORD_SIZE]; 1386 }; 1387 1388 1389 /**************************************************************************** 1390 * Multi-Function configuration * 1391 ****************************************************************************/ 1392 struct shared_mf_cfg { 1393 1394 u32 clp_mb; 1395 #define SHARED_MF_CLP_SET_DEFAULT 0x00000000 1396 /* set by CLP */ 1397 #define SHARED_MF_CLP_EXIT 0x00000001 1398 /* set by MCP */ 1399 #define SHARED_MF_CLP_EXIT_DONE 0x00010000 1400 1401 }; 1402 1403 struct port_mf_cfg { 1404 1405 u32 dynamic_cfg; /* device control channel */ 1406 #define PORT_MF_CFG_E1HOV_TAG_MASK 0x0000ffff 1407 #define PORT_MF_CFG_E1HOV_TAG_SHIFT 0 1408 #define PORT_MF_CFG_E1HOV_TAG_DEFAULT PORT_MF_CFG_E1HOV_TAG_MASK 1409 1410 u32 reserved[3]; 1411 1412 }; 1413 1414 struct func_mf_cfg { 1415 1416 u32 config; 1417 /* E/R/I/D */ 1418 /* function 0 of each port cannot be hidden */ 1419 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001 1420 1421 #define FUNC_MF_CFG_PROTOCOL_MASK 0x00000006 1422 #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000000 1423 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002 1424 #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004 1425 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006 1426 #define FUNC_MF_CFG_PROTOCOL_DEFAULT \ 1427 FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 1428 1429 #define FUNC_MF_CFG_FUNC_DISABLED 0x00000008 1430 #define FUNC_MF_CFG_FUNC_DELETED 0x00000010 1431 1432 /* PRI */ 1433 /* 0 - low priority, 3 - high priority */ 1434 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300 1435 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8 1436 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000 1437 1438 /* MINBW, MAXBW */ 1439 /* value range - 0..100, increments in 100Mbps */ 1440 #define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000 1441 #define FUNC_MF_CFG_MIN_BW_SHIFT 16 1442 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000 1443 #define FUNC_MF_CFG_MAX_BW_MASK 0xff000000 1444 #define FUNC_MF_CFG_MAX_BW_SHIFT 24 1445 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000 1446 1447 u32 mac_upper; /* MAC */ 1448 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff 1449 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0 1450 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK 1451 u32 mac_lower; 1452 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff 1453 1454 u32 e1hov_tag; /* VNI */ 1455 #define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff 1456 #define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0 1457 #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK 1458 1459 u32 reserved[2]; 1460 }; 1461 1462 /* This structure is not applicable and should not be accessed on 57711 */ 1463 struct func_ext_cfg { 1464 u32 func_cfg; 1465 #define MACP_FUNC_CFG_FLAGS_MASK 0x000000FF 1466 #define MACP_FUNC_CFG_FLAGS_SHIFT 0 1467 #define MACP_FUNC_CFG_FLAGS_ENABLED 0x00000001 1468 #define MACP_FUNC_CFG_FLAGS_ETHERNET 0x00000002 1469 #define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD 0x00000004 1470 #define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD 0x00000008 1471 1472 u32 iscsi_mac_addr_upper; 1473 u32 iscsi_mac_addr_lower; 1474 1475 u32 fcoe_mac_addr_upper; 1476 u32 fcoe_mac_addr_lower; 1477 1478 u32 fcoe_wwn_port_name_upper; 1479 u32 fcoe_wwn_port_name_lower; 1480 1481 u32 fcoe_wwn_node_name_upper; 1482 u32 fcoe_wwn_node_name_lower; 1483 1484 u32 preserve_data; 1485 #define MF_FUNC_CFG_PRESERVE_L2_MAC (1<<0) 1486 #define MF_FUNC_CFG_PRESERVE_ISCSI_MAC (1<<1) 1487 #define MF_FUNC_CFG_PRESERVE_FCOE_MAC (1<<2) 1488 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_P (1<<3) 1489 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_N (1<<4) 1490 #define MF_FUNC_CFG_PRESERVE_TX_BW (1<<5) 1491 }; 1492 1493 struct mf_cfg { 1494 1495 struct shared_mf_cfg shared_mf_config; /* 0x4 */ 1496 struct port_mf_cfg port_mf_config[PORT_MAX]; /* 0x10 * 2 = 0x20 */ 1497 /* for all chips, there are 8 mf functions */ 1498 struct func_mf_cfg func_mf_config[E1H_FUNC_MAX]; /* 0x18 * 8 = 0xc0 */ 1499 /* 1500 * Extended configuration per function - this array does not exist and 1501 * should not be accessed on 57711 1502 */ 1503 struct func_ext_cfg func_ext_config[E1H_FUNC_MAX]; /* 0x28 * 8 = 0x140*/ 1504 }; /* 0x224 */ 1505 1506 /**************************************************************************** 1507 * Shared Memory Region * 1508 ****************************************************************************/ 1509 struct shmem_region { /* SharedMem Offset (size) */ 1510 1511 u32 validity_map[PORT_MAX]; /* 0x0 (4*2 = 0x8) */ 1512 #define SHR_MEM_FORMAT_REV_MASK 0xff000000 1513 #define SHR_MEM_FORMAT_REV_ID ('A'<<24) 1514 /* validity bits */ 1515 #define SHR_MEM_VALIDITY_PCI_CFG 0x00100000 1516 #define SHR_MEM_VALIDITY_MB 0x00200000 1517 #define SHR_MEM_VALIDITY_DEV_INFO 0x00400000 1518 #define SHR_MEM_VALIDITY_RESERVED 0x00000007 1519 /* One licensing bit should be set */ 1520 #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038 1521 #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008 1522 #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010 1523 #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020 1524 /* Active MFW */ 1525 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000 1526 #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0 1527 #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040 1528 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080 1529 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0 1530 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0 1531 1532 struct shm_dev_info dev_info; /* 0x8 (0x438) */ 1533 1534 struct license_key drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */ 1535 1536 /* FW information (for internal FW use) */ 1537 u32 fw_info_fio_offset; /* 0x4a8 (0x4) */ 1538 struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */ 1539 1540 struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */ 1541 1542 #ifdef BMAPI 1543 /* This is a variable length array */ 1544 /* the number of function depends on the chip type */ 1545 struct drv_func_mb func_mb[1]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */ 1546 #else 1547 /* the number of function depends on the chip type */ 1548 struct drv_func_mb func_mb[]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */ 1549 #endif /* BMAPI */ 1550 1551 }; /* 57710 = 0x6dc | 57711 = 0x7E4 | 57712 = 0x734 */ 1552 1553 /**************************************************************************** 1554 * Shared Memory 2 Region * 1555 ****************************************************************************/ 1556 /* The fw_flr_ack is actually built in the following way: */ 1557 /* 8 bit: PF ack */ 1558 /* 64 bit: VF ack */ 1559 /* 8 bit: ios_dis_ack */ 1560 /* In order to maintain endianity in the mailbox hsi, we want to keep using */ 1561 /* u32. The fw must have the VF right after the PF since this is how it */ 1562 /* access arrays(it expects always the VF to reside after the PF, and that */ 1563 /* makes the calculation much easier for it. ) */ 1564 /* In order to answer both limitations, and keep the struct small, the code */ 1565 /* will abuse the structure defined here to achieve the actual partition */ 1566 /* above */ 1567 /****************************************************************************/ 1568 struct fw_flr_ack { 1569 u32 pf_ack; 1570 u32 vf_ack[1]; 1571 u32 iov_dis_ack; 1572 }; 1573 1574 struct fw_flr_mb { 1575 u32 aggint; 1576 u32 opgen_addr; 1577 struct fw_flr_ack ack; 1578 }; 1579 1580 /**** SUPPORT FOR SHMEM ARRRAYS *** 1581 * The SHMEM HSI is aligned on 32 bit boundaries which makes it difficult to 1582 * define arrays with storage types smaller then unsigned dwords. 1583 * The macros below add generic support for SHMEM arrays with numeric elements 1584 * that can span 2,4,8 or 16 bits. The array underlying type is a 32 bit dword 1585 * array with individual bit-filed elements accessed using shifts and masks. 1586 * 1587 */ 1588 1589 /* eb is the bitwidth of a single element */ 1590 #define SHMEM_ARRAY_MASK(eb) ((1<<(eb))-1) 1591 #define SHMEM_ARRAY_ENTRY(i, eb) ((i)/(32/(eb))) 1592 1593 /* the bit-position macro allows the used to flip the order of the arrays 1594 * elements on a per byte or word boundary. 1595 * 1596 * example: an array with 8 entries each 4 bit wide. This array will fit into 1597 * a single dword. The diagrmas below show the array order of the nibbles. 1598 * 1599 * SHMEM_ARRAY_BITPOS(i, 4, 4) defines the stadard ordering: 1600 * 1601 * | | | | 1602 * 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 1603 * | | | | 1604 * 1605 * SHMEM_ARRAY_BITPOS(i, 4, 8) defines a flip ordering per byte: 1606 * 1607 * | | | | 1608 * 1 | 0 | 3 | 2 | 5 | 4 | 7 | 6 | 1609 * | | | | 1610 * 1611 * SHMEM_ARRAY_BITPOS(i, 4, 16) defines a flip ordering per word: 1612 * 1613 * | | | | 1614 * 3 | 2 | 1 | 0 | 7 | 6 | 5 | 4 | 1615 * | | | | 1616 */ 1617 #define SHMEM_ARRAY_BITPOS(i, eb, fb) \ 1618 ((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \ 1619 (((i)%((fb)/(eb))) * (eb))) 1620 1621 #define SHMEM_ARRAY_GET(a, i, eb, fb) \ 1622 ((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) & \ 1623 SHMEM_ARRAY_MASK(eb)) 1624 1625 #define SHMEM_ARRAY_SET(a, i, eb, fb, val) \ 1626 do { \ 1627 a[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) << \ 1628 SHMEM_ARRAY_BITPOS(i, eb, fb)); \ 1629 a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) << \ 1630 SHMEM_ARRAY_BITPOS(i, eb, fb)); \ 1631 } while (0) 1632 1633 1634 /****START OF DCBX STRUCTURES DECLARATIONS****/ 1635 #define DCBX_MAX_NUM_PRI_PG_ENTRIES 8 1636 #define DCBX_PRI_PG_BITWIDTH 4 1637 #define DCBX_PRI_PG_FBITS 8 1638 #define DCBX_PRI_PG_GET(a, i) \ 1639 SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS) 1640 #define DCBX_PRI_PG_SET(a, i, val) \ 1641 SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val) 1642 #define DCBX_MAX_NUM_PG_BW_ENTRIES 8 1643 #define DCBX_BW_PG_BITWIDTH 8 1644 #define DCBX_PG_BW_GET(a, i) \ 1645 SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH) 1646 #define DCBX_PG_BW_SET(a, i, val) \ 1647 SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val) 1648 #define DCBX_STRICT_PRI_PG 15 1649 #define DCBX_MAX_APP_PROTOCOL 16 1650 #define FCOE_APP_IDX 0 1651 #define ISCSI_APP_IDX 1 1652 #define PREDEFINED_APP_IDX_MAX 2 1653 1654 1655 /* Big/Little endian have the same representation. */ 1656 struct dcbx_ets_feature { 1657 /* 1658 * For Admin MIB - is this feature supported by the 1659 * driver | For Local MIB - should this feature be enabled. 1660 */ 1661 u32 enabled; 1662 u32 pg_bw_tbl[2]; 1663 u32 pri_pg_tbl[1]; 1664 }; 1665 1666 /* Driver structure in LE */ 1667 struct dcbx_pfc_feature { 1668 #ifdef __BIG_ENDIAN 1669 u8 pri_en_bitmap; 1670 #define DCBX_PFC_PRI_0 0x01 1671 #define DCBX_PFC_PRI_1 0x02 1672 #define DCBX_PFC_PRI_2 0x04 1673 #define DCBX_PFC_PRI_3 0x08 1674 #define DCBX_PFC_PRI_4 0x10 1675 #define DCBX_PFC_PRI_5 0x20 1676 #define DCBX_PFC_PRI_6 0x40 1677 #define DCBX_PFC_PRI_7 0x80 1678 u8 pfc_caps; 1679 u8 reserved; 1680 u8 enabled; 1681 #elif defined(__LITTLE_ENDIAN) 1682 u8 enabled; 1683 u8 reserved; 1684 u8 pfc_caps; 1685 u8 pri_en_bitmap; 1686 #define DCBX_PFC_PRI_0 0x01 1687 #define DCBX_PFC_PRI_1 0x02 1688 #define DCBX_PFC_PRI_2 0x04 1689 #define DCBX_PFC_PRI_3 0x08 1690 #define DCBX_PFC_PRI_4 0x10 1691 #define DCBX_PFC_PRI_5 0x20 1692 #define DCBX_PFC_PRI_6 0x40 1693 #define DCBX_PFC_PRI_7 0x80 1694 #endif 1695 }; 1696 1697 struct dcbx_app_priority_entry { 1698 #ifdef __BIG_ENDIAN 1699 u16 app_id; 1700 u8 pri_bitmap; 1701 u8 appBitfield; 1702 #define DCBX_APP_ENTRY_VALID 0x01 1703 #define DCBX_APP_ENTRY_SF_MASK 0x30 1704 #define DCBX_APP_ENTRY_SF_SHIFT 4 1705 #define DCBX_APP_SF_ETH_TYPE 0x10 1706 #define DCBX_APP_SF_PORT 0x20 1707 #elif defined(__LITTLE_ENDIAN) 1708 u8 appBitfield; 1709 #define DCBX_APP_ENTRY_VALID 0x01 1710 #define DCBX_APP_ENTRY_SF_MASK 0x30 1711 #define DCBX_APP_ENTRY_SF_SHIFT 4 1712 #define DCBX_APP_SF_ETH_TYPE 0x10 1713 #define DCBX_APP_SF_PORT 0x20 1714 u8 pri_bitmap; 1715 u16 app_id; 1716 #endif 1717 }; 1718 1719 1720 /* FW structure in BE */ 1721 struct dcbx_app_priority_feature { 1722 #ifdef __BIG_ENDIAN 1723 u8 reserved; 1724 u8 default_pri; 1725 u8 tc_supported; 1726 u8 enabled; 1727 #elif defined(__LITTLE_ENDIAN) 1728 u8 enabled; 1729 u8 tc_supported; 1730 u8 default_pri; 1731 u8 reserved; 1732 #endif 1733 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL]; 1734 }; 1735 1736 /* FW structure in BE */ 1737 struct dcbx_features { 1738 /* PG feature */ 1739 struct dcbx_ets_feature ets; 1740 /* PFC feature */ 1741 struct dcbx_pfc_feature pfc; 1742 /* APP feature */ 1743 struct dcbx_app_priority_feature app; 1744 }; 1745 1746 /* LLDP protocol parameters */ 1747 /* FW structure in BE */ 1748 struct lldp_params { 1749 #ifdef __BIG_ENDIAN 1750 u8 msg_fast_tx_interval; 1751 u8 msg_tx_hold; 1752 u8 msg_tx_interval; 1753 u8 admin_status; 1754 #define LLDP_TX_ONLY 0x01 1755 #define LLDP_RX_ONLY 0x02 1756 #define LLDP_TX_RX 0x03 1757 #define LLDP_DISABLED 0x04 1758 u8 reserved1; 1759 u8 tx_fast; 1760 u8 tx_crd_max; 1761 u8 tx_crd; 1762 #elif defined(__LITTLE_ENDIAN) 1763 u8 admin_status; 1764 #define LLDP_TX_ONLY 0x01 1765 #define LLDP_RX_ONLY 0x02 1766 #define LLDP_TX_RX 0x03 1767 #define LLDP_DISABLED 0x04 1768 u8 msg_tx_interval; 1769 u8 msg_tx_hold; 1770 u8 msg_fast_tx_interval; 1771 u8 tx_crd; 1772 u8 tx_crd_max; 1773 u8 tx_fast; 1774 u8 reserved1; 1775 #endif 1776 #define REM_CHASSIS_ID_STAT_LEN 4 1777 #define REM_PORT_ID_STAT_LEN 4 1778 /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */ 1779 u32 peer_chassis_id[REM_CHASSIS_ID_STAT_LEN]; 1780 /* Holds remote Port ID TLV header, subtype and 9B of payload. */ 1781 u32 peer_port_id[REM_PORT_ID_STAT_LEN]; 1782 }; 1783 1784 struct lldp_dcbx_stat { 1785 #define LOCAL_CHASSIS_ID_STAT_LEN 2 1786 #define LOCAL_PORT_ID_STAT_LEN 2 1787 /* Holds local Chassis ID 8B payload of constant subtype 4. */ 1788 u32 local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN]; 1789 /* Holds local Port ID 8B payload of constant subtype 3. */ 1790 u32 local_port_id[LOCAL_PORT_ID_STAT_LEN]; 1791 /* Number of DCBX frames transmitted. */ 1792 u32 num_tx_dcbx_pkts; 1793 /* Number of DCBX frames received. */ 1794 u32 num_rx_dcbx_pkts; 1795 }; 1796 1797 /* ADMIN MIB - DCBX local machine default configuration. */ 1798 struct lldp_admin_mib { 1799 u32 ver_cfg_flags; 1800 #define DCBX_ETS_CONFIG_TX_ENABLED 0x00000001 1801 #define DCBX_PFC_CONFIG_TX_ENABLED 0x00000002 1802 #define DCBX_APP_CONFIG_TX_ENABLED 0x00000004 1803 #define DCBX_ETS_RECO_TX_ENABLED 0x00000008 1804 #define DCBX_ETS_RECO_VALID 0x00000010 1805 #define DCBX_ETS_WILLING 0x00000020 1806 #define DCBX_PFC_WILLING 0x00000040 1807 #define DCBX_APP_WILLING 0x00000080 1808 #define DCBX_VERSION_CEE 0x00000100 1809 #define DCBX_VERSION_IEEE 0x00000200 1810 #define DCBX_DCBX_ENABLED 0x00000400 1811 #define DCBX_CEE_VERSION_MASK 0x0000f000 1812 #define DCBX_CEE_VERSION_SHIFT 12 1813 #define DCBX_CEE_MAX_VERSION_MASK 0x000f0000 1814 #define DCBX_CEE_MAX_VERSION_SHIFT 16 1815 struct dcbx_features features; 1816 }; 1817 1818 /* REMOTE MIB - remote machine DCBX configuration. */ 1819 struct lldp_remote_mib { 1820 u32 prefix_seq_num; 1821 u32 flags; 1822 #define DCBX_ETS_TLV_RX 0x00000001 1823 #define DCBX_PFC_TLV_RX 0x00000002 1824 #define DCBX_APP_TLV_RX 0x00000004 1825 #define DCBX_ETS_RX_ERROR 0x00000010 1826 #define DCBX_PFC_RX_ERROR 0x00000020 1827 #define DCBX_APP_RX_ERROR 0x00000040 1828 #define DCBX_ETS_REM_WILLING 0x00000100 1829 #define DCBX_PFC_REM_WILLING 0x00000200 1830 #define DCBX_APP_REM_WILLING 0x00000400 1831 #define DCBX_REMOTE_ETS_RECO_VALID 0x00001000 1832 #define DCBX_REMOTE_MIB_VALID 0x00002000 1833 struct dcbx_features features; 1834 u32 suffix_seq_num; 1835 }; 1836 1837 /* LOCAL MIB - operational DCBX configuration - transmitted on Tx LLDPDU. */ 1838 struct lldp_local_mib { 1839 u32 prefix_seq_num; 1840 /* Indicates if there is mismatch with negotiation results. */ 1841 u32 error; 1842 #define DCBX_LOCAL_ETS_ERROR 0x00000001 1843 #define DCBX_LOCAL_PFC_ERROR 0x00000002 1844 #define DCBX_LOCAL_APP_ERROR 0x00000004 1845 #define DCBX_LOCAL_PFC_MISMATCH 0x00000010 1846 #define DCBX_LOCAL_APP_MISMATCH 0x00000020 1847 #define DCBX_REMOTE_MIB_ERROR 0x00000040 1848 struct dcbx_features features; 1849 u32 suffix_seq_num; 1850 }; 1851 /***END OF DCBX STRUCTURES DECLARATIONS***/ 1852 1853 struct ncsi_oem_fcoe_features { 1854 u32 fcoe_features1; 1855 #define FCOE_FEATURES1_IOS_PER_CONNECTION_MASK 0x0000FFFF 1856 #define FCOE_FEATURES1_IOS_PER_CONNECTION_OFFSET 0 1857 1858 #define FCOE_FEATURES1_LOGINS_PER_PORT_MASK 0xFFFF0000 1859 #define FCOE_FEATURES1_LOGINS_PER_PORT_OFFSET 16 1860 1861 u32 fcoe_features2; 1862 #define FCOE_FEATURES2_EXCHANGES_MASK 0x0000FFFF 1863 #define FCOE_FEATURES2_EXCHANGES_OFFSET 0 1864 1865 #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_MASK 0xFFFF0000 1866 #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_OFFSET 16 1867 1868 u32 fcoe_features3; 1869 #define FCOE_FEATURES3_TARGETS_SUPPORTED_MASK 0x0000FFFF 1870 #define FCOE_FEATURES3_TARGETS_SUPPORTED_OFFSET 0 1871 1872 #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_MASK 0xFFFF0000 1873 #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_OFFSET 16 1874 1875 u32 fcoe_features4; 1876 #define FCOE_FEATURES4_FEATURE_SETTINGS_MASK 0x0000000F 1877 #define FCOE_FEATURES4_FEATURE_SETTINGS_OFFSET 0 1878 }; 1879 1880 struct ncsi_oem_data { 1881 u32 driver_version[4]; 1882 struct ncsi_oem_fcoe_features ncsi_oem_fcoe_features; 1883 }; 1884 1885 struct shmem2_region { 1886 1887 u32 size; /* 0x0000 */ 1888 1889 u32 dcc_support; /* 0x0004 */ 1890 #define SHMEM_DCC_SUPPORT_NONE 0x00000000 1891 #define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV 0x00000001 1892 #define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV 0x00000004 1893 #define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV 0x00000008 1894 #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040 1895 #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080 1896 1897 u32 ext_phy_fw_version2[PORT_MAX]; /* 0x0008 */ 1898 /* 1899 * For backwards compatibility, if the mf_cfg_addr does not exist 1900 * (the size filed is smaller than 0xc) the mf_cfg resides at the 1901 * end of struct shmem_region 1902 */ 1903 u32 mf_cfg_addr; /* 0x0010 */ 1904 #define SHMEM_MF_CFG_ADDR_NONE 0x00000000 1905 1906 struct fw_flr_mb flr_mb; /* 0x0014 */ 1907 u32 dcbx_lldp_params_offset; /* 0x0028 */ 1908 #define SHMEM_LLDP_DCBX_PARAMS_NONE 0x00000000 1909 u32 dcbx_neg_res_offset; /* 0x002c */ 1910 #define SHMEM_DCBX_NEG_RES_NONE 0x00000000 1911 u32 dcbx_remote_mib_offset; /* 0x0030 */ 1912 #define SHMEM_DCBX_REMOTE_MIB_NONE 0x00000000 1913 /* 1914 * The other shmemX_base_addr holds the other path's shmem address 1915 * required for example in case of common phy init, or for path1 to know 1916 * the address of mcp debug trace which is located in offset from shmem 1917 * of path0 1918 */ 1919 u32 other_shmem_base_addr; /* 0x0034 */ 1920 u32 other_shmem2_base_addr; /* 0x0038 */ 1921 /* 1922 * mcp_vf_disabled is set by the MCP to indicate the driver about VFs 1923 * which were disabled/flred 1924 */ 1925 u32 mcp_vf_disabled[E2_VF_MAX / 32]; /* 0x003c */ 1926 1927 /* 1928 * drv_ack_vf_disabled is set by the PF driver to ack handled disabled 1929 * VFs 1930 */ 1931 u32 drv_ack_vf_disabled[E2_FUNC_MAX][E2_VF_MAX / 32]; /* 0x0044 */ 1932 1933 u32 dcbx_lldp_dcbx_stat_offset; /* 0x0064 */ 1934 #define SHMEM_LLDP_DCBX_STAT_NONE 0x00000000 1935 1936 /* 1937 * edebug_driver_if field is used to transfer messages between edebug 1938 * app to the driver through shmem2. 1939 * 1940 * message format: 1941 * bits 0-2 - function number / instance of driver to perform request 1942 * bits 3-5 - op code / is_ack? 1943 * bits 6-63 - data 1944 */ 1945 u32 edebug_driver_if[2]; /* 0x0068 */ 1946 #define EDEBUG_DRIVER_IF_OP_CODE_GET_PHYS_ADDR 1 1947 #define EDEBUG_DRIVER_IF_OP_CODE_GET_BUS_ADDR 2 1948 #define EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT 3 1949 1950 u32 nvm_retain_bitmap_addr; /* 0x0070 */ 1951 1952 u32 reserved1; /* 0x0074 */ 1953 1954 u32 reserved2[E2_FUNC_MAX]; 1955 1956 u32 reserved3[E2_FUNC_MAX];/* 0x0088 */ 1957 u32 reserved4[E2_FUNC_MAX];/* 0x0098 */ 1958 1959 u32 swim_base_addr; /* 0x0108 */ 1960 u32 swim_funcs; 1961 u32 swim_main_cb; 1962 1963 u32 reserved5[2]; 1964 1965 /* generic flags controlled by the driver */ 1966 u32 drv_flags; 1967 #define DRV_FLAGS_DCB_CONFIGURED 0x1 1968 1969 /* pointer to extended dev_info shared data copied from nvm image */ 1970 u32 extended_dev_info_shared_addr; 1971 u32 ncsi_oem_data_addr; 1972 1973 u32 ocsd_host_addr; /* initialized by option ROM */ 1974 u32 ocbb_host_addr; /* initialized by option ROM */ 1975 u32 ocsd_req_update_interval; /* initialized by option ROM */ 1976 u32 temperature_in_half_celsius; 1977 u32 glob_struct_in_host; 1978 1979 u32 dcbx_neg_res_ext_offset; 1980 #define SHMEM_DCBX_NEG_RES_EXT_NONE 0x00000000 1981 1982 u32 drv_capabilities_flag[E2_FUNC_MAX]; 1983 #define DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED 0x00000001 1984 #define DRV_FLAGS_CAPABILITIES_LOADED_L2 0x00000002 1985 #define DRV_FLAGS_CAPABILITIES_LOADED_FCOE 0x00000004 1986 #define DRV_FLAGS_CAPABILITIES_LOADED_ISCSI 0x00000008 1987 1988 u32 extended_dev_info_shared_cfg_size; 1989 1990 u32 dcbx_en[PORT_MAX]; 1991 1992 /* The offset points to the multi threaded meta structure */ 1993 u32 multi_thread_data_offset; 1994 1995 /* address of DMAable host address holding values from the drivers */ 1996 u32 drv_info_host_addr_lo; 1997 u32 drv_info_host_addr_hi; 1998 1999 /* general values written by the MFW (such as current version) */ 2000 u32 drv_info_control; 2001 #define DRV_INFO_CONTROL_VER_MASK 0x000000ff 2002 #define DRV_INFO_CONTROL_VER_SHIFT 0 2003 #define DRV_INFO_CONTROL_OP_CODE_MASK 0x0000ff00 2004 #define DRV_INFO_CONTROL_OP_CODE_SHIFT 8 2005 }; 2006 2007 2008 struct emac_stats { 2009 u32 rx_stat_ifhcinoctets; 2010 u32 rx_stat_ifhcinbadoctets; 2011 u32 rx_stat_etherstatsfragments; 2012 u32 rx_stat_ifhcinucastpkts; 2013 u32 rx_stat_ifhcinmulticastpkts; 2014 u32 rx_stat_ifhcinbroadcastpkts; 2015 u32 rx_stat_dot3statsfcserrors; 2016 u32 rx_stat_dot3statsalignmenterrors; 2017 u32 rx_stat_dot3statscarriersenseerrors; 2018 u32 rx_stat_xonpauseframesreceived; 2019 u32 rx_stat_xoffpauseframesreceived; 2020 u32 rx_stat_maccontrolframesreceived; 2021 u32 rx_stat_xoffstateentered; 2022 u32 rx_stat_dot3statsframestoolong; 2023 u32 rx_stat_etherstatsjabbers; 2024 u32 rx_stat_etherstatsundersizepkts; 2025 u32 rx_stat_etherstatspkts64octets; 2026 u32 rx_stat_etherstatspkts65octetsto127octets; 2027 u32 rx_stat_etherstatspkts128octetsto255octets; 2028 u32 rx_stat_etherstatspkts256octetsto511octets; 2029 u32 rx_stat_etherstatspkts512octetsto1023octets; 2030 u32 rx_stat_etherstatspkts1024octetsto1522octets; 2031 u32 rx_stat_etherstatspktsover1522octets; 2032 2033 u32 rx_stat_falsecarriererrors; 2034 2035 u32 tx_stat_ifhcoutoctets; 2036 u32 tx_stat_ifhcoutbadoctets; 2037 u32 tx_stat_etherstatscollisions; 2038 u32 tx_stat_outxonsent; 2039 u32 tx_stat_outxoffsent; 2040 u32 tx_stat_flowcontroldone; 2041 u32 tx_stat_dot3statssinglecollisionframes; 2042 u32 tx_stat_dot3statsmultiplecollisionframes; 2043 u32 tx_stat_dot3statsdeferredtransmissions; 2044 u32 tx_stat_dot3statsexcessivecollisions; 2045 u32 tx_stat_dot3statslatecollisions; 2046 u32 tx_stat_ifhcoutucastpkts; 2047 u32 tx_stat_ifhcoutmulticastpkts; 2048 u32 tx_stat_ifhcoutbroadcastpkts; 2049 u32 tx_stat_etherstatspkts64octets; 2050 u32 tx_stat_etherstatspkts65octetsto127octets; 2051 u32 tx_stat_etherstatspkts128octetsto255octets; 2052 u32 tx_stat_etherstatspkts256octetsto511octets; 2053 u32 tx_stat_etherstatspkts512octetsto1023octets; 2054 u32 tx_stat_etherstatspkts1024octetsto1522octets; 2055 u32 tx_stat_etherstatspktsover1522octets; 2056 u32 tx_stat_dot3statsinternalmactransmiterrors; 2057 }; 2058 2059 2060 struct bmac1_stats { 2061 u32 tx_stat_gtpkt_lo; 2062 u32 tx_stat_gtpkt_hi; 2063 u32 tx_stat_gtxpf_lo; 2064 u32 tx_stat_gtxpf_hi; 2065 u32 tx_stat_gtfcs_lo; 2066 u32 tx_stat_gtfcs_hi; 2067 u32 tx_stat_gtmca_lo; 2068 u32 tx_stat_gtmca_hi; 2069 u32 tx_stat_gtbca_lo; 2070 u32 tx_stat_gtbca_hi; 2071 u32 tx_stat_gtfrg_lo; 2072 u32 tx_stat_gtfrg_hi; 2073 u32 tx_stat_gtovr_lo; 2074 u32 tx_stat_gtovr_hi; 2075 u32 tx_stat_gt64_lo; 2076 u32 tx_stat_gt64_hi; 2077 u32 tx_stat_gt127_lo; 2078 u32 tx_stat_gt127_hi; 2079 u32 tx_stat_gt255_lo; 2080 u32 tx_stat_gt255_hi; 2081 u32 tx_stat_gt511_lo; 2082 u32 tx_stat_gt511_hi; 2083 u32 tx_stat_gt1023_lo; 2084 u32 tx_stat_gt1023_hi; 2085 u32 tx_stat_gt1518_lo; 2086 u32 tx_stat_gt1518_hi; 2087 u32 tx_stat_gt2047_lo; 2088 u32 tx_stat_gt2047_hi; 2089 u32 tx_stat_gt4095_lo; 2090 u32 tx_stat_gt4095_hi; 2091 u32 tx_stat_gt9216_lo; 2092 u32 tx_stat_gt9216_hi; 2093 u32 tx_stat_gt16383_lo; 2094 u32 tx_stat_gt16383_hi; 2095 u32 tx_stat_gtmax_lo; 2096 u32 tx_stat_gtmax_hi; 2097 u32 tx_stat_gtufl_lo; 2098 u32 tx_stat_gtufl_hi; 2099 u32 tx_stat_gterr_lo; 2100 u32 tx_stat_gterr_hi; 2101 u32 tx_stat_gtbyt_lo; 2102 u32 tx_stat_gtbyt_hi; 2103 2104 u32 rx_stat_gr64_lo; 2105 u32 rx_stat_gr64_hi; 2106 u32 rx_stat_gr127_lo; 2107 u32 rx_stat_gr127_hi; 2108 u32 rx_stat_gr255_lo; 2109 u32 rx_stat_gr255_hi; 2110 u32 rx_stat_gr511_lo; 2111 u32 rx_stat_gr511_hi; 2112 u32 rx_stat_gr1023_lo; 2113 u32 rx_stat_gr1023_hi; 2114 u32 rx_stat_gr1518_lo; 2115 u32 rx_stat_gr1518_hi; 2116 u32 rx_stat_gr2047_lo; 2117 u32 rx_stat_gr2047_hi; 2118 u32 rx_stat_gr4095_lo; 2119 u32 rx_stat_gr4095_hi; 2120 u32 rx_stat_gr9216_lo; 2121 u32 rx_stat_gr9216_hi; 2122 u32 rx_stat_gr16383_lo; 2123 u32 rx_stat_gr16383_hi; 2124 u32 rx_stat_grmax_lo; 2125 u32 rx_stat_grmax_hi; 2126 u32 rx_stat_grpkt_lo; 2127 u32 rx_stat_grpkt_hi; 2128 u32 rx_stat_grfcs_lo; 2129 u32 rx_stat_grfcs_hi; 2130 u32 rx_stat_grmca_lo; 2131 u32 rx_stat_grmca_hi; 2132 u32 rx_stat_grbca_lo; 2133 u32 rx_stat_grbca_hi; 2134 u32 rx_stat_grxcf_lo; 2135 u32 rx_stat_grxcf_hi; 2136 u32 rx_stat_grxpf_lo; 2137 u32 rx_stat_grxpf_hi; 2138 u32 rx_stat_grxuo_lo; 2139 u32 rx_stat_grxuo_hi; 2140 u32 rx_stat_grjbr_lo; 2141 u32 rx_stat_grjbr_hi; 2142 u32 rx_stat_grovr_lo; 2143 u32 rx_stat_grovr_hi; 2144 u32 rx_stat_grflr_lo; 2145 u32 rx_stat_grflr_hi; 2146 u32 rx_stat_grmeg_lo; 2147 u32 rx_stat_grmeg_hi; 2148 u32 rx_stat_grmeb_lo; 2149 u32 rx_stat_grmeb_hi; 2150 u32 rx_stat_grbyt_lo; 2151 u32 rx_stat_grbyt_hi; 2152 u32 rx_stat_grund_lo; 2153 u32 rx_stat_grund_hi; 2154 u32 rx_stat_grfrg_lo; 2155 u32 rx_stat_grfrg_hi; 2156 u32 rx_stat_grerb_lo; 2157 u32 rx_stat_grerb_hi; 2158 u32 rx_stat_grfre_lo; 2159 u32 rx_stat_grfre_hi; 2160 u32 rx_stat_gripj_lo; 2161 u32 rx_stat_gripj_hi; 2162 }; 2163 2164 struct bmac2_stats { 2165 u32 tx_stat_gtpk_lo; /* gtpok */ 2166 u32 tx_stat_gtpk_hi; /* gtpok */ 2167 u32 tx_stat_gtxpf_lo; /* gtpf */ 2168 u32 tx_stat_gtxpf_hi; /* gtpf */ 2169 u32 tx_stat_gtpp_lo; /* NEW BMAC2 */ 2170 u32 tx_stat_gtpp_hi; /* NEW BMAC2 */ 2171 u32 tx_stat_gtfcs_lo; 2172 u32 tx_stat_gtfcs_hi; 2173 u32 tx_stat_gtuca_lo; /* NEW BMAC2 */ 2174 u32 tx_stat_gtuca_hi; /* NEW BMAC2 */ 2175 u32 tx_stat_gtmca_lo; 2176 u32 tx_stat_gtmca_hi; 2177 u32 tx_stat_gtbca_lo; 2178 u32 tx_stat_gtbca_hi; 2179 u32 tx_stat_gtovr_lo; 2180 u32 tx_stat_gtovr_hi; 2181 u32 tx_stat_gtfrg_lo; 2182 u32 tx_stat_gtfrg_hi; 2183 u32 tx_stat_gtpkt1_lo; /* gtpkt */ 2184 u32 tx_stat_gtpkt1_hi; /* gtpkt */ 2185 u32 tx_stat_gt64_lo; 2186 u32 tx_stat_gt64_hi; 2187 u32 tx_stat_gt127_lo; 2188 u32 tx_stat_gt127_hi; 2189 u32 tx_stat_gt255_lo; 2190 u32 tx_stat_gt255_hi; 2191 u32 tx_stat_gt511_lo; 2192 u32 tx_stat_gt511_hi; 2193 u32 tx_stat_gt1023_lo; 2194 u32 tx_stat_gt1023_hi; 2195 u32 tx_stat_gt1518_lo; 2196 u32 tx_stat_gt1518_hi; 2197 u32 tx_stat_gt2047_lo; 2198 u32 tx_stat_gt2047_hi; 2199 u32 tx_stat_gt4095_lo; 2200 u32 tx_stat_gt4095_hi; 2201 u32 tx_stat_gt9216_lo; 2202 u32 tx_stat_gt9216_hi; 2203 u32 tx_stat_gt16383_lo; 2204 u32 tx_stat_gt16383_hi; 2205 u32 tx_stat_gtmax_lo; 2206 u32 tx_stat_gtmax_hi; 2207 u32 tx_stat_gtufl_lo; 2208 u32 tx_stat_gtufl_hi; 2209 u32 tx_stat_gterr_lo; 2210 u32 tx_stat_gterr_hi; 2211 u32 tx_stat_gtbyt_lo; 2212 u32 tx_stat_gtbyt_hi; 2213 2214 u32 rx_stat_gr64_lo; 2215 u32 rx_stat_gr64_hi; 2216 u32 rx_stat_gr127_lo; 2217 u32 rx_stat_gr127_hi; 2218 u32 rx_stat_gr255_lo; 2219 u32 rx_stat_gr255_hi; 2220 u32 rx_stat_gr511_lo; 2221 u32 rx_stat_gr511_hi; 2222 u32 rx_stat_gr1023_lo; 2223 u32 rx_stat_gr1023_hi; 2224 u32 rx_stat_gr1518_lo; 2225 u32 rx_stat_gr1518_hi; 2226 u32 rx_stat_gr2047_lo; 2227 u32 rx_stat_gr2047_hi; 2228 u32 rx_stat_gr4095_lo; 2229 u32 rx_stat_gr4095_hi; 2230 u32 rx_stat_gr9216_lo; 2231 u32 rx_stat_gr9216_hi; 2232 u32 rx_stat_gr16383_lo; 2233 u32 rx_stat_gr16383_hi; 2234 u32 rx_stat_grmax_lo; 2235 u32 rx_stat_grmax_hi; 2236 u32 rx_stat_grpkt_lo; 2237 u32 rx_stat_grpkt_hi; 2238 u32 rx_stat_grfcs_lo; 2239 u32 rx_stat_grfcs_hi; 2240 u32 rx_stat_gruca_lo; 2241 u32 rx_stat_gruca_hi; 2242 u32 rx_stat_grmca_lo; 2243 u32 rx_stat_grmca_hi; 2244 u32 rx_stat_grbca_lo; 2245 u32 rx_stat_grbca_hi; 2246 u32 rx_stat_grxpf_lo; /* grpf */ 2247 u32 rx_stat_grxpf_hi; /* grpf */ 2248 u32 rx_stat_grpp_lo; 2249 u32 rx_stat_grpp_hi; 2250 u32 rx_stat_grxuo_lo; /* gruo */ 2251 u32 rx_stat_grxuo_hi; /* gruo */ 2252 u32 rx_stat_grjbr_lo; 2253 u32 rx_stat_grjbr_hi; 2254 u32 rx_stat_grovr_lo; 2255 u32 rx_stat_grovr_hi; 2256 u32 rx_stat_grxcf_lo; /* grcf */ 2257 u32 rx_stat_grxcf_hi; /* grcf */ 2258 u32 rx_stat_grflr_lo; 2259 u32 rx_stat_grflr_hi; 2260 u32 rx_stat_grpok_lo; 2261 u32 rx_stat_grpok_hi; 2262 u32 rx_stat_grmeg_lo; 2263 u32 rx_stat_grmeg_hi; 2264 u32 rx_stat_grmeb_lo; 2265 u32 rx_stat_grmeb_hi; 2266 u32 rx_stat_grbyt_lo; 2267 u32 rx_stat_grbyt_hi; 2268 u32 rx_stat_grund_lo; 2269 u32 rx_stat_grund_hi; 2270 u32 rx_stat_grfrg_lo; 2271 u32 rx_stat_grfrg_hi; 2272 u32 rx_stat_grerb_lo; /* grerrbyt */ 2273 u32 rx_stat_grerb_hi; /* grerrbyt */ 2274 u32 rx_stat_grfre_lo; /* grfrerr */ 2275 u32 rx_stat_grfre_hi; /* grfrerr */ 2276 u32 rx_stat_gripj_lo; 2277 u32 rx_stat_gripj_hi; 2278 }; 2279 2280 struct mstat_stats { 2281 struct { 2282 /* OTE MSTAT on E3 has a bug where this register's contents are 2283 * actually tx_gtxpok + tx_gtxpf + (possibly)tx_gtxpp 2284 */ 2285 u32 tx_gtxpok_lo; 2286 u32 tx_gtxpok_hi; 2287 u32 tx_gtxpf_lo; 2288 u32 tx_gtxpf_hi; 2289 u32 tx_gtxpp_lo; 2290 u32 tx_gtxpp_hi; 2291 u32 tx_gtfcs_lo; 2292 u32 tx_gtfcs_hi; 2293 u32 tx_gtuca_lo; 2294 u32 tx_gtuca_hi; 2295 u32 tx_gtmca_lo; 2296 u32 tx_gtmca_hi; 2297 u32 tx_gtgca_lo; 2298 u32 tx_gtgca_hi; 2299 u32 tx_gtpkt_lo; 2300 u32 tx_gtpkt_hi; 2301 u32 tx_gt64_lo; 2302 u32 tx_gt64_hi; 2303 u32 tx_gt127_lo; 2304 u32 tx_gt127_hi; 2305 u32 tx_gt255_lo; 2306 u32 tx_gt255_hi; 2307 u32 tx_gt511_lo; 2308 u32 tx_gt511_hi; 2309 u32 tx_gt1023_lo; 2310 u32 tx_gt1023_hi; 2311 u32 tx_gt1518_lo; 2312 u32 tx_gt1518_hi; 2313 u32 tx_gt2047_lo; 2314 u32 tx_gt2047_hi; 2315 u32 tx_gt4095_lo; 2316 u32 tx_gt4095_hi; 2317 u32 tx_gt9216_lo; 2318 u32 tx_gt9216_hi; 2319 u32 tx_gt16383_lo; 2320 u32 tx_gt16383_hi; 2321 u32 tx_gtufl_lo; 2322 u32 tx_gtufl_hi; 2323 u32 tx_gterr_lo; 2324 u32 tx_gterr_hi; 2325 u32 tx_gtbyt_lo; 2326 u32 tx_gtbyt_hi; 2327 u32 tx_collisions_lo; 2328 u32 tx_collisions_hi; 2329 u32 tx_singlecollision_lo; 2330 u32 tx_singlecollision_hi; 2331 u32 tx_multiplecollisions_lo; 2332 u32 tx_multiplecollisions_hi; 2333 u32 tx_deferred_lo; 2334 u32 tx_deferred_hi; 2335 u32 tx_excessivecollisions_lo; 2336 u32 tx_excessivecollisions_hi; 2337 u32 tx_latecollisions_lo; 2338 u32 tx_latecollisions_hi; 2339 } stats_tx; 2340 2341 struct { 2342 u32 rx_gr64_lo; 2343 u32 rx_gr64_hi; 2344 u32 rx_gr127_lo; 2345 u32 rx_gr127_hi; 2346 u32 rx_gr255_lo; 2347 u32 rx_gr255_hi; 2348 u32 rx_gr511_lo; 2349 u32 rx_gr511_hi; 2350 u32 rx_gr1023_lo; 2351 u32 rx_gr1023_hi; 2352 u32 rx_gr1518_lo; 2353 u32 rx_gr1518_hi; 2354 u32 rx_gr2047_lo; 2355 u32 rx_gr2047_hi; 2356 u32 rx_gr4095_lo; 2357 u32 rx_gr4095_hi; 2358 u32 rx_gr9216_lo; 2359 u32 rx_gr9216_hi; 2360 u32 rx_gr16383_lo; 2361 u32 rx_gr16383_hi; 2362 u32 rx_grpkt_lo; 2363 u32 rx_grpkt_hi; 2364 u32 rx_grfcs_lo; 2365 u32 rx_grfcs_hi; 2366 u32 rx_gruca_lo; 2367 u32 rx_gruca_hi; 2368 u32 rx_grmca_lo; 2369 u32 rx_grmca_hi; 2370 u32 rx_grbca_lo; 2371 u32 rx_grbca_hi; 2372 u32 rx_grxpf_lo; 2373 u32 rx_grxpf_hi; 2374 u32 rx_grxpp_lo; 2375 u32 rx_grxpp_hi; 2376 u32 rx_grxuo_lo; 2377 u32 rx_grxuo_hi; 2378 u32 rx_grovr_lo; 2379 u32 rx_grovr_hi; 2380 u32 rx_grxcf_lo; 2381 u32 rx_grxcf_hi; 2382 u32 rx_grflr_lo; 2383 u32 rx_grflr_hi; 2384 u32 rx_grpok_lo; 2385 u32 rx_grpok_hi; 2386 u32 rx_grbyt_lo; 2387 u32 rx_grbyt_hi; 2388 u32 rx_grund_lo; 2389 u32 rx_grund_hi; 2390 u32 rx_grfrg_lo; 2391 u32 rx_grfrg_hi; 2392 u32 rx_grerb_lo; 2393 u32 rx_grerb_hi; 2394 u32 rx_grfre_lo; 2395 u32 rx_grfre_hi; 2396 2397 u32 rx_alignmenterrors_lo; 2398 u32 rx_alignmenterrors_hi; 2399 u32 rx_falsecarrier_lo; 2400 u32 rx_falsecarrier_hi; 2401 u32 rx_llfcmsgcnt_lo; 2402 u32 rx_llfcmsgcnt_hi; 2403 } stats_rx; 2404 }; 2405 2406 union mac_stats { 2407 struct emac_stats emac_stats; 2408 struct bmac1_stats bmac1_stats; 2409 struct bmac2_stats bmac2_stats; 2410 struct mstat_stats mstat_stats; 2411 }; 2412 2413 2414 struct mac_stx { 2415 /* in_bad_octets */ 2416 u32 rx_stat_ifhcinbadoctets_hi; 2417 u32 rx_stat_ifhcinbadoctets_lo; 2418 2419 /* out_bad_octets */ 2420 u32 tx_stat_ifhcoutbadoctets_hi; 2421 u32 tx_stat_ifhcoutbadoctets_lo; 2422 2423 /* crc_receive_errors */ 2424 u32 rx_stat_dot3statsfcserrors_hi; 2425 u32 rx_stat_dot3statsfcserrors_lo; 2426 /* alignment_errors */ 2427 u32 rx_stat_dot3statsalignmenterrors_hi; 2428 u32 rx_stat_dot3statsalignmenterrors_lo; 2429 /* carrier_sense_errors */ 2430 u32 rx_stat_dot3statscarriersenseerrors_hi; 2431 u32 rx_stat_dot3statscarriersenseerrors_lo; 2432 /* false_carrier_detections */ 2433 u32 rx_stat_falsecarriererrors_hi; 2434 u32 rx_stat_falsecarriererrors_lo; 2435 2436 /* runt_packets_received */ 2437 u32 rx_stat_etherstatsundersizepkts_hi; 2438 u32 rx_stat_etherstatsundersizepkts_lo; 2439 /* jabber_packets_received */ 2440 u32 rx_stat_dot3statsframestoolong_hi; 2441 u32 rx_stat_dot3statsframestoolong_lo; 2442 2443 /* error_runt_packets_received */ 2444 u32 rx_stat_etherstatsfragments_hi; 2445 u32 rx_stat_etherstatsfragments_lo; 2446 /* error_jabber_packets_received */ 2447 u32 rx_stat_etherstatsjabbers_hi; 2448 u32 rx_stat_etherstatsjabbers_lo; 2449 2450 /* control_frames_received */ 2451 u32 rx_stat_maccontrolframesreceived_hi; 2452 u32 rx_stat_maccontrolframesreceived_lo; 2453 u32 rx_stat_mac_xpf_hi; 2454 u32 rx_stat_mac_xpf_lo; 2455 u32 rx_stat_mac_xcf_hi; 2456 u32 rx_stat_mac_xcf_lo; 2457 2458 /* xoff_state_entered */ 2459 u32 rx_stat_xoffstateentered_hi; 2460 u32 rx_stat_xoffstateentered_lo; 2461 /* pause_xon_frames_received */ 2462 u32 rx_stat_xonpauseframesreceived_hi; 2463 u32 rx_stat_xonpauseframesreceived_lo; 2464 /* pause_xoff_frames_received */ 2465 u32 rx_stat_xoffpauseframesreceived_hi; 2466 u32 rx_stat_xoffpauseframesreceived_lo; 2467 /* pause_xon_frames_transmitted */ 2468 u32 tx_stat_outxonsent_hi; 2469 u32 tx_stat_outxonsent_lo; 2470 /* pause_xoff_frames_transmitted */ 2471 u32 tx_stat_outxoffsent_hi; 2472 u32 tx_stat_outxoffsent_lo; 2473 /* flow_control_done */ 2474 u32 tx_stat_flowcontroldone_hi; 2475 u32 tx_stat_flowcontroldone_lo; 2476 2477 /* ether_stats_collisions */ 2478 u32 tx_stat_etherstatscollisions_hi; 2479 u32 tx_stat_etherstatscollisions_lo; 2480 /* single_collision_transmit_frames */ 2481 u32 tx_stat_dot3statssinglecollisionframes_hi; 2482 u32 tx_stat_dot3statssinglecollisionframes_lo; 2483 /* multiple_collision_transmit_frames */ 2484 u32 tx_stat_dot3statsmultiplecollisionframes_hi; 2485 u32 tx_stat_dot3statsmultiplecollisionframes_lo; 2486 /* deferred_transmissions */ 2487 u32 tx_stat_dot3statsdeferredtransmissions_hi; 2488 u32 tx_stat_dot3statsdeferredtransmissions_lo; 2489 /* excessive_collision_frames */ 2490 u32 tx_stat_dot3statsexcessivecollisions_hi; 2491 u32 tx_stat_dot3statsexcessivecollisions_lo; 2492 /* late_collision_frames */ 2493 u32 tx_stat_dot3statslatecollisions_hi; 2494 u32 tx_stat_dot3statslatecollisions_lo; 2495 2496 /* frames_transmitted_64_bytes */ 2497 u32 tx_stat_etherstatspkts64octets_hi; 2498 u32 tx_stat_etherstatspkts64octets_lo; 2499 /* frames_transmitted_65_127_bytes */ 2500 u32 tx_stat_etherstatspkts65octetsto127octets_hi; 2501 u32 tx_stat_etherstatspkts65octetsto127octets_lo; 2502 /* frames_transmitted_128_255_bytes */ 2503 u32 tx_stat_etherstatspkts128octetsto255octets_hi; 2504 u32 tx_stat_etherstatspkts128octetsto255octets_lo; 2505 /* frames_transmitted_256_511_bytes */ 2506 u32 tx_stat_etherstatspkts256octetsto511octets_hi; 2507 u32 tx_stat_etherstatspkts256octetsto511octets_lo; 2508 /* frames_transmitted_512_1023_bytes */ 2509 u32 tx_stat_etherstatspkts512octetsto1023octets_hi; 2510 u32 tx_stat_etherstatspkts512octetsto1023octets_lo; 2511 /* frames_transmitted_1024_1522_bytes */ 2512 u32 tx_stat_etherstatspkts1024octetsto1522octets_hi; 2513 u32 tx_stat_etherstatspkts1024octetsto1522octets_lo; 2514 /* frames_transmitted_1523_9022_bytes */ 2515 u32 tx_stat_etherstatspktsover1522octets_hi; 2516 u32 tx_stat_etherstatspktsover1522octets_lo; 2517 u32 tx_stat_mac_2047_hi; 2518 u32 tx_stat_mac_2047_lo; 2519 u32 tx_stat_mac_4095_hi; 2520 u32 tx_stat_mac_4095_lo; 2521 u32 tx_stat_mac_9216_hi; 2522 u32 tx_stat_mac_9216_lo; 2523 u32 tx_stat_mac_16383_hi; 2524 u32 tx_stat_mac_16383_lo; 2525 2526 /* internal_mac_transmit_errors */ 2527 u32 tx_stat_dot3statsinternalmactransmiterrors_hi; 2528 u32 tx_stat_dot3statsinternalmactransmiterrors_lo; 2529 2530 /* if_out_discards */ 2531 u32 tx_stat_mac_ufl_hi; 2532 u32 tx_stat_mac_ufl_lo; 2533 }; 2534 2535 2536 #define MAC_STX_IDX_MAX 2 2537 2538 struct host_port_stats { 2539 u32 host_port_stats_counter; 2540 2541 struct mac_stx mac_stx[MAC_STX_IDX_MAX]; 2542 2543 u32 brb_drop_hi; 2544 u32 brb_drop_lo; 2545 2546 u32 not_used; /* obsolete */ 2547 u32 pfc_frames_tx_hi; 2548 u32 pfc_frames_tx_lo; 2549 u32 pfc_frames_rx_hi; 2550 u32 pfc_frames_rx_lo; 2551 }; 2552 2553 2554 struct host_func_stats { 2555 u32 host_func_stats_start; 2556 2557 u32 total_bytes_received_hi; 2558 u32 total_bytes_received_lo; 2559 2560 u32 total_bytes_transmitted_hi; 2561 u32 total_bytes_transmitted_lo; 2562 2563 u32 total_unicast_packets_received_hi; 2564 u32 total_unicast_packets_received_lo; 2565 2566 u32 total_multicast_packets_received_hi; 2567 u32 total_multicast_packets_received_lo; 2568 2569 u32 total_broadcast_packets_received_hi; 2570 u32 total_broadcast_packets_received_lo; 2571 2572 u32 total_unicast_packets_transmitted_hi; 2573 u32 total_unicast_packets_transmitted_lo; 2574 2575 u32 total_multicast_packets_transmitted_hi; 2576 u32 total_multicast_packets_transmitted_lo; 2577 2578 u32 total_broadcast_packets_transmitted_hi; 2579 u32 total_broadcast_packets_transmitted_lo; 2580 2581 u32 valid_bytes_received_hi; 2582 u32 valid_bytes_received_lo; 2583 2584 u32 host_func_stats_end; 2585 }; 2586 2587 /* VIC definitions */ 2588 #define VICSTATST_UIF_INDEX 2 2589 2590 /* current drv_info version */ 2591 #define DRV_INFO_CUR_VER 1 2592 2593 /* drv_info op codes supported */ 2594 enum drv_info_opcode { 2595 ETH_STATS_OPCODE, 2596 FCOE_STATS_OPCODE, 2597 ISCSI_STATS_OPCODE 2598 }; 2599 2600 #define ETH_STAT_INFO_VERSION_LEN 12 2601 /* Per PCI Function Ethernet Statistics required from the driver */ 2602 struct eth_stats_info { 2603 /* Function's Driver Version. padded to 12 */ 2604 u8 version[ETH_STAT_INFO_VERSION_LEN]; 2605 /* Locally Admin Addr. BigEndian EIU48. Actual size is 6 bytes */ 2606 u8 mac_local[8]; 2607 u8 mac_add1[8]; /* Additional Programmed MAC Addr 1. */ 2608 u8 mac_add2[8]; /* Additional Programmed MAC Addr 2. */ 2609 u32 mtu_size; /* MTU Size. Note : Negotiated MTU */ 2610 u32 feature_flags; /* Feature_Flags. */ 2611 #define FEATURE_ETH_CHKSUM_OFFLOAD_MASK 0x01 2612 #define FEATURE_ETH_LSO_MASK 0x02 2613 #define FEATURE_ETH_BOOTMODE_MASK 0x1C 2614 #define FEATURE_ETH_BOOTMODE_SHIFT 2 2615 #define FEATURE_ETH_BOOTMODE_NONE (0x0 << 2) 2616 #define FEATURE_ETH_BOOTMODE_PXE (0x1 << 2) 2617 #define FEATURE_ETH_BOOTMODE_ISCSI (0x2 << 2) 2618 #define FEATURE_ETH_BOOTMODE_FCOE (0x3 << 2) 2619 #define FEATURE_ETH_TOE_MASK 0x20 2620 u32 lso_max_size; /* LSO MaxOffloadSize. */ 2621 u32 lso_min_seg_cnt; /* LSO MinSegmentCount. */ 2622 /* Num Offloaded Connections TCP_IPv4. */ 2623 u32 ipv4_ofld_cnt; 2624 /* Num Offloaded Connections TCP_IPv6. */ 2625 u32 ipv6_ofld_cnt; 2626 u32 promiscuous_mode; /* Promiscuous Mode. non-zero true */ 2627 u32 txq_size; /* TX Descriptors Queue Size */ 2628 u32 rxq_size; /* RX Descriptors Queue Size */ 2629 /* TX Descriptor Queue Avg Depth. % Avg Queue Depth since last poll */ 2630 u32 txq_avg_depth; 2631 /* RX Descriptors Queue Avg Depth. % Avg Queue Depth since last poll */ 2632 u32 rxq_avg_depth; 2633 /* IOV_Offload. 0=none; 1=MultiQueue, 2=VEB 3= VEPA*/ 2634 u32 iov_offload; 2635 /* Number of NetQueue/VMQ Config'd. */ 2636 u32 netq_cnt; 2637 u32 vf_cnt; /* Num VF assigned to this PF. */ 2638 }; 2639 2640 /* Per PCI Function FCOE Statistics required from the driver */ 2641 struct fcoe_stats_info { 2642 u8 version[12]; /* Function's Driver Version. */ 2643 u8 mac_local[8]; /* Locally Admin Addr. */ 2644 u8 mac_add1[8]; /* Additional Programmed MAC Addr 1. */ 2645 u8 mac_add2[8]; /* Additional Programmed MAC Addr 2. */ 2646 /* QoS Priority (per 802.1p). 0-7255 */ 2647 u32 qos_priority; 2648 u32 txq_size; /* FCoE TX Descriptors Queue Size. */ 2649 u32 rxq_size; /* FCoE RX Descriptors Queue Size. */ 2650 /* FCoE TX Descriptor Queue Avg Depth. */ 2651 u32 txq_avg_depth; 2652 /* FCoE RX Descriptors Queue Avg Depth. */ 2653 u32 rxq_avg_depth; 2654 u32 rx_frames_lo; /* FCoE RX Frames received. */ 2655 u32 rx_frames_hi; /* FCoE RX Frames received. */ 2656 u32 rx_bytes_lo; /* FCoE RX Bytes received. */ 2657 u32 rx_bytes_hi; /* FCoE RX Bytes received. */ 2658 u32 tx_frames_lo; /* FCoE TX Frames sent. */ 2659 u32 tx_frames_hi; /* FCoE TX Frames sent. */ 2660 u32 tx_bytes_lo; /* FCoE TX Bytes sent. */ 2661 u32 tx_bytes_hi; /* FCoE TX Bytes sent. */ 2662 }; 2663 2664 /* Per PCI Function iSCSI Statistics required from the driver*/ 2665 struct iscsi_stats_info { 2666 u8 version[12]; /* Function's Driver Version. */ 2667 u8 mac_local[8]; /* Locally Admin iSCSI MAC Addr. */ 2668 u8 mac_add1[8]; /* Additional Programmed MAC Addr 1. */ 2669 /* QoS Priority (per 802.1p). 0-7255 */ 2670 u32 qos_priority; 2671 u8 initiator_name[64]; /* iSCSI Boot Initiator Node name. */ 2672 u8 ww_port_name[64]; /* iSCSI World wide port name */ 2673 u8 boot_target_name[64];/* iSCSI Boot Target Name. */ 2674 u8 boot_target_ip[16]; /* iSCSI Boot Target IP. */ 2675 u32 boot_target_portal; /* iSCSI Boot Target Portal. */ 2676 u8 boot_init_ip[16]; /* iSCSI Boot Initiator IP Address. */ 2677 u32 max_frame_size; /* Max Frame Size. bytes */ 2678 u32 txq_size; /* PDU TX Descriptors Queue Size. */ 2679 u32 rxq_size; /* PDU RX Descriptors Queue Size. */ 2680 u32 txq_avg_depth; /* PDU TX Descriptor Queue Avg Depth. */ 2681 u32 rxq_avg_depth; /* PDU RX Descriptors Queue Avg Depth. */ 2682 u32 rx_pdus_lo; /* iSCSI PDUs received. */ 2683 u32 rx_pdus_hi; /* iSCSI PDUs received. */ 2684 u32 rx_bytes_lo; /* iSCSI RX Bytes received. */ 2685 u32 rx_bytes_hi; /* iSCSI RX Bytes received. */ 2686 u32 tx_pdus_lo; /* iSCSI PDUs sent. */ 2687 u32 tx_pdus_hi; /* iSCSI PDUs sent. */ 2688 u32 tx_bytes_lo; /* iSCSI PDU TX Bytes sent. */ 2689 u32 tx_bytes_hi; /* iSCSI PDU TX Bytes sent. */ 2690 u32 pcp_prior_map_tbl; /* C-PCP to S-PCP Priority MapTable. 2691 * 9 nibbles, the position of each nibble 2692 * represents the C-PCP value, the value 2693 * of the nibble = S-PCP value. 2694 */ 2695 }; 2696 2697 union drv_info_to_mcp { 2698 struct eth_stats_info ether_stat; 2699 struct fcoe_stats_info fcoe_stat; 2700 struct iscsi_stats_info iscsi_stat; 2701 }; 2702 #define BCM_5710_FW_MAJOR_VERSION 7 2703 #define BCM_5710_FW_MINOR_VERSION 0 2704 #define BCM_5710_FW_REVISION_VERSION 29 2705 #define BCM_5710_FW_ENGINEERING_VERSION 0 2706 #define BCM_5710_FW_COMPILE_FLAGS 1 2707 2708 2709 /* 2710 * attention bits 2711 */ 2712 struct atten_sp_status_block { 2713 __le32 attn_bits; 2714 __le32 attn_bits_ack; 2715 u8 status_block_id; 2716 u8 reserved0; 2717 __le16 attn_bits_index; 2718 __le32 reserved1; 2719 }; 2720 2721 2722 /* 2723 * The eth aggregative context of Cstorm 2724 */ 2725 struct cstorm_eth_ag_context { 2726 u32 __reserved0[10]; 2727 }; 2728 2729 2730 /* 2731 * dmae command structure 2732 */ 2733 struct dmae_command { 2734 u32 opcode; 2735 #define DMAE_COMMAND_SRC (0x1<<0) 2736 #define DMAE_COMMAND_SRC_SHIFT 0 2737 #define DMAE_COMMAND_DST (0x3<<1) 2738 #define DMAE_COMMAND_DST_SHIFT 1 2739 #define DMAE_COMMAND_C_DST (0x1<<3) 2740 #define DMAE_COMMAND_C_DST_SHIFT 3 2741 #define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4) 2742 #define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4 2743 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5) 2744 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5 2745 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6) 2746 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6 2747 #define DMAE_COMMAND_ENDIANITY (0x3<<9) 2748 #define DMAE_COMMAND_ENDIANITY_SHIFT 9 2749 #define DMAE_COMMAND_PORT (0x1<<11) 2750 #define DMAE_COMMAND_PORT_SHIFT 11 2751 #define DMAE_COMMAND_CRC_RESET (0x1<<12) 2752 #define DMAE_COMMAND_CRC_RESET_SHIFT 12 2753 #define DMAE_COMMAND_SRC_RESET (0x1<<13) 2754 #define DMAE_COMMAND_SRC_RESET_SHIFT 13 2755 #define DMAE_COMMAND_DST_RESET (0x1<<14) 2756 #define DMAE_COMMAND_DST_RESET_SHIFT 14 2757 #define DMAE_COMMAND_E1HVN (0x3<<15) 2758 #define DMAE_COMMAND_E1HVN_SHIFT 15 2759 #define DMAE_COMMAND_DST_VN (0x3<<17) 2760 #define DMAE_COMMAND_DST_VN_SHIFT 17 2761 #define DMAE_COMMAND_C_FUNC (0x1<<19) 2762 #define DMAE_COMMAND_C_FUNC_SHIFT 19 2763 #define DMAE_COMMAND_ERR_POLICY (0x3<<20) 2764 #define DMAE_COMMAND_ERR_POLICY_SHIFT 20 2765 #define DMAE_COMMAND_RESERVED0 (0x3FF<<22) 2766 #define DMAE_COMMAND_RESERVED0_SHIFT 22 2767 u32 src_addr_lo; 2768 u32 src_addr_hi; 2769 u32 dst_addr_lo; 2770 u32 dst_addr_hi; 2771 #if defined(__BIG_ENDIAN) 2772 u16 opcode_iov; 2773 #define DMAE_COMMAND_SRC_VFID (0x3F<<0) 2774 #define DMAE_COMMAND_SRC_VFID_SHIFT 0 2775 #define DMAE_COMMAND_SRC_VFPF (0x1<<6) 2776 #define DMAE_COMMAND_SRC_VFPF_SHIFT 6 2777 #define DMAE_COMMAND_RESERVED1 (0x1<<7) 2778 #define DMAE_COMMAND_RESERVED1_SHIFT 7 2779 #define DMAE_COMMAND_DST_VFID (0x3F<<8) 2780 #define DMAE_COMMAND_DST_VFID_SHIFT 8 2781 #define DMAE_COMMAND_DST_VFPF (0x1<<14) 2782 #define DMAE_COMMAND_DST_VFPF_SHIFT 14 2783 #define DMAE_COMMAND_RESERVED2 (0x1<<15) 2784 #define DMAE_COMMAND_RESERVED2_SHIFT 15 2785 u16 len; 2786 #elif defined(__LITTLE_ENDIAN) 2787 u16 len; 2788 u16 opcode_iov; 2789 #define DMAE_COMMAND_SRC_VFID (0x3F<<0) 2790 #define DMAE_COMMAND_SRC_VFID_SHIFT 0 2791 #define DMAE_COMMAND_SRC_VFPF (0x1<<6) 2792 #define DMAE_COMMAND_SRC_VFPF_SHIFT 6 2793 #define DMAE_COMMAND_RESERVED1 (0x1<<7) 2794 #define DMAE_COMMAND_RESERVED1_SHIFT 7 2795 #define DMAE_COMMAND_DST_VFID (0x3F<<8) 2796 #define DMAE_COMMAND_DST_VFID_SHIFT 8 2797 #define DMAE_COMMAND_DST_VFPF (0x1<<14) 2798 #define DMAE_COMMAND_DST_VFPF_SHIFT 14 2799 #define DMAE_COMMAND_RESERVED2 (0x1<<15) 2800 #define DMAE_COMMAND_RESERVED2_SHIFT 15 2801 #endif 2802 u32 comp_addr_lo; 2803 u32 comp_addr_hi; 2804 u32 comp_val; 2805 u32 crc32; 2806 u32 crc32_c; 2807 #if defined(__BIG_ENDIAN) 2808 u16 crc16_c; 2809 u16 crc16; 2810 #elif defined(__LITTLE_ENDIAN) 2811 u16 crc16; 2812 u16 crc16_c; 2813 #endif 2814 #if defined(__BIG_ENDIAN) 2815 u16 reserved3; 2816 u16 crc_t10; 2817 #elif defined(__LITTLE_ENDIAN) 2818 u16 crc_t10; 2819 u16 reserved3; 2820 #endif 2821 #if defined(__BIG_ENDIAN) 2822 u16 xsum8; 2823 u16 xsum16; 2824 #elif defined(__LITTLE_ENDIAN) 2825 u16 xsum16; 2826 u16 xsum8; 2827 #endif 2828 }; 2829 2830 2831 /* 2832 * common data for all protocols 2833 */ 2834 struct doorbell_hdr { 2835 u8 header; 2836 #define DOORBELL_HDR_RX (0x1<<0) 2837 #define DOORBELL_HDR_RX_SHIFT 0 2838 #define DOORBELL_HDR_DB_TYPE (0x1<<1) 2839 #define DOORBELL_HDR_DB_TYPE_SHIFT 1 2840 #define DOORBELL_HDR_DPM_SIZE (0x3<<2) 2841 #define DOORBELL_HDR_DPM_SIZE_SHIFT 2 2842 #define DOORBELL_HDR_CONN_TYPE (0xF<<4) 2843 #define DOORBELL_HDR_CONN_TYPE_SHIFT 4 2844 }; 2845 2846 /* 2847 * Ethernet doorbell 2848 */ 2849 struct eth_tx_doorbell { 2850 #if defined(__BIG_ENDIAN) 2851 u16 npackets; 2852 u8 params; 2853 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) 2854 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0 2855 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) 2856 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6 2857 #define ETH_TX_DOORBELL_SPARE (0x1<<7) 2858 #define ETH_TX_DOORBELL_SPARE_SHIFT 7 2859 struct doorbell_hdr hdr; 2860 #elif defined(__LITTLE_ENDIAN) 2861 struct doorbell_hdr hdr; 2862 u8 params; 2863 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) 2864 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0 2865 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) 2866 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6 2867 #define ETH_TX_DOORBELL_SPARE (0x1<<7) 2868 #define ETH_TX_DOORBELL_SPARE_SHIFT 7 2869 u16 npackets; 2870 #endif 2871 }; 2872 2873 2874 /* 2875 * 3 lines. status block 2876 */ 2877 struct hc_status_block_e1x { 2878 __le16 index_values[HC_SB_MAX_INDICES_E1X]; 2879 __le16 running_index[HC_SB_MAX_SM]; 2880 __le32 rsrv[11]; 2881 }; 2882 2883 /* 2884 * host status block 2885 */ 2886 struct host_hc_status_block_e1x { 2887 struct hc_status_block_e1x sb; 2888 }; 2889 2890 2891 /* 2892 * 3 lines. status block 2893 */ 2894 struct hc_status_block_e2 { 2895 __le16 index_values[HC_SB_MAX_INDICES_E2]; 2896 __le16 running_index[HC_SB_MAX_SM]; 2897 __le32 reserved[11]; 2898 }; 2899 2900 /* 2901 * host status block 2902 */ 2903 struct host_hc_status_block_e2 { 2904 struct hc_status_block_e2 sb; 2905 }; 2906 2907 2908 /* 2909 * 5 lines. slow-path status block 2910 */ 2911 struct hc_sp_status_block { 2912 __le16 index_values[HC_SP_SB_MAX_INDICES]; 2913 __le16 running_index; 2914 __le16 rsrv; 2915 u32 rsrv1; 2916 }; 2917 2918 /* 2919 * host status block 2920 */ 2921 struct host_sp_status_block { 2922 struct atten_sp_status_block atten_status_block; 2923 struct hc_sp_status_block sp_sb; 2924 }; 2925 2926 2927 /* 2928 * IGU driver acknowledgment register 2929 */ 2930 struct igu_ack_register { 2931 #if defined(__BIG_ENDIAN) 2932 u16 sb_id_and_flags; 2933 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) 2934 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0 2935 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5) 2936 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5 2937 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) 2938 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8 2939 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) 2940 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9 2941 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11) 2942 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11 2943 u16 status_block_index; 2944 #elif defined(__LITTLE_ENDIAN) 2945 u16 status_block_index; 2946 u16 sb_id_and_flags; 2947 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) 2948 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0 2949 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5) 2950 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5 2951 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) 2952 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8 2953 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) 2954 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9 2955 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11) 2956 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11 2957 #endif 2958 }; 2959 2960 2961 /* 2962 * IGU driver acknowledgement register 2963 */ 2964 struct igu_backward_compatible { 2965 u32 sb_id_and_flags; 2966 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0) 2967 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0 2968 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16) 2969 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16 2970 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21) 2971 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21 2972 #define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24) 2973 #define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24 2974 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25) 2975 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25 2976 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27) 2977 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27 2978 u32 reserved_2; 2979 }; 2980 2981 2982 /* 2983 * IGU driver acknowledgement register 2984 */ 2985 struct igu_regular { 2986 u32 sb_id_and_flags; 2987 #define IGU_REGULAR_SB_INDEX (0xFFFFF<<0) 2988 #define IGU_REGULAR_SB_INDEX_SHIFT 0 2989 #define IGU_REGULAR_RESERVED0 (0x1<<20) 2990 #define IGU_REGULAR_RESERVED0_SHIFT 20 2991 #define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21) 2992 #define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21 2993 #define IGU_REGULAR_BUPDATE (0x1<<24) 2994 #define IGU_REGULAR_BUPDATE_SHIFT 24 2995 #define IGU_REGULAR_ENABLE_INT (0x3<<25) 2996 #define IGU_REGULAR_ENABLE_INT_SHIFT 25 2997 #define IGU_REGULAR_RESERVED_1 (0x1<<27) 2998 #define IGU_REGULAR_RESERVED_1_SHIFT 27 2999 #define IGU_REGULAR_CLEANUP_TYPE (0x3<<28) 3000 #define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28 3001 #define IGU_REGULAR_CLEANUP_SET (0x1<<30) 3002 #define IGU_REGULAR_CLEANUP_SET_SHIFT 30 3003 #define IGU_REGULAR_BCLEANUP (0x1<<31) 3004 #define IGU_REGULAR_BCLEANUP_SHIFT 31 3005 u32 reserved_2; 3006 }; 3007 3008 /* 3009 * IGU driver acknowledgement register 3010 */ 3011 union igu_consprod_reg { 3012 struct igu_regular regular; 3013 struct igu_backward_compatible backward_compatible; 3014 }; 3015 3016 3017 /* 3018 * Igu control commands 3019 */ 3020 enum igu_ctrl_cmd { 3021 IGU_CTRL_CMD_TYPE_RD, 3022 IGU_CTRL_CMD_TYPE_WR, 3023 MAX_IGU_CTRL_CMD 3024 }; 3025 3026 3027 /* 3028 * Control register for the IGU command register 3029 */ 3030 struct igu_ctrl_reg { 3031 u32 ctrl_data; 3032 #define IGU_CTRL_REG_ADDRESS (0xFFF<<0) 3033 #define IGU_CTRL_REG_ADDRESS_SHIFT 0 3034 #define IGU_CTRL_REG_FID (0x7F<<12) 3035 #define IGU_CTRL_REG_FID_SHIFT 12 3036 #define IGU_CTRL_REG_RESERVED (0x1<<19) 3037 #define IGU_CTRL_REG_RESERVED_SHIFT 19 3038 #define IGU_CTRL_REG_TYPE (0x1<<20) 3039 #define IGU_CTRL_REG_TYPE_SHIFT 20 3040 #define IGU_CTRL_REG_UNUSED (0x7FF<<21) 3041 #define IGU_CTRL_REG_UNUSED_SHIFT 21 3042 }; 3043 3044 3045 /* 3046 * Igu interrupt command 3047 */ 3048 enum igu_int_cmd { 3049 IGU_INT_ENABLE, 3050 IGU_INT_DISABLE, 3051 IGU_INT_NOP, 3052 IGU_INT_NOP2, 3053 MAX_IGU_INT_CMD 3054 }; 3055 3056 3057 /* 3058 * Igu segments 3059 */ 3060 enum igu_seg_access { 3061 IGU_SEG_ACCESS_NORM, 3062 IGU_SEG_ACCESS_DEF, 3063 IGU_SEG_ACCESS_ATTN, 3064 MAX_IGU_SEG_ACCESS 3065 }; 3066 3067 3068 /* 3069 * Parser parsing flags field 3070 */ 3071 struct parsing_flags { 3072 __le16 flags; 3073 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0) 3074 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0 3075 #define PARSING_FLAGS_VLAN (0x1<<1) 3076 #define PARSING_FLAGS_VLAN_SHIFT 1 3077 #define PARSING_FLAGS_EXTRA_VLAN (0x1<<2) 3078 #define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2 3079 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3) 3080 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3 3081 #define PARSING_FLAGS_IP_OPTIONS (0x1<<5) 3082 #define PARSING_FLAGS_IP_OPTIONS_SHIFT 5 3083 #define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6) 3084 #define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6 3085 #define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7) 3086 #define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7 3087 #define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9) 3088 #define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9 3089 #define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10) 3090 #define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10 3091 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11) 3092 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11 3093 #define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12) 3094 #define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12 3095 #define PARSING_FLAGS_LLC_SNAP (0x1<<13) 3096 #define PARSING_FLAGS_LLC_SNAP_SHIFT 13 3097 #define PARSING_FLAGS_RESERVED0 (0x3<<14) 3098 #define PARSING_FLAGS_RESERVED0_SHIFT 14 3099 }; 3100 3101 3102 /* 3103 * Parsing flags for TCP ACK type 3104 */ 3105 enum prs_flags_ack_type { 3106 PRS_FLAG_PUREACK_PIGGY, 3107 PRS_FLAG_PUREACK_PURE, 3108 MAX_PRS_FLAGS_ACK_TYPE 3109 }; 3110 3111 3112 /* 3113 * Parsing flags for Ethernet address type 3114 */ 3115 enum prs_flags_eth_addr_type { 3116 PRS_FLAG_ETHTYPE_NON_UNICAST, 3117 PRS_FLAG_ETHTYPE_UNICAST, 3118 MAX_PRS_FLAGS_ETH_ADDR_TYPE 3119 }; 3120 3121 3122 /* 3123 * Parsing flags for over-ethernet protocol 3124 */ 3125 enum prs_flags_over_eth { 3126 PRS_FLAG_OVERETH_UNKNOWN, 3127 PRS_FLAG_OVERETH_IPV4, 3128 PRS_FLAG_OVERETH_IPV6, 3129 PRS_FLAG_OVERETH_LLCSNAP_UNKNOWN, 3130 MAX_PRS_FLAGS_OVER_ETH 3131 }; 3132 3133 3134 /* 3135 * Parsing flags for over-IP protocol 3136 */ 3137 enum prs_flags_over_ip { 3138 PRS_FLAG_OVERIP_UNKNOWN, 3139 PRS_FLAG_OVERIP_TCP, 3140 PRS_FLAG_OVERIP_UDP, 3141 MAX_PRS_FLAGS_OVER_IP 3142 }; 3143 3144 3145 /* 3146 * SDM operation gen command (generate aggregative interrupt) 3147 */ 3148 struct sdm_op_gen { 3149 __le32 command; 3150 #define SDM_OP_GEN_COMP_PARAM (0x1F<<0) 3151 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0 3152 #define SDM_OP_GEN_COMP_TYPE (0x7<<5) 3153 #define SDM_OP_GEN_COMP_TYPE_SHIFT 5 3154 #define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8) 3155 #define SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8 3156 #define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16) 3157 #define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16 3158 #define SDM_OP_GEN_RESERVED (0x7FFF<<17) 3159 #define SDM_OP_GEN_RESERVED_SHIFT 17 3160 }; 3161 3162 3163 /* 3164 * Timers connection context 3165 */ 3166 struct timers_block_context { 3167 u32 __reserved_0; 3168 u32 __reserved_1; 3169 u32 __reserved_2; 3170 u32 flags; 3171 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0) 3172 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0 3173 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2) 3174 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2 3175 #define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3) 3176 #define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3 3177 }; 3178 3179 3180 /* 3181 * The eth aggregative context of Tstorm 3182 */ 3183 struct tstorm_eth_ag_context { 3184 u32 __reserved0[14]; 3185 }; 3186 3187 3188 /* 3189 * The eth aggregative context of Ustorm 3190 */ 3191 struct ustorm_eth_ag_context { 3192 u32 __reserved0; 3193 #if defined(__BIG_ENDIAN) 3194 u8 cdu_usage; 3195 u8 __reserved2; 3196 u16 __reserved1; 3197 #elif defined(__LITTLE_ENDIAN) 3198 u16 __reserved1; 3199 u8 __reserved2; 3200 u8 cdu_usage; 3201 #endif 3202 u32 __reserved3[6]; 3203 }; 3204 3205 3206 /* 3207 * The eth aggregative context of Xstorm 3208 */ 3209 struct xstorm_eth_ag_context { 3210 u32 reserved0; 3211 #if defined(__BIG_ENDIAN) 3212 u8 cdu_reserved; 3213 u8 reserved2; 3214 u16 reserved1; 3215 #elif defined(__LITTLE_ENDIAN) 3216 u16 reserved1; 3217 u8 reserved2; 3218 u8 cdu_reserved; 3219 #endif 3220 u32 reserved3[30]; 3221 }; 3222 3223 3224 /* 3225 * doorbell message sent to the chip 3226 */ 3227 struct doorbell { 3228 #if defined(__BIG_ENDIAN) 3229 u16 zero_fill2; 3230 u8 zero_fill1; 3231 struct doorbell_hdr header; 3232 #elif defined(__LITTLE_ENDIAN) 3233 struct doorbell_hdr header; 3234 u8 zero_fill1; 3235 u16 zero_fill2; 3236 #endif 3237 }; 3238 3239 3240 /* 3241 * doorbell message sent to the chip 3242 */ 3243 struct doorbell_set_prod { 3244 #if defined(__BIG_ENDIAN) 3245 u16 prod; 3246 u8 zero_fill1; 3247 struct doorbell_hdr header; 3248 #elif defined(__LITTLE_ENDIAN) 3249 struct doorbell_hdr header; 3250 u8 zero_fill1; 3251 u16 prod; 3252 #endif 3253 }; 3254 3255 3256 struct regpair { 3257 __le32 lo; 3258 __le32 hi; 3259 }; 3260 3261 3262 /* 3263 * Classify rule opcodes in E2/E3 3264 */ 3265 enum classify_rule { 3266 CLASSIFY_RULE_OPCODE_MAC, 3267 CLASSIFY_RULE_OPCODE_VLAN, 3268 CLASSIFY_RULE_OPCODE_PAIR, 3269 MAX_CLASSIFY_RULE 3270 }; 3271 3272 3273 /* 3274 * Classify rule types in E2/E3 3275 */ 3276 enum classify_rule_action_type { 3277 CLASSIFY_RULE_REMOVE, 3278 CLASSIFY_RULE_ADD, 3279 MAX_CLASSIFY_RULE_ACTION_TYPE 3280 }; 3281 3282 3283 /* 3284 * client init ramrod data 3285 */ 3286 struct client_init_general_data { 3287 u8 client_id; 3288 u8 statistics_counter_id; 3289 u8 statistics_en_flg; 3290 u8 is_fcoe_flg; 3291 u8 activate_flg; 3292 u8 sp_client_id; 3293 __le16 mtu; 3294 u8 statistics_zero_flg; 3295 u8 func_id; 3296 u8 cos; 3297 u8 traffic_type; 3298 u32 reserved0; 3299 }; 3300 3301 3302 /* 3303 * client init rx data 3304 */ 3305 struct client_init_rx_data { 3306 u8 tpa_en; 3307 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1<<0) 3308 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4_SHIFT 0 3309 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1<<1) 3310 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6_SHIFT 1 3311 #define CLIENT_INIT_RX_DATA_RESERVED5 (0x3F<<2) 3312 #define CLIENT_INIT_RX_DATA_RESERVED5_SHIFT 2 3313 u8 vmqueue_mode_en_flg; 3314 u8 extra_data_over_sgl_en_flg; 3315 u8 cache_line_alignment_log_size; 3316 u8 enable_dynamic_hc; 3317 u8 max_sges_for_packet; 3318 u8 client_qzone_id; 3319 u8 drop_ip_cs_err_flg; 3320 u8 drop_tcp_cs_err_flg; 3321 u8 drop_ttl0_flg; 3322 u8 drop_udp_cs_err_flg; 3323 u8 inner_vlan_removal_enable_flg; 3324 u8 outer_vlan_removal_enable_flg; 3325 u8 status_block_id; 3326 u8 rx_sb_index_number; 3327 u8 reserved0; 3328 u8 max_tpa_queues; 3329 u8 silent_vlan_removal_flg; 3330 __le16 max_bytes_on_bd; 3331 __le16 sge_buff_size; 3332 u8 approx_mcast_engine_id; 3333 u8 rss_engine_id; 3334 struct regpair bd_page_base; 3335 struct regpair sge_page_base; 3336 struct regpair cqe_page_base; 3337 u8 is_leading_rss; 3338 u8 is_approx_mcast; 3339 __le16 max_agg_size; 3340 __le16 state; 3341 #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1<<0) 3342 #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL_SHIFT 0 3343 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1<<1) 3344 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL_SHIFT 1 3345 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1<<2) 3346 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED_SHIFT 2 3347 #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1<<3) 3348 #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL_SHIFT 3 3349 #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1<<4) 3350 #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL_SHIFT 4 3351 #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1<<5) 3352 #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL_SHIFT 5 3353 #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1<<6) 3354 #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN_SHIFT 6 3355 #define CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF<<7) 3356 #define CLIENT_INIT_RX_DATA_RESERVED2_SHIFT 7 3357 __le16 cqe_pause_thr_low; 3358 __le16 cqe_pause_thr_high; 3359 __le16 bd_pause_thr_low; 3360 __le16 bd_pause_thr_high; 3361 __le16 sge_pause_thr_low; 3362 __le16 sge_pause_thr_high; 3363 __le16 rx_cos_mask; 3364 __le16 silent_vlan_value; 3365 __le16 silent_vlan_mask; 3366 __le32 reserved6[2]; 3367 }; 3368 3369 /* 3370 * client init tx data 3371 */ 3372 struct client_init_tx_data { 3373 u8 enforce_security_flg; 3374 u8 tx_status_block_id; 3375 u8 tx_sb_index_number; 3376 u8 tss_leading_client_id; 3377 u8 tx_switching_flg; 3378 u8 anti_spoofing_flg; 3379 __le16 default_vlan; 3380 struct regpair tx_bd_page_base; 3381 __le16 state; 3382 #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1<<0) 3383 #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL_SHIFT 0 3384 #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1<<1) 3385 #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL_SHIFT 1 3386 #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1<<2) 3387 #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL_SHIFT 2 3388 #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1<<3) 3389 #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN_SHIFT 3 3390 #define CLIENT_INIT_TX_DATA_RESERVED1 (0xFFF<<4) 3391 #define CLIENT_INIT_TX_DATA_RESERVED1_SHIFT 4 3392 u8 default_vlan_flg; 3393 u8 reserved2; 3394 __le32 reserved3; 3395 }; 3396 3397 /* 3398 * client init ramrod data 3399 */ 3400 struct client_init_ramrod_data { 3401 struct client_init_general_data general; 3402 struct client_init_rx_data rx; 3403 struct client_init_tx_data tx; 3404 }; 3405 3406 3407 /* 3408 * client update ramrod data 3409 */ 3410 struct client_update_ramrod_data { 3411 u8 client_id; 3412 u8 func_id; 3413 u8 inner_vlan_removal_enable_flg; 3414 u8 inner_vlan_removal_change_flg; 3415 u8 outer_vlan_removal_enable_flg; 3416 u8 outer_vlan_removal_change_flg; 3417 u8 anti_spoofing_enable_flg; 3418 u8 anti_spoofing_change_flg; 3419 u8 activate_flg; 3420 u8 activate_change_flg; 3421 __le16 default_vlan; 3422 u8 default_vlan_enable_flg; 3423 u8 default_vlan_change_flg; 3424 __le16 silent_vlan_value; 3425 __le16 silent_vlan_mask; 3426 u8 silent_vlan_removal_flg; 3427 u8 silent_vlan_change_flg; 3428 __le32 echo; 3429 }; 3430 3431 3432 /* 3433 * The eth storm context of Cstorm 3434 */ 3435 struct cstorm_eth_st_context { 3436 u32 __reserved0[4]; 3437 }; 3438 3439 3440 struct double_regpair { 3441 u32 regpair0_lo; 3442 u32 regpair0_hi; 3443 u32 regpair1_lo; 3444 u32 regpair1_hi; 3445 }; 3446 3447 3448 /* 3449 * Ethernet address typesm used in ethernet tx BDs 3450 */ 3451 enum eth_addr_type { 3452 UNKNOWN_ADDRESS, 3453 UNICAST_ADDRESS, 3454 MULTICAST_ADDRESS, 3455 BROADCAST_ADDRESS, 3456 MAX_ETH_ADDR_TYPE 3457 }; 3458 3459 3460 /* 3461 * 3462 */ 3463 struct eth_classify_cmd_header { 3464 u8 cmd_general_data; 3465 #define ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1<<0) 3466 #define ETH_CLASSIFY_CMD_HEADER_RX_CMD_SHIFT 0 3467 #define ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1<<1) 3468 #define ETH_CLASSIFY_CMD_HEADER_TX_CMD_SHIFT 1 3469 #define ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3<<2) 3470 #define ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT 2 3471 #define ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1<<4) 3472 #define ETH_CLASSIFY_CMD_HEADER_IS_ADD_SHIFT 4 3473 #define ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7<<5) 3474 #define ETH_CLASSIFY_CMD_HEADER_RESERVED0_SHIFT 5 3475 u8 func_id; 3476 u8 client_id; 3477 u8 reserved1; 3478 }; 3479 3480 3481 /* 3482 * header for eth classification config ramrod 3483 */ 3484 struct eth_classify_header { 3485 u8 rule_cnt; 3486 u8 reserved0; 3487 __le16 reserved1; 3488 __le32 echo; 3489 }; 3490 3491 3492 /* 3493 * Command for adding/removing a MAC classification rule 3494 */ 3495 struct eth_classify_mac_cmd { 3496 struct eth_classify_cmd_header header; 3497 __le32 reserved0; 3498 __le16 mac_lsb; 3499 __le16 mac_mid; 3500 __le16 mac_msb; 3501 __le16 reserved1; 3502 }; 3503 3504 3505 /* 3506 * Command for adding/removing a MAC-VLAN pair classification rule 3507 */ 3508 struct eth_classify_pair_cmd { 3509 struct eth_classify_cmd_header header; 3510 __le32 reserved0; 3511 __le16 mac_lsb; 3512 __le16 mac_mid; 3513 __le16 mac_msb; 3514 __le16 vlan; 3515 }; 3516 3517 3518 /* 3519 * Command for adding/removing a VLAN classification rule 3520 */ 3521 struct eth_classify_vlan_cmd { 3522 struct eth_classify_cmd_header header; 3523 __le32 reserved0; 3524 __le32 reserved1; 3525 __le16 reserved2; 3526 __le16 vlan; 3527 }; 3528 3529 /* 3530 * union for eth classification rule 3531 */ 3532 union eth_classify_rule_cmd { 3533 struct eth_classify_mac_cmd mac; 3534 struct eth_classify_vlan_cmd vlan; 3535 struct eth_classify_pair_cmd pair; 3536 }; 3537 3538 /* 3539 * parameters for eth classification configuration ramrod 3540 */ 3541 struct eth_classify_rules_ramrod_data { 3542 struct eth_classify_header header; 3543 union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT]; 3544 }; 3545 3546 3547 /* 3548 * The data contain client ID need to the ramrod 3549 */ 3550 struct eth_common_ramrod_data { 3551 __le32 client_id; 3552 __le32 reserved1; 3553 }; 3554 3555 3556 /* 3557 * The eth storm context of Ustorm 3558 */ 3559 struct ustorm_eth_st_context { 3560 u32 reserved0[52]; 3561 }; 3562 3563 /* 3564 * The eth storm context of Tstorm 3565 */ 3566 struct tstorm_eth_st_context { 3567 u32 __reserved0[28]; 3568 }; 3569 3570 /* 3571 * The eth storm context of Xstorm 3572 */ 3573 struct xstorm_eth_st_context { 3574 u32 reserved0[60]; 3575 }; 3576 3577 /* 3578 * Ethernet connection context 3579 */ 3580 struct eth_context { 3581 struct ustorm_eth_st_context ustorm_st_context; 3582 struct tstorm_eth_st_context tstorm_st_context; 3583 struct xstorm_eth_ag_context xstorm_ag_context; 3584 struct tstorm_eth_ag_context tstorm_ag_context; 3585 struct cstorm_eth_ag_context cstorm_ag_context; 3586 struct ustorm_eth_ag_context ustorm_ag_context; 3587 struct timers_block_context timers_context; 3588 struct xstorm_eth_st_context xstorm_st_context; 3589 struct cstorm_eth_st_context cstorm_st_context; 3590 }; 3591 3592 3593 /* 3594 * union for sgl and raw data. 3595 */ 3596 union eth_sgl_or_raw_data { 3597 __le16 sgl[8]; 3598 u32 raw_data[4]; 3599 }; 3600 3601 /* 3602 * eth FP end aggregation CQE parameters struct 3603 */ 3604 struct eth_end_agg_rx_cqe { 3605 u8 type_error_flags; 3606 #define ETH_END_AGG_RX_CQE_TYPE (0x3<<0) 3607 #define ETH_END_AGG_RX_CQE_TYPE_SHIFT 0 3608 #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1<<2) 3609 #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL_SHIFT 2 3610 #define ETH_END_AGG_RX_CQE_RESERVED0 (0x1F<<3) 3611 #define ETH_END_AGG_RX_CQE_RESERVED0_SHIFT 3 3612 u8 reserved1; 3613 u8 queue_index; 3614 u8 reserved2; 3615 __le32 timestamp_delta; 3616 __le16 num_of_coalesced_segs; 3617 __le16 pkt_len; 3618 u8 pure_ack_count; 3619 u8 reserved3; 3620 __le16 reserved4; 3621 union eth_sgl_or_raw_data sgl_or_raw_data; 3622 __le32 reserved5[8]; 3623 }; 3624 3625 3626 /* 3627 * regular eth FP CQE parameters struct 3628 */ 3629 struct eth_fast_path_rx_cqe { 3630 u8 type_error_flags; 3631 #define ETH_FAST_PATH_RX_CQE_TYPE (0x3<<0) 3632 #define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0 3633 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1<<2) 3634 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 2 3635 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<3) 3636 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 3 3637 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<4) 3638 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 4 3639 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<5) 3640 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 5 3641 #define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6) 3642 #define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6 3643 u8 status_flags; 3644 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0) 3645 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0 3646 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3) 3647 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3 3648 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4) 3649 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4 3650 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5) 3651 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5 3652 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6) 3653 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6 3654 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7) 3655 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7 3656 u8 queue_index; 3657 u8 placement_offset; 3658 __le32 rss_hash_result; 3659 __le16 vlan_tag; 3660 __le16 pkt_len; 3661 __le16 len_on_bd; 3662 struct parsing_flags pars_flags; 3663 union eth_sgl_or_raw_data sgl_or_raw_data; 3664 __le32 reserved1[8]; 3665 }; 3666 3667 3668 /* 3669 * Command for setting classification flags for a client 3670 */ 3671 struct eth_filter_rules_cmd { 3672 u8 cmd_general_data; 3673 #define ETH_FILTER_RULES_CMD_RX_CMD (0x1<<0) 3674 #define ETH_FILTER_RULES_CMD_RX_CMD_SHIFT 0 3675 #define ETH_FILTER_RULES_CMD_TX_CMD (0x1<<1) 3676 #define ETH_FILTER_RULES_CMD_TX_CMD_SHIFT 1 3677 #define ETH_FILTER_RULES_CMD_RESERVED0 (0x3F<<2) 3678 #define ETH_FILTER_RULES_CMD_RESERVED0_SHIFT 2 3679 u8 func_id; 3680 u8 client_id; 3681 u8 reserved1; 3682 __le16 state; 3683 #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1<<0) 3684 #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL_SHIFT 0 3685 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1<<1) 3686 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL_SHIFT 1 3687 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1<<2) 3688 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED_SHIFT 2 3689 #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1<<3) 3690 #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL_SHIFT 3 3691 #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1<<4) 3692 #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL_SHIFT 4 3693 #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1<<5) 3694 #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL_SHIFT 5 3695 #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1<<6) 3696 #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN_SHIFT 6 3697 #define ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF<<7) 3698 #define ETH_FILTER_RULES_CMD_RESERVED2_SHIFT 7 3699 __le16 reserved3; 3700 struct regpair reserved4; 3701 }; 3702 3703 3704 /* 3705 * parameters for eth classification filters ramrod 3706 */ 3707 struct eth_filter_rules_ramrod_data { 3708 struct eth_classify_header header; 3709 struct eth_filter_rules_cmd rules[FILTER_RULES_COUNT]; 3710 }; 3711 3712 3713 /* 3714 * parameters for eth classification configuration ramrod 3715 */ 3716 struct eth_general_rules_ramrod_data { 3717 struct eth_classify_header header; 3718 union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT]; 3719 }; 3720 3721 3722 /* 3723 * The data for Halt ramrod 3724 */ 3725 struct eth_halt_ramrod_data { 3726 __le32 client_id; 3727 __le32 reserved0; 3728 }; 3729 3730 3731 /* 3732 * Command for setting multicast classification for a client 3733 */ 3734 struct eth_multicast_rules_cmd { 3735 u8 cmd_general_data; 3736 #define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1<<0) 3737 #define ETH_MULTICAST_RULES_CMD_RX_CMD_SHIFT 0 3738 #define ETH_MULTICAST_RULES_CMD_TX_CMD (0x1<<1) 3739 #define ETH_MULTICAST_RULES_CMD_TX_CMD_SHIFT 1 3740 #define ETH_MULTICAST_RULES_CMD_IS_ADD (0x1<<2) 3741 #define ETH_MULTICAST_RULES_CMD_IS_ADD_SHIFT 2 3742 #define ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F<<3) 3743 #define ETH_MULTICAST_RULES_CMD_RESERVED0_SHIFT 3 3744 u8 func_id; 3745 u8 bin_id; 3746 u8 engine_id; 3747 __le32 reserved2; 3748 struct regpair reserved3; 3749 }; 3750 3751 3752 /* 3753 * parameters for multicast classification ramrod 3754 */ 3755 struct eth_multicast_rules_ramrod_data { 3756 struct eth_classify_header header; 3757 struct eth_multicast_rules_cmd rules[MULTICAST_RULES_COUNT]; 3758 }; 3759 3760 3761 /* 3762 * Place holder for ramrods protocol specific data 3763 */ 3764 struct ramrod_data { 3765 __le32 data_lo; 3766 __le32 data_hi; 3767 }; 3768 3769 /* 3770 * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits) 3771 */ 3772 union eth_ramrod_data { 3773 struct ramrod_data general; 3774 }; 3775 3776 3777 /* 3778 * RSS toeplitz hash type, as reported in CQE 3779 */ 3780 enum eth_rss_hash_type { 3781 DEFAULT_HASH_TYPE, 3782 IPV4_HASH_TYPE, 3783 TCP_IPV4_HASH_TYPE, 3784 IPV6_HASH_TYPE, 3785 TCP_IPV6_HASH_TYPE, 3786 VLAN_PRI_HASH_TYPE, 3787 E1HOV_PRI_HASH_TYPE, 3788 DSCP_HASH_TYPE, 3789 MAX_ETH_RSS_HASH_TYPE 3790 }; 3791 3792 3793 /* 3794 * Ethernet RSS mode 3795 */ 3796 enum eth_rss_mode { 3797 ETH_RSS_MODE_DISABLED, 3798 ETH_RSS_MODE_REGULAR, 3799 ETH_RSS_MODE_VLAN_PRI, 3800 ETH_RSS_MODE_E1HOV_PRI, 3801 ETH_RSS_MODE_IP_DSCP, 3802 MAX_ETH_RSS_MODE 3803 }; 3804 3805 3806 /* 3807 * parameters for RSS update ramrod (E2) 3808 */ 3809 struct eth_rss_update_ramrod_data { 3810 u8 rss_engine_id; 3811 u8 capabilities; 3812 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1<<0) 3813 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY_SHIFT 0 3814 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1<<1) 3815 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY_SHIFT 1 3816 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1<<2) 3817 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY_SHIFT 2 3818 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<3) 3819 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 3 3820 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<4) 3821 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 4 3822 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<5) 3823 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 5 3824 #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<6) 3825 #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 6 3826 #define __ETH_RSS_UPDATE_RAMROD_DATA_RESERVED0 (0x1<<7) 3827 #define __ETH_RSS_UPDATE_RAMROD_DATA_RESERVED0_SHIFT 7 3828 u8 rss_result_mask; 3829 u8 rss_mode; 3830 __le32 __reserved2; 3831 u8 indirection_table[T_ETH_INDIRECTION_TABLE_SIZE]; 3832 __le32 rss_key[T_ETH_RSS_KEY]; 3833 __le32 echo; 3834 __le32 reserved3; 3835 }; 3836 3837 3838 /* 3839 * The eth Rx Buffer Descriptor 3840 */ 3841 struct eth_rx_bd { 3842 __le32 addr_lo; 3843 __le32 addr_hi; 3844 }; 3845 3846 3847 /* 3848 * Eth Rx Cqe structure- general structure for ramrods 3849 */ 3850 struct common_ramrod_eth_rx_cqe { 3851 u8 ramrod_type; 3852 #define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3<<0) 3853 #define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0 3854 #define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<2) 3855 #define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 2 3856 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F<<3) 3857 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 3 3858 u8 conn_type; 3859 __le16 reserved1; 3860 __le32 conn_and_cmd_data; 3861 #define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0) 3862 #define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0 3863 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24) 3864 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24 3865 struct ramrod_data protocol_data; 3866 __le32 echo; 3867 __le32 reserved2[11]; 3868 }; 3869 3870 /* 3871 * Rx Last CQE in page (in ETH) 3872 */ 3873 struct eth_rx_cqe_next_page { 3874 __le32 addr_lo; 3875 __le32 addr_hi; 3876 __le32 reserved[14]; 3877 }; 3878 3879 /* 3880 * union for all eth rx cqe types (fix their sizes) 3881 */ 3882 union eth_rx_cqe { 3883 struct eth_fast_path_rx_cqe fast_path_cqe; 3884 struct common_ramrod_eth_rx_cqe ramrod_cqe; 3885 struct eth_rx_cqe_next_page next_page_cqe; 3886 struct eth_end_agg_rx_cqe end_agg_cqe; 3887 }; 3888 3889 3890 /* 3891 * Values for RX ETH CQE type field 3892 */ 3893 enum eth_rx_cqe_type { 3894 RX_ETH_CQE_TYPE_ETH_FASTPATH, 3895 RX_ETH_CQE_TYPE_ETH_RAMROD, 3896 RX_ETH_CQE_TYPE_ETH_START_AGG, 3897 RX_ETH_CQE_TYPE_ETH_STOP_AGG, 3898 MAX_ETH_RX_CQE_TYPE 3899 }; 3900 3901 3902 /* 3903 * Type of SGL/Raw field in ETH RX fast path CQE 3904 */ 3905 enum eth_rx_fp_sel { 3906 ETH_FP_CQE_REGULAR, 3907 ETH_FP_CQE_RAW, 3908 MAX_ETH_RX_FP_SEL 3909 }; 3910 3911 3912 /* 3913 * The eth Rx SGE Descriptor 3914 */ 3915 struct eth_rx_sge { 3916 __le32 addr_lo; 3917 __le32 addr_hi; 3918 }; 3919 3920 3921 /* 3922 * common data for all protocols 3923 */ 3924 struct spe_hdr { 3925 __le32 conn_and_cmd_data; 3926 #define SPE_HDR_CID (0xFFFFFF<<0) 3927 #define SPE_HDR_CID_SHIFT 0 3928 #define SPE_HDR_CMD_ID (0xFF<<24) 3929 #define SPE_HDR_CMD_ID_SHIFT 24 3930 __le16 type; 3931 #define SPE_HDR_CONN_TYPE (0xFF<<0) 3932 #define SPE_HDR_CONN_TYPE_SHIFT 0 3933 #define SPE_HDR_FUNCTION_ID (0xFF<<8) 3934 #define SPE_HDR_FUNCTION_ID_SHIFT 8 3935 __le16 reserved1; 3936 }; 3937 3938 /* 3939 * specific data for ethernet slow path element 3940 */ 3941 union eth_specific_data { 3942 u8 protocol_data[8]; 3943 struct regpair client_update_ramrod_data; 3944 struct regpair client_init_ramrod_init_data; 3945 struct eth_halt_ramrod_data halt_ramrod_data; 3946 struct regpair update_data_addr; 3947 struct eth_common_ramrod_data common_ramrod_data; 3948 struct regpair classify_cfg_addr; 3949 struct regpair filter_cfg_addr; 3950 struct regpair mcast_cfg_addr; 3951 }; 3952 3953 /* 3954 * Ethernet slow path element 3955 */ 3956 struct eth_spe { 3957 struct spe_hdr hdr; 3958 union eth_specific_data data; 3959 }; 3960 3961 3962 /* 3963 * Ethernet command ID for slow path elements 3964 */ 3965 enum eth_spqe_cmd_id { 3966 RAMROD_CMD_ID_ETH_UNUSED, 3967 RAMROD_CMD_ID_ETH_CLIENT_SETUP, 3968 RAMROD_CMD_ID_ETH_HALT, 3969 RAMROD_CMD_ID_ETH_FORWARD_SETUP, 3970 RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP, 3971 RAMROD_CMD_ID_ETH_CLIENT_UPDATE, 3972 RAMROD_CMD_ID_ETH_EMPTY, 3973 RAMROD_CMD_ID_ETH_TERMINATE, 3974 RAMROD_CMD_ID_ETH_TPA_UPDATE, 3975 RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES, 3976 RAMROD_CMD_ID_ETH_FILTER_RULES, 3977 RAMROD_CMD_ID_ETH_MULTICAST_RULES, 3978 RAMROD_CMD_ID_ETH_RSS_UPDATE, 3979 RAMROD_CMD_ID_ETH_SET_MAC, 3980 MAX_ETH_SPQE_CMD_ID 3981 }; 3982 3983 3984 /* 3985 * eth tpa update command 3986 */ 3987 enum eth_tpa_update_command { 3988 TPA_UPDATE_NONE_COMMAND, 3989 TPA_UPDATE_ENABLE_COMMAND, 3990 TPA_UPDATE_DISABLE_COMMAND, 3991 MAX_ETH_TPA_UPDATE_COMMAND 3992 }; 3993 3994 3995 /* 3996 * Tx regular BD structure 3997 */ 3998 struct eth_tx_bd { 3999 __le32 addr_lo; 4000 __le32 addr_hi; 4001 __le16 total_pkt_bytes; 4002 __le16 nbytes; 4003 u8 reserved[4]; 4004 }; 4005 4006 4007 /* 4008 * structure for easy accessibility to assembler 4009 */ 4010 struct eth_tx_bd_flags { 4011 u8 as_bitfield; 4012 #define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0) 4013 #define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0 4014 #define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1) 4015 #define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1 4016 #define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2) 4017 #define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2 4018 #define ETH_TX_BD_FLAGS_START_BD (0x1<<4) 4019 #define ETH_TX_BD_FLAGS_START_BD_SHIFT 4 4020 #define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5) 4021 #define ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5 4022 #define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6) 4023 #define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6 4024 #define ETH_TX_BD_FLAGS_IPV6 (0x1<<7) 4025 #define ETH_TX_BD_FLAGS_IPV6_SHIFT 7 4026 }; 4027 4028 /* 4029 * The eth Tx Buffer Descriptor 4030 */ 4031 struct eth_tx_start_bd { 4032 __le32 addr_lo; 4033 __le32 addr_hi; 4034 __le16 nbd; 4035 __le16 nbytes; 4036 __le16 vlan_or_ethertype; 4037 struct eth_tx_bd_flags bd_flags; 4038 u8 general_data; 4039 #define ETH_TX_START_BD_HDR_NBDS (0xF<<0) 4040 #define ETH_TX_START_BD_HDR_NBDS_SHIFT 0 4041 #define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4) 4042 #define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4 4043 #define ETH_TX_START_BD_RESREVED (0x1<<5) 4044 #define ETH_TX_START_BD_RESREVED_SHIFT 5 4045 #define ETH_TX_START_BD_ETH_ADDR_TYPE (0x3<<6) 4046 #define ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT 6 4047 }; 4048 4049 /* 4050 * Tx parsing BD structure for ETH E1/E1h 4051 */ 4052 struct eth_tx_parse_bd_e1x { 4053 u8 global_data; 4054 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0) 4055 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0 4056 #define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x1<<4) 4057 #define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 4 4058 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<5) 4059 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 5 4060 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<6) 4061 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 6 4062 #define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<7) 4063 #define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 7 4064 u8 tcp_flags; 4065 #define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0) 4066 #define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0 4067 #define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1) 4068 #define ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1 4069 #define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2) 4070 #define ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2 4071 #define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3) 4072 #define ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3 4073 #define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4) 4074 #define ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4 4075 #define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5) 4076 #define ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5 4077 #define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6) 4078 #define ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6 4079 #define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7) 4080 #define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7 4081 u8 ip_hlen_w; 4082 s8 reserved; 4083 __le16 total_hlen_w; 4084 __le16 tcp_pseudo_csum; 4085 __le16 lso_mss; 4086 __le16 ip_id; 4087 __le32 tcp_send_seq; 4088 }; 4089 4090 /* 4091 * Tx parsing BD structure for ETH E2 4092 */ 4093 struct eth_tx_parse_bd_e2 { 4094 __le16 dst_mac_addr_lo; 4095 __le16 dst_mac_addr_mid; 4096 __le16 dst_mac_addr_hi; 4097 __le16 src_mac_addr_lo; 4098 __le16 src_mac_addr_mid; 4099 __le16 src_mac_addr_hi; 4100 __le32 parsing_data; 4101 #define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W (0x1FFF<<0) 4102 #define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W_SHIFT 0 4103 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<13) 4104 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 13 4105 #define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<17) 4106 #define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 17 4107 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<31) 4108 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 31 4109 }; 4110 4111 /* 4112 * The last BD in the BD memory will hold a pointer to the next BD memory 4113 */ 4114 struct eth_tx_next_bd { 4115 __le32 addr_lo; 4116 __le32 addr_hi; 4117 u8 reserved[8]; 4118 }; 4119 4120 /* 4121 * union for 4 Bd types 4122 */ 4123 union eth_tx_bd_types { 4124 struct eth_tx_start_bd start_bd; 4125 struct eth_tx_bd reg_bd; 4126 struct eth_tx_parse_bd_e1x parse_bd_e1x; 4127 struct eth_tx_parse_bd_e2 parse_bd_e2; 4128 struct eth_tx_next_bd next_bd; 4129 }; 4130 4131 /* 4132 * array of 13 bds as appears in the eth xstorm context 4133 */ 4134 struct eth_tx_bds_array { 4135 union eth_tx_bd_types bds[13]; 4136 }; 4137 4138 4139 /* 4140 * VLAN mode on TX BDs 4141 */ 4142 enum eth_tx_vlan_type { 4143 X_ETH_NO_VLAN, 4144 X_ETH_OUTBAND_VLAN, 4145 X_ETH_INBAND_VLAN, 4146 X_ETH_FW_ADDED_VLAN, 4147 MAX_ETH_TX_VLAN_TYPE 4148 }; 4149 4150 4151 /* 4152 * Ethernet VLAN filtering mode in E1x 4153 */ 4154 enum eth_vlan_filter_mode { 4155 ETH_VLAN_FILTER_ANY_VLAN, 4156 ETH_VLAN_FILTER_SPECIFIC_VLAN, 4157 ETH_VLAN_FILTER_CLASSIFY, 4158 MAX_ETH_VLAN_FILTER_MODE 4159 }; 4160 4161 4162 /* 4163 * MAC filtering configuration command header 4164 */ 4165 struct mac_configuration_hdr { 4166 u8 length; 4167 u8 offset; 4168 __le16 client_id; 4169 __le32 echo; 4170 }; 4171 4172 /* 4173 * MAC address in list for ramrod 4174 */ 4175 struct mac_configuration_entry { 4176 __le16 lsb_mac_addr; 4177 __le16 middle_mac_addr; 4178 __le16 msb_mac_addr; 4179 __le16 vlan_id; 4180 u8 pf_id; 4181 u8 flags; 4182 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0) 4183 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0 4184 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1) 4185 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 1 4186 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2) 4187 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 2 4188 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4) 4189 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 4 4190 #define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5) 4191 #define MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 5 4192 #define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6) 4193 #define MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 6 4194 __le16 reserved0; 4195 __le32 clients_bit_vector; 4196 }; 4197 4198 /* 4199 * MAC filtering configuration command 4200 */ 4201 struct mac_configuration_cmd { 4202 struct mac_configuration_hdr hdr; 4203 struct mac_configuration_entry config_table[64]; 4204 }; 4205 4206 4207 /* 4208 * Set-MAC command type (in E1x) 4209 */ 4210 enum set_mac_action_type { 4211 T_ETH_MAC_COMMAND_INVALIDATE, 4212 T_ETH_MAC_COMMAND_SET, 4213 MAX_SET_MAC_ACTION_TYPE 4214 }; 4215 4216 4217 /* 4218 * tpa update ramrod data 4219 */ 4220 struct tpa_update_ramrod_data { 4221 u8 update_ipv4; 4222 u8 update_ipv6; 4223 u8 client_id; 4224 u8 max_tpa_queues; 4225 u8 max_sges_for_packet; 4226 u8 complete_on_both_clients; 4227 __le16 reserved1; 4228 __le16 sge_buff_size; 4229 __le16 max_agg_size; 4230 __le32 sge_page_base_lo; 4231 __le32 sge_page_base_hi; 4232 __le16 sge_pause_thr_low; 4233 __le16 sge_pause_thr_high; 4234 }; 4235 4236 4237 /* 4238 * approximate-match multicast filtering for E1H per function in Tstorm 4239 */ 4240 struct tstorm_eth_approximate_match_multicast_filtering { 4241 u32 mcast_add_hash_bit_array[8]; 4242 }; 4243 4244 4245 /* 4246 * Common configuration parameters per function in Tstorm 4247 */ 4248 struct tstorm_eth_function_common_config { 4249 __le16 config_flags; 4250 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0) 4251 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0 4252 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1) 4253 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1 4254 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2) 4255 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2 4256 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3) 4257 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3 4258 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4) 4259 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4 4260 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<7) 4261 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 7 4262 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0xFF<<8) 4263 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 8 4264 u8 rss_result_mask; 4265 u8 reserved1; 4266 __le16 vlan_id[2]; 4267 }; 4268 4269 4270 /* 4271 * MAC filtering configuration parameters per port in Tstorm 4272 */ 4273 struct tstorm_eth_mac_filter_config { 4274 __le32 ucast_drop_all; 4275 __le32 ucast_accept_all; 4276 __le32 mcast_drop_all; 4277 __le32 mcast_accept_all; 4278 __le32 bcast_accept_all; 4279 __le32 vlan_filter[2]; 4280 __le32 unmatched_unicast; 4281 }; 4282 4283 4284 /* 4285 * tx only queue init ramrod data 4286 */ 4287 struct tx_queue_init_ramrod_data { 4288 struct client_init_general_data general; 4289 struct client_init_tx_data tx; 4290 }; 4291 4292 4293 /* 4294 * Three RX producers for ETH 4295 */ 4296 struct ustorm_eth_rx_producers { 4297 #if defined(__BIG_ENDIAN) 4298 u16 bd_prod; 4299 u16 cqe_prod; 4300 #elif defined(__LITTLE_ENDIAN) 4301 u16 cqe_prod; 4302 u16 bd_prod; 4303 #endif 4304 #if defined(__BIG_ENDIAN) 4305 u16 reserved; 4306 u16 sge_prod; 4307 #elif defined(__LITTLE_ENDIAN) 4308 u16 sge_prod; 4309 u16 reserved; 4310 #endif 4311 }; 4312 4313 4314 /* 4315 * FCoE RX statistics parameters section#0 4316 */ 4317 struct fcoe_rx_stat_params_section0 { 4318 __le32 fcoe_rx_pkt_cnt; 4319 __le32 fcoe_rx_byte_cnt; 4320 }; 4321 4322 4323 /* 4324 * FCoE RX statistics parameters section#1 4325 */ 4326 struct fcoe_rx_stat_params_section1 { 4327 __le32 fcoe_ver_cnt; 4328 __le32 fcoe_rx_drop_pkt_cnt; 4329 }; 4330 4331 4332 /* 4333 * FCoE RX statistics parameters section#2 4334 */ 4335 struct fcoe_rx_stat_params_section2 { 4336 __le32 fc_crc_cnt; 4337 __le32 eofa_del_cnt; 4338 __le32 miss_frame_cnt; 4339 __le32 seq_timeout_cnt; 4340 __le32 drop_seq_cnt; 4341 __le32 fcoe_rx_drop_pkt_cnt; 4342 __le32 fcp_rx_pkt_cnt; 4343 __le32 reserved0; 4344 }; 4345 4346 4347 /* 4348 * FCoE TX statistics parameters 4349 */ 4350 struct fcoe_tx_stat_params { 4351 __le32 fcoe_tx_pkt_cnt; 4352 __le32 fcoe_tx_byte_cnt; 4353 __le32 fcp_tx_pkt_cnt; 4354 __le32 reserved0; 4355 }; 4356 4357 /* 4358 * FCoE statistics parameters 4359 */ 4360 struct fcoe_statistics_params { 4361 struct fcoe_tx_stat_params tx_stat; 4362 struct fcoe_rx_stat_params_section0 rx_stat0; 4363 struct fcoe_rx_stat_params_section1 rx_stat1; 4364 struct fcoe_rx_stat_params_section2 rx_stat2; 4365 }; 4366 4367 4368 /* 4369 * cfc delete event data 4370 */ 4371 struct cfc_del_event_data { 4372 u32 cid; 4373 u32 reserved0; 4374 u32 reserved1; 4375 }; 4376 4377 4378 /* 4379 * per-port SAFC demo variables 4380 */ 4381 struct cmng_flags_per_port { 4382 u32 cmng_enables; 4383 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0) 4384 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0 4385 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1) 4386 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1 4387 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<2) 4388 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 2 4389 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<3) 4390 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 3 4391 #define __CMNG_FLAGS_PER_PORT_RESERVED0 (0xFFFFFFF<<4) 4392 #define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 4 4393 u32 __reserved1; 4394 }; 4395 4396 4397 /* 4398 * per-port rate shaping variables 4399 */ 4400 struct rate_shaping_vars_per_port { 4401 u32 rs_periodic_timeout; 4402 u32 rs_threshold; 4403 }; 4404 4405 /* 4406 * per-port fairness variables 4407 */ 4408 struct fairness_vars_per_port { 4409 u32 upper_bound; 4410 u32 fair_threshold; 4411 u32 fairness_timeout; 4412 u32 reserved0; 4413 }; 4414 4415 /* 4416 * per-port SAFC variables 4417 */ 4418 struct safc_struct_per_port { 4419 #if defined(__BIG_ENDIAN) 4420 u16 __reserved1; 4421 u8 __reserved0; 4422 u8 safc_timeout_usec; 4423 #elif defined(__LITTLE_ENDIAN) 4424 u8 safc_timeout_usec; 4425 u8 __reserved0; 4426 u16 __reserved1; 4427 #endif 4428 u8 cos_to_traffic_types[MAX_COS_NUMBER]; 4429 u16 cos_to_pause_mask[NUM_OF_SAFC_BITS]; 4430 }; 4431 4432 /* 4433 * Per-port congestion management variables 4434 */ 4435 struct cmng_struct_per_port { 4436 struct rate_shaping_vars_per_port rs_vars; 4437 struct fairness_vars_per_port fair_vars; 4438 struct safc_struct_per_port safc_vars; 4439 struct cmng_flags_per_port flags; 4440 }; 4441 4442 4443 /* 4444 * Protocol-common command ID for slow path elements 4445 */ 4446 enum common_spqe_cmd_id { 4447 RAMROD_CMD_ID_COMMON_UNUSED, 4448 RAMROD_CMD_ID_COMMON_FUNCTION_START, 4449 RAMROD_CMD_ID_COMMON_FUNCTION_STOP, 4450 RAMROD_CMD_ID_COMMON_CFC_DEL, 4451 RAMROD_CMD_ID_COMMON_CFC_DEL_WB, 4452 RAMROD_CMD_ID_COMMON_STAT_QUERY, 4453 RAMROD_CMD_ID_COMMON_STOP_TRAFFIC, 4454 RAMROD_CMD_ID_COMMON_START_TRAFFIC, 4455 RAMROD_CMD_ID_COMMON_RESERVED1, 4456 RAMROD_CMD_ID_COMMON_RESERVED2, 4457 MAX_COMMON_SPQE_CMD_ID 4458 }; 4459 4460 4461 /* 4462 * Per-protocol connection types 4463 */ 4464 enum connection_type { 4465 ETH_CONNECTION_TYPE, 4466 TOE_CONNECTION_TYPE, 4467 RDMA_CONNECTION_TYPE, 4468 ISCSI_CONNECTION_TYPE, 4469 FCOE_CONNECTION_TYPE, 4470 RESERVED_CONNECTION_TYPE_0, 4471 RESERVED_CONNECTION_TYPE_1, 4472 RESERVED_CONNECTION_TYPE_2, 4473 NONE_CONNECTION_TYPE, 4474 MAX_CONNECTION_TYPE 4475 }; 4476 4477 4478 /* 4479 * Cos modes 4480 */ 4481 enum cos_mode { 4482 OVERRIDE_COS, 4483 STATIC_COS, 4484 FW_WRR, 4485 MAX_COS_MODE 4486 }; 4487 4488 4489 /* 4490 * Dynamic HC counters set by the driver 4491 */ 4492 struct hc_dynamic_drv_counter { 4493 u32 val[HC_SB_MAX_DYNAMIC_INDICES]; 4494 }; 4495 4496 /* 4497 * zone A per-queue data 4498 */ 4499 struct cstorm_queue_zone_data { 4500 struct hc_dynamic_drv_counter hc_dyn_drv_cnt; 4501 struct regpair reserved[2]; 4502 }; 4503 4504 4505 /* 4506 * Vf-PF channel data in cstorm ram (non-triggered zone) 4507 */ 4508 struct vf_pf_channel_zone_data { 4509 u32 msg_addr_lo; 4510 u32 msg_addr_hi; 4511 }; 4512 4513 /* 4514 * zone for VF non-triggered data 4515 */ 4516 struct non_trigger_vf_zone { 4517 struct vf_pf_channel_zone_data vf_pf_channel; 4518 }; 4519 4520 /* 4521 * Vf-PF channel trigger zone in cstorm ram 4522 */ 4523 struct vf_pf_channel_zone_trigger { 4524 u8 addr_valid; 4525 }; 4526 4527 /* 4528 * zone that triggers the in-bound interrupt 4529 */ 4530 struct trigger_vf_zone { 4531 #if defined(__BIG_ENDIAN) 4532 u16 reserved1; 4533 u8 reserved0; 4534 struct vf_pf_channel_zone_trigger vf_pf_channel; 4535 #elif defined(__LITTLE_ENDIAN) 4536 struct vf_pf_channel_zone_trigger vf_pf_channel; 4537 u8 reserved0; 4538 u16 reserved1; 4539 #endif 4540 u32 reserved2; 4541 }; 4542 4543 /* 4544 * zone B per-VF data 4545 */ 4546 struct cstorm_vf_zone_data { 4547 struct non_trigger_vf_zone non_trigger; 4548 struct trigger_vf_zone trigger; 4549 }; 4550 4551 4552 /* 4553 * Dynamic host coalescing init parameters, per state machine 4554 */ 4555 struct dynamic_hc_sm_config { 4556 u32 threshold[3]; 4557 u8 shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES]; 4558 u8 hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES]; 4559 u8 hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES]; 4560 u8 hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES]; 4561 u8 hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES]; 4562 }; 4563 4564 /* 4565 * Dynamic host coalescing init parameters 4566 */ 4567 struct dynamic_hc_config { 4568 struct dynamic_hc_sm_config sm_config[HC_SB_MAX_SM]; 4569 }; 4570 4571 4572 struct e2_integ_data { 4573 #if defined(__BIG_ENDIAN) 4574 u8 flags; 4575 #define E2_INTEG_DATA_TESTING_EN (0x1<<0) 4576 #define E2_INTEG_DATA_TESTING_EN_SHIFT 0 4577 #define E2_INTEG_DATA_LB_TX (0x1<<1) 4578 #define E2_INTEG_DATA_LB_TX_SHIFT 1 4579 #define E2_INTEG_DATA_COS_TX (0x1<<2) 4580 #define E2_INTEG_DATA_COS_TX_SHIFT 2 4581 #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) 4582 #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3 4583 #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) 4584 #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4 4585 #define E2_INTEG_DATA_RESERVED (0x7<<5) 4586 #define E2_INTEG_DATA_RESERVED_SHIFT 5 4587 u8 cos; 4588 u8 voq; 4589 u8 pbf_queue; 4590 #elif defined(__LITTLE_ENDIAN) 4591 u8 pbf_queue; 4592 u8 voq; 4593 u8 cos; 4594 u8 flags; 4595 #define E2_INTEG_DATA_TESTING_EN (0x1<<0) 4596 #define E2_INTEG_DATA_TESTING_EN_SHIFT 0 4597 #define E2_INTEG_DATA_LB_TX (0x1<<1) 4598 #define E2_INTEG_DATA_LB_TX_SHIFT 1 4599 #define E2_INTEG_DATA_COS_TX (0x1<<2) 4600 #define E2_INTEG_DATA_COS_TX_SHIFT 2 4601 #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) 4602 #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3 4603 #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) 4604 #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4 4605 #define E2_INTEG_DATA_RESERVED (0x7<<5) 4606 #define E2_INTEG_DATA_RESERVED_SHIFT 5 4607 #endif 4608 #if defined(__BIG_ENDIAN) 4609 u16 reserved3; 4610 u8 reserved2; 4611 u8 ramEn; 4612 #elif defined(__LITTLE_ENDIAN) 4613 u8 ramEn; 4614 u8 reserved2; 4615 u16 reserved3; 4616 #endif 4617 }; 4618 4619 4620 /* 4621 * set mac event data 4622 */ 4623 struct eth_event_data { 4624 u32 echo; 4625 u32 reserved0; 4626 u32 reserved1; 4627 }; 4628 4629 4630 /* 4631 * pf-vf event data 4632 */ 4633 struct vf_pf_event_data { 4634 u8 vf_id; 4635 u8 reserved0; 4636 u16 reserved1; 4637 u32 msg_addr_lo; 4638 u32 msg_addr_hi; 4639 }; 4640 4641 /* 4642 * VF FLR event data 4643 */ 4644 struct vf_flr_event_data { 4645 u8 vf_id; 4646 u8 reserved0; 4647 u16 reserved1; 4648 u32 reserved2; 4649 u32 reserved3; 4650 }; 4651 4652 /* 4653 * malicious VF event data 4654 */ 4655 struct malicious_vf_event_data { 4656 u8 vf_id; 4657 u8 reserved0; 4658 u16 reserved1; 4659 u32 reserved2; 4660 u32 reserved3; 4661 }; 4662 4663 /* 4664 * union for all event ring message types 4665 */ 4666 union event_data { 4667 struct vf_pf_event_data vf_pf_event; 4668 struct eth_event_data eth_event; 4669 struct cfc_del_event_data cfc_del_event; 4670 struct vf_flr_event_data vf_flr_event; 4671 struct malicious_vf_event_data malicious_vf_event; 4672 }; 4673 4674 4675 /* 4676 * per PF event ring data 4677 */ 4678 struct event_ring_data { 4679 struct regpair base_addr; 4680 #if defined(__BIG_ENDIAN) 4681 u8 index_id; 4682 u8 sb_id; 4683 u16 producer; 4684 #elif defined(__LITTLE_ENDIAN) 4685 u16 producer; 4686 u8 sb_id; 4687 u8 index_id; 4688 #endif 4689 u32 reserved0; 4690 }; 4691 4692 4693 /* 4694 * event ring message element (each element is 128 bits) 4695 */ 4696 struct event_ring_msg { 4697 u8 opcode; 4698 u8 error; 4699 u16 reserved1; 4700 union event_data data; 4701 }; 4702 4703 /* 4704 * event ring next page element (128 bits) 4705 */ 4706 struct event_ring_next { 4707 struct regpair addr; 4708 u32 reserved[2]; 4709 }; 4710 4711 /* 4712 * union for event ring element types (each element is 128 bits) 4713 */ 4714 union event_ring_elem { 4715 struct event_ring_msg message; 4716 struct event_ring_next next_page; 4717 }; 4718 4719 4720 /* 4721 * Common event ring opcodes 4722 */ 4723 enum event_ring_opcode { 4724 EVENT_RING_OPCODE_VF_PF_CHANNEL, 4725 EVENT_RING_OPCODE_FUNCTION_START, 4726 EVENT_RING_OPCODE_FUNCTION_STOP, 4727 EVENT_RING_OPCODE_CFC_DEL, 4728 EVENT_RING_OPCODE_CFC_DEL_WB, 4729 EVENT_RING_OPCODE_STAT_QUERY, 4730 EVENT_RING_OPCODE_STOP_TRAFFIC, 4731 EVENT_RING_OPCODE_START_TRAFFIC, 4732 EVENT_RING_OPCODE_VF_FLR, 4733 EVENT_RING_OPCODE_MALICIOUS_VF, 4734 EVENT_RING_OPCODE_FORWARD_SETUP, 4735 EVENT_RING_OPCODE_RSS_UPDATE_RULES, 4736 EVENT_RING_OPCODE_RESERVED1, 4737 EVENT_RING_OPCODE_RESERVED2, 4738 EVENT_RING_OPCODE_SET_MAC, 4739 EVENT_RING_OPCODE_CLASSIFICATION_RULES, 4740 EVENT_RING_OPCODE_FILTERS_RULES, 4741 EVENT_RING_OPCODE_MULTICAST_RULES, 4742 MAX_EVENT_RING_OPCODE 4743 }; 4744 4745 4746 /* 4747 * Modes for fairness algorithm 4748 */ 4749 enum fairness_mode { 4750 FAIRNESS_COS_WRR_MODE, 4751 FAIRNESS_COS_ETS_MODE, 4752 MAX_FAIRNESS_MODE 4753 }; 4754 4755 4756 /* 4757 * per-vnic fairness variables 4758 */ 4759 struct fairness_vars_per_vn { 4760 u32 cos_credit_delta[MAX_COS_NUMBER]; 4761 u32 vn_credit_delta; 4762 u32 __reserved0; 4763 }; 4764 4765 4766 /* 4767 * Priority and cos 4768 */ 4769 struct priority_cos { 4770 u8 priority; 4771 u8 cos; 4772 __le16 reserved1; 4773 }; 4774 4775 /* 4776 * The data for flow control configuration 4777 */ 4778 struct flow_control_configuration { 4779 struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES]; 4780 u8 dcb_enabled; 4781 u8 dcb_version; 4782 u8 dont_add_pri_0_en; 4783 u8 reserved1; 4784 __le32 reserved2; 4785 }; 4786 4787 4788 /* 4789 * 4790 */ 4791 struct function_start_data { 4792 __le16 function_mode; 4793 __le16 sd_vlan_tag; 4794 u16 reserved; 4795 u8 path_id; 4796 u8 network_cos_mode; 4797 }; 4798 4799 4800 /* 4801 * FW version stored in the Xstorm RAM 4802 */ 4803 struct fw_version { 4804 #if defined(__BIG_ENDIAN) 4805 u8 engineering; 4806 u8 revision; 4807 u8 minor; 4808 u8 major; 4809 #elif defined(__LITTLE_ENDIAN) 4810 u8 major; 4811 u8 minor; 4812 u8 revision; 4813 u8 engineering; 4814 #endif 4815 u32 flags; 4816 #define FW_VERSION_OPTIMIZED (0x1<<0) 4817 #define FW_VERSION_OPTIMIZED_SHIFT 0 4818 #define FW_VERSION_BIG_ENDIEN (0x1<<1) 4819 #define FW_VERSION_BIG_ENDIEN_SHIFT 1 4820 #define FW_VERSION_CHIP_VERSION (0x3<<2) 4821 #define FW_VERSION_CHIP_VERSION_SHIFT 2 4822 #define __FW_VERSION_RESERVED (0xFFFFFFF<<4) 4823 #define __FW_VERSION_RESERVED_SHIFT 4 4824 }; 4825 4826 4827 /* 4828 * Dynamic Host-Coalescing - Driver(host) counters 4829 */ 4830 struct hc_dynamic_sb_drv_counters { 4831 u32 dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES]; 4832 }; 4833 4834 4835 /* 4836 * 2 bytes. configuration/state parameters for a single protocol index 4837 */ 4838 struct hc_index_data { 4839 #if defined(__BIG_ENDIAN) 4840 u8 flags; 4841 #define HC_INDEX_DATA_SM_ID (0x1<<0) 4842 #define HC_INDEX_DATA_SM_ID_SHIFT 0 4843 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1) 4844 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1 4845 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) 4846 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2 4847 #define HC_INDEX_DATA_RESERVE (0x1F<<3) 4848 #define HC_INDEX_DATA_RESERVE_SHIFT 3 4849 u8 timeout; 4850 #elif defined(__LITTLE_ENDIAN) 4851 u8 timeout; 4852 u8 flags; 4853 #define HC_INDEX_DATA_SM_ID (0x1<<0) 4854 #define HC_INDEX_DATA_SM_ID_SHIFT 0 4855 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1) 4856 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1 4857 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) 4858 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2 4859 #define HC_INDEX_DATA_RESERVE (0x1F<<3) 4860 #define HC_INDEX_DATA_RESERVE_SHIFT 3 4861 #endif 4862 }; 4863 4864 4865 /* 4866 * HC state-machine 4867 */ 4868 struct hc_status_block_sm { 4869 #if defined(__BIG_ENDIAN) 4870 u8 igu_seg_id; 4871 u8 igu_sb_id; 4872 u8 timer_value; 4873 u8 __flags; 4874 #elif defined(__LITTLE_ENDIAN) 4875 u8 __flags; 4876 u8 timer_value; 4877 u8 igu_sb_id; 4878 u8 igu_seg_id; 4879 #endif 4880 u32 time_to_expire; 4881 }; 4882 4883 /* 4884 * hold PCI identification variables- used in various places in firmware 4885 */ 4886 struct pci_entity { 4887 #if defined(__BIG_ENDIAN) 4888 u8 vf_valid; 4889 u8 vf_id; 4890 u8 vnic_id; 4891 u8 pf_id; 4892 #elif defined(__LITTLE_ENDIAN) 4893 u8 pf_id; 4894 u8 vnic_id; 4895 u8 vf_id; 4896 u8 vf_valid; 4897 #endif 4898 }; 4899 4900 /* 4901 * The fast-path status block meta-data, common to all chips 4902 */ 4903 struct hc_sb_data { 4904 struct regpair host_sb_addr; 4905 struct hc_status_block_sm state_machine[HC_SB_MAX_SM]; 4906 struct pci_entity p_func; 4907 #if defined(__BIG_ENDIAN) 4908 u8 rsrv0; 4909 u8 state; 4910 u8 dhc_qzone_id; 4911 u8 same_igu_sb_1b; 4912 #elif defined(__LITTLE_ENDIAN) 4913 u8 same_igu_sb_1b; 4914 u8 dhc_qzone_id; 4915 u8 state; 4916 u8 rsrv0; 4917 #endif 4918 struct regpair rsrv1[2]; 4919 }; 4920 4921 4922 /* 4923 * Segment types for host coaslescing 4924 */ 4925 enum hc_segment { 4926 HC_REGULAR_SEGMENT, 4927 HC_DEFAULT_SEGMENT, 4928 MAX_HC_SEGMENT 4929 }; 4930 4931 4932 /* 4933 * The fast-path status block meta-data 4934 */ 4935 struct hc_sp_status_block_data { 4936 struct regpair host_sb_addr; 4937 #if defined(__BIG_ENDIAN) 4938 u8 rsrv1; 4939 u8 state; 4940 u8 igu_seg_id; 4941 u8 igu_sb_id; 4942 #elif defined(__LITTLE_ENDIAN) 4943 u8 igu_sb_id; 4944 u8 igu_seg_id; 4945 u8 state; 4946 u8 rsrv1; 4947 #endif 4948 struct pci_entity p_func; 4949 }; 4950 4951 4952 /* 4953 * The fast-path status block meta-data 4954 */ 4955 struct hc_status_block_data_e1x { 4956 struct hc_index_data index_data[HC_SB_MAX_INDICES_E1X]; 4957 struct hc_sb_data common; 4958 }; 4959 4960 4961 /* 4962 * The fast-path status block meta-data 4963 */ 4964 struct hc_status_block_data_e2 { 4965 struct hc_index_data index_data[HC_SB_MAX_INDICES_E2]; 4966 struct hc_sb_data common; 4967 }; 4968 4969 4970 /* 4971 * IGU block operartion modes (in Everest2) 4972 */ 4973 enum igu_mode { 4974 HC_IGU_BC_MODE, 4975 HC_IGU_NBC_MODE, 4976 MAX_IGU_MODE 4977 }; 4978 4979 4980 /* 4981 * IP versions 4982 */ 4983 enum ip_ver { 4984 IP_V4, 4985 IP_V6, 4986 MAX_IP_VER 4987 }; 4988 4989 4990 /* 4991 * Multi-function modes 4992 */ 4993 enum mf_mode { 4994 SINGLE_FUNCTION, 4995 MULTI_FUNCTION_SD, 4996 MULTI_FUNCTION_SI, 4997 MULTI_FUNCTION_RESERVED, 4998 MAX_MF_MODE 4999 }; 5000 5001 /* 5002 * Protocol-common statistics collected by the Tstorm (per pf) 5003 */ 5004 struct tstorm_per_pf_stats { 5005 struct regpair rcv_error_bytes; 5006 }; 5007 5008 /* 5009 * 5010 */ 5011 struct per_pf_stats { 5012 struct tstorm_per_pf_stats tstorm_pf_statistics; 5013 }; 5014 5015 5016 /* 5017 * Protocol-common statistics collected by the Tstorm (per port) 5018 */ 5019 struct tstorm_per_port_stats { 5020 __le32 mac_discard; 5021 __le32 mac_filter_discard; 5022 __le32 brb_truncate_discard; 5023 __le32 mf_tag_discard; 5024 __le32 packet_drop; 5025 __le32 reserved; 5026 }; 5027 5028 /* 5029 * 5030 */ 5031 struct per_port_stats { 5032 struct tstorm_per_port_stats tstorm_port_statistics; 5033 }; 5034 5035 5036 /* 5037 * Protocol-common statistics collected by the Tstorm (per client) 5038 */ 5039 struct tstorm_per_queue_stats { 5040 struct regpair rcv_ucast_bytes; 5041 __le32 rcv_ucast_pkts; 5042 __le32 checksum_discard; 5043 struct regpair rcv_bcast_bytes; 5044 __le32 rcv_bcast_pkts; 5045 __le32 pkts_too_big_discard; 5046 struct regpair rcv_mcast_bytes; 5047 __le32 rcv_mcast_pkts; 5048 __le32 ttl0_discard; 5049 __le16 no_buff_discard; 5050 __le16 reserved0; 5051 __le32 reserved1; 5052 }; 5053 5054 /* 5055 * Protocol-common statistics collected by the Ustorm (per client) 5056 */ 5057 struct ustorm_per_queue_stats { 5058 struct regpair ucast_no_buff_bytes; 5059 struct regpair mcast_no_buff_bytes; 5060 struct regpair bcast_no_buff_bytes; 5061 __le32 ucast_no_buff_pkts; 5062 __le32 mcast_no_buff_pkts; 5063 __le32 bcast_no_buff_pkts; 5064 __le32 coalesced_pkts; 5065 struct regpair coalesced_bytes; 5066 __le32 coalesced_events; 5067 __le32 coalesced_aborts; 5068 }; 5069 5070 /* 5071 * Protocol-common statistics collected by the Xstorm (per client) 5072 */ 5073 struct xstorm_per_queue_stats { 5074 struct regpair ucast_bytes_sent; 5075 struct regpair mcast_bytes_sent; 5076 struct regpair bcast_bytes_sent; 5077 __le32 ucast_pkts_sent; 5078 __le32 mcast_pkts_sent; 5079 __le32 bcast_pkts_sent; 5080 __le32 error_drop_pkts; 5081 }; 5082 5083 /* 5084 * 5085 */ 5086 struct per_queue_stats { 5087 struct tstorm_per_queue_stats tstorm_queue_statistics; 5088 struct ustorm_per_queue_stats ustorm_queue_statistics; 5089 struct xstorm_per_queue_stats xstorm_queue_statistics; 5090 }; 5091 5092 5093 /* 5094 * FW version stored in first line of pram 5095 */ 5096 struct pram_fw_version { 5097 u8 major; 5098 u8 minor; 5099 u8 revision; 5100 u8 engineering; 5101 u8 flags; 5102 #define PRAM_FW_VERSION_OPTIMIZED (0x1<<0) 5103 #define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0 5104 #define PRAM_FW_VERSION_STORM_ID (0x3<<1) 5105 #define PRAM_FW_VERSION_STORM_ID_SHIFT 1 5106 #define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3) 5107 #define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3 5108 #define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4) 5109 #define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4 5110 #define __PRAM_FW_VERSION_RESERVED0 (0x3<<6) 5111 #define __PRAM_FW_VERSION_RESERVED0_SHIFT 6 5112 }; 5113 5114 5115 /* 5116 * Ethernet slow path element 5117 */ 5118 union protocol_common_specific_data { 5119 u8 protocol_data[8]; 5120 struct regpair phy_address; 5121 struct regpair mac_config_addr; 5122 }; 5123 5124 /* 5125 * The send queue element 5126 */ 5127 struct protocol_common_spe { 5128 struct spe_hdr hdr; 5129 union protocol_common_specific_data data; 5130 }; 5131 5132 5133 /* 5134 * a single rate shaping counter. can be used as protocol or vnic counter 5135 */ 5136 struct rate_shaping_counter { 5137 u32 quota; 5138 #if defined(__BIG_ENDIAN) 5139 u16 __reserved0; 5140 u16 rate; 5141 #elif defined(__LITTLE_ENDIAN) 5142 u16 rate; 5143 u16 __reserved0; 5144 #endif 5145 }; 5146 5147 5148 /* 5149 * per-vnic rate shaping variables 5150 */ 5151 struct rate_shaping_vars_per_vn { 5152 struct rate_shaping_counter vn_counter; 5153 }; 5154 5155 5156 /* 5157 * The send queue element 5158 */ 5159 struct slow_path_element { 5160 struct spe_hdr hdr; 5161 struct regpair protocol_data; 5162 }; 5163 5164 5165 /* 5166 * Protocol-common statistics counter 5167 */ 5168 struct stats_counter { 5169 __le16 xstats_counter; 5170 __le16 reserved0; 5171 __le32 reserved1; 5172 __le16 tstats_counter; 5173 __le16 reserved2; 5174 __le32 reserved3; 5175 __le16 ustats_counter; 5176 __le16 reserved4; 5177 __le32 reserved5; 5178 __le16 cstats_counter; 5179 __le16 reserved6; 5180 __le32 reserved7; 5181 }; 5182 5183 5184 /* 5185 * 5186 */ 5187 struct stats_query_entry { 5188 u8 kind; 5189 u8 index; 5190 __le16 funcID; 5191 __le32 reserved; 5192 struct regpair address; 5193 }; 5194 5195 /* 5196 * statistic command 5197 */ 5198 struct stats_query_cmd_group { 5199 struct stats_query_entry query[STATS_QUERY_CMD_COUNT]; 5200 }; 5201 5202 5203 /* 5204 * statistic command header 5205 */ 5206 struct stats_query_header { 5207 u8 cmd_num; 5208 u8 reserved0; 5209 __le16 drv_stats_counter; 5210 __le32 reserved1; 5211 struct regpair stats_counters_addrs; 5212 }; 5213 5214 5215 /* 5216 * Types of statistcis query entry 5217 */ 5218 enum stats_query_type { 5219 STATS_TYPE_QUEUE, 5220 STATS_TYPE_PORT, 5221 STATS_TYPE_PF, 5222 STATS_TYPE_TOE, 5223 STATS_TYPE_FCOE, 5224 MAX_STATS_QUERY_TYPE 5225 }; 5226 5227 5228 /* 5229 * Indicate of the function status block state 5230 */ 5231 enum status_block_state { 5232 SB_DISABLED, 5233 SB_ENABLED, 5234 SB_CLEANED, 5235 MAX_STATUS_BLOCK_STATE 5236 }; 5237 5238 5239 /* 5240 * Storm IDs (including attentions for IGU related enums) 5241 */ 5242 enum storm_id { 5243 USTORM_ID, 5244 CSTORM_ID, 5245 XSTORM_ID, 5246 TSTORM_ID, 5247 ATTENTION_ID, 5248 MAX_STORM_ID 5249 }; 5250 5251 5252 /* 5253 * Taffic types used in ETS and flow control algorithms 5254 */ 5255 enum traffic_type { 5256 LLFC_TRAFFIC_TYPE_NW, 5257 LLFC_TRAFFIC_TYPE_FCOE, 5258 LLFC_TRAFFIC_TYPE_ISCSI, 5259 MAX_TRAFFIC_TYPE 5260 }; 5261 5262 5263 /* 5264 * zone A per-queue data 5265 */ 5266 struct tstorm_queue_zone_data { 5267 struct regpair reserved[4]; 5268 }; 5269 5270 5271 /* 5272 * zone B per-VF data 5273 */ 5274 struct tstorm_vf_zone_data { 5275 struct regpair reserved; 5276 }; 5277 5278 5279 /* 5280 * zone A per-queue data 5281 */ 5282 struct ustorm_queue_zone_data { 5283 struct ustorm_eth_rx_producers eth_rx_producers; 5284 struct regpair reserved[3]; 5285 }; 5286 5287 5288 /* 5289 * zone B per-VF data 5290 */ 5291 struct ustorm_vf_zone_data { 5292 struct regpair reserved; 5293 }; 5294 5295 5296 /* 5297 * data per VF-PF channel 5298 */ 5299 struct vf_pf_channel_data { 5300 #if defined(__BIG_ENDIAN) 5301 u16 reserved0; 5302 u8 valid; 5303 u8 state; 5304 #elif defined(__LITTLE_ENDIAN) 5305 u8 state; 5306 u8 valid; 5307 u16 reserved0; 5308 #endif 5309 u32 reserved1; 5310 }; 5311 5312 5313 /* 5314 * State of VF-PF channel 5315 */ 5316 enum vf_pf_channel_state { 5317 VF_PF_CHANNEL_STATE_READY, 5318 VF_PF_CHANNEL_STATE_WAITING_FOR_ACK, 5319 MAX_VF_PF_CHANNEL_STATE 5320 }; 5321 5322 5323 /* 5324 * zone A per-queue data 5325 */ 5326 struct xstorm_queue_zone_data { 5327 struct regpair reserved[4]; 5328 }; 5329 5330 5331 /* 5332 * zone B per-VF data 5333 */ 5334 struct xstorm_vf_zone_data { 5335 struct regpair reserved; 5336 }; 5337 5338 #endif /* BNX2X_HSI_H */ 5339