1 /* bnx2x_hsi.h: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2013 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 */ 9 #ifndef BNX2X_HSI_H 10 #define BNX2X_HSI_H 11 12 #include "bnx2x_fw_defs.h" 13 #include "bnx2x_mfw_req.h" 14 15 #define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e 16 17 struct license_key { 18 u32 reserved[6]; 19 20 u32 max_iscsi_conn; 21 #define BNX2X_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF 22 #define BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT 0 23 #define BNX2X_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000 24 #define BNX2X_MAX_ISCSI_INIT_CONN_SHIFT 16 25 26 u32 reserved_a; 27 28 u32 max_fcoe_conn; 29 #define BNX2X_MAX_FCOE_TRGT_CONN_MASK 0xFFFF 30 #define BNX2X_MAX_FCOE_TRGT_CONN_SHIFT 0 31 #define BNX2X_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000 32 #define BNX2X_MAX_FCOE_INIT_CONN_SHIFT 16 33 34 u32 reserved_b[4]; 35 }; 36 37 /**************************************************************************** 38 * Shared HW configuration * 39 ****************************************************************************/ 40 #define PIN_CFG_NA 0x00000000 41 #define PIN_CFG_GPIO0_P0 0x00000001 42 #define PIN_CFG_GPIO1_P0 0x00000002 43 #define PIN_CFG_GPIO2_P0 0x00000003 44 #define PIN_CFG_GPIO3_P0 0x00000004 45 #define PIN_CFG_GPIO0_P1 0x00000005 46 #define PIN_CFG_GPIO1_P1 0x00000006 47 #define PIN_CFG_GPIO2_P1 0x00000007 48 #define PIN_CFG_GPIO3_P1 0x00000008 49 #define PIN_CFG_EPIO0 0x00000009 50 #define PIN_CFG_EPIO1 0x0000000a 51 #define PIN_CFG_EPIO2 0x0000000b 52 #define PIN_CFG_EPIO3 0x0000000c 53 #define PIN_CFG_EPIO4 0x0000000d 54 #define PIN_CFG_EPIO5 0x0000000e 55 #define PIN_CFG_EPIO6 0x0000000f 56 #define PIN_CFG_EPIO7 0x00000010 57 #define PIN_CFG_EPIO8 0x00000011 58 #define PIN_CFG_EPIO9 0x00000012 59 #define PIN_CFG_EPIO10 0x00000013 60 #define PIN_CFG_EPIO11 0x00000014 61 #define PIN_CFG_EPIO12 0x00000015 62 #define PIN_CFG_EPIO13 0x00000016 63 #define PIN_CFG_EPIO14 0x00000017 64 #define PIN_CFG_EPIO15 0x00000018 65 #define PIN_CFG_EPIO16 0x00000019 66 #define PIN_CFG_EPIO17 0x0000001a 67 #define PIN_CFG_EPIO18 0x0000001b 68 #define PIN_CFG_EPIO19 0x0000001c 69 #define PIN_CFG_EPIO20 0x0000001d 70 #define PIN_CFG_EPIO21 0x0000001e 71 #define PIN_CFG_EPIO22 0x0000001f 72 #define PIN_CFG_EPIO23 0x00000020 73 #define PIN_CFG_EPIO24 0x00000021 74 #define PIN_CFG_EPIO25 0x00000022 75 #define PIN_CFG_EPIO26 0x00000023 76 #define PIN_CFG_EPIO27 0x00000024 77 #define PIN_CFG_EPIO28 0x00000025 78 #define PIN_CFG_EPIO29 0x00000026 79 #define PIN_CFG_EPIO30 0x00000027 80 #define PIN_CFG_EPIO31 0x00000028 81 82 /* EPIO definition */ 83 #define EPIO_CFG_NA 0x00000000 84 #define EPIO_CFG_EPIO0 0x00000001 85 #define EPIO_CFG_EPIO1 0x00000002 86 #define EPIO_CFG_EPIO2 0x00000003 87 #define EPIO_CFG_EPIO3 0x00000004 88 #define EPIO_CFG_EPIO4 0x00000005 89 #define EPIO_CFG_EPIO5 0x00000006 90 #define EPIO_CFG_EPIO6 0x00000007 91 #define EPIO_CFG_EPIO7 0x00000008 92 #define EPIO_CFG_EPIO8 0x00000009 93 #define EPIO_CFG_EPIO9 0x0000000a 94 #define EPIO_CFG_EPIO10 0x0000000b 95 #define EPIO_CFG_EPIO11 0x0000000c 96 #define EPIO_CFG_EPIO12 0x0000000d 97 #define EPIO_CFG_EPIO13 0x0000000e 98 #define EPIO_CFG_EPIO14 0x0000000f 99 #define EPIO_CFG_EPIO15 0x00000010 100 #define EPIO_CFG_EPIO16 0x00000011 101 #define EPIO_CFG_EPIO17 0x00000012 102 #define EPIO_CFG_EPIO18 0x00000013 103 #define EPIO_CFG_EPIO19 0x00000014 104 #define EPIO_CFG_EPIO20 0x00000015 105 #define EPIO_CFG_EPIO21 0x00000016 106 #define EPIO_CFG_EPIO22 0x00000017 107 #define EPIO_CFG_EPIO23 0x00000018 108 #define EPIO_CFG_EPIO24 0x00000019 109 #define EPIO_CFG_EPIO25 0x0000001a 110 #define EPIO_CFG_EPIO26 0x0000001b 111 #define EPIO_CFG_EPIO27 0x0000001c 112 #define EPIO_CFG_EPIO28 0x0000001d 113 #define EPIO_CFG_EPIO29 0x0000001e 114 #define EPIO_CFG_EPIO30 0x0000001f 115 #define EPIO_CFG_EPIO31 0x00000020 116 117 struct mac_addr { 118 u32 upper; 119 u32 lower; 120 }; 121 122 struct shared_hw_cfg { /* NVRAM Offset */ 123 /* Up to 16 bytes of NULL-terminated string */ 124 u8 part_num[16]; /* 0x104 */ 125 126 u32 config; /* 0x114 */ 127 #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001 128 #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0 129 #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000 130 #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001 131 #define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN 0x00000002 132 133 #define SHARED_HW_CFG_PORT_SWAP 0x00000004 134 135 #define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008 136 137 #define SHARED_HW_CFG_PCIE_GEN3_DISABLED 0x00000000 138 #define SHARED_HW_CFG_PCIE_GEN3_ENABLED 0x00000010 139 140 #define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700 141 #define SHARED_HW_CFG_MFW_SELECT_SHIFT 8 142 /* Whatever MFW found in NVM 143 (if multiple found, priority order is: NC-SI, UMP, IPMI) */ 144 #define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000 145 #define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100 146 #define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200 147 #define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300 148 /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI 149 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 150 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400 151 /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI 152 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 153 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500 154 /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP 155 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 156 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600 157 158 #define SHARED_HW_CFG_LED_MODE_MASK 0x000f0000 159 #define SHARED_HW_CFG_LED_MODE_SHIFT 16 160 #define SHARED_HW_CFG_LED_MAC1 0x00000000 161 #define SHARED_HW_CFG_LED_PHY1 0x00010000 162 #define SHARED_HW_CFG_LED_PHY2 0x00020000 163 #define SHARED_HW_CFG_LED_PHY3 0x00030000 164 #define SHARED_HW_CFG_LED_MAC2 0x00040000 165 #define SHARED_HW_CFG_LED_PHY4 0x00050000 166 #define SHARED_HW_CFG_LED_PHY5 0x00060000 167 #define SHARED_HW_CFG_LED_PHY6 0x00070000 168 #define SHARED_HW_CFG_LED_MAC3 0x00080000 169 #define SHARED_HW_CFG_LED_PHY7 0x00090000 170 #define SHARED_HW_CFG_LED_PHY9 0x000a0000 171 #define SHARED_HW_CFG_LED_PHY11 0x000b0000 172 #define SHARED_HW_CFG_LED_MAC4 0x000c0000 173 #define SHARED_HW_CFG_LED_PHY8 0x000d0000 174 #define SHARED_HW_CFG_LED_EXTPHY1 0x000e0000 175 #define SHARED_HW_CFG_LED_EXTPHY2 0x000f0000 176 177 178 #define SHARED_HW_CFG_AN_ENABLE_MASK 0x3f000000 179 #define SHARED_HW_CFG_AN_ENABLE_SHIFT 24 180 #define SHARED_HW_CFG_AN_ENABLE_CL37 0x01000000 181 #define SHARED_HW_CFG_AN_ENABLE_CL73 0x02000000 182 #define SHARED_HW_CFG_AN_ENABLE_BAM 0x04000000 183 #define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 0x08000000 184 #define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 0x10000000 185 #define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 0x20000000 186 187 #define SHARED_HW_CFG_SRIOV_MASK 0x40000000 188 #define SHARED_HW_CFG_SRIOV_DISABLED 0x00000000 189 #define SHARED_HW_CFG_SRIOV_ENABLED 0x40000000 190 191 #define SHARED_HW_CFG_ATC_MASK 0x80000000 192 #define SHARED_HW_CFG_ATC_DISABLED 0x00000000 193 #define SHARED_HW_CFG_ATC_ENABLED 0x80000000 194 195 u32 config2; /* 0x118 */ 196 /* one time auto detect grace period (in sec) */ 197 #define SHARED_HW_CFG_GRACE_PERIOD_MASK 0x000000ff 198 #define SHARED_HW_CFG_GRACE_PERIOD_SHIFT 0 199 200 #define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100 201 #define SHARED_HW_CFG_PCIE_GEN2_DISABLED 0x00000000 202 203 /* The default value for the core clock is 250MHz and it is 204 achieved by setting the clock change to 4 */ 205 #define SHARED_HW_CFG_CLOCK_CHANGE_MASK 0x00000e00 206 #define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT 9 207 208 #define SHARED_HW_CFG_SMBUS_TIMING_MASK 0x00001000 209 #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000 210 #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000 211 212 #define SHARED_HW_CFG_HIDE_PORT1 0x00002000 213 214 #define SHARED_HW_CFG_WOL_CAPABLE_MASK 0x00004000 215 #define SHARED_HW_CFG_WOL_CAPABLE_DISABLED 0x00000000 216 #define SHARED_HW_CFG_WOL_CAPABLE_ENABLED 0x00004000 217 218 /* Output low when PERST is asserted */ 219 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_MASK 0x00008000 220 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_DISABLED 0x00000000 221 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_ENABLED 0x00008000 222 223 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_MASK 0x00070000 224 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_SHIFT 16 225 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_HW 0x00000000 226 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_0DB 0x00010000 227 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_3_5DB 0x00020000 228 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_6_0DB 0x00030000 229 230 /* The fan failure mechanism is usually related to the PHY type 231 since the power consumption of the board is determined by the PHY. 232 Currently, fan is required for most designs with SFX7101, BCM8727 233 and BCM8481. If a fan is not required for a board which uses one 234 of those PHYs, this field should be set to "Disabled". If a fan is 235 required for a different PHY type, this option should be set to 236 "Enabled". The fan failure indication is expected on SPIO5 */ 237 #define SHARED_HW_CFG_FAN_FAILURE_MASK 0x00180000 238 #define SHARED_HW_CFG_FAN_FAILURE_SHIFT 19 239 #define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE 0x00000000 240 #define SHARED_HW_CFG_FAN_FAILURE_DISABLED 0x00080000 241 #define SHARED_HW_CFG_FAN_FAILURE_ENABLED 0x00100000 242 243 /* ASPM Power Management support */ 244 #define SHARED_HW_CFG_ASPM_SUPPORT_MASK 0x00600000 245 #define SHARED_HW_CFG_ASPM_SUPPORT_SHIFT 21 246 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_ENABLED 0x00000000 247 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_DISABLED 0x00200000 248 #define SHARED_HW_CFG_ASPM_SUPPORT_L1_DISABLED 0x00400000 249 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_DISABLED 0x00600000 250 251 /* The value of PM_TL_IGNORE_REQS (bit0) in PCI register 252 tl_control_0 (register 0x2800) */ 253 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_MASK 0x00800000 254 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_DISABLED 0x00000000 255 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_ENABLED 0x00800000 256 257 #define SHARED_HW_CFG_PORT_MODE_MASK 0x01000000 258 #define SHARED_HW_CFG_PORT_MODE_2 0x00000000 259 #define SHARED_HW_CFG_PORT_MODE_4 0x01000000 260 261 #define SHARED_HW_CFG_PATH_SWAP_MASK 0x02000000 262 #define SHARED_HW_CFG_PATH_SWAP_DISABLED 0x00000000 263 #define SHARED_HW_CFG_PATH_SWAP_ENABLED 0x02000000 264 265 /* Set the MDC/MDIO access for the first external phy */ 266 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK 0x1C000000 267 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT 26 268 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE 0x00000000 269 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0 0x04000000 270 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1 0x08000000 271 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH 0x0c000000 272 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED 0x10000000 273 274 /* Set the MDC/MDIO access for the second external phy */ 275 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK 0xE0000000 276 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT 29 277 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE 0x00000000 278 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0 0x20000000 279 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1 0x40000000 280 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH 0x60000000 281 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED 0x80000000 282 283 u32 config_3; /* 0x11C */ 284 #define SHARED_HW_CFG_EXTENDED_MF_MODE_MASK 0x00000F00 285 #define SHARED_HW_CFG_EXTENDED_MF_MODE_SHIFT 8 286 #define SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5 0x00000000 287 #define SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR2_DOT_0 0x00000100 288 289 u32 ump_nc_si_config; /* 0x120 */ 290 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003 291 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0 292 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000 293 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001 294 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000 295 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002 296 297 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK 0x00000f00 298 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT 8 299 300 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK 0x00ff0000 301 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT 16 302 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE 0x00000000 303 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000 304 305 u32 board; /* 0x124 */ 306 #define SHARED_HW_CFG_E3_I2C_MUX0_MASK 0x0000003F 307 #define SHARED_HW_CFG_E3_I2C_MUX0_SHIFT 0 308 #define SHARED_HW_CFG_E3_I2C_MUX1_MASK 0x00000FC0 309 #define SHARED_HW_CFG_E3_I2C_MUX1_SHIFT 6 310 /* Use the PIN_CFG_XXX defines on top */ 311 #define SHARED_HW_CFG_BOARD_REV_MASK 0x00ff0000 312 #define SHARED_HW_CFG_BOARD_REV_SHIFT 16 313 314 #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0x0f000000 315 #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 24 316 317 #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0xf0000000 318 #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 28 319 320 u32 wc_lane_config; /* 0x128 */ 321 #define SHARED_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF 322 #define SHARED_HW_CFG_LANE_SWAP_CFG_SHIFT 0 323 #define SHARED_HW_CFG_LANE_SWAP_CFG_32103210 0x00001b1b 324 #define SHARED_HW_CFG_LANE_SWAP_CFG_32100123 0x00001be4 325 #define SHARED_HW_CFG_LANE_SWAP_CFG_01233210 0x0000e41b 326 #define SHARED_HW_CFG_LANE_SWAP_CFG_01230123 0x0000e4e4 327 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF 328 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0 329 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00 330 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8 331 332 /* TX lane Polarity swap */ 333 #define SHARED_HW_CFG_TX_LANE0_POL_FLIP_ENABLED 0x00010000 334 #define SHARED_HW_CFG_TX_LANE1_POL_FLIP_ENABLED 0x00020000 335 #define SHARED_HW_CFG_TX_LANE2_POL_FLIP_ENABLED 0x00040000 336 #define SHARED_HW_CFG_TX_LANE3_POL_FLIP_ENABLED 0x00080000 337 /* TX lane Polarity swap */ 338 #define SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED 0x00100000 339 #define SHARED_HW_CFG_RX_LANE1_POL_FLIP_ENABLED 0x00200000 340 #define SHARED_HW_CFG_RX_LANE2_POL_FLIP_ENABLED 0x00400000 341 #define SHARED_HW_CFG_RX_LANE3_POL_FLIP_ENABLED 0x00800000 342 343 /* Selects the port layout of the board */ 344 #define SHARED_HW_CFG_E3_PORT_LAYOUT_MASK 0x0F000000 345 #define SHARED_HW_CFG_E3_PORT_LAYOUT_SHIFT 24 346 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01 0x00000000 347 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_10 0x01000000 348 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_0123 0x02000000 349 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_1032 0x03000000 350 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_2301 0x04000000 351 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_3210 0x05000000 352 }; 353 354 355 /**************************************************************************** 356 * Port HW configuration * 357 ****************************************************************************/ 358 struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */ 359 360 u32 pci_id; 361 #define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xffff0000 362 #define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000ffff 363 364 u32 pci_sub_id; 365 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xffff0000 366 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000ffff 367 368 u32 power_dissipated; 369 #define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000ff 370 #define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0 371 #define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000ff00 372 #define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8 373 #define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00ff0000 374 #define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16 375 #define PORT_HW_CFG_POWER_DIS_D3_MASK 0xff000000 376 #define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24 377 378 u32 power_consumed; 379 #define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000ff 380 #define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0 381 #define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000ff00 382 #define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8 383 #define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00ff0000 384 #define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16 385 #define PORT_HW_CFG_POWER_CONS_D3_MASK 0xff000000 386 #define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24 387 388 u32 mac_upper; 389 #define PORT_HW_CFG_UPPERMAC_MASK 0x0000ffff 390 #define PORT_HW_CFG_UPPERMAC_SHIFT 0 391 u32 mac_lower; 392 393 u32 iscsi_mac_upper; /* Upper 16 bits are always zeroes */ 394 u32 iscsi_mac_lower; 395 396 u32 rdma_mac_upper; /* Upper 16 bits are always zeroes */ 397 u32 rdma_mac_lower; 398 399 u32 serdes_config; 400 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000ffff 401 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0 402 403 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xffff0000 404 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 16 405 406 407 /* Default values: 2P-64, 4P-32 */ 408 u32 pf_config; /* 0x158 */ 409 #define PORT_HW_CFG_PF_NUM_VF_MASK 0x0000007F 410 #define PORT_HW_CFG_PF_NUM_VF_SHIFT 0 411 412 /* Default values: 17 */ 413 #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_MASK 0x00007F00 414 #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_SHIFT 8 415 416 #define PORT_HW_CFG_ENABLE_FLR_MASK 0x00010000 417 #define PORT_HW_CFG_FLR_ENABLED 0x00010000 418 419 u32 vf_config; /* 0x15C */ 420 #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_MASK 0x0000007F 421 #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_SHIFT 0 422 423 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_MASK 0xFFFF0000 424 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_SHIFT 16 425 426 u32 mf_pci_id; /* 0x160 */ 427 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_MASK 0x0000FFFF 428 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_SHIFT 0 429 430 /* Controls the TX laser of the SFP+ module */ 431 u32 sfp_ctrl; /* 0x164 */ 432 #define PORT_HW_CFG_TX_LASER_MASK 0x000000FF 433 #define PORT_HW_CFG_TX_LASER_SHIFT 0 434 #define PORT_HW_CFG_TX_LASER_MDIO 0x00000000 435 #define PORT_HW_CFG_TX_LASER_GPIO0 0x00000001 436 #define PORT_HW_CFG_TX_LASER_GPIO1 0x00000002 437 #define PORT_HW_CFG_TX_LASER_GPIO2 0x00000003 438 #define PORT_HW_CFG_TX_LASER_GPIO3 0x00000004 439 440 /* Controls the fault module LED of the SFP+ */ 441 #define PORT_HW_CFG_FAULT_MODULE_LED_MASK 0x0000FF00 442 #define PORT_HW_CFG_FAULT_MODULE_LED_SHIFT 8 443 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO0 0x00000000 444 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO1 0x00000100 445 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO2 0x00000200 446 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO3 0x00000300 447 #define PORT_HW_CFG_FAULT_MODULE_LED_DISABLED 0x00000400 448 449 /* The output pin TX_DIS that controls the TX laser of the SFP+ 450 module. Use the PIN_CFG_XXX defines on top */ 451 u32 e3_sfp_ctrl; /* 0x168 */ 452 #define PORT_HW_CFG_E3_TX_LASER_MASK 0x000000FF 453 #define PORT_HW_CFG_E3_TX_LASER_SHIFT 0 454 455 /* The output pin for SFPP_TYPE which turns on the Fault module LED */ 456 #define PORT_HW_CFG_E3_FAULT_MDL_LED_MASK 0x0000FF00 457 #define PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT 8 458 459 /* The input pin MOD_ABS that indicates whether SFP+ module is 460 present or not. Use the PIN_CFG_XXX defines on top */ 461 #define PORT_HW_CFG_E3_MOD_ABS_MASK 0x00FF0000 462 #define PORT_HW_CFG_E3_MOD_ABS_SHIFT 16 463 464 /* The output pin PWRDIS_SFP_X which disable the power of the SFP+ 465 module. Use the PIN_CFG_XXX defines on top */ 466 #define PORT_HW_CFG_E3_PWR_DIS_MASK 0xFF000000 467 #define PORT_HW_CFG_E3_PWR_DIS_SHIFT 24 468 469 /* 470 * The input pin which signals module transmit fault. Use the 471 * PIN_CFG_XXX defines on top 472 */ 473 u32 e3_cmn_pin_cfg; /* 0x16C */ 474 #define PORT_HW_CFG_E3_TX_FAULT_MASK 0x000000FF 475 #define PORT_HW_CFG_E3_TX_FAULT_SHIFT 0 476 477 /* The output pin which reset the PHY. Use the PIN_CFG_XXX defines on 478 top */ 479 #define PORT_HW_CFG_E3_PHY_RESET_MASK 0x0000FF00 480 #define PORT_HW_CFG_E3_PHY_RESET_SHIFT 8 481 482 /* 483 * The output pin which powers down the PHY. Use the PIN_CFG_XXX 484 * defines on top 485 */ 486 #define PORT_HW_CFG_E3_PWR_DOWN_MASK 0x00FF0000 487 #define PORT_HW_CFG_E3_PWR_DOWN_SHIFT 16 488 489 /* The output pin values BSC_SEL which selects the I2C for this port 490 in the I2C Mux */ 491 #define PORT_HW_CFG_E3_I2C_MUX0_MASK 0x01000000 492 #define PORT_HW_CFG_E3_I2C_MUX1_MASK 0x02000000 493 494 495 /* 496 * The input pin I_FAULT which indicate over-current has occurred. 497 * Use the PIN_CFG_XXX defines on top 498 */ 499 u32 e3_cmn_pin_cfg1; /* 0x170 */ 500 #define PORT_HW_CFG_E3_OVER_CURRENT_MASK 0x000000FF 501 #define PORT_HW_CFG_E3_OVER_CURRENT_SHIFT 0 502 503 /* pause on host ring */ 504 u32 generic_features; /* 0x174 */ 505 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_MASK 0x00000001 506 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_SHIFT 0 507 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_DISABLED 0x00000000 508 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED 0x00000001 509 510 /* SFP+ Tx Equalization: NIC recommended and tested value is 0xBEB2 511 * LOM recommended and tested value is 0xBEB2. Using a different 512 * value means using a value not tested by BRCM 513 */ 514 u32 sfi_tap_values; /* 0x178 */ 515 #define PORT_HW_CFG_TX_EQUALIZATION_MASK 0x0000FFFF 516 #define PORT_HW_CFG_TX_EQUALIZATION_SHIFT 0 517 518 /* SFP+ Tx driver broadcast IDRIVER: NIC recommended and tested 519 * value is 0x2. LOM recommended and tested value is 0x2. Using a 520 * different value means using a value not tested by BRCM 521 */ 522 #define PORT_HW_CFG_TX_DRV_BROADCAST_MASK 0x000F0000 523 #define PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT 16 524 525 u32 reserved0[5]; /* 0x17c */ 526 527 u32 aeu_int_mask; /* 0x190 */ 528 529 u32 media_type; /* 0x194 */ 530 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK 0x000000FF 531 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT 0 532 533 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK 0x0000FF00 534 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT 8 535 536 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK 0x00FF0000 537 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT 16 538 539 /* 4 times 16 bits for all 4 lanes. In case external PHY is present 540 (not direct mode), those values will not take effect on the 4 XGXS 541 lanes. For some external PHYs (such as 8706 and 8726) the values 542 will be used to configure the external PHY in those cases, not 543 all 4 values are needed. */ 544 u16 xgxs_config_rx[4]; /* 0x198 */ 545 u16 xgxs_config_tx[4]; /* 0x1A0 */ 546 547 /* For storing FCOE mac on shared memory */ 548 u32 fcoe_fip_mac_upper; 549 #define PORT_HW_CFG_FCOE_UPPERMAC_MASK 0x0000ffff 550 #define PORT_HW_CFG_FCOE_UPPERMAC_SHIFT 0 551 u32 fcoe_fip_mac_lower; 552 553 u32 fcoe_wwn_port_name_upper; 554 u32 fcoe_wwn_port_name_lower; 555 556 u32 fcoe_wwn_node_name_upper; 557 u32 fcoe_wwn_node_name_lower; 558 559 u32 Reserved1[49]; /* 0x1C0 */ 560 561 /* Enable RJ45 magjack pair swapping on 10GBase-T PHY (0=default), 562 84833 only */ 563 u32 xgbt_phy_cfg; /* 0x284 */ 564 #define PORT_HW_CFG_RJ45_PAIR_SWAP_MASK 0x000000FF 565 #define PORT_HW_CFG_RJ45_PAIR_SWAP_SHIFT 0 566 567 u32 default_cfg; /* 0x288 */ 568 #define PORT_HW_CFG_GPIO0_CONFIG_MASK 0x00000003 569 #define PORT_HW_CFG_GPIO0_CONFIG_SHIFT 0 570 #define PORT_HW_CFG_GPIO0_CONFIG_NA 0x00000000 571 #define PORT_HW_CFG_GPIO0_CONFIG_LOW 0x00000001 572 #define PORT_HW_CFG_GPIO0_CONFIG_HIGH 0x00000002 573 #define PORT_HW_CFG_GPIO0_CONFIG_INPUT 0x00000003 574 575 #define PORT_HW_CFG_GPIO1_CONFIG_MASK 0x0000000C 576 #define PORT_HW_CFG_GPIO1_CONFIG_SHIFT 2 577 #define PORT_HW_CFG_GPIO1_CONFIG_NA 0x00000000 578 #define PORT_HW_CFG_GPIO1_CONFIG_LOW 0x00000004 579 #define PORT_HW_CFG_GPIO1_CONFIG_HIGH 0x00000008 580 #define PORT_HW_CFG_GPIO1_CONFIG_INPUT 0x0000000c 581 582 #define PORT_HW_CFG_GPIO2_CONFIG_MASK 0x00000030 583 #define PORT_HW_CFG_GPIO2_CONFIG_SHIFT 4 584 #define PORT_HW_CFG_GPIO2_CONFIG_NA 0x00000000 585 #define PORT_HW_CFG_GPIO2_CONFIG_LOW 0x00000010 586 #define PORT_HW_CFG_GPIO2_CONFIG_HIGH 0x00000020 587 #define PORT_HW_CFG_GPIO2_CONFIG_INPUT 0x00000030 588 589 #define PORT_HW_CFG_GPIO3_CONFIG_MASK 0x000000C0 590 #define PORT_HW_CFG_GPIO3_CONFIG_SHIFT 6 591 #define PORT_HW_CFG_GPIO3_CONFIG_NA 0x00000000 592 #define PORT_HW_CFG_GPIO3_CONFIG_LOW 0x00000040 593 #define PORT_HW_CFG_GPIO3_CONFIG_HIGH 0x00000080 594 #define PORT_HW_CFG_GPIO3_CONFIG_INPUT 0x000000c0 595 596 /* When KR link is required to be set to force which is not 597 KR-compliant, this parameter determine what is the trigger for it. 598 When GPIO is selected, low input will force the speed. Currently 599 default speed is 1G. In the future, it may be widen to select the 600 forced speed in with another parameter. Note when force-1G is 601 enabled, it override option 56: Link Speed option. */ 602 #define PORT_HW_CFG_FORCE_KR_ENABLER_MASK 0x00000F00 603 #define PORT_HW_CFG_FORCE_KR_ENABLER_SHIFT 8 604 #define PORT_HW_CFG_FORCE_KR_ENABLER_NOT_FORCED 0x00000000 605 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P0 0x00000100 606 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P0 0x00000200 607 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P0 0x00000300 608 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P0 0x00000400 609 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P1 0x00000500 610 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P1 0x00000600 611 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P1 0x00000700 612 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P1 0x00000800 613 #define PORT_HW_CFG_FORCE_KR_ENABLER_FORCED 0x00000900 614 /* Enable to determine with which GPIO to reset the external phy */ 615 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK 0x000F0000 616 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT 16 617 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_PHY_TYPE 0x00000000 618 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0 0x00010000 619 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0 0x00020000 620 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0 0x00030000 621 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0 0x00040000 622 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1 0x00050000 623 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1 0x00060000 624 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1 0x00070000 625 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1 0x00080000 626 627 /* Enable BAM on KR */ 628 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK 0x00100000 629 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT 20 630 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED 0x00000000 631 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED 0x00100000 632 633 /* Enable Common Mode Sense */ 634 #define PORT_HW_CFG_ENABLE_CMS_MASK 0x00200000 635 #define PORT_HW_CFG_ENABLE_CMS_SHIFT 21 636 #define PORT_HW_CFG_ENABLE_CMS_DISABLED 0x00000000 637 #define PORT_HW_CFG_ENABLE_CMS_ENABLED 0x00200000 638 639 /* Determine the Serdes electrical interface */ 640 #define PORT_HW_CFG_NET_SERDES_IF_MASK 0x0F000000 641 #define PORT_HW_CFG_NET_SERDES_IF_SHIFT 24 642 #define PORT_HW_CFG_NET_SERDES_IF_SGMII 0x00000000 643 #define PORT_HW_CFG_NET_SERDES_IF_XFI 0x01000000 644 #define PORT_HW_CFG_NET_SERDES_IF_SFI 0x02000000 645 #define PORT_HW_CFG_NET_SERDES_IF_KR 0x03000000 646 #define PORT_HW_CFG_NET_SERDES_IF_DXGXS 0x04000000 647 #define PORT_HW_CFG_NET_SERDES_IF_KR2 0x05000000 648 649 650 u32 speed_capability_mask2; /* 0x28C */ 651 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK 0x0000FFFF 652 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0 653 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL 0x00000001 654 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3__ 0x00000002 655 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3___ 0x00000004 656 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL 0x00000008 657 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G 0x00000010 658 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_DOT_5G 0x00000020 659 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G 0x00000040 660 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_20G 0x00000080 661 662 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK 0xFFFF0000 663 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT 16 664 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL 0x00010000 665 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0__ 0x00020000 666 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0___ 0x00040000 667 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL 0x00080000 668 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G 0x00100000 669 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_DOT_5G 0x00200000 670 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G 0x00400000 671 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G 0x00800000 672 673 674 /* In the case where two media types (e.g. copper and fiber) are 675 present and electrically active at the same time, PHY Selection 676 will determine which of the two PHYs will be designated as the 677 Active PHY and used for a connection to the network. */ 678 u32 multi_phy_config; /* 0x290 */ 679 #define PORT_HW_CFG_PHY_SELECTION_MASK 0x00000007 680 #define PORT_HW_CFG_PHY_SELECTION_SHIFT 0 681 #define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT 0x00000000 682 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY 0x00000001 683 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY 0x00000002 684 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003 685 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004 686 687 /* When enabled, all second phy nvram parameters will be swapped 688 with the first phy parameters */ 689 #define PORT_HW_CFG_PHY_SWAPPED_MASK 0x00000008 690 #define PORT_HW_CFG_PHY_SWAPPED_SHIFT 3 691 #define PORT_HW_CFG_PHY_SWAPPED_DISABLED 0x00000000 692 #define PORT_HW_CFG_PHY_SWAPPED_ENABLED 0x00000008 693 694 695 /* Address of the second external phy */ 696 u32 external_phy_config2; /* 0x294 */ 697 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK 0x000000FF 698 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT 0 699 700 /* The second XGXS external PHY type */ 701 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK 0x0000FF00 702 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT 8 703 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT 0x00000000 704 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071 0x00000100 705 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072 0x00000200 706 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073 0x00000300 707 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705 0x00000400 708 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706 0x00000500 709 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726 0x00000600 710 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481 0x00000700 711 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101 0x00000800 712 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727 0x00000900 713 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC 0x00000a00 714 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823 0x00000b00 715 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640 0x00000c00 716 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833 0x00000d00 717 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54618SE 0x00000e00 718 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8722 0x00000f00 719 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54616 0x00001000 720 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84834 0x00001100 721 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00 722 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00 723 724 725 /* 4 times 16 bits for all 4 lanes. For some external PHYs (such as 726 8706, 8726 and 8727) not all 4 values are needed. */ 727 u16 xgxs_config2_rx[4]; /* 0x296 */ 728 u16 xgxs_config2_tx[4]; /* 0x2A0 */ 729 730 u32 lane_config; 731 #define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000ffff 732 #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0 733 /* AN and forced */ 734 #define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b 735 /* forced only */ 736 #define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4 737 /* forced only */ 738 #define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8 739 /* forced only */ 740 #define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4 741 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000ff 742 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0 743 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000ff00 744 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8 745 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000c000 746 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14 747 748 /* Indicate whether to swap the external phy polarity */ 749 #define PORT_HW_CFG_SWAP_PHY_POLARITY_MASK 0x00010000 750 #define PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED 0x00000000 751 #define PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED 0x00010000 752 753 754 u32 external_phy_config; 755 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000ff 756 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0 757 758 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000ff00 759 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8 760 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000 761 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100 762 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200 763 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300 764 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400 765 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500 766 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726 0x00000600 767 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700 768 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800 769 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 0x00000900 770 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00 771 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823 0x00000b00 772 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54640 0x00000c00 773 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833 0x00000d00 774 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE 0x00000e00 775 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722 0x00000f00 776 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616 0x00001000 777 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834 0x00001100 778 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC 0x0000fc00 779 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00 780 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00 781 782 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00ff0000 783 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16 784 785 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xff000000 786 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24 787 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000 788 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000 789 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD 0x02000000 790 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000 791 792 u32 speed_capability_mask; 793 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000ffff 794 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0 795 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001 796 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002 797 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004 798 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008 799 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010 800 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020 801 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040 802 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_20G 0x00000080 803 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000 804 805 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xffff0000 806 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16 807 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000 808 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000 809 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000 810 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000 811 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000 812 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000 813 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000 814 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_20G 0x00800000 815 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000 816 817 /* A place to hold the original MAC address as a backup */ 818 u32 backup_mac_upper; /* 0x2B4 */ 819 u32 backup_mac_lower; /* 0x2B8 */ 820 821 }; 822 823 824 /**************************************************************************** 825 * Shared Feature configuration * 826 ****************************************************************************/ 827 struct shared_feat_cfg { /* NVRAM Offset */ 828 829 u32 config; /* 0x450 */ 830 #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001 831 832 /* Use NVRAM values instead of HW default values */ 833 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_MASK \ 834 0x00000002 835 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED \ 836 0x00000000 837 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED \ 838 0x00000002 839 840 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_MASK 0x00000008 841 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_SPIO 0x00000000 842 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_NVRAM 0x00000008 843 844 #define SHARED_FEAT_CFG_NCSI_ID_MASK 0x00000030 845 #define SHARED_FEAT_CFG_NCSI_ID_SHIFT 4 846 847 /* Override the OTP back to single function mode. When using GPIO, 848 high means only SF, 0 is according to CLP configuration */ 849 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK 0x00000700 850 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT 8 851 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED 0x00000000 852 #define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF 0x00000100 853 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4 0x00000200 854 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT 0x00000300 855 #define SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE 0x00000400 856 #define SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE 0x00000600 857 #define SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE 0x00000700 858 859 /* The interval in seconds between sending LLDP packets. Set to zero 860 to disable the feature */ 861 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_MASK 0x00ff0000 862 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_SHIFT 16 863 864 /* The assigned device type ID for LLDP usage */ 865 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_MASK 0xff000000 866 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_SHIFT 24 867 868 }; 869 870 871 /**************************************************************************** 872 * Port Feature configuration * 873 ****************************************************************************/ 874 struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */ 875 876 u32 config; 877 #define PORT_FEATURE_BAR1_SIZE_MASK 0x0000000f 878 #define PORT_FEATURE_BAR1_SIZE_SHIFT 0 879 #define PORT_FEATURE_BAR1_SIZE_DISABLED 0x00000000 880 #define PORT_FEATURE_BAR1_SIZE_64K 0x00000001 881 #define PORT_FEATURE_BAR1_SIZE_128K 0x00000002 882 #define PORT_FEATURE_BAR1_SIZE_256K 0x00000003 883 #define PORT_FEATURE_BAR1_SIZE_512K 0x00000004 884 #define PORT_FEATURE_BAR1_SIZE_1M 0x00000005 885 #define PORT_FEATURE_BAR1_SIZE_2M 0x00000006 886 #define PORT_FEATURE_BAR1_SIZE_4M 0x00000007 887 #define PORT_FEATURE_BAR1_SIZE_8M 0x00000008 888 #define PORT_FEATURE_BAR1_SIZE_16M 0x00000009 889 #define PORT_FEATURE_BAR1_SIZE_32M 0x0000000a 890 #define PORT_FEATURE_BAR1_SIZE_64M 0x0000000b 891 #define PORT_FEATURE_BAR1_SIZE_128M 0x0000000c 892 #define PORT_FEATURE_BAR1_SIZE_256M 0x0000000d 893 #define PORT_FEATURE_BAR1_SIZE_512M 0x0000000e 894 #define PORT_FEATURE_BAR1_SIZE_1G 0x0000000f 895 #define PORT_FEATURE_BAR2_SIZE_MASK 0x000000f0 896 #define PORT_FEATURE_BAR2_SIZE_SHIFT 4 897 #define PORT_FEATURE_BAR2_SIZE_DISABLED 0x00000000 898 #define PORT_FEATURE_BAR2_SIZE_64K 0x00000010 899 #define PORT_FEATURE_BAR2_SIZE_128K 0x00000020 900 #define PORT_FEATURE_BAR2_SIZE_256K 0x00000030 901 #define PORT_FEATURE_BAR2_SIZE_512K 0x00000040 902 #define PORT_FEATURE_BAR2_SIZE_1M 0x00000050 903 #define PORT_FEATURE_BAR2_SIZE_2M 0x00000060 904 #define PORT_FEATURE_BAR2_SIZE_4M 0x00000070 905 #define PORT_FEATURE_BAR2_SIZE_8M 0x00000080 906 #define PORT_FEATURE_BAR2_SIZE_16M 0x00000090 907 #define PORT_FEATURE_BAR2_SIZE_32M 0x000000a0 908 #define PORT_FEATURE_BAR2_SIZE_64M 0x000000b0 909 #define PORT_FEATURE_BAR2_SIZE_128M 0x000000c0 910 #define PORT_FEATURE_BAR2_SIZE_256M 0x000000d0 911 #define PORT_FEATURE_BAR2_SIZE_512M 0x000000e0 912 #define PORT_FEATURE_BAR2_SIZE_1G 0x000000f0 913 914 #define PORT_FEAT_CFG_DCBX_MASK 0x00000100 915 #define PORT_FEAT_CFG_DCBX_DISABLED 0x00000000 916 #define PORT_FEAT_CFG_DCBX_ENABLED 0x00000100 917 918 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK 0x00000C00 919 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE 0x00000400 920 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI 0x00000800 921 922 #define PORT_FEATURE_EN_SIZE_MASK 0x0f000000 923 #define PORT_FEATURE_EN_SIZE_SHIFT 24 924 #define PORT_FEATURE_WOL_ENABLED 0x01000000 925 #define PORT_FEATURE_MBA_ENABLED 0x02000000 926 #define PORT_FEATURE_MFW_ENABLED 0x04000000 927 928 /* Advertise expansion ROM even if MBA is disabled */ 929 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_MASK 0x08000000 930 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED 0x00000000 931 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED 0x08000000 932 933 /* Check the optic vendor via i2c against a list of approved modules 934 in a separate nvram image */ 935 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK 0xe0000000 936 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT 29 937 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT \ 938 0x00000000 939 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER \ 940 0x20000000 941 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG 0x40000000 942 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN 0x60000000 943 944 u32 wol_config; 945 /* Default is used when driver sets to "auto" mode */ 946 #define PORT_FEATURE_WOL_DEFAULT_MASK 0x00000003 947 #define PORT_FEATURE_WOL_DEFAULT_SHIFT 0 948 #define PORT_FEATURE_WOL_DEFAULT_DISABLE 0x00000000 949 #define PORT_FEATURE_WOL_DEFAULT_MAGIC 0x00000001 950 #define PORT_FEATURE_WOL_DEFAULT_ACPI 0x00000002 951 #define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x00000003 952 #define PORT_FEATURE_WOL_RES_PAUSE_CAP 0x00000004 953 #define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP 0x00000008 954 #define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010 955 956 u32 mba_config; 957 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000007 958 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0 959 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000 960 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001 961 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002 962 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003 963 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT 0x00000004 964 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE 0x00000007 965 966 #define PORT_FEATURE_MBA_BOOT_RETRY_MASK 0x00000038 967 #define PORT_FEATURE_MBA_BOOT_RETRY_SHIFT 3 968 969 #define PORT_FEATURE_MBA_RES_PAUSE_CAP 0x00000100 970 #define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP 0x00000200 971 #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400 972 #define PORT_FEATURE_MBA_HOTKEY_MASK 0x00000800 973 #define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000 974 #define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800 975 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000ff000 976 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12 977 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000 978 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000 979 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000 980 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000 981 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000 982 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000 983 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000 984 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000 985 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000 986 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000 987 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000 988 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000 989 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000 990 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000 991 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000 992 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000 993 #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00f00000 994 #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20 995 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000 996 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24 997 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000 998 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000 999 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000 1000 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000 1001 #define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c000000 1002 #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26 1003 #define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000 1004 #define PORT_FEATURE_MBA_LINK_SPEED_10HD 0x04000000 1005 #define PORT_FEATURE_MBA_LINK_SPEED_10FD 0x08000000 1006 #define PORT_FEATURE_MBA_LINK_SPEED_100HD 0x0c000000 1007 #define PORT_FEATURE_MBA_LINK_SPEED_100FD 0x10000000 1008 #define PORT_FEATURE_MBA_LINK_SPEED_1GBPS 0x14000000 1009 #define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS 0x18000000 1010 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4 0x1c000000 1011 #define PORT_FEATURE_MBA_LINK_SPEED_20GBPS 0x20000000 1012 u32 bmc_config; 1013 #define PORT_FEATURE_BMC_LINK_OVERRIDE_MASK 0x00000001 1014 #define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT 0x00000000 1015 #define PORT_FEATURE_BMC_LINK_OVERRIDE_EN 0x00000001 1016 1017 u32 mba_vlan_cfg; 1018 #define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000ffff 1019 #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0 1020 #define PORT_FEATURE_MBA_VLAN_EN 0x00010000 1021 1022 u32 resource_cfg; 1023 #define PORT_FEATURE_RESOURCE_CFG_VALID 0x00000001 1024 #define PORT_FEATURE_RESOURCE_CFG_DIAG 0x00000002 1025 #define PORT_FEATURE_RESOURCE_CFG_L2 0x00000004 1026 #define PORT_FEATURE_RESOURCE_CFG_ISCSI 0x00000008 1027 #define PORT_FEATURE_RESOURCE_CFG_RDMA 0x00000010 1028 1029 u32 smbus_config; 1030 #define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe 1031 #define PORT_FEATURE_SMBUS_ADDR_SHIFT 1 1032 1033 u32 vf_config; 1034 #define PORT_FEAT_CFG_VF_BAR2_SIZE_MASK 0x0000000f 1035 #define PORT_FEAT_CFG_VF_BAR2_SIZE_SHIFT 0 1036 #define PORT_FEAT_CFG_VF_BAR2_SIZE_DISABLED 0x00000000 1037 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4K 0x00000001 1038 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8K 0x00000002 1039 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16K 0x00000003 1040 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32K 0x00000004 1041 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64K 0x00000005 1042 #define PORT_FEAT_CFG_VF_BAR2_SIZE_128K 0x00000006 1043 #define PORT_FEAT_CFG_VF_BAR2_SIZE_256K 0x00000007 1044 #define PORT_FEAT_CFG_VF_BAR2_SIZE_512K 0x00000008 1045 #define PORT_FEAT_CFG_VF_BAR2_SIZE_1M 0x00000009 1046 #define PORT_FEAT_CFG_VF_BAR2_SIZE_2M 0x0000000a 1047 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4M 0x0000000b 1048 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8M 0x0000000c 1049 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16M 0x0000000d 1050 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32M 0x0000000e 1051 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64M 0x0000000f 1052 1053 u32 link_config; /* Used as HW defaults for the driver */ 1054 #define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000 1055 #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24 1056 /* (forced) low speed switch (< 10G) */ 1057 #define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000 1058 /* (forced) high speed switch (>= 10G) */ 1059 #define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000 1060 #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000 1061 #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000 1062 1063 #define PORT_FEATURE_LINK_SPEED_MASK 0x000f0000 1064 #define PORT_FEATURE_LINK_SPEED_SHIFT 16 1065 #define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000 1066 #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00010000 1067 #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00020000 1068 #define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000 1069 #define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000 1070 #define PORT_FEATURE_LINK_SPEED_1G 0x00050000 1071 #define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000 1072 #define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000 1073 #define PORT_FEATURE_LINK_SPEED_20G 0x00080000 1074 1075 #define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700 1076 #define PORT_FEATURE_FLOW_CONTROL_SHIFT 8 1077 #define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000 1078 #define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100 1079 #define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200 1080 #define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300 1081 #define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400 1082 1083 /* The default for MCP link configuration, 1084 uses the same defines as link_config */ 1085 u32 mfw_wol_link_cfg; 1086 1087 /* The default for the driver of the second external phy, 1088 uses the same defines as link_config */ 1089 u32 link_config2; /* 0x47C */ 1090 1091 /* The default for MCP of the second external phy, 1092 uses the same defines as link_config */ 1093 u32 mfw_wol_link_cfg2; /* 0x480 */ 1094 1095 1096 /* EEE power saving mode */ 1097 u32 eee_power_mode; /* 0x484 */ 1098 #define PORT_FEAT_CFG_EEE_POWER_MODE_MASK 0x000000FF 1099 #define PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT 0 1100 #define PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED 0x00000000 1101 #define PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED 0x00000001 1102 #define PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE 0x00000002 1103 #define PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY 0x00000003 1104 1105 1106 u32 Reserved2[16]; /* 0x488 */ 1107 }; 1108 1109 1110 /**************************************************************************** 1111 * Device Information * 1112 ****************************************************************************/ 1113 struct shm_dev_info { /* size */ 1114 1115 u32 bc_rev; /* 8 bits each: major, minor, build */ /* 4 */ 1116 1117 struct shared_hw_cfg shared_hw_config; /* 40 */ 1118 1119 struct port_hw_cfg port_hw_config[PORT_MAX]; /* 400*2=800 */ 1120 1121 struct shared_feat_cfg shared_feature_config; /* 4 */ 1122 1123 struct port_feat_cfg port_feature_config[PORT_MAX];/* 116*2=232 */ 1124 1125 }; 1126 1127 1128 #if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN) 1129 #error "Missing either LITTLE_ENDIAN or BIG_ENDIAN definition." 1130 #endif 1131 1132 #define FUNC_0 0 1133 #define FUNC_1 1 1134 #define FUNC_2 2 1135 #define FUNC_3 3 1136 #define FUNC_4 4 1137 #define FUNC_5 5 1138 #define FUNC_6 6 1139 #define FUNC_7 7 1140 #define E1_FUNC_MAX 2 1141 #define E1H_FUNC_MAX 8 1142 #define E2_FUNC_MAX 4 /* per path */ 1143 1144 #define VN_0 0 1145 #define VN_1 1 1146 #define VN_2 2 1147 #define VN_3 3 1148 #define E1VN_MAX 1 1149 #define E1HVN_MAX 4 1150 1151 #define E2_VF_MAX 64 /* HC_REG_VF_CONFIGURATION_SIZE */ 1152 /* This value (in milliseconds) determines the frequency of the driver 1153 * issuing the PULSE message code. The firmware monitors this periodic 1154 * pulse to determine when to switch to an OS-absent mode. */ 1155 #define DRV_PULSE_PERIOD_MS 250 1156 1157 /* This value (in milliseconds) determines how long the driver should 1158 * wait for an acknowledgement from the firmware before timing out. Once 1159 * the firmware has timed out, the driver will assume there is no firmware 1160 * running and there won't be any firmware-driver synchronization during a 1161 * driver reset. */ 1162 #define FW_ACK_TIME_OUT_MS 5000 1163 1164 #define FW_ACK_POLL_TIME_MS 1 1165 1166 #define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS) 1167 1168 #define MFW_TRACE_SIGNATURE 0x54524342 1169 1170 /**************************************************************************** 1171 * Driver <-> FW Mailbox * 1172 ****************************************************************************/ 1173 struct drv_port_mb { 1174 1175 u32 link_status; 1176 /* Driver should update this field on any link change event */ 1177 1178 #define LINK_STATUS_NONE (0<<0) 1179 #define LINK_STATUS_LINK_FLAG_MASK 0x00000001 1180 #define LINK_STATUS_LINK_UP 0x00000001 1181 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E 1182 #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1) 1183 #define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1) 1184 #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1) 1185 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1) 1186 #define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1) 1187 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1) 1188 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1) 1189 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1) 1190 #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1) 1191 #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1) 1192 #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1) 1193 #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1) 1194 #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1) 1195 #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1) 1196 #define LINK_STATUS_SPEED_AND_DUPLEX_20GTFD (11<<1) 1197 #define LINK_STATUS_SPEED_AND_DUPLEX_20GXFD (11<<1) 1198 1199 #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020 1200 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020 1201 1202 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040 1203 #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080 1204 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080 1205 1206 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200 1207 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400 1208 #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800 1209 #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000 1210 #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000 1211 #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000 1212 #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000 1213 1214 #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000 1215 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000 1216 1217 #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000 1218 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000 1219 1220 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000 1221 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18) 1222 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18) 1223 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18) 1224 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18) 1225 1226 #define LINK_STATUS_SERDES_LINK 0x00100000 1227 1228 #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000 1229 #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000 1230 #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000 1231 #define LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE 0x10000000 1232 1233 #define LINK_STATUS_PFC_ENABLED 0x20000000 1234 1235 #define LINK_STATUS_PHYSICAL_LINK_FLAG 0x40000000 1236 #define LINK_STATUS_SFP_TX_FAULT 0x80000000 1237 1238 u32 port_stx; 1239 1240 u32 stat_nig_timer; 1241 1242 /* MCP firmware does not use this field */ 1243 u32 ext_phy_fw_version; 1244 1245 }; 1246 1247 1248 struct drv_func_mb { 1249 1250 u32 drv_mb_header; 1251 #define DRV_MSG_CODE_MASK 0xffff0000 1252 #define DRV_MSG_CODE_LOAD_REQ 0x10000000 1253 #define DRV_MSG_CODE_LOAD_DONE 0x11000000 1254 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000 1255 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000 1256 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000 1257 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000 1258 #define DRV_MSG_CODE_DCC_OK 0x30000000 1259 #define DRV_MSG_CODE_DCC_FAILURE 0x31000000 1260 #define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000 1261 #define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000 1262 #define DRV_MSG_CODE_VALIDATE_KEY 0x70000000 1263 #define DRV_MSG_CODE_GET_CURR_KEY 0x80000000 1264 #define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000 1265 #define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000 1266 #define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000 1267 #define DRV_MSG_CODE_OEM_OK 0x00010000 1268 #define DRV_MSG_CODE_OEM_FAILURE 0x00020000 1269 #define DRV_MSG_CODE_OEM_UPDATE_SVID_OK 0x00030000 1270 #define DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE 0x00040000 1271 /* 1272 * The optic module verification command requires bootcode 1273 * v5.0.6 or later, te specific optic module verification command 1274 * requires bootcode v5.2.12 or later 1275 */ 1276 #define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL 0xa0000000 1277 #define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL 0x00050006 1278 #define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL 0xa1000000 1279 #define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL 0x00050234 1280 #define DRV_MSG_CODE_VRFY_AFEX_SUPPORTED 0xa2000000 1281 #define REQ_BC_VER_4_VRFY_AFEX_SUPPORTED 0x00070002 1282 #define REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED 0x00070014 1283 #define REQ_BC_VER_4_MT_SUPPORTED 0x00070201 1284 #define REQ_BC_VER_4_PFC_STATS_SUPPORTED 0x00070201 1285 #define REQ_BC_VER_4_FCOE_FEATURES 0x00070209 1286 1287 #define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG 0xb0000000 1288 #define DRV_MSG_CODE_DCBX_PMF_DRV_OK 0xb2000000 1289 #define REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF 0x00070401 1290 1291 #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000 1292 1293 #define DRV_MSG_CODE_AFEX_DRIVER_SETMAC 0xd0000000 1294 #define DRV_MSG_CODE_AFEX_LISTGET_ACK 0xd1000000 1295 #define DRV_MSG_CODE_AFEX_LISTSET_ACK 0xd2000000 1296 #define DRV_MSG_CODE_AFEX_STATSGET_ACK 0xd3000000 1297 #define DRV_MSG_CODE_AFEX_VIFSET_ACK 0xd4000000 1298 1299 #define DRV_MSG_CODE_DRV_INFO_ACK 0xd8000000 1300 #define DRV_MSG_CODE_DRV_INFO_NACK 0xd9000000 1301 1302 #define DRV_MSG_CODE_EEE_RESULTS_ACK 0xda000000 1303 1304 #define DRV_MSG_CODE_RMMOD 0xdb000000 1305 #define REQ_BC_VER_4_RMMOD_CMD 0x0007080f 1306 1307 #define DRV_MSG_CODE_SET_MF_BW 0xe0000000 1308 #define REQ_BC_VER_4_SET_MF_BW 0x00060202 1309 #define DRV_MSG_CODE_SET_MF_BW_ACK 0xe1000000 1310 1311 #define DRV_MSG_CODE_LINK_STATUS_CHANGED 0x01000000 1312 1313 #define DRV_MSG_CODE_INITIATE_FLR 0x02000000 1314 #define REQ_BC_VER_4_INITIATE_FLR 0x00070213 1315 1316 #define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000 1317 #define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000 1318 #define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000 1319 #define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000 1320 1321 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff 1322 1323 u32 drv_mb_param; 1324 #define DRV_MSG_CODE_SET_MF_BW_MIN_MASK 0x00ff0000 1325 #define DRV_MSG_CODE_SET_MF_BW_MAX_MASK 0xff000000 1326 1327 #define DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET 0x00000002 1328 1329 #define DRV_MSG_CODE_LOAD_REQ_WITH_LFA 0x0000100a 1330 #define DRV_MSG_CODE_LOAD_REQ_FORCE_LFA 0x00002000 1331 1332 u32 fw_mb_header; 1333 #define FW_MSG_CODE_MASK 0xffff0000 1334 #define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000 1335 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000 1336 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000 1337 /* Load common chip is supported from bc 6.0.0 */ 1338 #define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP 0x00060000 1339 #define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 0x10130000 1340 1341 #define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000 1342 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000 1343 #define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000 1344 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000 1345 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000 1346 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000 1347 #define FW_MSG_CODE_DCC_DONE 0x30100000 1348 #define FW_MSG_CODE_LLDP_DONE 0x40100000 1349 #define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000 1350 #define FW_MSG_CODE_DIAG_REFUSE 0x50200000 1351 #define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000 1352 #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000 1353 #define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000 1354 #define FW_MSG_CODE_GET_KEY_DONE 0x80100000 1355 #define FW_MSG_CODE_NO_KEY 0x80f00000 1356 #define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000 1357 #define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000 1358 #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000 1359 #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000 1360 #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000 1361 #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000 1362 #define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS 0xa0100000 1363 #define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG 0xa0200000 1364 #define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED 0xa0300000 1365 #define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000 1366 #define FW_MSG_CODE_HW_SET_INVALID_IMAGE 0xb0100000 1367 1368 #define FW_MSG_CODE_AFEX_DRIVER_SETMAC_DONE 0xd0100000 1369 #define FW_MSG_CODE_AFEX_LISTGET_ACK 0xd1100000 1370 #define FW_MSG_CODE_AFEX_LISTSET_ACK 0xd2100000 1371 #define FW_MSG_CODE_AFEX_STATSGET_ACK 0xd3100000 1372 #define FW_MSG_CODE_AFEX_VIFSET_ACK 0xd4100000 1373 1374 #define FW_MSG_CODE_DRV_INFO_ACK 0xd8100000 1375 #define FW_MSG_CODE_DRV_INFO_NACK 0xd9100000 1376 1377 #define FW_MSG_CODE_EEE_RESULS_ACK 0xda100000 1378 1379 #define FW_MSG_CODE_RMMOD_ACK 0xdb100000 1380 1381 #define FW_MSG_CODE_SET_MF_BW_SENT 0xe0000000 1382 #define FW_MSG_CODE_SET_MF_BW_DONE 0xe1000000 1383 1384 #define FW_MSG_CODE_LINK_CHANGED_ACK 0x01100000 1385 1386 #define FW_MSG_CODE_LIC_CHALLENGE 0xff010000 1387 #define FW_MSG_CODE_LIC_RESPONSE 0xff020000 1388 #define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000 1389 #define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000 1390 1391 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff 1392 1393 u32 fw_mb_param; 1394 1395 u32 drv_pulse_mb; 1396 #define DRV_PULSE_SEQ_MASK 0x00007fff 1397 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000 1398 /* 1399 * The system time is in the format of 1400 * (year-2001)*12*32 + month*32 + day. 1401 */ 1402 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000 1403 /* 1404 * Indicate to the firmware not to go into the 1405 * OS-absent when it is not getting driver pulse. 1406 * This is used for debugging as well for PXE(MBA). 1407 */ 1408 1409 u32 mcp_pulse_mb; 1410 #define MCP_PULSE_SEQ_MASK 0x00007fff 1411 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000 1412 /* Indicates to the driver not to assert due to lack 1413 * of MCP response */ 1414 #define MCP_EVENT_MASK 0xffff0000 1415 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000 1416 1417 u32 iscsi_boot_signature; 1418 u32 iscsi_boot_block_offset; 1419 1420 u32 drv_status; 1421 #define DRV_STATUS_PMF 0x00000001 1422 #define DRV_STATUS_VF_DISABLED 0x00000002 1423 #define DRV_STATUS_SET_MF_BW 0x00000004 1424 #define DRV_STATUS_LINK_EVENT 0x00000008 1425 1426 #define DRV_STATUS_OEM_EVENT_MASK 0x00000070 1427 #define DRV_STATUS_OEM_DISABLE_ENABLE_PF 0x00000010 1428 #define DRV_STATUS_OEM_BANDWIDTH_ALLOCATION 0x00000020 1429 1430 #define DRV_STATUS_OEM_UPDATE_SVID 0x00000080 1431 1432 #define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00 1433 #define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100 1434 #define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200 1435 #define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS 0x00000400 1436 #define DRV_STATUS_DCC_RESERVED1 0x00000800 1437 #define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000 1438 #define DRV_STATUS_DCC_SET_PRIORITY 0x00002000 1439 1440 #define DRV_STATUS_DCBX_EVENT_MASK 0x000f0000 1441 #define DRV_STATUS_DCBX_NEGOTIATION_RESULTS 0x00010000 1442 #define DRV_STATUS_AFEX_EVENT_MASK 0x03f00000 1443 #define DRV_STATUS_AFEX_LISTGET_REQ 0x00100000 1444 #define DRV_STATUS_AFEX_LISTSET_REQ 0x00200000 1445 #define DRV_STATUS_AFEX_STATSGET_REQ 0x00400000 1446 #define DRV_STATUS_AFEX_VIFSET_REQ 0x00800000 1447 1448 #define DRV_STATUS_DRV_INFO_REQ 0x04000000 1449 1450 #define DRV_STATUS_EEE_NEGOTIATION_RESULTS 0x08000000 1451 1452 u32 virt_mac_upper; 1453 #define VIRT_MAC_SIGN_MASK 0xffff0000 1454 #define VIRT_MAC_SIGNATURE 0x564d0000 1455 u32 virt_mac_lower; 1456 1457 }; 1458 1459 1460 /**************************************************************************** 1461 * Management firmware state * 1462 ****************************************************************************/ 1463 /* Allocate 440 bytes for management firmware */ 1464 #define MGMTFW_STATE_WORD_SIZE 110 1465 1466 struct mgmtfw_state { 1467 u32 opaque[MGMTFW_STATE_WORD_SIZE]; 1468 }; 1469 1470 1471 /**************************************************************************** 1472 * Multi-Function configuration * 1473 ****************************************************************************/ 1474 struct shared_mf_cfg { 1475 1476 u32 clp_mb; 1477 #define SHARED_MF_CLP_SET_DEFAULT 0x00000000 1478 /* set by CLP */ 1479 #define SHARED_MF_CLP_EXIT 0x00000001 1480 /* set by MCP */ 1481 #define SHARED_MF_CLP_EXIT_DONE 0x00010000 1482 1483 }; 1484 1485 struct port_mf_cfg { 1486 1487 u32 dynamic_cfg; /* device control channel */ 1488 #define PORT_MF_CFG_E1HOV_TAG_MASK 0x0000ffff 1489 #define PORT_MF_CFG_E1HOV_TAG_SHIFT 0 1490 #define PORT_MF_CFG_E1HOV_TAG_DEFAULT PORT_MF_CFG_E1HOV_TAG_MASK 1491 1492 u32 reserved[1]; 1493 1494 }; 1495 1496 struct func_mf_cfg { 1497 1498 u32 config; 1499 /* E/R/I/D */ 1500 /* function 0 of each port cannot be hidden */ 1501 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001 1502 1503 #define FUNC_MF_CFG_PROTOCOL_MASK 0x00000006 1504 #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000000 1505 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002 1506 #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004 1507 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006 1508 #define FUNC_MF_CFG_PROTOCOL_DEFAULT \ 1509 FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 1510 1511 #define FUNC_MF_CFG_FUNC_DISABLED 0x00000008 1512 #define FUNC_MF_CFG_FUNC_DELETED 0x00000010 1513 1514 /* PRI */ 1515 /* 0 - low priority, 3 - high priority */ 1516 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300 1517 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8 1518 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000 1519 1520 /* MINBW, MAXBW */ 1521 /* value range - 0..100, increments in 100Mbps */ 1522 #define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000 1523 #define FUNC_MF_CFG_MIN_BW_SHIFT 16 1524 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000 1525 #define FUNC_MF_CFG_MAX_BW_MASK 0xff000000 1526 #define FUNC_MF_CFG_MAX_BW_SHIFT 24 1527 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000 1528 1529 u32 mac_upper; /* MAC */ 1530 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff 1531 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0 1532 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK 1533 u32 mac_lower; 1534 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff 1535 1536 u32 e1hov_tag; /* VNI */ 1537 #define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff 1538 #define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0 1539 #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK 1540 1541 /* afex default VLAN ID - 12 bits */ 1542 #define FUNC_MF_CFG_AFEX_VLAN_MASK 0x0fff0000 1543 #define FUNC_MF_CFG_AFEX_VLAN_SHIFT 16 1544 1545 u32 afex_config; 1546 #define FUNC_MF_CFG_AFEX_COS_FILTER_MASK 0x000000ff 1547 #define FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT 0 1548 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK 0x0000ff00 1549 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT 8 1550 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_VAL 0x00000100 1551 #define FUNC_MF_CFG_AFEX_VLAN_MODE_MASK 0x000f0000 1552 #define FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT 16 1553 1554 u32 reserved; 1555 }; 1556 1557 enum mf_cfg_afex_vlan_mode { 1558 FUNC_MF_CFG_AFEX_VLAN_TRUNK_MODE = 0, 1559 FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE, 1560 FUNC_MF_CFG_AFEX_VLAN_TRUNK_TAG_NATIVE_MODE 1561 }; 1562 1563 /* This structure is not applicable and should not be accessed on 57711 */ 1564 struct func_ext_cfg { 1565 u32 func_cfg; 1566 #define MACP_FUNC_CFG_FLAGS_MASK 0x0000007F 1567 #define MACP_FUNC_CFG_FLAGS_SHIFT 0 1568 #define MACP_FUNC_CFG_FLAGS_ENABLED 0x00000001 1569 #define MACP_FUNC_CFG_FLAGS_ETHERNET 0x00000002 1570 #define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD 0x00000004 1571 #define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD 0x00000008 1572 #define MACP_FUNC_CFG_PAUSE_ON_HOST_RING 0x00000080 1573 1574 u32 iscsi_mac_addr_upper; 1575 u32 iscsi_mac_addr_lower; 1576 1577 u32 fcoe_mac_addr_upper; 1578 u32 fcoe_mac_addr_lower; 1579 1580 u32 fcoe_wwn_port_name_upper; 1581 u32 fcoe_wwn_port_name_lower; 1582 1583 u32 fcoe_wwn_node_name_upper; 1584 u32 fcoe_wwn_node_name_lower; 1585 1586 u32 preserve_data; 1587 #define MF_FUNC_CFG_PRESERVE_L2_MAC (1<<0) 1588 #define MF_FUNC_CFG_PRESERVE_ISCSI_MAC (1<<1) 1589 #define MF_FUNC_CFG_PRESERVE_FCOE_MAC (1<<2) 1590 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_P (1<<3) 1591 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_N (1<<4) 1592 #define MF_FUNC_CFG_PRESERVE_TX_BW (1<<5) 1593 }; 1594 1595 struct mf_cfg { 1596 1597 struct shared_mf_cfg shared_mf_config; /* 0x4 */ 1598 /* 0x8*2*2=0x20 */ 1599 struct port_mf_cfg port_mf_config[NVM_PATH_MAX][PORT_MAX]; 1600 /* for all chips, there are 8 mf functions */ 1601 struct func_mf_cfg func_mf_config[E1H_FUNC_MAX]; /* 0x18 * 8 = 0xc0 */ 1602 /* 1603 * Extended configuration per function - this array does not exist and 1604 * should not be accessed on 57711 1605 */ 1606 struct func_ext_cfg func_ext_config[E1H_FUNC_MAX]; /* 0x28 * 8 = 0x140*/ 1607 }; /* 0x224 */ 1608 1609 /**************************************************************************** 1610 * Shared Memory Region * 1611 ****************************************************************************/ 1612 struct shmem_region { /* SharedMem Offset (size) */ 1613 1614 u32 validity_map[PORT_MAX]; /* 0x0 (4*2 = 0x8) */ 1615 #define SHR_MEM_FORMAT_REV_MASK 0xff000000 1616 #define SHR_MEM_FORMAT_REV_ID ('A'<<24) 1617 /* validity bits */ 1618 #define SHR_MEM_VALIDITY_PCI_CFG 0x00100000 1619 #define SHR_MEM_VALIDITY_MB 0x00200000 1620 #define SHR_MEM_VALIDITY_DEV_INFO 0x00400000 1621 #define SHR_MEM_VALIDITY_RESERVED 0x00000007 1622 /* One licensing bit should be set */ 1623 #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038 1624 #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008 1625 #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010 1626 #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020 1627 /* Active MFW */ 1628 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000 1629 #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0 1630 #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040 1631 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080 1632 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0 1633 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0 1634 1635 struct shm_dev_info dev_info; /* 0x8 (0x438) */ 1636 1637 struct license_key drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */ 1638 1639 /* FW information (for internal FW use) */ 1640 u32 fw_info_fio_offset; /* 0x4a8 (0x4) */ 1641 struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */ 1642 1643 struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */ 1644 1645 #ifdef BMAPI 1646 /* This is a variable length array */ 1647 /* the number of function depends on the chip type */ 1648 struct drv_func_mb func_mb[1]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */ 1649 #else 1650 /* the number of function depends on the chip type */ 1651 struct drv_func_mb func_mb[]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */ 1652 #endif /* BMAPI */ 1653 1654 }; /* 57710 = 0x6dc | 57711 = 0x7E4 | 57712 = 0x734 */ 1655 1656 /**************************************************************************** 1657 * Shared Memory 2 Region * 1658 ****************************************************************************/ 1659 /* The fw_flr_ack is actually built in the following way: */ 1660 /* 8 bit: PF ack */ 1661 /* 64 bit: VF ack */ 1662 /* 8 bit: ios_dis_ack */ 1663 /* In order to maintain endianity in the mailbox hsi, we want to keep using */ 1664 /* u32. The fw must have the VF right after the PF since this is how it */ 1665 /* access arrays(it expects always the VF to reside after the PF, and that */ 1666 /* makes the calculation much easier for it. ) */ 1667 /* In order to answer both limitations, and keep the struct small, the code */ 1668 /* will abuse the structure defined here to achieve the actual partition */ 1669 /* above */ 1670 /****************************************************************************/ 1671 struct fw_flr_ack { 1672 u32 pf_ack; 1673 u32 vf_ack[1]; 1674 u32 iov_dis_ack; 1675 }; 1676 1677 struct fw_flr_mb { 1678 u32 aggint; 1679 u32 opgen_addr; 1680 struct fw_flr_ack ack; 1681 }; 1682 1683 struct eee_remote_vals { 1684 u32 tx_tw; 1685 u32 rx_tw; 1686 }; 1687 1688 /**** SUPPORT FOR SHMEM ARRRAYS *** 1689 * The SHMEM HSI is aligned on 32 bit boundaries which makes it difficult to 1690 * define arrays with storage types smaller then unsigned dwords. 1691 * The macros below add generic support for SHMEM arrays with numeric elements 1692 * that can span 2,4,8 or 16 bits. The array underlying type is a 32 bit dword 1693 * array with individual bit-filed elements accessed using shifts and masks. 1694 * 1695 */ 1696 1697 /* eb is the bitwidth of a single element */ 1698 #define SHMEM_ARRAY_MASK(eb) ((1<<(eb))-1) 1699 #define SHMEM_ARRAY_ENTRY(i, eb) ((i)/(32/(eb))) 1700 1701 /* the bit-position macro allows the used to flip the order of the arrays 1702 * elements on a per byte or word boundary. 1703 * 1704 * example: an array with 8 entries each 4 bit wide. This array will fit into 1705 * a single dword. The diagrmas below show the array order of the nibbles. 1706 * 1707 * SHMEM_ARRAY_BITPOS(i, 4, 4) defines the stadard ordering: 1708 * 1709 * | | | | 1710 * 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 1711 * | | | | 1712 * 1713 * SHMEM_ARRAY_BITPOS(i, 4, 8) defines a flip ordering per byte: 1714 * 1715 * | | | | 1716 * 1 | 0 | 3 | 2 | 5 | 4 | 7 | 6 | 1717 * | | | | 1718 * 1719 * SHMEM_ARRAY_BITPOS(i, 4, 16) defines a flip ordering per word: 1720 * 1721 * | | | | 1722 * 3 | 2 | 1 | 0 | 7 | 6 | 5 | 4 | 1723 * | | | | 1724 */ 1725 #define SHMEM_ARRAY_BITPOS(i, eb, fb) \ 1726 ((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \ 1727 (((i)%((fb)/(eb))) * (eb))) 1728 1729 #define SHMEM_ARRAY_GET(a, i, eb, fb) \ 1730 ((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) & \ 1731 SHMEM_ARRAY_MASK(eb)) 1732 1733 #define SHMEM_ARRAY_SET(a, i, eb, fb, val) \ 1734 do { \ 1735 a[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) << \ 1736 SHMEM_ARRAY_BITPOS(i, eb, fb)); \ 1737 a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) << \ 1738 SHMEM_ARRAY_BITPOS(i, eb, fb)); \ 1739 } while (0) 1740 1741 1742 /****START OF DCBX STRUCTURES DECLARATIONS****/ 1743 #define DCBX_MAX_NUM_PRI_PG_ENTRIES 8 1744 #define DCBX_PRI_PG_BITWIDTH 4 1745 #define DCBX_PRI_PG_FBITS 8 1746 #define DCBX_PRI_PG_GET(a, i) \ 1747 SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS) 1748 #define DCBX_PRI_PG_SET(a, i, val) \ 1749 SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val) 1750 #define DCBX_MAX_NUM_PG_BW_ENTRIES 8 1751 #define DCBX_BW_PG_BITWIDTH 8 1752 #define DCBX_PG_BW_GET(a, i) \ 1753 SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH) 1754 #define DCBX_PG_BW_SET(a, i, val) \ 1755 SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val) 1756 #define DCBX_STRICT_PRI_PG 15 1757 #define DCBX_MAX_APP_PROTOCOL 16 1758 #define FCOE_APP_IDX 0 1759 #define ISCSI_APP_IDX 1 1760 #define PREDEFINED_APP_IDX_MAX 2 1761 1762 1763 /* Big/Little endian have the same representation. */ 1764 struct dcbx_ets_feature { 1765 /* 1766 * For Admin MIB - is this feature supported by the 1767 * driver | For Local MIB - should this feature be enabled. 1768 */ 1769 u32 enabled; 1770 u32 pg_bw_tbl[2]; 1771 u32 pri_pg_tbl[1]; 1772 }; 1773 1774 /* Driver structure in LE */ 1775 struct dcbx_pfc_feature { 1776 #ifdef __BIG_ENDIAN 1777 u8 pri_en_bitmap; 1778 #define DCBX_PFC_PRI_0 0x01 1779 #define DCBX_PFC_PRI_1 0x02 1780 #define DCBX_PFC_PRI_2 0x04 1781 #define DCBX_PFC_PRI_3 0x08 1782 #define DCBX_PFC_PRI_4 0x10 1783 #define DCBX_PFC_PRI_5 0x20 1784 #define DCBX_PFC_PRI_6 0x40 1785 #define DCBX_PFC_PRI_7 0x80 1786 u8 pfc_caps; 1787 u8 reserved; 1788 u8 enabled; 1789 #elif defined(__LITTLE_ENDIAN) 1790 u8 enabled; 1791 u8 reserved; 1792 u8 pfc_caps; 1793 u8 pri_en_bitmap; 1794 #define DCBX_PFC_PRI_0 0x01 1795 #define DCBX_PFC_PRI_1 0x02 1796 #define DCBX_PFC_PRI_2 0x04 1797 #define DCBX_PFC_PRI_3 0x08 1798 #define DCBX_PFC_PRI_4 0x10 1799 #define DCBX_PFC_PRI_5 0x20 1800 #define DCBX_PFC_PRI_6 0x40 1801 #define DCBX_PFC_PRI_7 0x80 1802 #endif 1803 }; 1804 1805 struct dcbx_app_priority_entry { 1806 #ifdef __BIG_ENDIAN 1807 u16 app_id; 1808 u8 pri_bitmap; 1809 u8 appBitfield; 1810 #define DCBX_APP_ENTRY_VALID 0x01 1811 #define DCBX_APP_ENTRY_SF_MASK 0x30 1812 #define DCBX_APP_ENTRY_SF_SHIFT 4 1813 #define DCBX_APP_SF_ETH_TYPE 0x10 1814 #define DCBX_APP_SF_PORT 0x20 1815 #elif defined(__LITTLE_ENDIAN) 1816 u8 appBitfield; 1817 #define DCBX_APP_ENTRY_VALID 0x01 1818 #define DCBX_APP_ENTRY_SF_MASK 0x30 1819 #define DCBX_APP_ENTRY_SF_SHIFT 4 1820 #define DCBX_APP_SF_ETH_TYPE 0x10 1821 #define DCBX_APP_SF_PORT 0x20 1822 u8 pri_bitmap; 1823 u16 app_id; 1824 #endif 1825 }; 1826 1827 1828 /* FW structure in BE */ 1829 struct dcbx_app_priority_feature { 1830 #ifdef __BIG_ENDIAN 1831 u8 reserved; 1832 u8 default_pri; 1833 u8 tc_supported; 1834 u8 enabled; 1835 #elif defined(__LITTLE_ENDIAN) 1836 u8 enabled; 1837 u8 tc_supported; 1838 u8 default_pri; 1839 u8 reserved; 1840 #endif 1841 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL]; 1842 }; 1843 1844 /* FW structure in BE */ 1845 struct dcbx_features { 1846 /* PG feature */ 1847 struct dcbx_ets_feature ets; 1848 /* PFC feature */ 1849 struct dcbx_pfc_feature pfc; 1850 /* APP feature */ 1851 struct dcbx_app_priority_feature app; 1852 }; 1853 1854 /* LLDP protocol parameters */ 1855 /* FW structure in BE */ 1856 struct lldp_params { 1857 #ifdef __BIG_ENDIAN 1858 u8 msg_fast_tx_interval; 1859 u8 msg_tx_hold; 1860 u8 msg_tx_interval; 1861 u8 admin_status; 1862 #define LLDP_TX_ONLY 0x01 1863 #define LLDP_RX_ONLY 0x02 1864 #define LLDP_TX_RX 0x03 1865 #define LLDP_DISABLED 0x04 1866 u8 reserved1; 1867 u8 tx_fast; 1868 u8 tx_crd_max; 1869 u8 tx_crd; 1870 #elif defined(__LITTLE_ENDIAN) 1871 u8 admin_status; 1872 #define LLDP_TX_ONLY 0x01 1873 #define LLDP_RX_ONLY 0x02 1874 #define LLDP_TX_RX 0x03 1875 #define LLDP_DISABLED 0x04 1876 u8 msg_tx_interval; 1877 u8 msg_tx_hold; 1878 u8 msg_fast_tx_interval; 1879 u8 tx_crd; 1880 u8 tx_crd_max; 1881 u8 tx_fast; 1882 u8 reserved1; 1883 #endif 1884 #define REM_CHASSIS_ID_STAT_LEN 4 1885 #define REM_PORT_ID_STAT_LEN 4 1886 /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */ 1887 u32 peer_chassis_id[REM_CHASSIS_ID_STAT_LEN]; 1888 /* Holds remote Port ID TLV header, subtype and 9B of payload. */ 1889 u32 peer_port_id[REM_PORT_ID_STAT_LEN]; 1890 }; 1891 1892 struct lldp_dcbx_stat { 1893 #define LOCAL_CHASSIS_ID_STAT_LEN 2 1894 #define LOCAL_PORT_ID_STAT_LEN 2 1895 /* Holds local Chassis ID 8B payload of constant subtype 4. */ 1896 u32 local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN]; 1897 /* Holds local Port ID 8B payload of constant subtype 3. */ 1898 u32 local_port_id[LOCAL_PORT_ID_STAT_LEN]; 1899 /* Number of DCBX frames transmitted. */ 1900 u32 num_tx_dcbx_pkts; 1901 /* Number of DCBX frames received. */ 1902 u32 num_rx_dcbx_pkts; 1903 }; 1904 1905 /* ADMIN MIB - DCBX local machine default configuration. */ 1906 struct lldp_admin_mib { 1907 u32 ver_cfg_flags; 1908 #define DCBX_ETS_CONFIG_TX_ENABLED 0x00000001 1909 #define DCBX_PFC_CONFIG_TX_ENABLED 0x00000002 1910 #define DCBX_APP_CONFIG_TX_ENABLED 0x00000004 1911 #define DCBX_ETS_RECO_TX_ENABLED 0x00000008 1912 #define DCBX_ETS_RECO_VALID 0x00000010 1913 #define DCBX_ETS_WILLING 0x00000020 1914 #define DCBX_PFC_WILLING 0x00000040 1915 #define DCBX_APP_WILLING 0x00000080 1916 #define DCBX_VERSION_CEE 0x00000100 1917 #define DCBX_VERSION_IEEE 0x00000200 1918 #define DCBX_DCBX_ENABLED 0x00000400 1919 #define DCBX_CEE_VERSION_MASK 0x0000f000 1920 #define DCBX_CEE_VERSION_SHIFT 12 1921 #define DCBX_CEE_MAX_VERSION_MASK 0x000f0000 1922 #define DCBX_CEE_MAX_VERSION_SHIFT 16 1923 struct dcbx_features features; 1924 }; 1925 1926 /* REMOTE MIB - remote machine DCBX configuration. */ 1927 struct lldp_remote_mib { 1928 u32 prefix_seq_num; 1929 u32 flags; 1930 #define DCBX_ETS_TLV_RX 0x00000001 1931 #define DCBX_PFC_TLV_RX 0x00000002 1932 #define DCBX_APP_TLV_RX 0x00000004 1933 #define DCBX_ETS_RX_ERROR 0x00000010 1934 #define DCBX_PFC_RX_ERROR 0x00000020 1935 #define DCBX_APP_RX_ERROR 0x00000040 1936 #define DCBX_ETS_REM_WILLING 0x00000100 1937 #define DCBX_PFC_REM_WILLING 0x00000200 1938 #define DCBX_APP_REM_WILLING 0x00000400 1939 #define DCBX_REMOTE_ETS_RECO_VALID 0x00001000 1940 #define DCBX_REMOTE_MIB_VALID 0x00002000 1941 struct dcbx_features features; 1942 u32 suffix_seq_num; 1943 }; 1944 1945 /* LOCAL MIB - operational DCBX configuration - transmitted on Tx LLDPDU. */ 1946 struct lldp_local_mib { 1947 u32 prefix_seq_num; 1948 /* Indicates if there is mismatch with negotiation results. */ 1949 u32 error; 1950 #define DCBX_LOCAL_ETS_ERROR 0x00000001 1951 #define DCBX_LOCAL_PFC_ERROR 0x00000002 1952 #define DCBX_LOCAL_APP_ERROR 0x00000004 1953 #define DCBX_LOCAL_PFC_MISMATCH 0x00000010 1954 #define DCBX_LOCAL_APP_MISMATCH 0x00000020 1955 #define DCBX_REMOTE_MIB_ERROR 0x00000040 1956 #define DCBX_REMOTE_ETS_TLV_NOT_FOUND 0x00000080 1957 #define DCBX_REMOTE_PFC_TLV_NOT_FOUND 0x00000100 1958 #define DCBX_REMOTE_APP_TLV_NOT_FOUND 0x00000200 1959 struct dcbx_features features; 1960 u32 suffix_seq_num; 1961 }; 1962 /***END OF DCBX STRUCTURES DECLARATIONS***/ 1963 1964 /***********************************************************/ 1965 /* Elink section */ 1966 /***********************************************************/ 1967 #define SHMEM_LINK_CONFIG_SIZE 2 1968 struct shmem_lfa { 1969 u32 req_duplex; 1970 #define REQ_DUPLEX_PHY0_MASK 0x0000ffff 1971 #define REQ_DUPLEX_PHY0_SHIFT 0 1972 #define REQ_DUPLEX_PHY1_MASK 0xffff0000 1973 #define REQ_DUPLEX_PHY1_SHIFT 16 1974 u32 req_flow_ctrl; 1975 #define REQ_FLOW_CTRL_PHY0_MASK 0x0000ffff 1976 #define REQ_FLOW_CTRL_PHY0_SHIFT 0 1977 #define REQ_FLOW_CTRL_PHY1_MASK 0xffff0000 1978 #define REQ_FLOW_CTRL_PHY1_SHIFT 16 1979 u32 req_line_speed; /* Also determine AutoNeg */ 1980 #define REQ_LINE_SPD_PHY0_MASK 0x0000ffff 1981 #define REQ_LINE_SPD_PHY0_SHIFT 0 1982 #define REQ_LINE_SPD_PHY1_MASK 0xffff0000 1983 #define REQ_LINE_SPD_PHY1_SHIFT 16 1984 u32 speed_cap_mask[SHMEM_LINK_CONFIG_SIZE]; 1985 u32 additional_config; 1986 #define REQ_FC_AUTO_ADV_MASK 0x0000ffff 1987 #define REQ_FC_AUTO_ADV0_SHIFT 0 1988 #define NO_LFA_DUE_TO_DCC_MASK 0x00010000 1989 u32 lfa_sts; 1990 #define LFA_LINK_FLAP_REASON_OFFSET 0 1991 #define LFA_LINK_FLAP_REASON_MASK 0x000000ff 1992 #define LFA_LINK_DOWN 0x1 1993 #define LFA_LOOPBACK_ENABLED 0x2 1994 #define LFA_DUPLEX_MISMATCH 0x3 1995 #define LFA_MFW_IS_TOO_OLD 0x4 1996 #define LFA_LINK_SPEED_MISMATCH 0x5 1997 #define LFA_FLOW_CTRL_MISMATCH 0x6 1998 #define LFA_SPEED_CAP_MISMATCH 0x7 1999 #define LFA_DCC_LFA_DISABLED 0x8 2000 #define LFA_EEE_MISMATCH 0x9 2001 2002 #define LINK_FLAP_AVOIDANCE_COUNT_OFFSET 8 2003 #define LINK_FLAP_AVOIDANCE_COUNT_MASK 0x0000ff00 2004 2005 #define LINK_FLAP_COUNT_OFFSET 16 2006 #define LINK_FLAP_COUNT_MASK 0x00ff0000 2007 2008 #define LFA_FLAGS_MASK 0xff000000 2009 #define SHMEM_LFA_DONT_CLEAR_STAT (1<<24) 2010 }; 2011 2012 /* Used to support NSCI get OS driver version 2013 * on driver load the version value will be set 2014 * on driver unload driver value of 0x0 will be set. 2015 */ 2016 struct os_drv_ver { 2017 #define DRV_VER_NOT_LOADED 0 2018 2019 /* personalties order is important */ 2020 #define DRV_PERS_ETHERNET 0 2021 #define DRV_PERS_ISCSI 1 2022 #define DRV_PERS_FCOE 2 2023 2024 /* shmem2 struct is constant can't add more personalties here */ 2025 #define MAX_DRV_PERS 3 2026 u32 versions[MAX_DRV_PERS]; 2027 }; 2028 2029 struct ncsi_oem_fcoe_features { 2030 u32 fcoe_features1; 2031 #define FCOE_FEATURES1_IOS_PER_CONNECTION_MASK 0x0000FFFF 2032 #define FCOE_FEATURES1_IOS_PER_CONNECTION_OFFSET 0 2033 2034 #define FCOE_FEATURES1_LOGINS_PER_PORT_MASK 0xFFFF0000 2035 #define FCOE_FEATURES1_LOGINS_PER_PORT_OFFSET 16 2036 2037 u32 fcoe_features2; 2038 #define FCOE_FEATURES2_EXCHANGES_MASK 0x0000FFFF 2039 #define FCOE_FEATURES2_EXCHANGES_OFFSET 0 2040 2041 #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_MASK 0xFFFF0000 2042 #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_OFFSET 16 2043 2044 u32 fcoe_features3; 2045 #define FCOE_FEATURES3_TARGETS_SUPPORTED_MASK 0x0000FFFF 2046 #define FCOE_FEATURES3_TARGETS_SUPPORTED_OFFSET 0 2047 2048 #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_MASK 0xFFFF0000 2049 #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_OFFSET 16 2050 2051 u32 fcoe_features4; 2052 #define FCOE_FEATURES4_FEATURE_SETTINGS_MASK 0x0000000F 2053 #define FCOE_FEATURES4_FEATURE_SETTINGS_OFFSET 0 2054 }; 2055 2056 struct ncsi_oem_data { 2057 u32 driver_version[4]; 2058 struct ncsi_oem_fcoe_features ncsi_oem_fcoe_features; 2059 }; 2060 2061 struct shmem2_region { 2062 2063 u32 size; /* 0x0000 */ 2064 2065 u32 dcc_support; /* 0x0004 */ 2066 #define SHMEM_DCC_SUPPORT_NONE 0x00000000 2067 #define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV 0x00000001 2068 #define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV 0x00000004 2069 #define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV 0x00000008 2070 #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040 2071 #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080 2072 2073 u32 ext_phy_fw_version2[PORT_MAX]; /* 0x0008 */ 2074 /* 2075 * For backwards compatibility, if the mf_cfg_addr does not exist 2076 * (the size filed is smaller than 0xc) the mf_cfg resides at the 2077 * end of struct shmem_region 2078 */ 2079 u32 mf_cfg_addr; /* 0x0010 */ 2080 #define SHMEM_MF_CFG_ADDR_NONE 0x00000000 2081 2082 struct fw_flr_mb flr_mb; /* 0x0014 */ 2083 u32 dcbx_lldp_params_offset; /* 0x0028 */ 2084 #define SHMEM_LLDP_DCBX_PARAMS_NONE 0x00000000 2085 u32 dcbx_neg_res_offset; /* 0x002c */ 2086 #define SHMEM_DCBX_NEG_RES_NONE 0x00000000 2087 u32 dcbx_remote_mib_offset; /* 0x0030 */ 2088 #define SHMEM_DCBX_REMOTE_MIB_NONE 0x00000000 2089 /* 2090 * The other shmemX_base_addr holds the other path's shmem address 2091 * required for example in case of common phy init, or for path1 to know 2092 * the address of mcp debug trace which is located in offset from shmem 2093 * of path0 2094 */ 2095 u32 other_shmem_base_addr; /* 0x0034 */ 2096 u32 other_shmem2_base_addr; /* 0x0038 */ 2097 /* 2098 * mcp_vf_disabled is set by the MCP to indicate the driver about VFs 2099 * which were disabled/flred 2100 */ 2101 u32 mcp_vf_disabled[E2_VF_MAX / 32]; /* 0x003c */ 2102 2103 /* 2104 * drv_ack_vf_disabled is set by the PF driver to ack handled disabled 2105 * VFs 2106 */ 2107 u32 drv_ack_vf_disabled[E2_FUNC_MAX][E2_VF_MAX / 32]; /* 0x0044 */ 2108 2109 u32 dcbx_lldp_dcbx_stat_offset; /* 0x0064 */ 2110 #define SHMEM_LLDP_DCBX_STAT_NONE 0x00000000 2111 2112 /* 2113 * edebug_driver_if field is used to transfer messages between edebug 2114 * app to the driver through shmem2. 2115 * 2116 * message format: 2117 * bits 0-2 - function number / instance of driver to perform request 2118 * bits 3-5 - op code / is_ack? 2119 * bits 6-63 - data 2120 */ 2121 u32 edebug_driver_if[2]; /* 0x0068 */ 2122 #define EDEBUG_DRIVER_IF_OP_CODE_GET_PHYS_ADDR 1 2123 #define EDEBUG_DRIVER_IF_OP_CODE_GET_BUS_ADDR 2 2124 #define EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT 3 2125 2126 u32 nvm_retain_bitmap_addr; /* 0x0070 */ 2127 2128 /* afex support of that driver */ 2129 u32 afex_driver_support; /* 0x0074 */ 2130 #define SHMEM_AFEX_VERSION_MASK 0x100f 2131 #define SHMEM_AFEX_SUPPORTED_VERSION_ONE 0x1001 2132 #define SHMEM_AFEX_REDUCED_DRV_LOADED 0x8000 2133 2134 /* driver receives addr in scratchpad to which it should respond */ 2135 u32 afex_scratchpad_addr_to_write[E2_FUNC_MAX]; 2136 2137 /* generic params from MCP to driver (value depends on the msg sent 2138 * to driver 2139 */ 2140 u32 afex_param1_to_driver[E2_FUNC_MAX]; /* 0x0088 */ 2141 u32 afex_param2_to_driver[E2_FUNC_MAX]; /* 0x0098 */ 2142 2143 u32 swim_base_addr; /* 0x0108 */ 2144 u32 swim_funcs; 2145 u32 swim_main_cb; 2146 2147 /* bitmap notifying which VIF profiles stored in nvram are enabled by 2148 * switch 2149 */ 2150 u32 afex_profiles_enabled[2]; 2151 2152 /* generic flags controlled by the driver */ 2153 u32 drv_flags; 2154 #define DRV_FLAGS_DCB_CONFIGURED 0x0 2155 #define DRV_FLAGS_DCB_CONFIGURATION_ABORTED 0x1 2156 #define DRV_FLAGS_DCB_MFW_CONFIGURED 0x2 2157 2158 #define DRV_FLAGS_PORT_MASK ((1 << DRV_FLAGS_DCB_CONFIGURED) | \ 2159 (1 << DRV_FLAGS_DCB_CONFIGURATION_ABORTED) | \ 2160 (1 << DRV_FLAGS_DCB_MFW_CONFIGURED)) 2161 /* pointer to extended dev_info shared data copied from nvm image */ 2162 u32 extended_dev_info_shared_addr; 2163 u32 ncsi_oem_data_addr; 2164 2165 u32 ocsd_host_addr; /* initialized by option ROM */ 2166 u32 ocbb_host_addr; /* initialized by option ROM */ 2167 u32 ocsd_req_update_interval; /* initialized by option ROM */ 2168 u32 temperature_in_half_celsius; 2169 u32 glob_struct_in_host; 2170 2171 u32 dcbx_neg_res_ext_offset; 2172 #define SHMEM_DCBX_NEG_RES_EXT_NONE 0x00000000 2173 2174 u32 drv_capabilities_flag[E2_FUNC_MAX]; 2175 #define DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED 0x00000001 2176 #define DRV_FLAGS_CAPABILITIES_LOADED_L2 0x00000002 2177 #define DRV_FLAGS_CAPABILITIES_LOADED_FCOE 0x00000004 2178 #define DRV_FLAGS_CAPABILITIES_LOADED_ISCSI 0x00000008 2179 2180 u32 extended_dev_info_shared_cfg_size; 2181 2182 u32 dcbx_en[PORT_MAX]; 2183 2184 /* The offset points to the multi threaded meta structure */ 2185 u32 multi_thread_data_offset; 2186 2187 /* address of DMAable host address holding values from the drivers */ 2188 u32 drv_info_host_addr_lo; 2189 u32 drv_info_host_addr_hi; 2190 2191 /* general values written by the MFW (such as current version) */ 2192 u32 drv_info_control; 2193 #define DRV_INFO_CONTROL_VER_MASK 0x000000ff 2194 #define DRV_INFO_CONTROL_VER_SHIFT 0 2195 #define DRV_INFO_CONTROL_OP_CODE_MASK 0x0000ff00 2196 #define DRV_INFO_CONTROL_OP_CODE_SHIFT 8 2197 u32 ibft_host_addr; /* initialized by option ROM */ 2198 struct eee_remote_vals eee_remote_vals[PORT_MAX]; 2199 u32 reserved[E2_FUNC_MAX]; 2200 2201 2202 /* the status of EEE auto-negotiation 2203 * bits 15:0 the configured tx-lpi entry timer value. Depends on bit 31. 2204 * bits 19:16 the supported modes for EEE. 2205 * bits 23:20 the speeds advertised for EEE. 2206 * bits 27:24 the speeds the Link partner advertised for EEE. 2207 * The supported/adv. modes in bits 27:19 originate from the 2208 * SHMEM_EEE_XXX_ADV definitions (where XXX is replaced by speed). 2209 * bit 28 when 1'b1 EEE was requested. 2210 * bit 29 when 1'b1 tx lpi was requested. 2211 * bit 30 when 1'b1 EEE was negotiated. Tx lpi will be asserted iff 2212 * 30:29 are 2'b11. 2213 * bit 31 when 1'b0 bits 15:0 contain a PORT_FEAT_CFG_EEE_ define as 2214 * value. When 1'b1 those bits contains a value times 16 microseconds. 2215 */ 2216 u32 eee_status[PORT_MAX]; 2217 #define SHMEM_EEE_TIMER_MASK 0x0000ffff 2218 #define SHMEM_EEE_SUPPORTED_MASK 0x000f0000 2219 #define SHMEM_EEE_SUPPORTED_SHIFT 16 2220 #define SHMEM_EEE_ADV_STATUS_MASK 0x00f00000 2221 #define SHMEM_EEE_100M_ADV (1<<0) 2222 #define SHMEM_EEE_1G_ADV (1<<1) 2223 #define SHMEM_EEE_10G_ADV (1<<2) 2224 #define SHMEM_EEE_ADV_STATUS_SHIFT 20 2225 #define SHMEM_EEE_LP_ADV_STATUS_MASK 0x0f000000 2226 #define SHMEM_EEE_LP_ADV_STATUS_SHIFT 24 2227 #define SHMEM_EEE_REQUESTED_BIT 0x10000000 2228 #define SHMEM_EEE_LPI_REQUESTED_BIT 0x20000000 2229 #define SHMEM_EEE_ACTIVE_BIT 0x40000000 2230 #define SHMEM_EEE_TIME_OUTPUT_BIT 0x80000000 2231 2232 u32 sizeof_port_stats; 2233 2234 /* Link Flap Avoidance */ 2235 u32 lfa_host_addr[PORT_MAX]; 2236 u32 reserved1; 2237 2238 u32 reserved2; /* Offset 0x148 */ 2239 u32 reserved3; /* Offset 0x14C */ 2240 u32 reserved4; /* Offset 0x150 */ 2241 u32 link_attr_sync[PORT_MAX]; /* Offset 0x154 */ 2242 #define LINK_ATTR_SYNC_KR2_ENABLE 0x00000001 2243 #define LINK_SFP_EEPROM_COMP_CODE_MASK 0x0000ff00 2244 #define LINK_SFP_EEPROM_COMP_CODE_SHIFT 8 2245 #define LINK_SFP_EEPROM_COMP_CODE_SR 0x00001000 2246 #define LINK_SFP_EEPROM_COMP_CODE_LR 0x00002000 2247 #define LINK_SFP_EEPROM_COMP_CODE_LRM 0x00004000 2248 2249 u32 reserved5[2]; 2250 u32 reserved6[PORT_MAX]; 2251 2252 /* driver version for each personality */ 2253 struct os_drv_ver func_os_drv_ver[E2_FUNC_MAX]; /* Offset 0x16c */ 2254 2255 /* Flag to the driver that PF's drv_info_host_addr buffer was read */ 2256 u32 mfw_drv_indication; 2257 2258 /* We use indication for each PF (0..3) */ 2259 #define MFW_DRV_IND_READ_DONE_OFFSET(_pf_) (1 << (_pf_)) 2260 }; 2261 2262 2263 struct emac_stats { 2264 u32 rx_stat_ifhcinoctets; 2265 u32 rx_stat_ifhcinbadoctets; 2266 u32 rx_stat_etherstatsfragments; 2267 u32 rx_stat_ifhcinucastpkts; 2268 u32 rx_stat_ifhcinmulticastpkts; 2269 u32 rx_stat_ifhcinbroadcastpkts; 2270 u32 rx_stat_dot3statsfcserrors; 2271 u32 rx_stat_dot3statsalignmenterrors; 2272 u32 rx_stat_dot3statscarriersenseerrors; 2273 u32 rx_stat_xonpauseframesreceived; 2274 u32 rx_stat_xoffpauseframesreceived; 2275 u32 rx_stat_maccontrolframesreceived; 2276 u32 rx_stat_xoffstateentered; 2277 u32 rx_stat_dot3statsframestoolong; 2278 u32 rx_stat_etherstatsjabbers; 2279 u32 rx_stat_etherstatsundersizepkts; 2280 u32 rx_stat_etherstatspkts64octets; 2281 u32 rx_stat_etherstatspkts65octetsto127octets; 2282 u32 rx_stat_etherstatspkts128octetsto255octets; 2283 u32 rx_stat_etherstatspkts256octetsto511octets; 2284 u32 rx_stat_etherstatspkts512octetsto1023octets; 2285 u32 rx_stat_etherstatspkts1024octetsto1522octets; 2286 u32 rx_stat_etherstatspktsover1522octets; 2287 2288 u32 rx_stat_falsecarriererrors; 2289 2290 u32 tx_stat_ifhcoutoctets; 2291 u32 tx_stat_ifhcoutbadoctets; 2292 u32 tx_stat_etherstatscollisions; 2293 u32 tx_stat_outxonsent; 2294 u32 tx_stat_outxoffsent; 2295 u32 tx_stat_flowcontroldone; 2296 u32 tx_stat_dot3statssinglecollisionframes; 2297 u32 tx_stat_dot3statsmultiplecollisionframes; 2298 u32 tx_stat_dot3statsdeferredtransmissions; 2299 u32 tx_stat_dot3statsexcessivecollisions; 2300 u32 tx_stat_dot3statslatecollisions; 2301 u32 tx_stat_ifhcoutucastpkts; 2302 u32 tx_stat_ifhcoutmulticastpkts; 2303 u32 tx_stat_ifhcoutbroadcastpkts; 2304 u32 tx_stat_etherstatspkts64octets; 2305 u32 tx_stat_etherstatspkts65octetsto127octets; 2306 u32 tx_stat_etherstatspkts128octetsto255octets; 2307 u32 tx_stat_etherstatspkts256octetsto511octets; 2308 u32 tx_stat_etherstatspkts512octetsto1023octets; 2309 u32 tx_stat_etherstatspkts1024octetsto1522octets; 2310 u32 tx_stat_etherstatspktsover1522octets; 2311 u32 tx_stat_dot3statsinternalmactransmiterrors; 2312 }; 2313 2314 2315 struct bmac1_stats { 2316 u32 tx_stat_gtpkt_lo; 2317 u32 tx_stat_gtpkt_hi; 2318 u32 tx_stat_gtxpf_lo; 2319 u32 tx_stat_gtxpf_hi; 2320 u32 tx_stat_gtfcs_lo; 2321 u32 tx_stat_gtfcs_hi; 2322 u32 tx_stat_gtmca_lo; 2323 u32 tx_stat_gtmca_hi; 2324 u32 tx_stat_gtbca_lo; 2325 u32 tx_stat_gtbca_hi; 2326 u32 tx_stat_gtfrg_lo; 2327 u32 tx_stat_gtfrg_hi; 2328 u32 tx_stat_gtovr_lo; 2329 u32 tx_stat_gtovr_hi; 2330 u32 tx_stat_gt64_lo; 2331 u32 tx_stat_gt64_hi; 2332 u32 tx_stat_gt127_lo; 2333 u32 tx_stat_gt127_hi; 2334 u32 tx_stat_gt255_lo; 2335 u32 tx_stat_gt255_hi; 2336 u32 tx_stat_gt511_lo; 2337 u32 tx_stat_gt511_hi; 2338 u32 tx_stat_gt1023_lo; 2339 u32 tx_stat_gt1023_hi; 2340 u32 tx_stat_gt1518_lo; 2341 u32 tx_stat_gt1518_hi; 2342 u32 tx_stat_gt2047_lo; 2343 u32 tx_stat_gt2047_hi; 2344 u32 tx_stat_gt4095_lo; 2345 u32 tx_stat_gt4095_hi; 2346 u32 tx_stat_gt9216_lo; 2347 u32 tx_stat_gt9216_hi; 2348 u32 tx_stat_gt16383_lo; 2349 u32 tx_stat_gt16383_hi; 2350 u32 tx_stat_gtmax_lo; 2351 u32 tx_stat_gtmax_hi; 2352 u32 tx_stat_gtufl_lo; 2353 u32 tx_stat_gtufl_hi; 2354 u32 tx_stat_gterr_lo; 2355 u32 tx_stat_gterr_hi; 2356 u32 tx_stat_gtbyt_lo; 2357 u32 tx_stat_gtbyt_hi; 2358 2359 u32 rx_stat_gr64_lo; 2360 u32 rx_stat_gr64_hi; 2361 u32 rx_stat_gr127_lo; 2362 u32 rx_stat_gr127_hi; 2363 u32 rx_stat_gr255_lo; 2364 u32 rx_stat_gr255_hi; 2365 u32 rx_stat_gr511_lo; 2366 u32 rx_stat_gr511_hi; 2367 u32 rx_stat_gr1023_lo; 2368 u32 rx_stat_gr1023_hi; 2369 u32 rx_stat_gr1518_lo; 2370 u32 rx_stat_gr1518_hi; 2371 u32 rx_stat_gr2047_lo; 2372 u32 rx_stat_gr2047_hi; 2373 u32 rx_stat_gr4095_lo; 2374 u32 rx_stat_gr4095_hi; 2375 u32 rx_stat_gr9216_lo; 2376 u32 rx_stat_gr9216_hi; 2377 u32 rx_stat_gr16383_lo; 2378 u32 rx_stat_gr16383_hi; 2379 u32 rx_stat_grmax_lo; 2380 u32 rx_stat_grmax_hi; 2381 u32 rx_stat_grpkt_lo; 2382 u32 rx_stat_grpkt_hi; 2383 u32 rx_stat_grfcs_lo; 2384 u32 rx_stat_grfcs_hi; 2385 u32 rx_stat_grmca_lo; 2386 u32 rx_stat_grmca_hi; 2387 u32 rx_stat_grbca_lo; 2388 u32 rx_stat_grbca_hi; 2389 u32 rx_stat_grxcf_lo; 2390 u32 rx_stat_grxcf_hi; 2391 u32 rx_stat_grxpf_lo; 2392 u32 rx_stat_grxpf_hi; 2393 u32 rx_stat_grxuo_lo; 2394 u32 rx_stat_grxuo_hi; 2395 u32 rx_stat_grjbr_lo; 2396 u32 rx_stat_grjbr_hi; 2397 u32 rx_stat_grovr_lo; 2398 u32 rx_stat_grovr_hi; 2399 u32 rx_stat_grflr_lo; 2400 u32 rx_stat_grflr_hi; 2401 u32 rx_stat_grmeg_lo; 2402 u32 rx_stat_grmeg_hi; 2403 u32 rx_stat_grmeb_lo; 2404 u32 rx_stat_grmeb_hi; 2405 u32 rx_stat_grbyt_lo; 2406 u32 rx_stat_grbyt_hi; 2407 u32 rx_stat_grund_lo; 2408 u32 rx_stat_grund_hi; 2409 u32 rx_stat_grfrg_lo; 2410 u32 rx_stat_grfrg_hi; 2411 u32 rx_stat_grerb_lo; 2412 u32 rx_stat_grerb_hi; 2413 u32 rx_stat_grfre_lo; 2414 u32 rx_stat_grfre_hi; 2415 u32 rx_stat_gripj_lo; 2416 u32 rx_stat_gripj_hi; 2417 }; 2418 2419 struct bmac2_stats { 2420 u32 tx_stat_gtpk_lo; /* gtpok */ 2421 u32 tx_stat_gtpk_hi; /* gtpok */ 2422 u32 tx_stat_gtxpf_lo; /* gtpf */ 2423 u32 tx_stat_gtxpf_hi; /* gtpf */ 2424 u32 tx_stat_gtpp_lo; /* NEW BMAC2 */ 2425 u32 tx_stat_gtpp_hi; /* NEW BMAC2 */ 2426 u32 tx_stat_gtfcs_lo; 2427 u32 tx_stat_gtfcs_hi; 2428 u32 tx_stat_gtuca_lo; /* NEW BMAC2 */ 2429 u32 tx_stat_gtuca_hi; /* NEW BMAC2 */ 2430 u32 tx_stat_gtmca_lo; 2431 u32 tx_stat_gtmca_hi; 2432 u32 tx_stat_gtbca_lo; 2433 u32 tx_stat_gtbca_hi; 2434 u32 tx_stat_gtovr_lo; 2435 u32 tx_stat_gtovr_hi; 2436 u32 tx_stat_gtfrg_lo; 2437 u32 tx_stat_gtfrg_hi; 2438 u32 tx_stat_gtpkt1_lo; /* gtpkt */ 2439 u32 tx_stat_gtpkt1_hi; /* gtpkt */ 2440 u32 tx_stat_gt64_lo; 2441 u32 tx_stat_gt64_hi; 2442 u32 tx_stat_gt127_lo; 2443 u32 tx_stat_gt127_hi; 2444 u32 tx_stat_gt255_lo; 2445 u32 tx_stat_gt255_hi; 2446 u32 tx_stat_gt511_lo; 2447 u32 tx_stat_gt511_hi; 2448 u32 tx_stat_gt1023_lo; 2449 u32 tx_stat_gt1023_hi; 2450 u32 tx_stat_gt1518_lo; 2451 u32 tx_stat_gt1518_hi; 2452 u32 tx_stat_gt2047_lo; 2453 u32 tx_stat_gt2047_hi; 2454 u32 tx_stat_gt4095_lo; 2455 u32 tx_stat_gt4095_hi; 2456 u32 tx_stat_gt9216_lo; 2457 u32 tx_stat_gt9216_hi; 2458 u32 tx_stat_gt16383_lo; 2459 u32 tx_stat_gt16383_hi; 2460 u32 tx_stat_gtmax_lo; 2461 u32 tx_stat_gtmax_hi; 2462 u32 tx_stat_gtufl_lo; 2463 u32 tx_stat_gtufl_hi; 2464 u32 tx_stat_gterr_lo; 2465 u32 tx_stat_gterr_hi; 2466 u32 tx_stat_gtbyt_lo; 2467 u32 tx_stat_gtbyt_hi; 2468 2469 u32 rx_stat_gr64_lo; 2470 u32 rx_stat_gr64_hi; 2471 u32 rx_stat_gr127_lo; 2472 u32 rx_stat_gr127_hi; 2473 u32 rx_stat_gr255_lo; 2474 u32 rx_stat_gr255_hi; 2475 u32 rx_stat_gr511_lo; 2476 u32 rx_stat_gr511_hi; 2477 u32 rx_stat_gr1023_lo; 2478 u32 rx_stat_gr1023_hi; 2479 u32 rx_stat_gr1518_lo; 2480 u32 rx_stat_gr1518_hi; 2481 u32 rx_stat_gr2047_lo; 2482 u32 rx_stat_gr2047_hi; 2483 u32 rx_stat_gr4095_lo; 2484 u32 rx_stat_gr4095_hi; 2485 u32 rx_stat_gr9216_lo; 2486 u32 rx_stat_gr9216_hi; 2487 u32 rx_stat_gr16383_lo; 2488 u32 rx_stat_gr16383_hi; 2489 u32 rx_stat_grmax_lo; 2490 u32 rx_stat_grmax_hi; 2491 u32 rx_stat_grpkt_lo; 2492 u32 rx_stat_grpkt_hi; 2493 u32 rx_stat_grfcs_lo; 2494 u32 rx_stat_grfcs_hi; 2495 u32 rx_stat_gruca_lo; 2496 u32 rx_stat_gruca_hi; 2497 u32 rx_stat_grmca_lo; 2498 u32 rx_stat_grmca_hi; 2499 u32 rx_stat_grbca_lo; 2500 u32 rx_stat_grbca_hi; 2501 u32 rx_stat_grxpf_lo; /* grpf */ 2502 u32 rx_stat_grxpf_hi; /* grpf */ 2503 u32 rx_stat_grpp_lo; 2504 u32 rx_stat_grpp_hi; 2505 u32 rx_stat_grxuo_lo; /* gruo */ 2506 u32 rx_stat_grxuo_hi; /* gruo */ 2507 u32 rx_stat_grjbr_lo; 2508 u32 rx_stat_grjbr_hi; 2509 u32 rx_stat_grovr_lo; 2510 u32 rx_stat_grovr_hi; 2511 u32 rx_stat_grxcf_lo; /* grcf */ 2512 u32 rx_stat_grxcf_hi; /* grcf */ 2513 u32 rx_stat_grflr_lo; 2514 u32 rx_stat_grflr_hi; 2515 u32 rx_stat_grpok_lo; 2516 u32 rx_stat_grpok_hi; 2517 u32 rx_stat_grmeg_lo; 2518 u32 rx_stat_grmeg_hi; 2519 u32 rx_stat_grmeb_lo; 2520 u32 rx_stat_grmeb_hi; 2521 u32 rx_stat_grbyt_lo; 2522 u32 rx_stat_grbyt_hi; 2523 u32 rx_stat_grund_lo; 2524 u32 rx_stat_grund_hi; 2525 u32 rx_stat_grfrg_lo; 2526 u32 rx_stat_grfrg_hi; 2527 u32 rx_stat_grerb_lo; /* grerrbyt */ 2528 u32 rx_stat_grerb_hi; /* grerrbyt */ 2529 u32 rx_stat_grfre_lo; /* grfrerr */ 2530 u32 rx_stat_grfre_hi; /* grfrerr */ 2531 u32 rx_stat_gripj_lo; 2532 u32 rx_stat_gripj_hi; 2533 }; 2534 2535 struct mstat_stats { 2536 struct { 2537 /* OTE MSTAT on E3 has a bug where this register's contents are 2538 * actually tx_gtxpok + tx_gtxpf + (possibly)tx_gtxpp 2539 */ 2540 u32 tx_gtxpok_lo; 2541 u32 tx_gtxpok_hi; 2542 u32 tx_gtxpf_lo; 2543 u32 tx_gtxpf_hi; 2544 u32 tx_gtxpp_lo; 2545 u32 tx_gtxpp_hi; 2546 u32 tx_gtfcs_lo; 2547 u32 tx_gtfcs_hi; 2548 u32 tx_gtuca_lo; 2549 u32 tx_gtuca_hi; 2550 u32 tx_gtmca_lo; 2551 u32 tx_gtmca_hi; 2552 u32 tx_gtgca_lo; 2553 u32 tx_gtgca_hi; 2554 u32 tx_gtpkt_lo; 2555 u32 tx_gtpkt_hi; 2556 u32 tx_gt64_lo; 2557 u32 tx_gt64_hi; 2558 u32 tx_gt127_lo; 2559 u32 tx_gt127_hi; 2560 u32 tx_gt255_lo; 2561 u32 tx_gt255_hi; 2562 u32 tx_gt511_lo; 2563 u32 tx_gt511_hi; 2564 u32 tx_gt1023_lo; 2565 u32 tx_gt1023_hi; 2566 u32 tx_gt1518_lo; 2567 u32 tx_gt1518_hi; 2568 u32 tx_gt2047_lo; 2569 u32 tx_gt2047_hi; 2570 u32 tx_gt4095_lo; 2571 u32 tx_gt4095_hi; 2572 u32 tx_gt9216_lo; 2573 u32 tx_gt9216_hi; 2574 u32 tx_gt16383_lo; 2575 u32 tx_gt16383_hi; 2576 u32 tx_gtufl_lo; 2577 u32 tx_gtufl_hi; 2578 u32 tx_gterr_lo; 2579 u32 tx_gterr_hi; 2580 u32 tx_gtbyt_lo; 2581 u32 tx_gtbyt_hi; 2582 u32 tx_collisions_lo; 2583 u32 tx_collisions_hi; 2584 u32 tx_singlecollision_lo; 2585 u32 tx_singlecollision_hi; 2586 u32 tx_multiplecollisions_lo; 2587 u32 tx_multiplecollisions_hi; 2588 u32 tx_deferred_lo; 2589 u32 tx_deferred_hi; 2590 u32 tx_excessivecollisions_lo; 2591 u32 tx_excessivecollisions_hi; 2592 u32 tx_latecollisions_lo; 2593 u32 tx_latecollisions_hi; 2594 } stats_tx; 2595 2596 struct { 2597 u32 rx_gr64_lo; 2598 u32 rx_gr64_hi; 2599 u32 rx_gr127_lo; 2600 u32 rx_gr127_hi; 2601 u32 rx_gr255_lo; 2602 u32 rx_gr255_hi; 2603 u32 rx_gr511_lo; 2604 u32 rx_gr511_hi; 2605 u32 rx_gr1023_lo; 2606 u32 rx_gr1023_hi; 2607 u32 rx_gr1518_lo; 2608 u32 rx_gr1518_hi; 2609 u32 rx_gr2047_lo; 2610 u32 rx_gr2047_hi; 2611 u32 rx_gr4095_lo; 2612 u32 rx_gr4095_hi; 2613 u32 rx_gr9216_lo; 2614 u32 rx_gr9216_hi; 2615 u32 rx_gr16383_lo; 2616 u32 rx_gr16383_hi; 2617 u32 rx_grpkt_lo; 2618 u32 rx_grpkt_hi; 2619 u32 rx_grfcs_lo; 2620 u32 rx_grfcs_hi; 2621 u32 rx_gruca_lo; 2622 u32 rx_gruca_hi; 2623 u32 rx_grmca_lo; 2624 u32 rx_grmca_hi; 2625 u32 rx_grbca_lo; 2626 u32 rx_grbca_hi; 2627 u32 rx_grxpf_lo; 2628 u32 rx_grxpf_hi; 2629 u32 rx_grxpp_lo; 2630 u32 rx_grxpp_hi; 2631 u32 rx_grxuo_lo; 2632 u32 rx_grxuo_hi; 2633 u32 rx_grovr_lo; 2634 u32 rx_grovr_hi; 2635 u32 rx_grxcf_lo; 2636 u32 rx_grxcf_hi; 2637 u32 rx_grflr_lo; 2638 u32 rx_grflr_hi; 2639 u32 rx_grpok_lo; 2640 u32 rx_grpok_hi; 2641 u32 rx_grbyt_lo; 2642 u32 rx_grbyt_hi; 2643 u32 rx_grund_lo; 2644 u32 rx_grund_hi; 2645 u32 rx_grfrg_lo; 2646 u32 rx_grfrg_hi; 2647 u32 rx_grerb_lo; 2648 u32 rx_grerb_hi; 2649 u32 rx_grfre_lo; 2650 u32 rx_grfre_hi; 2651 2652 u32 rx_alignmenterrors_lo; 2653 u32 rx_alignmenterrors_hi; 2654 u32 rx_falsecarrier_lo; 2655 u32 rx_falsecarrier_hi; 2656 u32 rx_llfcmsgcnt_lo; 2657 u32 rx_llfcmsgcnt_hi; 2658 } stats_rx; 2659 }; 2660 2661 union mac_stats { 2662 struct emac_stats emac_stats; 2663 struct bmac1_stats bmac1_stats; 2664 struct bmac2_stats bmac2_stats; 2665 struct mstat_stats mstat_stats; 2666 }; 2667 2668 2669 struct mac_stx { 2670 /* in_bad_octets */ 2671 u32 rx_stat_ifhcinbadoctets_hi; 2672 u32 rx_stat_ifhcinbadoctets_lo; 2673 2674 /* out_bad_octets */ 2675 u32 tx_stat_ifhcoutbadoctets_hi; 2676 u32 tx_stat_ifhcoutbadoctets_lo; 2677 2678 /* crc_receive_errors */ 2679 u32 rx_stat_dot3statsfcserrors_hi; 2680 u32 rx_stat_dot3statsfcserrors_lo; 2681 /* alignment_errors */ 2682 u32 rx_stat_dot3statsalignmenterrors_hi; 2683 u32 rx_stat_dot3statsalignmenterrors_lo; 2684 /* carrier_sense_errors */ 2685 u32 rx_stat_dot3statscarriersenseerrors_hi; 2686 u32 rx_stat_dot3statscarriersenseerrors_lo; 2687 /* false_carrier_detections */ 2688 u32 rx_stat_falsecarriererrors_hi; 2689 u32 rx_stat_falsecarriererrors_lo; 2690 2691 /* runt_packets_received */ 2692 u32 rx_stat_etherstatsundersizepkts_hi; 2693 u32 rx_stat_etherstatsundersizepkts_lo; 2694 /* jabber_packets_received */ 2695 u32 rx_stat_dot3statsframestoolong_hi; 2696 u32 rx_stat_dot3statsframestoolong_lo; 2697 2698 /* error_runt_packets_received */ 2699 u32 rx_stat_etherstatsfragments_hi; 2700 u32 rx_stat_etherstatsfragments_lo; 2701 /* error_jabber_packets_received */ 2702 u32 rx_stat_etherstatsjabbers_hi; 2703 u32 rx_stat_etherstatsjabbers_lo; 2704 2705 /* control_frames_received */ 2706 u32 rx_stat_maccontrolframesreceived_hi; 2707 u32 rx_stat_maccontrolframesreceived_lo; 2708 u32 rx_stat_mac_xpf_hi; 2709 u32 rx_stat_mac_xpf_lo; 2710 u32 rx_stat_mac_xcf_hi; 2711 u32 rx_stat_mac_xcf_lo; 2712 2713 /* xoff_state_entered */ 2714 u32 rx_stat_xoffstateentered_hi; 2715 u32 rx_stat_xoffstateentered_lo; 2716 /* pause_xon_frames_received */ 2717 u32 rx_stat_xonpauseframesreceived_hi; 2718 u32 rx_stat_xonpauseframesreceived_lo; 2719 /* pause_xoff_frames_received */ 2720 u32 rx_stat_xoffpauseframesreceived_hi; 2721 u32 rx_stat_xoffpauseframesreceived_lo; 2722 /* pause_xon_frames_transmitted */ 2723 u32 tx_stat_outxonsent_hi; 2724 u32 tx_stat_outxonsent_lo; 2725 /* pause_xoff_frames_transmitted */ 2726 u32 tx_stat_outxoffsent_hi; 2727 u32 tx_stat_outxoffsent_lo; 2728 /* flow_control_done */ 2729 u32 tx_stat_flowcontroldone_hi; 2730 u32 tx_stat_flowcontroldone_lo; 2731 2732 /* ether_stats_collisions */ 2733 u32 tx_stat_etherstatscollisions_hi; 2734 u32 tx_stat_etherstatscollisions_lo; 2735 /* single_collision_transmit_frames */ 2736 u32 tx_stat_dot3statssinglecollisionframes_hi; 2737 u32 tx_stat_dot3statssinglecollisionframes_lo; 2738 /* multiple_collision_transmit_frames */ 2739 u32 tx_stat_dot3statsmultiplecollisionframes_hi; 2740 u32 tx_stat_dot3statsmultiplecollisionframes_lo; 2741 /* deferred_transmissions */ 2742 u32 tx_stat_dot3statsdeferredtransmissions_hi; 2743 u32 tx_stat_dot3statsdeferredtransmissions_lo; 2744 /* excessive_collision_frames */ 2745 u32 tx_stat_dot3statsexcessivecollisions_hi; 2746 u32 tx_stat_dot3statsexcessivecollisions_lo; 2747 /* late_collision_frames */ 2748 u32 tx_stat_dot3statslatecollisions_hi; 2749 u32 tx_stat_dot3statslatecollisions_lo; 2750 2751 /* frames_transmitted_64_bytes */ 2752 u32 tx_stat_etherstatspkts64octets_hi; 2753 u32 tx_stat_etherstatspkts64octets_lo; 2754 /* frames_transmitted_65_127_bytes */ 2755 u32 tx_stat_etherstatspkts65octetsto127octets_hi; 2756 u32 tx_stat_etherstatspkts65octetsto127octets_lo; 2757 /* frames_transmitted_128_255_bytes */ 2758 u32 tx_stat_etherstatspkts128octetsto255octets_hi; 2759 u32 tx_stat_etherstatspkts128octetsto255octets_lo; 2760 /* frames_transmitted_256_511_bytes */ 2761 u32 tx_stat_etherstatspkts256octetsto511octets_hi; 2762 u32 tx_stat_etherstatspkts256octetsto511octets_lo; 2763 /* frames_transmitted_512_1023_bytes */ 2764 u32 tx_stat_etherstatspkts512octetsto1023octets_hi; 2765 u32 tx_stat_etherstatspkts512octetsto1023octets_lo; 2766 /* frames_transmitted_1024_1522_bytes */ 2767 u32 tx_stat_etherstatspkts1024octetsto1522octets_hi; 2768 u32 tx_stat_etherstatspkts1024octetsto1522octets_lo; 2769 /* frames_transmitted_1523_9022_bytes */ 2770 u32 tx_stat_etherstatspktsover1522octets_hi; 2771 u32 tx_stat_etherstatspktsover1522octets_lo; 2772 u32 tx_stat_mac_2047_hi; 2773 u32 tx_stat_mac_2047_lo; 2774 u32 tx_stat_mac_4095_hi; 2775 u32 tx_stat_mac_4095_lo; 2776 u32 tx_stat_mac_9216_hi; 2777 u32 tx_stat_mac_9216_lo; 2778 u32 tx_stat_mac_16383_hi; 2779 u32 tx_stat_mac_16383_lo; 2780 2781 /* internal_mac_transmit_errors */ 2782 u32 tx_stat_dot3statsinternalmactransmiterrors_hi; 2783 u32 tx_stat_dot3statsinternalmactransmiterrors_lo; 2784 2785 /* if_out_discards */ 2786 u32 tx_stat_mac_ufl_hi; 2787 u32 tx_stat_mac_ufl_lo; 2788 }; 2789 2790 2791 #define MAC_STX_IDX_MAX 2 2792 2793 struct host_port_stats { 2794 u32 host_port_stats_counter; 2795 2796 struct mac_stx mac_stx[MAC_STX_IDX_MAX]; 2797 2798 u32 brb_drop_hi; 2799 u32 brb_drop_lo; 2800 2801 u32 not_used; /* obsolete */ 2802 u32 pfc_frames_tx_hi; 2803 u32 pfc_frames_tx_lo; 2804 u32 pfc_frames_rx_hi; 2805 u32 pfc_frames_rx_lo; 2806 2807 u32 eee_lpi_count_hi; 2808 u32 eee_lpi_count_lo; 2809 }; 2810 2811 2812 struct host_func_stats { 2813 u32 host_func_stats_start; 2814 2815 u32 total_bytes_received_hi; 2816 u32 total_bytes_received_lo; 2817 2818 u32 total_bytes_transmitted_hi; 2819 u32 total_bytes_transmitted_lo; 2820 2821 u32 total_unicast_packets_received_hi; 2822 u32 total_unicast_packets_received_lo; 2823 2824 u32 total_multicast_packets_received_hi; 2825 u32 total_multicast_packets_received_lo; 2826 2827 u32 total_broadcast_packets_received_hi; 2828 u32 total_broadcast_packets_received_lo; 2829 2830 u32 total_unicast_packets_transmitted_hi; 2831 u32 total_unicast_packets_transmitted_lo; 2832 2833 u32 total_multicast_packets_transmitted_hi; 2834 u32 total_multicast_packets_transmitted_lo; 2835 2836 u32 total_broadcast_packets_transmitted_hi; 2837 u32 total_broadcast_packets_transmitted_lo; 2838 2839 u32 valid_bytes_received_hi; 2840 u32 valid_bytes_received_lo; 2841 2842 u32 host_func_stats_end; 2843 }; 2844 2845 /* VIC definitions */ 2846 #define VICSTATST_UIF_INDEX 2 2847 2848 2849 /* stats collected for afex. 2850 * NOTE: structure is exactly as expected to be received by the switch. 2851 * order must remain exactly as is unless protocol changes ! 2852 */ 2853 struct afex_stats { 2854 u32 tx_unicast_frames_hi; 2855 u32 tx_unicast_frames_lo; 2856 u32 tx_unicast_bytes_hi; 2857 u32 tx_unicast_bytes_lo; 2858 u32 tx_multicast_frames_hi; 2859 u32 tx_multicast_frames_lo; 2860 u32 tx_multicast_bytes_hi; 2861 u32 tx_multicast_bytes_lo; 2862 u32 tx_broadcast_frames_hi; 2863 u32 tx_broadcast_frames_lo; 2864 u32 tx_broadcast_bytes_hi; 2865 u32 tx_broadcast_bytes_lo; 2866 u32 tx_frames_discarded_hi; 2867 u32 tx_frames_discarded_lo; 2868 u32 tx_frames_dropped_hi; 2869 u32 tx_frames_dropped_lo; 2870 2871 u32 rx_unicast_frames_hi; 2872 u32 rx_unicast_frames_lo; 2873 u32 rx_unicast_bytes_hi; 2874 u32 rx_unicast_bytes_lo; 2875 u32 rx_multicast_frames_hi; 2876 u32 rx_multicast_frames_lo; 2877 u32 rx_multicast_bytes_hi; 2878 u32 rx_multicast_bytes_lo; 2879 u32 rx_broadcast_frames_hi; 2880 u32 rx_broadcast_frames_lo; 2881 u32 rx_broadcast_bytes_hi; 2882 u32 rx_broadcast_bytes_lo; 2883 u32 rx_frames_discarded_hi; 2884 u32 rx_frames_discarded_lo; 2885 u32 rx_frames_dropped_hi; 2886 u32 rx_frames_dropped_lo; 2887 }; 2888 2889 #define BCM_5710_FW_MAJOR_VERSION 7 2890 #define BCM_5710_FW_MINOR_VERSION 10 2891 #define BCM_5710_FW_REVISION_VERSION 51 2892 #define BCM_5710_FW_ENGINEERING_VERSION 0 2893 #define BCM_5710_FW_COMPILE_FLAGS 1 2894 2895 2896 /* 2897 * attention bits 2898 */ 2899 struct atten_sp_status_block { 2900 __le32 attn_bits; 2901 __le32 attn_bits_ack; 2902 u8 status_block_id; 2903 u8 reserved0; 2904 __le16 attn_bits_index; 2905 __le32 reserved1; 2906 }; 2907 2908 2909 /* 2910 * The eth aggregative context of Cstorm 2911 */ 2912 struct cstorm_eth_ag_context { 2913 u32 __reserved0[10]; 2914 }; 2915 2916 2917 /* 2918 * dmae command structure 2919 */ 2920 struct dmae_command { 2921 u32 opcode; 2922 #define DMAE_COMMAND_SRC (0x1<<0) 2923 #define DMAE_COMMAND_SRC_SHIFT 0 2924 #define DMAE_COMMAND_DST (0x3<<1) 2925 #define DMAE_COMMAND_DST_SHIFT 1 2926 #define DMAE_COMMAND_C_DST (0x1<<3) 2927 #define DMAE_COMMAND_C_DST_SHIFT 3 2928 #define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4) 2929 #define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4 2930 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5) 2931 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5 2932 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6) 2933 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6 2934 #define DMAE_COMMAND_ENDIANITY (0x3<<9) 2935 #define DMAE_COMMAND_ENDIANITY_SHIFT 9 2936 #define DMAE_COMMAND_PORT (0x1<<11) 2937 #define DMAE_COMMAND_PORT_SHIFT 11 2938 #define DMAE_COMMAND_CRC_RESET (0x1<<12) 2939 #define DMAE_COMMAND_CRC_RESET_SHIFT 12 2940 #define DMAE_COMMAND_SRC_RESET (0x1<<13) 2941 #define DMAE_COMMAND_SRC_RESET_SHIFT 13 2942 #define DMAE_COMMAND_DST_RESET (0x1<<14) 2943 #define DMAE_COMMAND_DST_RESET_SHIFT 14 2944 #define DMAE_COMMAND_E1HVN (0x3<<15) 2945 #define DMAE_COMMAND_E1HVN_SHIFT 15 2946 #define DMAE_COMMAND_DST_VN (0x3<<17) 2947 #define DMAE_COMMAND_DST_VN_SHIFT 17 2948 #define DMAE_COMMAND_C_FUNC (0x1<<19) 2949 #define DMAE_COMMAND_C_FUNC_SHIFT 19 2950 #define DMAE_COMMAND_ERR_POLICY (0x3<<20) 2951 #define DMAE_COMMAND_ERR_POLICY_SHIFT 20 2952 #define DMAE_COMMAND_RESERVED0 (0x3FF<<22) 2953 #define DMAE_COMMAND_RESERVED0_SHIFT 22 2954 u32 src_addr_lo; 2955 u32 src_addr_hi; 2956 u32 dst_addr_lo; 2957 u32 dst_addr_hi; 2958 #if defined(__BIG_ENDIAN) 2959 u16 opcode_iov; 2960 #define DMAE_COMMAND_SRC_VFID (0x3F<<0) 2961 #define DMAE_COMMAND_SRC_VFID_SHIFT 0 2962 #define DMAE_COMMAND_SRC_VFPF (0x1<<6) 2963 #define DMAE_COMMAND_SRC_VFPF_SHIFT 6 2964 #define DMAE_COMMAND_RESERVED1 (0x1<<7) 2965 #define DMAE_COMMAND_RESERVED1_SHIFT 7 2966 #define DMAE_COMMAND_DST_VFID (0x3F<<8) 2967 #define DMAE_COMMAND_DST_VFID_SHIFT 8 2968 #define DMAE_COMMAND_DST_VFPF (0x1<<14) 2969 #define DMAE_COMMAND_DST_VFPF_SHIFT 14 2970 #define DMAE_COMMAND_RESERVED2 (0x1<<15) 2971 #define DMAE_COMMAND_RESERVED2_SHIFT 15 2972 u16 len; 2973 #elif defined(__LITTLE_ENDIAN) 2974 u16 len; 2975 u16 opcode_iov; 2976 #define DMAE_COMMAND_SRC_VFID (0x3F<<0) 2977 #define DMAE_COMMAND_SRC_VFID_SHIFT 0 2978 #define DMAE_COMMAND_SRC_VFPF (0x1<<6) 2979 #define DMAE_COMMAND_SRC_VFPF_SHIFT 6 2980 #define DMAE_COMMAND_RESERVED1 (0x1<<7) 2981 #define DMAE_COMMAND_RESERVED1_SHIFT 7 2982 #define DMAE_COMMAND_DST_VFID (0x3F<<8) 2983 #define DMAE_COMMAND_DST_VFID_SHIFT 8 2984 #define DMAE_COMMAND_DST_VFPF (0x1<<14) 2985 #define DMAE_COMMAND_DST_VFPF_SHIFT 14 2986 #define DMAE_COMMAND_RESERVED2 (0x1<<15) 2987 #define DMAE_COMMAND_RESERVED2_SHIFT 15 2988 #endif 2989 u32 comp_addr_lo; 2990 u32 comp_addr_hi; 2991 u32 comp_val; 2992 u32 crc32; 2993 u32 crc32_c; 2994 #if defined(__BIG_ENDIAN) 2995 u16 crc16_c; 2996 u16 crc16; 2997 #elif defined(__LITTLE_ENDIAN) 2998 u16 crc16; 2999 u16 crc16_c; 3000 #endif 3001 #if defined(__BIG_ENDIAN) 3002 u16 reserved3; 3003 u16 crc_t10; 3004 #elif defined(__LITTLE_ENDIAN) 3005 u16 crc_t10; 3006 u16 reserved3; 3007 #endif 3008 #if defined(__BIG_ENDIAN) 3009 u16 xsum8; 3010 u16 xsum16; 3011 #elif defined(__LITTLE_ENDIAN) 3012 u16 xsum16; 3013 u16 xsum8; 3014 #endif 3015 }; 3016 3017 3018 /* 3019 * common data for all protocols 3020 */ 3021 struct doorbell_hdr { 3022 u8 header; 3023 #define DOORBELL_HDR_RX (0x1<<0) 3024 #define DOORBELL_HDR_RX_SHIFT 0 3025 #define DOORBELL_HDR_DB_TYPE (0x1<<1) 3026 #define DOORBELL_HDR_DB_TYPE_SHIFT 1 3027 #define DOORBELL_HDR_DPM_SIZE (0x3<<2) 3028 #define DOORBELL_HDR_DPM_SIZE_SHIFT 2 3029 #define DOORBELL_HDR_CONN_TYPE (0xF<<4) 3030 #define DOORBELL_HDR_CONN_TYPE_SHIFT 4 3031 }; 3032 3033 /* 3034 * Ethernet doorbell 3035 */ 3036 struct eth_tx_doorbell { 3037 #if defined(__BIG_ENDIAN) 3038 u16 npackets; 3039 u8 params; 3040 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) 3041 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0 3042 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) 3043 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6 3044 #define ETH_TX_DOORBELL_SPARE (0x1<<7) 3045 #define ETH_TX_DOORBELL_SPARE_SHIFT 7 3046 struct doorbell_hdr hdr; 3047 #elif defined(__LITTLE_ENDIAN) 3048 struct doorbell_hdr hdr; 3049 u8 params; 3050 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) 3051 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0 3052 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) 3053 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6 3054 #define ETH_TX_DOORBELL_SPARE (0x1<<7) 3055 #define ETH_TX_DOORBELL_SPARE_SHIFT 7 3056 u16 npackets; 3057 #endif 3058 }; 3059 3060 3061 /* 3062 * 3 lines. status block 3063 */ 3064 struct hc_status_block_e1x { 3065 __le16 index_values[HC_SB_MAX_INDICES_E1X]; 3066 __le16 running_index[HC_SB_MAX_SM]; 3067 __le32 rsrv[11]; 3068 }; 3069 3070 /* 3071 * host status block 3072 */ 3073 struct host_hc_status_block_e1x { 3074 struct hc_status_block_e1x sb; 3075 }; 3076 3077 3078 /* 3079 * 3 lines. status block 3080 */ 3081 struct hc_status_block_e2 { 3082 __le16 index_values[HC_SB_MAX_INDICES_E2]; 3083 __le16 running_index[HC_SB_MAX_SM]; 3084 __le32 reserved[11]; 3085 }; 3086 3087 /* 3088 * host status block 3089 */ 3090 struct host_hc_status_block_e2 { 3091 struct hc_status_block_e2 sb; 3092 }; 3093 3094 3095 /* 3096 * 5 lines. slow-path status block 3097 */ 3098 struct hc_sp_status_block { 3099 __le16 index_values[HC_SP_SB_MAX_INDICES]; 3100 __le16 running_index; 3101 __le16 rsrv; 3102 u32 rsrv1; 3103 }; 3104 3105 /* 3106 * host status block 3107 */ 3108 struct host_sp_status_block { 3109 struct atten_sp_status_block atten_status_block; 3110 struct hc_sp_status_block sp_sb; 3111 }; 3112 3113 3114 /* 3115 * IGU driver acknowledgment register 3116 */ 3117 struct igu_ack_register { 3118 #if defined(__BIG_ENDIAN) 3119 u16 sb_id_and_flags; 3120 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) 3121 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0 3122 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5) 3123 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5 3124 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) 3125 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8 3126 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) 3127 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9 3128 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11) 3129 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11 3130 u16 status_block_index; 3131 #elif defined(__LITTLE_ENDIAN) 3132 u16 status_block_index; 3133 u16 sb_id_and_flags; 3134 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) 3135 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0 3136 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5) 3137 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5 3138 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) 3139 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8 3140 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) 3141 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9 3142 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11) 3143 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11 3144 #endif 3145 }; 3146 3147 3148 /* 3149 * IGU driver acknowledgement register 3150 */ 3151 struct igu_backward_compatible { 3152 u32 sb_id_and_flags; 3153 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0) 3154 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0 3155 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16) 3156 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16 3157 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21) 3158 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21 3159 #define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24) 3160 #define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24 3161 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25) 3162 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25 3163 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27) 3164 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27 3165 u32 reserved_2; 3166 }; 3167 3168 3169 /* 3170 * IGU driver acknowledgement register 3171 */ 3172 struct igu_regular { 3173 u32 sb_id_and_flags; 3174 #define IGU_REGULAR_SB_INDEX (0xFFFFF<<0) 3175 #define IGU_REGULAR_SB_INDEX_SHIFT 0 3176 #define IGU_REGULAR_RESERVED0 (0x1<<20) 3177 #define IGU_REGULAR_RESERVED0_SHIFT 20 3178 #define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21) 3179 #define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21 3180 #define IGU_REGULAR_BUPDATE (0x1<<24) 3181 #define IGU_REGULAR_BUPDATE_SHIFT 24 3182 #define IGU_REGULAR_ENABLE_INT (0x3<<25) 3183 #define IGU_REGULAR_ENABLE_INT_SHIFT 25 3184 #define IGU_REGULAR_RESERVED_1 (0x1<<27) 3185 #define IGU_REGULAR_RESERVED_1_SHIFT 27 3186 #define IGU_REGULAR_CLEANUP_TYPE (0x3<<28) 3187 #define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28 3188 #define IGU_REGULAR_CLEANUP_SET (0x1<<30) 3189 #define IGU_REGULAR_CLEANUP_SET_SHIFT 30 3190 #define IGU_REGULAR_BCLEANUP (0x1<<31) 3191 #define IGU_REGULAR_BCLEANUP_SHIFT 31 3192 u32 reserved_2; 3193 }; 3194 3195 /* 3196 * IGU driver acknowledgement register 3197 */ 3198 union igu_consprod_reg { 3199 struct igu_regular regular; 3200 struct igu_backward_compatible backward_compatible; 3201 }; 3202 3203 3204 /* 3205 * Igu control commands 3206 */ 3207 enum igu_ctrl_cmd { 3208 IGU_CTRL_CMD_TYPE_RD, 3209 IGU_CTRL_CMD_TYPE_WR, 3210 MAX_IGU_CTRL_CMD 3211 }; 3212 3213 3214 /* 3215 * Control register for the IGU command register 3216 */ 3217 struct igu_ctrl_reg { 3218 u32 ctrl_data; 3219 #define IGU_CTRL_REG_ADDRESS (0xFFF<<0) 3220 #define IGU_CTRL_REG_ADDRESS_SHIFT 0 3221 #define IGU_CTRL_REG_FID (0x7F<<12) 3222 #define IGU_CTRL_REG_FID_SHIFT 12 3223 #define IGU_CTRL_REG_RESERVED (0x1<<19) 3224 #define IGU_CTRL_REG_RESERVED_SHIFT 19 3225 #define IGU_CTRL_REG_TYPE (0x1<<20) 3226 #define IGU_CTRL_REG_TYPE_SHIFT 20 3227 #define IGU_CTRL_REG_UNUSED (0x7FF<<21) 3228 #define IGU_CTRL_REG_UNUSED_SHIFT 21 3229 }; 3230 3231 3232 /* 3233 * Igu interrupt command 3234 */ 3235 enum igu_int_cmd { 3236 IGU_INT_ENABLE, 3237 IGU_INT_DISABLE, 3238 IGU_INT_NOP, 3239 IGU_INT_NOP2, 3240 MAX_IGU_INT_CMD 3241 }; 3242 3243 3244 /* 3245 * Igu segments 3246 */ 3247 enum igu_seg_access { 3248 IGU_SEG_ACCESS_NORM, 3249 IGU_SEG_ACCESS_DEF, 3250 IGU_SEG_ACCESS_ATTN, 3251 MAX_IGU_SEG_ACCESS 3252 }; 3253 3254 3255 /* 3256 * Parser parsing flags field 3257 */ 3258 struct parsing_flags { 3259 __le16 flags; 3260 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0) 3261 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0 3262 #define PARSING_FLAGS_VLAN (0x1<<1) 3263 #define PARSING_FLAGS_VLAN_SHIFT 1 3264 #define PARSING_FLAGS_EXTRA_VLAN (0x1<<2) 3265 #define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2 3266 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3) 3267 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3 3268 #define PARSING_FLAGS_IP_OPTIONS (0x1<<5) 3269 #define PARSING_FLAGS_IP_OPTIONS_SHIFT 5 3270 #define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6) 3271 #define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6 3272 #define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7) 3273 #define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7 3274 #define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9) 3275 #define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9 3276 #define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10) 3277 #define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10 3278 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11) 3279 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11 3280 #define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12) 3281 #define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12 3282 #define PARSING_FLAGS_LLC_SNAP (0x1<<13) 3283 #define PARSING_FLAGS_LLC_SNAP_SHIFT 13 3284 #define PARSING_FLAGS_RESERVED0 (0x3<<14) 3285 #define PARSING_FLAGS_RESERVED0_SHIFT 14 3286 }; 3287 3288 3289 /* 3290 * Parsing flags for TCP ACK type 3291 */ 3292 enum prs_flags_ack_type { 3293 PRS_FLAG_PUREACK_PIGGY, 3294 PRS_FLAG_PUREACK_PURE, 3295 MAX_PRS_FLAGS_ACK_TYPE 3296 }; 3297 3298 3299 /* 3300 * Parsing flags for Ethernet address type 3301 */ 3302 enum prs_flags_eth_addr_type { 3303 PRS_FLAG_ETHTYPE_NON_UNICAST, 3304 PRS_FLAG_ETHTYPE_UNICAST, 3305 MAX_PRS_FLAGS_ETH_ADDR_TYPE 3306 }; 3307 3308 3309 /* 3310 * Parsing flags for over-ethernet protocol 3311 */ 3312 enum prs_flags_over_eth { 3313 PRS_FLAG_OVERETH_UNKNOWN, 3314 PRS_FLAG_OVERETH_IPV4, 3315 PRS_FLAG_OVERETH_IPV6, 3316 PRS_FLAG_OVERETH_LLCSNAP_UNKNOWN, 3317 MAX_PRS_FLAGS_OVER_ETH 3318 }; 3319 3320 3321 /* 3322 * Parsing flags for over-IP protocol 3323 */ 3324 enum prs_flags_over_ip { 3325 PRS_FLAG_OVERIP_UNKNOWN, 3326 PRS_FLAG_OVERIP_TCP, 3327 PRS_FLAG_OVERIP_UDP, 3328 MAX_PRS_FLAGS_OVER_IP 3329 }; 3330 3331 3332 /* 3333 * SDM operation gen command (generate aggregative interrupt) 3334 */ 3335 struct sdm_op_gen { 3336 __le32 command; 3337 #define SDM_OP_GEN_COMP_PARAM (0x1F<<0) 3338 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0 3339 #define SDM_OP_GEN_COMP_TYPE (0x7<<5) 3340 #define SDM_OP_GEN_COMP_TYPE_SHIFT 5 3341 #define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8) 3342 #define SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8 3343 #define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16) 3344 #define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16 3345 #define SDM_OP_GEN_RESERVED (0x7FFF<<17) 3346 #define SDM_OP_GEN_RESERVED_SHIFT 17 3347 }; 3348 3349 3350 /* 3351 * Timers connection context 3352 */ 3353 struct timers_block_context { 3354 u32 __reserved_0; 3355 u32 __reserved_1; 3356 u32 __reserved_2; 3357 u32 flags; 3358 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0) 3359 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0 3360 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2) 3361 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2 3362 #define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3) 3363 #define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3 3364 }; 3365 3366 3367 /* 3368 * The eth aggregative context of Tstorm 3369 */ 3370 struct tstorm_eth_ag_context { 3371 u32 __reserved0[14]; 3372 }; 3373 3374 3375 /* 3376 * The eth aggregative context of Ustorm 3377 */ 3378 struct ustorm_eth_ag_context { 3379 u32 __reserved0; 3380 #if defined(__BIG_ENDIAN) 3381 u8 cdu_usage; 3382 u8 __reserved2; 3383 u16 __reserved1; 3384 #elif defined(__LITTLE_ENDIAN) 3385 u16 __reserved1; 3386 u8 __reserved2; 3387 u8 cdu_usage; 3388 #endif 3389 u32 __reserved3[6]; 3390 }; 3391 3392 3393 /* 3394 * The eth aggregative context of Xstorm 3395 */ 3396 struct xstorm_eth_ag_context { 3397 u32 reserved0; 3398 #if defined(__BIG_ENDIAN) 3399 u8 cdu_reserved; 3400 u8 reserved2; 3401 u16 reserved1; 3402 #elif defined(__LITTLE_ENDIAN) 3403 u16 reserved1; 3404 u8 reserved2; 3405 u8 cdu_reserved; 3406 #endif 3407 u32 reserved3[30]; 3408 }; 3409 3410 3411 /* 3412 * doorbell message sent to the chip 3413 */ 3414 struct doorbell { 3415 #if defined(__BIG_ENDIAN) 3416 u16 zero_fill2; 3417 u8 zero_fill1; 3418 struct doorbell_hdr header; 3419 #elif defined(__LITTLE_ENDIAN) 3420 struct doorbell_hdr header; 3421 u8 zero_fill1; 3422 u16 zero_fill2; 3423 #endif 3424 }; 3425 3426 3427 /* 3428 * doorbell message sent to the chip 3429 */ 3430 struct doorbell_set_prod { 3431 #if defined(__BIG_ENDIAN) 3432 u16 prod; 3433 u8 zero_fill1; 3434 struct doorbell_hdr header; 3435 #elif defined(__LITTLE_ENDIAN) 3436 struct doorbell_hdr header; 3437 u8 zero_fill1; 3438 u16 prod; 3439 #endif 3440 }; 3441 3442 3443 struct regpair { 3444 __le32 lo; 3445 __le32 hi; 3446 }; 3447 3448 struct regpair_native { 3449 u32 lo; 3450 u32 hi; 3451 }; 3452 3453 /* 3454 * Classify rule opcodes in E2/E3 3455 */ 3456 enum classify_rule { 3457 CLASSIFY_RULE_OPCODE_MAC, 3458 CLASSIFY_RULE_OPCODE_VLAN, 3459 CLASSIFY_RULE_OPCODE_PAIR, 3460 CLASSIFY_RULE_OPCODE_VXLAN, 3461 MAX_CLASSIFY_RULE 3462 }; 3463 3464 3465 /* 3466 * Classify rule types in E2/E3 3467 */ 3468 enum classify_rule_action_type { 3469 CLASSIFY_RULE_REMOVE, 3470 CLASSIFY_RULE_ADD, 3471 MAX_CLASSIFY_RULE_ACTION_TYPE 3472 }; 3473 3474 3475 /* 3476 * client init ramrod data 3477 */ 3478 struct client_init_general_data { 3479 u8 client_id; 3480 u8 statistics_counter_id; 3481 u8 statistics_en_flg; 3482 u8 is_fcoe_flg; 3483 u8 activate_flg; 3484 u8 sp_client_id; 3485 __le16 mtu; 3486 u8 statistics_zero_flg; 3487 u8 func_id; 3488 u8 cos; 3489 u8 traffic_type; 3490 u8 fp_hsi_ver; 3491 u8 reserved0[3]; 3492 }; 3493 3494 3495 /* 3496 * client init rx data 3497 */ 3498 struct client_init_rx_data { 3499 u8 tpa_en; 3500 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1<<0) 3501 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4_SHIFT 0 3502 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1<<1) 3503 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6_SHIFT 1 3504 #define CLIENT_INIT_RX_DATA_TPA_MODE (0x1<<2) 3505 #define CLIENT_INIT_RX_DATA_TPA_MODE_SHIFT 2 3506 #define CLIENT_INIT_RX_DATA_RESERVED5 (0x1F<<3) 3507 #define CLIENT_INIT_RX_DATA_RESERVED5_SHIFT 3 3508 u8 vmqueue_mode_en_flg; 3509 u8 extra_data_over_sgl_en_flg; 3510 u8 cache_line_alignment_log_size; 3511 u8 enable_dynamic_hc; 3512 u8 max_sges_for_packet; 3513 u8 client_qzone_id; 3514 u8 drop_ip_cs_err_flg; 3515 u8 drop_tcp_cs_err_flg; 3516 u8 drop_ttl0_flg; 3517 u8 drop_udp_cs_err_flg; 3518 u8 inner_vlan_removal_enable_flg; 3519 u8 outer_vlan_removal_enable_flg; 3520 u8 status_block_id; 3521 u8 rx_sb_index_number; 3522 u8 dont_verify_rings_pause_thr_flg; 3523 u8 max_tpa_queues; 3524 u8 silent_vlan_removal_flg; 3525 __le16 max_bytes_on_bd; 3526 __le16 sge_buff_size; 3527 u8 approx_mcast_engine_id; 3528 u8 rss_engine_id; 3529 struct regpair bd_page_base; 3530 struct regpair sge_page_base; 3531 struct regpair cqe_page_base; 3532 u8 is_leading_rss; 3533 u8 is_approx_mcast; 3534 __le16 max_agg_size; 3535 __le16 state; 3536 #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1<<0) 3537 #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL_SHIFT 0 3538 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1<<1) 3539 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL_SHIFT 1 3540 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1<<2) 3541 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED_SHIFT 2 3542 #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1<<3) 3543 #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL_SHIFT 3 3544 #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1<<4) 3545 #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL_SHIFT 4 3546 #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1<<5) 3547 #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL_SHIFT 5 3548 #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1<<6) 3549 #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN_SHIFT 6 3550 #define CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF<<7) 3551 #define CLIENT_INIT_RX_DATA_RESERVED2_SHIFT 7 3552 __le16 cqe_pause_thr_low; 3553 __le16 cqe_pause_thr_high; 3554 __le16 bd_pause_thr_low; 3555 __le16 bd_pause_thr_high; 3556 __le16 sge_pause_thr_low; 3557 __le16 sge_pause_thr_high; 3558 __le16 rx_cos_mask; 3559 __le16 silent_vlan_value; 3560 __le16 silent_vlan_mask; 3561 u8 handle_ptp_pkts_flg; 3562 u8 reserved6[3]; 3563 __le32 reserved7; 3564 }; 3565 3566 /* 3567 * client init tx data 3568 */ 3569 struct client_init_tx_data { 3570 u8 enforce_security_flg; 3571 u8 tx_status_block_id; 3572 u8 tx_sb_index_number; 3573 u8 tss_leading_client_id; 3574 u8 tx_switching_flg; 3575 u8 anti_spoofing_flg; 3576 __le16 default_vlan; 3577 struct regpair tx_bd_page_base; 3578 __le16 state; 3579 #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1<<0) 3580 #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL_SHIFT 0 3581 #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1<<1) 3582 #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL_SHIFT 1 3583 #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1<<2) 3584 #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL_SHIFT 2 3585 #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1<<3) 3586 #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN_SHIFT 3 3587 #define CLIENT_INIT_TX_DATA_RESERVED0 (0xFFF<<4) 3588 #define CLIENT_INIT_TX_DATA_RESERVED0_SHIFT 4 3589 u8 default_vlan_flg; 3590 u8 force_default_pri_flg; 3591 u8 tunnel_lso_inc_ip_id; 3592 u8 refuse_outband_vlan_flg; 3593 u8 tunnel_non_lso_pcsum_location; 3594 u8 tunnel_non_lso_outer_ip_csum_location; 3595 }; 3596 3597 /* 3598 * client init ramrod data 3599 */ 3600 struct client_init_ramrod_data { 3601 struct client_init_general_data general; 3602 struct client_init_rx_data rx; 3603 struct client_init_tx_data tx; 3604 }; 3605 3606 3607 /* 3608 * client update ramrod data 3609 */ 3610 struct client_update_ramrod_data { 3611 u8 client_id; 3612 u8 func_id; 3613 u8 inner_vlan_removal_enable_flg; 3614 u8 inner_vlan_removal_change_flg; 3615 u8 outer_vlan_removal_enable_flg; 3616 u8 outer_vlan_removal_change_flg; 3617 u8 anti_spoofing_enable_flg; 3618 u8 anti_spoofing_change_flg; 3619 u8 activate_flg; 3620 u8 activate_change_flg; 3621 __le16 default_vlan; 3622 u8 default_vlan_enable_flg; 3623 u8 default_vlan_change_flg; 3624 __le16 silent_vlan_value; 3625 __le16 silent_vlan_mask; 3626 u8 silent_vlan_removal_flg; 3627 u8 silent_vlan_change_flg; 3628 u8 refuse_outband_vlan_flg; 3629 u8 refuse_outband_vlan_change_flg; 3630 u8 tx_switching_flg; 3631 u8 tx_switching_change_flg; 3632 u8 handle_ptp_pkts_flg; 3633 u8 handle_ptp_pkts_change_flg; 3634 __le16 reserved1; 3635 __le32 echo; 3636 }; 3637 3638 3639 /* 3640 * The eth storm context of Cstorm 3641 */ 3642 struct cstorm_eth_st_context { 3643 u32 __reserved0[4]; 3644 }; 3645 3646 3647 struct double_regpair { 3648 u32 regpair0_lo; 3649 u32 regpair0_hi; 3650 u32 regpair1_lo; 3651 u32 regpair1_hi; 3652 }; 3653 3654 /* 2nd parse bd type used in ethernet tx BDs */ 3655 enum eth_2nd_parse_bd_type { 3656 ETH_2ND_PARSE_BD_TYPE_LSO_TUNNEL, 3657 MAX_ETH_2ND_PARSE_BD_TYPE 3658 }; 3659 3660 /* 3661 * Ethernet address typesm used in ethernet tx BDs 3662 */ 3663 enum eth_addr_type { 3664 UNKNOWN_ADDRESS, 3665 UNICAST_ADDRESS, 3666 MULTICAST_ADDRESS, 3667 BROADCAST_ADDRESS, 3668 MAX_ETH_ADDR_TYPE 3669 }; 3670 3671 3672 /* 3673 * 3674 */ 3675 struct eth_classify_cmd_header { 3676 u8 cmd_general_data; 3677 #define ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1<<0) 3678 #define ETH_CLASSIFY_CMD_HEADER_RX_CMD_SHIFT 0 3679 #define ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1<<1) 3680 #define ETH_CLASSIFY_CMD_HEADER_TX_CMD_SHIFT 1 3681 #define ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3<<2) 3682 #define ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT 2 3683 #define ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1<<4) 3684 #define ETH_CLASSIFY_CMD_HEADER_IS_ADD_SHIFT 4 3685 #define ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7<<5) 3686 #define ETH_CLASSIFY_CMD_HEADER_RESERVED0_SHIFT 5 3687 u8 func_id; 3688 u8 client_id; 3689 u8 reserved1; 3690 }; 3691 3692 3693 /* 3694 * header for eth classification config ramrod 3695 */ 3696 struct eth_classify_header { 3697 u8 rule_cnt; 3698 u8 reserved0; 3699 __le16 reserved1; 3700 __le32 echo; 3701 }; 3702 3703 3704 /* 3705 * Command for adding/removing a MAC classification rule 3706 */ 3707 struct eth_classify_mac_cmd { 3708 struct eth_classify_cmd_header header; 3709 __le16 reserved0; 3710 __le16 inner_mac; 3711 __le16 mac_lsb; 3712 __le16 mac_mid; 3713 __le16 mac_msb; 3714 __le16 reserved1; 3715 }; 3716 3717 3718 /* 3719 * Command for adding/removing a MAC-VLAN pair classification rule 3720 */ 3721 struct eth_classify_pair_cmd { 3722 struct eth_classify_cmd_header header; 3723 __le16 reserved0; 3724 __le16 inner_mac; 3725 __le16 mac_lsb; 3726 __le16 mac_mid; 3727 __le16 mac_msb; 3728 __le16 vlan; 3729 }; 3730 3731 3732 /* 3733 * Command for adding/removing a VLAN classification rule 3734 */ 3735 struct eth_classify_vlan_cmd { 3736 struct eth_classify_cmd_header header; 3737 __le32 reserved0; 3738 __le32 reserved1; 3739 __le16 reserved2; 3740 __le16 vlan; 3741 }; 3742 3743 /* 3744 * Command for adding/removing a VXLAN classification rule 3745 */ 3746 struct eth_classify_vxlan_cmd { 3747 struct eth_classify_cmd_header header; 3748 __le32 vni; 3749 __le16 inner_mac_lsb; 3750 __le16 inner_mac_mid; 3751 __le16 inner_mac_msb; 3752 __le16 reserved1; 3753 }; 3754 3755 /* 3756 * union for eth classification rule 3757 */ 3758 union eth_classify_rule_cmd { 3759 struct eth_classify_mac_cmd mac; 3760 struct eth_classify_vlan_cmd vlan; 3761 struct eth_classify_pair_cmd pair; 3762 struct eth_classify_vxlan_cmd vxlan; 3763 }; 3764 3765 /* 3766 * parameters for eth classification configuration ramrod 3767 */ 3768 struct eth_classify_rules_ramrod_data { 3769 struct eth_classify_header header; 3770 union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT]; 3771 }; 3772 3773 3774 /* 3775 * The data contain client ID need to the ramrod 3776 */ 3777 struct eth_common_ramrod_data { 3778 __le32 client_id; 3779 __le32 reserved1; 3780 }; 3781 3782 3783 /* 3784 * The eth storm context of Ustorm 3785 */ 3786 struct ustorm_eth_st_context { 3787 u32 reserved0[52]; 3788 }; 3789 3790 /* 3791 * The eth storm context of Tstorm 3792 */ 3793 struct tstorm_eth_st_context { 3794 u32 __reserved0[28]; 3795 }; 3796 3797 /* 3798 * The eth storm context of Xstorm 3799 */ 3800 struct xstorm_eth_st_context { 3801 u32 reserved0[60]; 3802 }; 3803 3804 /* 3805 * Ethernet connection context 3806 */ 3807 struct eth_context { 3808 struct ustorm_eth_st_context ustorm_st_context; 3809 struct tstorm_eth_st_context tstorm_st_context; 3810 struct xstorm_eth_ag_context xstorm_ag_context; 3811 struct tstorm_eth_ag_context tstorm_ag_context; 3812 struct cstorm_eth_ag_context cstorm_ag_context; 3813 struct ustorm_eth_ag_context ustorm_ag_context; 3814 struct timers_block_context timers_context; 3815 struct xstorm_eth_st_context xstorm_st_context; 3816 struct cstorm_eth_st_context cstorm_st_context; 3817 }; 3818 3819 3820 /* 3821 * union for sgl and raw data. 3822 */ 3823 union eth_sgl_or_raw_data { 3824 __le16 sgl[8]; 3825 u32 raw_data[4]; 3826 }; 3827 3828 /* 3829 * eth FP end aggregation CQE parameters struct 3830 */ 3831 struct eth_end_agg_rx_cqe { 3832 u8 type_error_flags; 3833 #define ETH_END_AGG_RX_CQE_TYPE (0x3<<0) 3834 #define ETH_END_AGG_RX_CQE_TYPE_SHIFT 0 3835 #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1<<2) 3836 #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL_SHIFT 2 3837 #define ETH_END_AGG_RX_CQE_RESERVED0 (0x1F<<3) 3838 #define ETH_END_AGG_RX_CQE_RESERVED0_SHIFT 3 3839 u8 reserved1; 3840 u8 queue_index; 3841 u8 reserved2; 3842 __le32 timestamp_delta; 3843 __le16 num_of_coalesced_segs; 3844 __le16 pkt_len; 3845 u8 pure_ack_count; 3846 u8 reserved3; 3847 __le16 reserved4; 3848 union eth_sgl_or_raw_data sgl_or_raw_data; 3849 __le32 reserved5[8]; 3850 }; 3851 3852 3853 /* 3854 * regular eth FP CQE parameters struct 3855 */ 3856 struct eth_fast_path_rx_cqe { 3857 u8 type_error_flags; 3858 #define ETH_FAST_PATH_RX_CQE_TYPE (0x3<<0) 3859 #define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0 3860 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1<<2) 3861 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 2 3862 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<3) 3863 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 3 3864 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<4) 3865 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 4 3866 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<5) 3867 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 5 3868 #define ETH_FAST_PATH_RX_CQE_PTP_PKT (0x1<<6) 3869 #define ETH_FAST_PATH_RX_CQE_PTP_PKT_SHIFT 6 3870 #define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x1<<7) 3871 #define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 7 3872 u8 status_flags; 3873 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0) 3874 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0 3875 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3) 3876 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3 3877 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4) 3878 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4 3879 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5) 3880 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5 3881 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6) 3882 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6 3883 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7) 3884 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7 3885 u8 queue_index; 3886 u8 placement_offset; 3887 __le32 rss_hash_result; 3888 __le16 vlan_tag; 3889 __le16 pkt_len_or_gro_seg_len; 3890 __le16 len_on_bd; 3891 struct parsing_flags pars_flags; 3892 union eth_sgl_or_raw_data sgl_or_raw_data; 3893 __le32 reserved1[7]; 3894 u32 marker; 3895 }; 3896 3897 3898 /* 3899 * Command for setting classification flags for a client 3900 */ 3901 struct eth_filter_rules_cmd { 3902 u8 cmd_general_data; 3903 #define ETH_FILTER_RULES_CMD_RX_CMD (0x1<<0) 3904 #define ETH_FILTER_RULES_CMD_RX_CMD_SHIFT 0 3905 #define ETH_FILTER_RULES_CMD_TX_CMD (0x1<<1) 3906 #define ETH_FILTER_RULES_CMD_TX_CMD_SHIFT 1 3907 #define ETH_FILTER_RULES_CMD_RESERVED0 (0x3F<<2) 3908 #define ETH_FILTER_RULES_CMD_RESERVED0_SHIFT 2 3909 u8 func_id; 3910 u8 client_id; 3911 u8 reserved1; 3912 __le16 state; 3913 #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1<<0) 3914 #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL_SHIFT 0 3915 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1<<1) 3916 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL_SHIFT 1 3917 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1<<2) 3918 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED_SHIFT 2 3919 #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1<<3) 3920 #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL_SHIFT 3 3921 #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1<<4) 3922 #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL_SHIFT 4 3923 #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1<<5) 3924 #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL_SHIFT 5 3925 #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1<<6) 3926 #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN_SHIFT 6 3927 #define ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF<<7) 3928 #define ETH_FILTER_RULES_CMD_RESERVED2_SHIFT 7 3929 __le16 reserved3; 3930 struct regpair reserved4; 3931 }; 3932 3933 3934 /* 3935 * parameters for eth classification filters ramrod 3936 */ 3937 struct eth_filter_rules_ramrod_data { 3938 struct eth_classify_header header; 3939 struct eth_filter_rules_cmd rules[FILTER_RULES_COUNT]; 3940 }; 3941 3942 /* Hsi version */ 3943 enum eth_fp_hsi_ver { 3944 ETH_FP_HSI_VER_0, 3945 ETH_FP_HSI_VER_1, 3946 ETH_FP_HSI_VER_2, 3947 MAX_ETH_FP_HSI_VER 3948 }; 3949 3950 /* 3951 * parameters for eth classification configuration ramrod 3952 */ 3953 struct eth_general_rules_ramrod_data { 3954 struct eth_classify_header header; 3955 union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT]; 3956 }; 3957 3958 3959 /* 3960 * The data for Halt ramrod 3961 */ 3962 struct eth_halt_ramrod_data { 3963 __le32 client_id; 3964 __le32 reserved0; 3965 }; 3966 3967 3968 /* 3969 * destination and source mac address. 3970 */ 3971 struct eth_mac_addresses { 3972 #if defined(__BIG_ENDIAN) 3973 __le16 dst_mid; 3974 __le16 dst_lo; 3975 #elif defined(__LITTLE_ENDIAN) 3976 __le16 dst_lo; 3977 __le16 dst_mid; 3978 #endif 3979 #if defined(__BIG_ENDIAN) 3980 __le16 src_lo; 3981 __le16 dst_hi; 3982 #elif defined(__LITTLE_ENDIAN) 3983 __le16 dst_hi; 3984 __le16 src_lo; 3985 #endif 3986 #if defined(__BIG_ENDIAN) 3987 __le16 src_hi; 3988 __le16 src_mid; 3989 #elif defined(__LITTLE_ENDIAN) 3990 __le16 src_mid; 3991 __le16 src_hi; 3992 #endif 3993 }; 3994 3995 /* tunneling related data */ 3996 struct eth_tunnel_data { 3997 __le16 dst_lo; 3998 __le16 dst_mid; 3999 __le16 dst_hi; 4000 __le16 fw_ip_hdr_csum; 4001 __le16 pseudo_csum; 4002 u8 ip_hdr_start_inner_w; 4003 u8 flags; 4004 #define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER (0x1<<0) 4005 #define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER_SHIFT 0 4006 #define ETH_TUNNEL_DATA_RESERVED (0x7F<<1) 4007 #define ETH_TUNNEL_DATA_RESERVED_SHIFT 1 4008 }; 4009 4010 /* union for mac addresses and for tunneling data. 4011 * considered as tunneling data only if (tunnel_exist == 1). 4012 */ 4013 union eth_mac_addr_or_tunnel_data { 4014 struct eth_mac_addresses mac_addr; 4015 struct eth_tunnel_data tunnel_data; 4016 }; 4017 4018 /*Command for setting multicast classification for a client */ 4019 struct eth_multicast_rules_cmd { 4020 u8 cmd_general_data; 4021 #define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1<<0) 4022 #define ETH_MULTICAST_RULES_CMD_RX_CMD_SHIFT 0 4023 #define ETH_MULTICAST_RULES_CMD_TX_CMD (0x1<<1) 4024 #define ETH_MULTICAST_RULES_CMD_TX_CMD_SHIFT 1 4025 #define ETH_MULTICAST_RULES_CMD_IS_ADD (0x1<<2) 4026 #define ETH_MULTICAST_RULES_CMD_IS_ADD_SHIFT 2 4027 #define ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F<<3) 4028 #define ETH_MULTICAST_RULES_CMD_RESERVED0_SHIFT 3 4029 u8 func_id; 4030 u8 bin_id; 4031 u8 engine_id; 4032 __le32 reserved2; 4033 struct regpair reserved3; 4034 }; 4035 4036 /* 4037 * parameters for multicast classification ramrod 4038 */ 4039 struct eth_multicast_rules_ramrod_data { 4040 struct eth_classify_header header; 4041 struct eth_multicast_rules_cmd rules[MULTICAST_RULES_COUNT]; 4042 }; 4043 4044 /* 4045 * Place holder for ramrods protocol specific data 4046 */ 4047 struct ramrod_data { 4048 __le32 data_lo; 4049 __le32 data_hi; 4050 }; 4051 4052 /* 4053 * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits) 4054 */ 4055 union eth_ramrod_data { 4056 struct ramrod_data general; 4057 }; 4058 4059 4060 /* 4061 * RSS toeplitz hash type, as reported in CQE 4062 */ 4063 enum eth_rss_hash_type { 4064 DEFAULT_HASH_TYPE, 4065 IPV4_HASH_TYPE, 4066 TCP_IPV4_HASH_TYPE, 4067 IPV6_HASH_TYPE, 4068 TCP_IPV6_HASH_TYPE, 4069 VLAN_PRI_HASH_TYPE, 4070 E1HOV_PRI_HASH_TYPE, 4071 DSCP_HASH_TYPE, 4072 MAX_ETH_RSS_HASH_TYPE 4073 }; 4074 4075 4076 /* 4077 * Ethernet RSS mode 4078 */ 4079 enum eth_rss_mode { 4080 ETH_RSS_MODE_DISABLED, 4081 ETH_RSS_MODE_REGULAR, 4082 ETH_RSS_MODE_VLAN_PRI, 4083 ETH_RSS_MODE_E1HOV_PRI, 4084 ETH_RSS_MODE_IP_DSCP, 4085 MAX_ETH_RSS_MODE 4086 }; 4087 4088 4089 /* 4090 * parameters for RSS update ramrod (E2) 4091 */ 4092 struct eth_rss_update_ramrod_data { 4093 u8 rss_engine_id; 4094 u8 rss_mode; 4095 __le16 capabilities; 4096 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1<<0) 4097 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY_SHIFT 0 4098 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1<<1) 4099 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY_SHIFT 1 4100 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1<<2) 4101 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY_SHIFT 2 4102 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_VXLAN_CAPABILITY (0x1<<3) 4103 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_VXLAN_CAPABILITY_SHIFT 3 4104 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<4) 4105 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 4 4106 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<5) 4107 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 5 4108 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<6) 4109 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 6 4110 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_VXLAN_CAPABILITY (0x1<<7) 4111 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_VXLAN_CAPABILITY_SHIFT 7 4112 #define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY (0x1<<8) 4113 #define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY_SHIFT 8 4114 #define ETH_RSS_UPDATE_RAMROD_DATA_NVGRE_KEY_ENTROPY_CAPABILITY (0x1<<9) 4115 #define ETH_RSS_UPDATE_RAMROD_DATA_NVGRE_KEY_ENTROPY_CAPABILITY_SHIFT 9 4116 #define ETH_RSS_UPDATE_RAMROD_DATA_GRE_INNER_HDRS_CAPABILITY (0x1<<10) 4117 #define ETH_RSS_UPDATE_RAMROD_DATA_GRE_INNER_HDRS_CAPABILITY_SHIFT 10 4118 #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<11) 4119 #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 11 4120 #define ETH_RSS_UPDATE_RAMROD_DATA_RESERVED (0xF<<12) 4121 #define ETH_RSS_UPDATE_RAMROD_DATA_RESERVED_SHIFT 12 4122 u8 rss_result_mask; 4123 u8 reserved3; 4124 __le16 reserved4; 4125 u8 indirection_table[T_ETH_INDIRECTION_TABLE_SIZE]; 4126 __le32 rss_key[T_ETH_RSS_KEY]; 4127 __le32 echo; 4128 __le32 reserved5; 4129 }; 4130 4131 4132 /* 4133 * The eth Rx Buffer Descriptor 4134 */ 4135 struct eth_rx_bd { 4136 __le32 addr_lo; 4137 __le32 addr_hi; 4138 }; 4139 4140 4141 /* 4142 * Eth Rx Cqe structure- general structure for ramrods 4143 */ 4144 struct common_ramrod_eth_rx_cqe { 4145 u8 ramrod_type; 4146 #define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3<<0) 4147 #define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0 4148 #define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<2) 4149 #define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 2 4150 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F<<3) 4151 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 3 4152 u8 conn_type; 4153 __le16 reserved1; 4154 __le32 conn_and_cmd_data; 4155 #define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0) 4156 #define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0 4157 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24) 4158 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24 4159 struct ramrod_data protocol_data; 4160 __le32 echo; 4161 __le32 reserved2[11]; 4162 }; 4163 4164 /* 4165 * Rx Last CQE in page (in ETH) 4166 */ 4167 struct eth_rx_cqe_next_page { 4168 __le32 addr_lo; 4169 __le32 addr_hi; 4170 __le32 reserved[14]; 4171 }; 4172 4173 /* 4174 * union for all eth rx cqe types (fix their sizes) 4175 */ 4176 union eth_rx_cqe { 4177 struct eth_fast_path_rx_cqe fast_path_cqe; 4178 struct common_ramrod_eth_rx_cqe ramrod_cqe; 4179 struct eth_rx_cqe_next_page next_page_cqe; 4180 struct eth_end_agg_rx_cqe end_agg_cqe; 4181 }; 4182 4183 4184 /* 4185 * Values for RX ETH CQE type field 4186 */ 4187 enum eth_rx_cqe_type { 4188 RX_ETH_CQE_TYPE_ETH_FASTPATH, 4189 RX_ETH_CQE_TYPE_ETH_RAMROD, 4190 RX_ETH_CQE_TYPE_ETH_START_AGG, 4191 RX_ETH_CQE_TYPE_ETH_STOP_AGG, 4192 MAX_ETH_RX_CQE_TYPE 4193 }; 4194 4195 4196 /* 4197 * Type of SGL/Raw field in ETH RX fast path CQE 4198 */ 4199 enum eth_rx_fp_sel { 4200 ETH_FP_CQE_REGULAR, 4201 ETH_FP_CQE_RAW, 4202 MAX_ETH_RX_FP_SEL 4203 }; 4204 4205 4206 /* 4207 * The eth Rx SGE Descriptor 4208 */ 4209 struct eth_rx_sge { 4210 __le32 addr_lo; 4211 __le32 addr_hi; 4212 }; 4213 4214 4215 /* 4216 * common data for all protocols 4217 */ 4218 struct spe_hdr { 4219 __le32 conn_and_cmd_data; 4220 #define SPE_HDR_CID (0xFFFFFF<<0) 4221 #define SPE_HDR_CID_SHIFT 0 4222 #define SPE_HDR_CMD_ID (0xFF<<24) 4223 #define SPE_HDR_CMD_ID_SHIFT 24 4224 __le16 type; 4225 #define SPE_HDR_CONN_TYPE (0xFF<<0) 4226 #define SPE_HDR_CONN_TYPE_SHIFT 0 4227 #define SPE_HDR_FUNCTION_ID (0xFF<<8) 4228 #define SPE_HDR_FUNCTION_ID_SHIFT 8 4229 __le16 reserved1; 4230 }; 4231 4232 /* 4233 * specific data for ethernet slow path element 4234 */ 4235 union eth_specific_data { 4236 u8 protocol_data[8]; 4237 struct regpair client_update_ramrod_data; 4238 struct regpair client_init_ramrod_init_data; 4239 struct eth_halt_ramrod_data halt_ramrod_data; 4240 struct regpair update_data_addr; 4241 struct eth_common_ramrod_data common_ramrod_data; 4242 struct regpair classify_cfg_addr; 4243 struct regpair filter_cfg_addr; 4244 struct regpair mcast_cfg_addr; 4245 }; 4246 4247 /* 4248 * Ethernet slow path element 4249 */ 4250 struct eth_spe { 4251 struct spe_hdr hdr; 4252 union eth_specific_data data; 4253 }; 4254 4255 4256 /* 4257 * Ethernet command ID for slow path elements 4258 */ 4259 enum eth_spqe_cmd_id { 4260 RAMROD_CMD_ID_ETH_UNUSED, 4261 RAMROD_CMD_ID_ETH_CLIENT_SETUP, 4262 RAMROD_CMD_ID_ETH_HALT, 4263 RAMROD_CMD_ID_ETH_FORWARD_SETUP, 4264 RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP, 4265 RAMROD_CMD_ID_ETH_CLIENT_UPDATE, 4266 RAMROD_CMD_ID_ETH_EMPTY, 4267 RAMROD_CMD_ID_ETH_TERMINATE, 4268 RAMROD_CMD_ID_ETH_TPA_UPDATE, 4269 RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES, 4270 RAMROD_CMD_ID_ETH_FILTER_RULES, 4271 RAMROD_CMD_ID_ETH_MULTICAST_RULES, 4272 RAMROD_CMD_ID_ETH_RSS_UPDATE, 4273 RAMROD_CMD_ID_ETH_SET_MAC, 4274 MAX_ETH_SPQE_CMD_ID 4275 }; 4276 4277 4278 /* 4279 * eth tpa update command 4280 */ 4281 enum eth_tpa_update_command { 4282 TPA_UPDATE_NONE_COMMAND, 4283 TPA_UPDATE_ENABLE_COMMAND, 4284 TPA_UPDATE_DISABLE_COMMAND, 4285 MAX_ETH_TPA_UPDATE_COMMAND 4286 }; 4287 4288 /* In case of LSO over IPv4 tunnel, whether to increment 4289 * IP ID on external IP header or internal IP header 4290 */ 4291 enum eth_tunnel_lso_inc_ip_id { 4292 EXT_HEADER, 4293 INT_HEADER, 4294 MAX_ETH_TUNNEL_LSO_INC_IP_ID 4295 }; 4296 4297 /* In case tunnel exist and L4 checksum offload, 4298 * the pseudo checksum location, on packet or on BD. 4299 */ 4300 enum eth_tunnel_non_lso_csum_location { 4301 CSUM_ON_PKT, 4302 CSUM_ON_BD, 4303 MAX_ETH_TUNNEL_NON_LSO_CSUM_LOCATION 4304 }; 4305 4306 /* 4307 * Tx regular BD structure 4308 */ 4309 struct eth_tx_bd { 4310 __le32 addr_lo; 4311 __le32 addr_hi; 4312 __le16 total_pkt_bytes; 4313 __le16 nbytes; 4314 u8 reserved[4]; 4315 }; 4316 4317 4318 /* 4319 * structure for easy accessibility to assembler 4320 */ 4321 struct eth_tx_bd_flags { 4322 u8 as_bitfield; 4323 #define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0) 4324 #define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0 4325 #define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1) 4326 #define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1 4327 #define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2) 4328 #define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2 4329 #define ETH_TX_BD_FLAGS_START_BD (0x1<<4) 4330 #define ETH_TX_BD_FLAGS_START_BD_SHIFT 4 4331 #define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5) 4332 #define ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5 4333 #define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6) 4334 #define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6 4335 #define ETH_TX_BD_FLAGS_IPV6 (0x1<<7) 4336 #define ETH_TX_BD_FLAGS_IPV6_SHIFT 7 4337 }; 4338 4339 /* 4340 * The eth Tx Buffer Descriptor 4341 */ 4342 struct eth_tx_start_bd { 4343 __le32 addr_lo; 4344 __le32 addr_hi; 4345 __le16 nbd; 4346 __le16 nbytes; 4347 __le16 vlan_or_ethertype; 4348 struct eth_tx_bd_flags bd_flags; 4349 u8 general_data; 4350 #define ETH_TX_START_BD_HDR_NBDS (0x7<<0) 4351 #define ETH_TX_START_BD_HDR_NBDS_SHIFT 0 4352 #define ETH_TX_START_BD_NO_ADDED_TAGS (0x1<<3) 4353 #define ETH_TX_START_BD_NO_ADDED_TAGS_SHIFT 3 4354 #define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4) 4355 #define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4 4356 #define ETH_TX_START_BD_PARSE_NBDS (0x3<<5) 4357 #define ETH_TX_START_BD_PARSE_NBDS_SHIFT 5 4358 #define ETH_TX_START_BD_TUNNEL_EXIST (0x1<<7) 4359 #define ETH_TX_START_BD_TUNNEL_EXIST_SHIFT 7 4360 }; 4361 4362 /* 4363 * Tx parsing BD structure for ETH E1/E1h 4364 */ 4365 struct eth_tx_parse_bd_e1x { 4366 __le16 global_data; 4367 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0) 4368 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0 4369 #define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE (0x3<<4) 4370 #define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE_SHIFT 4 4371 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<6) 4372 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 6 4373 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<7) 4374 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 7 4375 #define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<8) 4376 #define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 8 4377 #define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x7F<<9) 4378 #define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 9 4379 u8 tcp_flags; 4380 #define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0) 4381 #define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0 4382 #define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1) 4383 #define ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1 4384 #define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2) 4385 #define ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2 4386 #define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3) 4387 #define ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3 4388 #define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4) 4389 #define ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4 4390 #define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5) 4391 #define ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5 4392 #define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6) 4393 #define ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6 4394 #define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7) 4395 #define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7 4396 u8 ip_hlen_w; 4397 __le16 total_hlen_w; 4398 __le16 tcp_pseudo_csum; 4399 __le16 lso_mss; 4400 __le16 ip_id; 4401 __le32 tcp_send_seq; 4402 }; 4403 4404 /* 4405 * Tx parsing BD structure for ETH E2 4406 */ 4407 struct eth_tx_parse_bd_e2 { 4408 union eth_mac_addr_or_tunnel_data data; 4409 __le32 parsing_data; 4410 #define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W (0x7FF<<0) 4411 #define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W_SHIFT 0 4412 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<11) 4413 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 11 4414 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<15) 4415 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 15 4416 #define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<16) 4417 #define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 16 4418 #define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE (0x3<<30) 4419 #define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT 30 4420 }; 4421 4422 /* 4423 * Tx 2nd parsing BD structure for ETH packet 4424 */ 4425 struct eth_tx_parse_2nd_bd { 4426 __le16 global_data; 4427 #define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W (0xF<<0) 4428 #define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W_SHIFT 0 4429 #define ETH_TX_PARSE_2ND_BD_RESERVED0 (0x1<<4) 4430 #define ETH_TX_PARSE_2ND_BD_RESERVED0_SHIFT 4 4431 #define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN (0x1<<5) 4432 #define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN_SHIFT 5 4433 #define ETH_TX_PARSE_2ND_BD_NS_FLG (0x1<<6) 4434 #define ETH_TX_PARSE_2ND_BD_NS_FLG_SHIFT 6 4435 #define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST (0x1<<7) 4436 #define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST_SHIFT 7 4437 #define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W (0x1F<<8) 4438 #define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W_SHIFT 8 4439 #define ETH_TX_PARSE_2ND_BD_RESERVED1 (0x7<<13) 4440 #define ETH_TX_PARSE_2ND_BD_RESERVED1_SHIFT 13 4441 u8 bd_type; 4442 #define ETH_TX_PARSE_2ND_BD_TYPE (0xF<<0) 4443 #define ETH_TX_PARSE_2ND_BD_TYPE_SHIFT 0 4444 #define ETH_TX_PARSE_2ND_BD_RESERVED2 (0xF<<4) 4445 #define ETH_TX_PARSE_2ND_BD_RESERVED2_SHIFT 4 4446 u8 reserved3; 4447 u8 tcp_flags; 4448 #define ETH_TX_PARSE_2ND_BD_FIN_FLG (0x1<<0) 4449 #define ETH_TX_PARSE_2ND_BD_FIN_FLG_SHIFT 0 4450 #define ETH_TX_PARSE_2ND_BD_SYN_FLG (0x1<<1) 4451 #define ETH_TX_PARSE_2ND_BD_SYN_FLG_SHIFT 1 4452 #define ETH_TX_PARSE_2ND_BD_RST_FLG (0x1<<2) 4453 #define ETH_TX_PARSE_2ND_BD_RST_FLG_SHIFT 2 4454 #define ETH_TX_PARSE_2ND_BD_PSH_FLG (0x1<<3) 4455 #define ETH_TX_PARSE_2ND_BD_PSH_FLG_SHIFT 3 4456 #define ETH_TX_PARSE_2ND_BD_ACK_FLG (0x1<<4) 4457 #define ETH_TX_PARSE_2ND_BD_ACK_FLG_SHIFT 4 4458 #define ETH_TX_PARSE_2ND_BD_URG_FLG (0x1<<5) 4459 #define ETH_TX_PARSE_2ND_BD_URG_FLG_SHIFT 5 4460 #define ETH_TX_PARSE_2ND_BD_ECE_FLG (0x1<<6) 4461 #define ETH_TX_PARSE_2ND_BD_ECE_FLG_SHIFT 6 4462 #define ETH_TX_PARSE_2ND_BD_CWR_FLG (0x1<<7) 4463 #define ETH_TX_PARSE_2ND_BD_CWR_FLG_SHIFT 7 4464 u8 reserved4; 4465 u8 tunnel_udp_hdr_start_w; 4466 u8 fw_ip_hdr_to_payload_w; 4467 __le16 fw_ip_csum_wo_len_flags_frag; 4468 __le16 hw_ip_id; 4469 __le32 tcp_send_seq; 4470 }; 4471 4472 /* The last BD in the BD memory will hold a pointer to the next BD memory */ 4473 struct eth_tx_next_bd { 4474 __le32 addr_lo; 4475 __le32 addr_hi; 4476 u8 reserved[8]; 4477 }; 4478 4479 /* 4480 * union for 4 Bd types 4481 */ 4482 union eth_tx_bd_types { 4483 struct eth_tx_start_bd start_bd; 4484 struct eth_tx_bd reg_bd; 4485 struct eth_tx_parse_bd_e1x parse_bd_e1x; 4486 struct eth_tx_parse_bd_e2 parse_bd_e2; 4487 struct eth_tx_parse_2nd_bd parse_2nd_bd; 4488 struct eth_tx_next_bd next_bd; 4489 }; 4490 4491 /* 4492 * array of 13 bds as appears in the eth xstorm context 4493 */ 4494 struct eth_tx_bds_array { 4495 union eth_tx_bd_types bds[13]; 4496 }; 4497 4498 4499 /* 4500 * VLAN mode on TX BDs 4501 */ 4502 enum eth_tx_vlan_type { 4503 X_ETH_NO_VLAN, 4504 X_ETH_OUTBAND_VLAN, 4505 X_ETH_INBAND_VLAN, 4506 X_ETH_FW_ADDED_VLAN, 4507 MAX_ETH_TX_VLAN_TYPE 4508 }; 4509 4510 4511 /* 4512 * Ethernet VLAN filtering mode in E1x 4513 */ 4514 enum eth_vlan_filter_mode { 4515 ETH_VLAN_FILTER_ANY_VLAN, 4516 ETH_VLAN_FILTER_SPECIFIC_VLAN, 4517 ETH_VLAN_FILTER_CLASSIFY, 4518 MAX_ETH_VLAN_FILTER_MODE 4519 }; 4520 4521 4522 /* 4523 * MAC filtering configuration command header 4524 */ 4525 struct mac_configuration_hdr { 4526 u8 length; 4527 u8 offset; 4528 __le16 client_id; 4529 __le32 echo; 4530 }; 4531 4532 /* 4533 * MAC address in list for ramrod 4534 */ 4535 struct mac_configuration_entry { 4536 __le16 lsb_mac_addr; 4537 __le16 middle_mac_addr; 4538 __le16 msb_mac_addr; 4539 __le16 vlan_id; 4540 u8 pf_id; 4541 u8 flags; 4542 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0) 4543 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0 4544 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1) 4545 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 1 4546 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2) 4547 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 2 4548 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4) 4549 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 4 4550 #define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5) 4551 #define MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 5 4552 #define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6) 4553 #define MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 6 4554 __le16 reserved0; 4555 __le32 clients_bit_vector; 4556 }; 4557 4558 /* 4559 * MAC filtering configuration command 4560 */ 4561 struct mac_configuration_cmd { 4562 struct mac_configuration_hdr hdr; 4563 struct mac_configuration_entry config_table[64]; 4564 }; 4565 4566 4567 /* 4568 * Set-MAC command type (in E1x) 4569 */ 4570 enum set_mac_action_type { 4571 T_ETH_MAC_COMMAND_INVALIDATE, 4572 T_ETH_MAC_COMMAND_SET, 4573 MAX_SET_MAC_ACTION_TYPE 4574 }; 4575 4576 4577 /* 4578 * Ethernet TPA Modes 4579 */ 4580 enum tpa_mode { 4581 TPA_LRO, 4582 TPA_GRO, 4583 MAX_TPA_MODE}; 4584 4585 4586 /* 4587 * tpa update ramrod data 4588 */ 4589 struct tpa_update_ramrod_data { 4590 u8 update_ipv4; 4591 u8 update_ipv6; 4592 u8 client_id; 4593 u8 max_tpa_queues; 4594 u8 max_sges_for_packet; 4595 u8 complete_on_both_clients; 4596 u8 dont_verify_rings_pause_thr_flg; 4597 u8 tpa_mode; 4598 __le16 sge_buff_size; 4599 __le16 max_agg_size; 4600 __le32 sge_page_base_lo; 4601 __le32 sge_page_base_hi; 4602 __le16 sge_pause_thr_low; 4603 __le16 sge_pause_thr_high; 4604 }; 4605 4606 4607 /* 4608 * approximate-match multicast filtering for E1H per function in Tstorm 4609 */ 4610 struct tstorm_eth_approximate_match_multicast_filtering { 4611 u32 mcast_add_hash_bit_array[8]; 4612 }; 4613 4614 4615 /* 4616 * Common configuration parameters per function in Tstorm 4617 */ 4618 struct tstorm_eth_function_common_config { 4619 __le16 config_flags; 4620 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0) 4621 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0 4622 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1) 4623 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1 4624 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2) 4625 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2 4626 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3) 4627 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3 4628 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4) 4629 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4 4630 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<7) 4631 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 7 4632 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0xFF<<8) 4633 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 8 4634 u8 rss_result_mask; 4635 u8 reserved1; 4636 __le16 vlan_id[2]; 4637 }; 4638 4639 4640 /* 4641 * MAC filtering configuration parameters per port in Tstorm 4642 */ 4643 struct tstorm_eth_mac_filter_config { 4644 u32 ucast_drop_all; 4645 u32 ucast_accept_all; 4646 u32 mcast_drop_all; 4647 u32 mcast_accept_all; 4648 u32 bcast_accept_all; 4649 u32 vlan_filter[2]; 4650 u32 unmatched_unicast; 4651 }; 4652 4653 4654 /* 4655 * tx only queue init ramrod data 4656 */ 4657 struct tx_queue_init_ramrod_data { 4658 struct client_init_general_data general; 4659 struct client_init_tx_data tx; 4660 }; 4661 4662 4663 /* 4664 * Three RX producers for ETH 4665 */ 4666 struct ustorm_eth_rx_producers { 4667 #if defined(__BIG_ENDIAN) 4668 u16 bd_prod; 4669 u16 cqe_prod; 4670 #elif defined(__LITTLE_ENDIAN) 4671 u16 cqe_prod; 4672 u16 bd_prod; 4673 #endif 4674 #if defined(__BIG_ENDIAN) 4675 u16 reserved; 4676 u16 sge_prod; 4677 #elif defined(__LITTLE_ENDIAN) 4678 u16 sge_prod; 4679 u16 reserved; 4680 #endif 4681 }; 4682 4683 4684 /* 4685 * FCoE RX statistics parameters section#0 4686 */ 4687 struct fcoe_rx_stat_params_section0 { 4688 __le32 fcoe_rx_pkt_cnt; 4689 __le32 fcoe_rx_byte_cnt; 4690 }; 4691 4692 4693 /* 4694 * FCoE RX statistics parameters section#1 4695 */ 4696 struct fcoe_rx_stat_params_section1 { 4697 __le32 fcoe_ver_cnt; 4698 __le32 fcoe_rx_drop_pkt_cnt; 4699 }; 4700 4701 4702 /* 4703 * FCoE RX statistics parameters section#2 4704 */ 4705 struct fcoe_rx_stat_params_section2 { 4706 __le32 fc_crc_cnt; 4707 __le32 eofa_del_cnt; 4708 __le32 miss_frame_cnt; 4709 __le32 seq_timeout_cnt; 4710 __le32 drop_seq_cnt; 4711 __le32 fcoe_rx_drop_pkt_cnt; 4712 __le32 fcp_rx_pkt_cnt; 4713 __le32 reserved0; 4714 }; 4715 4716 4717 /* 4718 * FCoE TX statistics parameters 4719 */ 4720 struct fcoe_tx_stat_params { 4721 __le32 fcoe_tx_pkt_cnt; 4722 __le32 fcoe_tx_byte_cnt; 4723 __le32 fcp_tx_pkt_cnt; 4724 __le32 reserved0; 4725 }; 4726 4727 /* 4728 * FCoE statistics parameters 4729 */ 4730 struct fcoe_statistics_params { 4731 struct fcoe_tx_stat_params tx_stat; 4732 struct fcoe_rx_stat_params_section0 rx_stat0; 4733 struct fcoe_rx_stat_params_section1 rx_stat1; 4734 struct fcoe_rx_stat_params_section2 rx_stat2; 4735 }; 4736 4737 4738 /* 4739 * The data afex vif list ramrod need 4740 */ 4741 struct afex_vif_list_ramrod_data { 4742 u8 afex_vif_list_command; 4743 u8 func_bit_map; 4744 __le16 vif_list_index; 4745 u8 func_to_clear; 4746 u8 echo; 4747 __le16 reserved1; 4748 }; 4749 4750 4751 /* 4752 * cfc delete event data 4753 */ 4754 struct cfc_del_event_data { 4755 u32 cid; 4756 u32 reserved0; 4757 u32 reserved1; 4758 }; 4759 4760 4761 /* 4762 * per-port SAFC demo variables 4763 */ 4764 struct cmng_flags_per_port { 4765 u32 cmng_enables; 4766 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0) 4767 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0 4768 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1) 4769 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1 4770 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<2) 4771 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 2 4772 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<3) 4773 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 3 4774 #define __CMNG_FLAGS_PER_PORT_RESERVED0 (0xFFFFFFF<<4) 4775 #define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 4 4776 u32 __reserved1; 4777 }; 4778 4779 4780 /* 4781 * per-port rate shaping variables 4782 */ 4783 struct rate_shaping_vars_per_port { 4784 u32 rs_periodic_timeout; 4785 u32 rs_threshold; 4786 }; 4787 4788 /* 4789 * per-port fairness variables 4790 */ 4791 struct fairness_vars_per_port { 4792 u32 upper_bound; 4793 u32 fair_threshold; 4794 u32 fairness_timeout; 4795 u32 reserved0; 4796 }; 4797 4798 /* 4799 * per-port SAFC variables 4800 */ 4801 struct safc_struct_per_port { 4802 #if defined(__BIG_ENDIAN) 4803 u16 __reserved1; 4804 u8 __reserved0; 4805 u8 safc_timeout_usec; 4806 #elif defined(__LITTLE_ENDIAN) 4807 u8 safc_timeout_usec; 4808 u8 __reserved0; 4809 u16 __reserved1; 4810 #endif 4811 u8 cos_to_traffic_types[MAX_COS_NUMBER]; 4812 u16 cos_to_pause_mask[NUM_OF_SAFC_BITS]; 4813 }; 4814 4815 /* 4816 * Per-port congestion management variables 4817 */ 4818 struct cmng_struct_per_port { 4819 struct rate_shaping_vars_per_port rs_vars; 4820 struct fairness_vars_per_port fair_vars; 4821 struct safc_struct_per_port safc_vars; 4822 struct cmng_flags_per_port flags; 4823 }; 4824 4825 /* 4826 * a single rate shaping counter. can be used as protocol or vnic counter 4827 */ 4828 struct rate_shaping_counter { 4829 u32 quota; 4830 #if defined(__BIG_ENDIAN) 4831 u16 __reserved0; 4832 u16 rate; 4833 #elif defined(__LITTLE_ENDIAN) 4834 u16 rate; 4835 u16 __reserved0; 4836 #endif 4837 }; 4838 4839 /* 4840 * per-vnic rate shaping variables 4841 */ 4842 struct rate_shaping_vars_per_vn { 4843 struct rate_shaping_counter vn_counter; 4844 }; 4845 4846 /* 4847 * per-vnic fairness variables 4848 */ 4849 struct fairness_vars_per_vn { 4850 u32 cos_credit_delta[MAX_COS_NUMBER]; 4851 u32 vn_credit_delta; 4852 u32 __reserved0; 4853 }; 4854 4855 /* 4856 * cmng port init state 4857 */ 4858 struct cmng_vnic { 4859 struct rate_shaping_vars_per_vn vnic_max_rate[4]; 4860 struct fairness_vars_per_vn vnic_min_rate[4]; 4861 }; 4862 4863 /* 4864 * cmng port init state 4865 */ 4866 struct cmng_init { 4867 struct cmng_struct_per_port port; 4868 struct cmng_vnic vnic; 4869 }; 4870 4871 4872 /* 4873 * driver parameters for congestion management init, all rates are in Mbps 4874 */ 4875 struct cmng_init_input { 4876 u32 port_rate; 4877 u16 vnic_min_rate[4]; 4878 u16 vnic_max_rate[4]; 4879 u16 cos_min_rate[MAX_COS_NUMBER]; 4880 u16 cos_to_pause_mask[MAX_COS_NUMBER]; 4881 struct cmng_flags_per_port flags; 4882 }; 4883 4884 4885 /* 4886 * Protocol-common command ID for slow path elements 4887 */ 4888 enum common_spqe_cmd_id { 4889 RAMROD_CMD_ID_COMMON_UNUSED, 4890 RAMROD_CMD_ID_COMMON_FUNCTION_START, 4891 RAMROD_CMD_ID_COMMON_FUNCTION_STOP, 4892 RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE, 4893 RAMROD_CMD_ID_COMMON_CFC_DEL, 4894 RAMROD_CMD_ID_COMMON_CFC_DEL_WB, 4895 RAMROD_CMD_ID_COMMON_STAT_QUERY, 4896 RAMROD_CMD_ID_COMMON_STOP_TRAFFIC, 4897 RAMROD_CMD_ID_COMMON_START_TRAFFIC, 4898 RAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS, 4899 RAMROD_CMD_ID_COMMON_SET_TIMESYNC, 4900 MAX_COMMON_SPQE_CMD_ID 4901 }; 4902 4903 /* 4904 * Per-protocol connection types 4905 */ 4906 enum connection_type { 4907 ETH_CONNECTION_TYPE, 4908 TOE_CONNECTION_TYPE, 4909 RDMA_CONNECTION_TYPE, 4910 ISCSI_CONNECTION_TYPE, 4911 FCOE_CONNECTION_TYPE, 4912 RESERVED_CONNECTION_TYPE_0, 4913 RESERVED_CONNECTION_TYPE_1, 4914 RESERVED_CONNECTION_TYPE_2, 4915 NONE_CONNECTION_TYPE, 4916 MAX_CONNECTION_TYPE 4917 }; 4918 4919 4920 /* 4921 * Cos modes 4922 */ 4923 enum cos_mode { 4924 OVERRIDE_COS, 4925 STATIC_COS, 4926 FW_WRR, 4927 MAX_COS_MODE 4928 }; 4929 4930 4931 /* 4932 * Dynamic HC counters set by the driver 4933 */ 4934 struct hc_dynamic_drv_counter { 4935 u32 val[HC_SB_MAX_DYNAMIC_INDICES]; 4936 }; 4937 4938 /* 4939 * zone A per-queue data 4940 */ 4941 struct cstorm_queue_zone_data { 4942 struct hc_dynamic_drv_counter hc_dyn_drv_cnt; 4943 struct regpair reserved[2]; 4944 }; 4945 4946 4947 /* 4948 * Vf-PF channel data in cstorm ram (non-triggered zone) 4949 */ 4950 struct vf_pf_channel_zone_data { 4951 u32 msg_addr_lo; 4952 u32 msg_addr_hi; 4953 }; 4954 4955 /* 4956 * zone for VF non-triggered data 4957 */ 4958 struct non_trigger_vf_zone { 4959 struct vf_pf_channel_zone_data vf_pf_channel; 4960 }; 4961 4962 /* 4963 * Vf-PF channel trigger zone in cstorm ram 4964 */ 4965 struct vf_pf_channel_zone_trigger { 4966 u8 addr_valid; 4967 }; 4968 4969 /* 4970 * zone that triggers the in-bound interrupt 4971 */ 4972 struct trigger_vf_zone { 4973 #if defined(__BIG_ENDIAN) 4974 u16 reserved1; 4975 u8 reserved0; 4976 struct vf_pf_channel_zone_trigger vf_pf_channel; 4977 #elif defined(__LITTLE_ENDIAN) 4978 struct vf_pf_channel_zone_trigger vf_pf_channel; 4979 u8 reserved0; 4980 u16 reserved1; 4981 #endif 4982 u32 reserved2; 4983 }; 4984 4985 /* 4986 * zone B per-VF data 4987 */ 4988 struct cstorm_vf_zone_data { 4989 struct non_trigger_vf_zone non_trigger; 4990 struct trigger_vf_zone trigger; 4991 }; 4992 4993 4994 /* 4995 * Dynamic host coalescing init parameters, per state machine 4996 */ 4997 struct dynamic_hc_sm_config { 4998 u32 threshold[3]; 4999 u8 shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES]; 5000 u8 hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES]; 5001 u8 hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES]; 5002 u8 hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES]; 5003 u8 hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES]; 5004 }; 5005 5006 /* 5007 * Dynamic host coalescing init parameters 5008 */ 5009 struct dynamic_hc_config { 5010 struct dynamic_hc_sm_config sm_config[HC_SB_MAX_SM]; 5011 }; 5012 5013 5014 struct e2_integ_data { 5015 #if defined(__BIG_ENDIAN) 5016 u8 flags; 5017 #define E2_INTEG_DATA_TESTING_EN (0x1<<0) 5018 #define E2_INTEG_DATA_TESTING_EN_SHIFT 0 5019 #define E2_INTEG_DATA_LB_TX (0x1<<1) 5020 #define E2_INTEG_DATA_LB_TX_SHIFT 1 5021 #define E2_INTEG_DATA_COS_TX (0x1<<2) 5022 #define E2_INTEG_DATA_COS_TX_SHIFT 2 5023 #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) 5024 #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3 5025 #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) 5026 #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4 5027 #define E2_INTEG_DATA_RESERVED (0x7<<5) 5028 #define E2_INTEG_DATA_RESERVED_SHIFT 5 5029 u8 cos; 5030 u8 voq; 5031 u8 pbf_queue; 5032 #elif defined(__LITTLE_ENDIAN) 5033 u8 pbf_queue; 5034 u8 voq; 5035 u8 cos; 5036 u8 flags; 5037 #define E2_INTEG_DATA_TESTING_EN (0x1<<0) 5038 #define E2_INTEG_DATA_TESTING_EN_SHIFT 0 5039 #define E2_INTEG_DATA_LB_TX (0x1<<1) 5040 #define E2_INTEG_DATA_LB_TX_SHIFT 1 5041 #define E2_INTEG_DATA_COS_TX (0x1<<2) 5042 #define E2_INTEG_DATA_COS_TX_SHIFT 2 5043 #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) 5044 #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3 5045 #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) 5046 #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4 5047 #define E2_INTEG_DATA_RESERVED (0x7<<5) 5048 #define E2_INTEG_DATA_RESERVED_SHIFT 5 5049 #endif 5050 #if defined(__BIG_ENDIAN) 5051 u16 reserved3; 5052 u8 reserved2; 5053 u8 ramEn; 5054 #elif defined(__LITTLE_ENDIAN) 5055 u8 ramEn; 5056 u8 reserved2; 5057 u16 reserved3; 5058 #endif 5059 }; 5060 5061 5062 /* 5063 * set mac event data 5064 */ 5065 struct eth_event_data { 5066 u32 echo; 5067 u32 reserved0; 5068 u32 reserved1; 5069 }; 5070 5071 5072 /* 5073 * pf-vf event data 5074 */ 5075 struct vf_pf_event_data { 5076 u8 vf_id; 5077 u8 reserved0; 5078 u16 reserved1; 5079 u32 msg_addr_lo; 5080 u32 msg_addr_hi; 5081 }; 5082 5083 /* 5084 * VF FLR event data 5085 */ 5086 struct vf_flr_event_data { 5087 u8 vf_id; 5088 u8 reserved0; 5089 u16 reserved1; 5090 u32 reserved2; 5091 u32 reserved3; 5092 }; 5093 5094 /* 5095 * malicious VF event data 5096 */ 5097 struct malicious_vf_event_data { 5098 u8 vf_id; 5099 u8 err_id; 5100 u16 reserved1; 5101 u32 reserved2; 5102 u32 reserved3; 5103 }; 5104 5105 /* 5106 * vif list event data 5107 */ 5108 struct vif_list_event_data { 5109 u8 func_bit_map; 5110 u8 echo; 5111 __le16 reserved0; 5112 __le32 reserved1; 5113 __le32 reserved2; 5114 }; 5115 5116 /* function update event data */ 5117 struct function_update_event_data { 5118 u8 echo; 5119 u8 reserved; 5120 __le16 reserved0; 5121 __le32 reserved1; 5122 __le32 reserved2; 5123 }; 5124 5125 5126 /* union for all event ring message types */ 5127 union event_data { 5128 struct vf_pf_event_data vf_pf_event; 5129 struct eth_event_data eth_event; 5130 struct cfc_del_event_data cfc_del_event; 5131 struct vf_flr_event_data vf_flr_event; 5132 struct malicious_vf_event_data malicious_vf_event; 5133 struct vif_list_event_data vif_list_event; 5134 struct function_update_event_data function_update_event; 5135 }; 5136 5137 5138 /* 5139 * per PF event ring data 5140 */ 5141 struct event_ring_data { 5142 struct regpair_native base_addr; 5143 #if defined(__BIG_ENDIAN) 5144 u8 index_id; 5145 u8 sb_id; 5146 u16 producer; 5147 #elif defined(__LITTLE_ENDIAN) 5148 u16 producer; 5149 u8 sb_id; 5150 u8 index_id; 5151 #endif 5152 u32 reserved0; 5153 }; 5154 5155 5156 /* 5157 * event ring message element (each element is 128 bits) 5158 */ 5159 struct event_ring_msg { 5160 u8 opcode; 5161 u8 error; 5162 u16 reserved1; 5163 union event_data data; 5164 }; 5165 5166 /* 5167 * event ring next page element (128 bits) 5168 */ 5169 struct event_ring_next { 5170 struct regpair addr; 5171 u32 reserved[2]; 5172 }; 5173 5174 /* 5175 * union for event ring element types (each element is 128 bits) 5176 */ 5177 union event_ring_elem { 5178 struct event_ring_msg message; 5179 struct event_ring_next next_page; 5180 }; 5181 5182 5183 /* 5184 * Common event ring opcodes 5185 */ 5186 enum event_ring_opcode { 5187 EVENT_RING_OPCODE_VF_PF_CHANNEL, 5188 EVENT_RING_OPCODE_FUNCTION_START, 5189 EVENT_RING_OPCODE_FUNCTION_STOP, 5190 EVENT_RING_OPCODE_CFC_DEL, 5191 EVENT_RING_OPCODE_CFC_DEL_WB, 5192 EVENT_RING_OPCODE_STAT_QUERY, 5193 EVENT_RING_OPCODE_STOP_TRAFFIC, 5194 EVENT_RING_OPCODE_START_TRAFFIC, 5195 EVENT_RING_OPCODE_VF_FLR, 5196 EVENT_RING_OPCODE_MALICIOUS_VF, 5197 EVENT_RING_OPCODE_FORWARD_SETUP, 5198 EVENT_RING_OPCODE_RSS_UPDATE_RULES, 5199 EVENT_RING_OPCODE_FUNCTION_UPDATE, 5200 EVENT_RING_OPCODE_AFEX_VIF_LISTS, 5201 EVENT_RING_OPCODE_SET_MAC, 5202 EVENT_RING_OPCODE_CLASSIFICATION_RULES, 5203 EVENT_RING_OPCODE_FILTERS_RULES, 5204 EVENT_RING_OPCODE_MULTICAST_RULES, 5205 EVENT_RING_OPCODE_SET_TIMESYNC, 5206 MAX_EVENT_RING_OPCODE 5207 }; 5208 5209 /* 5210 * Modes for fairness algorithm 5211 */ 5212 enum fairness_mode { 5213 FAIRNESS_COS_WRR_MODE, 5214 FAIRNESS_COS_ETS_MODE, 5215 MAX_FAIRNESS_MODE 5216 }; 5217 5218 5219 /* 5220 * Priority and cos 5221 */ 5222 struct priority_cos { 5223 u8 priority; 5224 u8 cos; 5225 __le16 reserved1; 5226 }; 5227 5228 /* 5229 * The data for flow control configuration 5230 */ 5231 struct flow_control_configuration { 5232 struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES]; 5233 u8 dcb_enabled; 5234 u8 dcb_version; 5235 u8 dont_add_pri_0_en; 5236 u8 reserved1; 5237 __le32 reserved2; 5238 }; 5239 5240 5241 /* 5242 * 5243 */ 5244 struct function_start_data { 5245 u8 function_mode; 5246 u8 allow_npar_tx_switching; 5247 __le16 sd_vlan_tag; 5248 __le16 vif_id; 5249 u8 path_id; 5250 u8 network_cos_mode; 5251 u8 dmae_cmd_id; 5252 u8 tunnel_mode; 5253 u8 gre_tunnel_type; 5254 u8 tunn_clss_en; 5255 u8 inner_gre_rss_en; 5256 u8 sd_accept_mf_clss_fail; 5257 __le16 vxlan_dst_port; 5258 __le16 sd_accept_mf_clss_fail_ethtype; 5259 __le16 sd_vlan_eth_type; 5260 u8 sd_vlan_force_pri_flg; 5261 u8 sd_vlan_force_pri_val; 5262 u8 sd_accept_mf_clss_fail_match_ethtype; 5263 u8 no_added_tags; 5264 }; 5265 5266 struct function_update_data { 5267 u8 vif_id_change_flg; 5268 u8 afex_default_vlan_change_flg; 5269 u8 allowed_priorities_change_flg; 5270 u8 network_cos_mode_change_flg; 5271 __le16 vif_id; 5272 __le16 afex_default_vlan; 5273 u8 allowed_priorities; 5274 u8 network_cos_mode; 5275 u8 lb_mode_en_change_flg; 5276 u8 lb_mode_en; 5277 u8 tx_switch_suspend_change_flg; 5278 u8 tx_switch_suspend; 5279 u8 echo; 5280 u8 update_tunn_cfg_flg; 5281 u8 tunnel_mode; 5282 u8 gre_tunnel_type; 5283 u8 tunn_clss_en; 5284 u8 inner_gre_rss_en; 5285 __le16 vxlan_dst_port; 5286 u8 sd_vlan_force_pri_change_flg; 5287 u8 sd_vlan_force_pri_flg; 5288 u8 sd_vlan_force_pri_val; 5289 u8 sd_vlan_tag_change_flg; 5290 u8 sd_vlan_eth_type_change_flg; 5291 u8 reserved1; 5292 __le16 sd_vlan_tag; 5293 __le16 sd_vlan_eth_type; 5294 }; 5295 5296 /* 5297 * FW version stored in the Xstorm RAM 5298 */ 5299 struct fw_version { 5300 #if defined(__BIG_ENDIAN) 5301 u8 engineering; 5302 u8 revision; 5303 u8 minor; 5304 u8 major; 5305 #elif defined(__LITTLE_ENDIAN) 5306 u8 major; 5307 u8 minor; 5308 u8 revision; 5309 u8 engineering; 5310 #endif 5311 u32 flags; 5312 #define FW_VERSION_OPTIMIZED (0x1<<0) 5313 #define FW_VERSION_OPTIMIZED_SHIFT 0 5314 #define FW_VERSION_BIG_ENDIEN (0x1<<1) 5315 #define FW_VERSION_BIG_ENDIEN_SHIFT 1 5316 #define FW_VERSION_CHIP_VERSION (0x3<<2) 5317 #define FW_VERSION_CHIP_VERSION_SHIFT 2 5318 #define __FW_VERSION_RESERVED (0xFFFFFFF<<4) 5319 #define __FW_VERSION_RESERVED_SHIFT 4 5320 }; 5321 5322 5323 /* GRE Tunnel Mode */ 5324 enum gre_tunnel_type { 5325 NVGRE_TUNNEL, 5326 L2GRE_TUNNEL, 5327 IPGRE_TUNNEL, 5328 MAX_GRE_TUNNEL_TYPE 5329 }; 5330 5331 /* 5332 * Dynamic Host-Coalescing - Driver(host) counters 5333 */ 5334 struct hc_dynamic_sb_drv_counters { 5335 u32 dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES]; 5336 }; 5337 5338 5339 /* 5340 * 2 bytes. configuration/state parameters for a single protocol index 5341 */ 5342 struct hc_index_data { 5343 #if defined(__BIG_ENDIAN) 5344 u8 flags; 5345 #define HC_INDEX_DATA_SM_ID (0x1<<0) 5346 #define HC_INDEX_DATA_SM_ID_SHIFT 0 5347 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1) 5348 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1 5349 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) 5350 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2 5351 #define HC_INDEX_DATA_RESERVE (0x1F<<3) 5352 #define HC_INDEX_DATA_RESERVE_SHIFT 3 5353 u8 timeout; 5354 #elif defined(__LITTLE_ENDIAN) 5355 u8 timeout; 5356 u8 flags; 5357 #define HC_INDEX_DATA_SM_ID (0x1<<0) 5358 #define HC_INDEX_DATA_SM_ID_SHIFT 0 5359 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1) 5360 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1 5361 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) 5362 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2 5363 #define HC_INDEX_DATA_RESERVE (0x1F<<3) 5364 #define HC_INDEX_DATA_RESERVE_SHIFT 3 5365 #endif 5366 }; 5367 5368 5369 /* 5370 * HC state-machine 5371 */ 5372 struct hc_status_block_sm { 5373 #if defined(__BIG_ENDIAN) 5374 u8 igu_seg_id; 5375 u8 igu_sb_id; 5376 u8 timer_value; 5377 u8 __flags; 5378 #elif defined(__LITTLE_ENDIAN) 5379 u8 __flags; 5380 u8 timer_value; 5381 u8 igu_sb_id; 5382 u8 igu_seg_id; 5383 #endif 5384 u32 time_to_expire; 5385 }; 5386 5387 /* 5388 * hold PCI identification variables- used in various places in firmware 5389 */ 5390 struct pci_entity { 5391 #if defined(__BIG_ENDIAN) 5392 u8 vf_valid; 5393 u8 vf_id; 5394 u8 vnic_id; 5395 u8 pf_id; 5396 #elif defined(__LITTLE_ENDIAN) 5397 u8 pf_id; 5398 u8 vnic_id; 5399 u8 vf_id; 5400 u8 vf_valid; 5401 #endif 5402 }; 5403 5404 /* 5405 * The fast-path status block meta-data, common to all chips 5406 */ 5407 struct hc_sb_data { 5408 struct regpair_native host_sb_addr; 5409 struct hc_status_block_sm state_machine[HC_SB_MAX_SM]; 5410 struct pci_entity p_func; 5411 #if defined(__BIG_ENDIAN) 5412 u8 rsrv0; 5413 u8 state; 5414 u8 dhc_qzone_id; 5415 u8 same_igu_sb_1b; 5416 #elif defined(__LITTLE_ENDIAN) 5417 u8 same_igu_sb_1b; 5418 u8 dhc_qzone_id; 5419 u8 state; 5420 u8 rsrv0; 5421 #endif 5422 struct regpair_native rsrv1[2]; 5423 }; 5424 5425 5426 /* 5427 * Segment types for host coaslescing 5428 */ 5429 enum hc_segment { 5430 HC_REGULAR_SEGMENT, 5431 HC_DEFAULT_SEGMENT, 5432 MAX_HC_SEGMENT 5433 }; 5434 5435 5436 /* 5437 * The fast-path status block meta-data 5438 */ 5439 struct hc_sp_status_block_data { 5440 struct regpair_native host_sb_addr; 5441 #if defined(__BIG_ENDIAN) 5442 u8 rsrv1; 5443 u8 state; 5444 u8 igu_seg_id; 5445 u8 igu_sb_id; 5446 #elif defined(__LITTLE_ENDIAN) 5447 u8 igu_sb_id; 5448 u8 igu_seg_id; 5449 u8 state; 5450 u8 rsrv1; 5451 #endif 5452 struct pci_entity p_func; 5453 }; 5454 5455 5456 /* 5457 * The fast-path status block meta-data 5458 */ 5459 struct hc_status_block_data_e1x { 5460 struct hc_index_data index_data[HC_SB_MAX_INDICES_E1X]; 5461 struct hc_sb_data common; 5462 }; 5463 5464 5465 /* 5466 * The fast-path status block meta-data 5467 */ 5468 struct hc_status_block_data_e2 { 5469 struct hc_index_data index_data[HC_SB_MAX_INDICES_E2]; 5470 struct hc_sb_data common; 5471 }; 5472 5473 5474 /* 5475 * IGU block operartion modes (in Everest2) 5476 */ 5477 enum igu_mode { 5478 HC_IGU_BC_MODE, 5479 HC_IGU_NBC_MODE, 5480 MAX_IGU_MODE 5481 }; 5482 5483 5484 /* 5485 * IP versions 5486 */ 5487 enum ip_ver { 5488 IP_V4, 5489 IP_V6, 5490 MAX_IP_VER 5491 }; 5492 5493 /* 5494 * Malicious VF error ID 5495 */ 5496 enum malicious_vf_error_id { 5497 MALICIOUS_VF_NO_ERROR, 5498 VF_PF_CHANNEL_NOT_READY, 5499 ETH_ILLEGAL_BD_LENGTHS, 5500 ETH_PACKET_TOO_SHORT, 5501 ETH_PAYLOAD_TOO_BIG, 5502 ETH_ILLEGAL_ETH_TYPE, 5503 ETH_ILLEGAL_LSO_HDR_LEN, 5504 ETH_TOO_MANY_BDS, 5505 ETH_ZERO_HDR_NBDS, 5506 ETH_START_BD_NOT_SET, 5507 ETH_ILLEGAL_PARSE_NBDS, 5508 ETH_IPV6_AND_CHECKSUM, 5509 ETH_VLAN_FLG_INCORRECT, 5510 ETH_ILLEGAL_LSO_MSS, 5511 ETH_TUNNEL_NOT_SUPPORTED, 5512 MAX_MALICIOUS_VF_ERROR_ID 5513 }; 5514 5515 /* 5516 * Multi-function modes 5517 */ 5518 enum mf_mode { 5519 SINGLE_FUNCTION, 5520 MULTI_FUNCTION_SD, 5521 MULTI_FUNCTION_SI, 5522 MULTI_FUNCTION_AFEX, 5523 MAX_MF_MODE 5524 }; 5525 5526 /* 5527 * Protocol-common statistics collected by the Tstorm (per pf) 5528 */ 5529 struct tstorm_per_pf_stats { 5530 struct regpair rcv_error_bytes; 5531 }; 5532 5533 /* 5534 * 5535 */ 5536 struct per_pf_stats { 5537 struct tstorm_per_pf_stats tstorm_pf_statistics; 5538 }; 5539 5540 5541 /* 5542 * Protocol-common statistics collected by the Tstorm (per port) 5543 */ 5544 struct tstorm_per_port_stats { 5545 __le32 mac_discard; 5546 __le32 mac_filter_discard; 5547 __le32 brb_truncate_discard; 5548 __le32 mf_tag_discard; 5549 __le32 packet_drop; 5550 __le32 reserved; 5551 }; 5552 5553 /* 5554 * 5555 */ 5556 struct per_port_stats { 5557 struct tstorm_per_port_stats tstorm_port_statistics; 5558 }; 5559 5560 5561 /* 5562 * Protocol-common statistics collected by the Tstorm (per client) 5563 */ 5564 struct tstorm_per_queue_stats { 5565 struct regpair rcv_ucast_bytes; 5566 __le32 rcv_ucast_pkts; 5567 __le32 checksum_discard; 5568 struct regpair rcv_bcast_bytes; 5569 __le32 rcv_bcast_pkts; 5570 __le32 pkts_too_big_discard; 5571 struct regpair rcv_mcast_bytes; 5572 __le32 rcv_mcast_pkts; 5573 __le32 ttl0_discard; 5574 __le16 no_buff_discard; 5575 __le16 reserved0; 5576 __le32 reserved1; 5577 }; 5578 5579 /* 5580 * Protocol-common statistics collected by the Ustorm (per client) 5581 */ 5582 struct ustorm_per_queue_stats { 5583 struct regpair ucast_no_buff_bytes; 5584 struct regpair mcast_no_buff_bytes; 5585 struct regpair bcast_no_buff_bytes; 5586 __le32 ucast_no_buff_pkts; 5587 __le32 mcast_no_buff_pkts; 5588 __le32 bcast_no_buff_pkts; 5589 __le32 coalesced_pkts; 5590 struct regpair coalesced_bytes; 5591 __le32 coalesced_events; 5592 __le32 coalesced_aborts; 5593 }; 5594 5595 /* 5596 * Protocol-common statistics collected by the Xstorm (per client) 5597 */ 5598 struct xstorm_per_queue_stats { 5599 struct regpair ucast_bytes_sent; 5600 struct regpair mcast_bytes_sent; 5601 struct regpair bcast_bytes_sent; 5602 __le32 ucast_pkts_sent; 5603 __le32 mcast_pkts_sent; 5604 __le32 bcast_pkts_sent; 5605 __le32 error_drop_pkts; 5606 }; 5607 5608 /* 5609 * 5610 */ 5611 struct per_queue_stats { 5612 struct tstorm_per_queue_stats tstorm_queue_statistics; 5613 struct ustorm_per_queue_stats ustorm_queue_statistics; 5614 struct xstorm_per_queue_stats xstorm_queue_statistics; 5615 }; 5616 5617 5618 /* 5619 * FW version stored in first line of pram 5620 */ 5621 struct pram_fw_version { 5622 u8 major; 5623 u8 minor; 5624 u8 revision; 5625 u8 engineering; 5626 u8 flags; 5627 #define PRAM_FW_VERSION_OPTIMIZED (0x1<<0) 5628 #define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0 5629 #define PRAM_FW_VERSION_STORM_ID (0x3<<1) 5630 #define PRAM_FW_VERSION_STORM_ID_SHIFT 1 5631 #define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3) 5632 #define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3 5633 #define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4) 5634 #define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4 5635 #define __PRAM_FW_VERSION_RESERVED0 (0x3<<6) 5636 #define __PRAM_FW_VERSION_RESERVED0_SHIFT 6 5637 }; 5638 5639 5640 /* 5641 * Ethernet slow path element 5642 */ 5643 union protocol_common_specific_data { 5644 u8 protocol_data[8]; 5645 struct regpair phy_address; 5646 struct regpair mac_config_addr; 5647 struct afex_vif_list_ramrod_data afex_vif_list_data; 5648 }; 5649 5650 /* 5651 * The send queue element 5652 */ 5653 struct protocol_common_spe { 5654 struct spe_hdr hdr; 5655 union protocol_common_specific_data data; 5656 }; 5657 5658 /* The data for the Set Timesync Ramrod */ 5659 struct set_timesync_ramrod_data { 5660 u8 drift_adjust_cmd; 5661 u8 offset_cmd; 5662 u8 add_sub_drift_adjust_value; 5663 u8 drift_adjust_value; 5664 u32 drift_adjust_period; 5665 struct regpair offset_delta; 5666 }; 5667 5668 /* 5669 * The send queue element 5670 */ 5671 struct slow_path_element { 5672 struct spe_hdr hdr; 5673 struct regpair protocol_data; 5674 }; 5675 5676 5677 /* 5678 * Protocol-common statistics counter 5679 */ 5680 struct stats_counter { 5681 __le16 xstats_counter; 5682 __le16 reserved0; 5683 __le32 reserved1; 5684 __le16 tstats_counter; 5685 __le16 reserved2; 5686 __le32 reserved3; 5687 __le16 ustats_counter; 5688 __le16 reserved4; 5689 __le32 reserved5; 5690 __le16 cstats_counter; 5691 __le16 reserved6; 5692 __le32 reserved7; 5693 }; 5694 5695 5696 /* 5697 * 5698 */ 5699 struct stats_query_entry { 5700 u8 kind; 5701 u8 index; 5702 __le16 funcID; 5703 __le32 reserved; 5704 struct regpair address; 5705 }; 5706 5707 /* 5708 * statistic command 5709 */ 5710 struct stats_query_cmd_group { 5711 struct stats_query_entry query[STATS_QUERY_CMD_COUNT]; 5712 }; 5713 5714 5715 /* 5716 * statistic command header 5717 */ 5718 struct stats_query_header { 5719 u8 cmd_num; 5720 u8 reserved0; 5721 __le16 drv_stats_counter; 5722 __le32 reserved1; 5723 struct regpair stats_counters_addrs; 5724 }; 5725 5726 5727 /* 5728 * Types of statistcis query entry 5729 */ 5730 enum stats_query_type { 5731 STATS_TYPE_QUEUE, 5732 STATS_TYPE_PORT, 5733 STATS_TYPE_PF, 5734 STATS_TYPE_TOE, 5735 STATS_TYPE_FCOE, 5736 MAX_STATS_QUERY_TYPE 5737 }; 5738 5739 5740 /* 5741 * Indicate of the function status block state 5742 */ 5743 enum status_block_state { 5744 SB_DISABLED, 5745 SB_ENABLED, 5746 SB_CLEANED, 5747 MAX_STATUS_BLOCK_STATE 5748 }; 5749 5750 5751 /* 5752 * Storm IDs (including attentions for IGU related enums) 5753 */ 5754 enum storm_id { 5755 USTORM_ID, 5756 CSTORM_ID, 5757 XSTORM_ID, 5758 TSTORM_ID, 5759 ATTENTION_ID, 5760 MAX_STORM_ID 5761 }; 5762 5763 5764 /* 5765 * Taffic types used in ETS and flow control algorithms 5766 */ 5767 enum traffic_type { 5768 LLFC_TRAFFIC_TYPE_NW, 5769 LLFC_TRAFFIC_TYPE_FCOE, 5770 LLFC_TRAFFIC_TYPE_ISCSI, 5771 MAX_TRAFFIC_TYPE 5772 }; 5773 5774 5775 /* 5776 * zone A per-queue data 5777 */ 5778 struct tstorm_queue_zone_data { 5779 struct regpair reserved[4]; 5780 }; 5781 5782 5783 /* 5784 * zone B per-VF data 5785 */ 5786 struct tstorm_vf_zone_data { 5787 struct regpair reserved; 5788 }; 5789 5790 /* Add or Subtract Value for Set Timesync Ramrod */ 5791 enum ts_add_sub_value { 5792 TS_SUB_VALUE, 5793 TS_ADD_VALUE, 5794 MAX_TS_ADD_SUB_VALUE 5795 }; 5796 5797 /* Drift-Adjust Commands for Set Timesync Ramrod */ 5798 enum ts_drift_adjust_cmd { 5799 TS_DRIFT_ADJUST_KEEP, 5800 TS_DRIFT_ADJUST_SET, 5801 TS_DRIFT_ADJUST_RESET, 5802 MAX_TS_DRIFT_ADJUST_CMD 5803 }; 5804 5805 /* Offset Commands for Set Timesync Ramrod */ 5806 enum ts_offset_cmd { 5807 TS_OFFSET_KEEP, 5808 TS_OFFSET_INC, 5809 TS_OFFSET_DEC, 5810 MAX_TS_OFFSET_CMD 5811 }; 5812 5813 /* Tunnel Mode */ 5814 enum tunnel_mode { 5815 TUNN_MODE_NONE, 5816 TUNN_MODE_VXLAN, 5817 TUNN_MODE_GRE, 5818 MAX_TUNNEL_MODE 5819 }; 5820 5821 /* zone A per-queue data */ 5822 struct ustorm_queue_zone_data { 5823 struct ustorm_eth_rx_producers eth_rx_producers; 5824 struct regpair reserved[3]; 5825 }; 5826 5827 5828 /* 5829 * zone B per-VF data 5830 */ 5831 struct ustorm_vf_zone_data { 5832 struct regpair reserved; 5833 }; 5834 5835 5836 /* 5837 * data per VF-PF channel 5838 */ 5839 struct vf_pf_channel_data { 5840 #if defined(__BIG_ENDIAN) 5841 u16 reserved0; 5842 u8 valid; 5843 u8 state; 5844 #elif defined(__LITTLE_ENDIAN) 5845 u8 state; 5846 u8 valid; 5847 u16 reserved0; 5848 #endif 5849 u32 reserved1; 5850 }; 5851 5852 5853 /* 5854 * State of VF-PF channel 5855 */ 5856 enum vf_pf_channel_state { 5857 VF_PF_CHANNEL_STATE_READY, 5858 VF_PF_CHANNEL_STATE_WAITING_FOR_ACK, 5859 MAX_VF_PF_CHANNEL_STATE 5860 }; 5861 5862 5863 /* 5864 * vif_list_rule_kind 5865 */ 5866 enum vif_list_rule_kind { 5867 VIF_LIST_RULE_SET, 5868 VIF_LIST_RULE_GET, 5869 VIF_LIST_RULE_CLEAR_ALL, 5870 VIF_LIST_RULE_CLEAR_FUNC, 5871 MAX_VIF_LIST_RULE_KIND 5872 }; 5873 5874 5875 /* 5876 * zone A per-queue data 5877 */ 5878 struct xstorm_queue_zone_data { 5879 struct regpair reserved[4]; 5880 }; 5881 5882 5883 /* 5884 * zone B per-VF data 5885 */ 5886 struct xstorm_vf_zone_data { 5887 struct regpair reserved; 5888 }; 5889 5890 #endif /* BNX2X_HSI_H */ 5891