1 /* bnx2x_ethtool.c: QLogic Everest network driver. 2 * 3 * Copyright (c) 2007-2013 Broadcom Corporation 4 * Copyright (c) 2014 QLogic Corporation 5 * All rights reserved 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation. 10 * 11 * Maintained by: Ariel Elior <ariel.elior@qlogic.com> 12 * Written by: Eliezer Tamir 13 * Based on code from Michael Chan's bnx2 driver 14 * UDP CSUM errata workaround by Arik Gendelman 15 * Slowpath and fastpath rework by Vladislav Zolotarov 16 * Statistics and Link management by Yitchak Gertner 17 * 18 */ 19 20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 21 22 #include <linux/ethtool.h> 23 #include <linux/netdevice.h> 24 #include <linux/types.h> 25 #include <linux/sched.h> 26 #include <linux/crc32.h> 27 #include "bnx2x.h" 28 #include "bnx2x_cmn.h" 29 #include "bnx2x_dump.h" 30 #include "bnx2x_init.h" 31 32 /* Note: in the format strings below %s is replaced by the queue-name which is 33 * either its index or 'fcoe' for the fcoe queue. Make sure the format string 34 * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2 35 */ 36 #define MAX_QUEUE_NAME_LEN 4 37 static const struct { 38 long offset; 39 int size; 40 char string[ETH_GSTRING_LEN]; 41 } bnx2x_q_stats_arr[] = { 42 /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" }, 43 { Q_STATS_OFFSET32(total_unicast_packets_received_hi), 44 8, "[%s]: rx_ucast_packets" }, 45 { Q_STATS_OFFSET32(total_multicast_packets_received_hi), 46 8, "[%s]: rx_mcast_packets" }, 47 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi), 48 8, "[%s]: rx_bcast_packets" }, 49 { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" }, 50 { Q_STATS_OFFSET32(rx_err_discard_pkt), 51 4, "[%s]: rx_phy_ip_err_discards"}, 52 { Q_STATS_OFFSET32(rx_skb_alloc_failed), 53 4, "[%s]: rx_skb_alloc_discard" }, 54 { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" }, 55 56 { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" }, 57 /* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi), 58 8, "[%s]: tx_ucast_packets" }, 59 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi), 60 8, "[%s]: tx_mcast_packets" }, 61 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi), 62 8, "[%s]: tx_bcast_packets" }, 63 { Q_STATS_OFFSET32(total_tpa_aggregations_hi), 64 8, "[%s]: tpa_aggregations" }, 65 { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi), 66 8, "[%s]: tpa_aggregated_frames"}, 67 { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"}, 68 { Q_STATS_OFFSET32(driver_filtered_tx_pkt), 69 4, "[%s]: driver_filtered_tx_pkt" } 70 }; 71 72 #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr) 73 74 static const struct { 75 long offset; 76 int size; 77 u32 flags; 78 #define STATS_FLAGS_PORT 1 79 #define STATS_FLAGS_FUNC 2 80 #define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT) 81 char string[ETH_GSTRING_LEN]; 82 } bnx2x_stats_arr[] = { 83 /* 1 */ { STATS_OFFSET32(total_bytes_received_hi), 84 8, STATS_FLAGS_BOTH, "rx_bytes" }, 85 { STATS_OFFSET32(error_bytes_received_hi), 86 8, STATS_FLAGS_BOTH, "rx_error_bytes" }, 87 { STATS_OFFSET32(total_unicast_packets_received_hi), 88 8, STATS_FLAGS_BOTH, "rx_ucast_packets" }, 89 { STATS_OFFSET32(total_multicast_packets_received_hi), 90 8, STATS_FLAGS_BOTH, "rx_mcast_packets" }, 91 { STATS_OFFSET32(total_broadcast_packets_received_hi), 92 8, STATS_FLAGS_BOTH, "rx_bcast_packets" }, 93 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi), 94 8, STATS_FLAGS_PORT, "rx_crc_errors" }, 95 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi), 96 8, STATS_FLAGS_PORT, "rx_align_errors" }, 97 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi), 98 8, STATS_FLAGS_PORT, "rx_undersize_packets" }, 99 { STATS_OFFSET32(etherstatsoverrsizepkts_hi), 100 8, STATS_FLAGS_PORT, "rx_oversize_packets" }, 101 /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi), 102 8, STATS_FLAGS_PORT, "rx_fragments" }, 103 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi), 104 8, STATS_FLAGS_PORT, "rx_jabbers" }, 105 { STATS_OFFSET32(no_buff_discard_hi), 106 8, STATS_FLAGS_BOTH, "rx_discards" }, 107 { STATS_OFFSET32(mac_filter_discard), 108 4, STATS_FLAGS_PORT, "rx_filtered_packets" }, 109 { STATS_OFFSET32(mf_tag_discard), 110 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" }, 111 { STATS_OFFSET32(pfc_frames_received_hi), 112 8, STATS_FLAGS_PORT, "pfc_frames_received" }, 113 { STATS_OFFSET32(pfc_frames_sent_hi), 114 8, STATS_FLAGS_PORT, "pfc_frames_sent" }, 115 { STATS_OFFSET32(brb_drop_hi), 116 8, STATS_FLAGS_PORT, "rx_brb_discard" }, 117 { STATS_OFFSET32(brb_truncate_hi), 118 8, STATS_FLAGS_PORT, "rx_brb_truncate" }, 119 { STATS_OFFSET32(pause_frames_received_hi), 120 8, STATS_FLAGS_PORT, "rx_pause_frames" }, 121 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi), 122 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" }, 123 { STATS_OFFSET32(nig_timer_max), 124 4, STATS_FLAGS_PORT, "rx_constant_pause_events" }, 125 /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt), 126 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"}, 127 { STATS_OFFSET32(rx_skb_alloc_failed), 128 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" }, 129 { STATS_OFFSET32(hw_csum_err), 130 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" }, 131 132 { STATS_OFFSET32(total_bytes_transmitted_hi), 133 8, STATS_FLAGS_BOTH, "tx_bytes" }, 134 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi), 135 8, STATS_FLAGS_PORT, "tx_error_bytes" }, 136 { STATS_OFFSET32(total_unicast_packets_transmitted_hi), 137 8, STATS_FLAGS_BOTH, "tx_ucast_packets" }, 138 { STATS_OFFSET32(total_multicast_packets_transmitted_hi), 139 8, STATS_FLAGS_BOTH, "tx_mcast_packets" }, 140 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi), 141 8, STATS_FLAGS_BOTH, "tx_bcast_packets" }, 142 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi), 143 8, STATS_FLAGS_PORT, "tx_mac_errors" }, 144 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi), 145 8, STATS_FLAGS_PORT, "tx_carrier_errors" }, 146 /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi), 147 8, STATS_FLAGS_PORT, "tx_single_collisions" }, 148 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi), 149 8, STATS_FLAGS_PORT, "tx_multi_collisions" }, 150 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi), 151 8, STATS_FLAGS_PORT, "tx_deferred" }, 152 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi), 153 8, STATS_FLAGS_PORT, "tx_excess_collisions" }, 154 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi), 155 8, STATS_FLAGS_PORT, "tx_late_collisions" }, 156 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi), 157 8, STATS_FLAGS_PORT, "tx_total_collisions" }, 158 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi), 159 8, STATS_FLAGS_PORT, "tx_64_byte_packets" }, 160 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi), 161 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" }, 162 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi), 163 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" }, 164 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi), 165 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" }, 166 /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi), 167 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" }, 168 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi), 169 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" }, 170 { STATS_OFFSET32(etherstatspktsover1522octets_hi), 171 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" }, 172 { STATS_OFFSET32(pause_frames_sent_hi), 173 8, STATS_FLAGS_PORT, "tx_pause_frames" }, 174 { STATS_OFFSET32(total_tpa_aggregations_hi), 175 8, STATS_FLAGS_FUNC, "tpa_aggregations" }, 176 { STATS_OFFSET32(total_tpa_aggregated_frames_hi), 177 8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"}, 178 { STATS_OFFSET32(total_tpa_bytes_hi), 179 8, STATS_FLAGS_FUNC, "tpa_bytes"}, 180 { STATS_OFFSET32(recoverable_error), 181 4, STATS_FLAGS_FUNC, "recoverable_errors" }, 182 { STATS_OFFSET32(unrecoverable_error), 183 4, STATS_FLAGS_FUNC, "unrecoverable_errors" }, 184 { STATS_OFFSET32(driver_filtered_tx_pkt), 185 4, STATS_FLAGS_FUNC, "driver_filtered_tx_pkt" }, 186 { STATS_OFFSET32(eee_tx_lpi), 187 4, STATS_FLAGS_PORT, "Tx LPI entry count"} 188 }; 189 190 #define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr) 191 192 static int bnx2x_get_port_type(struct bnx2x *bp) 193 { 194 int port_type; 195 u32 phy_idx = bnx2x_get_cur_phy_idx(bp); 196 switch (bp->link_params.phy[phy_idx].media_type) { 197 case ETH_PHY_SFPP_10G_FIBER: 198 case ETH_PHY_SFP_1G_FIBER: 199 case ETH_PHY_XFP_FIBER: 200 case ETH_PHY_KR: 201 case ETH_PHY_CX4: 202 port_type = PORT_FIBRE; 203 break; 204 case ETH_PHY_DA_TWINAX: 205 port_type = PORT_DA; 206 break; 207 case ETH_PHY_BASE_T: 208 port_type = PORT_TP; 209 break; 210 case ETH_PHY_NOT_PRESENT: 211 port_type = PORT_NONE; 212 break; 213 case ETH_PHY_UNSPECIFIED: 214 default: 215 port_type = PORT_OTHER; 216 break; 217 } 218 return port_type; 219 } 220 221 static int bnx2x_get_vf_settings(struct net_device *dev, 222 struct ethtool_cmd *cmd) 223 { 224 struct bnx2x *bp = netdev_priv(dev); 225 226 if (bp->state == BNX2X_STATE_OPEN) { 227 if (test_bit(BNX2X_LINK_REPORT_FD, 228 &bp->vf_link_vars.link_report_flags)) 229 cmd->duplex = DUPLEX_FULL; 230 else 231 cmd->duplex = DUPLEX_HALF; 232 233 ethtool_cmd_speed_set(cmd, bp->vf_link_vars.line_speed); 234 } else { 235 cmd->duplex = DUPLEX_UNKNOWN; 236 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN); 237 } 238 239 cmd->port = PORT_OTHER; 240 cmd->phy_address = 0; 241 cmd->transceiver = XCVR_INTERNAL; 242 cmd->autoneg = AUTONEG_DISABLE; 243 cmd->maxtxpkt = 0; 244 cmd->maxrxpkt = 0; 245 246 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" 247 " supported 0x%x advertising 0x%x speed %u\n" 248 " duplex %d port %d phy_address %d transceiver %d\n" 249 " autoneg %d maxtxpkt %d maxrxpkt %d\n", 250 cmd->cmd, cmd->supported, cmd->advertising, 251 ethtool_cmd_speed(cmd), 252 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver, 253 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt); 254 255 return 0; 256 } 257 258 static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 259 { 260 struct bnx2x *bp = netdev_priv(dev); 261 int cfg_idx = bnx2x_get_link_cfg_idx(bp); 262 u32 media_type; 263 264 /* Dual Media boards present all available port types */ 265 cmd->supported = bp->port.supported[cfg_idx] | 266 (bp->port.supported[cfg_idx ^ 1] & 267 (SUPPORTED_TP | SUPPORTED_FIBRE)); 268 cmd->advertising = bp->port.advertising[cfg_idx]; 269 media_type = bp->link_params.phy[bnx2x_get_cur_phy_idx(bp)].media_type; 270 if (media_type == ETH_PHY_SFP_1G_FIBER) { 271 cmd->supported &= ~(SUPPORTED_10000baseT_Full); 272 cmd->advertising &= ~(ADVERTISED_10000baseT_Full); 273 } 274 275 if ((bp->state == BNX2X_STATE_OPEN) && bp->link_vars.link_up && 276 !(bp->flags & MF_FUNC_DIS)) { 277 cmd->duplex = bp->link_vars.duplex; 278 279 if (IS_MF(bp) && !BP_NOMCP(bp)) 280 ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp)); 281 else 282 ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed); 283 } else { 284 cmd->duplex = DUPLEX_UNKNOWN; 285 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN); 286 } 287 288 cmd->port = bnx2x_get_port_type(bp); 289 290 cmd->phy_address = bp->mdio.prtad; 291 cmd->transceiver = XCVR_INTERNAL; 292 293 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) 294 cmd->autoneg = AUTONEG_ENABLE; 295 else 296 cmd->autoneg = AUTONEG_DISABLE; 297 298 /* Publish LP advertised speeds and FC */ 299 if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 300 u32 status = bp->link_vars.link_status; 301 302 cmd->lp_advertising |= ADVERTISED_Autoneg; 303 if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE) 304 cmd->lp_advertising |= ADVERTISED_Pause; 305 if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE) 306 cmd->lp_advertising |= ADVERTISED_Asym_Pause; 307 308 if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE) 309 cmd->lp_advertising |= ADVERTISED_10baseT_Half; 310 if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE) 311 cmd->lp_advertising |= ADVERTISED_10baseT_Full; 312 if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE) 313 cmd->lp_advertising |= ADVERTISED_100baseT_Half; 314 if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE) 315 cmd->lp_advertising |= ADVERTISED_100baseT_Full; 316 if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) 317 cmd->lp_advertising |= ADVERTISED_1000baseT_Half; 318 if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) { 319 if (media_type == ETH_PHY_KR) { 320 cmd->lp_advertising |= 321 ADVERTISED_1000baseKX_Full; 322 } else { 323 cmd->lp_advertising |= 324 ADVERTISED_1000baseT_Full; 325 } 326 } 327 if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE) 328 cmd->lp_advertising |= ADVERTISED_2500baseX_Full; 329 if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE) { 330 if (media_type == ETH_PHY_KR) { 331 cmd->lp_advertising |= 332 ADVERTISED_10000baseKR_Full; 333 } else { 334 cmd->lp_advertising |= 335 ADVERTISED_10000baseT_Full; 336 } 337 } 338 if (status & LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE) 339 cmd->lp_advertising |= ADVERTISED_20000baseKR2_Full; 340 } 341 342 cmd->maxtxpkt = 0; 343 cmd->maxrxpkt = 0; 344 345 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" 346 " supported 0x%x advertising 0x%x speed %u\n" 347 " duplex %d port %d phy_address %d transceiver %d\n" 348 " autoneg %d maxtxpkt %d maxrxpkt %d\n", 349 cmd->cmd, cmd->supported, cmd->advertising, 350 ethtool_cmd_speed(cmd), 351 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver, 352 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt); 353 354 return 0; 355 } 356 357 static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 358 { 359 struct bnx2x *bp = netdev_priv(dev); 360 u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config; 361 u32 speed, phy_idx; 362 363 if (IS_MF_SD(bp)) 364 return 0; 365 366 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" 367 " supported 0x%x advertising 0x%x speed %u\n" 368 " duplex %d port %d phy_address %d transceiver %d\n" 369 " autoneg %d maxtxpkt %d maxrxpkt %d\n", 370 cmd->cmd, cmd->supported, cmd->advertising, 371 ethtool_cmd_speed(cmd), 372 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver, 373 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt); 374 375 speed = ethtool_cmd_speed(cmd); 376 377 /* If received a request for an unknown duplex, assume full*/ 378 if (cmd->duplex == DUPLEX_UNKNOWN) 379 cmd->duplex = DUPLEX_FULL; 380 381 if (IS_MF_SI(bp)) { 382 u32 part; 383 u32 line_speed = bp->link_vars.line_speed; 384 385 /* use 10G if no link detected */ 386 if (!line_speed) 387 line_speed = 10000; 388 389 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) { 390 DP(BNX2X_MSG_ETHTOOL, 391 "To set speed BC %X or higher is required, please upgrade BC\n", 392 REQ_BC_VER_4_SET_MF_BW); 393 return -EINVAL; 394 } 395 396 part = (speed * 100) / line_speed; 397 398 if (line_speed < speed || !part) { 399 DP(BNX2X_MSG_ETHTOOL, 400 "Speed setting should be in a range from 1%% to 100%% of actual line speed\n"); 401 return -EINVAL; 402 } 403 404 if (bp->state != BNX2X_STATE_OPEN) 405 /* store value for following "load" */ 406 bp->pending_max = part; 407 else 408 bnx2x_update_max_mf_config(bp, part); 409 410 return 0; 411 } 412 413 cfg_idx = bnx2x_get_link_cfg_idx(bp); 414 old_multi_phy_config = bp->link_params.multi_phy_config; 415 if (cmd->port != bnx2x_get_port_type(bp)) { 416 switch (cmd->port) { 417 case PORT_TP: 418 if (!(bp->port.supported[0] & SUPPORTED_TP || 419 bp->port.supported[1] & SUPPORTED_TP)) { 420 DP(BNX2X_MSG_ETHTOOL, 421 "Unsupported port type\n"); 422 return -EINVAL; 423 } 424 bp->link_params.multi_phy_config &= 425 ~PORT_HW_CFG_PHY_SELECTION_MASK; 426 if (bp->link_params.multi_phy_config & 427 PORT_HW_CFG_PHY_SWAPPED_ENABLED) 428 bp->link_params.multi_phy_config |= 429 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; 430 else 431 bp->link_params.multi_phy_config |= 432 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; 433 break; 434 case PORT_FIBRE: 435 case PORT_DA: 436 case PORT_NONE: 437 if (!(bp->port.supported[0] & SUPPORTED_FIBRE || 438 bp->port.supported[1] & SUPPORTED_FIBRE)) { 439 DP(BNX2X_MSG_ETHTOOL, 440 "Unsupported port type\n"); 441 return -EINVAL; 442 } 443 bp->link_params.multi_phy_config &= 444 ~PORT_HW_CFG_PHY_SELECTION_MASK; 445 if (bp->link_params.multi_phy_config & 446 PORT_HW_CFG_PHY_SWAPPED_ENABLED) 447 bp->link_params.multi_phy_config |= 448 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; 449 else 450 bp->link_params.multi_phy_config |= 451 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; 452 break; 453 default: 454 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n"); 455 return -EINVAL; 456 } 457 } 458 /* Save new config in case command complete successfully */ 459 new_multi_phy_config = bp->link_params.multi_phy_config; 460 /* Get the new cfg_idx */ 461 cfg_idx = bnx2x_get_link_cfg_idx(bp); 462 /* Restore old config in case command failed */ 463 bp->link_params.multi_phy_config = old_multi_phy_config; 464 DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx); 465 466 if (cmd->autoneg == AUTONEG_ENABLE) { 467 u32 an_supported_speed = bp->port.supported[cfg_idx]; 468 if (bp->link_params.phy[EXT_PHY1].type == 469 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) 470 an_supported_speed |= (SUPPORTED_100baseT_Half | 471 SUPPORTED_100baseT_Full); 472 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) { 473 DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n"); 474 return -EINVAL; 475 } 476 477 /* advertise the requested speed and duplex if supported */ 478 if (cmd->advertising & ~an_supported_speed) { 479 DP(BNX2X_MSG_ETHTOOL, 480 "Advertisement parameters are not supported\n"); 481 return -EINVAL; 482 } 483 484 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG; 485 bp->link_params.req_duplex[cfg_idx] = cmd->duplex; 486 bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg | 487 cmd->advertising); 488 if (cmd->advertising) { 489 490 bp->link_params.speed_cap_mask[cfg_idx] = 0; 491 if (cmd->advertising & ADVERTISED_10baseT_Half) { 492 bp->link_params.speed_cap_mask[cfg_idx] |= 493 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF; 494 } 495 if (cmd->advertising & ADVERTISED_10baseT_Full) 496 bp->link_params.speed_cap_mask[cfg_idx] |= 497 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL; 498 499 if (cmd->advertising & ADVERTISED_100baseT_Full) 500 bp->link_params.speed_cap_mask[cfg_idx] |= 501 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL; 502 503 if (cmd->advertising & ADVERTISED_100baseT_Half) { 504 bp->link_params.speed_cap_mask[cfg_idx] |= 505 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF; 506 } 507 if (cmd->advertising & ADVERTISED_1000baseT_Half) { 508 bp->link_params.speed_cap_mask[cfg_idx] |= 509 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G; 510 } 511 if (cmd->advertising & (ADVERTISED_1000baseT_Full | 512 ADVERTISED_1000baseKX_Full)) 513 bp->link_params.speed_cap_mask[cfg_idx] |= 514 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G; 515 516 if (cmd->advertising & (ADVERTISED_10000baseT_Full | 517 ADVERTISED_10000baseKX4_Full | 518 ADVERTISED_10000baseKR_Full)) 519 bp->link_params.speed_cap_mask[cfg_idx] |= 520 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G; 521 522 if (cmd->advertising & ADVERTISED_20000baseKR2_Full) 523 bp->link_params.speed_cap_mask[cfg_idx] |= 524 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G; 525 } 526 } else { /* forced speed */ 527 /* advertise the requested speed and duplex if supported */ 528 switch (speed) { 529 case SPEED_10: 530 if (cmd->duplex == DUPLEX_FULL) { 531 if (!(bp->port.supported[cfg_idx] & 532 SUPPORTED_10baseT_Full)) { 533 DP(BNX2X_MSG_ETHTOOL, 534 "10M full not supported\n"); 535 return -EINVAL; 536 } 537 538 advertising = (ADVERTISED_10baseT_Full | 539 ADVERTISED_TP); 540 } else { 541 if (!(bp->port.supported[cfg_idx] & 542 SUPPORTED_10baseT_Half)) { 543 DP(BNX2X_MSG_ETHTOOL, 544 "10M half not supported\n"); 545 return -EINVAL; 546 } 547 548 advertising = (ADVERTISED_10baseT_Half | 549 ADVERTISED_TP); 550 } 551 break; 552 553 case SPEED_100: 554 if (cmd->duplex == DUPLEX_FULL) { 555 if (!(bp->port.supported[cfg_idx] & 556 SUPPORTED_100baseT_Full)) { 557 DP(BNX2X_MSG_ETHTOOL, 558 "100M full not supported\n"); 559 return -EINVAL; 560 } 561 562 advertising = (ADVERTISED_100baseT_Full | 563 ADVERTISED_TP); 564 } else { 565 if (!(bp->port.supported[cfg_idx] & 566 SUPPORTED_100baseT_Half)) { 567 DP(BNX2X_MSG_ETHTOOL, 568 "100M half not supported\n"); 569 return -EINVAL; 570 } 571 572 advertising = (ADVERTISED_100baseT_Half | 573 ADVERTISED_TP); 574 } 575 break; 576 577 case SPEED_1000: 578 if (cmd->duplex != DUPLEX_FULL) { 579 DP(BNX2X_MSG_ETHTOOL, 580 "1G half not supported\n"); 581 return -EINVAL; 582 } 583 584 if (bp->port.supported[cfg_idx] & 585 SUPPORTED_1000baseT_Full) { 586 advertising = (ADVERTISED_1000baseT_Full | 587 ADVERTISED_TP); 588 589 } else if (bp->port.supported[cfg_idx] & 590 SUPPORTED_1000baseKX_Full) { 591 advertising = ADVERTISED_1000baseKX_Full; 592 } else { 593 DP(BNX2X_MSG_ETHTOOL, 594 "1G full not supported\n"); 595 return -EINVAL; 596 } 597 598 break; 599 600 case SPEED_2500: 601 if (cmd->duplex != DUPLEX_FULL) { 602 DP(BNX2X_MSG_ETHTOOL, 603 "2.5G half not supported\n"); 604 return -EINVAL; 605 } 606 607 if (!(bp->port.supported[cfg_idx] 608 & SUPPORTED_2500baseX_Full)) { 609 DP(BNX2X_MSG_ETHTOOL, 610 "2.5G full not supported\n"); 611 return -EINVAL; 612 } 613 614 advertising = (ADVERTISED_2500baseX_Full | 615 ADVERTISED_TP); 616 break; 617 618 case SPEED_10000: 619 if (cmd->duplex != DUPLEX_FULL) { 620 DP(BNX2X_MSG_ETHTOOL, 621 "10G half not supported\n"); 622 return -EINVAL; 623 } 624 phy_idx = bnx2x_get_cur_phy_idx(bp); 625 if ((bp->port.supported[cfg_idx] & 626 SUPPORTED_10000baseT_Full) && 627 (bp->link_params.phy[phy_idx].media_type != 628 ETH_PHY_SFP_1G_FIBER)) { 629 advertising = (ADVERTISED_10000baseT_Full | 630 ADVERTISED_FIBRE); 631 } else if (bp->port.supported[cfg_idx] & 632 SUPPORTED_10000baseKR_Full) { 633 advertising = (ADVERTISED_10000baseKR_Full | 634 ADVERTISED_FIBRE); 635 } else { 636 DP(BNX2X_MSG_ETHTOOL, 637 "10G full not supported\n"); 638 return -EINVAL; 639 } 640 641 break; 642 643 default: 644 DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed); 645 return -EINVAL; 646 } 647 648 bp->link_params.req_line_speed[cfg_idx] = speed; 649 bp->link_params.req_duplex[cfg_idx] = cmd->duplex; 650 bp->port.advertising[cfg_idx] = advertising; 651 } 652 653 DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n" 654 " req_duplex %d advertising 0x%x\n", 655 bp->link_params.req_line_speed[cfg_idx], 656 bp->link_params.req_duplex[cfg_idx], 657 bp->port.advertising[cfg_idx]); 658 659 /* Set new config */ 660 bp->link_params.multi_phy_config = new_multi_phy_config; 661 if (netif_running(dev)) { 662 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 663 bnx2x_force_link_reset(bp); 664 bnx2x_link_set(bp); 665 } 666 667 return 0; 668 } 669 670 #define DUMP_ALL_PRESETS 0x1FFF 671 #define DUMP_MAX_PRESETS 13 672 673 static int __bnx2x_get_preset_regs_len(struct bnx2x *bp, u32 preset) 674 { 675 if (CHIP_IS_E1(bp)) 676 return dump_num_registers[0][preset-1]; 677 else if (CHIP_IS_E1H(bp)) 678 return dump_num_registers[1][preset-1]; 679 else if (CHIP_IS_E2(bp)) 680 return dump_num_registers[2][preset-1]; 681 else if (CHIP_IS_E3A0(bp)) 682 return dump_num_registers[3][preset-1]; 683 else if (CHIP_IS_E3B0(bp)) 684 return dump_num_registers[4][preset-1]; 685 else 686 return 0; 687 } 688 689 static int __bnx2x_get_regs_len(struct bnx2x *bp) 690 { 691 u32 preset_idx; 692 int regdump_len = 0; 693 694 /* Calculate the total preset regs length */ 695 for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) 696 regdump_len += __bnx2x_get_preset_regs_len(bp, preset_idx); 697 698 return regdump_len; 699 } 700 701 static int bnx2x_get_regs_len(struct net_device *dev) 702 { 703 struct bnx2x *bp = netdev_priv(dev); 704 int regdump_len = 0; 705 706 if (IS_VF(bp)) 707 return 0; 708 709 regdump_len = __bnx2x_get_regs_len(bp); 710 regdump_len *= 4; 711 regdump_len += sizeof(struct dump_header); 712 713 return regdump_len; 714 } 715 716 #define IS_E1_REG(chips) ((chips & DUMP_CHIP_E1) == DUMP_CHIP_E1) 717 #define IS_E1H_REG(chips) ((chips & DUMP_CHIP_E1H) == DUMP_CHIP_E1H) 718 #define IS_E2_REG(chips) ((chips & DUMP_CHIP_E2) == DUMP_CHIP_E2) 719 #define IS_E3A0_REG(chips) ((chips & DUMP_CHIP_E3A0) == DUMP_CHIP_E3A0) 720 #define IS_E3B0_REG(chips) ((chips & DUMP_CHIP_E3B0) == DUMP_CHIP_E3B0) 721 722 #define IS_REG_IN_PRESET(presets, idx) \ 723 ((presets & (1 << (idx-1))) == (1 << (idx-1))) 724 725 /******* Paged registers info selectors ********/ 726 static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp) 727 { 728 if (CHIP_IS_E2(bp)) 729 return page_vals_e2; 730 else if (CHIP_IS_E3(bp)) 731 return page_vals_e3; 732 else 733 return NULL; 734 } 735 736 static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp) 737 { 738 if (CHIP_IS_E2(bp)) 739 return PAGE_MODE_VALUES_E2; 740 else if (CHIP_IS_E3(bp)) 741 return PAGE_MODE_VALUES_E3; 742 else 743 return 0; 744 } 745 746 static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp) 747 { 748 if (CHIP_IS_E2(bp)) 749 return page_write_regs_e2; 750 else if (CHIP_IS_E3(bp)) 751 return page_write_regs_e3; 752 else 753 return NULL; 754 } 755 756 static u32 __bnx2x_get_page_write_num(struct bnx2x *bp) 757 { 758 if (CHIP_IS_E2(bp)) 759 return PAGE_WRITE_REGS_E2; 760 else if (CHIP_IS_E3(bp)) 761 return PAGE_WRITE_REGS_E3; 762 else 763 return 0; 764 } 765 766 static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp) 767 { 768 if (CHIP_IS_E2(bp)) 769 return page_read_regs_e2; 770 else if (CHIP_IS_E3(bp)) 771 return page_read_regs_e3; 772 else 773 return NULL; 774 } 775 776 static u32 __bnx2x_get_page_read_num(struct bnx2x *bp) 777 { 778 if (CHIP_IS_E2(bp)) 779 return PAGE_READ_REGS_E2; 780 else if (CHIP_IS_E3(bp)) 781 return PAGE_READ_REGS_E3; 782 else 783 return 0; 784 } 785 786 static bool bnx2x_is_reg_in_chip(struct bnx2x *bp, 787 const struct reg_addr *reg_info) 788 { 789 if (CHIP_IS_E1(bp)) 790 return IS_E1_REG(reg_info->chips); 791 else if (CHIP_IS_E1H(bp)) 792 return IS_E1H_REG(reg_info->chips); 793 else if (CHIP_IS_E2(bp)) 794 return IS_E2_REG(reg_info->chips); 795 else if (CHIP_IS_E3A0(bp)) 796 return IS_E3A0_REG(reg_info->chips); 797 else if (CHIP_IS_E3B0(bp)) 798 return IS_E3B0_REG(reg_info->chips); 799 else 800 return false; 801 } 802 803 static bool bnx2x_is_wreg_in_chip(struct bnx2x *bp, 804 const struct wreg_addr *wreg_info) 805 { 806 if (CHIP_IS_E1(bp)) 807 return IS_E1_REG(wreg_info->chips); 808 else if (CHIP_IS_E1H(bp)) 809 return IS_E1H_REG(wreg_info->chips); 810 else if (CHIP_IS_E2(bp)) 811 return IS_E2_REG(wreg_info->chips); 812 else if (CHIP_IS_E3A0(bp)) 813 return IS_E3A0_REG(wreg_info->chips); 814 else if (CHIP_IS_E3B0(bp)) 815 return IS_E3B0_REG(wreg_info->chips); 816 else 817 return false; 818 } 819 820 /** 821 * bnx2x_read_pages_regs - read "paged" registers 822 * 823 * @bp device handle 824 * @p output buffer 825 * 826 * Reads "paged" memories: memories that may only be read by first writing to a 827 * specific address ("write address") and then reading from a specific address 828 * ("read address"). There may be more than one write address per "page" and 829 * more than one read address per write address. 830 */ 831 static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p, u32 preset) 832 { 833 u32 i, j, k, n; 834 835 /* addresses of the paged registers */ 836 const u32 *page_addr = __bnx2x_get_page_addr_ar(bp); 837 /* number of paged registers */ 838 int num_pages = __bnx2x_get_page_reg_num(bp); 839 /* write addresses */ 840 const u32 *write_addr = __bnx2x_get_page_write_ar(bp); 841 /* number of write addresses */ 842 int write_num = __bnx2x_get_page_write_num(bp); 843 /* read addresses info */ 844 const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp); 845 /* number of read addresses */ 846 int read_num = __bnx2x_get_page_read_num(bp); 847 u32 addr, size; 848 849 for (i = 0; i < num_pages; i++) { 850 for (j = 0; j < write_num; j++) { 851 REG_WR(bp, write_addr[j], page_addr[i]); 852 853 for (k = 0; k < read_num; k++) { 854 if (IS_REG_IN_PRESET(read_addr[k].presets, 855 preset)) { 856 size = read_addr[k].size; 857 for (n = 0; n < size; n++) { 858 addr = read_addr[k].addr + n*4; 859 *p++ = REG_RD(bp, addr); 860 } 861 } 862 } 863 } 864 } 865 } 866 867 static int __bnx2x_get_preset_regs(struct bnx2x *bp, u32 *p, u32 preset) 868 { 869 u32 i, j, addr; 870 const struct wreg_addr *wreg_addr_p = NULL; 871 872 if (CHIP_IS_E1(bp)) 873 wreg_addr_p = &wreg_addr_e1; 874 else if (CHIP_IS_E1H(bp)) 875 wreg_addr_p = &wreg_addr_e1h; 876 else if (CHIP_IS_E2(bp)) 877 wreg_addr_p = &wreg_addr_e2; 878 else if (CHIP_IS_E3A0(bp)) 879 wreg_addr_p = &wreg_addr_e3; 880 else if (CHIP_IS_E3B0(bp)) 881 wreg_addr_p = &wreg_addr_e3b0; 882 883 /* Read the idle_chk registers */ 884 for (i = 0; i < IDLE_REGS_COUNT; i++) { 885 if (bnx2x_is_reg_in_chip(bp, &idle_reg_addrs[i]) && 886 IS_REG_IN_PRESET(idle_reg_addrs[i].presets, preset)) { 887 for (j = 0; j < idle_reg_addrs[i].size; j++) 888 *p++ = REG_RD(bp, idle_reg_addrs[i].addr + j*4); 889 } 890 } 891 892 /* Read the regular registers */ 893 for (i = 0; i < REGS_COUNT; i++) { 894 if (bnx2x_is_reg_in_chip(bp, ®_addrs[i]) && 895 IS_REG_IN_PRESET(reg_addrs[i].presets, preset)) { 896 for (j = 0; j < reg_addrs[i].size; j++) 897 *p++ = REG_RD(bp, reg_addrs[i].addr + j*4); 898 } 899 } 900 901 /* Read the CAM registers */ 902 if (bnx2x_is_wreg_in_chip(bp, wreg_addr_p) && 903 IS_REG_IN_PRESET(wreg_addr_p->presets, preset)) { 904 for (i = 0; i < wreg_addr_p->size; i++) { 905 *p++ = REG_RD(bp, wreg_addr_p->addr + i*4); 906 907 /* In case of wreg_addr register, read additional 908 registers from read_regs array 909 */ 910 for (j = 0; j < wreg_addr_p->read_regs_count; j++) { 911 addr = *(wreg_addr_p->read_regs); 912 *p++ = REG_RD(bp, addr + j*4); 913 } 914 } 915 } 916 917 /* Paged registers are supported in E2 & E3 only */ 918 if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) { 919 /* Read "paged" registers */ 920 bnx2x_read_pages_regs(bp, p, preset); 921 } 922 923 return 0; 924 } 925 926 static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p) 927 { 928 u32 preset_idx; 929 930 /* Read all registers, by reading all preset registers */ 931 for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) { 932 /* Skip presets with IOR */ 933 if ((preset_idx == 2) || 934 (preset_idx == 5) || 935 (preset_idx == 8) || 936 (preset_idx == 11)) 937 continue; 938 __bnx2x_get_preset_regs(bp, p, preset_idx); 939 p += __bnx2x_get_preset_regs_len(bp, preset_idx); 940 } 941 } 942 943 static void bnx2x_get_regs(struct net_device *dev, 944 struct ethtool_regs *regs, void *_p) 945 { 946 u32 *p = _p; 947 struct bnx2x *bp = netdev_priv(dev); 948 struct dump_header dump_hdr = {0}; 949 950 regs->version = 2; 951 memset(p, 0, regs->len); 952 953 if (!netif_running(bp->dev)) 954 return; 955 956 /* Disable parity attentions as long as following dump may 957 * cause false alarms by reading never written registers. We 958 * will re-enable parity attentions right after the dump. 959 */ 960 961 bnx2x_disable_blocks_parity(bp); 962 963 dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1; 964 dump_hdr.preset = DUMP_ALL_PRESETS; 965 dump_hdr.version = BNX2X_DUMP_VERSION; 966 967 /* dump_meta_data presents OR of CHIP and PATH. */ 968 if (CHIP_IS_E1(bp)) { 969 dump_hdr.dump_meta_data = DUMP_CHIP_E1; 970 } else if (CHIP_IS_E1H(bp)) { 971 dump_hdr.dump_meta_data = DUMP_CHIP_E1H; 972 } else if (CHIP_IS_E2(bp)) { 973 dump_hdr.dump_meta_data = DUMP_CHIP_E2 | 974 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 975 } else if (CHIP_IS_E3A0(bp)) { 976 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 | 977 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 978 } else if (CHIP_IS_E3B0(bp)) { 979 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 | 980 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 981 } 982 983 memcpy(p, &dump_hdr, sizeof(struct dump_header)); 984 p += dump_hdr.header_size + 1; 985 986 /* Actually read the registers */ 987 __bnx2x_get_regs(bp, p); 988 989 /* Re-enable parity attentions */ 990 bnx2x_clear_blocks_parity(bp); 991 bnx2x_enable_blocks_parity(bp); 992 } 993 994 static int bnx2x_get_preset_regs_len(struct net_device *dev, u32 preset) 995 { 996 struct bnx2x *bp = netdev_priv(dev); 997 int regdump_len = 0; 998 999 regdump_len = __bnx2x_get_preset_regs_len(bp, preset); 1000 regdump_len *= 4; 1001 regdump_len += sizeof(struct dump_header); 1002 1003 return regdump_len; 1004 } 1005 1006 static int bnx2x_set_dump(struct net_device *dev, struct ethtool_dump *val) 1007 { 1008 struct bnx2x *bp = netdev_priv(dev); 1009 1010 /* Use the ethtool_dump "flag" field as the dump preset index */ 1011 if (val->flag < 1 || val->flag > DUMP_MAX_PRESETS) 1012 return -EINVAL; 1013 1014 bp->dump_preset_idx = val->flag; 1015 return 0; 1016 } 1017 1018 static int bnx2x_get_dump_flag(struct net_device *dev, 1019 struct ethtool_dump *dump) 1020 { 1021 struct bnx2x *bp = netdev_priv(dev); 1022 1023 dump->version = BNX2X_DUMP_VERSION; 1024 dump->flag = bp->dump_preset_idx; 1025 /* Calculate the requested preset idx length */ 1026 dump->len = bnx2x_get_preset_regs_len(dev, bp->dump_preset_idx); 1027 DP(BNX2X_MSG_ETHTOOL, "Get dump preset %d length=%d\n", 1028 bp->dump_preset_idx, dump->len); 1029 return 0; 1030 } 1031 1032 static int bnx2x_get_dump_data(struct net_device *dev, 1033 struct ethtool_dump *dump, 1034 void *buffer) 1035 { 1036 u32 *p = buffer; 1037 struct bnx2x *bp = netdev_priv(dev); 1038 struct dump_header dump_hdr = {0}; 1039 1040 /* Disable parity attentions as long as following dump may 1041 * cause false alarms by reading never written registers. We 1042 * will re-enable parity attentions right after the dump. 1043 */ 1044 1045 bnx2x_disable_blocks_parity(bp); 1046 1047 dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1; 1048 dump_hdr.preset = bp->dump_preset_idx; 1049 dump_hdr.version = BNX2X_DUMP_VERSION; 1050 1051 DP(BNX2X_MSG_ETHTOOL, "Get dump data of preset %d\n", dump_hdr.preset); 1052 1053 /* dump_meta_data presents OR of CHIP and PATH. */ 1054 if (CHIP_IS_E1(bp)) { 1055 dump_hdr.dump_meta_data = DUMP_CHIP_E1; 1056 } else if (CHIP_IS_E1H(bp)) { 1057 dump_hdr.dump_meta_data = DUMP_CHIP_E1H; 1058 } else if (CHIP_IS_E2(bp)) { 1059 dump_hdr.dump_meta_data = DUMP_CHIP_E2 | 1060 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 1061 } else if (CHIP_IS_E3A0(bp)) { 1062 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 | 1063 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 1064 } else if (CHIP_IS_E3B0(bp)) { 1065 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 | 1066 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0); 1067 } 1068 1069 memcpy(p, &dump_hdr, sizeof(struct dump_header)); 1070 p += dump_hdr.header_size + 1; 1071 1072 /* Actually read the registers */ 1073 __bnx2x_get_preset_regs(bp, p, dump_hdr.preset); 1074 1075 /* Re-enable parity attentions */ 1076 bnx2x_clear_blocks_parity(bp); 1077 bnx2x_enable_blocks_parity(bp); 1078 1079 return 0; 1080 } 1081 1082 static void bnx2x_get_drvinfo(struct net_device *dev, 1083 struct ethtool_drvinfo *info) 1084 { 1085 struct bnx2x *bp = netdev_priv(dev); 1086 1087 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); 1088 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version)); 1089 1090 bnx2x_fill_fw_str(bp, info->fw_version, sizeof(info->fw_version)); 1091 1092 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info)); 1093 info->n_stats = BNX2X_NUM_STATS; 1094 info->testinfo_len = BNX2X_NUM_TESTS(bp); 1095 info->eedump_len = bp->common.flash_size; 1096 info->regdump_len = bnx2x_get_regs_len(dev); 1097 } 1098 1099 static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1100 { 1101 struct bnx2x *bp = netdev_priv(dev); 1102 1103 if (bp->flags & NO_WOL_FLAG) { 1104 wol->supported = 0; 1105 wol->wolopts = 0; 1106 } else { 1107 wol->supported = WAKE_MAGIC; 1108 if (bp->wol) 1109 wol->wolopts = WAKE_MAGIC; 1110 else 1111 wol->wolopts = 0; 1112 } 1113 memset(&wol->sopass, 0, sizeof(wol->sopass)); 1114 } 1115 1116 static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1117 { 1118 struct bnx2x *bp = netdev_priv(dev); 1119 1120 if (wol->wolopts & ~WAKE_MAGIC) { 1121 DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n"); 1122 return -EINVAL; 1123 } 1124 1125 if (wol->wolopts & WAKE_MAGIC) { 1126 if (bp->flags & NO_WOL_FLAG) { 1127 DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n"); 1128 return -EINVAL; 1129 } 1130 bp->wol = 1; 1131 } else 1132 bp->wol = 0; 1133 1134 if (SHMEM2_HAS(bp, curr_cfg)) 1135 SHMEM2_WR(bp, curr_cfg, CURR_CFG_MET_OS); 1136 1137 return 0; 1138 } 1139 1140 static u32 bnx2x_get_msglevel(struct net_device *dev) 1141 { 1142 struct bnx2x *bp = netdev_priv(dev); 1143 1144 return bp->msg_enable; 1145 } 1146 1147 static void bnx2x_set_msglevel(struct net_device *dev, u32 level) 1148 { 1149 struct bnx2x *bp = netdev_priv(dev); 1150 1151 if (capable(CAP_NET_ADMIN)) { 1152 /* dump MCP trace */ 1153 if (IS_PF(bp) && (level & BNX2X_MSG_MCP)) 1154 bnx2x_fw_dump_lvl(bp, KERN_INFO); 1155 bp->msg_enable = level; 1156 } 1157 } 1158 1159 static int bnx2x_nway_reset(struct net_device *dev) 1160 { 1161 struct bnx2x *bp = netdev_priv(dev); 1162 1163 if (!bp->port.pmf) 1164 return 0; 1165 1166 if (netif_running(dev)) { 1167 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 1168 bnx2x_force_link_reset(bp); 1169 bnx2x_link_set(bp); 1170 } 1171 1172 return 0; 1173 } 1174 1175 static u32 bnx2x_get_link(struct net_device *dev) 1176 { 1177 struct bnx2x *bp = netdev_priv(dev); 1178 1179 if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN)) 1180 return 0; 1181 1182 if (IS_VF(bp)) 1183 return !test_bit(BNX2X_LINK_REPORT_LINK_DOWN, 1184 &bp->vf_link_vars.link_report_flags); 1185 1186 return bp->link_vars.link_up; 1187 } 1188 1189 static int bnx2x_get_eeprom_len(struct net_device *dev) 1190 { 1191 struct bnx2x *bp = netdev_priv(dev); 1192 1193 return bp->common.flash_size; 1194 } 1195 1196 /* Per pf misc lock must be acquired before the per port mcp lock. Otherwise, 1197 * had we done things the other way around, if two pfs from the same port would 1198 * attempt to access nvram at the same time, we could run into a scenario such 1199 * as: 1200 * pf A takes the port lock. 1201 * pf B succeeds in taking the same lock since they are from the same port. 1202 * pf A takes the per pf misc lock. Performs eeprom access. 1203 * pf A finishes. Unlocks the per pf misc lock. 1204 * Pf B takes the lock and proceeds to perform it's own access. 1205 * pf A unlocks the per port lock, while pf B is still working (!). 1206 * mcp takes the per port lock and corrupts pf B's access (and/or has it's own 1207 * access corrupted by pf B) 1208 */ 1209 static int bnx2x_acquire_nvram_lock(struct bnx2x *bp) 1210 { 1211 int port = BP_PORT(bp); 1212 int count, i; 1213 u32 val; 1214 1215 /* acquire HW lock: protect against other PFs in PF Direct Assignment */ 1216 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM); 1217 1218 /* adjust timeout for emulation/FPGA */ 1219 count = BNX2X_NVRAM_TIMEOUT_COUNT; 1220 if (CHIP_REV_IS_SLOW(bp)) 1221 count *= 100; 1222 1223 /* request access to nvram interface */ 1224 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, 1225 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port)); 1226 1227 for (i = 0; i < count*10; i++) { 1228 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); 1229 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) 1230 break; 1231 1232 udelay(5); 1233 } 1234 1235 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) { 1236 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1237 "cannot get access to nvram interface\n"); 1238 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM); 1239 return -EBUSY; 1240 } 1241 1242 return 0; 1243 } 1244 1245 static int bnx2x_release_nvram_lock(struct bnx2x *bp) 1246 { 1247 int port = BP_PORT(bp); 1248 int count, i; 1249 u32 val; 1250 1251 /* adjust timeout for emulation/FPGA */ 1252 count = BNX2X_NVRAM_TIMEOUT_COUNT; 1253 if (CHIP_REV_IS_SLOW(bp)) 1254 count *= 100; 1255 1256 /* relinquish nvram interface */ 1257 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, 1258 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port)); 1259 1260 for (i = 0; i < count*10; i++) { 1261 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); 1262 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) 1263 break; 1264 1265 udelay(5); 1266 } 1267 1268 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) { 1269 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1270 "cannot free access to nvram interface\n"); 1271 return -EBUSY; 1272 } 1273 1274 /* release HW lock: protect against other PFs in PF Direct Assignment */ 1275 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM); 1276 return 0; 1277 } 1278 1279 static void bnx2x_enable_nvram_access(struct bnx2x *bp) 1280 { 1281 u32 val; 1282 1283 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE); 1284 1285 /* enable both bits, even on read */ 1286 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE, 1287 (val | MCPR_NVM_ACCESS_ENABLE_EN | 1288 MCPR_NVM_ACCESS_ENABLE_WR_EN)); 1289 } 1290 1291 static void bnx2x_disable_nvram_access(struct bnx2x *bp) 1292 { 1293 u32 val; 1294 1295 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE); 1296 1297 /* disable both bits, even after read */ 1298 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE, 1299 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN | 1300 MCPR_NVM_ACCESS_ENABLE_WR_EN))); 1301 } 1302 1303 static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val, 1304 u32 cmd_flags) 1305 { 1306 int count, i, rc; 1307 u32 val; 1308 1309 /* build the command word */ 1310 cmd_flags |= MCPR_NVM_COMMAND_DOIT; 1311 1312 /* need to clear DONE bit separately */ 1313 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); 1314 1315 /* address of the NVRAM to read from */ 1316 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR, 1317 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE)); 1318 1319 /* issue a read command */ 1320 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); 1321 1322 /* adjust timeout for emulation/FPGA */ 1323 count = BNX2X_NVRAM_TIMEOUT_COUNT; 1324 if (CHIP_REV_IS_SLOW(bp)) 1325 count *= 100; 1326 1327 /* wait for completion */ 1328 *ret_val = 0; 1329 rc = -EBUSY; 1330 for (i = 0; i < count; i++) { 1331 udelay(5); 1332 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND); 1333 1334 if (val & MCPR_NVM_COMMAND_DONE) { 1335 val = REG_RD(bp, MCP_REG_MCPR_NVM_READ); 1336 /* we read nvram data in cpu order 1337 * but ethtool sees it as an array of bytes 1338 * converting to big-endian will do the work 1339 */ 1340 *ret_val = cpu_to_be32(val); 1341 rc = 0; 1342 break; 1343 } 1344 } 1345 if (rc == -EBUSY) 1346 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1347 "nvram read timeout expired\n"); 1348 return rc; 1349 } 1350 1351 int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf, 1352 int buf_size) 1353 { 1354 int rc; 1355 u32 cmd_flags; 1356 __be32 val; 1357 1358 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { 1359 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1360 "Invalid parameter: offset 0x%x buf_size 0x%x\n", 1361 offset, buf_size); 1362 return -EINVAL; 1363 } 1364 1365 if (offset + buf_size > bp->common.flash_size) { 1366 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1367 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", 1368 offset, buf_size, bp->common.flash_size); 1369 return -EINVAL; 1370 } 1371 1372 /* request access to nvram interface */ 1373 rc = bnx2x_acquire_nvram_lock(bp); 1374 if (rc) 1375 return rc; 1376 1377 /* enable access to nvram interface */ 1378 bnx2x_enable_nvram_access(bp); 1379 1380 /* read the first word(s) */ 1381 cmd_flags = MCPR_NVM_COMMAND_FIRST; 1382 while ((buf_size > sizeof(u32)) && (rc == 0)) { 1383 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags); 1384 memcpy(ret_buf, &val, 4); 1385 1386 /* advance to the next dword */ 1387 offset += sizeof(u32); 1388 ret_buf += sizeof(u32); 1389 buf_size -= sizeof(u32); 1390 cmd_flags = 0; 1391 } 1392 1393 if (rc == 0) { 1394 cmd_flags |= MCPR_NVM_COMMAND_LAST; 1395 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags); 1396 memcpy(ret_buf, &val, 4); 1397 } 1398 1399 /* disable access to nvram interface */ 1400 bnx2x_disable_nvram_access(bp); 1401 bnx2x_release_nvram_lock(bp); 1402 1403 return rc; 1404 } 1405 1406 static int bnx2x_nvram_read32(struct bnx2x *bp, u32 offset, u32 *buf, 1407 int buf_size) 1408 { 1409 int rc; 1410 1411 rc = bnx2x_nvram_read(bp, offset, (u8 *)buf, buf_size); 1412 1413 if (!rc) { 1414 __be32 *be = (__be32 *)buf; 1415 1416 while ((buf_size -= 4) >= 0) 1417 *buf++ = be32_to_cpu(*be++); 1418 } 1419 1420 return rc; 1421 } 1422 1423 static bool bnx2x_is_nvm_accessible(struct bnx2x *bp) 1424 { 1425 int rc = 1; 1426 u16 pm = 0; 1427 struct net_device *dev = pci_get_drvdata(bp->pdev); 1428 1429 if (bp->pdev->pm_cap) 1430 rc = pci_read_config_word(bp->pdev, 1431 bp->pdev->pm_cap + PCI_PM_CTRL, &pm); 1432 1433 if ((rc && !netif_running(dev)) || 1434 (!rc && ((pm & PCI_PM_CTRL_STATE_MASK) != (__force u16)PCI_D0))) 1435 return false; 1436 1437 return true; 1438 } 1439 1440 static int bnx2x_get_eeprom(struct net_device *dev, 1441 struct ethtool_eeprom *eeprom, u8 *eebuf) 1442 { 1443 struct bnx2x *bp = netdev_priv(dev); 1444 1445 if (!bnx2x_is_nvm_accessible(bp)) { 1446 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1447 "cannot access eeprom when the interface is down\n"); 1448 return -EAGAIN; 1449 } 1450 1451 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n" 1452 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n", 1453 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset, 1454 eeprom->len, eeprom->len); 1455 1456 /* parameters already validated in ethtool_get_eeprom */ 1457 1458 return bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len); 1459 } 1460 1461 static int bnx2x_get_module_eeprom(struct net_device *dev, 1462 struct ethtool_eeprom *ee, 1463 u8 *data) 1464 { 1465 struct bnx2x *bp = netdev_priv(dev); 1466 int rc = -EINVAL, phy_idx; 1467 u8 *user_data = data; 1468 unsigned int start_addr = ee->offset, xfer_size = 0; 1469 1470 if (!bnx2x_is_nvm_accessible(bp)) { 1471 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1472 "cannot access eeprom when the interface is down\n"); 1473 return -EAGAIN; 1474 } 1475 1476 phy_idx = bnx2x_get_cur_phy_idx(bp); 1477 1478 /* Read A0 section */ 1479 if (start_addr < ETH_MODULE_SFF_8079_LEN) { 1480 /* Limit transfer size to the A0 section boundary */ 1481 if (start_addr + ee->len > ETH_MODULE_SFF_8079_LEN) 1482 xfer_size = ETH_MODULE_SFF_8079_LEN - start_addr; 1483 else 1484 xfer_size = ee->len; 1485 bnx2x_acquire_phy_lock(bp); 1486 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], 1487 &bp->link_params, 1488 I2C_DEV_ADDR_A0, 1489 start_addr, 1490 xfer_size, 1491 user_data); 1492 bnx2x_release_phy_lock(bp); 1493 if (rc) { 1494 DP(BNX2X_MSG_ETHTOOL, "Failed reading A0 section\n"); 1495 1496 return -EINVAL; 1497 } 1498 user_data += xfer_size; 1499 start_addr += xfer_size; 1500 } 1501 1502 /* Read A2 section */ 1503 if ((start_addr >= ETH_MODULE_SFF_8079_LEN) && 1504 (start_addr < ETH_MODULE_SFF_8472_LEN)) { 1505 xfer_size = ee->len - xfer_size; 1506 /* Limit transfer size to the A2 section boundary */ 1507 if (start_addr + xfer_size > ETH_MODULE_SFF_8472_LEN) 1508 xfer_size = ETH_MODULE_SFF_8472_LEN - start_addr; 1509 start_addr -= ETH_MODULE_SFF_8079_LEN; 1510 bnx2x_acquire_phy_lock(bp); 1511 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], 1512 &bp->link_params, 1513 I2C_DEV_ADDR_A2, 1514 start_addr, 1515 xfer_size, 1516 user_data); 1517 bnx2x_release_phy_lock(bp); 1518 if (rc) { 1519 DP(BNX2X_MSG_ETHTOOL, "Failed reading A2 section\n"); 1520 return -EINVAL; 1521 } 1522 } 1523 return rc; 1524 } 1525 1526 static int bnx2x_get_module_info(struct net_device *dev, 1527 struct ethtool_modinfo *modinfo) 1528 { 1529 struct bnx2x *bp = netdev_priv(dev); 1530 int phy_idx, rc; 1531 u8 sff8472_comp, diag_type; 1532 1533 if (!bnx2x_is_nvm_accessible(bp)) { 1534 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1535 "cannot access eeprom when the interface is down\n"); 1536 return -EAGAIN; 1537 } 1538 phy_idx = bnx2x_get_cur_phy_idx(bp); 1539 bnx2x_acquire_phy_lock(bp); 1540 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], 1541 &bp->link_params, 1542 I2C_DEV_ADDR_A0, 1543 SFP_EEPROM_SFF_8472_COMP_ADDR, 1544 SFP_EEPROM_SFF_8472_COMP_SIZE, 1545 &sff8472_comp); 1546 bnx2x_release_phy_lock(bp); 1547 if (rc) { 1548 DP(BNX2X_MSG_ETHTOOL, "Failed reading SFF-8472 comp field\n"); 1549 return -EINVAL; 1550 } 1551 1552 bnx2x_acquire_phy_lock(bp); 1553 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx], 1554 &bp->link_params, 1555 I2C_DEV_ADDR_A0, 1556 SFP_EEPROM_DIAG_TYPE_ADDR, 1557 SFP_EEPROM_DIAG_TYPE_SIZE, 1558 &diag_type); 1559 bnx2x_release_phy_lock(bp); 1560 if (rc) { 1561 DP(BNX2X_MSG_ETHTOOL, "Failed reading Diag Type field\n"); 1562 return -EINVAL; 1563 } 1564 1565 if (!sff8472_comp || 1566 (diag_type & SFP_EEPROM_DIAG_ADDR_CHANGE_REQ)) { 1567 modinfo->type = ETH_MODULE_SFF_8079; 1568 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN; 1569 } else { 1570 modinfo->type = ETH_MODULE_SFF_8472; 1571 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 1572 } 1573 return 0; 1574 } 1575 1576 static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val, 1577 u32 cmd_flags) 1578 { 1579 int count, i, rc; 1580 1581 /* build the command word */ 1582 cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR; 1583 1584 /* need to clear DONE bit separately */ 1585 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); 1586 1587 /* write the data */ 1588 REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val); 1589 1590 /* address of the NVRAM to write to */ 1591 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR, 1592 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE)); 1593 1594 /* issue the write command */ 1595 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); 1596 1597 /* adjust timeout for emulation/FPGA */ 1598 count = BNX2X_NVRAM_TIMEOUT_COUNT; 1599 if (CHIP_REV_IS_SLOW(bp)) 1600 count *= 100; 1601 1602 /* wait for completion */ 1603 rc = -EBUSY; 1604 for (i = 0; i < count; i++) { 1605 udelay(5); 1606 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND); 1607 if (val & MCPR_NVM_COMMAND_DONE) { 1608 rc = 0; 1609 break; 1610 } 1611 } 1612 1613 if (rc == -EBUSY) 1614 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1615 "nvram write timeout expired\n"); 1616 return rc; 1617 } 1618 1619 #define BYTE_OFFSET(offset) (8 * (offset & 0x03)) 1620 1621 static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf, 1622 int buf_size) 1623 { 1624 int rc; 1625 u32 cmd_flags, align_offset, val; 1626 __be32 val_be; 1627 1628 if (offset + buf_size > bp->common.flash_size) { 1629 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1630 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", 1631 offset, buf_size, bp->common.flash_size); 1632 return -EINVAL; 1633 } 1634 1635 /* request access to nvram interface */ 1636 rc = bnx2x_acquire_nvram_lock(bp); 1637 if (rc) 1638 return rc; 1639 1640 /* enable access to nvram interface */ 1641 bnx2x_enable_nvram_access(bp); 1642 1643 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST); 1644 align_offset = (offset & ~0x03); 1645 rc = bnx2x_nvram_read_dword(bp, align_offset, &val_be, cmd_flags); 1646 1647 if (rc == 0) { 1648 /* nvram data is returned as an array of bytes 1649 * convert it back to cpu order 1650 */ 1651 val = be32_to_cpu(val_be); 1652 1653 val &= ~le32_to_cpu((__force __le32) 1654 (0xff << BYTE_OFFSET(offset))); 1655 val |= le32_to_cpu((__force __le32) 1656 (*data_buf << BYTE_OFFSET(offset))); 1657 1658 rc = bnx2x_nvram_write_dword(bp, align_offset, val, 1659 cmd_flags); 1660 } 1661 1662 /* disable access to nvram interface */ 1663 bnx2x_disable_nvram_access(bp); 1664 bnx2x_release_nvram_lock(bp); 1665 1666 return rc; 1667 } 1668 1669 static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf, 1670 int buf_size) 1671 { 1672 int rc; 1673 u32 cmd_flags; 1674 u32 val; 1675 u32 written_so_far; 1676 1677 if (buf_size == 1) /* ethtool */ 1678 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size); 1679 1680 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { 1681 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1682 "Invalid parameter: offset 0x%x buf_size 0x%x\n", 1683 offset, buf_size); 1684 return -EINVAL; 1685 } 1686 1687 if (offset + buf_size > bp->common.flash_size) { 1688 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1689 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", 1690 offset, buf_size, bp->common.flash_size); 1691 return -EINVAL; 1692 } 1693 1694 /* request access to nvram interface */ 1695 rc = bnx2x_acquire_nvram_lock(bp); 1696 if (rc) 1697 return rc; 1698 1699 /* enable access to nvram interface */ 1700 bnx2x_enable_nvram_access(bp); 1701 1702 written_so_far = 0; 1703 cmd_flags = MCPR_NVM_COMMAND_FIRST; 1704 while ((written_so_far < buf_size) && (rc == 0)) { 1705 if (written_so_far == (buf_size - sizeof(u32))) 1706 cmd_flags |= MCPR_NVM_COMMAND_LAST; 1707 else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0) 1708 cmd_flags |= MCPR_NVM_COMMAND_LAST; 1709 else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0) 1710 cmd_flags |= MCPR_NVM_COMMAND_FIRST; 1711 1712 memcpy(&val, data_buf, 4); 1713 1714 /* Notice unlike bnx2x_nvram_read_dword() this will not 1715 * change val using be32_to_cpu(), which causes data to flip 1716 * if the eeprom is read and then written back. This is due 1717 * to tools utilizing this functionality that would break 1718 * if this would be resolved. 1719 */ 1720 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags); 1721 1722 /* advance to the next dword */ 1723 offset += sizeof(u32); 1724 data_buf += sizeof(u32); 1725 written_so_far += sizeof(u32); 1726 1727 /* At end of each 4Kb page, release nvram lock to allow MFW 1728 * chance to take it for its own use. 1729 */ 1730 if ((cmd_flags & MCPR_NVM_COMMAND_LAST) && 1731 (written_so_far < buf_size)) { 1732 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1733 "Releasing NVM lock after offset 0x%x\n", 1734 (u32)(offset - sizeof(u32))); 1735 bnx2x_release_nvram_lock(bp); 1736 usleep_range(1000, 2000); 1737 rc = bnx2x_acquire_nvram_lock(bp); 1738 if (rc) 1739 return rc; 1740 } 1741 1742 cmd_flags = 0; 1743 } 1744 1745 /* disable access to nvram interface */ 1746 bnx2x_disable_nvram_access(bp); 1747 bnx2x_release_nvram_lock(bp); 1748 1749 return rc; 1750 } 1751 1752 static int bnx2x_set_eeprom(struct net_device *dev, 1753 struct ethtool_eeprom *eeprom, u8 *eebuf) 1754 { 1755 struct bnx2x *bp = netdev_priv(dev); 1756 int port = BP_PORT(bp); 1757 int rc = 0; 1758 u32 ext_phy_config; 1759 1760 if (!bnx2x_is_nvm_accessible(bp)) { 1761 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1762 "cannot access eeprom when the interface is down\n"); 1763 return -EAGAIN; 1764 } 1765 1766 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n" 1767 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n", 1768 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset, 1769 eeprom->len, eeprom->len); 1770 1771 /* parameters already validated in ethtool_set_eeprom */ 1772 1773 /* PHY eeprom can be accessed only by the PMF */ 1774 if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) && 1775 !bp->port.pmf) { 1776 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 1777 "wrong magic or interface is not pmf\n"); 1778 return -EINVAL; 1779 } 1780 1781 ext_phy_config = 1782 SHMEM_RD(bp, 1783 dev_info.port_hw_config[port].external_phy_config); 1784 1785 if (eeprom->magic == 0x50485950) { 1786 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */ 1787 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 1788 1789 bnx2x_acquire_phy_lock(bp); 1790 rc |= bnx2x_link_reset(&bp->link_params, 1791 &bp->link_vars, 0); 1792 if (XGXS_EXT_PHY_TYPE(ext_phy_config) == 1793 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) 1794 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, 1795 MISC_REGISTERS_GPIO_HIGH, port); 1796 bnx2x_release_phy_lock(bp); 1797 bnx2x_link_report(bp); 1798 1799 } else if (eeprom->magic == 0x50485952) { 1800 /* 'PHYR' (0x50485952): re-init link after FW upgrade */ 1801 if (bp->state == BNX2X_STATE_OPEN) { 1802 bnx2x_acquire_phy_lock(bp); 1803 rc |= bnx2x_link_reset(&bp->link_params, 1804 &bp->link_vars, 1); 1805 1806 rc |= bnx2x_phy_init(&bp->link_params, 1807 &bp->link_vars); 1808 bnx2x_release_phy_lock(bp); 1809 bnx2x_calc_fc_adv(bp); 1810 } 1811 } else if (eeprom->magic == 0x53985943) { 1812 /* 'PHYC' (0x53985943): PHY FW upgrade completed */ 1813 if (XGXS_EXT_PHY_TYPE(ext_phy_config) == 1814 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) { 1815 1816 /* DSP Remove Download Mode */ 1817 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, 1818 MISC_REGISTERS_GPIO_LOW, port); 1819 1820 bnx2x_acquire_phy_lock(bp); 1821 1822 bnx2x_sfx7101_sp_sw_reset(bp, 1823 &bp->link_params.phy[EXT_PHY1]); 1824 1825 /* wait 0.5 sec to allow it to run */ 1826 msleep(500); 1827 bnx2x_ext_phy_hw_reset(bp, port); 1828 msleep(500); 1829 bnx2x_release_phy_lock(bp); 1830 } 1831 } else 1832 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len); 1833 1834 return rc; 1835 } 1836 1837 static int bnx2x_get_coalesce(struct net_device *dev, 1838 struct ethtool_coalesce *coal) 1839 { 1840 struct bnx2x *bp = netdev_priv(dev); 1841 1842 memset(coal, 0, sizeof(struct ethtool_coalesce)); 1843 1844 coal->rx_coalesce_usecs = bp->rx_ticks; 1845 coal->tx_coalesce_usecs = bp->tx_ticks; 1846 1847 return 0; 1848 } 1849 1850 static int bnx2x_set_coalesce(struct net_device *dev, 1851 struct ethtool_coalesce *coal) 1852 { 1853 struct bnx2x *bp = netdev_priv(dev); 1854 1855 bp->rx_ticks = (u16)coal->rx_coalesce_usecs; 1856 if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT) 1857 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT; 1858 1859 bp->tx_ticks = (u16)coal->tx_coalesce_usecs; 1860 if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT) 1861 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT; 1862 1863 if (netif_running(dev)) 1864 bnx2x_update_coalesce(bp); 1865 1866 return 0; 1867 } 1868 1869 static void bnx2x_get_ringparam(struct net_device *dev, 1870 struct ethtool_ringparam *ering) 1871 { 1872 struct bnx2x *bp = netdev_priv(dev); 1873 1874 ering->rx_max_pending = MAX_RX_AVAIL; 1875 1876 if (bp->rx_ring_size) 1877 ering->rx_pending = bp->rx_ring_size; 1878 else 1879 ering->rx_pending = MAX_RX_AVAIL; 1880 1881 ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL; 1882 ering->tx_pending = bp->tx_ring_size; 1883 } 1884 1885 static int bnx2x_set_ringparam(struct net_device *dev, 1886 struct ethtool_ringparam *ering) 1887 { 1888 struct bnx2x *bp = netdev_priv(dev); 1889 1890 DP(BNX2X_MSG_ETHTOOL, 1891 "set ring params command parameters: rx_pending = %d, tx_pending = %d\n", 1892 ering->rx_pending, ering->tx_pending); 1893 1894 if (pci_num_vf(bp->pdev)) { 1895 DP(BNX2X_MSG_IOV, 1896 "VFs are enabled, can not change ring parameters\n"); 1897 return -EPERM; 1898 } 1899 1900 if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 1901 DP(BNX2X_MSG_ETHTOOL, 1902 "Handling parity error recovery. Try again later\n"); 1903 return -EAGAIN; 1904 } 1905 1906 if ((ering->rx_pending > MAX_RX_AVAIL) || 1907 (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA : 1908 MIN_RX_SIZE_TPA)) || 1909 (ering->tx_pending > (IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL)) || 1910 (ering->tx_pending <= MAX_SKB_FRAGS + 4)) { 1911 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 1912 return -EINVAL; 1913 } 1914 1915 bp->rx_ring_size = ering->rx_pending; 1916 bp->tx_ring_size = ering->tx_pending; 1917 1918 return bnx2x_reload_if_running(dev); 1919 } 1920 1921 static void bnx2x_get_pauseparam(struct net_device *dev, 1922 struct ethtool_pauseparam *epause) 1923 { 1924 struct bnx2x *bp = netdev_priv(dev); 1925 int cfg_idx = bnx2x_get_link_cfg_idx(bp); 1926 int cfg_reg; 1927 1928 epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] == 1929 BNX2X_FLOW_CTRL_AUTO); 1930 1931 if (!epause->autoneg) 1932 cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx]; 1933 else 1934 cfg_reg = bp->link_params.req_fc_auto_adv; 1935 1936 epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) == 1937 BNX2X_FLOW_CTRL_RX); 1938 epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) == 1939 BNX2X_FLOW_CTRL_TX); 1940 1941 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n" 1942 " autoneg %d rx_pause %d tx_pause %d\n", 1943 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause); 1944 } 1945 1946 static int bnx2x_set_pauseparam(struct net_device *dev, 1947 struct ethtool_pauseparam *epause) 1948 { 1949 struct bnx2x *bp = netdev_priv(dev); 1950 u32 cfg_idx = bnx2x_get_link_cfg_idx(bp); 1951 if (IS_MF(bp)) 1952 return 0; 1953 1954 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n" 1955 " autoneg %d rx_pause %d tx_pause %d\n", 1956 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause); 1957 1958 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO; 1959 1960 if (epause->rx_pause) 1961 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX; 1962 1963 if (epause->tx_pause) 1964 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX; 1965 1966 if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO) 1967 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE; 1968 1969 if (epause->autoneg) { 1970 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) { 1971 DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n"); 1972 return -EINVAL; 1973 } 1974 1975 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) { 1976 bp->link_params.req_flow_ctrl[cfg_idx] = 1977 BNX2X_FLOW_CTRL_AUTO; 1978 } 1979 bp->link_params.req_fc_auto_adv = 0; 1980 if (epause->rx_pause) 1981 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_RX; 1982 1983 if (epause->tx_pause) 1984 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_TX; 1985 1986 if (!bp->link_params.req_fc_auto_adv) 1987 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_NONE; 1988 } 1989 1990 DP(BNX2X_MSG_ETHTOOL, 1991 "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]); 1992 1993 if (netif_running(dev)) { 1994 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 1995 bnx2x_force_link_reset(bp); 1996 bnx2x_link_set(bp); 1997 } 1998 1999 return 0; 2000 } 2001 2002 static const char bnx2x_tests_str_arr[BNX2X_NUM_TESTS_SF][ETH_GSTRING_LEN] = { 2003 "register_test (offline) ", 2004 "memory_test (offline) ", 2005 "int_loopback_test (offline)", 2006 "ext_loopback_test (offline)", 2007 "nvram_test (online) ", 2008 "interrupt_test (online) ", 2009 "link_test (online) " 2010 }; 2011 2012 enum { 2013 BNX2X_PRI_FLAG_ISCSI, 2014 BNX2X_PRI_FLAG_FCOE, 2015 BNX2X_PRI_FLAG_STORAGE, 2016 BNX2X_PRI_FLAG_LEN, 2017 }; 2018 2019 static const char bnx2x_private_arr[BNX2X_PRI_FLAG_LEN][ETH_GSTRING_LEN] = { 2020 "iSCSI offload support", 2021 "FCoE offload support", 2022 "Storage only interface" 2023 }; 2024 2025 static u32 bnx2x_eee_to_adv(u32 eee_adv) 2026 { 2027 u32 modes = 0; 2028 2029 if (eee_adv & SHMEM_EEE_100M_ADV) 2030 modes |= ADVERTISED_100baseT_Full; 2031 if (eee_adv & SHMEM_EEE_1G_ADV) 2032 modes |= ADVERTISED_1000baseT_Full; 2033 if (eee_adv & SHMEM_EEE_10G_ADV) 2034 modes |= ADVERTISED_10000baseT_Full; 2035 2036 return modes; 2037 } 2038 2039 static u32 bnx2x_adv_to_eee(u32 modes, u32 shift) 2040 { 2041 u32 eee_adv = 0; 2042 if (modes & ADVERTISED_100baseT_Full) 2043 eee_adv |= SHMEM_EEE_100M_ADV; 2044 if (modes & ADVERTISED_1000baseT_Full) 2045 eee_adv |= SHMEM_EEE_1G_ADV; 2046 if (modes & ADVERTISED_10000baseT_Full) 2047 eee_adv |= SHMEM_EEE_10G_ADV; 2048 2049 return eee_adv << shift; 2050 } 2051 2052 static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata) 2053 { 2054 struct bnx2x *bp = netdev_priv(dev); 2055 u32 eee_cfg; 2056 2057 if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) { 2058 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n"); 2059 return -EOPNOTSUPP; 2060 } 2061 2062 eee_cfg = bp->link_vars.eee_status; 2063 2064 edata->supported = 2065 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >> 2066 SHMEM_EEE_SUPPORTED_SHIFT); 2067 2068 edata->advertised = 2069 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >> 2070 SHMEM_EEE_ADV_STATUS_SHIFT); 2071 edata->lp_advertised = 2072 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >> 2073 SHMEM_EEE_LP_ADV_STATUS_SHIFT); 2074 2075 /* SHMEM value is in 16u units --> Convert to 1u units. */ 2076 edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4; 2077 2078 edata->eee_enabled = (eee_cfg & SHMEM_EEE_REQUESTED_BIT) ? 1 : 0; 2079 edata->eee_active = (eee_cfg & SHMEM_EEE_ACTIVE_BIT) ? 1 : 0; 2080 edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0; 2081 2082 return 0; 2083 } 2084 2085 static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata) 2086 { 2087 struct bnx2x *bp = netdev_priv(dev); 2088 u32 eee_cfg; 2089 u32 advertised; 2090 2091 if (IS_MF(bp)) 2092 return 0; 2093 2094 if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) { 2095 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n"); 2096 return -EOPNOTSUPP; 2097 } 2098 2099 eee_cfg = bp->link_vars.eee_status; 2100 2101 if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) { 2102 DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n"); 2103 return -EOPNOTSUPP; 2104 } 2105 2106 advertised = bnx2x_adv_to_eee(edata->advertised, 2107 SHMEM_EEE_ADV_STATUS_SHIFT); 2108 if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) { 2109 DP(BNX2X_MSG_ETHTOOL, 2110 "Direct manipulation of EEE advertisement is not supported\n"); 2111 return -EINVAL; 2112 } 2113 2114 if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) { 2115 DP(BNX2X_MSG_ETHTOOL, 2116 "Maximal Tx Lpi timer supported is %x(u)\n", 2117 EEE_MODE_TIMER_MASK); 2118 return -EINVAL; 2119 } 2120 if (edata->tx_lpi_enabled && 2121 (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) { 2122 DP(BNX2X_MSG_ETHTOOL, 2123 "Minimal Tx Lpi timer supported is %d(u)\n", 2124 EEE_MODE_NVRAM_AGGRESSIVE_TIME); 2125 return -EINVAL; 2126 } 2127 2128 /* All is well; Apply changes*/ 2129 if (edata->eee_enabled) 2130 bp->link_params.eee_mode |= EEE_MODE_ADV_LPI; 2131 else 2132 bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI; 2133 2134 if (edata->tx_lpi_enabled) 2135 bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI; 2136 else 2137 bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI; 2138 2139 bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK; 2140 bp->link_params.eee_mode |= (edata->tx_lpi_timer & 2141 EEE_MODE_TIMER_MASK) | 2142 EEE_MODE_OVERRIDE_NVRAM | 2143 EEE_MODE_OUTPUT_TIME; 2144 2145 /* Restart link to propagate changes */ 2146 if (netif_running(dev)) { 2147 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 2148 bnx2x_force_link_reset(bp); 2149 bnx2x_link_set(bp); 2150 } 2151 2152 return 0; 2153 } 2154 2155 enum { 2156 BNX2X_CHIP_E1_OFST = 0, 2157 BNX2X_CHIP_E1H_OFST, 2158 BNX2X_CHIP_E2_OFST, 2159 BNX2X_CHIP_E3_OFST, 2160 BNX2X_CHIP_E3B0_OFST, 2161 BNX2X_CHIP_MAX_OFST 2162 }; 2163 2164 #define BNX2X_CHIP_MASK_E1 (1 << BNX2X_CHIP_E1_OFST) 2165 #define BNX2X_CHIP_MASK_E1H (1 << BNX2X_CHIP_E1H_OFST) 2166 #define BNX2X_CHIP_MASK_E2 (1 << BNX2X_CHIP_E2_OFST) 2167 #define BNX2X_CHIP_MASK_E3 (1 << BNX2X_CHIP_E3_OFST) 2168 #define BNX2X_CHIP_MASK_E3B0 (1 << BNX2X_CHIP_E3B0_OFST) 2169 2170 #define BNX2X_CHIP_MASK_ALL ((1 << BNX2X_CHIP_MAX_OFST) - 1) 2171 #define BNX2X_CHIP_MASK_E1X (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H) 2172 2173 static int bnx2x_test_registers(struct bnx2x *bp) 2174 { 2175 int idx, i, rc = -ENODEV; 2176 u32 wr_val = 0, hw; 2177 int port = BP_PORT(bp); 2178 static const struct { 2179 u32 hw; 2180 u32 offset0; 2181 u32 offset1; 2182 u32 mask; 2183 } reg_tbl[] = { 2184 /* 0 */ { BNX2X_CHIP_MASK_ALL, 2185 BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff }, 2186 { BNX2X_CHIP_MASK_ALL, 2187 DORQ_REG_DB_ADDR0, 4, 0xffffffff }, 2188 { BNX2X_CHIP_MASK_E1X, 2189 HC_REG_AGG_INT_0, 4, 0x000003ff }, 2190 { BNX2X_CHIP_MASK_ALL, 2191 PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 }, 2192 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3, 2193 PBF_REG_P0_INIT_CRD, 4, 0x000007ff }, 2194 { BNX2X_CHIP_MASK_E3B0, 2195 PBF_REG_INIT_CRD_Q0, 4, 0x000007ff }, 2196 { BNX2X_CHIP_MASK_ALL, 2197 PRS_REG_CID_PORT_0, 4, 0x00ffffff }, 2198 { BNX2X_CHIP_MASK_ALL, 2199 PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff }, 2200 { BNX2X_CHIP_MASK_ALL, 2201 PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff }, 2202 { BNX2X_CHIP_MASK_ALL, 2203 PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff }, 2204 /* 10 */ { BNX2X_CHIP_MASK_ALL, 2205 PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff }, 2206 { BNX2X_CHIP_MASK_ALL, 2207 PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff }, 2208 { BNX2X_CHIP_MASK_ALL, 2209 QM_REG_CONNNUM_0, 4, 0x000fffff }, 2210 { BNX2X_CHIP_MASK_ALL, 2211 TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff }, 2212 { BNX2X_CHIP_MASK_ALL, 2213 SRC_REG_KEYRSS0_0, 40, 0xffffffff }, 2214 { BNX2X_CHIP_MASK_ALL, 2215 SRC_REG_KEYRSS0_7, 40, 0xffffffff }, 2216 { BNX2X_CHIP_MASK_ALL, 2217 XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 }, 2218 { BNX2X_CHIP_MASK_ALL, 2219 XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 }, 2220 { BNX2X_CHIP_MASK_ALL, 2221 XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff }, 2222 { BNX2X_CHIP_MASK_ALL, 2223 NIG_REG_LLH0_T_BIT, 4, 0x00000001 }, 2224 /* 20 */ { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2225 NIG_REG_EMAC0_IN_EN, 4, 0x00000001 }, 2226 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2227 NIG_REG_BMAC0_IN_EN, 4, 0x00000001 }, 2228 { BNX2X_CHIP_MASK_ALL, 2229 NIG_REG_XCM0_OUT_EN, 4, 0x00000001 }, 2230 { BNX2X_CHIP_MASK_ALL, 2231 NIG_REG_BRB0_OUT_EN, 4, 0x00000001 }, 2232 { BNX2X_CHIP_MASK_ALL, 2233 NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 }, 2234 { BNX2X_CHIP_MASK_ALL, 2235 NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff }, 2236 { BNX2X_CHIP_MASK_ALL, 2237 NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff }, 2238 { BNX2X_CHIP_MASK_ALL, 2239 NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff }, 2240 { BNX2X_CHIP_MASK_ALL, 2241 NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff }, 2242 { BNX2X_CHIP_MASK_ALL, 2243 NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 }, 2244 /* 30 */ { BNX2X_CHIP_MASK_ALL, 2245 NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff }, 2246 { BNX2X_CHIP_MASK_ALL, 2247 NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff }, 2248 { BNX2X_CHIP_MASK_ALL, 2249 NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff }, 2250 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2251 NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 }, 2252 { BNX2X_CHIP_MASK_ALL, 2253 NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001}, 2254 { BNX2X_CHIP_MASK_ALL, 2255 NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff }, 2256 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2257 NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 }, 2258 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, 2259 NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f }, 2260 2261 { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 } 2262 }; 2263 2264 if (!bnx2x_is_nvm_accessible(bp)) { 2265 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2266 "cannot access eeprom when the interface is down\n"); 2267 return rc; 2268 } 2269 2270 if (CHIP_IS_E1(bp)) 2271 hw = BNX2X_CHIP_MASK_E1; 2272 else if (CHIP_IS_E1H(bp)) 2273 hw = BNX2X_CHIP_MASK_E1H; 2274 else if (CHIP_IS_E2(bp)) 2275 hw = BNX2X_CHIP_MASK_E2; 2276 else if (CHIP_IS_E3B0(bp)) 2277 hw = BNX2X_CHIP_MASK_E3B0; 2278 else /* e3 A0 */ 2279 hw = BNX2X_CHIP_MASK_E3; 2280 2281 /* Repeat the test twice: 2282 * First by writing 0x00000000, second by writing 0xffffffff 2283 */ 2284 for (idx = 0; idx < 2; idx++) { 2285 2286 switch (idx) { 2287 case 0: 2288 wr_val = 0; 2289 break; 2290 case 1: 2291 wr_val = 0xffffffff; 2292 break; 2293 } 2294 2295 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) { 2296 u32 offset, mask, save_val, val; 2297 if (!(hw & reg_tbl[i].hw)) 2298 continue; 2299 2300 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1; 2301 mask = reg_tbl[i].mask; 2302 2303 save_val = REG_RD(bp, offset); 2304 2305 REG_WR(bp, offset, wr_val & mask); 2306 2307 val = REG_RD(bp, offset); 2308 2309 /* Restore the original register's value */ 2310 REG_WR(bp, offset, save_val); 2311 2312 /* verify value is as expected */ 2313 if ((val & mask) != (wr_val & mask)) { 2314 DP(BNX2X_MSG_ETHTOOL, 2315 "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n", 2316 offset, val, wr_val, mask); 2317 goto test_reg_exit; 2318 } 2319 } 2320 } 2321 2322 rc = 0; 2323 2324 test_reg_exit: 2325 return rc; 2326 } 2327 2328 static int bnx2x_test_memory(struct bnx2x *bp) 2329 { 2330 int i, j, rc = -ENODEV; 2331 u32 val, index; 2332 static const struct { 2333 u32 offset; 2334 int size; 2335 } mem_tbl[] = { 2336 { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE }, 2337 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE }, 2338 { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE }, 2339 { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE }, 2340 { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE }, 2341 { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE }, 2342 { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE }, 2343 2344 { 0xffffffff, 0 } 2345 }; 2346 2347 static const struct { 2348 char *name; 2349 u32 offset; 2350 u32 hw_mask[BNX2X_CHIP_MAX_OFST]; 2351 } prty_tbl[] = { 2352 { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS, 2353 {0x3ffc0, 0, 0, 0} }, 2354 { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS, 2355 {0x2, 0x2, 0, 0} }, 2356 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS, 2357 {0, 0, 0, 0} }, 2358 { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS, 2359 {0x3ffc0, 0, 0, 0} }, 2360 { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS, 2361 {0x3ffc0, 0, 0, 0} }, 2362 { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS, 2363 {0x3ffc1, 0, 0, 0} }, 2364 2365 { NULL, 0xffffffff, {0, 0, 0, 0} } 2366 }; 2367 2368 if (!bnx2x_is_nvm_accessible(bp)) { 2369 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2370 "cannot access eeprom when the interface is down\n"); 2371 return rc; 2372 } 2373 2374 if (CHIP_IS_E1(bp)) 2375 index = BNX2X_CHIP_E1_OFST; 2376 else if (CHIP_IS_E1H(bp)) 2377 index = BNX2X_CHIP_E1H_OFST; 2378 else if (CHIP_IS_E2(bp)) 2379 index = BNX2X_CHIP_E2_OFST; 2380 else /* e3 */ 2381 index = BNX2X_CHIP_E3_OFST; 2382 2383 /* pre-Check the parity status */ 2384 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) { 2385 val = REG_RD(bp, prty_tbl[i].offset); 2386 if (val & ~(prty_tbl[i].hw_mask[index])) { 2387 DP(BNX2X_MSG_ETHTOOL, 2388 "%s is 0x%x\n", prty_tbl[i].name, val); 2389 goto test_mem_exit; 2390 } 2391 } 2392 2393 /* Go through all the memories */ 2394 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) 2395 for (j = 0; j < mem_tbl[i].size; j++) 2396 REG_RD(bp, mem_tbl[i].offset + j*4); 2397 2398 /* Check the parity status */ 2399 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) { 2400 val = REG_RD(bp, prty_tbl[i].offset); 2401 if (val & ~(prty_tbl[i].hw_mask[index])) { 2402 DP(BNX2X_MSG_ETHTOOL, 2403 "%s is 0x%x\n", prty_tbl[i].name, val); 2404 goto test_mem_exit; 2405 } 2406 } 2407 2408 rc = 0; 2409 2410 test_mem_exit: 2411 return rc; 2412 } 2413 2414 static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes) 2415 { 2416 int cnt = 1400; 2417 2418 if (link_up) { 2419 while (bnx2x_link_test(bp, is_serdes) && cnt--) 2420 msleep(20); 2421 2422 if (cnt <= 0 && bnx2x_link_test(bp, is_serdes)) 2423 DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n"); 2424 2425 cnt = 1400; 2426 while (!bp->link_vars.link_up && cnt--) 2427 msleep(20); 2428 2429 if (cnt <= 0 && !bp->link_vars.link_up) 2430 DP(BNX2X_MSG_ETHTOOL, 2431 "Timeout waiting for link init\n"); 2432 } 2433 } 2434 2435 static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode) 2436 { 2437 unsigned int pkt_size, num_pkts, i; 2438 struct sk_buff *skb; 2439 unsigned char *packet; 2440 struct bnx2x_fastpath *fp_rx = &bp->fp[0]; 2441 struct bnx2x_fastpath *fp_tx = &bp->fp[0]; 2442 struct bnx2x_fp_txdata *txdata = fp_tx->txdata_ptr[0]; 2443 u16 tx_start_idx, tx_idx; 2444 u16 rx_start_idx, rx_idx; 2445 u16 pkt_prod, bd_prod; 2446 struct sw_tx_bd *tx_buf; 2447 struct eth_tx_start_bd *tx_start_bd; 2448 dma_addr_t mapping; 2449 union eth_rx_cqe *cqe; 2450 u8 cqe_fp_flags, cqe_fp_type; 2451 struct sw_rx_bd *rx_buf; 2452 u16 len; 2453 int rc = -ENODEV; 2454 u8 *data; 2455 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, 2456 txdata->txq_index); 2457 2458 /* check the loopback mode */ 2459 switch (loopback_mode) { 2460 case BNX2X_PHY_LOOPBACK: 2461 if (bp->link_params.loopback_mode != LOOPBACK_XGXS) { 2462 DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n"); 2463 return -EINVAL; 2464 } 2465 break; 2466 case BNX2X_MAC_LOOPBACK: 2467 if (CHIP_IS_E3(bp)) { 2468 int cfg_idx = bnx2x_get_link_cfg_idx(bp); 2469 if (bp->port.supported[cfg_idx] & 2470 (SUPPORTED_10000baseT_Full | 2471 SUPPORTED_20000baseMLD2_Full | 2472 SUPPORTED_20000baseKR2_Full)) 2473 bp->link_params.loopback_mode = LOOPBACK_XMAC; 2474 else 2475 bp->link_params.loopback_mode = LOOPBACK_UMAC; 2476 } else 2477 bp->link_params.loopback_mode = LOOPBACK_BMAC; 2478 2479 bnx2x_phy_init(&bp->link_params, &bp->link_vars); 2480 break; 2481 case BNX2X_EXT_LOOPBACK: 2482 if (bp->link_params.loopback_mode != LOOPBACK_EXT) { 2483 DP(BNX2X_MSG_ETHTOOL, 2484 "Can't configure external loopback\n"); 2485 return -EINVAL; 2486 } 2487 break; 2488 default: 2489 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 2490 return -EINVAL; 2491 } 2492 2493 /* prepare the loopback packet */ 2494 pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ? 2495 bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN); 2496 skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size); 2497 if (!skb) { 2498 DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n"); 2499 rc = -ENOMEM; 2500 goto test_loopback_exit; 2501 } 2502 packet = skb_put(skb, pkt_size); 2503 memcpy(packet, bp->dev->dev_addr, ETH_ALEN); 2504 eth_zero_addr(packet + ETH_ALEN); 2505 memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN)); 2506 for (i = ETH_HLEN; i < pkt_size; i++) 2507 packet[i] = (unsigned char) (i & 0xff); 2508 mapping = dma_map_single(&bp->pdev->dev, skb->data, 2509 skb_headlen(skb), DMA_TO_DEVICE); 2510 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) { 2511 rc = -ENOMEM; 2512 dev_kfree_skb(skb); 2513 DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n"); 2514 goto test_loopback_exit; 2515 } 2516 2517 /* send the loopback packet */ 2518 num_pkts = 0; 2519 tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb); 2520 rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb); 2521 2522 netdev_tx_sent_queue(txq, skb->len); 2523 2524 pkt_prod = txdata->tx_pkt_prod++; 2525 tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)]; 2526 tx_buf->first_bd = txdata->tx_bd_prod; 2527 tx_buf->skb = skb; 2528 tx_buf->flags = 0; 2529 2530 bd_prod = TX_BD(txdata->tx_bd_prod); 2531 tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd; 2532 tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping)); 2533 tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping)); 2534 tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */ 2535 tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb)); 2536 tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod); 2537 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD; 2538 SET_FLAG(tx_start_bd->general_data, 2539 ETH_TX_START_BD_HDR_NBDS, 2540 1); 2541 SET_FLAG(tx_start_bd->general_data, 2542 ETH_TX_START_BD_PARSE_NBDS, 2543 0); 2544 2545 /* turn on parsing and get a BD */ 2546 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod)); 2547 2548 if (CHIP_IS_E1x(bp)) { 2549 u16 global_data = 0; 2550 struct eth_tx_parse_bd_e1x *pbd_e1x = 2551 &txdata->tx_desc_ring[bd_prod].parse_bd_e1x; 2552 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x)); 2553 SET_FLAG(global_data, 2554 ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, UNICAST_ADDRESS); 2555 pbd_e1x->global_data = cpu_to_le16(global_data); 2556 } else { 2557 u32 parsing_data = 0; 2558 struct eth_tx_parse_bd_e2 *pbd_e2 = 2559 &txdata->tx_desc_ring[bd_prod].parse_bd_e2; 2560 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2)); 2561 SET_FLAG(parsing_data, 2562 ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, UNICAST_ADDRESS); 2563 pbd_e2->parsing_data = cpu_to_le32(parsing_data); 2564 } 2565 wmb(); 2566 2567 txdata->tx_db.data.prod += 2; 2568 barrier(); 2569 DOORBELL(bp, txdata->cid, txdata->tx_db.raw); 2570 2571 mmiowb(); 2572 barrier(); 2573 2574 num_pkts++; 2575 txdata->tx_bd_prod += 2; /* start + pbd */ 2576 2577 udelay(100); 2578 2579 tx_idx = le16_to_cpu(*txdata->tx_cons_sb); 2580 if (tx_idx != tx_start_idx + num_pkts) 2581 goto test_loopback_exit; 2582 2583 /* Unlike HC IGU won't generate an interrupt for status block 2584 * updates that have been performed while interrupts were 2585 * disabled. 2586 */ 2587 if (bp->common.int_block == INT_BLOCK_IGU) { 2588 /* Disable local BHes to prevent a dead-lock situation between 2589 * sch_direct_xmit() and bnx2x_run_loopback() (calling 2590 * bnx2x_tx_int()), as both are taking netif_tx_lock(). 2591 */ 2592 local_bh_disable(); 2593 bnx2x_tx_int(bp, txdata); 2594 local_bh_enable(); 2595 } 2596 2597 rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb); 2598 if (rx_idx != rx_start_idx + num_pkts) 2599 goto test_loopback_exit; 2600 2601 cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)]; 2602 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags; 2603 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE; 2604 if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS)) 2605 goto test_loopback_rx_exit; 2606 2607 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len); 2608 if (len != pkt_size) 2609 goto test_loopback_rx_exit; 2610 2611 rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)]; 2612 dma_sync_single_for_cpu(&bp->pdev->dev, 2613 dma_unmap_addr(rx_buf, mapping), 2614 fp_rx->rx_buf_size, DMA_FROM_DEVICE); 2615 data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset; 2616 for (i = ETH_HLEN; i < pkt_size; i++) 2617 if (*(data + i) != (unsigned char) (i & 0xff)) 2618 goto test_loopback_rx_exit; 2619 2620 rc = 0; 2621 2622 test_loopback_rx_exit: 2623 2624 fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons); 2625 fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod); 2626 fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons); 2627 fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod); 2628 2629 /* Update producers */ 2630 bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod, 2631 fp_rx->rx_sge_prod); 2632 2633 test_loopback_exit: 2634 bp->link_params.loopback_mode = LOOPBACK_NONE; 2635 2636 return rc; 2637 } 2638 2639 static int bnx2x_test_loopback(struct bnx2x *bp) 2640 { 2641 int rc = 0, res; 2642 2643 if (BP_NOMCP(bp)) 2644 return rc; 2645 2646 if (!netif_running(bp->dev)) 2647 return BNX2X_LOOPBACK_FAILED; 2648 2649 bnx2x_netif_stop(bp, 1); 2650 bnx2x_acquire_phy_lock(bp); 2651 2652 res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK); 2653 if (res) { 2654 DP(BNX2X_MSG_ETHTOOL, " PHY loopback failed (res %d)\n", res); 2655 rc |= BNX2X_PHY_LOOPBACK_FAILED; 2656 } 2657 2658 res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK); 2659 if (res) { 2660 DP(BNX2X_MSG_ETHTOOL, " MAC loopback failed (res %d)\n", res); 2661 rc |= BNX2X_MAC_LOOPBACK_FAILED; 2662 } 2663 2664 bnx2x_release_phy_lock(bp); 2665 bnx2x_netif_start(bp); 2666 2667 return rc; 2668 } 2669 2670 static int bnx2x_test_ext_loopback(struct bnx2x *bp) 2671 { 2672 int rc; 2673 u8 is_serdes = 2674 (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0; 2675 2676 if (BP_NOMCP(bp)) 2677 return -ENODEV; 2678 2679 if (!netif_running(bp->dev)) 2680 return BNX2X_EXT_LOOPBACK_FAILED; 2681 2682 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false); 2683 rc = bnx2x_nic_load(bp, LOAD_LOOPBACK_EXT); 2684 if (rc) { 2685 DP(BNX2X_MSG_ETHTOOL, 2686 "Can't perform self-test, nic_load (for external lb) failed\n"); 2687 return -ENODEV; 2688 } 2689 bnx2x_wait_for_link(bp, 1, is_serdes); 2690 2691 bnx2x_netif_stop(bp, 1); 2692 2693 rc = bnx2x_run_loopback(bp, BNX2X_EXT_LOOPBACK); 2694 if (rc) 2695 DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed (res %d)\n", rc); 2696 2697 bnx2x_netif_start(bp); 2698 2699 return rc; 2700 } 2701 2702 struct code_entry { 2703 u32 sram_start_addr; 2704 u32 code_attribute; 2705 #define CODE_IMAGE_TYPE_MASK 0xf0800003 2706 #define CODE_IMAGE_VNTAG_PROFILES_DATA 0xd0000003 2707 #define CODE_IMAGE_LENGTH_MASK 0x007ffffc 2708 #define CODE_IMAGE_TYPE_EXTENDED_DIR 0xe0000000 2709 u32 nvm_start_addr; 2710 }; 2711 2712 #define CODE_ENTRY_MAX 16 2713 #define CODE_ENTRY_EXTENDED_DIR_IDX 15 2714 #define MAX_IMAGES_IN_EXTENDED_DIR 64 2715 #define NVRAM_DIR_OFFSET 0x14 2716 2717 #define EXTENDED_DIR_EXISTS(code) \ 2718 ((code & CODE_IMAGE_TYPE_MASK) == CODE_IMAGE_TYPE_EXTENDED_DIR && \ 2719 (code & CODE_IMAGE_LENGTH_MASK) != 0) 2720 2721 #define CRC32_RESIDUAL 0xdebb20e3 2722 #define CRC_BUFF_SIZE 256 2723 2724 static int bnx2x_nvram_crc(struct bnx2x *bp, 2725 int offset, 2726 int size, 2727 u8 *buff) 2728 { 2729 u32 crc = ~0; 2730 int rc = 0, done = 0; 2731 2732 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2733 "NVRAM CRC from 0x%08x to 0x%08x\n", offset, offset + size); 2734 2735 while (done < size) { 2736 int count = min_t(int, size - done, CRC_BUFF_SIZE); 2737 2738 rc = bnx2x_nvram_read(bp, offset + done, buff, count); 2739 2740 if (rc) 2741 return rc; 2742 2743 crc = crc32_le(crc, buff, count); 2744 done += count; 2745 } 2746 2747 if (crc != CRC32_RESIDUAL) 2748 rc = -EINVAL; 2749 2750 return rc; 2751 } 2752 2753 static int bnx2x_test_nvram_dir(struct bnx2x *bp, 2754 struct code_entry *entry, 2755 u8 *buff) 2756 { 2757 size_t size = entry->code_attribute & CODE_IMAGE_LENGTH_MASK; 2758 u32 type = entry->code_attribute & CODE_IMAGE_TYPE_MASK; 2759 int rc; 2760 2761 /* Zero-length images and AFEX profiles do not have CRC */ 2762 if (size == 0 || type == CODE_IMAGE_VNTAG_PROFILES_DATA) 2763 return 0; 2764 2765 rc = bnx2x_nvram_crc(bp, entry->nvm_start_addr, size, buff); 2766 if (rc) 2767 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2768 "image %x has failed crc test (rc %d)\n", type, rc); 2769 2770 return rc; 2771 } 2772 2773 static int bnx2x_test_dir_entry(struct bnx2x *bp, u32 addr, u8 *buff) 2774 { 2775 int rc; 2776 struct code_entry entry; 2777 2778 rc = bnx2x_nvram_read32(bp, addr, (u32 *)&entry, sizeof(entry)); 2779 if (rc) 2780 return rc; 2781 2782 return bnx2x_test_nvram_dir(bp, &entry, buff); 2783 } 2784 2785 static int bnx2x_test_nvram_ext_dirs(struct bnx2x *bp, u8 *buff) 2786 { 2787 u32 rc, cnt, dir_offset = NVRAM_DIR_OFFSET; 2788 struct code_entry entry; 2789 int i; 2790 2791 rc = bnx2x_nvram_read32(bp, 2792 dir_offset + 2793 sizeof(entry) * CODE_ENTRY_EXTENDED_DIR_IDX, 2794 (u32 *)&entry, sizeof(entry)); 2795 if (rc) 2796 return rc; 2797 2798 if (!EXTENDED_DIR_EXISTS(entry.code_attribute)) 2799 return 0; 2800 2801 rc = bnx2x_nvram_read32(bp, entry.nvm_start_addr, 2802 &cnt, sizeof(u32)); 2803 if (rc) 2804 return rc; 2805 2806 dir_offset = entry.nvm_start_addr + 8; 2807 2808 for (i = 0; i < cnt && i < MAX_IMAGES_IN_EXTENDED_DIR; i++) { 2809 rc = bnx2x_test_dir_entry(bp, dir_offset + 2810 sizeof(struct code_entry) * i, 2811 buff); 2812 if (rc) 2813 return rc; 2814 } 2815 2816 return 0; 2817 } 2818 2819 static int bnx2x_test_nvram_dirs(struct bnx2x *bp, u8 *buff) 2820 { 2821 u32 rc, dir_offset = NVRAM_DIR_OFFSET; 2822 int i; 2823 2824 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "NVRAM DIRS CRC test-set\n"); 2825 2826 for (i = 0; i < CODE_ENTRY_EXTENDED_DIR_IDX; i++) { 2827 rc = bnx2x_test_dir_entry(bp, dir_offset + 2828 sizeof(struct code_entry) * i, 2829 buff); 2830 if (rc) 2831 return rc; 2832 } 2833 2834 return bnx2x_test_nvram_ext_dirs(bp, buff); 2835 } 2836 2837 struct crc_pair { 2838 int offset; 2839 int size; 2840 }; 2841 2842 static int bnx2x_test_nvram_tbl(struct bnx2x *bp, 2843 const struct crc_pair *nvram_tbl, u8 *buf) 2844 { 2845 int i; 2846 2847 for (i = 0; nvram_tbl[i].size; i++) { 2848 int rc = bnx2x_nvram_crc(bp, nvram_tbl[i].offset, 2849 nvram_tbl[i].size, buf); 2850 if (rc) { 2851 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2852 "nvram_tbl[%d] has failed crc test (rc %d)\n", 2853 i, rc); 2854 return rc; 2855 } 2856 } 2857 2858 return 0; 2859 } 2860 2861 static int bnx2x_test_nvram(struct bnx2x *bp) 2862 { 2863 const struct crc_pair nvram_tbl[] = { 2864 { 0, 0x14 }, /* bootstrap */ 2865 { 0x14, 0xec }, /* dir */ 2866 { 0x100, 0x350 }, /* manuf_info */ 2867 { 0x450, 0xf0 }, /* feature_info */ 2868 { 0x640, 0x64 }, /* upgrade_key_info */ 2869 { 0x708, 0x70 }, /* manuf_key_info */ 2870 { 0, 0 } 2871 }; 2872 const struct crc_pair nvram_tbl2[] = { 2873 { 0x7e8, 0x350 }, /* manuf_info2 */ 2874 { 0xb38, 0xf0 }, /* feature_info */ 2875 { 0, 0 } 2876 }; 2877 2878 u8 *buf; 2879 int rc; 2880 u32 magic; 2881 2882 if (BP_NOMCP(bp)) 2883 return 0; 2884 2885 buf = kmalloc(CRC_BUFF_SIZE, GFP_KERNEL); 2886 if (!buf) { 2887 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n"); 2888 rc = -ENOMEM; 2889 goto test_nvram_exit; 2890 } 2891 2892 rc = bnx2x_nvram_read32(bp, 0, &magic, sizeof(magic)); 2893 if (rc) { 2894 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2895 "magic value read (rc %d)\n", rc); 2896 goto test_nvram_exit; 2897 } 2898 2899 if (magic != 0x669955aa) { 2900 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2901 "wrong magic value (0x%08x)\n", magic); 2902 rc = -ENODEV; 2903 goto test_nvram_exit; 2904 } 2905 2906 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "Port 0 CRC test-set\n"); 2907 rc = bnx2x_test_nvram_tbl(bp, nvram_tbl, buf); 2908 if (rc) 2909 goto test_nvram_exit; 2910 2911 if (!CHIP_IS_E1x(bp) && !CHIP_IS_57811xx(bp)) { 2912 u32 hide = SHMEM_RD(bp, dev_info.shared_hw_config.config2) & 2913 SHARED_HW_CFG_HIDE_PORT1; 2914 2915 if (!hide) { 2916 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2917 "Port 1 CRC test-set\n"); 2918 rc = bnx2x_test_nvram_tbl(bp, nvram_tbl2, buf); 2919 if (rc) 2920 goto test_nvram_exit; 2921 } 2922 } 2923 2924 rc = bnx2x_test_nvram_dirs(bp, buf); 2925 2926 test_nvram_exit: 2927 kfree(buf); 2928 return rc; 2929 } 2930 2931 /* Send an EMPTY ramrod on the first queue */ 2932 static int bnx2x_test_intr(struct bnx2x *bp) 2933 { 2934 struct bnx2x_queue_state_params params = {NULL}; 2935 2936 if (!netif_running(bp->dev)) { 2937 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 2938 "cannot access eeprom when the interface is down\n"); 2939 return -ENODEV; 2940 } 2941 2942 params.q_obj = &bp->sp_objs->q_obj; 2943 params.cmd = BNX2X_Q_CMD_EMPTY; 2944 2945 __set_bit(RAMROD_COMP_WAIT, ¶ms.ramrod_flags); 2946 2947 return bnx2x_queue_state_change(bp, ¶ms); 2948 } 2949 2950 static void bnx2x_self_test(struct net_device *dev, 2951 struct ethtool_test *etest, u64 *buf) 2952 { 2953 struct bnx2x *bp = netdev_priv(dev); 2954 u8 is_serdes, link_up; 2955 int rc, cnt = 0; 2956 2957 if (pci_num_vf(bp->pdev)) { 2958 DP(BNX2X_MSG_IOV, 2959 "VFs are enabled, can not perform self test\n"); 2960 return; 2961 } 2962 2963 if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 2964 netdev_err(bp->dev, 2965 "Handling parity error recovery. Try again later\n"); 2966 etest->flags |= ETH_TEST_FL_FAILED; 2967 return; 2968 } 2969 2970 DP(BNX2X_MSG_ETHTOOL, 2971 "Self-test command parameters: offline = %d, external_lb = %d\n", 2972 (etest->flags & ETH_TEST_FL_OFFLINE), 2973 (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2); 2974 2975 memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS(bp)); 2976 2977 if (bnx2x_test_nvram(bp) != 0) { 2978 if (!IS_MF(bp)) 2979 buf[4] = 1; 2980 else 2981 buf[0] = 1; 2982 etest->flags |= ETH_TEST_FL_FAILED; 2983 } 2984 2985 if (!netif_running(dev)) { 2986 DP(BNX2X_MSG_ETHTOOL, "Interface is down\n"); 2987 return; 2988 } 2989 2990 is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0; 2991 link_up = bp->link_vars.link_up; 2992 /* offline tests are not supported in MF mode */ 2993 if ((etest->flags & ETH_TEST_FL_OFFLINE) && !IS_MF(bp)) { 2994 int port = BP_PORT(bp); 2995 u32 val; 2996 2997 /* save current value of input enable for TX port IF */ 2998 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4); 2999 /* disable input for TX port IF */ 3000 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0); 3001 3002 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false); 3003 rc = bnx2x_nic_load(bp, LOAD_DIAG); 3004 if (rc) { 3005 etest->flags |= ETH_TEST_FL_FAILED; 3006 DP(BNX2X_MSG_ETHTOOL, 3007 "Can't perform self-test, nic_load (for offline) failed\n"); 3008 return; 3009 } 3010 3011 /* wait until link state is restored */ 3012 bnx2x_wait_for_link(bp, 1, is_serdes); 3013 3014 if (bnx2x_test_registers(bp) != 0) { 3015 buf[0] = 1; 3016 etest->flags |= ETH_TEST_FL_FAILED; 3017 } 3018 if (bnx2x_test_memory(bp) != 0) { 3019 buf[1] = 1; 3020 etest->flags |= ETH_TEST_FL_FAILED; 3021 } 3022 3023 buf[2] = bnx2x_test_loopback(bp); /* internal LB */ 3024 if (buf[2] != 0) 3025 etest->flags |= ETH_TEST_FL_FAILED; 3026 3027 if (etest->flags & ETH_TEST_FL_EXTERNAL_LB) { 3028 buf[3] = bnx2x_test_ext_loopback(bp); /* external LB */ 3029 if (buf[3] != 0) 3030 etest->flags |= ETH_TEST_FL_FAILED; 3031 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; 3032 } 3033 3034 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false); 3035 3036 /* restore input for TX port IF */ 3037 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val); 3038 rc = bnx2x_nic_load(bp, LOAD_NORMAL); 3039 if (rc) { 3040 etest->flags |= ETH_TEST_FL_FAILED; 3041 DP(BNX2X_MSG_ETHTOOL, 3042 "Can't perform self-test, nic_load (for online) failed\n"); 3043 return; 3044 } 3045 /* wait until link state is restored */ 3046 bnx2x_wait_for_link(bp, link_up, is_serdes); 3047 } 3048 3049 if (bnx2x_test_intr(bp) != 0) { 3050 if (!IS_MF(bp)) 3051 buf[5] = 1; 3052 else 3053 buf[1] = 1; 3054 etest->flags |= ETH_TEST_FL_FAILED; 3055 } 3056 3057 if (link_up) { 3058 cnt = 100; 3059 while (bnx2x_link_test(bp, is_serdes) && --cnt) 3060 msleep(20); 3061 } 3062 3063 if (!cnt) { 3064 if (!IS_MF(bp)) 3065 buf[6] = 1; 3066 else 3067 buf[2] = 1; 3068 etest->flags |= ETH_TEST_FL_FAILED; 3069 } 3070 } 3071 3072 #define IS_PORT_STAT(i) \ 3073 ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT) 3074 #define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC) 3075 #define HIDE_PORT_STAT(bp) \ 3076 ((IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS)) || \ 3077 IS_VF(bp)) 3078 3079 /* ethtool statistics are displayed for all regular ethernet queues and the 3080 * fcoe L2 queue if not disabled 3081 */ 3082 static int bnx2x_num_stat_queues(struct bnx2x *bp) 3083 { 3084 return BNX2X_NUM_ETH_QUEUES(bp); 3085 } 3086 3087 static int bnx2x_get_sset_count(struct net_device *dev, int stringset) 3088 { 3089 struct bnx2x *bp = netdev_priv(dev); 3090 int i, num_strings = 0; 3091 3092 switch (stringset) { 3093 case ETH_SS_STATS: 3094 if (is_multi(bp)) { 3095 num_strings = bnx2x_num_stat_queues(bp) * 3096 BNX2X_NUM_Q_STATS; 3097 } else 3098 num_strings = 0; 3099 if (HIDE_PORT_STAT(bp)) { 3100 for (i = 0; i < BNX2X_NUM_STATS; i++) 3101 if (IS_FUNC_STAT(i)) 3102 num_strings++; 3103 } else 3104 num_strings += BNX2X_NUM_STATS; 3105 3106 return num_strings; 3107 3108 case ETH_SS_TEST: 3109 return BNX2X_NUM_TESTS(bp); 3110 3111 case ETH_SS_PRIV_FLAGS: 3112 return BNX2X_PRI_FLAG_LEN; 3113 3114 default: 3115 return -EINVAL; 3116 } 3117 } 3118 3119 static u32 bnx2x_get_private_flags(struct net_device *dev) 3120 { 3121 struct bnx2x *bp = netdev_priv(dev); 3122 u32 flags = 0; 3123 3124 flags |= (!(bp->flags & NO_ISCSI_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_ISCSI; 3125 flags |= (!(bp->flags & NO_FCOE_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_FCOE; 3126 flags |= (!!IS_MF_STORAGE_ONLY(bp)) << BNX2X_PRI_FLAG_STORAGE; 3127 3128 return flags; 3129 } 3130 3131 static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf) 3132 { 3133 struct bnx2x *bp = netdev_priv(dev); 3134 int i, j, k, start; 3135 char queue_name[MAX_QUEUE_NAME_LEN+1]; 3136 3137 switch (stringset) { 3138 case ETH_SS_STATS: 3139 k = 0; 3140 if (is_multi(bp)) { 3141 for_each_eth_queue(bp, i) { 3142 memset(queue_name, 0, sizeof(queue_name)); 3143 sprintf(queue_name, "%d", i); 3144 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) 3145 snprintf(buf + (k + j)*ETH_GSTRING_LEN, 3146 ETH_GSTRING_LEN, 3147 bnx2x_q_stats_arr[j].string, 3148 queue_name); 3149 k += BNX2X_NUM_Q_STATS; 3150 } 3151 } 3152 3153 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { 3154 if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i)) 3155 continue; 3156 strcpy(buf + (k + j)*ETH_GSTRING_LEN, 3157 bnx2x_stats_arr[i].string); 3158 j++; 3159 } 3160 3161 break; 3162 3163 case ETH_SS_TEST: 3164 /* First 4 tests cannot be done in MF mode */ 3165 if (!IS_MF(bp)) 3166 start = 0; 3167 else 3168 start = 4; 3169 memcpy(buf, bnx2x_tests_str_arr + start, 3170 ETH_GSTRING_LEN * BNX2X_NUM_TESTS(bp)); 3171 break; 3172 3173 case ETH_SS_PRIV_FLAGS: 3174 memcpy(buf, bnx2x_private_arr, 3175 ETH_GSTRING_LEN * BNX2X_PRI_FLAG_LEN); 3176 break; 3177 } 3178 } 3179 3180 static void bnx2x_get_ethtool_stats(struct net_device *dev, 3181 struct ethtool_stats *stats, u64 *buf) 3182 { 3183 struct bnx2x *bp = netdev_priv(dev); 3184 u32 *hw_stats, *offset; 3185 int i, j, k = 0; 3186 3187 if (is_multi(bp)) { 3188 for_each_eth_queue(bp, i) { 3189 hw_stats = (u32 *)&bp->fp_stats[i].eth_q_stats; 3190 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) { 3191 if (bnx2x_q_stats_arr[j].size == 0) { 3192 /* skip this counter */ 3193 buf[k + j] = 0; 3194 continue; 3195 } 3196 offset = (hw_stats + 3197 bnx2x_q_stats_arr[j].offset); 3198 if (bnx2x_q_stats_arr[j].size == 4) { 3199 /* 4-byte counter */ 3200 buf[k + j] = (u64) *offset; 3201 continue; 3202 } 3203 /* 8-byte counter */ 3204 buf[k + j] = HILO_U64(*offset, *(offset + 1)); 3205 } 3206 k += BNX2X_NUM_Q_STATS; 3207 } 3208 } 3209 3210 hw_stats = (u32 *)&bp->eth_stats; 3211 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { 3212 if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i)) 3213 continue; 3214 if (bnx2x_stats_arr[i].size == 0) { 3215 /* skip this counter */ 3216 buf[k + j] = 0; 3217 j++; 3218 continue; 3219 } 3220 offset = (hw_stats + bnx2x_stats_arr[i].offset); 3221 if (bnx2x_stats_arr[i].size == 4) { 3222 /* 4-byte counter */ 3223 buf[k + j] = (u64) *offset; 3224 j++; 3225 continue; 3226 } 3227 /* 8-byte counter */ 3228 buf[k + j] = HILO_U64(*offset, *(offset + 1)); 3229 j++; 3230 } 3231 } 3232 3233 static int bnx2x_set_phys_id(struct net_device *dev, 3234 enum ethtool_phys_id_state state) 3235 { 3236 struct bnx2x *bp = netdev_priv(dev); 3237 3238 if (!bnx2x_is_nvm_accessible(bp)) { 3239 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, 3240 "cannot access eeprom when the interface is down\n"); 3241 return -EAGAIN; 3242 } 3243 3244 switch (state) { 3245 case ETHTOOL_ID_ACTIVE: 3246 return 1; /* cycle on/off once per second */ 3247 3248 case ETHTOOL_ID_ON: 3249 bnx2x_acquire_phy_lock(bp); 3250 bnx2x_set_led(&bp->link_params, &bp->link_vars, 3251 LED_MODE_ON, SPEED_1000); 3252 bnx2x_release_phy_lock(bp); 3253 break; 3254 3255 case ETHTOOL_ID_OFF: 3256 bnx2x_acquire_phy_lock(bp); 3257 bnx2x_set_led(&bp->link_params, &bp->link_vars, 3258 LED_MODE_FRONT_PANEL_OFF, 0); 3259 bnx2x_release_phy_lock(bp); 3260 break; 3261 3262 case ETHTOOL_ID_INACTIVE: 3263 bnx2x_acquire_phy_lock(bp); 3264 bnx2x_set_led(&bp->link_params, &bp->link_vars, 3265 LED_MODE_OPER, 3266 bp->link_vars.line_speed); 3267 bnx2x_release_phy_lock(bp); 3268 } 3269 3270 return 0; 3271 } 3272 3273 static int bnx2x_get_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info) 3274 { 3275 switch (info->flow_type) { 3276 case TCP_V4_FLOW: 3277 case TCP_V6_FLOW: 3278 info->data = RXH_IP_SRC | RXH_IP_DST | 3279 RXH_L4_B_0_1 | RXH_L4_B_2_3; 3280 break; 3281 case UDP_V4_FLOW: 3282 if (bp->rss_conf_obj.udp_rss_v4) 3283 info->data = RXH_IP_SRC | RXH_IP_DST | 3284 RXH_L4_B_0_1 | RXH_L4_B_2_3; 3285 else 3286 info->data = RXH_IP_SRC | RXH_IP_DST; 3287 break; 3288 case UDP_V6_FLOW: 3289 if (bp->rss_conf_obj.udp_rss_v6) 3290 info->data = RXH_IP_SRC | RXH_IP_DST | 3291 RXH_L4_B_0_1 | RXH_L4_B_2_3; 3292 else 3293 info->data = RXH_IP_SRC | RXH_IP_DST; 3294 break; 3295 case IPV4_FLOW: 3296 case IPV6_FLOW: 3297 info->data = RXH_IP_SRC | RXH_IP_DST; 3298 break; 3299 default: 3300 info->data = 0; 3301 break; 3302 } 3303 3304 return 0; 3305 } 3306 3307 static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info, 3308 u32 *rules __always_unused) 3309 { 3310 struct bnx2x *bp = netdev_priv(dev); 3311 3312 switch (info->cmd) { 3313 case ETHTOOL_GRXRINGS: 3314 info->data = BNX2X_NUM_ETH_QUEUES(bp); 3315 return 0; 3316 case ETHTOOL_GRXFH: 3317 return bnx2x_get_rss_flags(bp, info); 3318 default: 3319 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 3320 return -EOPNOTSUPP; 3321 } 3322 } 3323 3324 static int bnx2x_set_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info) 3325 { 3326 int udp_rss_requested; 3327 3328 DP(BNX2X_MSG_ETHTOOL, 3329 "Set rss flags command parameters: flow type = %d, data = %llu\n", 3330 info->flow_type, info->data); 3331 3332 switch (info->flow_type) { 3333 case TCP_V4_FLOW: 3334 case TCP_V6_FLOW: 3335 /* For TCP only 4-tupple hash is supported */ 3336 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST | 3337 RXH_L4_B_0_1 | RXH_L4_B_2_3)) { 3338 DP(BNX2X_MSG_ETHTOOL, 3339 "Command parameters not supported\n"); 3340 return -EINVAL; 3341 } 3342 return 0; 3343 3344 case UDP_V4_FLOW: 3345 case UDP_V6_FLOW: 3346 /* For UDP either 2-tupple hash or 4-tupple hash is supported */ 3347 if (info->data == (RXH_IP_SRC | RXH_IP_DST | 3348 RXH_L4_B_0_1 | RXH_L4_B_2_3)) 3349 udp_rss_requested = 1; 3350 else if (info->data == (RXH_IP_SRC | RXH_IP_DST)) 3351 udp_rss_requested = 0; 3352 else 3353 return -EINVAL; 3354 3355 if (CHIP_IS_E1x(bp) && udp_rss_requested) { 3356 DP(BNX2X_MSG_ETHTOOL, 3357 "57710, 57711 boards don't support RSS according to UDP 4-tuple\n"); 3358 return -EINVAL; 3359 } 3360 3361 if ((info->flow_type == UDP_V4_FLOW) && 3362 (bp->rss_conf_obj.udp_rss_v4 != udp_rss_requested)) { 3363 bp->rss_conf_obj.udp_rss_v4 = udp_rss_requested; 3364 DP(BNX2X_MSG_ETHTOOL, 3365 "rss re-configured, UDP 4-tupple %s\n", 3366 udp_rss_requested ? "enabled" : "disabled"); 3367 return bnx2x_rss(bp, &bp->rss_conf_obj, false, true); 3368 } else if ((info->flow_type == UDP_V6_FLOW) && 3369 (bp->rss_conf_obj.udp_rss_v6 != udp_rss_requested)) { 3370 bp->rss_conf_obj.udp_rss_v6 = udp_rss_requested; 3371 DP(BNX2X_MSG_ETHTOOL, 3372 "rss re-configured, UDP 4-tupple %s\n", 3373 udp_rss_requested ? "enabled" : "disabled"); 3374 return bnx2x_rss(bp, &bp->rss_conf_obj, false, true); 3375 } 3376 return 0; 3377 3378 case IPV4_FLOW: 3379 case IPV6_FLOW: 3380 /* For IP only 2-tupple hash is supported */ 3381 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST)) { 3382 DP(BNX2X_MSG_ETHTOOL, 3383 "Command parameters not supported\n"); 3384 return -EINVAL; 3385 } 3386 return 0; 3387 3388 case SCTP_V4_FLOW: 3389 case AH_ESP_V4_FLOW: 3390 case AH_V4_FLOW: 3391 case ESP_V4_FLOW: 3392 case SCTP_V6_FLOW: 3393 case AH_ESP_V6_FLOW: 3394 case AH_V6_FLOW: 3395 case ESP_V6_FLOW: 3396 case IP_USER_FLOW: 3397 case ETHER_FLOW: 3398 /* RSS is not supported for these protocols */ 3399 if (info->data) { 3400 DP(BNX2X_MSG_ETHTOOL, 3401 "Command parameters not supported\n"); 3402 return -EINVAL; 3403 } 3404 return 0; 3405 3406 default: 3407 return -EINVAL; 3408 } 3409 } 3410 3411 static int bnx2x_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info) 3412 { 3413 struct bnx2x *bp = netdev_priv(dev); 3414 3415 switch (info->cmd) { 3416 case ETHTOOL_SRXFH: 3417 return bnx2x_set_rss_flags(bp, info); 3418 default: 3419 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); 3420 return -EOPNOTSUPP; 3421 } 3422 } 3423 3424 static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev) 3425 { 3426 return T_ETH_INDIRECTION_TABLE_SIZE; 3427 } 3428 3429 static int bnx2x_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 3430 u8 *hfunc) 3431 { 3432 struct bnx2x *bp = netdev_priv(dev); 3433 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0}; 3434 size_t i; 3435 3436 if (hfunc) 3437 *hfunc = ETH_RSS_HASH_TOP; 3438 if (!indir) 3439 return 0; 3440 3441 /* Get the current configuration of the RSS indirection table */ 3442 bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table); 3443 3444 /* 3445 * We can't use a memcpy() as an internal storage of an 3446 * indirection table is a u8 array while indir->ring_index 3447 * points to an array of u32. 3448 * 3449 * Indirection table contains the FW Client IDs, so we need to 3450 * align the returned table to the Client ID of the leading RSS 3451 * queue. 3452 */ 3453 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) 3454 indir[i] = ind_table[i] - bp->fp->cl_id; 3455 3456 return 0; 3457 } 3458 3459 static int bnx2x_set_rxfh(struct net_device *dev, const u32 *indir, 3460 const u8 *key, const u8 hfunc) 3461 { 3462 struct bnx2x *bp = netdev_priv(dev); 3463 size_t i; 3464 3465 /* We require at least one supported parameter to be changed and no 3466 * change in any of the unsupported parameters 3467 */ 3468 if (key || 3469 (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP)) 3470 return -EOPNOTSUPP; 3471 3472 if (!indir) 3473 return 0; 3474 3475 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) { 3476 /* 3477 * The same as in bnx2x_get_rxfh: we can't use a memcpy() 3478 * as an internal storage of an indirection table is a u8 array 3479 * while indir->ring_index points to an array of u32. 3480 * 3481 * Indirection table contains the FW Client IDs, so we need to 3482 * align the received table to the Client ID of the leading RSS 3483 * queue 3484 */ 3485 bp->rss_conf_obj.ind_table[i] = indir[i] + bp->fp->cl_id; 3486 } 3487 3488 return bnx2x_config_rss_eth(bp, false); 3489 } 3490 3491 /** 3492 * bnx2x_get_channels - gets the number of RSS queues. 3493 * 3494 * @dev: net device 3495 * @channels: returns the number of max / current queues 3496 */ 3497 static void bnx2x_get_channels(struct net_device *dev, 3498 struct ethtool_channels *channels) 3499 { 3500 struct bnx2x *bp = netdev_priv(dev); 3501 3502 channels->max_combined = BNX2X_MAX_RSS_COUNT(bp); 3503 channels->combined_count = BNX2X_NUM_ETH_QUEUES(bp); 3504 } 3505 3506 /** 3507 * bnx2x_change_num_queues - change the number of RSS queues. 3508 * 3509 * @bp: bnx2x private structure 3510 * 3511 * Re-configure interrupt mode to get the new number of MSI-X 3512 * vectors and re-add NAPI objects. 3513 */ 3514 static void bnx2x_change_num_queues(struct bnx2x *bp, int num_rss) 3515 { 3516 bnx2x_disable_msi(bp); 3517 bp->num_ethernet_queues = num_rss; 3518 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues; 3519 BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues); 3520 bnx2x_set_int_mode(bp); 3521 } 3522 3523 /** 3524 * bnx2x_set_channels - sets the number of RSS queues. 3525 * 3526 * @dev: net device 3527 * @channels: includes the number of queues requested 3528 */ 3529 static int bnx2x_set_channels(struct net_device *dev, 3530 struct ethtool_channels *channels) 3531 { 3532 struct bnx2x *bp = netdev_priv(dev); 3533 3534 DP(BNX2X_MSG_ETHTOOL, 3535 "set-channels command parameters: rx = %d, tx = %d, other = %d, combined = %d\n", 3536 channels->rx_count, channels->tx_count, channels->other_count, 3537 channels->combined_count); 3538 3539 if (pci_num_vf(bp->pdev)) { 3540 DP(BNX2X_MSG_IOV, "VFs are enabled, can not set channels\n"); 3541 return -EPERM; 3542 } 3543 3544 /* We don't support separate rx / tx channels. 3545 * We don't allow setting 'other' channels. 3546 */ 3547 if (channels->rx_count || channels->tx_count || channels->other_count 3548 || (channels->combined_count == 0) || 3549 (channels->combined_count > BNX2X_MAX_RSS_COUNT(bp))) { 3550 DP(BNX2X_MSG_ETHTOOL, "command parameters not supported\n"); 3551 return -EINVAL; 3552 } 3553 3554 /* Check if there was a change in the active parameters */ 3555 if (channels->combined_count == BNX2X_NUM_ETH_QUEUES(bp)) { 3556 DP(BNX2X_MSG_ETHTOOL, "No change in active parameters\n"); 3557 return 0; 3558 } 3559 3560 /* Set the requested number of queues in bp context. 3561 * Note that the actual number of queues created during load may be 3562 * less than requested if memory is low. 3563 */ 3564 if (unlikely(!netif_running(dev))) { 3565 bnx2x_change_num_queues(bp, channels->combined_count); 3566 return 0; 3567 } 3568 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true); 3569 bnx2x_change_num_queues(bp, channels->combined_count); 3570 return bnx2x_nic_load(bp, LOAD_NORMAL); 3571 } 3572 3573 static int bnx2x_get_ts_info(struct net_device *dev, 3574 struct ethtool_ts_info *info) 3575 { 3576 struct bnx2x *bp = netdev_priv(dev); 3577 3578 if (bp->flags & PTP_SUPPORTED) { 3579 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 3580 SOF_TIMESTAMPING_RX_SOFTWARE | 3581 SOF_TIMESTAMPING_SOFTWARE | 3582 SOF_TIMESTAMPING_TX_HARDWARE | 3583 SOF_TIMESTAMPING_RX_HARDWARE | 3584 SOF_TIMESTAMPING_RAW_HARDWARE; 3585 3586 if (bp->ptp_clock) 3587 info->phc_index = ptp_clock_index(bp->ptp_clock); 3588 else 3589 info->phc_index = -1; 3590 3591 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 3592 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) | 3593 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) | 3594 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); 3595 3596 info->tx_types = (1 << HWTSTAMP_TX_OFF)|(1 << HWTSTAMP_TX_ON); 3597 3598 return 0; 3599 } 3600 3601 return ethtool_op_get_ts_info(dev, info); 3602 } 3603 3604 static const struct ethtool_ops bnx2x_ethtool_ops = { 3605 .get_settings = bnx2x_get_settings, 3606 .set_settings = bnx2x_set_settings, 3607 .get_drvinfo = bnx2x_get_drvinfo, 3608 .get_regs_len = bnx2x_get_regs_len, 3609 .get_regs = bnx2x_get_regs, 3610 .get_dump_flag = bnx2x_get_dump_flag, 3611 .get_dump_data = bnx2x_get_dump_data, 3612 .set_dump = bnx2x_set_dump, 3613 .get_wol = bnx2x_get_wol, 3614 .set_wol = bnx2x_set_wol, 3615 .get_msglevel = bnx2x_get_msglevel, 3616 .set_msglevel = bnx2x_set_msglevel, 3617 .nway_reset = bnx2x_nway_reset, 3618 .get_link = bnx2x_get_link, 3619 .get_eeprom_len = bnx2x_get_eeprom_len, 3620 .get_eeprom = bnx2x_get_eeprom, 3621 .set_eeprom = bnx2x_set_eeprom, 3622 .get_coalesce = bnx2x_get_coalesce, 3623 .set_coalesce = bnx2x_set_coalesce, 3624 .get_ringparam = bnx2x_get_ringparam, 3625 .set_ringparam = bnx2x_set_ringparam, 3626 .get_pauseparam = bnx2x_get_pauseparam, 3627 .set_pauseparam = bnx2x_set_pauseparam, 3628 .self_test = bnx2x_self_test, 3629 .get_sset_count = bnx2x_get_sset_count, 3630 .get_priv_flags = bnx2x_get_private_flags, 3631 .get_strings = bnx2x_get_strings, 3632 .set_phys_id = bnx2x_set_phys_id, 3633 .get_ethtool_stats = bnx2x_get_ethtool_stats, 3634 .get_rxnfc = bnx2x_get_rxnfc, 3635 .set_rxnfc = bnx2x_set_rxnfc, 3636 .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size, 3637 .get_rxfh = bnx2x_get_rxfh, 3638 .set_rxfh = bnx2x_set_rxfh, 3639 .get_channels = bnx2x_get_channels, 3640 .set_channels = bnx2x_set_channels, 3641 .get_module_info = bnx2x_get_module_info, 3642 .get_module_eeprom = bnx2x_get_module_eeprom, 3643 .get_eee = bnx2x_get_eee, 3644 .set_eee = bnx2x_set_eee, 3645 .get_ts_info = bnx2x_get_ts_info, 3646 }; 3647 3648 static const struct ethtool_ops bnx2x_vf_ethtool_ops = { 3649 .get_settings = bnx2x_get_vf_settings, 3650 .get_drvinfo = bnx2x_get_drvinfo, 3651 .get_msglevel = bnx2x_get_msglevel, 3652 .set_msglevel = bnx2x_set_msglevel, 3653 .get_link = bnx2x_get_link, 3654 .get_coalesce = bnx2x_get_coalesce, 3655 .get_ringparam = bnx2x_get_ringparam, 3656 .set_ringparam = bnx2x_set_ringparam, 3657 .get_sset_count = bnx2x_get_sset_count, 3658 .get_strings = bnx2x_get_strings, 3659 .get_ethtool_stats = bnx2x_get_ethtool_stats, 3660 .get_rxnfc = bnx2x_get_rxnfc, 3661 .set_rxnfc = bnx2x_set_rxnfc, 3662 .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size, 3663 .get_rxfh = bnx2x_get_rxfh, 3664 .set_rxfh = bnx2x_set_rxfh, 3665 .get_channels = bnx2x_get_channels, 3666 .set_channels = bnx2x_set_channels, 3667 }; 3668 3669 void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev) 3670 { 3671 netdev->ethtool_ops = (IS_PF(bp)) ? 3672 &bnx2x_ethtool_ops : &bnx2x_vf_ethtool_ops; 3673 } 3674