1 /* bnx2x_cmn.h: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2012 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 * 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com> 10 * Written by: Eliezer Tamir 11 * Based on code from Michael Chan's bnx2 driver 12 * UDP CSUM errata workaround by Arik Gendelman 13 * Slowpath and fastpath rework by Vladislav Zolotarov 14 * Statistics and Link management by Yitchak Gertner 15 * 16 */ 17 #ifndef BNX2X_CMN_H 18 #define BNX2X_CMN_H 19 20 #include <linux/types.h> 21 #include <linux/pci.h> 22 #include <linux/netdevice.h> 23 #include <linux/etherdevice.h> 24 25 26 #include "bnx2x.h" 27 28 /* This is used as a replacement for an MCP if it's not present */ 29 extern int load_count[2][3]; /* per-path: 0-common, 1-port0, 2-port1 */ 30 31 extern int num_queues; 32 extern int int_mode; 33 34 /************************ Macros ********************************/ 35 #define BNX2X_PCI_FREE(x, y, size) \ 36 do { \ 37 if (x) { \ 38 dma_free_coherent(&bp->pdev->dev, size, (void *)x, y); \ 39 x = NULL; \ 40 y = 0; \ 41 } \ 42 } while (0) 43 44 #define BNX2X_FREE(x) \ 45 do { \ 46 if (x) { \ 47 kfree((void *)x); \ 48 x = NULL; \ 49 } \ 50 } while (0) 51 52 #define BNX2X_PCI_ALLOC(x, y, size) \ 53 do { \ 54 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \ 55 if (x == NULL) \ 56 goto alloc_mem_err; \ 57 memset((void *)x, 0, size); \ 58 } while (0) 59 60 #define BNX2X_ALLOC(x, size) \ 61 do { \ 62 x = kzalloc(size, GFP_KERNEL); \ 63 if (x == NULL) \ 64 goto alloc_mem_err; \ 65 } while (0) 66 67 /*********************** Interfaces **************************** 68 * Functions that need to be implemented by each driver version 69 */ 70 /* Init */ 71 72 /** 73 * bnx2x_send_unload_req - request unload mode from the MCP. 74 * 75 * @bp: driver handle 76 * @unload_mode: requested function's unload mode 77 * 78 * Return unload mode returned by the MCP: COMMON, PORT or FUNC. 79 */ 80 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode); 81 82 /** 83 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP. 84 * 85 * @bp: driver handle 86 * @keep_link: true iff link should be kept up 87 */ 88 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link); 89 90 /** 91 * bnx2x_config_rss_pf - configure RSS parameters in a PF. 92 * 93 * @bp: driver handle 94 * @rss_obj: RSS object to use 95 * @ind_table: indirection table to configure 96 * @config_hash: re-configure RSS hash keys configuration 97 */ 98 int bnx2x_config_rss_pf(struct bnx2x *bp, struct bnx2x_rss_config_obj *rss_obj, 99 bool config_hash); 100 101 /** 102 * bnx2x__init_func_obj - init function object 103 * 104 * @bp: driver handle 105 * 106 * Initializes the Function Object with the appropriate 107 * parameters which include a function slow path driver 108 * interface. 109 */ 110 void bnx2x__init_func_obj(struct bnx2x *bp); 111 112 /** 113 * bnx2x_setup_queue - setup eth queue. 114 * 115 * @bp: driver handle 116 * @fp: pointer to the fastpath structure 117 * @leading: boolean 118 * 119 */ 120 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, 121 bool leading); 122 123 /** 124 * bnx2x_setup_leading - bring up a leading eth queue. 125 * 126 * @bp: driver handle 127 */ 128 int bnx2x_setup_leading(struct bnx2x *bp); 129 130 /** 131 * bnx2x_fw_command - send the MCP a request 132 * 133 * @bp: driver handle 134 * @command: request 135 * @param: request's parameter 136 * 137 * block until there is a reply 138 */ 139 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param); 140 141 /** 142 * bnx2x_initial_phy_init - initialize link parameters structure variables. 143 * 144 * @bp: driver handle 145 * @load_mode: current mode 146 */ 147 u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode); 148 149 /** 150 * bnx2x_link_set - configure hw according to link parameters structure. 151 * 152 * @bp: driver handle 153 */ 154 void bnx2x_link_set(struct bnx2x *bp); 155 156 /** 157 * bnx2x_force_link_reset - Forces link reset, and put the PHY 158 * in reset as well. 159 * 160 * @bp: driver handle 161 */ 162 void bnx2x_force_link_reset(struct bnx2x *bp); 163 164 /** 165 * bnx2x_link_test - query link status. 166 * 167 * @bp: driver handle 168 * @is_serdes: bool 169 * 170 * Returns 0 if link is UP. 171 */ 172 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes); 173 174 /** 175 * bnx2x_drv_pulse - write driver pulse to shmem 176 * 177 * @bp: driver handle 178 * 179 * writes the value in bp->fw_drv_pulse_wr_seq to drv_pulse mbox 180 * in the shmem. 181 */ 182 void bnx2x_drv_pulse(struct bnx2x *bp); 183 184 /** 185 * bnx2x_igu_ack_sb - update IGU with current SB value 186 * 187 * @bp: driver handle 188 * @igu_sb_id: SB id 189 * @segment: SB segment 190 * @index: SB index 191 * @op: SB operation 192 * @update: is HW update required 193 */ 194 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, 195 u16 index, u8 op, u8 update); 196 197 /* Disable transactions from chip to host */ 198 void bnx2x_pf_disable(struct bnx2x *bp); 199 200 /** 201 * bnx2x__link_status_update - handles link status change. 202 * 203 * @bp: driver handle 204 */ 205 void bnx2x__link_status_update(struct bnx2x *bp); 206 207 /** 208 * bnx2x_link_report - report link status to upper layer. 209 * 210 * @bp: driver handle 211 */ 212 void bnx2x_link_report(struct bnx2x *bp); 213 214 /* None-atomic version of bnx2x_link_report() */ 215 void __bnx2x_link_report(struct bnx2x *bp); 216 217 /** 218 * bnx2x_get_mf_speed - calculate MF speed. 219 * 220 * @bp: driver handle 221 * 222 * Takes into account current linespeed and MF configuration. 223 */ 224 u16 bnx2x_get_mf_speed(struct bnx2x *bp); 225 226 /** 227 * bnx2x_msix_sp_int - MSI-X slowpath interrupt handler 228 * 229 * @irq: irq number 230 * @dev_instance: private instance 231 */ 232 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance); 233 234 /** 235 * bnx2x_interrupt - non MSI-X interrupt handler 236 * 237 * @irq: irq number 238 * @dev_instance: private instance 239 */ 240 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance); 241 #ifdef BCM_CNIC 242 243 /** 244 * bnx2x_cnic_notify - send command to cnic driver 245 * 246 * @bp: driver handle 247 * @cmd: command 248 */ 249 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd); 250 251 /** 252 * bnx2x_setup_cnic_irq_info - provides cnic with IRQ information 253 * 254 * @bp: driver handle 255 */ 256 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp); 257 258 /** 259 * bnx2x_setup_cnic_info - provides cnic with updated info 260 * 261 * @bp: driver handle 262 */ 263 void bnx2x_setup_cnic_info(struct bnx2x *bp); 264 265 #endif 266 267 /** 268 * bnx2x_int_enable - enable HW interrupts. 269 * 270 * @bp: driver handle 271 */ 272 void bnx2x_int_enable(struct bnx2x *bp); 273 274 /** 275 * bnx2x_int_disable_sync - disable interrupts. 276 * 277 * @bp: driver handle 278 * @disable_hw: true, disable HW interrupts. 279 * 280 * This function ensures that there are no 281 * ISRs or SP DPCs (sp_task) are running after it returns. 282 */ 283 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw); 284 285 /** 286 * bnx2x_nic_init - init driver internals. 287 * 288 * @bp: driver handle 289 * @load_code: COMMON, PORT or FUNCTION 290 * 291 * Initializes: 292 * - rings 293 * - status blocks 294 * - etc. 295 */ 296 void bnx2x_nic_init(struct bnx2x *bp, u32 load_code); 297 298 /** 299 * bnx2x_alloc_mem - allocate driver's memory. 300 * 301 * @bp: driver handle 302 */ 303 int bnx2x_alloc_mem(struct bnx2x *bp); 304 305 /** 306 * bnx2x_free_mem - release driver's memory. 307 * 308 * @bp: driver handle 309 */ 310 void bnx2x_free_mem(struct bnx2x *bp); 311 312 /** 313 * bnx2x_set_num_queues - set number of queues according to mode. 314 * 315 * @bp: driver handle 316 */ 317 void bnx2x_set_num_queues(struct bnx2x *bp); 318 319 /** 320 * bnx2x_chip_cleanup - cleanup chip internals. 321 * 322 * @bp: driver handle 323 * @unload_mode: COMMON, PORT, FUNCTION 324 * @keep_link: true iff link should be kept up. 325 * 326 * - Cleanup MAC configuration. 327 * - Closes clients. 328 * - etc. 329 */ 330 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link); 331 332 /** 333 * bnx2x_acquire_hw_lock - acquire HW lock. 334 * 335 * @bp: driver handle 336 * @resource: resource bit which was locked 337 */ 338 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource); 339 340 /** 341 * bnx2x_release_hw_lock - release HW lock. 342 * 343 * @bp: driver handle 344 * @resource: resource bit which was locked 345 */ 346 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource); 347 348 /** 349 * bnx2x_release_leader_lock - release recovery leader lock 350 * 351 * @bp: driver handle 352 */ 353 int bnx2x_release_leader_lock(struct bnx2x *bp); 354 355 /** 356 * bnx2x_set_eth_mac - configure eth MAC address in the HW 357 * 358 * @bp: driver handle 359 * @set: set or clear 360 * 361 * Configures according to the value in netdev->dev_addr. 362 */ 363 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set); 364 365 /** 366 * bnx2x_set_rx_mode - set MAC filtering configurations. 367 * 368 * @dev: netdevice 369 * 370 * called with netif_tx_lock from dev_mcast.c 371 * If bp->state is OPEN, should be called with 372 * netif_addr_lock_bh() 373 */ 374 void bnx2x_set_rx_mode(struct net_device *dev); 375 376 /** 377 * bnx2x_set_storm_rx_mode - configure MAC filtering rules in a FW. 378 * 379 * @bp: driver handle 380 * 381 * If bp->state is OPEN, should be called with 382 * netif_addr_lock_bh(). 383 */ 384 void bnx2x_set_storm_rx_mode(struct bnx2x *bp); 385 386 /** 387 * bnx2x_set_q_rx_mode - configures rx_mode for a single queue. 388 * 389 * @bp: driver handle 390 * @cl_id: client id 391 * @rx_mode_flags: rx mode configuration 392 * @rx_accept_flags: rx accept configuration 393 * @tx_accept_flags: tx accept configuration (tx switch) 394 * @ramrod_flags: ramrod configuration 395 */ 396 void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id, 397 unsigned long rx_mode_flags, 398 unsigned long rx_accept_flags, 399 unsigned long tx_accept_flags, 400 unsigned long ramrod_flags); 401 402 /* Parity errors related */ 403 void bnx2x_set_pf_load(struct bnx2x *bp); 404 bool bnx2x_clear_pf_load(struct bnx2x *bp); 405 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print); 406 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine); 407 void bnx2x_set_reset_in_progress(struct bnx2x *bp); 408 void bnx2x_set_reset_global(struct bnx2x *bp); 409 void bnx2x_disable_close_the_gate(struct bnx2x *bp); 410 411 /** 412 * bnx2x_sp_event - handle ramrods completion. 413 * 414 * @fp: fastpath handle for the event 415 * @rr_cqe: eth_rx_cqe 416 */ 417 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe); 418 419 /** 420 * bnx2x_ilt_set_info - prepare ILT configurations. 421 * 422 * @bp: driver handle 423 */ 424 void bnx2x_ilt_set_info(struct bnx2x *bp); 425 426 /** 427 * bnx2x_dcbx_init - initialize dcbx protocol. 428 * 429 * @bp: driver handle 430 */ 431 void bnx2x_dcbx_init(struct bnx2x *bp, bool update_shmem); 432 433 /** 434 * bnx2x_set_power_state - set power state to the requested value. 435 * 436 * @bp: driver handle 437 * @state: required state D0 or D3hot 438 * 439 * Currently only D0 and D3hot are supported. 440 */ 441 int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state); 442 443 /** 444 * bnx2x_update_max_mf_config - update MAX part of MF configuration in HW. 445 * 446 * @bp: driver handle 447 * @value: new value 448 */ 449 void bnx2x_update_max_mf_config(struct bnx2x *bp, u32 value); 450 /* Error handling */ 451 void bnx2x_panic_dump(struct bnx2x *bp); 452 453 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl); 454 455 /* validate currect fw is loaded */ 456 bool bnx2x_test_firmware_version(struct bnx2x *bp, bool is_err); 457 458 /* dev_close main block */ 459 int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode, bool keep_link); 460 461 /* dev_open main block */ 462 int bnx2x_nic_load(struct bnx2x *bp, int load_mode); 463 464 /* hard_xmit callback */ 465 netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev); 466 467 /* setup_tc callback */ 468 int bnx2x_setup_tc(struct net_device *dev, u8 num_tc); 469 470 /* select_queue callback */ 471 u16 bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb); 472 473 /* reload helper */ 474 int bnx2x_reload_if_running(struct net_device *dev); 475 476 int bnx2x_change_mac_addr(struct net_device *dev, void *p); 477 478 /* NAPI poll Rx part */ 479 int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget); 480 481 void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp, 482 u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod); 483 484 /* NAPI poll Tx part */ 485 int bnx2x_tx_int(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata); 486 487 /* suspend/resume callbacks */ 488 int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state); 489 int bnx2x_resume(struct pci_dev *pdev); 490 491 /* Release IRQ vectors */ 492 void bnx2x_free_irq(struct bnx2x *bp); 493 494 void bnx2x_free_fp_mem(struct bnx2x *bp); 495 int bnx2x_alloc_fp_mem(struct bnx2x *bp); 496 void bnx2x_init_rx_rings(struct bnx2x *bp); 497 void bnx2x_free_skbs(struct bnx2x *bp); 498 void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw); 499 void bnx2x_netif_start(struct bnx2x *bp); 500 501 /** 502 * bnx2x_enable_msix - set msix configuration. 503 * 504 * @bp: driver handle 505 * 506 * fills msix_table, requests vectors, updates num_queues 507 * according to number of available vectors. 508 */ 509 int bnx2x_enable_msix(struct bnx2x *bp); 510 511 /** 512 * bnx2x_enable_msi - request msi mode from OS, updated internals accordingly 513 * 514 * @bp: driver handle 515 */ 516 int bnx2x_enable_msi(struct bnx2x *bp); 517 518 /** 519 * bnx2x_poll - NAPI callback 520 * 521 * @napi: napi structure 522 * @budget: 523 * 524 */ 525 int bnx2x_poll(struct napi_struct *napi, int budget); 526 527 /** 528 * bnx2x_alloc_mem_bp - allocate memories outsize main driver structure 529 * 530 * @bp: driver handle 531 */ 532 int __devinit bnx2x_alloc_mem_bp(struct bnx2x *bp); 533 534 /** 535 * bnx2x_free_mem_bp - release memories outsize main driver structure 536 * 537 * @bp: driver handle 538 */ 539 void bnx2x_free_mem_bp(struct bnx2x *bp); 540 541 /** 542 * bnx2x_change_mtu - change mtu netdev callback 543 * 544 * @dev: net device 545 * @new_mtu: requested mtu 546 * 547 */ 548 int bnx2x_change_mtu(struct net_device *dev, int new_mtu); 549 550 #if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC) 551 /** 552 * bnx2x_fcoe_get_wwn - return the requested WWN value for this port 553 * 554 * @dev: net_device 555 * @wwn: output buffer 556 * @type: WWN type: NETDEV_FCOE_WWNN (node) or NETDEV_FCOE_WWPN (port) 557 * 558 */ 559 int bnx2x_fcoe_get_wwn(struct net_device *dev, u64 *wwn, int type); 560 #endif 561 562 netdev_features_t bnx2x_fix_features(struct net_device *dev, 563 netdev_features_t features); 564 int bnx2x_set_features(struct net_device *dev, netdev_features_t features); 565 566 /** 567 * bnx2x_tx_timeout - tx timeout netdev callback 568 * 569 * @dev: net device 570 */ 571 void bnx2x_tx_timeout(struct net_device *dev); 572 573 /*********************** Inlines **********************************/ 574 /*********************** Fast path ********************************/ 575 static inline void bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp) 576 { 577 barrier(); /* status block is written to by the chip */ 578 fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID]; 579 } 580 581 static inline void bnx2x_update_rx_prod_gen(struct bnx2x *bp, 582 struct bnx2x_fastpath *fp, u16 bd_prod, 583 u16 rx_comp_prod, u16 rx_sge_prod, u32 start) 584 { 585 struct ustorm_eth_rx_producers rx_prods = {0}; 586 u32 i; 587 588 /* Update producers */ 589 rx_prods.bd_prod = bd_prod; 590 rx_prods.cqe_prod = rx_comp_prod; 591 rx_prods.sge_prod = rx_sge_prod; 592 593 /* 594 * Make sure that the BD and SGE data is updated before updating the 595 * producers since FW might read the BD/SGE right after the producer 596 * is updated. 597 * This is only applicable for weak-ordered memory model archs such 598 * as IA-64. The following barrier is also mandatory since FW will 599 * assumes BDs must have buffers. 600 */ 601 wmb(); 602 603 for (i = 0; i < sizeof(rx_prods)/4; i++) 604 REG_WR(bp, start + i*4, ((u32 *)&rx_prods)[i]); 605 606 mmiowb(); /* keep prod updates ordered */ 607 608 DP(NETIF_MSG_RX_STATUS, 609 "queue[%d]: wrote bd_prod %u cqe_prod %u sge_prod %u\n", 610 fp->index, bd_prod, rx_comp_prod, rx_sge_prod); 611 } 612 613 static inline void bnx2x_igu_ack_sb_gen(struct bnx2x *bp, u8 igu_sb_id, 614 u8 segment, u16 index, u8 op, 615 u8 update, u32 igu_addr) 616 { 617 struct igu_regular cmd_data = {0}; 618 619 cmd_data.sb_id_and_flags = 620 ((index << IGU_REGULAR_SB_INDEX_SHIFT) | 621 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) | 622 (update << IGU_REGULAR_BUPDATE_SHIFT) | 623 (op << IGU_REGULAR_ENABLE_INT_SHIFT)); 624 625 DP(NETIF_MSG_INTR, "write 0x%08x to IGU addr 0x%x\n", 626 cmd_data.sb_id_and_flags, igu_addr); 627 REG_WR(bp, igu_addr, cmd_data.sb_id_and_flags); 628 629 /* Make sure that ACK is written */ 630 mmiowb(); 631 barrier(); 632 } 633 634 static inline void bnx2x_hc_ack_sb(struct bnx2x *bp, u8 sb_id, 635 u8 storm, u16 index, u8 op, u8 update) 636 { 637 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 + 638 COMMAND_REG_INT_ACK); 639 struct igu_ack_register igu_ack; 640 641 igu_ack.status_block_index = index; 642 igu_ack.sb_id_and_flags = 643 ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) | 644 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) | 645 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) | 646 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT)); 647 648 REG_WR(bp, hc_addr, (*(u32 *)&igu_ack)); 649 650 /* Make sure that ACK is written */ 651 mmiowb(); 652 barrier(); 653 } 654 655 static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 storm, 656 u16 index, u8 op, u8 update) 657 { 658 if (bp->common.int_block == INT_BLOCK_HC) 659 bnx2x_hc_ack_sb(bp, igu_sb_id, storm, index, op, update); 660 else { 661 u8 segment; 662 663 if (CHIP_INT_MODE_IS_BC(bp)) 664 segment = storm; 665 else if (igu_sb_id != bp->igu_dsb_id) 666 segment = IGU_SEG_ACCESS_DEF; 667 else if (storm == ATTENTION_ID) 668 segment = IGU_SEG_ACCESS_ATTN; 669 else 670 segment = IGU_SEG_ACCESS_DEF; 671 bnx2x_igu_ack_sb(bp, igu_sb_id, segment, index, op, update); 672 } 673 } 674 675 static inline u16 bnx2x_hc_ack_int(struct bnx2x *bp) 676 { 677 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 + 678 COMMAND_REG_SIMD_MASK); 679 u32 result = REG_RD(bp, hc_addr); 680 681 barrier(); 682 return result; 683 } 684 685 static inline u16 bnx2x_igu_ack_int(struct bnx2x *bp) 686 { 687 u32 igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8); 688 u32 result = REG_RD(bp, igu_addr); 689 690 DP(NETIF_MSG_INTR, "read 0x%08x from IGU addr 0x%x\n", 691 result, igu_addr); 692 693 barrier(); 694 return result; 695 } 696 697 static inline u16 bnx2x_ack_int(struct bnx2x *bp) 698 { 699 barrier(); 700 if (bp->common.int_block == INT_BLOCK_HC) 701 return bnx2x_hc_ack_int(bp); 702 else 703 return bnx2x_igu_ack_int(bp); 704 } 705 706 static inline int bnx2x_has_tx_work_unload(struct bnx2x_fp_txdata *txdata) 707 { 708 /* Tell compiler that consumer and producer can change */ 709 barrier(); 710 return txdata->tx_pkt_prod != txdata->tx_pkt_cons; 711 } 712 713 static inline u16 bnx2x_tx_avail(struct bnx2x *bp, 714 struct bnx2x_fp_txdata *txdata) 715 { 716 s16 used; 717 u16 prod; 718 u16 cons; 719 720 prod = txdata->tx_bd_prod; 721 cons = txdata->tx_bd_cons; 722 723 used = SUB_S16(prod, cons); 724 725 #ifdef BNX2X_STOP_ON_ERROR 726 WARN_ON(used < 0); 727 WARN_ON(used > txdata->tx_ring_size); 728 WARN_ON((txdata->tx_ring_size - used) > MAX_TX_AVAIL); 729 #endif 730 731 return (s16)(txdata->tx_ring_size) - used; 732 } 733 734 static inline int bnx2x_tx_queue_has_work(struct bnx2x_fp_txdata *txdata) 735 { 736 u16 hw_cons; 737 738 /* Tell compiler that status block fields can change */ 739 barrier(); 740 hw_cons = le16_to_cpu(*txdata->tx_cons_sb); 741 return hw_cons != txdata->tx_pkt_cons; 742 } 743 744 static inline bool bnx2x_has_tx_work(struct bnx2x_fastpath *fp) 745 { 746 u8 cos; 747 for_each_cos_in_tx_queue(fp, cos) 748 if (bnx2x_tx_queue_has_work(fp->txdata_ptr[cos])) 749 return true; 750 return false; 751 } 752 753 static inline int bnx2x_has_rx_work(struct bnx2x_fastpath *fp) 754 { 755 u16 rx_cons_sb; 756 757 /* Tell compiler that status block fields can change */ 758 barrier(); 759 rx_cons_sb = le16_to_cpu(*fp->rx_cons_sb); 760 if ((rx_cons_sb & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT) 761 rx_cons_sb++; 762 return (fp->rx_comp_cons != rx_cons_sb); 763 } 764 765 /** 766 * bnx2x_tx_disable - disables tx from stack point of view 767 * 768 * @bp: driver handle 769 */ 770 static inline void bnx2x_tx_disable(struct bnx2x *bp) 771 { 772 netif_tx_disable(bp->dev); 773 netif_carrier_off(bp->dev); 774 } 775 776 static inline void bnx2x_free_rx_sge(struct bnx2x *bp, 777 struct bnx2x_fastpath *fp, u16 index) 778 { 779 struct sw_rx_page *sw_buf = &fp->rx_page_ring[index]; 780 struct page *page = sw_buf->page; 781 struct eth_rx_sge *sge = &fp->rx_sge_ring[index]; 782 783 /* Skip "next page" elements */ 784 if (!page) 785 return; 786 787 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(sw_buf, mapping), 788 SGE_PAGE_SIZE*PAGES_PER_SGE, DMA_FROM_DEVICE); 789 __free_pages(page, PAGES_PER_SGE_SHIFT); 790 791 sw_buf->page = NULL; 792 sge->addr_hi = 0; 793 sge->addr_lo = 0; 794 } 795 796 static inline void bnx2x_add_all_napi(struct bnx2x *bp) 797 { 798 int i; 799 800 bp->num_napi_queues = bp->num_queues; 801 802 /* Add NAPI objects */ 803 for_each_rx_queue(bp, i) 804 netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi), 805 bnx2x_poll, BNX2X_NAPI_WEIGHT); 806 } 807 808 static inline void bnx2x_del_all_napi(struct bnx2x *bp) 809 { 810 int i; 811 812 for_each_rx_queue(bp, i) 813 netif_napi_del(&bnx2x_fp(bp, i, napi)); 814 } 815 816 void bnx2x_set_int_mode(struct bnx2x *bp); 817 818 static inline void bnx2x_disable_msi(struct bnx2x *bp) 819 { 820 if (bp->flags & USING_MSIX_FLAG) { 821 pci_disable_msix(bp->pdev); 822 bp->flags &= ~(USING_MSIX_FLAG | USING_SINGLE_MSIX_FLAG); 823 } else if (bp->flags & USING_MSI_FLAG) { 824 pci_disable_msi(bp->pdev); 825 bp->flags &= ~USING_MSI_FLAG; 826 } 827 } 828 829 static inline int bnx2x_calc_num_queues(struct bnx2x *bp) 830 { 831 return num_queues ? 832 min_t(int, num_queues, BNX2X_MAX_QUEUES(bp)) : 833 min_t(int, netif_get_num_default_rss_queues(), 834 BNX2X_MAX_QUEUES(bp)); 835 } 836 837 static inline void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath *fp) 838 { 839 int i, j; 840 841 for (i = 1; i <= NUM_RX_SGE_PAGES; i++) { 842 int idx = RX_SGE_CNT * i - 1; 843 844 for (j = 0; j < 2; j++) { 845 BIT_VEC64_CLEAR_BIT(fp->sge_mask, idx); 846 idx--; 847 } 848 } 849 } 850 851 static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp) 852 { 853 /* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */ 854 memset(fp->sge_mask, 0xff, sizeof(fp->sge_mask)); 855 856 /* Clear the two last indices in the page to 1: 857 these are the indices that correspond to the "next" element, 858 hence will never be indicated and should be removed from 859 the calculations. */ 860 bnx2x_clear_sge_mask_next_elems(fp); 861 } 862 863 /* note that we are not allocating a new buffer, 864 * we are just moving one from cons to prod 865 * we are not creating a new mapping, 866 * so there is no need to check for dma_mapping_error(). 867 */ 868 static inline void bnx2x_reuse_rx_data(struct bnx2x_fastpath *fp, 869 u16 cons, u16 prod) 870 { 871 struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons]; 872 struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod]; 873 struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons]; 874 struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod]; 875 876 dma_unmap_addr_set(prod_rx_buf, mapping, 877 dma_unmap_addr(cons_rx_buf, mapping)); 878 prod_rx_buf->data = cons_rx_buf->data; 879 *prod_bd = *cons_bd; 880 } 881 882 /************************* Init ******************************************/ 883 884 /* returns func by VN for current port */ 885 static inline int func_by_vn(struct bnx2x *bp, int vn) 886 { 887 return 2 * vn + BP_PORT(bp); 888 } 889 890 static inline int bnx2x_config_rss_eth(struct bnx2x *bp, bool config_hash) 891 { 892 return bnx2x_config_rss_pf(bp, &bp->rss_conf_obj, config_hash); 893 } 894 895 /** 896 * bnx2x_func_start - init function 897 * 898 * @bp: driver handle 899 * 900 * Must be called before sending CLIENT_SETUP for the first client. 901 */ 902 static inline int bnx2x_func_start(struct bnx2x *bp) 903 { 904 struct bnx2x_func_state_params func_params = {NULL}; 905 struct bnx2x_func_start_params *start_params = 906 &func_params.params.start; 907 908 /* Prepare parameters for function state transitions */ 909 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 910 911 func_params.f_obj = &bp->func_obj; 912 func_params.cmd = BNX2X_F_CMD_START; 913 914 /* Function parameters */ 915 start_params->mf_mode = bp->mf_mode; 916 start_params->sd_vlan_tag = bp->mf_ov; 917 918 if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) 919 start_params->network_cos_mode = STATIC_COS; 920 else /* CHIP_IS_E1X */ 921 start_params->network_cos_mode = FW_WRR; 922 923 return bnx2x_func_state_change(bp, &func_params); 924 } 925 926 927 /** 928 * bnx2x_set_fw_mac_addr - fill in a MAC address in FW format 929 * 930 * @fw_hi: pointer to upper part 931 * @fw_mid: pointer to middle part 932 * @fw_lo: pointer to lower part 933 * @mac: pointer to MAC address 934 */ 935 static inline void bnx2x_set_fw_mac_addr(u16 *fw_hi, u16 *fw_mid, u16 *fw_lo, 936 u8 *mac) 937 { 938 ((u8 *)fw_hi)[0] = mac[1]; 939 ((u8 *)fw_hi)[1] = mac[0]; 940 ((u8 *)fw_mid)[0] = mac[3]; 941 ((u8 *)fw_mid)[1] = mac[2]; 942 ((u8 *)fw_lo)[0] = mac[5]; 943 ((u8 *)fw_lo)[1] = mac[4]; 944 } 945 946 static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp, 947 struct bnx2x_fastpath *fp, int last) 948 { 949 int i; 950 951 if (fp->disable_tpa) 952 return; 953 954 for (i = 0; i < last; i++) 955 bnx2x_free_rx_sge(bp, fp, i); 956 } 957 958 static inline void bnx2x_set_next_page_rx_bd(struct bnx2x_fastpath *fp) 959 { 960 int i; 961 962 for (i = 1; i <= NUM_RX_RINGS; i++) { 963 struct eth_rx_bd *rx_bd; 964 965 rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2]; 966 rx_bd->addr_hi = 967 cpu_to_le32(U64_HI(fp->rx_desc_mapping + 968 BCM_PAGE_SIZE*(i % NUM_RX_RINGS))); 969 rx_bd->addr_lo = 970 cpu_to_le32(U64_LO(fp->rx_desc_mapping + 971 BCM_PAGE_SIZE*(i % NUM_RX_RINGS))); 972 } 973 } 974 975 /* Statistics ID are global per chip/path, while Client IDs for E1x are per 976 * port. 977 */ 978 static inline u8 bnx2x_stats_id(struct bnx2x_fastpath *fp) 979 { 980 struct bnx2x *bp = fp->bp; 981 if (!CHIP_IS_E1x(bp)) { 982 #ifdef BCM_CNIC 983 /* there are special statistics counters for FCoE 136..140 */ 984 if (IS_FCOE_FP(fp)) 985 return bp->cnic_base_cl_id + (bp->pf_num >> 1); 986 #endif 987 return fp->cl_id; 988 } 989 return fp->cl_id + BP_PORT(bp) * FP_SB_MAX_E1x; 990 } 991 992 static inline void bnx2x_init_vlan_mac_fp_objs(struct bnx2x_fastpath *fp, 993 bnx2x_obj_type obj_type) 994 { 995 struct bnx2x *bp = fp->bp; 996 997 /* Configure classification DBs */ 998 bnx2x_init_mac_obj(bp, &bnx2x_sp_obj(bp, fp).mac_obj, fp->cl_id, 999 fp->cid, BP_FUNC(bp), bnx2x_sp(bp, mac_rdata), 1000 bnx2x_sp_mapping(bp, mac_rdata), 1001 BNX2X_FILTER_MAC_PENDING, 1002 &bp->sp_state, obj_type, 1003 &bp->macs_pool); 1004 } 1005 1006 /** 1007 * bnx2x_get_path_func_num - get number of active functions 1008 * 1009 * @bp: driver handle 1010 * 1011 * Calculates the number of active (not hidden) functions on the 1012 * current path. 1013 */ 1014 static inline u8 bnx2x_get_path_func_num(struct bnx2x *bp) 1015 { 1016 u8 func_num = 0, i; 1017 1018 /* 57710 has only one function per-port */ 1019 if (CHIP_IS_E1(bp)) 1020 return 1; 1021 1022 /* Calculate a number of functions enabled on the current 1023 * PATH/PORT. 1024 */ 1025 if (CHIP_REV_IS_SLOW(bp)) { 1026 if (IS_MF(bp)) 1027 func_num = 4; 1028 else 1029 func_num = 2; 1030 } else { 1031 for (i = 0; i < E1H_FUNC_MAX / 2; i++) { 1032 u32 func_config = 1033 MF_CFG_RD(bp, 1034 func_mf_config[BP_PORT(bp) + 2 * i]. 1035 config); 1036 func_num += 1037 ((func_config & FUNC_MF_CFG_FUNC_HIDE) ? 0 : 1); 1038 } 1039 } 1040 1041 WARN_ON(!func_num); 1042 1043 return func_num; 1044 } 1045 1046 static inline void bnx2x_init_bp_objs(struct bnx2x *bp) 1047 { 1048 /* RX_MODE controlling object */ 1049 bnx2x_init_rx_mode_obj(bp, &bp->rx_mode_obj); 1050 1051 /* multicast configuration controlling object */ 1052 bnx2x_init_mcast_obj(bp, &bp->mcast_obj, bp->fp->cl_id, bp->fp->cid, 1053 BP_FUNC(bp), BP_FUNC(bp), 1054 bnx2x_sp(bp, mcast_rdata), 1055 bnx2x_sp_mapping(bp, mcast_rdata), 1056 BNX2X_FILTER_MCAST_PENDING, &bp->sp_state, 1057 BNX2X_OBJ_TYPE_RX); 1058 1059 /* Setup CAM credit pools */ 1060 bnx2x_init_mac_credit_pool(bp, &bp->macs_pool, BP_FUNC(bp), 1061 bnx2x_get_path_func_num(bp)); 1062 1063 /* RSS configuration object */ 1064 bnx2x_init_rss_config_obj(bp, &bp->rss_conf_obj, bp->fp->cl_id, 1065 bp->fp->cid, BP_FUNC(bp), BP_FUNC(bp), 1066 bnx2x_sp(bp, rss_rdata), 1067 bnx2x_sp_mapping(bp, rss_rdata), 1068 BNX2X_FILTER_RSS_CONF_PENDING, &bp->sp_state, 1069 BNX2X_OBJ_TYPE_RX); 1070 } 1071 1072 static inline u8 bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp) 1073 { 1074 if (CHIP_IS_E1x(fp->bp)) 1075 return fp->cl_id + BP_PORT(fp->bp) * ETH_MAX_RX_CLIENTS_E1H; 1076 else 1077 return fp->cl_id; 1078 } 1079 1080 static inline u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp) 1081 { 1082 struct bnx2x *bp = fp->bp; 1083 1084 if (!CHIP_IS_E1x(bp)) 1085 return USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id); 1086 else 1087 return USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id); 1088 } 1089 1090 static inline void bnx2x_init_txdata(struct bnx2x *bp, 1091 struct bnx2x_fp_txdata *txdata, u32 cid, 1092 int txq_index, __le16 *tx_cons_sb, 1093 struct bnx2x_fastpath *fp) 1094 { 1095 txdata->cid = cid; 1096 txdata->txq_index = txq_index; 1097 txdata->tx_cons_sb = tx_cons_sb; 1098 txdata->parent_fp = fp; 1099 txdata->tx_ring_size = IS_FCOE_FP(fp) ? MAX_TX_AVAIL : bp->tx_ring_size; 1100 1101 DP(NETIF_MSG_IFUP, "created tx data cid %d, txq %d\n", 1102 txdata->cid, txdata->txq_index); 1103 } 1104 1105 #ifdef BCM_CNIC 1106 static inline u8 bnx2x_cnic_eth_cl_id(struct bnx2x *bp, u8 cl_idx) 1107 { 1108 return bp->cnic_base_cl_id + cl_idx + 1109 (bp->pf_num >> 1) * BNX2X_MAX_CNIC_ETH_CL_ID_IDX; 1110 } 1111 1112 static inline u8 bnx2x_cnic_fw_sb_id(struct bnx2x *bp) 1113 { 1114 1115 /* the 'first' id is allocated for the cnic */ 1116 return bp->base_fw_ndsb; 1117 } 1118 1119 static inline u8 bnx2x_cnic_igu_sb_id(struct bnx2x *bp) 1120 { 1121 return bp->igu_base_sb; 1122 } 1123 1124 1125 static inline void bnx2x_init_fcoe_fp(struct bnx2x *bp) 1126 { 1127 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); 1128 unsigned long q_type = 0; 1129 1130 bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp); 1131 bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp, 1132 BNX2X_FCOE_ETH_CL_ID_IDX); 1133 bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp); 1134 bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID; 1135 bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id; 1136 bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX; 1137 bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]), 1138 fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX, 1139 fp); 1140 1141 DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index); 1142 1143 /* qZone id equals to FW (per path) client id */ 1144 bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp); 1145 /* init shortcut */ 1146 bnx2x_fcoe(bp, ustorm_rx_prods_offset) = 1147 bnx2x_rx_ustorm_prods_offset(fp); 1148 1149 /* Configure Queue State object */ 1150 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); 1151 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); 1152 1153 /* No multi-CoS for FCoE L2 client */ 1154 BUG_ON(fp->max_cos != 1); 1155 1156 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, 1157 &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata), 1158 bnx2x_sp_mapping(bp, q_rdata), q_type); 1159 1160 DP(NETIF_MSG_IFUP, 1161 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n", 1162 fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, 1163 fp->igu_sb_id); 1164 } 1165 #endif 1166 1167 static inline int bnx2x_clean_tx_queue(struct bnx2x *bp, 1168 struct bnx2x_fp_txdata *txdata) 1169 { 1170 int cnt = 1000; 1171 1172 while (bnx2x_has_tx_work_unload(txdata)) { 1173 if (!cnt) { 1174 BNX2X_ERR("timeout waiting for queue[%d]: txdata->tx_pkt_prod(%d) != txdata->tx_pkt_cons(%d)\n", 1175 txdata->txq_index, txdata->tx_pkt_prod, 1176 txdata->tx_pkt_cons); 1177 #ifdef BNX2X_STOP_ON_ERROR 1178 bnx2x_panic(); 1179 return -EBUSY; 1180 #else 1181 break; 1182 #endif 1183 } 1184 cnt--; 1185 usleep_range(1000, 1000); 1186 } 1187 1188 return 0; 1189 } 1190 1191 int bnx2x_get_link_cfg_idx(struct bnx2x *bp); 1192 1193 static inline void __storm_memset_struct(struct bnx2x *bp, 1194 u32 addr, size_t size, u32 *data) 1195 { 1196 int i; 1197 for (i = 0; i < size/4; i++) 1198 REG_WR(bp, addr + (i * 4), data[i]); 1199 } 1200 1201 /** 1202 * bnx2x_wait_sp_comp - wait for the outstanding SP commands. 1203 * 1204 * @bp: driver handle 1205 * @mask: bits that need to be cleared 1206 */ 1207 static inline bool bnx2x_wait_sp_comp(struct bnx2x *bp, unsigned long mask) 1208 { 1209 int tout = 5000; /* Wait for 5 secs tops */ 1210 1211 while (tout--) { 1212 smp_mb(); 1213 netif_addr_lock_bh(bp->dev); 1214 if (!(bp->sp_state & mask)) { 1215 netif_addr_unlock_bh(bp->dev); 1216 return true; 1217 } 1218 netif_addr_unlock_bh(bp->dev); 1219 1220 usleep_range(1000, 1000); 1221 } 1222 1223 smp_mb(); 1224 1225 netif_addr_lock_bh(bp->dev); 1226 if (bp->sp_state & mask) { 1227 BNX2X_ERR("Filtering completion timed out. sp_state 0x%lx, mask 0x%lx\n", 1228 bp->sp_state, mask); 1229 netif_addr_unlock_bh(bp->dev); 1230 return false; 1231 } 1232 netif_addr_unlock_bh(bp->dev); 1233 1234 return true; 1235 } 1236 1237 /** 1238 * bnx2x_set_ctx_validation - set CDU context validation values 1239 * 1240 * @bp: driver handle 1241 * @cxt: context of the connection on the host memory 1242 * @cid: SW CID of the connection to be configured 1243 */ 1244 void bnx2x_set_ctx_validation(struct bnx2x *bp, struct eth_context *cxt, 1245 u32 cid); 1246 1247 void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, u8 fw_sb_id, 1248 u8 sb_index, u8 disable, u16 usec); 1249 void bnx2x_acquire_phy_lock(struct bnx2x *bp); 1250 void bnx2x_release_phy_lock(struct bnx2x *bp); 1251 1252 /** 1253 * bnx2x_extract_max_cfg - extract MAX BW part from MF configuration. 1254 * 1255 * @bp: driver handle 1256 * @mf_cfg: MF configuration 1257 * 1258 */ 1259 static inline u16 bnx2x_extract_max_cfg(struct bnx2x *bp, u32 mf_cfg) 1260 { 1261 u16 max_cfg = (mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >> 1262 FUNC_MF_CFG_MAX_BW_SHIFT; 1263 if (!max_cfg) { 1264 DP(NETIF_MSG_IFUP | BNX2X_MSG_ETHTOOL, 1265 "Max BW configured to 0 - using 100 instead\n"); 1266 max_cfg = 100; 1267 } 1268 return max_cfg; 1269 } 1270 1271 /* checks if HW supports GRO for given MTU */ 1272 static inline bool bnx2x_mtu_allows_gro(int mtu) 1273 { 1274 /* gro frags per page */ 1275 int fpp = SGE_PAGE_SIZE / (mtu - ETH_MAX_TPA_HEADER_SIZE); 1276 1277 /* 1278 * 1. number of frags should not grow above MAX_SKB_FRAGS 1279 * 2. frag must fit the page 1280 */ 1281 return mtu <= SGE_PAGE_SIZE && (U_ETH_SGL_SIZE * fpp) <= MAX_SKB_FRAGS; 1282 } 1283 #ifdef BCM_CNIC 1284 /** 1285 * bnx2x_get_iscsi_info - update iSCSI params according to licensing info. 1286 * 1287 * @bp: driver handle 1288 * 1289 */ 1290 void bnx2x_get_iscsi_info(struct bnx2x *bp); 1291 #endif 1292 1293 /** 1294 * bnx2x_link_sync_notify - send notification to other functions. 1295 * 1296 * @bp: driver handle 1297 * 1298 */ 1299 static inline void bnx2x_link_sync_notify(struct bnx2x *bp) 1300 { 1301 int func; 1302 int vn; 1303 1304 /* Set the attention towards other drivers on the same port */ 1305 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { 1306 if (vn == BP_VN(bp)) 1307 continue; 1308 1309 func = func_by_vn(bp, vn); 1310 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 + 1311 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1); 1312 } 1313 } 1314 1315 /** 1316 * bnx2x_update_drv_flags - update flags in shmem 1317 * 1318 * @bp: driver handle 1319 * @flags: flags to update 1320 * @set: set or clear 1321 * 1322 */ 1323 static inline void bnx2x_update_drv_flags(struct bnx2x *bp, u32 flags, u32 set) 1324 { 1325 if (SHMEM2_HAS(bp, drv_flags)) { 1326 u32 drv_flags; 1327 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS); 1328 drv_flags = SHMEM2_RD(bp, drv_flags); 1329 1330 if (set) 1331 SET_FLAGS(drv_flags, flags); 1332 else 1333 RESET_FLAGS(drv_flags, flags); 1334 1335 SHMEM2_WR(bp, drv_flags, drv_flags); 1336 DP(NETIF_MSG_IFUP, "drv_flags 0x%08x\n", drv_flags); 1337 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS); 1338 } 1339 } 1340 1341 static inline bool bnx2x_is_valid_ether_addr(struct bnx2x *bp, u8 *addr) 1342 { 1343 if (is_valid_ether_addr(addr)) 1344 return true; 1345 #ifdef BCM_CNIC 1346 if (is_zero_ether_addr(addr) && 1347 (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) 1348 return true; 1349 #endif 1350 return false; 1351 } 1352 1353 #endif /* BNX2X_CMN_H */ 1354