1 /* bnx2.c: QLogic bnx2 network driver. 2 * 3 * Copyright (c) 2004-2014 Broadcom Corporation 4 * Copyright (c) 2014-2015 QLogic Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 * 10 * Written by: Michael Chan (mchan@broadcom.com) 11 */ 12 13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 14 15 #include <linux/module.h> 16 #include <linux/moduleparam.h> 17 18 #include <linux/stringify.h> 19 #include <linux/kernel.h> 20 #include <linux/timer.h> 21 #include <linux/errno.h> 22 #include <linux/ioport.h> 23 #include <linux/slab.h> 24 #include <linux/vmalloc.h> 25 #include <linux/interrupt.h> 26 #include <linux/pci.h> 27 #include <linux/netdevice.h> 28 #include <linux/etherdevice.h> 29 #include <linux/skbuff.h> 30 #include <linux/dma-mapping.h> 31 #include <linux/bitops.h> 32 #include <asm/io.h> 33 #include <asm/irq.h> 34 #include <linux/delay.h> 35 #include <asm/byteorder.h> 36 #include <asm/page.h> 37 #include <linux/time.h> 38 #include <linux/ethtool.h> 39 #include <linux/mii.h> 40 #include <linux/if.h> 41 #include <linux/if_vlan.h> 42 #include <net/ip.h> 43 #include <net/tcp.h> 44 #include <net/checksum.h> 45 #include <linux/workqueue.h> 46 #include <linux/crc32.h> 47 #include <linux/prefetch.h> 48 #include <linux/cache.h> 49 #include <linux/firmware.h> 50 #include <linux/log2.h> 51 #include <linux/aer.h> 52 53 #if IS_ENABLED(CONFIG_CNIC) 54 #define BCM_CNIC 1 55 #include "cnic_if.h" 56 #endif 57 #include "bnx2.h" 58 #include "bnx2_fw.h" 59 60 #define DRV_MODULE_NAME "bnx2" 61 #define DRV_MODULE_VERSION "2.2.6" 62 #define DRV_MODULE_RELDATE "January 29, 2014" 63 #define FW_MIPS_FILE_06 "bnx2/bnx2-mips-06-6.2.3.fw" 64 #define FW_RV2P_FILE_06 "bnx2/bnx2-rv2p-06-6.0.15.fw" 65 #define FW_MIPS_FILE_09 "bnx2/bnx2-mips-09-6.2.1b.fw" 66 #define FW_RV2P_FILE_09_Ax "bnx2/bnx2-rv2p-09ax-6.0.17.fw" 67 #define FW_RV2P_FILE_09 "bnx2/bnx2-rv2p-09-6.0.17.fw" 68 69 #define RUN_AT(x) (jiffies + (x)) 70 71 /* Time in jiffies before concluding the transmitter is hung. */ 72 #define TX_TIMEOUT (5*HZ) 73 74 static char version[] = 75 "QLogic " DRV_MODULE_NAME " Gigabit Ethernet Driver v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; 76 77 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>"); 78 MODULE_DESCRIPTION("QLogic BCM5706/5708/5709/5716 Driver"); 79 MODULE_LICENSE("GPL"); 80 MODULE_VERSION(DRV_MODULE_VERSION); 81 MODULE_FIRMWARE(FW_MIPS_FILE_06); 82 MODULE_FIRMWARE(FW_RV2P_FILE_06); 83 MODULE_FIRMWARE(FW_MIPS_FILE_09); 84 MODULE_FIRMWARE(FW_RV2P_FILE_09); 85 MODULE_FIRMWARE(FW_RV2P_FILE_09_Ax); 86 87 static int disable_msi = 0; 88 89 module_param(disable_msi, int, S_IRUGO); 90 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)"); 91 92 typedef enum { 93 BCM5706 = 0, 94 NC370T, 95 NC370I, 96 BCM5706S, 97 NC370F, 98 BCM5708, 99 BCM5708S, 100 BCM5709, 101 BCM5709S, 102 BCM5716, 103 BCM5716S, 104 } board_t; 105 106 /* indexed by board_t, above */ 107 static struct { 108 char *name; 109 } board_info[] = { 110 { "Broadcom NetXtreme II BCM5706 1000Base-T" }, 111 { "HP NC370T Multifunction Gigabit Server Adapter" }, 112 { "HP NC370i Multifunction Gigabit Server Adapter" }, 113 { "Broadcom NetXtreme II BCM5706 1000Base-SX" }, 114 { "HP NC370F Multifunction Gigabit Server Adapter" }, 115 { "Broadcom NetXtreme II BCM5708 1000Base-T" }, 116 { "Broadcom NetXtreme II BCM5708 1000Base-SX" }, 117 { "Broadcom NetXtreme II BCM5709 1000Base-T" }, 118 { "Broadcom NetXtreme II BCM5709 1000Base-SX" }, 119 { "Broadcom NetXtreme II BCM5716 1000Base-T" }, 120 { "Broadcom NetXtreme II BCM5716 1000Base-SX" }, 121 }; 122 123 static const struct pci_device_id bnx2_pci_tbl[] = { 124 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706, 125 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T }, 126 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706, 127 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I }, 128 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706, 129 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 }, 130 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708, 131 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 }, 132 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S, 133 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F }, 134 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S, 135 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S }, 136 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S, 137 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S }, 138 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709, 139 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 }, 140 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S, 141 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S }, 142 { PCI_VENDOR_ID_BROADCOM, 0x163b, 143 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 }, 144 { PCI_VENDOR_ID_BROADCOM, 0x163c, 145 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716S }, 146 { 0, } 147 }; 148 149 static const struct flash_spec flash_table[] = 150 { 151 #define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE) 152 #define NONBUFFERED_FLAGS (BNX2_NV_WREN) 153 /* Slow EEPROM */ 154 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, 155 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 156 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 157 "EEPROM - slow"}, 158 /* Expansion entry 0001 */ 159 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, 160 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 161 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 162 "Entry 0001"}, 163 /* Saifun SA25F010 (non-buffered flash) */ 164 /* strap, cfg1, & write1 need updates */ 165 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, 166 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 167 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, 168 "Non-buffered flash (128kB)"}, 169 /* Saifun SA25F020 (non-buffered flash) */ 170 /* strap, cfg1, & write1 need updates */ 171 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, 172 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 173 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, 174 "Non-buffered flash (256kB)"}, 175 /* Expansion entry 0100 */ 176 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, 177 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 178 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 179 "Entry 0100"}, 180 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ 181 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, 182 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 183 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, 184 "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, 185 /* Entry 0110: ST M45PE20 (non-buffered flash)*/ 186 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, 187 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 188 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, 189 "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, 190 /* Saifun SA25F005 (non-buffered flash) */ 191 /* strap, cfg1, & write1 need updates */ 192 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, 193 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 194 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, 195 "Non-buffered flash (64kB)"}, 196 /* Fast EEPROM */ 197 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, 198 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 199 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 200 "EEPROM - fast"}, 201 /* Expansion entry 1001 */ 202 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, 203 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 204 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 205 "Entry 1001"}, 206 /* Expansion entry 1010 */ 207 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, 208 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 209 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 210 "Entry 1010"}, 211 /* ATMEL AT45DB011B (buffered flash) */ 212 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, 213 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 214 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, 215 "Buffered flash (128kB)"}, 216 /* Expansion entry 1100 */ 217 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, 218 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 219 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 220 "Entry 1100"}, 221 /* Expansion entry 1101 */ 222 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, 223 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 224 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 225 "Entry 1101"}, 226 /* Ateml Expansion entry 1110 */ 227 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, 228 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 229 BUFFERED_FLASH_BYTE_ADDR_MASK, 0, 230 "Entry 1110 (Atmel)"}, 231 /* ATMEL AT45DB021B (buffered flash) */ 232 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, 233 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 234 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, 235 "Buffered flash (256kB)"}, 236 }; 237 238 static const struct flash_spec flash_5709 = { 239 .flags = BNX2_NV_BUFFERED, 240 .page_bits = BCM5709_FLASH_PAGE_BITS, 241 .page_size = BCM5709_FLASH_PAGE_SIZE, 242 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK, 243 .total_size = BUFFERED_FLASH_TOTAL_SIZE*2, 244 .name = "5709 Buffered flash (256kB)", 245 }; 246 247 MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl); 248 249 static void bnx2_init_napi(struct bnx2 *bp); 250 static void bnx2_del_napi(struct bnx2 *bp); 251 252 static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr) 253 { 254 u32 diff; 255 256 /* Tell compiler to fetch tx_prod and tx_cons from memory. */ 257 barrier(); 258 259 /* The ring uses 256 indices for 255 entries, one of them 260 * needs to be skipped. 261 */ 262 diff = txr->tx_prod - txr->tx_cons; 263 if (unlikely(diff >= BNX2_TX_DESC_CNT)) { 264 diff &= 0xffff; 265 if (diff == BNX2_TX_DESC_CNT) 266 diff = BNX2_MAX_TX_DESC_CNT; 267 } 268 return bp->tx_ring_size - diff; 269 } 270 271 static u32 272 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset) 273 { 274 u32 val; 275 276 spin_lock_bh(&bp->indirect_lock); 277 BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset); 278 val = BNX2_RD(bp, BNX2_PCICFG_REG_WINDOW); 279 spin_unlock_bh(&bp->indirect_lock); 280 return val; 281 } 282 283 static void 284 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val) 285 { 286 spin_lock_bh(&bp->indirect_lock); 287 BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset); 288 BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW, val); 289 spin_unlock_bh(&bp->indirect_lock); 290 } 291 292 static void 293 bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val) 294 { 295 bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val); 296 } 297 298 static u32 299 bnx2_shmem_rd(struct bnx2 *bp, u32 offset) 300 { 301 return bnx2_reg_rd_ind(bp, bp->shmem_base + offset); 302 } 303 304 static void 305 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val) 306 { 307 offset += cid_addr; 308 spin_lock_bh(&bp->indirect_lock); 309 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { 310 int i; 311 312 BNX2_WR(bp, BNX2_CTX_CTX_DATA, val); 313 BNX2_WR(bp, BNX2_CTX_CTX_CTRL, 314 offset | BNX2_CTX_CTX_CTRL_WRITE_REQ); 315 for (i = 0; i < 5; i++) { 316 val = BNX2_RD(bp, BNX2_CTX_CTX_CTRL); 317 if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0) 318 break; 319 udelay(5); 320 } 321 } else { 322 BNX2_WR(bp, BNX2_CTX_DATA_ADR, offset); 323 BNX2_WR(bp, BNX2_CTX_DATA, val); 324 } 325 spin_unlock_bh(&bp->indirect_lock); 326 } 327 328 #ifdef BCM_CNIC 329 static int 330 bnx2_drv_ctl(struct net_device *dev, struct drv_ctl_info *info) 331 { 332 struct bnx2 *bp = netdev_priv(dev); 333 struct drv_ctl_io *io = &info->data.io; 334 335 switch (info->cmd) { 336 case DRV_CTL_IO_WR_CMD: 337 bnx2_reg_wr_ind(bp, io->offset, io->data); 338 break; 339 case DRV_CTL_IO_RD_CMD: 340 io->data = bnx2_reg_rd_ind(bp, io->offset); 341 break; 342 case DRV_CTL_CTX_WR_CMD: 343 bnx2_ctx_wr(bp, io->cid_addr, io->offset, io->data); 344 break; 345 default: 346 return -EINVAL; 347 } 348 return 0; 349 } 350 351 static void bnx2_setup_cnic_irq_info(struct bnx2 *bp) 352 { 353 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 354 struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; 355 int sb_id; 356 357 if (bp->flags & BNX2_FLAG_USING_MSIX) { 358 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX; 359 bnapi->cnic_present = 0; 360 sb_id = bp->irq_nvecs; 361 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX; 362 } else { 363 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX; 364 bnapi->cnic_tag = bnapi->last_status_idx; 365 bnapi->cnic_present = 1; 366 sb_id = 0; 367 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX; 368 } 369 370 cp->irq_arr[0].vector = bp->irq_tbl[sb_id].vector; 371 cp->irq_arr[0].status_blk = (void *) 372 ((unsigned long) bnapi->status_blk.msi + 373 (BNX2_SBLK_MSIX_ALIGN_SIZE * sb_id)); 374 cp->irq_arr[0].status_blk_num = sb_id; 375 cp->num_irq = 1; 376 } 377 378 static int bnx2_register_cnic(struct net_device *dev, struct cnic_ops *ops, 379 void *data) 380 { 381 struct bnx2 *bp = netdev_priv(dev); 382 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 383 384 if (ops == NULL) 385 return -EINVAL; 386 387 if (cp->drv_state & CNIC_DRV_STATE_REGD) 388 return -EBUSY; 389 390 if (!bnx2_reg_rd_ind(bp, BNX2_FW_MAX_ISCSI_CONN)) 391 return -ENODEV; 392 393 bp->cnic_data = data; 394 rcu_assign_pointer(bp->cnic_ops, ops); 395 396 cp->num_irq = 0; 397 cp->drv_state = CNIC_DRV_STATE_REGD; 398 399 bnx2_setup_cnic_irq_info(bp); 400 401 return 0; 402 } 403 404 static int bnx2_unregister_cnic(struct net_device *dev) 405 { 406 struct bnx2 *bp = netdev_priv(dev); 407 struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; 408 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 409 410 mutex_lock(&bp->cnic_lock); 411 cp->drv_state = 0; 412 bnapi->cnic_present = 0; 413 RCU_INIT_POINTER(bp->cnic_ops, NULL); 414 mutex_unlock(&bp->cnic_lock); 415 synchronize_rcu(); 416 return 0; 417 } 418 419 static struct cnic_eth_dev *bnx2_cnic_probe(struct net_device *dev) 420 { 421 struct bnx2 *bp = netdev_priv(dev); 422 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 423 424 if (!cp->max_iscsi_conn) 425 return NULL; 426 427 cp->drv_owner = THIS_MODULE; 428 cp->chip_id = bp->chip_id; 429 cp->pdev = bp->pdev; 430 cp->io_base = bp->regview; 431 cp->drv_ctl = bnx2_drv_ctl; 432 cp->drv_register_cnic = bnx2_register_cnic; 433 cp->drv_unregister_cnic = bnx2_unregister_cnic; 434 435 return cp; 436 } 437 438 static void 439 bnx2_cnic_stop(struct bnx2 *bp) 440 { 441 struct cnic_ops *c_ops; 442 struct cnic_ctl_info info; 443 444 mutex_lock(&bp->cnic_lock); 445 c_ops = rcu_dereference_protected(bp->cnic_ops, 446 lockdep_is_held(&bp->cnic_lock)); 447 if (c_ops) { 448 info.cmd = CNIC_CTL_STOP_CMD; 449 c_ops->cnic_ctl(bp->cnic_data, &info); 450 } 451 mutex_unlock(&bp->cnic_lock); 452 } 453 454 static void 455 bnx2_cnic_start(struct bnx2 *bp) 456 { 457 struct cnic_ops *c_ops; 458 struct cnic_ctl_info info; 459 460 mutex_lock(&bp->cnic_lock); 461 c_ops = rcu_dereference_protected(bp->cnic_ops, 462 lockdep_is_held(&bp->cnic_lock)); 463 if (c_ops) { 464 if (!(bp->flags & BNX2_FLAG_USING_MSIX)) { 465 struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; 466 467 bnapi->cnic_tag = bnapi->last_status_idx; 468 } 469 info.cmd = CNIC_CTL_START_CMD; 470 c_ops->cnic_ctl(bp->cnic_data, &info); 471 } 472 mutex_unlock(&bp->cnic_lock); 473 } 474 475 #else 476 477 static void 478 bnx2_cnic_stop(struct bnx2 *bp) 479 { 480 } 481 482 static void 483 bnx2_cnic_start(struct bnx2 *bp) 484 { 485 } 486 487 #endif 488 489 static int 490 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val) 491 { 492 u32 val1; 493 int i, ret; 494 495 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) { 496 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); 497 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL; 498 499 BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1); 500 BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); 501 502 udelay(40); 503 } 504 505 val1 = (bp->phy_addr << 21) | (reg << 16) | 506 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT | 507 BNX2_EMAC_MDIO_COMM_START_BUSY; 508 BNX2_WR(bp, BNX2_EMAC_MDIO_COMM, val1); 509 510 for (i = 0; i < 50; i++) { 511 udelay(10); 512 513 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM); 514 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) { 515 udelay(5); 516 517 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM); 518 val1 &= BNX2_EMAC_MDIO_COMM_DATA; 519 520 break; 521 } 522 } 523 524 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) { 525 *val = 0x0; 526 ret = -EBUSY; 527 } 528 else { 529 *val = val1; 530 ret = 0; 531 } 532 533 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) { 534 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); 535 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL; 536 537 BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1); 538 BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); 539 540 udelay(40); 541 } 542 543 return ret; 544 } 545 546 static int 547 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val) 548 { 549 u32 val1; 550 int i, ret; 551 552 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) { 553 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); 554 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL; 555 556 BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1); 557 BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); 558 559 udelay(40); 560 } 561 562 val1 = (bp->phy_addr << 21) | (reg << 16) | val | 563 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE | 564 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT; 565 BNX2_WR(bp, BNX2_EMAC_MDIO_COMM, val1); 566 567 for (i = 0; i < 50; i++) { 568 udelay(10); 569 570 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM); 571 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) { 572 udelay(5); 573 break; 574 } 575 } 576 577 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) 578 ret = -EBUSY; 579 else 580 ret = 0; 581 582 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) { 583 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); 584 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL; 585 586 BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1); 587 BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); 588 589 udelay(40); 590 } 591 592 return ret; 593 } 594 595 static void 596 bnx2_disable_int(struct bnx2 *bp) 597 { 598 int i; 599 struct bnx2_napi *bnapi; 600 601 for (i = 0; i < bp->irq_nvecs; i++) { 602 bnapi = &bp->bnx2_napi[i]; 603 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num | 604 BNX2_PCICFG_INT_ACK_CMD_MASK_INT); 605 } 606 BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD); 607 } 608 609 static void 610 bnx2_enable_int(struct bnx2 *bp) 611 { 612 int i; 613 struct bnx2_napi *bnapi; 614 615 for (i = 0; i < bp->irq_nvecs; i++) { 616 bnapi = &bp->bnx2_napi[i]; 617 618 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num | 619 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | 620 BNX2_PCICFG_INT_ACK_CMD_MASK_INT | 621 bnapi->last_status_idx); 622 623 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num | 624 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | 625 bnapi->last_status_idx); 626 } 627 BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW); 628 } 629 630 static void 631 bnx2_disable_int_sync(struct bnx2 *bp) 632 { 633 int i; 634 635 atomic_inc(&bp->intr_sem); 636 if (!netif_running(bp->dev)) 637 return; 638 639 bnx2_disable_int(bp); 640 for (i = 0; i < bp->irq_nvecs; i++) 641 synchronize_irq(bp->irq_tbl[i].vector); 642 } 643 644 static void 645 bnx2_napi_disable(struct bnx2 *bp) 646 { 647 int i; 648 649 for (i = 0; i < bp->irq_nvecs; i++) 650 napi_disable(&bp->bnx2_napi[i].napi); 651 } 652 653 static void 654 bnx2_napi_enable(struct bnx2 *bp) 655 { 656 int i; 657 658 for (i = 0; i < bp->irq_nvecs; i++) 659 napi_enable(&bp->bnx2_napi[i].napi); 660 } 661 662 static void 663 bnx2_netif_stop(struct bnx2 *bp, bool stop_cnic) 664 { 665 if (stop_cnic) 666 bnx2_cnic_stop(bp); 667 if (netif_running(bp->dev)) { 668 bnx2_napi_disable(bp); 669 netif_tx_disable(bp->dev); 670 } 671 bnx2_disable_int_sync(bp); 672 netif_carrier_off(bp->dev); /* prevent tx timeout */ 673 } 674 675 static void 676 bnx2_netif_start(struct bnx2 *bp, bool start_cnic) 677 { 678 if (atomic_dec_and_test(&bp->intr_sem)) { 679 if (netif_running(bp->dev)) { 680 netif_tx_wake_all_queues(bp->dev); 681 spin_lock_bh(&bp->phy_lock); 682 if (bp->link_up) 683 netif_carrier_on(bp->dev); 684 spin_unlock_bh(&bp->phy_lock); 685 bnx2_napi_enable(bp); 686 bnx2_enable_int(bp); 687 if (start_cnic) 688 bnx2_cnic_start(bp); 689 } 690 } 691 } 692 693 static void 694 bnx2_free_tx_mem(struct bnx2 *bp) 695 { 696 int i; 697 698 for (i = 0; i < bp->num_tx_rings; i++) { 699 struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; 700 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; 701 702 if (txr->tx_desc_ring) { 703 dma_free_coherent(&bp->pdev->dev, TXBD_RING_SIZE, 704 txr->tx_desc_ring, 705 txr->tx_desc_mapping); 706 txr->tx_desc_ring = NULL; 707 } 708 kfree(txr->tx_buf_ring); 709 txr->tx_buf_ring = NULL; 710 } 711 } 712 713 static void 714 bnx2_free_rx_mem(struct bnx2 *bp) 715 { 716 int i; 717 718 for (i = 0; i < bp->num_rx_rings; i++) { 719 struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; 720 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; 721 int j; 722 723 for (j = 0; j < bp->rx_max_ring; j++) { 724 if (rxr->rx_desc_ring[j]) 725 dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE, 726 rxr->rx_desc_ring[j], 727 rxr->rx_desc_mapping[j]); 728 rxr->rx_desc_ring[j] = NULL; 729 } 730 vfree(rxr->rx_buf_ring); 731 rxr->rx_buf_ring = NULL; 732 733 for (j = 0; j < bp->rx_max_pg_ring; j++) { 734 if (rxr->rx_pg_desc_ring[j]) 735 dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE, 736 rxr->rx_pg_desc_ring[j], 737 rxr->rx_pg_desc_mapping[j]); 738 rxr->rx_pg_desc_ring[j] = NULL; 739 } 740 vfree(rxr->rx_pg_ring); 741 rxr->rx_pg_ring = NULL; 742 } 743 } 744 745 static int 746 bnx2_alloc_tx_mem(struct bnx2 *bp) 747 { 748 int i; 749 750 for (i = 0; i < bp->num_tx_rings; i++) { 751 struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; 752 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; 753 754 txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL); 755 if (txr->tx_buf_ring == NULL) 756 return -ENOMEM; 757 758 txr->tx_desc_ring = 759 dma_alloc_coherent(&bp->pdev->dev, TXBD_RING_SIZE, 760 &txr->tx_desc_mapping, GFP_KERNEL); 761 if (txr->tx_desc_ring == NULL) 762 return -ENOMEM; 763 } 764 return 0; 765 } 766 767 static int 768 bnx2_alloc_rx_mem(struct bnx2 *bp) 769 { 770 int i; 771 772 for (i = 0; i < bp->num_rx_rings; i++) { 773 struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; 774 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; 775 int j; 776 777 rxr->rx_buf_ring = 778 vzalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring); 779 if (rxr->rx_buf_ring == NULL) 780 return -ENOMEM; 781 782 for (j = 0; j < bp->rx_max_ring; j++) { 783 rxr->rx_desc_ring[j] = 784 dma_alloc_coherent(&bp->pdev->dev, 785 RXBD_RING_SIZE, 786 &rxr->rx_desc_mapping[j], 787 GFP_KERNEL); 788 if (rxr->rx_desc_ring[j] == NULL) 789 return -ENOMEM; 790 791 } 792 793 if (bp->rx_pg_ring_size) { 794 rxr->rx_pg_ring = vzalloc(SW_RXPG_RING_SIZE * 795 bp->rx_max_pg_ring); 796 if (rxr->rx_pg_ring == NULL) 797 return -ENOMEM; 798 799 } 800 801 for (j = 0; j < bp->rx_max_pg_ring; j++) { 802 rxr->rx_pg_desc_ring[j] = 803 dma_alloc_coherent(&bp->pdev->dev, 804 RXBD_RING_SIZE, 805 &rxr->rx_pg_desc_mapping[j], 806 GFP_KERNEL); 807 if (rxr->rx_pg_desc_ring[j] == NULL) 808 return -ENOMEM; 809 810 } 811 } 812 return 0; 813 } 814 815 static void 816 bnx2_free_stats_blk(struct net_device *dev) 817 { 818 struct bnx2 *bp = netdev_priv(dev); 819 820 if (bp->status_blk) { 821 dma_free_coherent(&bp->pdev->dev, bp->status_stats_size, 822 bp->status_blk, 823 bp->status_blk_mapping); 824 bp->status_blk = NULL; 825 bp->stats_blk = NULL; 826 } 827 } 828 829 static int 830 bnx2_alloc_stats_blk(struct net_device *dev) 831 { 832 int status_blk_size; 833 void *status_blk; 834 struct bnx2 *bp = netdev_priv(dev); 835 836 /* Combine status and statistics blocks into one allocation. */ 837 status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block)); 838 if (bp->flags & BNX2_FLAG_MSIX_CAP) 839 status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC * 840 BNX2_SBLK_MSIX_ALIGN_SIZE); 841 bp->status_stats_size = status_blk_size + 842 sizeof(struct statistics_block); 843 status_blk = dma_zalloc_coherent(&bp->pdev->dev, bp->status_stats_size, 844 &bp->status_blk_mapping, GFP_KERNEL); 845 if (status_blk == NULL) 846 return -ENOMEM; 847 848 bp->status_blk = status_blk; 849 bp->stats_blk = status_blk + status_blk_size; 850 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size; 851 852 return 0; 853 } 854 855 static void 856 bnx2_free_mem(struct bnx2 *bp) 857 { 858 int i; 859 struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; 860 861 bnx2_free_tx_mem(bp); 862 bnx2_free_rx_mem(bp); 863 864 for (i = 0; i < bp->ctx_pages; i++) { 865 if (bp->ctx_blk[i]) { 866 dma_free_coherent(&bp->pdev->dev, BNX2_PAGE_SIZE, 867 bp->ctx_blk[i], 868 bp->ctx_blk_mapping[i]); 869 bp->ctx_blk[i] = NULL; 870 } 871 } 872 873 if (bnapi->status_blk.msi) 874 bnapi->status_blk.msi = NULL; 875 } 876 877 static int 878 bnx2_alloc_mem(struct bnx2 *bp) 879 { 880 int i, err; 881 struct bnx2_napi *bnapi; 882 883 bnapi = &bp->bnx2_napi[0]; 884 bnapi->status_blk.msi = bp->status_blk; 885 bnapi->hw_tx_cons_ptr = 886 &bnapi->status_blk.msi->status_tx_quick_consumer_index0; 887 bnapi->hw_rx_cons_ptr = 888 &bnapi->status_blk.msi->status_rx_quick_consumer_index0; 889 if (bp->flags & BNX2_FLAG_MSIX_CAP) { 890 for (i = 1; i < bp->irq_nvecs; i++) { 891 struct status_block_msix *sblk; 892 893 bnapi = &bp->bnx2_napi[i]; 894 895 sblk = (bp->status_blk + BNX2_SBLK_MSIX_ALIGN_SIZE * i); 896 bnapi->status_blk.msix = sblk; 897 bnapi->hw_tx_cons_ptr = 898 &sblk->status_tx_quick_consumer_index; 899 bnapi->hw_rx_cons_ptr = 900 &sblk->status_rx_quick_consumer_index; 901 bnapi->int_num = i << 24; 902 } 903 } 904 905 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { 906 bp->ctx_pages = 0x2000 / BNX2_PAGE_SIZE; 907 if (bp->ctx_pages == 0) 908 bp->ctx_pages = 1; 909 for (i = 0; i < bp->ctx_pages; i++) { 910 bp->ctx_blk[i] = dma_alloc_coherent(&bp->pdev->dev, 911 BNX2_PAGE_SIZE, 912 &bp->ctx_blk_mapping[i], 913 GFP_KERNEL); 914 if (bp->ctx_blk[i] == NULL) 915 goto alloc_mem_err; 916 } 917 } 918 919 err = bnx2_alloc_rx_mem(bp); 920 if (err) 921 goto alloc_mem_err; 922 923 err = bnx2_alloc_tx_mem(bp); 924 if (err) 925 goto alloc_mem_err; 926 927 return 0; 928 929 alloc_mem_err: 930 bnx2_free_mem(bp); 931 return -ENOMEM; 932 } 933 934 static void 935 bnx2_report_fw_link(struct bnx2 *bp) 936 { 937 u32 fw_link_status = 0; 938 939 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) 940 return; 941 942 if (bp->link_up) { 943 u32 bmsr; 944 945 switch (bp->line_speed) { 946 case SPEED_10: 947 if (bp->duplex == DUPLEX_HALF) 948 fw_link_status = BNX2_LINK_STATUS_10HALF; 949 else 950 fw_link_status = BNX2_LINK_STATUS_10FULL; 951 break; 952 case SPEED_100: 953 if (bp->duplex == DUPLEX_HALF) 954 fw_link_status = BNX2_LINK_STATUS_100HALF; 955 else 956 fw_link_status = BNX2_LINK_STATUS_100FULL; 957 break; 958 case SPEED_1000: 959 if (bp->duplex == DUPLEX_HALF) 960 fw_link_status = BNX2_LINK_STATUS_1000HALF; 961 else 962 fw_link_status = BNX2_LINK_STATUS_1000FULL; 963 break; 964 case SPEED_2500: 965 if (bp->duplex == DUPLEX_HALF) 966 fw_link_status = BNX2_LINK_STATUS_2500HALF; 967 else 968 fw_link_status = BNX2_LINK_STATUS_2500FULL; 969 break; 970 } 971 972 fw_link_status |= BNX2_LINK_STATUS_LINK_UP; 973 974 if (bp->autoneg) { 975 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED; 976 977 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); 978 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); 979 980 if (!(bmsr & BMSR_ANEGCOMPLETE) || 981 bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) 982 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET; 983 else 984 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE; 985 } 986 } 987 else 988 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN; 989 990 bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status); 991 } 992 993 static char * 994 bnx2_xceiver_str(struct bnx2 *bp) 995 { 996 return (bp->phy_port == PORT_FIBRE) ? "SerDes" : 997 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" : 998 "Copper"); 999 } 1000 1001 static void 1002 bnx2_report_link(struct bnx2 *bp) 1003 { 1004 if (bp->link_up) { 1005 netif_carrier_on(bp->dev); 1006 netdev_info(bp->dev, "NIC %s Link is Up, %d Mbps %s duplex", 1007 bnx2_xceiver_str(bp), 1008 bp->line_speed, 1009 bp->duplex == DUPLEX_FULL ? "full" : "half"); 1010 1011 if (bp->flow_ctrl) { 1012 if (bp->flow_ctrl & FLOW_CTRL_RX) { 1013 pr_cont(", receive "); 1014 if (bp->flow_ctrl & FLOW_CTRL_TX) 1015 pr_cont("& transmit "); 1016 } 1017 else { 1018 pr_cont(", transmit "); 1019 } 1020 pr_cont("flow control ON"); 1021 } 1022 pr_cont("\n"); 1023 } else { 1024 netif_carrier_off(bp->dev); 1025 netdev_err(bp->dev, "NIC %s Link is Down\n", 1026 bnx2_xceiver_str(bp)); 1027 } 1028 1029 bnx2_report_fw_link(bp); 1030 } 1031 1032 static void 1033 bnx2_resolve_flow_ctrl(struct bnx2 *bp) 1034 { 1035 u32 local_adv, remote_adv; 1036 1037 bp->flow_ctrl = 0; 1038 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) != 1039 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) { 1040 1041 if (bp->duplex == DUPLEX_FULL) { 1042 bp->flow_ctrl = bp->req_flow_ctrl; 1043 } 1044 return; 1045 } 1046 1047 if (bp->duplex != DUPLEX_FULL) { 1048 return; 1049 } 1050 1051 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && 1052 (BNX2_CHIP(bp) == BNX2_CHIP_5708)) { 1053 u32 val; 1054 1055 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val); 1056 if (val & BCM5708S_1000X_STAT1_TX_PAUSE) 1057 bp->flow_ctrl |= FLOW_CTRL_TX; 1058 if (val & BCM5708S_1000X_STAT1_RX_PAUSE) 1059 bp->flow_ctrl |= FLOW_CTRL_RX; 1060 return; 1061 } 1062 1063 bnx2_read_phy(bp, bp->mii_adv, &local_adv); 1064 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv); 1065 1066 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { 1067 u32 new_local_adv = 0; 1068 u32 new_remote_adv = 0; 1069 1070 if (local_adv & ADVERTISE_1000XPAUSE) 1071 new_local_adv |= ADVERTISE_PAUSE_CAP; 1072 if (local_adv & ADVERTISE_1000XPSE_ASYM) 1073 new_local_adv |= ADVERTISE_PAUSE_ASYM; 1074 if (remote_adv & ADVERTISE_1000XPAUSE) 1075 new_remote_adv |= ADVERTISE_PAUSE_CAP; 1076 if (remote_adv & ADVERTISE_1000XPSE_ASYM) 1077 new_remote_adv |= ADVERTISE_PAUSE_ASYM; 1078 1079 local_adv = new_local_adv; 1080 remote_adv = new_remote_adv; 1081 } 1082 1083 /* See Table 28B-3 of 802.3ab-1999 spec. */ 1084 if (local_adv & ADVERTISE_PAUSE_CAP) { 1085 if(local_adv & ADVERTISE_PAUSE_ASYM) { 1086 if (remote_adv & ADVERTISE_PAUSE_CAP) { 1087 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; 1088 } 1089 else if (remote_adv & ADVERTISE_PAUSE_ASYM) { 1090 bp->flow_ctrl = FLOW_CTRL_RX; 1091 } 1092 } 1093 else { 1094 if (remote_adv & ADVERTISE_PAUSE_CAP) { 1095 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; 1096 } 1097 } 1098 } 1099 else if (local_adv & ADVERTISE_PAUSE_ASYM) { 1100 if ((remote_adv & ADVERTISE_PAUSE_CAP) && 1101 (remote_adv & ADVERTISE_PAUSE_ASYM)) { 1102 1103 bp->flow_ctrl = FLOW_CTRL_TX; 1104 } 1105 } 1106 } 1107 1108 static int 1109 bnx2_5709s_linkup(struct bnx2 *bp) 1110 { 1111 u32 val, speed; 1112 1113 bp->link_up = 1; 1114 1115 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS); 1116 bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val); 1117 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0); 1118 1119 if ((bp->autoneg & AUTONEG_SPEED) == 0) { 1120 bp->line_speed = bp->req_line_speed; 1121 bp->duplex = bp->req_duplex; 1122 return 0; 1123 } 1124 speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK; 1125 switch (speed) { 1126 case MII_BNX2_GP_TOP_AN_SPEED_10: 1127 bp->line_speed = SPEED_10; 1128 break; 1129 case MII_BNX2_GP_TOP_AN_SPEED_100: 1130 bp->line_speed = SPEED_100; 1131 break; 1132 case MII_BNX2_GP_TOP_AN_SPEED_1G: 1133 case MII_BNX2_GP_TOP_AN_SPEED_1GKV: 1134 bp->line_speed = SPEED_1000; 1135 break; 1136 case MII_BNX2_GP_TOP_AN_SPEED_2_5G: 1137 bp->line_speed = SPEED_2500; 1138 break; 1139 } 1140 if (val & MII_BNX2_GP_TOP_AN_FD) 1141 bp->duplex = DUPLEX_FULL; 1142 else 1143 bp->duplex = DUPLEX_HALF; 1144 return 0; 1145 } 1146 1147 static int 1148 bnx2_5708s_linkup(struct bnx2 *bp) 1149 { 1150 u32 val; 1151 1152 bp->link_up = 1; 1153 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val); 1154 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) { 1155 case BCM5708S_1000X_STAT1_SPEED_10: 1156 bp->line_speed = SPEED_10; 1157 break; 1158 case BCM5708S_1000X_STAT1_SPEED_100: 1159 bp->line_speed = SPEED_100; 1160 break; 1161 case BCM5708S_1000X_STAT1_SPEED_1G: 1162 bp->line_speed = SPEED_1000; 1163 break; 1164 case BCM5708S_1000X_STAT1_SPEED_2G5: 1165 bp->line_speed = SPEED_2500; 1166 break; 1167 } 1168 if (val & BCM5708S_1000X_STAT1_FD) 1169 bp->duplex = DUPLEX_FULL; 1170 else 1171 bp->duplex = DUPLEX_HALF; 1172 1173 return 0; 1174 } 1175 1176 static int 1177 bnx2_5706s_linkup(struct bnx2 *bp) 1178 { 1179 u32 bmcr, local_adv, remote_adv, common; 1180 1181 bp->link_up = 1; 1182 bp->line_speed = SPEED_1000; 1183 1184 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); 1185 if (bmcr & BMCR_FULLDPLX) { 1186 bp->duplex = DUPLEX_FULL; 1187 } 1188 else { 1189 bp->duplex = DUPLEX_HALF; 1190 } 1191 1192 if (!(bmcr & BMCR_ANENABLE)) { 1193 return 0; 1194 } 1195 1196 bnx2_read_phy(bp, bp->mii_adv, &local_adv); 1197 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv); 1198 1199 common = local_adv & remote_adv; 1200 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) { 1201 1202 if (common & ADVERTISE_1000XFULL) { 1203 bp->duplex = DUPLEX_FULL; 1204 } 1205 else { 1206 bp->duplex = DUPLEX_HALF; 1207 } 1208 } 1209 1210 return 0; 1211 } 1212 1213 static int 1214 bnx2_copper_linkup(struct bnx2 *bp) 1215 { 1216 u32 bmcr; 1217 1218 bp->phy_flags &= ~BNX2_PHY_FLAG_MDIX; 1219 1220 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); 1221 if (bmcr & BMCR_ANENABLE) { 1222 u32 local_adv, remote_adv, common; 1223 1224 bnx2_read_phy(bp, MII_CTRL1000, &local_adv); 1225 bnx2_read_phy(bp, MII_STAT1000, &remote_adv); 1226 1227 common = local_adv & (remote_adv >> 2); 1228 if (common & ADVERTISE_1000FULL) { 1229 bp->line_speed = SPEED_1000; 1230 bp->duplex = DUPLEX_FULL; 1231 } 1232 else if (common & ADVERTISE_1000HALF) { 1233 bp->line_speed = SPEED_1000; 1234 bp->duplex = DUPLEX_HALF; 1235 } 1236 else { 1237 bnx2_read_phy(bp, bp->mii_adv, &local_adv); 1238 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv); 1239 1240 common = local_adv & remote_adv; 1241 if (common & ADVERTISE_100FULL) { 1242 bp->line_speed = SPEED_100; 1243 bp->duplex = DUPLEX_FULL; 1244 } 1245 else if (common & ADVERTISE_100HALF) { 1246 bp->line_speed = SPEED_100; 1247 bp->duplex = DUPLEX_HALF; 1248 } 1249 else if (common & ADVERTISE_10FULL) { 1250 bp->line_speed = SPEED_10; 1251 bp->duplex = DUPLEX_FULL; 1252 } 1253 else if (common & ADVERTISE_10HALF) { 1254 bp->line_speed = SPEED_10; 1255 bp->duplex = DUPLEX_HALF; 1256 } 1257 else { 1258 bp->line_speed = 0; 1259 bp->link_up = 0; 1260 } 1261 } 1262 } 1263 else { 1264 if (bmcr & BMCR_SPEED100) { 1265 bp->line_speed = SPEED_100; 1266 } 1267 else { 1268 bp->line_speed = SPEED_10; 1269 } 1270 if (bmcr & BMCR_FULLDPLX) { 1271 bp->duplex = DUPLEX_FULL; 1272 } 1273 else { 1274 bp->duplex = DUPLEX_HALF; 1275 } 1276 } 1277 1278 if (bp->link_up) { 1279 u32 ext_status; 1280 1281 bnx2_read_phy(bp, MII_BNX2_EXT_STATUS, &ext_status); 1282 if (ext_status & EXT_STATUS_MDIX) 1283 bp->phy_flags |= BNX2_PHY_FLAG_MDIX; 1284 } 1285 1286 return 0; 1287 } 1288 1289 static void 1290 bnx2_init_rx_context(struct bnx2 *bp, u32 cid) 1291 { 1292 u32 val, rx_cid_addr = GET_CID_ADDR(cid); 1293 1294 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE; 1295 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2; 1296 val |= 0x02 << 8; 1297 1298 if (bp->flow_ctrl & FLOW_CTRL_TX) 1299 val |= BNX2_L2CTX_FLOW_CTRL_ENABLE; 1300 1301 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val); 1302 } 1303 1304 static void 1305 bnx2_init_all_rx_contexts(struct bnx2 *bp) 1306 { 1307 int i; 1308 u32 cid; 1309 1310 for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) { 1311 if (i == 1) 1312 cid = RX_RSS_CID; 1313 bnx2_init_rx_context(bp, cid); 1314 } 1315 } 1316 1317 static void 1318 bnx2_set_mac_link(struct bnx2 *bp) 1319 { 1320 u32 val; 1321 1322 BNX2_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620); 1323 if (bp->link_up && (bp->line_speed == SPEED_1000) && 1324 (bp->duplex == DUPLEX_HALF)) { 1325 BNX2_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff); 1326 } 1327 1328 /* Configure the EMAC mode register. */ 1329 val = BNX2_RD(bp, BNX2_EMAC_MODE); 1330 1331 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX | 1332 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK | 1333 BNX2_EMAC_MODE_25G_MODE); 1334 1335 if (bp->link_up) { 1336 switch (bp->line_speed) { 1337 case SPEED_10: 1338 if (BNX2_CHIP(bp) != BNX2_CHIP_5706) { 1339 val |= BNX2_EMAC_MODE_PORT_MII_10M; 1340 break; 1341 } 1342 /* fall through */ 1343 case SPEED_100: 1344 val |= BNX2_EMAC_MODE_PORT_MII; 1345 break; 1346 case SPEED_2500: 1347 val |= BNX2_EMAC_MODE_25G_MODE; 1348 /* fall through */ 1349 case SPEED_1000: 1350 val |= BNX2_EMAC_MODE_PORT_GMII; 1351 break; 1352 } 1353 } 1354 else { 1355 val |= BNX2_EMAC_MODE_PORT_GMII; 1356 } 1357 1358 /* Set the MAC to operate in the appropriate duplex mode. */ 1359 if (bp->duplex == DUPLEX_HALF) 1360 val |= BNX2_EMAC_MODE_HALF_DUPLEX; 1361 BNX2_WR(bp, BNX2_EMAC_MODE, val); 1362 1363 /* Enable/disable rx PAUSE. */ 1364 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN; 1365 1366 if (bp->flow_ctrl & FLOW_CTRL_RX) 1367 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN; 1368 BNX2_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode); 1369 1370 /* Enable/disable tx PAUSE. */ 1371 val = BNX2_RD(bp, BNX2_EMAC_TX_MODE); 1372 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN; 1373 1374 if (bp->flow_ctrl & FLOW_CTRL_TX) 1375 val |= BNX2_EMAC_TX_MODE_FLOW_EN; 1376 BNX2_WR(bp, BNX2_EMAC_TX_MODE, val); 1377 1378 /* Acknowledge the interrupt. */ 1379 BNX2_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE); 1380 1381 bnx2_init_all_rx_contexts(bp); 1382 } 1383 1384 static void 1385 bnx2_enable_bmsr1(struct bnx2 *bp) 1386 { 1387 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && 1388 (BNX2_CHIP(bp) == BNX2_CHIP_5709)) 1389 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, 1390 MII_BNX2_BLK_ADDR_GP_STATUS); 1391 } 1392 1393 static void 1394 bnx2_disable_bmsr1(struct bnx2 *bp) 1395 { 1396 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && 1397 (BNX2_CHIP(bp) == BNX2_CHIP_5709)) 1398 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, 1399 MII_BNX2_BLK_ADDR_COMBO_IEEEB0); 1400 } 1401 1402 static int 1403 bnx2_test_and_enable_2g5(struct bnx2 *bp) 1404 { 1405 u32 up1; 1406 int ret = 1; 1407 1408 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) 1409 return 0; 1410 1411 if (bp->autoneg & AUTONEG_SPEED) 1412 bp->advertising |= ADVERTISED_2500baseX_Full; 1413 1414 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) 1415 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G); 1416 1417 bnx2_read_phy(bp, bp->mii_up1, &up1); 1418 if (!(up1 & BCM5708S_UP1_2G5)) { 1419 up1 |= BCM5708S_UP1_2G5; 1420 bnx2_write_phy(bp, bp->mii_up1, up1); 1421 ret = 0; 1422 } 1423 1424 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) 1425 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, 1426 MII_BNX2_BLK_ADDR_COMBO_IEEEB0); 1427 1428 return ret; 1429 } 1430 1431 static int 1432 bnx2_test_and_disable_2g5(struct bnx2 *bp) 1433 { 1434 u32 up1; 1435 int ret = 0; 1436 1437 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) 1438 return 0; 1439 1440 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) 1441 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G); 1442 1443 bnx2_read_phy(bp, bp->mii_up1, &up1); 1444 if (up1 & BCM5708S_UP1_2G5) { 1445 up1 &= ~BCM5708S_UP1_2G5; 1446 bnx2_write_phy(bp, bp->mii_up1, up1); 1447 ret = 1; 1448 } 1449 1450 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) 1451 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, 1452 MII_BNX2_BLK_ADDR_COMBO_IEEEB0); 1453 1454 return ret; 1455 } 1456 1457 static void 1458 bnx2_enable_forced_2g5(struct bnx2 *bp) 1459 { 1460 u32 uninitialized_var(bmcr); 1461 int err; 1462 1463 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) 1464 return; 1465 1466 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { 1467 u32 val; 1468 1469 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, 1470 MII_BNX2_BLK_ADDR_SERDES_DIG); 1471 if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) { 1472 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK; 1473 val |= MII_BNX2_SD_MISC1_FORCE | 1474 MII_BNX2_SD_MISC1_FORCE_2_5G; 1475 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val); 1476 } 1477 1478 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, 1479 MII_BNX2_BLK_ADDR_COMBO_IEEEB0); 1480 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); 1481 1482 } else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) { 1483 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); 1484 if (!err) 1485 bmcr |= BCM5708S_BMCR_FORCE_2500; 1486 } else { 1487 return; 1488 } 1489 1490 if (err) 1491 return; 1492 1493 if (bp->autoneg & AUTONEG_SPEED) { 1494 bmcr &= ~BMCR_ANENABLE; 1495 if (bp->req_duplex == DUPLEX_FULL) 1496 bmcr |= BMCR_FULLDPLX; 1497 } 1498 bnx2_write_phy(bp, bp->mii_bmcr, bmcr); 1499 } 1500 1501 static void 1502 bnx2_disable_forced_2g5(struct bnx2 *bp) 1503 { 1504 u32 uninitialized_var(bmcr); 1505 int err; 1506 1507 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) 1508 return; 1509 1510 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { 1511 u32 val; 1512 1513 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, 1514 MII_BNX2_BLK_ADDR_SERDES_DIG); 1515 if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) { 1516 val &= ~MII_BNX2_SD_MISC1_FORCE; 1517 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val); 1518 } 1519 1520 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, 1521 MII_BNX2_BLK_ADDR_COMBO_IEEEB0); 1522 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); 1523 1524 } else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) { 1525 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); 1526 if (!err) 1527 bmcr &= ~BCM5708S_BMCR_FORCE_2500; 1528 } else { 1529 return; 1530 } 1531 1532 if (err) 1533 return; 1534 1535 if (bp->autoneg & AUTONEG_SPEED) 1536 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART; 1537 bnx2_write_phy(bp, bp->mii_bmcr, bmcr); 1538 } 1539 1540 static void 1541 bnx2_5706s_force_link_dn(struct bnx2 *bp, int start) 1542 { 1543 u32 val; 1544 1545 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL); 1546 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val); 1547 if (start) 1548 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f); 1549 else 1550 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0); 1551 } 1552 1553 static int 1554 bnx2_set_link(struct bnx2 *bp) 1555 { 1556 u32 bmsr; 1557 u8 link_up; 1558 1559 if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) { 1560 bp->link_up = 1; 1561 return 0; 1562 } 1563 1564 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) 1565 return 0; 1566 1567 link_up = bp->link_up; 1568 1569 bnx2_enable_bmsr1(bp); 1570 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr); 1571 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr); 1572 bnx2_disable_bmsr1(bp); 1573 1574 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && 1575 (BNX2_CHIP(bp) == BNX2_CHIP_5706)) { 1576 u32 val, an_dbg; 1577 1578 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) { 1579 bnx2_5706s_force_link_dn(bp, 0); 1580 bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN; 1581 } 1582 val = BNX2_RD(bp, BNX2_EMAC_STATUS); 1583 1584 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG); 1585 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg); 1586 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg); 1587 1588 if ((val & BNX2_EMAC_STATUS_LINK) && 1589 !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC)) 1590 bmsr |= BMSR_LSTATUS; 1591 else 1592 bmsr &= ~BMSR_LSTATUS; 1593 } 1594 1595 if (bmsr & BMSR_LSTATUS) { 1596 bp->link_up = 1; 1597 1598 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { 1599 if (BNX2_CHIP(bp) == BNX2_CHIP_5706) 1600 bnx2_5706s_linkup(bp); 1601 else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) 1602 bnx2_5708s_linkup(bp); 1603 else if (BNX2_CHIP(bp) == BNX2_CHIP_5709) 1604 bnx2_5709s_linkup(bp); 1605 } 1606 else { 1607 bnx2_copper_linkup(bp); 1608 } 1609 bnx2_resolve_flow_ctrl(bp); 1610 } 1611 else { 1612 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && 1613 (bp->autoneg & AUTONEG_SPEED)) 1614 bnx2_disable_forced_2g5(bp); 1615 1616 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) { 1617 u32 bmcr; 1618 1619 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); 1620 bmcr |= BMCR_ANENABLE; 1621 bnx2_write_phy(bp, bp->mii_bmcr, bmcr); 1622 1623 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT; 1624 } 1625 bp->link_up = 0; 1626 } 1627 1628 if (bp->link_up != link_up) { 1629 bnx2_report_link(bp); 1630 } 1631 1632 bnx2_set_mac_link(bp); 1633 1634 return 0; 1635 } 1636 1637 static int 1638 bnx2_reset_phy(struct bnx2 *bp) 1639 { 1640 int i; 1641 u32 reg; 1642 1643 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET); 1644 1645 #define PHY_RESET_MAX_WAIT 100 1646 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) { 1647 udelay(10); 1648 1649 bnx2_read_phy(bp, bp->mii_bmcr, ®); 1650 if (!(reg & BMCR_RESET)) { 1651 udelay(20); 1652 break; 1653 } 1654 } 1655 if (i == PHY_RESET_MAX_WAIT) { 1656 return -EBUSY; 1657 } 1658 return 0; 1659 } 1660 1661 static u32 1662 bnx2_phy_get_pause_adv(struct bnx2 *bp) 1663 { 1664 u32 adv = 0; 1665 1666 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) == 1667 (FLOW_CTRL_RX | FLOW_CTRL_TX)) { 1668 1669 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { 1670 adv = ADVERTISE_1000XPAUSE; 1671 } 1672 else { 1673 adv = ADVERTISE_PAUSE_CAP; 1674 } 1675 } 1676 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) { 1677 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { 1678 adv = ADVERTISE_1000XPSE_ASYM; 1679 } 1680 else { 1681 adv = ADVERTISE_PAUSE_ASYM; 1682 } 1683 } 1684 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) { 1685 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { 1686 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM; 1687 } 1688 else { 1689 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; 1690 } 1691 } 1692 return adv; 1693 } 1694 1695 static int bnx2_fw_sync(struct bnx2 *, u32, int, int); 1696 1697 static int 1698 bnx2_setup_remote_phy(struct bnx2 *bp, u8 port) 1699 __releases(&bp->phy_lock) 1700 __acquires(&bp->phy_lock) 1701 { 1702 u32 speed_arg = 0, pause_adv; 1703 1704 pause_adv = bnx2_phy_get_pause_adv(bp); 1705 1706 if (bp->autoneg & AUTONEG_SPEED) { 1707 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG; 1708 if (bp->advertising & ADVERTISED_10baseT_Half) 1709 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF; 1710 if (bp->advertising & ADVERTISED_10baseT_Full) 1711 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL; 1712 if (bp->advertising & ADVERTISED_100baseT_Half) 1713 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF; 1714 if (bp->advertising & ADVERTISED_100baseT_Full) 1715 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL; 1716 if (bp->advertising & ADVERTISED_1000baseT_Full) 1717 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL; 1718 if (bp->advertising & ADVERTISED_2500baseX_Full) 1719 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL; 1720 } else { 1721 if (bp->req_line_speed == SPEED_2500) 1722 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL; 1723 else if (bp->req_line_speed == SPEED_1000) 1724 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL; 1725 else if (bp->req_line_speed == SPEED_100) { 1726 if (bp->req_duplex == DUPLEX_FULL) 1727 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL; 1728 else 1729 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF; 1730 } else if (bp->req_line_speed == SPEED_10) { 1731 if (bp->req_duplex == DUPLEX_FULL) 1732 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL; 1733 else 1734 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF; 1735 } 1736 } 1737 1738 if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP)) 1739 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE; 1740 if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM)) 1741 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE; 1742 1743 if (port == PORT_TP) 1744 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE | 1745 BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED; 1746 1747 bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg); 1748 1749 spin_unlock_bh(&bp->phy_lock); 1750 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0); 1751 spin_lock_bh(&bp->phy_lock); 1752 1753 return 0; 1754 } 1755 1756 static int 1757 bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port) 1758 __releases(&bp->phy_lock) 1759 __acquires(&bp->phy_lock) 1760 { 1761 u32 adv, bmcr; 1762 u32 new_adv = 0; 1763 1764 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) 1765 return bnx2_setup_remote_phy(bp, port); 1766 1767 if (!(bp->autoneg & AUTONEG_SPEED)) { 1768 u32 new_bmcr; 1769 int force_link_down = 0; 1770 1771 if (bp->req_line_speed == SPEED_2500) { 1772 if (!bnx2_test_and_enable_2g5(bp)) 1773 force_link_down = 1; 1774 } else if (bp->req_line_speed == SPEED_1000) { 1775 if (bnx2_test_and_disable_2g5(bp)) 1776 force_link_down = 1; 1777 } 1778 bnx2_read_phy(bp, bp->mii_adv, &adv); 1779 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF); 1780 1781 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); 1782 new_bmcr = bmcr & ~BMCR_ANENABLE; 1783 new_bmcr |= BMCR_SPEED1000; 1784 1785 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { 1786 if (bp->req_line_speed == SPEED_2500) 1787 bnx2_enable_forced_2g5(bp); 1788 else if (bp->req_line_speed == SPEED_1000) { 1789 bnx2_disable_forced_2g5(bp); 1790 new_bmcr &= ~0x2000; 1791 } 1792 1793 } else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) { 1794 if (bp->req_line_speed == SPEED_2500) 1795 new_bmcr |= BCM5708S_BMCR_FORCE_2500; 1796 else 1797 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500; 1798 } 1799 1800 if (bp->req_duplex == DUPLEX_FULL) { 1801 adv |= ADVERTISE_1000XFULL; 1802 new_bmcr |= BMCR_FULLDPLX; 1803 } 1804 else { 1805 adv |= ADVERTISE_1000XHALF; 1806 new_bmcr &= ~BMCR_FULLDPLX; 1807 } 1808 if ((new_bmcr != bmcr) || (force_link_down)) { 1809 /* Force a link down visible on the other side */ 1810 if (bp->link_up) { 1811 bnx2_write_phy(bp, bp->mii_adv, adv & 1812 ~(ADVERTISE_1000XFULL | 1813 ADVERTISE_1000XHALF)); 1814 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | 1815 BMCR_ANRESTART | BMCR_ANENABLE); 1816 1817 bp->link_up = 0; 1818 netif_carrier_off(bp->dev); 1819 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr); 1820 bnx2_report_link(bp); 1821 } 1822 bnx2_write_phy(bp, bp->mii_adv, adv); 1823 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr); 1824 } else { 1825 bnx2_resolve_flow_ctrl(bp); 1826 bnx2_set_mac_link(bp); 1827 } 1828 return 0; 1829 } 1830 1831 bnx2_test_and_enable_2g5(bp); 1832 1833 if (bp->advertising & ADVERTISED_1000baseT_Full) 1834 new_adv |= ADVERTISE_1000XFULL; 1835 1836 new_adv |= bnx2_phy_get_pause_adv(bp); 1837 1838 bnx2_read_phy(bp, bp->mii_adv, &adv); 1839 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); 1840 1841 bp->serdes_an_pending = 0; 1842 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) { 1843 /* Force a link down visible on the other side */ 1844 if (bp->link_up) { 1845 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK); 1846 spin_unlock_bh(&bp->phy_lock); 1847 msleep(20); 1848 spin_lock_bh(&bp->phy_lock); 1849 } 1850 1851 bnx2_write_phy(bp, bp->mii_adv, new_adv); 1852 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | 1853 BMCR_ANENABLE); 1854 /* Speed up link-up time when the link partner 1855 * does not autonegotiate which is very common 1856 * in blade servers. Some blade servers use 1857 * IPMI for kerboard input and it's important 1858 * to minimize link disruptions. Autoneg. involves 1859 * exchanging base pages plus 3 next pages and 1860 * normally completes in about 120 msec. 1861 */ 1862 bp->current_interval = BNX2_SERDES_AN_TIMEOUT; 1863 bp->serdes_an_pending = 1; 1864 mod_timer(&bp->timer, jiffies + bp->current_interval); 1865 } else { 1866 bnx2_resolve_flow_ctrl(bp); 1867 bnx2_set_mac_link(bp); 1868 } 1869 1870 return 0; 1871 } 1872 1873 #define ETHTOOL_ALL_FIBRE_SPEED \ 1874 (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ? \ 1875 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\ 1876 (ADVERTISED_1000baseT_Full) 1877 1878 #define ETHTOOL_ALL_COPPER_SPEED \ 1879 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \ 1880 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \ 1881 ADVERTISED_1000baseT_Full) 1882 1883 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \ 1884 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA) 1885 1886 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL) 1887 1888 static void 1889 bnx2_set_default_remote_link(struct bnx2 *bp) 1890 { 1891 u32 link; 1892 1893 if (bp->phy_port == PORT_TP) 1894 link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK); 1895 else 1896 link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK); 1897 1898 if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) { 1899 bp->req_line_speed = 0; 1900 bp->autoneg |= AUTONEG_SPEED; 1901 bp->advertising = ADVERTISED_Autoneg; 1902 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF) 1903 bp->advertising |= ADVERTISED_10baseT_Half; 1904 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL) 1905 bp->advertising |= ADVERTISED_10baseT_Full; 1906 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF) 1907 bp->advertising |= ADVERTISED_100baseT_Half; 1908 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL) 1909 bp->advertising |= ADVERTISED_100baseT_Full; 1910 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL) 1911 bp->advertising |= ADVERTISED_1000baseT_Full; 1912 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL) 1913 bp->advertising |= ADVERTISED_2500baseX_Full; 1914 } else { 1915 bp->autoneg = 0; 1916 bp->advertising = 0; 1917 bp->req_duplex = DUPLEX_FULL; 1918 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) { 1919 bp->req_line_speed = SPEED_10; 1920 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF) 1921 bp->req_duplex = DUPLEX_HALF; 1922 } 1923 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) { 1924 bp->req_line_speed = SPEED_100; 1925 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF) 1926 bp->req_duplex = DUPLEX_HALF; 1927 } 1928 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL) 1929 bp->req_line_speed = SPEED_1000; 1930 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL) 1931 bp->req_line_speed = SPEED_2500; 1932 } 1933 } 1934 1935 static void 1936 bnx2_set_default_link(struct bnx2 *bp) 1937 { 1938 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) { 1939 bnx2_set_default_remote_link(bp); 1940 return; 1941 } 1942 1943 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL; 1944 bp->req_line_speed = 0; 1945 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { 1946 u32 reg; 1947 1948 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg; 1949 1950 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG); 1951 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK; 1952 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) { 1953 bp->autoneg = 0; 1954 bp->req_line_speed = bp->line_speed = SPEED_1000; 1955 bp->req_duplex = DUPLEX_FULL; 1956 } 1957 } else 1958 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg; 1959 } 1960 1961 static void 1962 bnx2_send_heart_beat(struct bnx2 *bp) 1963 { 1964 u32 msg; 1965 u32 addr; 1966 1967 spin_lock(&bp->indirect_lock); 1968 msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK); 1969 addr = bp->shmem_base + BNX2_DRV_PULSE_MB; 1970 BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr); 1971 BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW, msg); 1972 spin_unlock(&bp->indirect_lock); 1973 } 1974 1975 static void 1976 bnx2_remote_phy_event(struct bnx2 *bp) 1977 { 1978 u32 msg; 1979 u8 link_up = bp->link_up; 1980 u8 old_port; 1981 1982 msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS); 1983 1984 if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED) 1985 bnx2_send_heart_beat(bp); 1986 1987 msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED; 1988 1989 if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN) 1990 bp->link_up = 0; 1991 else { 1992 u32 speed; 1993 1994 bp->link_up = 1; 1995 speed = msg & BNX2_LINK_STATUS_SPEED_MASK; 1996 bp->duplex = DUPLEX_FULL; 1997 switch (speed) { 1998 case BNX2_LINK_STATUS_10HALF: 1999 bp->duplex = DUPLEX_HALF; 2000 /* fall through */ 2001 case BNX2_LINK_STATUS_10FULL: 2002 bp->line_speed = SPEED_10; 2003 break; 2004 case BNX2_LINK_STATUS_100HALF: 2005 bp->duplex = DUPLEX_HALF; 2006 /* fall through */ 2007 case BNX2_LINK_STATUS_100BASE_T4: 2008 case BNX2_LINK_STATUS_100FULL: 2009 bp->line_speed = SPEED_100; 2010 break; 2011 case BNX2_LINK_STATUS_1000HALF: 2012 bp->duplex = DUPLEX_HALF; 2013 /* fall through */ 2014 case BNX2_LINK_STATUS_1000FULL: 2015 bp->line_speed = SPEED_1000; 2016 break; 2017 case BNX2_LINK_STATUS_2500HALF: 2018 bp->duplex = DUPLEX_HALF; 2019 /* fall through */ 2020 case BNX2_LINK_STATUS_2500FULL: 2021 bp->line_speed = SPEED_2500; 2022 break; 2023 default: 2024 bp->line_speed = 0; 2025 break; 2026 } 2027 2028 bp->flow_ctrl = 0; 2029 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) != 2030 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) { 2031 if (bp->duplex == DUPLEX_FULL) 2032 bp->flow_ctrl = bp->req_flow_ctrl; 2033 } else { 2034 if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED) 2035 bp->flow_ctrl |= FLOW_CTRL_TX; 2036 if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED) 2037 bp->flow_ctrl |= FLOW_CTRL_RX; 2038 } 2039 2040 old_port = bp->phy_port; 2041 if (msg & BNX2_LINK_STATUS_SERDES_LINK) 2042 bp->phy_port = PORT_FIBRE; 2043 else 2044 bp->phy_port = PORT_TP; 2045 2046 if (old_port != bp->phy_port) 2047 bnx2_set_default_link(bp); 2048 2049 } 2050 if (bp->link_up != link_up) 2051 bnx2_report_link(bp); 2052 2053 bnx2_set_mac_link(bp); 2054 } 2055 2056 static int 2057 bnx2_set_remote_link(struct bnx2 *bp) 2058 { 2059 u32 evt_code; 2060 2061 evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB); 2062 switch (evt_code) { 2063 case BNX2_FW_EVT_CODE_LINK_EVENT: 2064 bnx2_remote_phy_event(bp); 2065 break; 2066 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT: 2067 default: 2068 bnx2_send_heart_beat(bp); 2069 break; 2070 } 2071 return 0; 2072 } 2073 2074 static int 2075 bnx2_setup_copper_phy(struct bnx2 *bp) 2076 __releases(&bp->phy_lock) 2077 __acquires(&bp->phy_lock) 2078 { 2079 u32 bmcr, adv_reg, new_adv = 0; 2080 u32 new_bmcr; 2081 2082 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); 2083 2084 bnx2_read_phy(bp, bp->mii_adv, &adv_reg); 2085 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP | 2086 ADVERTISE_PAUSE_ASYM); 2087 2088 new_adv = ADVERTISE_CSMA | ethtool_adv_to_mii_adv_t(bp->advertising); 2089 2090 if (bp->autoneg & AUTONEG_SPEED) { 2091 u32 adv1000_reg; 2092 u32 new_adv1000 = 0; 2093 2094 new_adv |= bnx2_phy_get_pause_adv(bp); 2095 2096 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg); 2097 adv1000_reg &= PHY_ALL_1000_SPEED; 2098 2099 new_adv1000 |= ethtool_adv_to_mii_ctrl1000_t(bp->advertising); 2100 if ((adv1000_reg != new_adv1000) || 2101 (adv_reg != new_adv) || 2102 ((bmcr & BMCR_ANENABLE) == 0)) { 2103 2104 bnx2_write_phy(bp, bp->mii_adv, new_adv); 2105 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000); 2106 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART | 2107 BMCR_ANENABLE); 2108 } 2109 else if (bp->link_up) { 2110 /* Flow ctrl may have changed from auto to forced */ 2111 /* or vice-versa. */ 2112 2113 bnx2_resolve_flow_ctrl(bp); 2114 bnx2_set_mac_link(bp); 2115 } 2116 return 0; 2117 } 2118 2119 /* advertise nothing when forcing speed */ 2120 if (adv_reg != new_adv) 2121 bnx2_write_phy(bp, bp->mii_adv, new_adv); 2122 2123 new_bmcr = 0; 2124 if (bp->req_line_speed == SPEED_100) { 2125 new_bmcr |= BMCR_SPEED100; 2126 } 2127 if (bp->req_duplex == DUPLEX_FULL) { 2128 new_bmcr |= BMCR_FULLDPLX; 2129 } 2130 if (new_bmcr != bmcr) { 2131 u32 bmsr; 2132 2133 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); 2134 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); 2135 2136 if (bmsr & BMSR_LSTATUS) { 2137 /* Force link down */ 2138 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK); 2139 spin_unlock_bh(&bp->phy_lock); 2140 msleep(50); 2141 spin_lock_bh(&bp->phy_lock); 2142 2143 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); 2144 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); 2145 } 2146 2147 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr); 2148 2149 /* Normally, the new speed is setup after the link has 2150 * gone down and up again. In some cases, link will not go 2151 * down so we need to set up the new speed here. 2152 */ 2153 if (bmsr & BMSR_LSTATUS) { 2154 bp->line_speed = bp->req_line_speed; 2155 bp->duplex = bp->req_duplex; 2156 bnx2_resolve_flow_ctrl(bp); 2157 bnx2_set_mac_link(bp); 2158 } 2159 } else { 2160 bnx2_resolve_flow_ctrl(bp); 2161 bnx2_set_mac_link(bp); 2162 } 2163 return 0; 2164 } 2165 2166 static int 2167 bnx2_setup_phy(struct bnx2 *bp, u8 port) 2168 __releases(&bp->phy_lock) 2169 __acquires(&bp->phy_lock) 2170 { 2171 if (bp->loopback == MAC_LOOPBACK) 2172 return 0; 2173 2174 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { 2175 return bnx2_setup_serdes_phy(bp, port); 2176 } 2177 else { 2178 return bnx2_setup_copper_phy(bp); 2179 } 2180 } 2181 2182 static int 2183 bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy) 2184 { 2185 u32 val; 2186 2187 bp->mii_bmcr = MII_BMCR + 0x10; 2188 bp->mii_bmsr = MII_BMSR + 0x10; 2189 bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1; 2190 bp->mii_adv = MII_ADVERTISE + 0x10; 2191 bp->mii_lpa = MII_LPA + 0x10; 2192 bp->mii_up1 = MII_BNX2_OVER1G_UP1; 2193 2194 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER); 2195 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD); 2196 2197 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0); 2198 if (reset_phy) 2199 bnx2_reset_phy(bp); 2200 2201 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG); 2202 2203 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val); 2204 val &= ~MII_BNX2_SD_1000XCTL1_AUTODET; 2205 val |= MII_BNX2_SD_1000XCTL1_FIBER; 2206 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val); 2207 2208 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G); 2209 bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val); 2210 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) 2211 val |= BCM5708S_UP1_2G5; 2212 else 2213 val &= ~BCM5708S_UP1_2G5; 2214 bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val); 2215 2216 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG); 2217 bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val); 2218 val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM; 2219 bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val); 2220 2221 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0); 2222 2223 val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN | 2224 MII_BNX2_CL73_BAM_NP_AFT_BP_EN; 2225 bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val); 2226 2227 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0); 2228 2229 return 0; 2230 } 2231 2232 static int 2233 bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy) 2234 { 2235 u32 val; 2236 2237 if (reset_phy) 2238 bnx2_reset_phy(bp); 2239 2240 bp->mii_up1 = BCM5708S_UP1; 2241 2242 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3); 2243 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE); 2244 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG); 2245 2246 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val); 2247 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN; 2248 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val); 2249 2250 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val); 2251 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN; 2252 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val); 2253 2254 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) { 2255 bnx2_read_phy(bp, BCM5708S_UP1, &val); 2256 val |= BCM5708S_UP1_2G5; 2257 bnx2_write_phy(bp, BCM5708S_UP1, val); 2258 } 2259 2260 if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0) || 2261 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B0) || 2262 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B1)) { 2263 /* increase tx signal amplitude */ 2264 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, 2265 BCM5708S_BLK_ADDR_TX_MISC); 2266 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val); 2267 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM; 2268 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val); 2269 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG); 2270 } 2271 2272 val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) & 2273 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK; 2274 2275 if (val) { 2276 u32 is_backplane; 2277 2278 is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG); 2279 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) { 2280 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, 2281 BCM5708S_BLK_ADDR_TX_MISC); 2282 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val); 2283 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, 2284 BCM5708S_BLK_ADDR_DIG); 2285 } 2286 } 2287 return 0; 2288 } 2289 2290 static int 2291 bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy) 2292 { 2293 if (reset_phy) 2294 bnx2_reset_phy(bp); 2295 2296 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT; 2297 2298 if (BNX2_CHIP(bp) == BNX2_CHIP_5706) 2299 BNX2_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300); 2300 2301 if (bp->dev->mtu > 1500) { 2302 u32 val; 2303 2304 /* Set extended packet length bit */ 2305 bnx2_write_phy(bp, 0x18, 0x7); 2306 bnx2_read_phy(bp, 0x18, &val); 2307 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000); 2308 2309 bnx2_write_phy(bp, 0x1c, 0x6c00); 2310 bnx2_read_phy(bp, 0x1c, &val); 2311 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02); 2312 } 2313 else { 2314 u32 val; 2315 2316 bnx2_write_phy(bp, 0x18, 0x7); 2317 bnx2_read_phy(bp, 0x18, &val); 2318 bnx2_write_phy(bp, 0x18, val & ~0x4007); 2319 2320 bnx2_write_phy(bp, 0x1c, 0x6c00); 2321 bnx2_read_phy(bp, 0x1c, &val); 2322 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00); 2323 } 2324 2325 return 0; 2326 } 2327 2328 static int 2329 bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy) 2330 { 2331 u32 val; 2332 2333 if (reset_phy) 2334 bnx2_reset_phy(bp); 2335 2336 if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) { 2337 bnx2_write_phy(bp, 0x18, 0x0c00); 2338 bnx2_write_phy(bp, 0x17, 0x000a); 2339 bnx2_write_phy(bp, 0x15, 0x310b); 2340 bnx2_write_phy(bp, 0x17, 0x201f); 2341 bnx2_write_phy(bp, 0x15, 0x9506); 2342 bnx2_write_phy(bp, 0x17, 0x401f); 2343 bnx2_write_phy(bp, 0x15, 0x14e2); 2344 bnx2_write_phy(bp, 0x18, 0x0400); 2345 } 2346 2347 if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) { 2348 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, 2349 MII_BNX2_DSP_EXPAND_REG | 0x8); 2350 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val); 2351 val &= ~(1 << 8); 2352 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val); 2353 } 2354 2355 if (bp->dev->mtu > 1500) { 2356 /* Set extended packet length bit */ 2357 bnx2_write_phy(bp, 0x18, 0x7); 2358 bnx2_read_phy(bp, 0x18, &val); 2359 bnx2_write_phy(bp, 0x18, val | 0x4000); 2360 2361 bnx2_read_phy(bp, 0x10, &val); 2362 bnx2_write_phy(bp, 0x10, val | 0x1); 2363 } 2364 else { 2365 bnx2_write_phy(bp, 0x18, 0x7); 2366 bnx2_read_phy(bp, 0x18, &val); 2367 bnx2_write_phy(bp, 0x18, val & ~0x4007); 2368 2369 bnx2_read_phy(bp, 0x10, &val); 2370 bnx2_write_phy(bp, 0x10, val & ~0x1); 2371 } 2372 2373 /* ethernet@wirespeed */ 2374 bnx2_write_phy(bp, MII_BNX2_AUX_CTL, AUX_CTL_MISC_CTL); 2375 bnx2_read_phy(bp, MII_BNX2_AUX_CTL, &val); 2376 val |= AUX_CTL_MISC_CTL_WR | AUX_CTL_MISC_CTL_WIRESPEED; 2377 2378 /* auto-mdix */ 2379 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) 2380 val |= AUX_CTL_MISC_CTL_AUTOMDIX; 2381 2382 bnx2_write_phy(bp, MII_BNX2_AUX_CTL, val); 2383 return 0; 2384 } 2385 2386 2387 static int 2388 bnx2_init_phy(struct bnx2 *bp, int reset_phy) 2389 __releases(&bp->phy_lock) 2390 __acquires(&bp->phy_lock) 2391 { 2392 u32 val; 2393 int rc = 0; 2394 2395 bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK; 2396 bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY; 2397 2398 bp->mii_bmcr = MII_BMCR; 2399 bp->mii_bmsr = MII_BMSR; 2400 bp->mii_bmsr1 = MII_BMSR; 2401 bp->mii_adv = MII_ADVERTISE; 2402 bp->mii_lpa = MII_LPA; 2403 2404 BNX2_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK); 2405 2406 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) 2407 goto setup_phy; 2408 2409 bnx2_read_phy(bp, MII_PHYSID1, &val); 2410 bp->phy_id = val << 16; 2411 bnx2_read_phy(bp, MII_PHYSID2, &val); 2412 bp->phy_id |= val & 0xffff; 2413 2414 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { 2415 if (BNX2_CHIP(bp) == BNX2_CHIP_5706) 2416 rc = bnx2_init_5706s_phy(bp, reset_phy); 2417 else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) 2418 rc = bnx2_init_5708s_phy(bp, reset_phy); 2419 else if (BNX2_CHIP(bp) == BNX2_CHIP_5709) 2420 rc = bnx2_init_5709s_phy(bp, reset_phy); 2421 } 2422 else { 2423 rc = bnx2_init_copper_phy(bp, reset_phy); 2424 } 2425 2426 setup_phy: 2427 if (!rc) 2428 rc = bnx2_setup_phy(bp, bp->phy_port); 2429 2430 return rc; 2431 } 2432 2433 static int 2434 bnx2_set_mac_loopback(struct bnx2 *bp) 2435 { 2436 u32 mac_mode; 2437 2438 mac_mode = BNX2_RD(bp, BNX2_EMAC_MODE); 2439 mac_mode &= ~BNX2_EMAC_MODE_PORT; 2440 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK; 2441 BNX2_WR(bp, BNX2_EMAC_MODE, mac_mode); 2442 bp->link_up = 1; 2443 return 0; 2444 } 2445 2446 static int bnx2_test_link(struct bnx2 *); 2447 2448 static int 2449 bnx2_set_phy_loopback(struct bnx2 *bp) 2450 { 2451 u32 mac_mode; 2452 int rc, i; 2453 2454 spin_lock_bh(&bp->phy_lock); 2455 rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX | 2456 BMCR_SPEED1000); 2457 spin_unlock_bh(&bp->phy_lock); 2458 if (rc) 2459 return rc; 2460 2461 for (i = 0; i < 10; i++) { 2462 if (bnx2_test_link(bp) == 0) 2463 break; 2464 msleep(100); 2465 } 2466 2467 mac_mode = BNX2_RD(bp, BNX2_EMAC_MODE); 2468 mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX | 2469 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK | 2470 BNX2_EMAC_MODE_25G_MODE); 2471 2472 mac_mode |= BNX2_EMAC_MODE_PORT_GMII; 2473 BNX2_WR(bp, BNX2_EMAC_MODE, mac_mode); 2474 bp->link_up = 1; 2475 return 0; 2476 } 2477 2478 static void 2479 bnx2_dump_mcp_state(struct bnx2 *bp) 2480 { 2481 struct net_device *dev = bp->dev; 2482 u32 mcp_p0, mcp_p1; 2483 2484 netdev_err(dev, "<--- start MCP states dump --->\n"); 2485 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { 2486 mcp_p0 = BNX2_MCP_STATE_P0; 2487 mcp_p1 = BNX2_MCP_STATE_P1; 2488 } else { 2489 mcp_p0 = BNX2_MCP_STATE_P0_5708; 2490 mcp_p1 = BNX2_MCP_STATE_P1_5708; 2491 } 2492 netdev_err(dev, "DEBUG: MCP_STATE_P0[%08x] MCP_STATE_P1[%08x]\n", 2493 bnx2_reg_rd_ind(bp, mcp_p0), bnx2_reg_rd_ind(bp, mcp_p1)); 2494 netdev_err(dev, "DEBUG: MCP mode[%08x] state[%08x] evt_mask[%08x]\n", 2495 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_MODE), 2496 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_STATE), 2497 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_EVENT_MASK)); 2498 netdev_err(dev, "DEBUG: pc[%08x] pc[%08x] instr[%08x]\n", 2499 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_PROGRAM_COUNTER), 2500 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_PROGRAM_COUNTER), 2501 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_INSTRUCTION)); 2502 netdev_err(dev, "DEBUG: shmem states:\n"); 2503 netdev_err(dev, "DEBUG: drv_mb[%08x] fw_mb[%08x] link_status[%08x]", 2504 bnx2_shmem_rd(bp, BNX2_DRV_MB), 2505 bnx2_shmem_rd(bp, BNX2_FW_MB), 2506 bnx2_shmem_rd(bp, BNX2_LINK_STATUS)); 2507 pr_cont(" drv_pulse_mb[%08x]\n", bnx2_shmem_rd(bp, BNX2_DRV_PULSE_MB)); 2508 netdev_err(dev, "DEBUG: dev_info_signature[%08x] reset_type[%08x]", 2509 bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE), 2510 bnx2_shmem_rd(bp, BNX2_BC_STATE_RESET_TYPE)); 2511 pr_cont(" condition[%08x]\n", 2512 bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION)); 2513 DP_SHMEM_LINE(bp, BNX2_BC_RESET_TYPE); 2514 DP_SHMEM_LINE(bp, 0x3cc); 2515 DP_SHMEM_LINE(bp, 0x3dc); 2516 DP_SHMEM_LINE(bp, 0x3ec); 2517 netdev_err(dev, "DEBUG: 0x3fc[%08x]\n", bnx2_shmem_rd(bp, 0x3fc)); 2518 netdev_err(dev, "<--- end MCP states dump --->\n"); 2519 } 2520 2521 static int 2522 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent) 2523 { 2524 int i; 2525 u32 val; 2526 2527 bp->fw_wr_seq++; 2528 msg_data |= bp->fw_wr_seq; 2529 bp->fw_last_msg = msg_data; 2530 2531 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data); 2532 2533 if (!ack) 2534 return 0; 2535 2536 /* wait for an acknowledgement. */ 2537 for (i = 0; i < (BNX2_FW_ACK_TIME_OUT_MS / 10); i++) { 2538 msleep(10); 2539 2540 val = bnx2_shmem_rd(bp, BNX2_FW_MB); 2541 2542 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ)) 2543 break; 2544 } 2545 if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0) 2546 return 0; 2547 2548 /* If we timed out, inform the firmware that this is the case. */ 2549 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) { 2550 msg_data &= ~BNX2_DRV_MSG_CODE; 2551 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT; 2552 2553 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data); 2554 if (!silent) { 2555 pr_err("fw sync timeout, reset code = %x\n", msg_data); 2556 bnx2_dump_mcp_state(bp); 2557 } 2558 2559 return -EBUSY; 2560 } 2561 2562 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK) 2563 return -EIO; 2564 2565 return 0; 2566 } 2567 2568 static int 2569 bnx2_init_5709_context(struct bnx2 *bp) 2570 { 2571 int i, ret = 0; 2572 u32 val; 2573 2574 val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12); 2575 val |= (BNX2_PAGE_BITS - 8) << 16; 2576 BNX2_WR(bp, BNX2_CTX_COMMAND, val); 2577 for (i = 0; i < 10; i++) { 2578 val = BNX2_RD(bp, BNX2_CTX_COMMAND); 2579 if (!(val & BNX2_CTX_COMMAND_MEM_INIT)) 2580 break; 2581 udelay(2); 2582 } 2583 if (val & BNX2_CTX_COMMAND_MEM_INIT) 2584 return -EBUSY; 2585 2586 for (i = 0; i < bp->ctx_pages; i++) { 2587 int j; 2588 2589 if (bp->ctx_blk[i]) 2590 memset(bp->ctx_blk[i], 0, BNX2_PAGE_SIZE); 2591 else 2592 return -ENOMEM; 2593 2594 BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0, 2595 (bp->ctx_blk_mapping[i] & 0xffffffff) | 2596 BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID); 2597 BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1, 2598 (u64) bp->ctx_blk_mapping[i] >> 32); 2599 BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i | 2600 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ); 2601 for (j = 0; j < 10; j++) { 2602 2603 val = BNX2_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL); 2604 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ)) 2605 break; 2606 udelay(5); 2607 } 2608 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) { 2609 ret = -EBUSY; 2610 break; 2611 } 2612 } 2613 return ret; 2614 } 2615 2616 static void 2617 bnx2_init_context(struct bnx2 *bp) 2618 { 2619 u32 vcid; 2620 2621 vcid = 96; 2622 while (vcid) { 2623 u32 vcid_addr, pcid_addr, offset; 2624 int i; 2625 2626 vcid--; 2627 2628 if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) { 2629 u32 new_vcid; 2630 2631 vcid_addr = GET_PCID_ADDR(vcid); 2632 if (vcid & 0x8) { 2633 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7); 2634 } 2635 else { 2636 new_vcid = vcid; 2637 } 2638 pcid_addr = GET_PCID_ADDR(new_vcid); 2639 } 2640 else { 2641 vcid_addr = GET_CID_ADDR(vcid); 2642 pcid_addr = vcid_addr; 2643 } 2644 2645 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) { 2646 vcid_addr += (i << PHY_CTX_SHIFT); 2647 pcid_addr += (i << PHY_CTX_SHIFT); 2648 2649 BNX2_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr); 2650 BNX2_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr); 2651 2652 /* Zero out the context. */ 2653 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) 2654 bnx2_ctx_wr(bp, vcid_addr, offset, 0); 2655 } 2656 } 2657 } 2658 2659 static int 2660 bnx2_alloc_bad_rbuf(struct bnx2 *bp) 2661 { 2662 u16 *good_mbuf; 2663 u32 good_mbuf_cnt; 2664 u32 val; 2665 2666 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL); 2667 if (good_mbuf == NULL) 2668 return -ENOMEM; 2669 2670 BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS, 2671 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE); 2672 2673 good_mbuf_cnt = 0; 2674 2675 /* Allocate a bunch of mbufs and save the good ones in an array. */ 2676 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1); 2677 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) { 2678 bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND, 2679 BNX2_RBUF_COMMAND_ALLOC_REQ); 2680 2681 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC); 2682 2683 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE; 2684 2685 /* The addresses with Bit 9 set are bad memory blocks. */ 2686 if (!(val & (1 << 9))) { 2687 good_mbuf[good_mbuf_cnt] = (u16) val; 2688 good_mbuf_cnt++; 2689 } 2690 2691 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1); 2692 } 2693 2694 /* Free the good ones back to the mbuf pool thus discarding 2695 * all the bad ones. */ 2696 while (good_mbuf_cnt) { 2697 good_mbuf_cnt--; 2698 2699 val = good_mbuf[good_mbuf_cnt]; 2700 val = (val << 9) | val | 1; 2701 2702 bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val); 2703 } 2704 kfree(good_mbuf); 2705 return 0; 2706 } 2707 2708 static void 2709 bnx2_set_mac_addr(struct bnx2 *bp, u8 *mac_addr, u32 pos) 2710 { 2711 u32 val; 2712 2713 val = (mac_addr[0] << 8) | mac_addr[1]; 2714 2715 BNX2_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val); 2716 2717 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 2718 (mac_addr[4] << 8) | mac_addr[5]; 2719 2720 BNX2_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val); 2721 } 2722 2723 static inline int 2724 bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index, gfp_t gfp) 2725 { 2726 dma_addr_t mapping; 2727 struct bnx2_sw_pg *rx_pg = &rxr->rx_pg_ring[index]; 2728 struct bnx2_rx_bd *rxbd = 2729 &rxr->rx_pg_desc_ring[BNX2_RX_RING(index)][BNX2_RX_IDX(index)]; 2730 struct page *page = alloc_page(gfp); 2731 2732 if (!page) 2733 return -ENOMEM; 2734 mapping = dma_map_page(&bp->pdev->dev, page, 0, PAGE_SIZE, 2735 PCI_DMA_FROMDEVICE); 2736 if (dma_mapping_error(&bp->pdev->dev, mapping)) { 2737 __free_page(page); 2738 return -EIO; 2739 } 2740 2741 rx_pg->page = page; 2742 dma_unmap_addr_set(rx_pg, mapping, mapping); 2743 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32; 2744 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff; 2745 return 0; 2746 } 2747 2748 static void 2749 bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index) 2750 { 2751 struct bnx2_sw_pg *rx_pg = &rxr->rx_pg_ring[index]; 2752 struct page *page = rx_pg->page; 2753 2754 if (!page) 2755 return; 2756 2757 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(rx_pg, mapping), 2758 PAGE_SIZE, PCI_DMA_FROMDEVICE); 2759 2760 __free_page(page); 2761 rx_pg->page = NULL; 2762 } 2763 2764 static inline int 2765 bnx2_alloc_rx_data(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index, gfp_t gfp) 2766 { 2767 u8 *data; 2768 struct bnx2_sw_bd *rx_buf = &rxr->rx_buf_ring[index]; 2769 dma_addr_t mapping; 2770 struct bnx2_rx_bd *rxbd = 2771 &rxr->rx_desc_ring[BNX2_RX_RING(index)][BNX2_RX_IDX(index)]; 2772 2773 data = kmalloc(bp->rx_buf_size, gfp); 2774 if (!data) 2775 return -ENOMEM; 2776 2777 mapping = dma_map_single(&bp->pdev->dev, 2778 get_l2_fhdr(data), 2779 bp->rx_buf_use_size, 2780 PCI_DMA_FROMDEVICE); 2781 if (dma_mapping_error(&bp->pdev->dev, mapping)) { 2782 kfree(data); 2783 return -EIO; 2784 } 2785 2786 rx_buf->data = data; 2787 dma_unmap_addr_set(rx_buf, mapping, mapping); 2788 2789 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32; 2790 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff; 2791 2792 rxr->rx_prod_bseq += bp->rx_buf_use_size; 2793 2794 return 0; 2795 } 2796 2797 static int 2798 bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event) 2799 { 2800 struct status_block *sblk = bnapi->status_blk.msi; 2801 u32 new_link_state, old_link_state; 2802 int is_set = 1; 2803 2804 new_link_state = sblk->status_attn_bits & event; 2805 old_link_state = sblk->status_attn_bits_ack & event; 2806 if (new_link_state != old_link_state) { 2807 if (new_link_state) 2808 BNX2_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event); 2809 else 2810 BNX2_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event); 2811 } else 2812 is_set = 0; 2813 2814 return is_set; 2815 } 2816 2817 static void 2818 bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi) 2819 { 2820 spin_lock(&bp->phy_lock); 2821 2822 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE)) 2823 bnx2_set_link(bp); 2824 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT)) 2825 bnx2_set_remote_link(bp); 2826 2827 spin_unlock(&bp->phy_lock); 2828 2829 } 2830 2831 static inline u16 2832 bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi) 2833 { 2834 u16 cons; 2835 2836 /* Tell compiler that status block fields can change. */ 2837 barrier(); 2838 cons = *bnapi->hw_tx_cons_ptr; 2839 barrier(); 2840 if (unlikely((cons & BNX2_MAX_TX_DESC_CNT) == BNX2_MAX_TX_DESC_CNT)) 2841 cons++; 2842 return cons; 2843 } 2844 2845 static int 2846 bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget) 2847 { 2848 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; 2849 u16 hw_cons, sw_cons, sw_ring_cons; 2850 int tx_pkt = 0, index; 2851 unsigned int tx_bytes = 0; 2852 struct netdev_queue *txq; 2853 2854 index = (bnapi - bp->bnx2_napi); 2855 txq = netdev_get_tx_queue(bp->dev, index); 2856 2857 hw_cons = bnx2_get_hw_tx_cons(bnapi); 2858 sw_cons = txr->tx_cons; 2859 2860 while (sw_cons != hw_cons) { 2861 struct bnx2_sw_tx_bd *tx_buf; 2862 struct sk_buff *skb; 2863 int i, last; 2864 2865 sw_ring_cons = BNX2_TX_RING_IDX(sw_cons); 2866 2867 tx_buf = &txr->tx_buf_ring[sw_ring_cons]; 2868 skb = tx_buf->skb; 2869 2870 /* prefetch skb_end_pointer() to speedup skb_shinfo(skb) */ 2871 prefetch(&skb->end); 2872 2873 /* partial BD completions possible with TSO packets */ 2874 if (tx_buf->is_gso) { 2875 u16 last_idx, last_ring_idx; 2876 2877 last_idx = sw_cons + tx_buf->nr_frags + 1; 2878 last_ring_idx = sw_ring_cons + tx_buf->nr_frags + 1; 2879 if (unlikely(last_ring_idx >= BNX2_MAX_TX_DESC_CNT)) { 2880 last_idx++; 2881 } 2882 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) { 2883 break; 2884 } 2885 } 2886 2887 dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping), 2888 skb_headlen(skb), PCI_DMA_TODEVICE); 2889 2890 tx_buf->skb = NULL; 2891 last = tx_buf->nr_frags; 2892 2893 for (i = 0; i < last; i++) { 2894 struct bnx2_sw_tx_bd *tx_buf; 2895 2896 sw_cons = BNX2_NEXT_TX_BD(sw_cons); 2897 2898 tx_buf = &txr->tx_buf_ring[BNX2_TX_RING_IDX(sw_cons)]; 2899 dma_unmap_page(&bp->pdev->dev, 2900 dma_unmap_addr(tx_buf, mapping), 2901 skb_frag_size(&skb_shinfo(skb)->frags[i]), 2902 PCI_DMA_TODEVICE); 2903 } 2904 2905 sw_cons = BNX2_NEXT_TX_BD(sw_cons); 2906 2907 tx_bytes += skb->len; 2908 dev_kfree_skb_any(skb); 2909 tx_pkt++; 2910 if (tx_pkt == budget) 2911 break; 2912 2913 if (hw_cons == sw_cons) 2914 hw_cons = bnx2_get_hw_tx_cons(bnapi); 2915 } 2916 2917 netdev_tx_completed_queue(txq, tx_pkt, tx_bytes); 2918 txr->hw_tx_cons = hw_cons; 2919 txr->tx_cons = sw_cons; 2920 2921 /* Need to make the tx_cons update visible to bnx2_start_xmit() 2922 * before checking for netif_tx_queue_stopped(). Without the 2923 * memory barrier, there is a small possibility that bnx2_start_xmit() 2924 * will miss it and cause the queue to be stopped forever. 2925 */ 2926 smp_mb(); 2927 2928 if (unlikely(netif_tx_queue_stopped(txq)) && 2929 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) { 2930 __netif_tx_lock(txq, smp_processor_id()); 2931 if ((netif_tx_queue_stopped(txq)) && 2932 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) 2933 netif_tx_wake_queue(txq); 2934 __netif_tx_unlock(txq); 2935 } 2936 2937 return tx_pkt; 2938 } 2939 2940 static void 2941 bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, 2942 struct sk_buff *skb, int count) 2943 { 2944 struct bnx2_sw_pg *cons_rx_pg, *prod_rx_pg; 2945 struct bnx2_rx_bd *cons_bd, *prod_bd; 2946 int i; 2947 u16 hw_prod, prod; 2948 u16 cons = rxr->rx_pg_cons; 2949 2950 cons_rx_pg = &rxr->rx_pg_ring[cons]; 2951 2952 /* The caller was unable to allocate a new page to replace the 2953 * last one in the frags array, so we need to recycle that page 2954 * and then free the skb. 2955 */ 2956 if (skb) { 2957 struct page *page; 2958 struct skb_shared_info *shinfo; 2959 2960 shinfo = skb_shinfo(skb); 2961 shinfo->nr_frags--; 2962 page = skb_frag_page(&shinfo->frags[shinfo->nr_frags]); 2963 __skb_frag_set_page(&shinfo->frags[shinfo->nr_frags], NULL); 2964 2965 cons_rx_pg->page = page; 2966 dev_kfree_skb(skb); 2967 } 2968 2969 hw_prod = rxr->rx_pg_prod; 2970 2971 for (i = 0; i < count; i++) { 2972 prod = BNX2_RX_PG_RING_IDX(hw_prod); 2973 2974 prod_rx_pg = &rxr->rx_pg_ring[prod]; 2975 cons_rx_pg = &rxr->rx_pg_ring[cons]; 2976 cons_bd = &rxr->rx_pg_desc_ring[BNX2_RX_RING(cons)] 2977 [BNX2_RX_IDX(cons)]; 2978 prod_bd = &rxr->rx_pg_desc_ring[BNX2_RX_RING(prod)] 2979 [BNX2_RX_IDX(prod)]; 2980 2981 if (prod != cons) { 2982 prod_rx_pg->page = cons_rx_pg->page; 2983 cons_rx_pg->page = NULL; 2984 dma_unmap_addr_set(prod_rx_pg, mapping, 2985 dma_unmap_addr(cons_rx_pg, mapping)); 2986 2987 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi; 2988 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo; 2989 2990 } 2991 cons = BNX2_RX_PG_RING_IDX(BNX2_NEXT_RX_BD(cons)); 2992 hw_prod = BNX2_NEXT_RX_BD(hw_prod); 2993 } 2994 rxr->rx_pg_prod = hw_prod; 2995 rxr->rx_pg_cons = cons; 2996 } 2997 2998 static inline void 2999 bnx2_reuse_rx_data(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, 3000 u8 *data, u16 cons, u16 prod) 3001 { 3002 struct bnx2_sw_bd *cons_rx_buf, *prod_rx_buf; 3003 struct bnx2_rx_bd *cons_bd, *prod_bd; 3004 3005 cons_rx_buf = &rxr->rx_buf_ring[cons]; 3006 prod_rx_buf = &rxr->rx_buf_ring[prod]; 3007 3008 dma_sync_single_for_device(&bp->pdev->dev, 3009 dma_unmap_addr(cons_rx_buf, mapping), 3010 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, PCI_DMA_FROMDEVICE); 3011 3012 rxr->rx_prod_bseq += bp->rx_buf_use_size; 3013 3014 prod_rx_buf->data = data; 3015 3016 if (cons == prod) 3017 return; 3018 3019 dma_unmap_addr_set(prod_rx_buf, mapping, 3020 dma_unmap_addr(cons_rx_buf, mapping)); 3021 3022 cons_bd = &rxr->rx_desc_ring[BNX2_RX_RING(cons)][BNX2_RX_IDX(cons)]; 3023 prod_bd = &rxr->rx_desc_ring[BNX2_RX_RING(prod)][BNX2_RX_IDX(prod)]; 3024 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi; 3025 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo; 3026 } 3027 3028 static struct sk_buff * 3029 bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u8 *data, 3030 unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr, 3031 u32 ring_idx) 3032 { 3033 int err; 3034 u16 prod = ring_idx & 0xffff; 3035 struct sk_buff *skb; 3036 3037 err = bnx2_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC); 3038 if (unlikely(err)) { 3039 bnx2_reuse_rx_data(bp, rxr, data, (u16) (ring_idx >> 16), prod); 3040 error: 3041 if (hdr_len) { 3042 unsigned int raw_len = len + 4; 3043 int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT; 3044 3045 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages); 3046 } 3047 return NULL; 3048 } 3049 3050 dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size, 3051 PCI_DMA_FROMDEVICE); 3052 skb = build_skb(data, 0); 3053 if (!skb) { 3054 kfree(data); 3055 goto error; 3056 } 3057 skb_reserve(skb, ((u8 *)get_l2_fhdr(data) - data) + BNX2_RX_OFFSET); 3058 if (hdr_len == 0) { 3059 skb_put(skb, len); 3060 return skb; 3061 } else { 3062 unsigned int i, frag_len, frag_size, pages; 3063 struct bnx2_sw_pg *rx_pg; 3064 u16 pg_cons = rxr->rx_pg_cons; 3065 u16 pg_prod = rxr->rx_pg_prod; 3066 3067 frag_size = len + 4 - hdr_len; 3068 pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT; 3069 skb_put(skb, hdr_len); 3070 3071 for (i = 0; i < pages; i++) { 3072 dma_addr_t mapping_old; 3073 3074 frag_len = min(frag_size, (unsigned int) PAGE_SIZE); 3075 if (unlikely(frag_len <= 4)) { 3076 unsigned int tail = 4 - frag_len; 3077 3078 rxr->rx_pg_cons = pg_cons; 3079 rxr->rx_pg_prod = pg_prod; 3080 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, 3081 pages - i); 3082 skb->len -= tail; 3083 if (i == 0) { 3084 skb->tail -= tail; 3085 } else { 3086 skb_frag_t *frag = 3087 &skb_shinfo(skb)->frags[i - 1]; 3088 skb_frag_size_sub(frag, tail); 3089 skb->data_len -= tail; 3090 } 3091 return skb; 3092 } 3093 rx_pg = &rxr->rx_pg_ring[pg_cons]; 3094 3095 /* Don't unmap yet. If we're unable to allocate a new 3096 * page, we need to recycle the page and the DMA addr. 3097 */ 3098 mapping_old = dma_unmap_addr(rx_pg, mapping); 3099 if (i == pages - 1) 3100 frag_len -= 4; 3101 3102 skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len); 3103 rx_pg->page = NULL; 3104 3105 err = bnx2_alloc_rx_page(bp, rxr, 3106 BNX2_RX_PG_RING_IDX(pg_prod), 3107 GFP_ATOMIC); 3108 if (unlikely(err)) { 3109 rxr->rx_pg_cons = pg_cons; 3110 rxr->rx_pg_prod = pg_prod; 3111 bnx2_reuse_rx_skb_pages(bp, rxr, skb, 3112 pages - i); 3113 return NULL; 3114 } 3115 3116 dma_unmap_page(&bp->pdev->dev, mapping_old, 3117 PAGE_SIZE, PCI_DMA_FROMDEVICE); 3118 3119 frag_size -= frag_len; 3120 skb->data_len += frag_len; 3121 skb->truesize += PAGE_SIZE; 3122 skb->len += frag_len; 3123 3124 pg_prod = BNX2_NEXT_RX_BD(pg_prod); 3125 pg_cons = BNX2_RX_PG_RING_IDX(BNX2_NEXT_RX_BD(pg_cons)); 3126 } 3127 rxr->rx_pg_prod = pg_prod; 3128 rxr->rx_pg_cons = pg_cons; 3129 } 3130 return skb; 3131 } 3132 3133 static inline u16 3134 bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi) 3135 { 3136 u16 cons; 3137 3138 /* Tell compiler that status block fields can change. */ 3139 barrier(); 3140 cons = *bnapi->hw_rx_cons_ptr; 3141 barrier(); 3142 if (unlikely((cons & BNX2_MAX_RX_DESC_CNT) == BNX2_MAX_RX_DESC_CNT)) 3143 cons++; 3144 return cons; 3145 } 3146 3147 static int 3148 bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget) 3149 { 3150 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; 3151 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod; 3152 struct l2_fhdr *rx_hdr; 3153 int rx_pkt = 0, pg_ring_used = 0; 3154 3155 if (budget <= 0) 3156 return rx_pkt; 3157 3158 hw_cons = bnx2_get_hw_rx_cons(bnapi); 3159 sw_cons = rxr->rx_cons; 3160 sw_prod = rxr->rx_prod; 3161 3162 /* Memory barrier necessary as speculative reads of the rx 3163 * buffer can be ahead of the index in the status block 3164 */ 3165 rmb(); 3166 while (sw_cons != hw_cons) { 3167 unsigned int len, hdr_len; 3168 u32 status; 3169 struct bnx2_sw_bd *rx_buf, *next_rx_buf; 3170 struct sk_buff *skb; 3171 dma_addr_t dma_addr; 3172 u8 *data; 3173 u16 next_ring_idx; 3174 3175 sw_ring_cons = BNX2_RX_RING_IDX(sw_cons); 3176 sw_ring_prod = BNX2_RX_RING_IDX(sw_prod); 3177 3178 rx_buf = &rxr->rx_buf_ring[sw_ring_cons]; 3179 data = rx_buf->data; 3180 rx_buf->data = NULL; 3181 3182 rx_hdr = get_l2_fhdr(data); 3183 prefetch(rx_hdr); 3184 3185 dma_addr = dma_unmap_addr(rx_buf, mapping); 3186 3187 dma_sync_single_for_cpu(&bp->pdev->dev, dma_addr, 3188 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, 3189 PCI_DMA_FROMDEVICE); 3190 3191 next_ring_idx = BNX2_RX_RING_IDX(BNX2_NEXT_RX_BD(sw_cons)); 3192 next_rx_buf = &rxr->rx_buf_ring[next_ring_idx]; 3193 prefetch(get_l2_fhdr(next_rx_buf->data)); 3194 3195 len = rx_hdr->l2_fhdr_pkt_len; 3196 status = rx_hdr->l2_fhdr_status; 3197 3198 hdr_len = 0; 3199 if (status & L2_FHDR_STATUS_SPLIT) { 3200 hdr_len = rx_hdr->l2_fhdr_ip_xsum; 3201 pg_ring_used = 1; 3202 } else if (len > bp->rx_jumbo_thresh) { 3203 hdr_len = bp->rx_jumbo_thresh; 3204 pg_ring_used = 1; 3205 } 3206 3207 if (unlikely(status & (L2_FHDR_ERRORS_BAD_CRC | 3208 L2_FHDR_ERRORS_PHY_DECODE | 3209 L2_FHDR_ERRORS_ALIGNMENT | 3210 L2_FHDR_ERRORS_TOO_SHORT | 3211 L2_FHDR_ERRORS_GIANT_FRAME))) { 3212 3213 bnx2_reuse_rx_data(bp, rxr, data, sw_ring_cons, 3214 sw_ring_prod); 3215 if (pg_ring_used) { 3216 int pages; 3217 3218 pages = PAGE_ALIGN(len - hdr_len) >> PAGE_SHIFT; 3219 3220 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages); 3221 } 3222 goto next_rx; 3223 } 3224 3225 len -= 4; 3226 3227 if (len <= bp->rx_copy_thresh) { 3228 skb = netdev_alloc_skb(bp->dev, len + 6); 3229 if (skb == NULL) { 3230 bnx2_reuse_rx_data(bp, rxr, data, sw_ring_cons, 3231 sw_ring_prod); 3232 goto next_rx; 3233 } 3234 3235 /* aligned copy */ 3236 memcpy(skb->data, 3237 (u8 *)rx_hdr + BNX2_RX_OFFSET - 6, 3238 len + 6); 3239 skb_reserve(skb, 6); 3240 skb_put(skb, len); 3241 3242 bnx2_reuse_rx_data(bp, rxr, data, 3243 sw_ring_cons, sw_ring_prod); 3244 3245 } else { 3246 skb = bnx2_rx_skb(bp, rxr, data, len, hdr_len, dma_addr, 3247 (sw_ring_cons << 16) | sw_ring_prod); 3248 if (!skb) 3249 goto next_rx; 3250 } 3251 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && 3252 !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) 3253 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), rx_hdr->l2_fhdr_vlan_tag); 3254 3255 skb->protocol = eth_type_trans(skb, bp->dev); 3256 3257 if (len > (bp->dev->mtu + ETH_HLEN) && 3258 skb->protocol != htons(0x8100) && 3259 skb->protocol != htons(ETH_P_8021AD)) { 3260 3261 dev_kfree_skb(skb); 3262 goto next_rx; 3263 3264 } 3265 3266 skb_checksum_none_assert(skb); 3267 if ((bp->dev->features & NETIF_F_RXCSUM) && 3268 (status & (L2_FHDR_STATUS_TCP_SEGMENT | 3269 L2_FHDR_STATUS_UDP_DATAGRAM))) { 3270 3271 if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM | 3272 L2_FHDR_ERRORS_UDP_XSUM)) == 0)) 3273 skb->ip_summed = CHECKSUM_UNNECESSARY; 3274 } 3275 if ((bp->dev->features & NETIF_F_RXHASH) && 3276 ((status & L2_FHDR_STATUS_USE_RXHASH) == 3277 L2_FHDR_STATUS_USE_RXHASH)) 3278 skb_set_hash(skb, rx_hdr->l2_fhdr_hash, 3279 PKT_HASH_TYPE_L3); 3280 3281 skb_record_rx_queue(skb, bnapi - &bp->bnx2_napi[0]); 3282 napi_gro_receive(&bnapi->napi, skb); 3283 rx_pkt++; 3284 3285 next_rx: 3286 sw_cons = BNX2_NEXT_RX_BD(sw_cons); 3287 sw_prod = BNX2_NEXT_RX_BD(sw_prod); 3288 3289 if ((rx_pkt == budget)) 3290 break; 3291 3292 /* Refresh hw_cons to see if there is new work */ 3293 if (sw_cons == hw_cons) { 3294 hw_cons = bnx2_get_hw_rx_cons(bnapi); 3295 rmb(); 3296 } 3297 } 3298 rxr->rx_cons = sw_cons; 3299 rxr->rx_prod = sw_prod; 3300 3301 if (pg_ring_used) 3302 BNX2_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod); 3303 3304 BNX2_WR16(bp, rxr->rx_bidx_addr, sw_prod); 3305 3306 BNX2_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq); 3307 3308 mmiowb(); 3309 3310 return rx_pkt; 3311 3312 } 3313 3314 /* MSI ISR - The only difference between this and the INTx ISR 3315 * is that the MSI interrupt is always serviced. 3316 */ 3317 static irqreturn_t 3318 bnx2_msi(int irq, void *dev_instance) 3319 { 3320 struct bnx2_napi *bnapi = dev_instance; 3321 struct bnx2 *bp = bnapi->bp; 3322 3323 prefetch(bnapi->status_blk.msi); 3324 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, 3325 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | 3326 BNX2_PCICFG_INT_ACK_CMD_MASK_INT); 3327 3328 /* Return here if interrupt is disabled. */ 3329 if (unlikely(atomic_read(&bp->intr_sem) != 0)) 3330 return IRQ_HANDLED; 3331 3332 napi_schedule(&bnapi->napi); 3333 3334 return IRQ_HANDLED; 3335 } 3336 3337 static irqreturn_t 3338 bnx2_msi_1shot(int irq, void *dev_instance) 3339 { 3340 struct bnx2_napi *bnapi = dev_instance; 3341 struct bnx2 *bp = bnapi->bp; 3342 3343 prefetch(bnapi->status_blk.msi); 3344 3345 /* Return here if interrupt is disabled. */ 3346 if (unlikely(atomic_read(&bp->intr_sem) != 0)) 3347 return IRQ_HANDLED; 3348 3349 napi_schedule(&bnapi->napi); 3350 3351 return IRQ_HANDLED; 3352 } 3353 3354 static irqreturn_t 3355 bnx2_interrupt(int irq, void *dev_instance) 3356 { 3357 struct bnx2_napi *bnapi = dev_instance; 3358 struct bnx2 *bp = bnapi->bp; 3359 struct status_block *sblk = bnapi->status_blk.msi; 3360 3361 /* When using INTx, it is possible for the interrupt to arrive 3362 * at the CPU before the status block posted prior to the 3363 * interrupt. Reading a register will flush the status block. 3364 * When using MSI, the MSI message will always complete after 3365 * the status block write. 3366 */ 3367 if ((sblk->status_idx == bnapi->last_status_idx) && 3368 (BNX2_RD(bp, BNX2_PCICFG_MISC_STATUS) & 3369 BNX2_PCICFG_MISC_STATUS_INTA_VALUE)) 3370 return IRQ_NONE; 3371 3372 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, 3373 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | 3374 BNX2_PCICFG_INT_ACK_CMD_MASK_INT); 3375 3376 /* Read back to deassert IRQ immediately to avoid too many 3377 * spurious interrupts. 3378 */ 3379 BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD); 3380 3381 /* Return here if interrupt is shared and is disabled. */ 3382 if (unlikely(atomic_read(&bp->intr_sem) != 0)) 3383 return IRQ_HANDLED; 3384 3385 if (napi_schedule_prep(&bnapi->napi)) { 3386 bnapi->last_status_idx = sblk->status_idx; 3387 __napi_schedule(&bnapi->napi); 3388 } 3389 3390 return IRQ_HANDLED; 3391 } 3392 3393 static inline int 3394 bnx2_has_fast_work(struct bnx2_napi *bnapi) 3395 { 3396 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; 3397 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; 3398 3399 if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) || 3400 (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)) 3401 return 1; 3402 return 0; 3403 } 3404 3405 #define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \ 3406 STATUS_ATTN_BITS_TIMER_ABORT) 3407 3408 static inline int 3409 bnx2_has_work(struct bnx2_napi *bnapi) 3410 { 3411 struct status_block *sblk = bnapi->status_blk.msi; 3412 3413 if (bnx2_has_fast_work(bnapi)) 3414 return 1; 3415 3416 #ifdef BCM_CNIC 3417 if (bnapi->cnic_present && (bnapi->cnic_tag != sblk->status_idx)) 3418 return 1; 3419 #endif 3420 3421 if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) != 3422 (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS)) 3423 return 1; 3424 3425 return 0; 3426 } 3427 3428 static void 3429 bnx2_chk_missed_msi(struct bnx2 *bp) 3430 { 3431 struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; 3432 u32 msi_ctrl; 3433 3434 if (bnx2_has_work(bnapi)) { 3435 msi_ctrl = BNX2_RD(bp, BNX2_PCICFG_MSI_CONTROL); 3436 if (!(msi_ctrl & BNX2_PCICFG_MSI_CONTROL_ENABLE)) 3437 return; 3438 3439 if (bnapi->last_status_idx == bp->idle_chk_status_idx) { 3440 BNX2_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl & 3441 ~BNX2_PCICFG_MSI_CONTROL_ENABLE); 3442 BNX2_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl); 3443 bnx2_msi(bp->irq_tbl[0].vector, bnapi); 3444 } 3445 } 3446 3447 bp->idle_chk_status_idx = bnapi->last_status_idx; 3448 } 3449 3450 #ifdef BCM_CNIC 3451 static void bnx2_poll_cnic(struct bnx2 *bp, struct bnx2_napi *bnapi) 3452 { 3453 struct cnic_ops *c_ops; 3454 3455 if (!bnapi->cnic_present) 3456 return; 3457 3458 rcu_read_lock(); 3459 c_ops = rcu_dereference(bp->cnic_ops); 3460 if (c_ops) 3461 bnapi->cnic_tag = c_ops->cnic_handler(bp->cnic_data, 3462 bnapi->status_blk.msi); 3463 rcu_read_unlock(); 3464 } 3465 #endif 3466 3467 static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi) 3468 { 3469 struct status_block *sblk = bnapi->status_blk.msi; 3470 u32 status_attn_bits = sblk->status_attn_bits; 3471 u32 status_attn_bits_ack = sblk->status_attn_bits_ack; 3472 3473 if ((status_attn_bits & STATUS_ATTN_EVENTS) != 3474 (status_attn_bits_ack & STATUS_ATTN_EVENTS)) { 3475 3476 bnx2_phy_int(bp, bnapi); 3477 3478 /* This is needed to take care of transient status 3479 * during link changes. 3480 */ 3481 BNX2_WR(bp, BNX2_HC_COMMAND, 3482 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT); 3483 BNX2_RD(bp, BNX2_HC_COMMAND); 3484 } 3485 } 3486 3487 static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi, 3488 int work_done, int budget) 3489 { 3490 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; 3491 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; 3492 3493 if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons) 3494 bnx2_tx_int(bp, bnapi, 0); 3495 3496 if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) 3497 work_done += bnx2_rx_int(bp, bnapi, budget - work_done); 3498 3499 return work_done; 3500 } 3501 3502 static int bnx2_poll_msix(struct napi_struct *napi, int budget) 3503 { 3504 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi); 3505 struct bnx2 *bp = bnapi->bp; 3506 int work_done = 0; 3507 struct status_block_msix *sblk = bnapi->status_blk.msix; 3508 3509 while (1) { 3510 work_done = bnx2_poll_work(bp, bnapi, work_done, budget); 3511 if (unlikely(work_done >= budget)) 3512 break; 3513 3514 bnapi->last_status_idx = sblk->status_idx; 3515 /* status idx must be read before checking for more work. */ 3516 rmb(); 3517 if (likely(!bnx2_has_fast_work(bnapi))) { 3518 3519 napi_complete(napi); 3520 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num | 3521 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | 3522 bnapi->last_status_idx); 3523 break; 3524 } 3525 } 3526 return work_done; 3527 } 3528 3529 static int bnx2_poll(struct napi_struct *napi, int budget) 3530 { 3531 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi); 3532 struct bnx2 *bp = bnapi->bp; 3533 int work_done = 0; 3534 struct status_block *sblk = bnapi->status_blk.msi; 3535 3536 while (1) { 3537 bnx2_poll_link(bp, bnapi); 3538 3539 work_done = bnx2_poll_work(bp, bnapi, work_done, budget); 3540 3541 #ifdef BCM_CNIC 3542 bnx2_poll_cnic(bp, bnapi); 3543 #endif 3544 3545 /* bnapi->last_status_idx is used below to tell the hw how 3546 * much work has been processed, so we must read it before 3547 * checking for more work. 3548 */ 3549 bnapi->last_status_idx = sblk->status_idx; 3550 3551 if (unlikely(work_done >= budget)) 3552 break; 3553 3554 rmb(); 3555 if (likely(!bnx2_has_work(bnapi))) { 3556 napi_complete(napi); 3557 if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) { 3558 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, 3559 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | 3560 bnapi->last_status_idx); 3561 break; 3562 } 3563 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, 3564 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | 3565 BNX2_PCICFG_INT_ACK_CMD_MASK_INT | 3566 bnapi->last_status_idx); 3567 3568 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, 3569 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | 3570 bnapi->last_status_idx); 3571 break; 3572 } 3573 } 3574 3575 return work_done; 3576 } 3577 3578 /* Called with rtnl_lock from vlan functions and also netif_tx_lock 3579 * from set_multicast. 3580 */ 3581 static void 3582 bnx2_set_rx_mode(struct net_device *dev) 3583 { 3584 struct bnx2 *bp = netdev_priv(dev); 3585 u32 rx_mode, sort_mode; 3586 struct netdev_hw_addr *ha; 3587 int i; 3588 3589 if (!netif_running(dev)) 3590 return; 3591 3592 spin_lock_bh(&bp->phy_lock); 3593 3594 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS | 3595 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG); 3596 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN; 3597 if (!(dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 3598 (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)) 3599 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG; 3600 if (dev->flags & IFF_PROMISC) { 3601 /* Promiscuous mode. */ 3602 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS; 3603 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN | 3604 BNX2_RPM_SORT_USER0_PROM_VLAN; 3605 } 3606 else if (dev->flags & IFF_ALLMULTI) { 3607 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { 3608 BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4), 3609 0xffffffff); 3610 } 3611 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN; 3612 } 3613 else { 3614 /* Accept one or more multicast(s). */ 3615 u32 mc_filter[NUM_MC_HASH_REGISTERS]; 3616 u32 regidx; 3617 u32 bit; 3618 u32 crc; 3619 3620 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS); 3621 3622 netdev_for_each_mc_addr(ha, dev) { 3623 crc = ether_crc_le(ETH_ALEN, ha->addr); 3624 bit = crc & 0xff; 3625 regidx = (bit & 0xe0) >> 5; 3626 bit &= 0x1f; 3627 mc_filter[regidx] |= (1 << bit); 3628 } 3629 3630 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { 3631 BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4), 3632 mc_filter[i]); 3633 } 3634 3635 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN; 3636 } 3637 3638 if (netdev_uc_count(dev) > BNX2_MAX_UNICAST_ADDRESSES) { 3639 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS; 3640 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN | 3641 BNX2_RPM_SORT_USER0_PROM_VLAN; 3642 } else if (!(dev->flags & IFF_PROMISC)) { 3643 /* Add all entries into to the match filter list */ 3644 i = 0; 3645 netdev_for_each_uc_addr(ha, dev) { 3646 bnx2_set_mac_addr(bp, ha->addr, 3647 i + BNX2_START_UNICAST_ADDRESS_INDEX); 3648 sort_mode |= (1 << 3649 (i + BNX2_START_UNICAST_ADDRESS_INDEX)); 3650 i++; 3651 } 3652 3653 } 3654 3655 if (rx_mode != bp->rx_mode) { 3656 bp->rx_mode = rx_mode; 3657 BNX2_WR(bp, BNX2_EMAC_RX_MODE, rx_mode); 3658 } 3659 3660 BNX2_WR(bp, BNX2_RPM_SORT_USER0, 0x0); 3661 BNX2_WR(bp, BNX2_RPM_SORT_USER0, sort_mode); 3662 BNX2_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA); 3663 3664 spin_unlock_bh(&bp->phy_lock); 3665 } 3666 3667 static int 3668 check_fw_section(const struct firmware *fw, 3669 const struct bnx2_fw_file_section *section, 3670 u32 alignment, bool non_empty) 3671 { 3672 u32 offset = be32_to_cpu(section->offset); 3673 u32 len = be32_to_cpu(section->len); 3674 3675 if ((offset == 0 && len != 0) || offset >= fw->size || offset & 3) 3676 return -EINVAL; 3677 if ((non_empty && len == 0) || len > fw->size - offset || 3678 len & (alignment - 1)) 3679 return -EINVAL; 3680 return 0; 3681 } 3682 3683 static int 3684 check_mips_fw_entry(const struct firmware *fw, 3685 const struct bnx2_mips_fw_file_entry *entry) 3686 { 3687 if (check_fw_section(fw, &entry->text, 4, true) || 3688 check_fw_section(fw, &entry->data, 4, false) || 3689 check_fw_section(fw, &entry->rodata, 4, false)) 3690 return -EINVAL; 3691 return 0; 3692 } 3693 3694 static void bnx2_release_firmware(struct bnx2 *bp) 3695 { 3696 if (bp->rv2p_firmware) { 3697 release_firmware(bp->mips_firmware); 3698 release_firmware(bp->rv2p_firmware); 3699 bp->rv2p_firmware = NULL; 3700 } 3701 } 3702 3703 static int bnx2_request_uncached_firmware(struct bnx2 *bp) 3704 { 3705 const char *mips_fw_file, *rv2p_fw_file; 3706 const struct bnx2_mips_fw_file *mips_fw; 3707 const struct bnx2_rv2p_fw_file *rv2p_fw; 3708 int rc; 3709 3710 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { 3711 mips_fw_file = FW_MIPS_FILE_09; 3712 if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5709_A0) || 3713 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5709_A1)) 3714 rv2p_fw_file = FW_RV2P_FILE_09_Ax; 3715 else 3716 rv2p_fw_file = FW_RV2P_FILE_09; 3717 } else { 3718 mips_fw_file = FW_MIPS_FILE_06; 3719 rv2p_fw_file = FW_RV2P_FILE_06; 3720 } 3721 3722 rc = request_firmware(&bp->mips_firmware, mips_fw_file, &bp->pdev->dev); 3723 if (rc) { 3724 pr_err("Can't load firmware file \"%s\"\n", mips_fw_file); 3725 goto out; 3726 } 3727 3728 rc = request_firmware(&bp->rv2p_firmware, rv2p_fw_file, &bp->pdev->dev); 3729 if (rc) { 3730 pr_err("Can't load firmware file \"%s\"\n", rv2p_fw_file); 3731 goto err_release_mips_firmware; 3732 } 3733 mips_fw = (const struct bnx2_mips_fw_file *) bp->mips_firmware->data; 3734 rv2p_fw = (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data; 3735 if (bp->mips_firmware->size < sizeof(*mips_fw) || 3736 check_mips_fw_entry(bp->mips_firmware, &mips_fw->com) || 3737 check_mips_fw_entry(bp->mips_firmware, &mips_fw->cp) || 3738 check_mips_fw_entry(bp->mips_firmware, &mips_fw->rxp) || 3739 check_mips_fw_entry(bp->mips_firmware, &mips_fw->tpat) || 3740 check_mips_fw_entry(bp->mips_firmware, &mips_fw->txp)) { 3741 pr_err("Firmware file \"%s\" is invalid\n", mips_fw_file); 3742 rc = -EINVAL; 3743 goto err_release_firmware; 3744 } 3745 if (bp->rv2p_firmware->size < sizeof(*rv2p_fw) || 3746 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc1.rv2p, 8, true) || 3747 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc2.rv2p, 8, true)) { 3748 pr_err("Firmware file \"%s\" is invalid\n", rv2p_fw_file); 3749 rc = -EINVAL; 3750 goto err_release_firmware; 3751 } 3752 out: 3753 return rc; 3754 3755 err_release_firmware: 3756 release_firmware(bp->rv2p_firmware); 3757 bp->rv2p_firmware = NULL; 3758 err_release_mips_firmware: 3759 release_firmware(bp->mips_firmware); 3760 goto out; 3761 } 3762 3763 static int bnx2_request_firmware(struct bnx2 *bp) 3764 { 3765 return bp->rv2p_firmware ? 0 : bnx2_request_uncached_firmware(bp); 3766 } 3767 3768 static u32 3769 rv2p_fw_fixup(u32 rv2p_proc, int idx, u32 loc, u32 rv2p_code) 3770 { 3771 switch (idx) { 3772 case RV2P_P1_FIXUP_PAGE_SIZE_IDX: 3773 rv2p_code &= ~RV2P_BD_PAGE_SIZE_MSK; 3774 rv2p_code |= RV2P_BD_PAGE_SIZE; 3775 break; 3776 } 3777 return rv2p_code; 3778 } 3779 3780 static int 3781 load_rv2p_fw(struct bnx2 *bp, u32 rv2p_proc, 3782 const struct bnx2_rv2p_fw_file_entry *fw_entry) 3783 { 3784 u32 rv2p_code_len, file_offset; 3785 __be32 *rv2p_code; 3786 int i; 3787 u32 val, cmd, addr; 3788 3789 rv2p_code_len = be32_to_cpu(fw_entry->rv2p.len); 3790 file_offset = be32_to_cpu(fw_entry->rv2p.offset); 3791 3792 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset); 3793 3794 if (rv2p_proc == RV2P_PROC1) { 3795 cmd = BNX2_RV2P_PROC1_ADDR_CMD_RDWR; 3796 addr = BNX2_RV2P_PROC1_ADDR_CMD; 3797 } else { 3798 cmd = BNX2_RV2P_PROC2_ADDR_CMD_RDWR; 3799 addr = BNX2_RV2P_PROC2_ADDR_CMD; 3800 } 3801 3802 for (i = 0; i < rv2p_code_len; i += 8) { 3803 BNX2_WR(bp, BNX2_RV2P_INSTR_HIGH, be32_to_cpu(*rv2p_code)); 3804 rv2p_code++; 3805 BNX2_WR(bp, BNX2_RV2P_INSTR_LOW, be32_to_cpu(*rv2p_code)); 3806 rv2p_code++; 3807 3808 val = (i / 8) | cmd; 3809 BNX2_WR(bp, addr, val); 3810 } 3811 3812 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset); 3813 for (i = 0; i < 8; i++) { 3814 u32 loc, code; 3815 3816 loc = be32_to_cpu(fw_entry->fixup[i]); 3817 if (loc && ((loc * 4) < rv2p_code_len)) { 3818 code = be32_to_cpu(*(rv2p_code + loc - 1)); 3819 BNX2_WR(bp, BNX2_RV2P_INSTR_HIGH, code); 3820 code = be32_to_cpu(*(rv2p_code + loc)); 3821 code = rv2p_fw_fixup(rv2p_proc, i, loc, code); 3822 BNX2_WR(bp, BNX2_RV2P_INSTR_LOW, code); 3823 3824 val = (loc / 2) | cmd; 3825 BNX2_WR(bp, addr, val); 3826 } 3827 } 3828 3829 /* Reset the processor, un-stall is done later. */ 3830 if (rv2p_proc == RV2P_PROC1) { 3831 BNX2_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET); 3832 } 3833 else { 3834 BNX2_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET); 3835 } 3836 3837 return 0; 3838 } 3839 3840 static int 3841 load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg, 3842 const struct bnx2_mips_fw_file_entry *fw_entry) 3843 { 3844 u32 addr, len, file_offset; 3845 __be32 *data; 3846 u32 offset; 3847 u32 val; 3848 3849 /* Halt the CPU. */ 3850 val = bnx2_reg_rd_ind(bp, cpu_reg->mode); 3851 val |= cpu_reg->mode_value_halt; 3852 bnx2_reg_wr_ind(bp, cpu_reg->mode, val); 3853 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear); 3854 3855 /* Load the Text area. */ 3856 addr = be32_to_cpu(fw_entry->text.addr); 3857 len = be32_to_cpu(fw_entry->text.len); 3858 file_offset = be32_to_cpu(fw_entry->text.offset); 3859 data = (__be32 *)(bp->mips_firmware->data + file_offset); 3860 3861 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base); 3862 if (len) { 3863 int j; 3864 3865 for (j = 0; j < (len / 4); j++, offset += 4) 3866 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j])); 3867 } 3868 3869 /* Load the Data area. */ 3870 addr = be32_to_cpu(fw_entry->data.addr); 3871 len = be32_to_cpu(fw_entry->data.len); 3872 file_offset = be32_to_cpu(fw_entry->data.offset); 3873 data = (__be32 *)(bp->mips_firmware->data + file_offset); 3874 3875 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base); 3876 if (len) { 3877 int j; 3878 3879 for (j = 0; j < (len / 4); j++, offset += 4) 3880 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j])); 3881 } 3882 3883 /* Load the Read-Only area. */ 3884 addr = be32_to_cpu(fw_entry->rodata.addr); 3885 len = be32_to_cpu(fw_entry->rodata.len); 3886 file_offset = be32_to_cpu(fw_entry->rodata.offset); 3887 data = (__be32 *)(bp->mips_firmware->data + file_offset); 3888 3889 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base); 3890 if (len) { 3891 int j; 3892 3893 for (j = 0; j < (len / 4); j++, offset += 4) 3894 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j])); 3895 } 3896 3897 /* Clear the pre-fetch instruction. */ 3898 bnx2_reg_wr_ind(bp, cpu_reg->inst, 0); 3899 3900 val = be32_to_cpu(fw_entry->start_addr); 3901 bnx2_reg_wr_ind(bp, cpu_reg->pc, val); 3902 3903 /* Start the CPU. */ 3904 val = bnx2_reg_rd_ind(bp, cpu_reg->mode); 3905 val &= ~cpu_reg->mode_value_halt; 3906 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear); 3907 bnx2_reg_wr_ind(bp, cpu_reg->mode, val); 3908 3909 return 0; 3910 } 3911 3912 static int 3913 bnx2_init_cpus(struct bnx2 *bp) 3914 { 3915 const struct bnx2_mips_fw_file *mips_fw = 3916 (const struct bnx2_mips_fw_file *) bp->mips_firmware->data; 3917 const struct bnx2_rv2p_fw_file *rv2p_fw = 3918 (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data; 3919 int rc; 3920 3921 /* Initialize the RV2P processor. */ 3922 load_rv2p_fw(bp, RV2P_PROC1, &rv2p_fw->proc1); 3923 load_rv2p_fw(bp, RV2P_PROC2, &rv2p_fw->proc2); 3924 3925 /* Initialize the RX Processor. */ 3926 rc = load_cpu_fw(bp, &cpu_reg_rxp, &mips_fw->rxp); 3927 if (rc) 3928 goto init_cpu_err; 3929 3930 /* Initialize the TX Processor. */ 3931 rc = load_cpu_fw(bp, &cpu_reg_txp, &mips_fw->txp); 3932 if (rc) 3933 goto init_cpu_err; 3934 3935 /* Initialize the TX Patch-up Processor. */ 3936 rc = load_cpu_fw(bp, &cpu_reg_tpat, &mips_fw->tpat); 3937 if (rc) 3938 goto init_cpu_err; 3939 3940 /* Initialize the Completion Processor. */ 3941 rc = load_cpu_fw(bp, &cpu_reg_com, &mips_fw->com); 3942 if (rc) 3943 goto init_cpu_err; 3944 3945 /* Initialize the Command Processor. */ 3946 rc = load_cpu_fw(bp, &cpu_reg_cp, &mips_fw->cp); 3947 3948 init_cpu_err: 3949 return rc; 3950 } 3951 3952 static void 3953 bnx2_setup_wol(struct bnx2 *bp) 3954 { 3955 int i; 3956 u32 val, wol_msg; 3957 3958 if (bp->wol) { 3959 u32 advertising; 3960 u8 autoneg; 3961 3962 autoneg = bp->autoneg; 3963 advertising = bp->advertising; 3964 3965 if (bp->phy_port == PORT_TP) { 3966 bp->autoneg = AUTONEG_SPEED; 3967 bp->advertising = ADVERTISED_10baseT_Half | 3968 ADVERTISED_10baseT_Full | 3969 ADVERTISED_100baseT_Half | 3970 ADVERTISED_100baseT_Full | 3971 ADVERTISED_Autoneg; 3972 } 3973 3974 spin_lock_bh(&bp->phy_lock); 3975 bnx2_setup_phy(bp, bp->phy_port); 3976 spin_unlock_bh(&bp->phy_lock); 3977 3978 bp->autoneg = autoneg; 3979 bp->advertising = advertising; 3980 3981 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0); 3982 3983 val = BNX2_RD(bp, BNX2_EMAC_MODE); 3984 3985 /* Enable port mode. */ 3986 val &= ~BNX2_EMAC_MODE_PORT; 3987 val |= BNX2_EMAC_MODE_MPKT_RCVD | 3988 BNX2_EMAC_MODE_ACPI_RCVD | 3989 BNX2_EMAC_MODE_MPKT; 3990 if (bp->phy_port == PORT_TP) { 3991 val |= BNX2_EMAC_MODE_PORT_MII; 3992 } else { 3993 val |= BNX2_EMAC_MODE_PORT_GMII; 3994 if (bp->line_speed == SPEED_2500) 3995 val |= BNX2_EMAC_MODE_25G_MODE; 3996 } 3997 3998 BNX2_WR(bp, BNX2_EMAC_MODE, val); 3999 4000 /* receive all multicast */ 4001 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { 4002 BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4), 4003 0xffffffff); 4004 } 4005 BNX2_WR(bp, BNX2_EMAC_RX_MODE, BNX2_EMAC_RX_MODE_SORT_MODE); 4006 4007 val = 1 | BNX2_RPM_SORT_USER0_BC_EN | BNX2_RPM_SORT_USER0_MC_EN; 4008 BNX2_WR(bp, BNX2_RPM_SORT_USER0, 0x0); 4009 BNX2_WR(bp, BNX2_RPM_SORT_USER0, val); 4010 BNX2_WR(bp, BNX2_RPM_SORT_USER0, val | BNX2_RPM_SORT_USER0_ENA); 4011 4012 /* Need to enable EMAC and RPM for WOL. */ 4013 BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS, 4014 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE | 4015 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE | 4016 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE); 4017 4018 val = BNX2_RD(bp, BNX2_RPM_CONFIG); 4019 val &= ~BNX2_RPM_CONFIG_ACPI_ENA; 4020 BNX2_WR(bp, BNX2_RPM_CONFIG, val); 4021 4022 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL; 4023 } else { 4024 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL; 4025 } 4026 4027 if (!(bp->flags & BNX2_FLAG_NO_WOL)) { 4028 u32 val; 4029 4030 wol_msg |= BNX2_DRV_MSG_DATA_WAIT3; 4031 if (bp->fw_last_msg || BNX2_CHIP(bp) != BNX2_CHIP_5709) { 4032 bnx2_fw_sync(bp, wol_msg, 1, 0); 4033 return; 4034 } 4035 /* Tell firmware not to power down the PHY yet, otherwise 4036 * the chip will take a long time to respond to MMIO reads. 4037 */ 4038 val = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE); 4039 bnx2_shmem_wr(bp, BNX2_PORT_FEATURE, 4040 val | BNX2_PORT_FEATURE_ASF_ENABLED); 4041 bnx2_fw_sync(bp, wol_msg, 1, 0); 4042 bnx2_shmem_wr(bp, BNX2_PORT_FEATURE, val); 4043 } 4044 4045 } 4046 4047 static int 4048 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state) 4049 { 4050 switch (state) { 4051 case PCI_D0: { 4052 u32 val; 4053 4054 pci_enable_wake(bp->pdev, PCI_D0, false); 4055 pci_set_power_state(bp->pdev, PCI_D0); 4056 4057 val = BNX2_RD(bp, BNX2_EMAC_MODE); 4058 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD; 4059 val &= ~BNX2_EMAC_MODE_MPKT; 4060 BNX2_WR(bp, BNX2_EMAC_MODE, val); 4061 4062 val = BNX2_RD(bp, BNX2_RPM_CONFIG); 4063 val &= ~BNX2_RPM_CONFIG_ACPI_ENA; 4064 BNX2_WR(bp, BNX2_RPM_CONFIG, val); 4065 break; 4066 } 4067 case PCI_D3hot: { 4068 bnx2_setup_wol(bp); 4069 pci_wake_from_d3(bp->pdev, bp->wol); 4070 if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) || 4071 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1)) { 4072 4073 if (bp->wol) 4074 pci_set_power_state(bp->pdev, PCI_D3hot); 4075 break; 4076 4077 } 4078 if (!bp->fw_last_msg && BNX2_CHIP(bp) == BNX2_CHIP_5709) { 4079 u32 val; 4080 4081 /* Tell firmware not to power down the PHY yet, 4082 * otherwise the other port may not respond to 4083 * MMIO reads. 4084 */ 4085 val = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION); 4086 val &= ~BNX2_CONDITION_PM_STATE_MASK; 4087 val |= BNX2_CONDITION_PM_STATE_UNPREP; 4088 bnx2_shmem_wr(bp, BNX2_BC_STATE_CONDITION, val); 4089 } 4090 pci_set_power_state(bp->pdev, PCI_D3hot); 4091 4092 /* No more memory access after this point until 4093 * device is brought back to D0. 4094 */ 4095 break; 4096 } 4097 default: 4098 return -EINVAL; 4099 } 4100 return 0; 4101 } 4102 4103 static int 4104 bnx2_acquire_nvram_lock(struct bnx2 *bp) 4105 { 4106 u32 val; 4107 int j; 4108 4109 /* Request access to the flash interface. */ 4110 BNX2_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2); 4111 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 4112 val = BNX2_RD(bp, BNX2_NVM_SW_ARB); 4113 if (val & BNX2_NVM_SW_ARB_ARB_ARB2) 4114 break; 4115 4116 udelay(5); 4117 } 4118 4119 if (j >= NVRAM_TIMEOUT_COUNT) 4120 return -EBUSY; 4121 4122 return 0; 4123 } 4124 4125 static int 4126 bnx2_release_nvram_lock(struct bnx2 *bp) 4127 { 4128 int j; 4129 u32 val; 4130 4131 /* Relinquish nvram interface. */ 4132 BNX2_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2); 4133 4134 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 4135 val = BNX2_RD(bp, BNX2_NVM_SW_ARB); 4136 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2)) 4137 break; 4138 4139 udelay(5); 4140 } 4141 4142 if (j >= NVRAM_TIMEOUT_COUNT) 4143 return -EBUSY; 4144 4145 return 0; 4146 } 4147 4148 4149 static int 4150 bnx2_enable_nvram_write(struct bnx2 *bp) 4151 { 4152 u32 val; 4153 4154 val = BNX2_RD(bp, BNX2_MISC_CFG); 4155 BNX2_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI); 4156 4157 if (bp->flash_info->flags & BNX2_NV_WREN) { 4158 int j; 4159 4160 BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE); 4161 BNX2_WR(bp, BNX2_NVM_COMMAND, 4162 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT); 4163 4164 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 4165 udelay(5); 4166 4167 val = BNX2_RD(bp, BNX2_NVM_COMMAND); 4168 if (val & BNX2_NVM_COMMAND_DONE) 4169 break; 4170 } 4171 4172 if (j >= NVRAM_TIMEOUT_COUNT) 4173 return -EBUSY; 4174 } 4175 return 0; 4176 } 4177 4178 static void 4179 bnx2_disable_nvram_write(struct bnx2 *bp) 4180 { 4181 u32 val; 4182 4183 val = BNX2_RD(bp, BNX2_MISC_CFG); 4184 BNX2_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN); 4185 } 4186 4187 4188 static void 4189 bnx2_enable_nvram_access(struct bnx2 *bp) 4190 { 4191 u32 val; 4192 4193 val = BNX2_RD(bp, BNX2_NVM_ACCESS_ENABLE); 4194 /* Enable both bits, even on read. */ 4195 BNX2_WR(bp, BNX2_NVM_ACCESS_ENABLE, 4196 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN); 4197 } 4198 4199 static void 4200 bnx2_disable_nvram_access(struct bnx2 *bp) 4201 { 4202 u32 val; 4203 4204 val = BNX2_RD(bp, BNX2_NVM_ACCESS_ENABLE); 4205 /* Disable both bits, even after read. */ 4206 BNX2_WR(bp, BNX2_NVM_ACCESS_ENABLE, 4207 val & ~(BNX2_NVM_ACCESS_ENABLE_EN | 4208 BNX2_NVM_ACCESS_ENABLE_WR_EN)); 4209 } 4210 4211 static int 4212 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset) 4213 { 4214 u32 cmd; 4215 int j; 4216 4217 if (bp->flash_info->flags & BNX2_NV_BUFFERED) 4218 /* Buffered flash, no erase needed */ 4219 return 0; 4220 4221 /* Build an erase command */ 4222 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR | 4223 BNX2_NVM_COMMAND_DOIT; 4224 4225 /* Need to clear DONE bit separately. */ 4226 BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE); 4227 4228 /* Address of the NVRAM to read from. */ 4229 BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE); 4230 4231 /* Issue an erase command. */ 4232 BNX2_WR(bp, BNX2_NVM_COMMAND, cmd); 4233 4234 /* Wait for completion. */ 4235 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 4236 u32 val; 4237 4238 udelay(5); 4239 4240 val = BNX2_RD(bp, BNX2_NVM_COMMAND); 4241 if (val & BNX2_NVM_COMMAND_DONE) 4242 break; 4243 } 4244 4245 if (j >= NVRAM_TIMEOUT_COUNT) 4246 return -EBUSY; 4247 4248 return 0; 4249 } 4250 4251 static int 4252 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags) 4253 { 4254 u32 cmd; 4255 int j; 4256 4257 /* Build the command word. */ 4258 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags; 4259 4260 /* Calculate an offset of a buffered flash, not needed for 5709. */ 4261 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) { 4262 offset = ((offset / bp->flash_info->page_size) << 4263 bp->flash_info->page_bits) + 4264 (offset % bp->flash_info->page_size); 4265 } 4266 4267 /* Need to clear DONE bit separately. */ 4268 BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE); 4269 4270 /* Address of the NVRAM to read from. */ 4271 BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE); 4272 4273 /* Issue a read command. */ 4274 BNX2_WR(bp, BNX2_NVM_COMMAND, cmd); 4275 4276 /* Wait for completion. */ 4277 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 4278 u32 val; 4279 4280 udelay(5); 4281 4282 val = BNX2_RD(bp, BNX2_NVM_COMMAND); 4283 if (val & BNX2_NVM_COMMAND_DONE) { 4284 __be32 v = cpu_to_be32(BNX2_RD(bp, BNX2_NVM_READ)); 4285 memcpy(ret_val, &v, 4); 4286 break; 4287 } 4288 } 4289 if (j >= NVRAM_TIMEOUT_COUNT) 4290 return -EBUSY; 4291 4292 return 0; 4293 } 4294 4295 4296 static int 4297 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags) 4298 { 4299 u32 cmd; 4300 __be32 val32; 4301 int j; 4302 4303 /* Build the command word. */ 4304 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags; 4305 4306 /* Calculate an offset of a buffered flash, not needed for 5709. */ 4307 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) { 4308 offset = ((offset / bp->flash_info->page_size) << 4309 bp->flash_info->page_bits) + 4310 (offset % bp->flash_info->page_size); 4311 } 4312 4313 /* Need to clear DONE bit separately. */ 4314 BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE); 4315 4316 memcpy(&val32, val, 4); 4317 4318 /* Write the data. */ 4319 BNX2_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32)); 4320 4321 /* Address of the NVRAM to write to. */ 4322 BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE); 4323 4324 /* Issue the write command. */ 4325 BNX2_WR(bp, BNX2_NVM_COMMAND, cmd); 4326 4327 /* Wait for completion. */ 4328 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 4329 udelay(5); 4330 4331 if (BNX2_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE) 4332 break; 4333 } 4334 if (j >= NVRAM_TIMEOUT_COUNT) 4335 return -EBUSY; 4336 4337 return 0; 4338 } 4339 4340 static int 4341 bnx2_init_nvram(struct bnx2 *bp) 4342 { 4343 u32 val; 4344 int j, entry_count, rc = 0; 4345 const struct flash_spec *flash; 4346 4347 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { 4348 bp->flash_info = &flash_5709; 4349 goto get_flash_size; 4350 } 4351 4352 /* Determine the selected interface. */ 4353 val = BNX2_RD(bp, BNX2_NVM_CFG1); 4354 4355 entry_count = ARRAY_SIZE(flash_table); 4356 4357 if (val & 0x40000000) { 4358 4359 /* Flash interface has been reconfigured */ 4360 for (j = 0, flash = &flash_table[0]; j < entry_count; 4361 j++, flash++) { 4362 if ((val & FLASH_BACKUP_STRAP_MASK) == 4363 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { 4364 bp->flash_info = flash; 4365 break; 4366 } 4367 } 4368 } 4369 else { 4370 u32 mask; 4371 /* Not yet been reconfigured */ 4372 4373 if (val & (1 << 23)) 4374 mask = FLASH_BACKUP_STRAP_MASK; 4375 else 4376 mask = FLASH_STRAP_MASK; 4377 4378 for (j = 0, flash = &flash_table[0]; j < entry_count; 4379 j++, flash++) { 4380 4381 if ((val & mask) == (flash->strapping & mask)) { 4382 bp->flash_info = flash; 4383 4384 /* Request access to the flash interface. */ 4385 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0) 4386 return rc; 4387 4388 /* Enable access to flash interface */ 4389 bnx2_enable_nvram_access(bp); 4390 4391 /* Reconfigure the flash interface */ 4392 BNX2_WR(bp, BNX2_NVM_CFG1, flash->config1); 4393 BNX2_WR(bp, BNX2_NVM_CFG2, flash->config2); 4394 BNX2_WR(bp, BNX2_NVM_CFG3, flash->config3); 4395 BNX2_WR(bp, BNX2_NVM_WRITE1, flash->write1); 4396 4397 /* Disable access to flash interface */ 4398 bnx2_disable_nvram_access(bp); 4399 bnx2_release_nvram_lock(bp); 4400 4401 break; 4402 } 4403 } 4404 } /* if (val & 0x40000000) */ 4405 4406 if (j == entry_count) { 4407 bp->flash_info = NULL; 4408 pr_alert("Unknown flash/EEPROM type\n"); 4409 return -ENODEV; 4410 } 4411 4412 get_flash_size: 4413 val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2); 4414 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK; 4415 if (val) 4416 bp->flash_size = val; 4417 else 4418 bp->flash_size = bp->flash_info->total_size; 4419 4420 return rc; 4421 } 4422 4423 static int 4424 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf, 4425 int buf_size) 4426 { 4427 int rc = 0; 4428 u32 cmd_flags, offset32, len32, extra; 4429 4430 if (buf_size == 0) 4431 return 0; 4432 4433 /* Request access to the flash interface. */ 4434 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0) 4435 return rc; 4436 4437 /* Enable access to flash interface */ 4438 bnx2_enable_nvram_access(bp); 4439 4440 len32 = buf_size; 4441 offset32 = offset; 4442 extra = 0; 4443 4444 cmd_flags = 0; 4445 4446 if (offset32 & 3) { 4447 u8 buf[4]; 4448 u32 pre_len; 4449 4450 offset32 &= ~3; 4451 pre_len = 4 - (offset & 3); 4452 4453 if (pre_len >= len32) { 4454 pre_len = len32; 4455 cmd_flags = BNX2_NVM_COMMAND_FIRST | 4456 BNX2_NVM_COMMAND_LAST; 4457 } 4458 else { 4459 cmd_flags = BNX2_NVM_COMMAND_FIRST; 4460 } 4461 4462 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags); 4463 4464 if (rc) 4465 return rc; 4466 4467 memcpy(ret_buf, buf + (offset & 3), pre_len); 4468 4469 offset32 += 4; 4470 ret_buf += pre_len; 4471 len32 -= pre_len; 4472 } 4473 if (len32 & 3) { 4474 extra = 4 - (len32 & 3); 4475 len32 = (len32 + 4) & ~3; 4476 } 4477 4478 if (len32 == 4) { 4479 u8 buf[4]; 4480 4481 if (cmd_flags) 4482 cmd_flags = BNX2_NVM_COMMAND_LAST; 4483 else 4484 cmd_flags = BNX2_NVM_COMMAND_FIRST | 4485 BNX2_NVM_COMMAND_LAST; 4486 4487 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags); 4488 4489 memcpy(ret_buf, buf, 4 - extra); 4490 } 4491 else if (len32 > 0) { 4492 u8 buf[4]; 4493 4494 /* Read the first word. */ 4495 if (cmd_flags) 4496 cmd_flags = 0; 4497 else 4498 cmd_flags = BNX2_NVM_COMMAND_FIRST; 4499 4500 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags); 4501 4502 /* Advance to the next dword. */ 4503 offset32 += 4; 4504 ret_buf += 4; 4505 len32 -= 4; 4506 4507 while (len32 > 4 && rc == 0) { 4508 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0); 4509 4510 /* Advance to the next dword. */ 4511 offset32 += 4; 4512 ret_buf += 4; 4513 len32 -= 4; 4514 } 4515 4516 if (rc) 4517 return rc; 4518 4519 cmd_flags = BNX2_NVM_COMMAND_LAST; 4520 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags); 4521 4522 memcpy(ret_buf, buf, 4 - extra); 4523 } 4524 4525 /* Disable access to flash interface */ 4526 bnx2_disable_nvram_access(bp); 4527 4528 bnx2_release_nvram_lock(bp); 4529 4530 return rc; 4531 } 4532 4533 static int 4534 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf, 4535 int buf_size) 4536 { 4537 u32 written, offset32, len32; 4538 u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL; 4539 int rc = 0; 4540 int align_start, align_end; 4541 4542 buf = data_buf; 4543 offset32 = offset; 4544 len32 = buf_size; 4545 align_start = align_end = 0; 4546 4547 if ((align_start = (offset32 & 3))) { 4548 offset32 &= ~3; 4549 len32 += align_start; 4550 if (len32 < 4) 4551 len32 = 4; 4552 if ((rc = bnx2_nvram_read(bp, offset32, start, 4))) 4553 return rc; 4554 } 4555 4556 if (len32 & 3) { 4557 align_end = 4 - (len32 & 3); 4558 len32 += align_end; 4559 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4))) 4560 return rc; 4561 } 4562 4563 if (align_start || align_end) { 4564 align_buf = kmalloc(len32, GFP_KERNEL); 4565 if (align_buf == NULL) 4566 return -ENOMEM; 4567 if (align_start) { 4568 memcpy(align_buf, start, 4); 4569 } 4570 if (align_end) { 4571 memcpy(align_buf + len32 - 4, end, 4); 4572 } 4573 memcpy(align_buf + align_start, data_buf, buf_size); 4574 buf = align_buf; 4575 } 4576 4577 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) { 4578 flash_buffer = kmalloc(264, GFP_KERNEL); 4579 if (flash_buffer == NULL) { 4580 rc = -ENOMEM; 4581 goto nvram_write_end; 4582 } 4583 } 4584 4585 written = 0; 4586 while ((written < len32) && (rc == 0)) { 4587 u32 page_start, page_end, data_start, data_end; 4588 u32 addr, cmd_flags; 4589 int i; 4590 4591 /* Find the page_start addr */ 4592 page_start = offset32 + written; 4593 page_start -= (page_start % bp->flash_info->page_size); 4594 /* Find the page_end addr */ 4595 page_end = page_start + bp->flash_info->page_size; 4596 /* Find the data_start addr */ 4597 data_start = (written == 0) ? offset32 : page_start; 4598 /* Find the data_end addr */ 4599 data_end = (page_end > offset32 + len32) ? 4600 (offset32 + len32) : page_end; 4601 4602 /* Request access to the flash interface. */ 4603 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0) 4604 goto nvram_write_end; 4605 4606 /* Enable access to flash interface */ 4607 bnx2_enable_nvram_access(bp); 4608 4609 cmd_flags = BNX2_NVM_COMMAND_FIRST; 4610 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) { 4611 int j; 4612 4613 /* Read the whole page into the buffer 4614 * (non-buffer flash only) */ 4615 for (j = 0; j < bp->flash_info->page_size; j += 4) { 4616 if (j == (bp->flash_info->page_size - 4)) { 4617 cmd_flags |= BNX2_NVM_COMMAND_LAST; 4618 } 4619 rc = bnx2_nvram_read_dword(bp, 4620 page_start + j, 4621 &flash_buffer[j], 4622 cmd_flags); 4623 4624 if (rc) 4625 goto nvram_write_end; 4626 4627 cmd_flags = 0; 4628 } 4629 } 4630 4631 /* Enable writes to flash interface (unlock write-protect) */ 4632 if ((rc = bnx2_enable_nvram_write(bp)) != 0) 4633 goto nvram_write_end; 4634 4635 /* Loop to write back the buffer data from page_start to 4636 * data_start */ 4637 i = 0; 4638 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) { 4639 /* Erase the page */ 4640 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0) 4641 goto nvram_write_end; 4642 4643 /* Re-enable the write again for the actual write */ 4644 bnx2_enable_nvram_write(bp); 4645 4646 for (addr = page_start; addr < data_start; 4647 addr += 4, i += 4) { 4648 4649 rc = bnx2_nvram_write_dword(bp, addr, 4650 &flash_buffer[i], cmd_flags); 4651 4652 if (rc != 0) 4653 goto nvram_write_end; 4654 4655 cmd_flags = 0; 4656 } 4657 } 4658 4659 /* Loop to write the new data from data_start to data_end */ 4660 for (addr = data_start; addr < data_end; addr += 4, i += 4) { 4661 if ((addr == page_end - 4) || 4662 ((bp->flash_info->flags & BNX2_NV_BUFFERED) && 4663 (addr == data_end - 4))) { 4664 4665 cmd_flags |= BNX2_NVM_COMMAND_LAST; 4666 } 4667 rc = bnx2_nvram_write_dword(bp, addr, buf, 4668 cmd_flags); 4669 4670 if (rc != 0) 4671 goto nvram_write_end; 4672 4673 cmd_flags = 0; 4674 buf += 4; 4675 } 4676 4677 /* Loop to write back the buffer data from data_end 4678 * to page_end */ 4679 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) { 4680 for (addr = data_end; addr < page_end; 4681 addr += 4, i += 4) { 4682 4683 if (addr == page_end-4) { 4684 cmd_flags = BNX2_NVM_COMMAND_LAST; 4685 } 4686 rc = bnx2_nvram_write_dword(bp, addr, 4687 &flash_buffer[i], cmd_flags); 4688 4689 if (rc != 0) 4690 goto nvram_write_end; 4691 4692 cmd_flags = 0; 4693 } 4694 } 4695 4696 /* Disable writes to flash interface (lock write-protect) */ 4697 bnx2_disable_nvram_write(bp); 4698 4699 /* Disable access to flash interface */ 4700 bnx2_disable_nvram_access(bp); 4701 bnx2_release_nvram_lock(bp); 4702 4703 /* Increment written */ 4704 written += data_end - data_start; 4705 } 4706 4707 nvram_write_end: 4708 kfree(flash_buffer); 4709 kfree(align_buf); 4710 return rc; 4711 } 4712 4713 static void 4714 bnx2_init_fw_cap(struct bnx2 *bp) 4715 { 4716 u32 val, sig = 0; 4717 4718 bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP; 4719 bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN; 4720 4721 if (!(bp->flags & BNX2_FLAG_ASF_ENABLE)) 4722 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN; 4723 4724 val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB); 4725 if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE) 4726 return; 4727 4728 if ((val & BNX2_FW_CAP_CAN_KEEP_VLAN) == BNX2_FW_CAP_CAN_KEEP_VLAN) { 4729 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN; 4730 sig |= BNX2_DRV_ACK_CAP_SIGNATURE | BNX2_FW_CAP_CAN_KEEP_VLAN; 4731 } 4732 4733 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && 4734 (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE)) { 4735 u32 link; 4736 4737 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP; 4738 4739 link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS); 4740 if (link & BNX2_LINK_STATUS_SERDES_LINK) 4741 bp->phy_port = PORT_FIBRE; 4742 else 4743 bp->phy_port = PORT_TP; 4744 4745 sig |= BNX2_DRV_ACK_CAP_SIGNATURE | 4746 BNX2_FW_CAP_REMOTE_PHY_CAPABLE; 4747 } 4748 4749 if (netif_running(bp->dev) && sig) 4750 bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig); 4751 } 4752 4753 static void 4754 bnx2_setup_msix_tbl(struct bnx2 *bp) 4755 { 4756 BNX2_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN); 4757 4758 BNX2_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR); 4759 BNX2_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR); 4760 } 4761 4762 static int 4763 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code) 4764 { 4765 u32 val; 4766 int i, rc = 0; 4767 u8 old_port; 4768 4769 /* Wait for the current PCI transaction to complete before 4770 * issuing a reset. */ 4771 if ((BNX2_CHIP(bp) == BNX2_CHIP_5706) || 4772 (BNX2_CHIP(bp) == BNX2_CHIP_5708)) { 4773 BNX2_WR(bp, BNX2_MISC_ENABLE_CLR_BITS, 4774 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | 4775 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | 4776 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | 4777 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); 4778 val = BNX2_RD(bp, BNX2_MISC_ENABLE_CLR_BITS); 4779 udelay(5); 4780 } else { /* 5709 */ 4781 val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL); 4782 val &= ~BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE; 4783 BNX2_WR(bp, BNX2_MISC_NEW_CORE_CTL, val); 4784 val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL); 4785 4786 for (i = 0; i < 100; i++) { 4787 msleep(1); 4788 val = BNX2_RD(bp, BNX2_PCICFG_DEVICE_CONTROL); 4789 if (!(val & BNX2_PCICFG_DEVICE_STATUS_NO_PEND)) 4790 break; 4791 } 4792 } 4793 4794 /* Wait for the firmware to tell us it is ok to issue a reset. */ 4795 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1); 4796 4797 /* Deposit a driver reset signature so the firmware knows that 4798 * this is a soft reset. */ 4799 bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE, 4800 BNX2_DRV_RESET_SIGNATURE_MAGIC); 4801 4802 /* Do a dummy read to force the chip to complete all current transaction 4803 * before we issue a reset. */ 4804 val = BNX2_RD(bp, BNX2_MISC_ID); 4805 4806 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { 4807 BNX2_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET); 4808 BNX2_RD(bp, BNX2_MISC_COMMAND); 4809 udelay(5); 4810 4811 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 4812 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 4813 4814 BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG, val); 4815 4816 } else { 4817 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ | 4818 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 4819 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 4820 4821 /* Chip reset. */ 4822 BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG, val); 4823 4824 /* Reading back any register after chip reset will hang the 4825 * bus on 5706 A0 and A1. The msleep below provides plenty 4826 * of margin for write posting. 4827 */ 4828 if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) || 4829 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1)) 4830 msleep(20); 4831 4832 /* Reset takes approximate 30 usec */ 4833 for (i = 0; i < 10; i++) { 4834 val = BNX2_RD(bp, BNX2_PCICFG_MISC_CONFIG); 4835 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ | 4836 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) 4837 break; 4838 udelay(10); 4839 } 4840 4841 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ | 4842 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { 4843 pr_err("Chip reset did not complete\n"); 4844 return -EBUSY; 4845 } 4846 } 4847 4848 /* Make sure byte swapping is properly configured. */ 4849 val = BNX2_RD(bp, BNX2_PCI_SWAP_DIAG0); 4850 if (val != 0x01020304) { 4851 pr_err("Chip not in correct endian mode\n"); 4852 return -ENODEV; 4853 } 4854 4855 /* Wait for the firmware to finish its initialization. */ 4856 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0); 4857 if (rc) 4858 return rc; 4859 4860 spin_lock_bh(&bp->phy_lock); 4861 old_port = bp->phy_port; 4862 bnx2_init_fw_cap(bp); 4863 if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) && 4864 old_port != bp->phy_port) 4865 bnx2_set_default_remote_link(bp); 4866 spin_unlock_bh(&bp->phy_lock); 4867 4868 if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) { 4869 /* Adjust the voltage regular to two steps lower. The default 4870 * of this register is 0x0000000e. */ 4871 BNX2_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa); 4872 4873 /* Remove bad rbuf memory from the free pool. */ 4874 rc = bnx2_alloc_bad_rbuf(bp); 4875 } 4876 4877 if (bp->flags & BNX2_FLAG_USING_MSIX) { 4878 bnx2_setup_msix_tbl(bp); 4879 /* Prevent MSIX table reads and write from timing out */ 4880 BNX2_WR(bp, BNX2_MISC_ECO_HW_CTL, 4881 BNX2_MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN); 4882 } 4883 4884 return rc; 4885 } 4886 4887 static int 4888 bnx2_init_chip(struct bnx2 *bp) 4889 { 4890 u32 val, mtu; 4891 int rc, i; 4892 4893 /* Make sure the interrupt is not active. */ 4894 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT); 4895 4896 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP | 4897 BNX2_DMA_CONFIG_DATA_WORD_SWAP | 4898 #ifdef __BIG_ENDIAN 4899 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP | 4900 #endif 4901 BNX2_DMA_CONFIG_CNTL_WORD_SWAP | 4902 DMA_READ_CHANS << 12 | 4903 DMA_WRITE_CHANS << 16; 4904 4905 val |= (0x2 << 20) | (1 << 11); 4906 4907 if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133)) 4908 val |= (1 << 23); 4909 4910 if ((BNX2_CHIP(bp) == BNX2_CHIP_5706) && 4911 (BNX2_CHIP_ID(bp) != BNX2_CHIP_ID_5706_A0) && 4912 !(bp->flags & BNX2_FLAG_PCIX)) 4913 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA; 4914 4915 BNX2_WR(bp, BNX2_DMA_CONFIG, val); 4916 4917 if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) { 4918 val = BNX2_RD(bp, BNX2_TDMA_CONFIG); 4919 val |= BNX2_TDMA_CONFIG_ONE_DMA; 4920 BNX2_WR(bp, BNX2_TDMA_CONFIG, val); 4921 } 4922 4923 if (bp->flags & BNX2_FLAG_PCIX) { 4924 u16 val16; 4925 4926 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD, 4927 &val16); 4928 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD, 4929 val16 & ~PCI_X_CMD_ERO); 4930 } 4931 4932 BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS, 4933 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | 4934 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | 4935 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); 4936 4937 /* Initialize context mapping and zero out the quick contexts. The 4938 * context block must have already been enabled. */ 4939 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { 4940 rc = bnx2_init_5709_context(bp); 4941 if (rc) 4942 return rc; 4943 } else 4944 bnx2_init_context(bp); 4945 4946 if ((rc = bnx2_init_cpus(bp)) != 0) 4947 return rc; 4948 4949 bnx2_init_nvram(bp); 4950 4951 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0); 4952 4953 val = BNX2_RD(bp, BNX2_MQ_CONFIG); 4954 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE; 4955 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; 4956 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { 4957 val |= BNX2_MQ_CONFIG_BIN_MQ_MODE; 4958 if (BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Ax) 4959 val |= BNX2_MQ_CONFIG_HALT_DIS; 4960 } 4961 4962 BNX2_WR(bp, BNX2_MQ_CONFIG, val); 4963 4964 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); 4965 BNX2_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val); 4966 BNX2_WR(bp, BNX2_MQ_KNL_WIND_END, val); 4967 4968 val = (BNX2_PAGE_BITS - 8) << 24; 4969 BNX2_WR(bp, BNX2_RV2P_CONFIG, val); 4970 4971 /* Configure page size. */ 4972 val = BNX2_RD(bp, BNX2_TBDR_CONFIG); 4973 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE; 4974 val |= (BNX2_PAGE_BITS - 8) << 24 | 0x40; 4975 BNX2_WR(bp, BNX2_TBDR_CONFIG, val); 4976 4977 val = bp->mac_addr[0] + 4978 (bp->mac_addr[1] << 8) + 4979 (bp->mac_addr[2] << 16) + 4980 bp->mac_addr[3] + 4981 (bp->mac_addr[4] << 8) + 4982 (bp->mac_addr[5] << 16); 4983 BNX2_WR(bp, BNX2_EMAC_BACKOFF_SEED, val); 4984 4985 /* Program the MTU. Also include 4 bytes for CRC32. */ 4986 mtu = bp->dev->mtu; 4987 val = mtu + ETH_HLEN + ETH_FCS_LEN; 4988 if (val > (MAX_ETHERNET_PACKET_SIZE + 4)) 4989 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA; 4990 BNX2_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val); 4991 4992 if (mtu < 1500) 4993 mtu = 1500; 4994 4995 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu)); 4996 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu)); 4997 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu)); 4998 4999 memset(bp->bnx2_napi[0].status_blk.msi, 0, bp->status_stats_size); 5000 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) 5001 bp->bnx2_napi[i].last_status_idx = 0; 5002 5003 bp->idle_chk_status_idx = 0xffff; 5004 5005 /* Set up how to generate a link change interrupt. */ 5006 BNX2_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK); 5007 5008 BNX2_WR(bp, BNX2_HC_STATUS_ADDR_L, 5009 (u64) bp->status_blk_mapping & 0xffffffff); 5010 BNX2_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32); 5011 5012 BNX2_WR(bp, BNX2_HC_STATISTICS_ADDR_L, 5013 (u64) bp->stats_blk_mapping & 0xffffffff); 5014 BNX2_WR(bp, BNX2_HC_STATISTICS_ADDR_H, 5015 (u64) bp->stats_blk_mapping >> 32); 5016 5017 BNX2_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP, 5018 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip); 5019 5020 BNX2_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP, 5021 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip); 5022 5023 BNX2_WR(bp, BNX2_HC_COMP_PROD_TRIP, 5024 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip); 5025 5026 BNX2_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks); 5027 5028 BNX2_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks); 5029 5030 BNX2_WR(bp, BNX2_HC_COM_TICKS, 5031 (bp->com_ticks_int << 16) | bp->com_ticks); 5032 5033 BNX2_WR(bp, BNX2_HC_CMD_TICKS, 5034 (bp->cmd_ticks_int << 16) | bp->cmd_ticks); 5035 5036 if (bp->flags & BNX2_FLAG_BROKEN_STATS) 5037 BNX2_WR(bp, BNX2_HC_STATS_TICKS, 0); 5038 else 5039 BNX2_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks); 5040 BNX2_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ 5041 5042 if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1) 5043 val = BNX2_HC_CONFIG_COLLECT_STATS; 5044 else { 5045 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE | 5046 BNX2_HC_CONFIG_COLLECT_STATS; 5047 } 5048 5049 if (bp->flags & BNX2_FLAG_USING_MSIX) { 5050 BNX2_WR(bp, BNX2_HC_MSIX_BIT_VECTOR, 5051 BNX2_HC_MSIX_BIT_VECTOR_VAL); 5052 5053 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B; 5054 } 5055 5056 if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI) 5057 val |= BNX2_HC_CONFIG_ONE_SHOT | BNX2_HC_CONFIG_USE_INT_PARAM; 5058 5059 BNX2_WR(bp, BNX2_HC_CONFIG, val); 5060 5061 if (bp->rx_ticks < 25) 5062 bnx2_reg_wr_ind(bp, BNX2_FW_RX_LOW_LATENCY, 1); 5063 else 5064 bnx2_reg_wr_ind(bp, BNX2_FW_RX_LOW_LATENCY, 0); 5065 5066 for (i = 1; i < bp->irq_nvecs; i++) { 5067 u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) + 5068 BNX2_HC_SB_CONFIG_1; 5069 5070 BNX2_WR(bp, base, 5071 BNX2_HC_SB_CONFIG_1_TX_TMR_MODE | 5072 BNX2_HC_SB_CONFIG_1_RX_TMR_MODE | 5073 BNX2_HC_SB_CONFIG_1_ONE_SHOT); 5074 5075 BNX2_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF, 5076 (bp->tx_quick_cons_trip_int << 16) | 5077 bp->tx_quick_cons_trip); 5078 5079 BNX2_WR(bp, base + BNX2_HC_TX_TICKS_OFF, 5080 (bp->tx_ticks_int << 16) | bp->tx_ticks); 5081 5082 BNX2_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF, 5083 (bp->rx_quick_cons_trip_int << 16) | 5084 bp->rx_quick_cons_trip); 5085 5086 BNX2_WR(bp, base + BNX2_HC_RX_TICKS_OFF, 5087 (bp->rx_ticks_int << 16) | bp->rx_ticks); 5088 } 5089 5090 /* Clear internal stats counters. */ 5091 BNX2_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW); 5092 5093 BNX2_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS); 5094 5095 /* Initialize the receive filter. */ 5096 bnx2_set_rx_mode(bp->dev); 5097 5098 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { 5099 val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL); 5100 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE; 5101 BNX2_WR(bp, BNX2_MISC_NEW_CORE_CTL, val); 5102 } 5103 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET, 5104 1, 0); 5105 5106 BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT); 5107 BNX2_RD(bp, BNX2_MISC_ENABLE_SET_BITS); 5108 5109 udelay(20); 5110 5111 bp->hc_cmd = BNX2_RD(bp, BNX2_HC_COMMAND); 5112 5113 return rc; 5114 } 5115 5116 static void 5117 bnx2_clear_ring_states(struct bnx2 *bp) 5118 { 5119 struct bnx2_napi *bnapi; 5120 struct bnx2_tx_ring_info *txr; 5121 struct bnx2_rx_ring_info *rxr; 5122 int i; 5123 5124 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) { 5125 bnapi = &bp->bnx2_napi[i]; 5126 txr = &bnapi->tx_ring; 5127 rxr = &bnapi->rx_ring; 5128 5129 txr->tx_cons = 0; 5130 txr->hw_tx_cons = 0; 5131 rxr->rx_prod_bseq = 0; 5132 rxr->rx_prod = 0; 5133 rxr->rx_cons = 0; 5134 rxr->rx_pg_prod = 0; 5135 rxr->rx_pg_cons = 0; 5136 } 5137 } 5138 5139 static void 5140 bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr) 5141 { 5142 u32 val, offset0, offset1, offset2, offset3; 5143 u32 cid_addr = GET_CID_ADDR(cid); 5144 5145 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { 5146 offset0 = BNX2_L2CTX_TYPE_XI; 5147 offset1 = BNX2_L2CTX_CMD_TYPE_XI; 5148 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI; 5149 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI; 5150 } else { 5151 offset0 = BNX2_L2CTX_TYPE; 5152 offset1 = BNX2_L2CTX_CMD_TYPE; 5153 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI; 5154 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO; 5155 } 5156 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2; 5157 bnx2_ctx_wr(bp, cid_addr, offset0, val); 5158 5159 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); 5160 bnx2_ctx_wr(bp, cid_addr, offset1, val); 5161 5162 val = (u64) txr->tx_desc_mapping >> 32; 5163 bnx2_ctx_wr(bp, cid_addr, offset2, val); 5164 5165 val = (u64) txr->tx_desc_mapping & 0xffffffff; 5166 bnx2_ctx_wr(bp, cid_addr, offset3, val); 5167 } 5168 5169 static void 5170 bnx2_init_tx_ring(struct bnx2 *bp, int ring_num) 5171 { 5172 struct bnx2_tx_bd *txbd; 5173 u32 cid = TX_CID; 5174 struct bnx2_napi *bnapi; 5175 struct bnx2_tx_ring_info *txr; 5176 5177 bnapi = &bp->bnx2_napi[ring_num]; 5178 txr = &bnapi->tx_ring; 5179 5180 if (ring_num == 0) 5181 cid = TX_CID; 5182 else 5183 cid = TX_TSS_CID + ring_num - 1; 5184 5185 bp->tx_wake_thresh = bp->tx_ring_size / 2; 5186 5187 txbd = &txr->tx_desc_ring[BNX2_MAX_TX_DESC_CNT]; 5188 5189 txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32; 5190 txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff; 5191 5192 txr->tx_prod = 0; 5193 txr->tx_prod_bseq = 0; 5194 5195 txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX; 5196 txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ; 5197 5198 bnx2_init_tx_context(bp, cid, txr); 5199 } 5200 5201 static void 5202 bnx2_init_rxbd_rings(struct bnx2_rx_bd *rx_ring[], dma_addr_t dma[], 5203 u32 buf_size, int num_rings) 5204 { 5205 int i; 5206 struct bnx2_rx_bd *rxbd; 5207 5208 for (i = 0; i < num_rings; i++) { 5209 int j; 5210 5211 rxbd = &rx_ring[i][0]; 5212 for (j = 0; j < BNX2_MAX_RX_DESC_CNT; j++, rxbd++) { 5213 rxbd->rx_bd_len = buf_size; 5214 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END; 5215 } 5216 if (i == (num_rings - 1)) 5217 j = 0; 5218 else 5219 j = i + 1; 5220 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32; 5221 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff; 5222 } 5223 } 5224 5225 static void 5226 bnx2_init_rx_ring(struct bnx2 *bp, int ring_num) 5227 { 5228 int i; 5229 u16 prod, ring_prod; 5230 u32 cid, rx_cid_addr, val; 5231 struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num]; 5232 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; 5233 5234 if (ring_num == 0) 5235 cid = RX_CID; 5236 else 5237 cid = RX_RSS_CID + ring_num - 1; 5238 5239 rx_cid_addr = GET_CID_ADDR(cid); 5240 5241 bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping, 5242 bp->rx_buf_use_size, bp->rx_max_ring); 5243 5244 bnx2_init_rx_context(bp, cid); 5245 5246 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { 5247 val = BNX2_RD(bp, BNX2_MQ_MAP_L2_5); 5248 BNX2_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM); 5249 } 5250 5251 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0); 5252 if (bp->rx_pg_ring_size) { 5253 bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring, 5254 rxr->rx_pg_desc_mapping, 5255 PAGE_SIZE, bp->rx_max_pg_ring); 5256 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE; 5257 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val); 5258 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY, 5259 BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num); 5260 5261 val = (u64) rxr->rx_pg_desc_mapping[0] >> 32; 5262 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val); 5263 5264 val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff; 5265 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val); 5266 5267 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) 5268 BNX2_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT); 5269 } 5270 5271 val = (u64) rxr->rx_desc_mapping[0] >> 32; 5272 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val); 5273 5274 val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff; 5275 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val); 5276 5277 ring_prod = prod = rxr->rx_pg_prod; 5278 for (i = 0; i < bp->rx_pg_ring_size; i++) { 5279 if (bnx2_alloc_rx_page(bp, rxr, ring_prod, GFP_KERNEL) < 0) { 5280 netdev_warn(bp->dev, "init'ed rx page ring %d with %d/%d pages only\n", 5281 ring_num, i, bp->rx_pg_ring_size); 5282 break; 5283 } 5284 prod = BNX2_NEXT_RX_BD(prod); 5285 ring_prod = BNX2_RX_PG_RING_IDX(prod); 5286 } 5287 rxr->rx_pg_prod = prod; 5288 5289 ring_prod = prod = rxr->rx_prod; 5290 for (i = 0; i < bp->rx_ring_size; i++) { 5291 if (bnx2_alloc_rx_data(bp, rxr, ring_prod, GFP_KERNEL) < 0) { 5292 netdev_warn(bp->dev, "init'ed rx ring %d with %d/%d skbs only\n", 5293 ring_num, i, bp->rx_ring_size); 5294 break; 5295 } 5296 prod = BNX2_NEXT_RX_BD(prod); 5297 ring_prod = BNX2_RX_RING_IDX(prod); 5298 } 5299 rxr->rx_prod = prod; 5300 5301 rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX; 5302 rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ; 5303 rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX; 5304 5305 BNX2_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod); 5306 BNX2_WR16(bp, rxr->rx_bidx_addr, prod); 5307 5308 BNX2_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq); 5309 } 5310 5311 static void 5312 bnx2_init_all_rings(struct bnx2 *bp) 5313 { 5314 int i; 5315 u32 val; 5316 5317 bnx2_clear_ring_states(bp); 5318 5319 BNX2_WR(bp, BNX2_TSCH_TSS_CFG, 0); 5320 for (i = 0; i < bp->num_tx_rings; i++) 5321 bnx2_init_tx_ring(bp, i); 5322 5323 if (bp->num_tx_rings > 1) 5324 BNX2_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) | 5325 (TX_TSS_CID << 7)); 5326 5327 BNX2_WR(bp, BNX2_RLUP_RSS_CONFIG, 0); 5328 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0); 5329 5330 for (i = 0; i < bp->num_rx_rings; i++) 5331 bnx2_init_rx_ring(bp, i); 5332 5333 if (bp->num_rx_rings > 1) { 5334 u32 tbl_32 = 0; 5335 5336 for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) { 5337 int shift = (i % 8) << 2; 5338 5339 tbl_32 |= (i % (bp->num_rx_rings - 1)) << shift; 5340 if ((i % 8) == 7) { 5341 BNX2_WR(bp, BNX2_RLUP_RSS_DATA, tbl_32); 5342 BNX2_WR(bp, BNX2_RLUP_RSS_COMMAND, (i >> 3) | 5343 BNX2_RLUP_RSS_COMMAND_RSS_WRITE_MASK | 5344 BNX2_RLUP_RSS_COMMAND_WRITE | 5345 BNX2_RLUP_RSS_COMMAND_HASH_MASK); 5346 tbl_32 = 0; 5347 } 5348 } 5349 5350 val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI | 5351 BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI; 5352 5353 BNX2_WR(bp, BNX2_RLUP_RSS_CONFIG, val); 5354 5355 } 5356 } 5357 5358 static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size) 5359 { 5360 u32 max, num_rings = 1; 5361 5362 while (ring_size > BNX2_MAX_RX_DESC_CNT) { 5363 ring_size -= BNX2_MAX_RX_DESC_CNT; 5364 num_rings++; 5365 } 5366 /* round to next power of 2 */ 5367 max = max_size; 5368 while ((max & num_rings) == 0) 5369 max >>= 1; 5370 5371 if (num_rings != max) 5372 max <<= 1; 5373 5374 return max; 5375 } 5376 5377 static void 5378 bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size) 5379 { 5380 u32 rx_size, rx_space, jumbo_size; 5381 5382 /* 8 for CRC and VLAN */ 5383 rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8; 5384 5385 rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD + 5386 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 5387 5388 bp->rx_copy_thresh = BNX2_RX_COPY_THRESH; 5389 bp->rx_pg_ring_size = 0; 5390 bp->rx_max_pg_ring = 0; 5391 bp->rx_max_pg_ring_idx = 0; 5392 if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) { 5393 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT; 5394 5395 jumbo_size = size * pages; 5396 if (jumbo_size > BNX2_MAX_TOTAL_RX_PG_DESC_CNT) 5397 jumbo_size = BNX2_MAX_TOTAL_RX_PG_DESC_CNT; 5398 5399 bp->rx_pg_ring_size = jumbo_size; 5400 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size, 5401 BNX2_MAX_RX_PG_RINGS); 5402 bp->rx_max_pg_ring_idx = 5403 (bp->rx_max_pg_ring * BNX2_RX_DESC_CNT) - 1; 5404 rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET; 5405 bp->rx_copy_thresh = 0; 5406 } 5407 5408 bp->rx_buf_use_size = rx_size; 5409 /* hw alignment + build_skb() overhead*/ 5410 bp->rx_buf_size = SKB_DATA_ALIGN(bp->rx_buf_use_size + BNX2_RX_ALIGN) + 5411 NET_SKB_PAD + SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 5412 bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET; 5413 bp->rx_ring_size = size; 5414 bp->rx_max_ring = bnx2_find_max_ring(size, BNX2_MAX_RX_RINGS); 5415 bp->rx_max_ring_idx = (bp->rx_max_ring * BNX2_RX_DESC_CNT) - 1; 5416 } 5417 5418 static void 5419 bnx2_free_tx_skbs(struct bnx2 *bp) 5420 { 5421 int i; 5422 5423 for (i = 0; i < bp->num_tx_rings; i++) { 5424 struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; 5425 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; 5426 int j; 5427 5428 if (txr->tx_buf_ring == NULL) 5429 continue; 5430 5431 for (j = 0; j < BNX2_TX_DESC_CNT; ) { 5432 struct bnx2_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j]; 5433 struct sk_buff *skb = tx_buf->skb; 5434 int k, last; 5435 5436 if (skb == NULL) { 5437 j = BNX2_NEXT_TX_BD(j); 5438 continue; 5439 } 5440 5441 dma_unmap_single(&bp->pdev->dev, 5442 dma_unmap_addr(tx_buf, mapping), 5443 skb_headlen(skb), 5444 PCI_DMA_TODEVICE); 5445 5446 tx_buf->skb = NULL; 5447 5448 last = tx_buf->nr_frags; 5449 j = BNX2_NEXT_TX_BD(j); 5450 for (k = 0; k < last; k++, j = BNX2_NEXT_TX_BD(j)) { 5451 tx_buf = &txr->tx_buf_ring[BNX2_TX_RING_IDX(j)]; 5452 dma_unmap_page(&bp->pdev->dev, 5453 dma_unmap_addr(tx_buf, mapping), 5454 skb_frag_size(&skb_shinfo(skb)->frags[k]), 5455 PCI_DMA_TODEVICE); 5456 } 5457 dev_kfree_skb(skb); 5458 } 5459 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i)); 5460 } 5461 } 5462 5463 static void 5464 bnx2_free_rx_skbs(struct bnx2 *bp) 5465 { 5466 int i; 5467 5468 for (i = 0; i < bp->num_rx_rings; i++) { 5469 struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; 5470 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; 5471 int j; 5472 5473 if (rxr->rx_buf_ring == NULL) 5474 return; 5475 5476 for (j = 0; j < bp->rx_max_ring_idx; j++) { 5477 struct bnx2_sw_bd *rx_buf = &rxr->rx_buf_ring[j]; 5478 u8 *data = rx_buf->data; 5479 5480 if (data == NULL) 5481 continue; 5482 5483 dma_unmap_single(&bp->pdev->dev, 5484 dma_unmap_addr(rx_buf, mapping), 5485 bp->rx_buf_use_size, 5486 PCI_DMA_FROMDEVICE); 5487 5488 rx_buf->data = NULL; 5489 5490 kfree(data); 5491 } 5492 for (j = 0; j < bp->rx_max_pg_ring_idx; j++) 5493 bnx2_free_rx_page(bp, rxr, j); 5494 } 5495 } 5496 5497 static void 5498 bnx2_free_skbs(struct bnx2 *bp) 5499 { 5500 bnx2_free_tx_skbs(bp); 5501 bnx2_free_rx_skbs(bp); 5502 } 5503 5504 static int 5505 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code) 5506 { 5507 int rc; 5508 5509 rc = bnx2_reset_chip(bp, reset_code); 5510 bnx2_free_skbs(bp); 5511 if (rc) 5512 return rc; 5513 5514 if ((rc = bnx2_init_chip(bp)) != 0) 5515 return rc; 5516 5517 bnx2_init_all_rings(bp); 5518 return 0; 5519 } 5520 5521 static int 5522 bnx2_init_nic(struct bnx2 *bp, int reset_phy) 5523 { 5524 int rc; 5525 5526 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0) 5527 return rc; 5528 5529 spin_lock_bh(&bp->phy_lock); 5530 bnx2_init_phy(bp, reset_phy); 5531 bnx2_set_link(bp); 5532 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) 5533 bnx2_remote_phy_event(bp); 5534 spin_unlock_bh(&bp->phy_lock); 5535 return 0; 5536 } 5537 5538 static int 5539 bnx2_shutdown_chip(struct bnx2 *bp) 5540 { 5541 u32 reset_code; 5542 5543 if (bp->flags & BNX2_FLAG_NO_WOL) 5544 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN; 5545 else if (bp->wol) 5546 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL; 5547 else 5548 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL; 5549 5550 return bnx2_reset_chip(bp, reset_code); 5551 } 5552 5553 static int 5554 bnx2_test_registers(struct bnx2 *bp) 5555 { 5556 int ret; 5557 int i, is_5709; 5558 static const struct { 5559 u16 offset; 5560 u16 flags; 5561 #define BNX2_FL_NOT_5709 1 5562 u32 rw_mask; 5563 u32 ro_mask; 5564 } reg_tbl[] = { 5565 { 0x006c, 0, 0x00000000, 0x0000003f }, 5566 { 0x0090, 0, 0xffffffff, 0x00000000 }, 5567 { 0x0094, 0, 0x00000000, 0x00000000 }, 5568 5569 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 }, 5570 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, 5571 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, 5572 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff }, 5573 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 }, 5574 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 }, 5575 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff }, 5576 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, 5577 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, 5578 5579 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, 5580 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, 5581 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 }, 5582 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 }, 5583 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 }, 5584 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 }, 5585 5586 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 }, 5587 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 }, 5588 { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 }, 5589 5590 { 0x1000, 0, 0x00000000, 0x00000001 }, 5591 { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 }, 5592 5593 { 0x1408, 0, 0x01c00800, 0x00000000 }, 5594 { 0x149c, 0, 0x8000ffff, 0x00000000 }, 5595 { 0x14a8, 0, 0x00000000, 0x000001ff }, 5596 { 0x14ac, 0, 0x0fffffff, 0x10000000 }, 5597 { 0x14b0, 0, 0x00000002, 0x00000001 }, 5598 { 0x14b8, 0, 0x00000000, 0x00000000 }, 5599 { 0x14c0, 0, 0x00000000, 0x00000009 }, 5600 { 0x14c4, 0, 0x00003fff, 0x00000000 }, 5601 { 0x14cc, 0, 0x00000000, 0x00000001 }, 5602 { 0x14d0, 0, 0xffffffff, 0x00000000 }, 5603 5604 { 0x1800, 0, 0x00000000, 0x00000001 }, 5605 { 0x1804, 0, 0x00000000, 0x00000003 }, 5606 5607 { 0x2800, 0, 0x00000000, 0x00000001 }, 5608 { 0x2804, 0, 0x00000000, 0x00003f01 }, 5609 { 0x2808, 0, 0x0f3f3f03, 0x00000000 }, 5610 { 0x2810, 0, 0xffff0000, 0x00000000 }, 5611 { 0x2814, 0, 0xffff0000, 0x00000000 }, 5612 { 0x2818, 0, 0xffff0000, 0x00000000 }, 5613 { 0x281c, 0, 0xffff0000, 0x00000000 }, 5614 { 0x2834, 0, 0xffffffff, 0x00000000 }, 5615 { 0x2840, 0, 0x00000000, 0xffffffff }, 5616 { 0x2844, 0, 0x00000000, 0xffffffff }, 5617 { 0x2848, 0, 0xffffffff, 0x00000000 }, 5618 { 0x284c, 0, 0xf800f800, 0x07ff07ff }, 5619 5620 { 0x2c00, 0, 0x00000000, 0x00000011 }, 5621 { 0x2c04, 0, 0x00000000, 0x00030007 }, 5622 5623 { 0x3c00, 0, 0x00000000, 0x00000001 }, 5624 { 0x3c04, 0, 0x00000000, 0x00070000 }, 5625 { 0x3c08, 0, 0x00007f71, 0x07f00000 }, 5626 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 }, 5627 { 0x3c10, 0, 0xffffffff, 0x00000000 }, 5628 { 0x3c14, 0, 0x00000000, 0xffffffff }, 5629 { 0x3c18, 0, 0x00000000, 0xffffffff }, 5630 { 0x3c1c, 0, 0xfffff000, 0x00000000 }, 5631 { 0x3c20, 0, 0xffffff00, 0x00000000 }, 5632 5633 { 0x5004, 0, 0x00000000, 0x0000007f }, 5634 { 0x5008, 0, 0x0f0007ff, 0x00000000 }, 5635 5636 { 0x5c00, 0, 0x00000000, 0x00000001 }, 5637 { 0x5c04, 0, 0x00000000, 0x0003000f }, 5638 { 0x5c08, 0, 0x00000003, 0x00000000 }, 5639 { 0x5c0c, 0, 0x0000fff8, 0x00000000 }, 5640 { 0x5c10, 0, 0x00000000, 0xffffffff }, 5641 { 0x5c80, 0, 0x00000000, 0x0f7113f1 }, 5642 { 0x5c84, 0, 0x00000000, 0x0000f333 }, 5643 { 0x5c88, 0, 0x00000000, 0x00077373 }, 5644 { 0x5c8c, 0, 0x00000000, 0x0007f737 }, 5645 5646 { 0x6808, 0, 0x0000ff7f, 0x00000000 }, 5647 { 0x680c, 0, 0xffffffff, 0x00000000 }, 5648 { 0x6810, 0, 0xffffffff, 0x00000000 }, 5649 { 0x6814, 0, 0xffffffff, 0x00000000 }, 5650 { 0x6818, 0, 0xffffffff, 0x00000000 }, 5651 { 0x681c, 0, 0xffffffff, 0x00000000 }, 5652 { 0x6820, 0, 0x00ff00ff, 0x00000000 }, 5653 { 0x6824, 0, 0x00ff00ff, 0x00000000 }, 5654 { 0x6828, 0, 0x00ff00ff, 0x00000000 }, 5655 { 0x682c, 0, 0x03ff03ff, 0x00000000 }, 5656 { 0x6830, 0, 0x03ff03ff, 0x00000000 }, 5657 { 0x6834, 0, 0x03ff03ff, 0x00000000 }, 5658 { 0x6838, 0, 0x03ff03ff, 0x00000000 }, 5659 { 0x683c, 0, 0x0000ffff, 0x00000000 }, 5660 { 0x6840, 0, 0x00000ff0, 0x00000000 }, 5661 { 0x6844, 0, 0x00ffff00, 0x00000000 }, 5662 { 0x684c, 0, 0xffffffff, 0x00000000 }, 5663 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 }, 5664 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 }, 5665 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 }, 5666 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 }, 5667 { 0x6908, 0, 0x00000000, 0x0001ff0f }, 5668 { 0x690c, 0, 0x00000000, 0x0ffe00f0 }, 5669 5670 { 0xffff, 0, 0x00000000, 0x00000000 }, 5671 }; 5672 5673 ret = 0; 5674 is_5709 = 0; 5675 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) 5676 is_5709 = 1; 5677 5678 for (i = 0; reg_tbl[i].offset != 0xffff; i++) { 5679 u32 offset, rw_mask, ro_mask, save_val, val; 5680 u16 flags = reg_tbl[i].flags; 5681 5682 if (is_5709 && (flags & BNX2_FL_NOT_5709)) 5683 continue; 5684 5685 offset = (u32) reg_tbl[i].offset; 5686 rw_mask = reg_tbl[i].rw_mask; 5687 ro_mask = reg_tbl[i].ro_mask; 5688 5689 save_val = readl(bp->regview + offset); 5690 5691 writel(0, bp->regview + offset); 5692 5693 val = readl(bp->regview + offset); 5694 if ((val & rw_mask) != 0) { 5695 goto reg_test_err; 5696 } 5697 5698 if ((val & ro_mask) != (save_val & ro_mask)) { 5699 goto reg_test_err; 5700 } 5701 5702 writel(0xffffffff, bp->regview + offset); 5703 5704 val = readl(bp->regview + offset); 5705 if ((val & rw_mask) != rw_mask) { 5706 goto reg_test_err; 5707 } 5708 5709 if ((val & ro_mask) != (save_val & ro_mask)) { 5710 goto reg_test_err; 5711 } 5712 5713 writel(save_val, bp->regview + offset); 5714 continue; 5715 5716 reg_test_err: 5717 writel(save_val, bp->regview + offset); 5718 ret = -ENODEV; 5719 break; 5720 } 5721 return ret; 5722 } 5723 5724 static int 5725 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size) 5726 { 5727 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555, 5728 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa }; 5729 int i; 5730 5731 for (i = 0; i < sizeof(test_pattern) / 4; i++) { 5732 u32 offset; 5733 5734 for (offset = 0; offset < size; offset += 4) { 5735 5736 bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]); 5737 5738 if (bnx2_reg_rd_ind(bp, start + offset) != 5739 test_pattern[i]) { 5740 return -ENODEV; 5741 } 5742 } 5743 } 5744 return 0; 5745 } 5746 5747 static int 5748 bnx2_test_memory(struct bnx2 *bp) 5749 { 5750 int ret = 0; 5751 int i; 5752 static struct mem_entry { 5753 u32 offset; 5754 u32 len; 5755 } mem_tbl_5706[] = { 5756 { 0x60000, 0x4000 }, 5757 { 0xa0000, 0x3000 }, 5758 { 0xe0000, 0x4000 }, 5759 { 0x120000, 0x4000 }, 5760 { 0x1a0000, 0x4000 }, 5761 { 0x160000, 0x4000 }, 5762 { 0xffffffff, 0 }, 5763 }, 5764 mem_tbl_5709[] = { 5765 { 0x60000, 0x4000 }, 5766 { 0xa0000, 0x3000 }, 5767 { 0xe0000, 0x4000 }, 5768 { 0x120000, 0x4000 }, 5769 { 0x1a0000, 0x4000 }, 5770 { 0xffffffff, 0 }, 5771 }; 5772 struct mem_entry *mem_tbl; 5773 5774 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) 5775 mem_tbl = mem_tbl_5709; 5776 else 5777 mem_tbl = mem_tbl_5706; 5778 5779 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) { 5780 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset, 5781 mem_tbl[i].len)) != 0) { 5782 return ret; 5783 } 5784 } 5785 5786 return ret; 5787 } 5788 5789 #define BNX2_MAC_LOOPBACK 0 5790 #define BNX2_PHY_LOOPBACK 1 5791 5792 static int 5793 bnx2_run_loopback(struct bnx2 *bp, int loopback_mode) 5794 { 5795 unsigned int pkt_size, num_pkts, i; 5796 struct sk_buff *skb; 5797 u8 *data; 5798 unsigned char *packet; 5799 u16 rx_start_idx, rx_idx; 5800 dma_addr_t map; 5801 struct bnx2_tx_bd *txbd; 5802 struct bnx2_sw_bd *rx_buf; 5803 struct l2_fhdr *rx_hdr; 5804 int ret = -ENODEV; 5805 struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi; 5806 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; 5807 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; 5808 5809 tx_napi = bnapi; 5810 5811 txr = &tx_napi->tx_ring; 5812 rxr = &bnapi->rx_ring; 5813 if (loopback_mode == BNX2_MAC_LOOPBACK) { 5814 bp->loopback = MAC_LOOPBACK; 5815 bnx2_set_mac_loopback(bp); 5816 } 5817 else if (loopback_mode == BNX2_PHY_LOOPBACK) { 5818 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) 5819 return 0; 5820 5821 bp->loopback = PHY_LOOPBACK; 5822 bnx2_set_phy_loopback(bp); 5823 } 5824 else 5825 return -EINVAL; 5826 5827 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4); 5828 skb = netdev_alloc_skb(bp->dev, pkt_size); 5829 if (!skb) 5830 return -ENOMEM; 5831 packet = skb_put(skb, pkt_size); 5832 memcpy(packet, bp->dev->dev_addr, ETH_ALEN); 5833 memset(packet + ETH_ALEN, 0x0, 8); 5834 for (i = 14; i < pkt_size; i++) 5835 packet[i] = (unsigned char) (i & 0xff); 5836 5837 map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size, 5838 PCI_DMA_TODEVICE); 5839 if (dma_mapping_error(&bp->pdev->dev, map)) { 5840 dev_kfree_skb(skb); 5841 return -EIO; 5842 } 5843 5844 BNX2_WR(bp, BNX2_HC_COMMAND, 5845 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT); 5846 5847 BNX2_RD(bp, BNX2_HC_COMMAND); 5848 5849 udelay(5); 5850 rx_start_idx = bnx2_get_hw_rx_cons(bnapi); 5851 5852 num_pkts = 0; 5853 5854 txbd = &txr->tx_desc_ring[BNX2_TX_RING_IDX(txr->tx_prod)]; 5855 5856 txbd->tx_bd_haddr_hi = (u64) map >> 32; 5857 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff; 5858 txbd->tx_bd_mss_nbytes = pkt_size; 5859 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END; 5860 5861 num_pkts++; 5862 txr->tx_prod = BNX2_NEXT_TX_BD(txr->tx_prod); 5863 txr->tx_prod_bseq += pkt_size; 5864 5865 BNX2_WR16(bp, txr->tx_bidx_addr, txr->tx_prod); 5866 BNX2_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq); 5867 5868 udelay(100); 5869 5870 BNX2_WR(bp, BNX2_HC_COMMAND, 5871 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT); 5872 5873 BNX2_RD(bp, BNX2_HC_COMMAND); 5874 5875 udelay(5); 5876 5877 dma_unmap_single(&bp->pdev->dev, map, pkt_size, PCI_DMA_TODEVICE); 5878 dev_kfree_skb(skb); 5879 5880 if (bnx2_get_hw_tx_cons(tx_napi) != txr->tx_prod) 5881 goto loopback_test_done; 5882 5883 rx_idx = bnx2_get_hw_rx_cons(bnapi); 5884 if (rx_idx != rx_start_idx + num_pkts) { 5885 goto loopback_test_done; 5886 } 5887 5888 rx_buf = &rxr->rx_buf_ring[rx_start_idx]; 5889 data = rx_buf->data; 5890 5891 rx_hdr = get_l2_fhdr(data); 5892 data = (u8 *)rx_hdr + BNX2_RX_OFFSET; 5893 5894 dma_sync_single_for_cpu(&bp->pdev->dev, 5895 dma_unmap_addr(rx_buf, mapping), 5896 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE); 5897 5898 if (rx_hdr->l2_fhdr_status & 5899 (L2_FHDR_ERRORS_BAD_CRC | 5900 L2_FHDR_ERRORS_PHY_DECODE | 5901 L2_FHDR_ERRORS_ALIGNMENT | 5902 L2_FHDR_ERRORS_TOO_SHORT | 5903 L2_FHDR_ERRORS_GIANT_FRAME)) { 5904 5905 goto loopback_test_done; 5906 } 5907 5908 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) { 5909 goto loopback_test_done; 5910 } 5911 5912 for (i = 14; i < pkt_size; i++) { 5913 if (*(data + i) != (unsigned char) (i & 0xff)) { 5914 goto loopback_test_done; 5915 } 5916 } 5917 5918 ret = 0; 5919 5920 loopback_test_done: 5921 bp->loopback = 0; 5922 return ret; 5923 } 5924 5925 #define BNX2_MAC_LOOPBACK_FAILED 1 5926 #define BNX2_PHY_LOOPBACK_FAILED 2 5927 #define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \ 5928 BNX2_PHY_LOOPBACK_FAILED) 5929 5930 static int 5931 bnx2_test_loopback(struct bnx2 *bp) 5932 { 5933 int rc = 0; 5934 5935 if (!netif_running(bp->dev)) 5936 return BNX2_LOOPBACK_FAILED; 5937 5938 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET); 5939 spin_lock_bh(&bp->phy_lock); 5940 bnx2_init_phy(bp, 1); 5941 spin_unlock_bh(&bp->phy_lock); 5942 if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK)) 5943 rc |= BNX2_MAC_LOOPBACK_FAILED; 5944 if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK)) 5945 rc |= BNX2_PHY_LOOPBACK_FAILED; 5946 return rc; 5947 } 5948 5949 #define NVRAM_SIZE 0x200 5950 #define CRC32_RESIDUAL 0xdebb20e3 5951 5952 static int 5953 bnx2_test_nvram(struct bnx2 *bp) 5954 { 5955 __be32 buf[NVRAM_SIZE / 4]; 5956 u8 *data = (u8 *) buf; 5957 int rc = 0; 5958 u32 magic, csum; 5959 5960 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0) 5961 goto test_nvram_done; 5962 5963 magic = be32_to_cpu(buf[0]); 5964 if (magic != 0x669955aa) { 5965 rc = -ENODEV; 5966 goto test_nvram_done; 5967 } 5968 5969 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0) 5970 goto test_nvram_done; 5971 5972 csum = ether_crc_le(0x100, data); 5973 if (csum != CRC32_RESIDUAL) { 5974 rc = -ENODEV; 5975 goto test_nvram_done; 5976 } 5977 5978 csum = ether_crc_le(0x100, data + 0x100); 5979 if (csum != CRC32_RESIDUAL) { 5980 rc = -ENODEV; 5981 } 5982 5983 test_nvram_done: 5984 return rc; 5985 } 5986 5987 static int 5988 bnx2_test_link(struct bnx2 *bp) 5989 { 5990 u32 bmsr; 5991 5992 if (!netif_running(bp->dev)) 5993 return -ENODEV; 5994 5995 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) { 5996 if (bp->link_up) 5997 return 0; 5998 return -ENODEV; 5999 } 6000 spin_lock_bh(&bp->phy_lock); 6001 bnx2_enable_bmsr1(bp); 6002 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr); 6003 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr); 6004 bnx2_disable_bmsr1(bp); 6005 spin_unlock_bh(&bp->phy_lock); 6006 6007 if (bmsr & BMSR_LSTATUS) { 6008 return 0; 6009 } 6010 return -ENODEV; 6011 } 6012 6013 static int 6014 bnx2_test_intr(struct bnx2 *bp) 6015 { 6016 int i; 6017 u16 status_idx; 6018 6019 if (!netif_running(bp->dev)) 6020 return -ENODEV; 6021 6022 status_idx = BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff; 6023 6024 /* This register is not touched during run-time. */ 6025 BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW); 6026 BNX2_RD(bp, BNX2_HC_COMMAND); 6027 6028 for (i = 0; i < 10; i++) { 6029 if ((BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) != 6030 status_idx) { 6031 6032 break; 6033 } 6034 6035 msleep_interruptible(10); 6036 } 6037 if (i < 10) 6038 return 0; 6039 6040 return -ENODEV; 6041 } 6042 6043 /* Determining link for parallel detection. */ 6044 static int 6045 bnx2_5706_serdes_has_link(struct bnx2 *bp) 6046 { 6047 u32 mode_ctl, an_dbg, exp; 6048 6049 if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL) 6050 return 0; 6051 6052 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL); 6053 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl); 6054 6055 if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET)) 6056 return 0; 6057 6058 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG); 6059 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg); 6060 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg); 6061 6062 if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID)) 6063 return 0; 6064 6065 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1); 6066 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp); 6067 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp); 6068 6069 if (exp & MII_EXPAND_REG1_RUDI_C) /* receiving CONFIG */ 6070 return 0; 6071 6072 return 1; 6073 } 6074 6075 static void 6076 bnx2_5706_serdes_timer(struct bnx2 *bp) 6077 { 6078 int check_link = 1; 6079 6080 spin_lock(&bp->phy_lock); 6081 if (bp->serdes_an_pending) { 6082 bp->serdes_an_pending--; 6083 check_link = 0; 6084 } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) { 6085 u32 bmcr; 6086 6087 bp->current_interval = BNX2_TIMER_INTERVAL; 6088 6089 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); 6090 6091 if (bmcr & BMCR_ANENABLE) { 6092 if (bnx2_5706_serdes_has_link(bp)) { 6093 bmcr &= ~BMCR_ANENABLE; 6094 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX; 6095 bnx2_write_phy(bp, bp->mii_bmcr, bmcr); 6096 bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT; 6097 } 6098 } 6099 } 6100 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) && 6101 (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) { 6102 u32 phy2; 6103 6104 bnx2_write_phy(bp, 0x17, 0x0f01); 6105 bnx2_read_phy(bp, 0x15, &phy2); 6106 if (phy2 & 0x20) { 6107 u32 bmcr; 6108 6109 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); 6110 bmcr |= BMCR_ANENABLE; 6111 bnx2_write_phy(bp, bp->mii_bmcr, bmcr); 6112 6113 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT; 6114 } 6115 } else 6116 bp->current_interval = BNX2_TIMER_INTERVAL; 6117 6118 if (check_link) { 6119 u32 val; 6120 6121 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG); 6122 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val); 6123 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val); 6124 6125 if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) { 6126 if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) { 6127 bnx2_5706s_force_link_dn(bp, 1); 6128 bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN; 6129 } else 6130 bnx2_set_link(bp); 6131 } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC)) 6132 bnx2_set_link(bp); 6133 } 6134 spin_unlock(&bp->phy_lock); 6135 } 6136 6137 static void 6138 bnx2_5708_serdes_timer(struct bnx2 *bp) 6139 { 6140 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) 6141 return; 6142 6143 if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) { 6144 bp->serdes_an_pending = 0; 6145 return; 6146 } 6147 6148 spin_lock(&bp->phy_lock); 6149 if (bp->serdes_an_pending) 6150 bp->serdes_an_pending--; 6151 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) { 6152 u32 bmcr; 6153 6154 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); 6155 if (bmcr & BMCR_ANENABLE) { 6156 bnx2_enable_forced_2g5(bp); 6157 bp->current_interval = BNX2_SERDES_FORCED_TIMEOUT; 6158 } else { 6159 bnx2_disable_forced_2g5(bp); 6160 bp->serdes_an_pending = 2; 6161 bp->current_interval = BNX2_TIMER_INTERVAL; 6162 } 6163 6164 } else 6165 bp->current_interval = BNX2_TIMER_INTERVAL; 6166 6167 spin_unlock(&bp->phy_lock); 6168 } 6169 6170 static void 6171 bnx2_timer(unsigned long data) 6172 { 6173 struct bnx2 *bp = (struct bnx2 *) data; 6174 6175 if (!netif_running(bp->dev)) 6176 return; 6177 6178 if (atomic_read(&bp->intr_sem) != 0) 6179 goto bnx2_restart_timer; 6180 6181 if ((bp->flags & (BNX2_FLAG_USING_MSI | BNX2_FLAG_ONE_SHOT_MSI)) == 6182 BNX2_FLAG_USING_MSI) 6183 bnx2_chk_missed_msi(bp); 6184 6185 bnx2_send_heart_beat(bp); 6186 6187 bp->stats_blk->stat_FwRxDrop = 6188 bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT); 6189 6190 /* workaround occasional corrupted counters */ 6191 if ((bp->flags & BNX2_FLAG_BROKEN_STATS) && bp->stats_ticks) 6192 BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | 6193 BNX2_HC_COMMAND_STATS_NOW); 6194 6195 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { 6196 if (BNX2_CHIP(bp) == BNX2_CHIP_5706) 6197 bnx2_5706_serdes_timer(bp); 6198 else 6199 bnx2_5708_serdes_timer(bp); 6200 } 6201 6202 bnx2_restart_timer: 6203 mod_timer(&bp->timer, jiffies + bp->current_interval); 6204 } 6205 6206 static int 6207 bnx2_request_irq(struct bnx2 *bp) 6208 { 6209 unsigned long flags; 6210 struct bnx2_irq *irq; 6211 int rc = 0, i; 6212 6213 if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX) 6214 flags = 0; 6215 else 6216 flags = IRQF_SHARED; 6217 6218 for (i = 0; i < bp->irq_nvecs; i++) { 6219 irq = &bp->irq_tbl[i]; 6220 rc = request_irq(irq->vector, irq->handler, flags, irq->name, 6221 &bp->bnx2_napi[i]); 6222 if (rc) 6223 break; 6224 irq->requested = 1; 6225 } 6226 return rc; 6227 } 6228 6229 static void 6230 __bnx2_free_irq(struct bnx2 *bp) 6231 { 6232 struct bnx2_irq *irq; 6233 int i; 6234 6235 for (i = 0; i < bp->irq_nvecs; i++) { 6236 irq = &bp->irq_tbl[i]; 6237 if (irq->requested) 6238 free_irq(irq->vector, &bp->bnx2_napi[i]); 6239 irq->requested = 0; 6240 } 6241 } 6242 6243 static void 6244 bnx2_free_irq(struct bnx2 *bp) 6245 { 6246 6247 __bnx2_free_irq(bp); 6248 if (bp->flags & BNX2_FLAG_USING_MSI) 6249 pci_disable_msi(bp->pdev); 6250 else if (bp->flags & BNX2_FLAG_USING_MSIX) 6251 pci_disable_msix(bp->pdev); 6252 6253 bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI); 6254 } 6255 6256 static void 6257 bnx2_enable_msix(struct bnx2 *bp, int msix_vecs) 6258 { 6259 int i, total_vecs; 6260 struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC]; 6261 struct net_device *dev = bp->dev; 6262 const int len = sizeof(bp->irq_tbl[0].name); 6263 6264 bnx2_setup_msix_tbl(bp); 6265 BNX2_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1); 6266 BNX2_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE); 6267 BNX2_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE); 6268 6269 /* Need to flush the previous three writes to ensure MSI-X 6270 * is setup properly */ 6271 BNX2_RD(bp, BNX2_PCI_MSIX_CONTROL); 6272 6273 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) { 6274 msix_ent[i].entry = i; 6275 msix_ent[i].vector = 0; 6276 } 6277 6278 total_vecs = msix_vecs; 6279 #ifdef BCM_CNIC 6280 total_vecs++; 6281 #endif 6282 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, 6283 BNX2_MIN_MSIX_VEC, total_vecs); 6284 if (total_vecs < 0) 6285 return; 6286 6287 msix_vecs = total_vecs; 6288 #ifdef BCM_CNIC 6289 msix_vecs--; 6290 #endif 6291 bp->irq_nvecs = msix_vecs; 6292 bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI; 6293 for (i = 0; i < total_vecs; i++) { 6294 bp->irq_tbl[i].vector = msix_ent[i].vector; 6295 snprintf(bp->irq_tbl[i].name, len, "%s-%d", dev->name, i); 6296 bp->irq_tbl[i].handler = bnx2_msi_1shot; 6297 } 6298 } 6299 6300 static int 6301 bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi) 6302 { 6303 int cpus = netif_get_num_default_rss_queues(); 6304 int msix_vecs; 6305 6306 if (!bp->num_req_rx_rings) 6307 msix_vecs = max(cpus + 1, bp->num_req_tx_rings); 6308 else if (!bp->num_req_tx_rings) 6309 msix_vecs = max(cpus, bp->num_req_rx_rings); 6310 else 6311 msix_vecs = max(bp->num_req_rx_rings, bp->num_req_tx_rings); 6312 6313 msix_vecs = min(msix_vecs, RX_MAX_RINGS); 6314 6315 bp->irq_tbl[0].handler = bnx2_interrupt; 6316 strcpy(bp->irq_tbl[0].name, bp->dev->name); 6317 bp->irq_nvecs = 1; 6318 bp->irq_tbl[0].vector = bp->pdev->irq; 6319 6320 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi) 6321 bnx2_enable_msix(bp, msix_vecs); 6322 6323 if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi && 6324 !(bp->flags & BNX2_FLAG_USING_MSIX)) { 6325 if (pci_enable_msi(bp->pdev) == 0) { 6326 bp->flags |= BNX2_FLAG_USING_MSI; 6327 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { 6328 bp->flags |= BNX2_FLAG_ONE_SHOT_MSI; 6329 bp->irq_tbl[0].handler = bnx2_msi_1shot; 6330 } else 6331 bp->irq_tbl[0].handler = bnx2_msi; 6332 6333 bp->irq_tbl[0].vector = bp->pdev->irq; 6334 } 6335 } 6336 6337 if (!bp->num_req_tx_rings) 6338 bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs); 6339 else 6340 bp->num_tx_rings = min(bp->irq_nvecs, bp->num_req_tx_rings); 6341 6342 if (!bp->num_req_rx_rings) 6343 bp->num_rx_rings = bp->irq_nvecs; 6344 else 6345 bp->num_rx_rings = min(bp->irq_nvecs, bp->num_req_rx_rings); 6346 6347 netif_set_real_num_tx_queues(bp->dev, bp->num_tx_rings); 6348 6349 return netif_set_real_num_rx_queues(bp->dev, bp->num_rx_rings); 6350 } 6351 6352 /* Called with rtnl_lock */ 6353 static int 6354 bnx2_open(struct net_device *dev) 6355 { 6356 struct bnx2 *bp = netdev_priv(dev); 6357 int rc; 6358 6359 netif_carrier_off(dev); 6360 6361 bnx2_disable_int(bp); 6362 6363 rc = bnx2_setup_int_mode(bp, disable_msi); 6364 if (rc) 6365 goto open_err; 6366 bnx2_init_napi(bp); 6367 bnx2_napi_enable(bp); 6368 rc = bnx2_alloc_mem(bp); 6369 if (rc) 6370 goto open_err; 6371 6372 rc = bnx2_request_irq(bp); 6373 if (rc) 6374 goto open_err; 6375 6376 rc = bnx2_init_nic(bp, 1); 6377 if (rc) 6378 goto open_err; 6379 6380 mod_timer(&bp->timer, jiffies + bp->current_interval); 6381 6382 atomic_set(&bp->intr_sem, 0); 6383 6384 memset(bp->temp_stats_blk, 0, sizeof(struct statistics_block)); 6385 6386 bnx2_enable_int(bp); 6387 6388 if (bp->flags & BNX2_FLAG_USING_MSI) { 6389 /* Test MSI to make sure it is working 6390 * If MSI test fails, go back to INTx mode 6391 */ 6392 if (bnx2_test_intr(bp) != 0) { 6393 netdev_warn(bp->dev, "No interrupt was generated using MSI, switching to INTx mode. Please report this failure to the PCI maintainer and include system chipset information.\n"); 6394 6395 bnx2_disable_int(bp); 6396 bnx2_free_irq(bp); 6397 6398 bnx2_setup_int_mode(bp, 1); 6399 6400 rc = bnx2_init_nic(bp, 0); 6401 6402 if (!rc) 6403 rc = bnx2_request_irq(bp); 6404 6405 if (rc) { 6406 del_timer_sync(&bp->timer); 6407 goto open_err; 6408 } 6409 bnx2_enable_int(bp); 6410 } 6411 } 6412 if (bp->flags & BNX2_FLAG_USING_MSI) 6413 netdev_info(dev, "using MSI\n"); 6414 else if (bp->flags & BNX2_FLAG_USING_MSIX) 6415 netdev_info(dev, "using MSIX\n"); 6416 6417 netif_tx_start_all_queues(dev); 6418 out: 6419 return rc; 6420 6421 open_err: 6422 bnx2_napi_disable(bp); 6423 bnx2_free_skbs(bp); 6424 bnx2_free_irq(bp); 6425 bnx2_free_mem(bp); 6426 bnx2_del_napi(bp); 6427 goto out; 6428 } 6429 6430 static void 6431 bnx2_reset_task(struct work_struct *work) 6432 { 6433 struct bnx2 *bp = container_of(work, struct bnx2, reset_task); 6434 int rc; 6435 u16 pcicmd; 6436 6437 rtnl_lock(); 6438 if (!netif_running(bp->dev)) { 6439 rtnl_unlock(); 6440 return; 6441 } 6442 6443 bnx2_netif_stop(bp, true); 6444 6445 pci_read_config_word(bp->pdev, PCI_COMMAND, &pcicmd); 6446 if (!(pcicmd & PCI_COMMAND_MEMORY)) { 6447 /* in case PCI block has reset */ 6448 pci_restore_state(bp->pdev); 6449 pci_save_state(bp->pdev); 6450 } 6451 rc = bnx2_init_nic(bp, 1); 6452 if (rc) { 6453 netdev_err(bp->dev, "failed to reset NIC, closing\n"); 6454 bnx2_napi_enable(bp); 6455 dev_close(bp->dev); 6456 rtnl_unlock(); 6457 return; 6458 } 6459 6460 atomic_set(&bp->intr_sem, 1); 6461 bnx2_netif_start(bp, true); 6462 rtnl_unlock(); 6463 } 6464 6465 #define BNX2_FTQ_ENTRY(ftq) { __stringify(ftq##FTQ_CTL), BNX2_##ftq##FTQ_CTL } 6466 6467 static void 6468 bnx2_dump_ftq(struct bnx2 *bp) 6469 { 6470 int i; 6471 u32 reg, bdidx, cid, valid; 6472 struct net_device *dev = bp->dev; 6473 static const struct ftq_reg { 6474 char *name; 6475 u32 off; 6476 } ftq_arr[] = { 6477 BNX2_FTQ_ENTRY(RV2P_P), 6478 BNX2_FTQ_ENTRY(RV2P_T), 6479 BNX2_FTQ_ENTRY(RV2P_M), 6480 BNX2_FTQ_ENTRY(TBDR_), 6481 BNX2_FTQ_ENTRY(TDMA_), 6482 BNX2_FTQ_ENTRY(TXP_), 6483 BNX2_FTQ_ENTRY(TXP_), 6484 BNX2_FTQ_ENTRY(TPAT_), 6485 BNX2_FTQ_ENTRY(RXP_C), 6486 BNX2_FTQ_ENTRY(RXP_), 6487 BNX2_FTQ_ENTRY(COM_COMXQ_), 6488 BNX2_FTQ_ENTRY(COM_COMTQ_), 6489 BNX2_FTQ_ENTRY(COM_COMQ_), 6490 BNX2_FTQ_ENTRY(CP_CPQ_), 6491 }; 6492 6493 netdev_err(dev, "<--- start FTQ dump --->\n"); 6494 for (i = 0; i < ARRAY_SIZE(ftq_arr); i++) 6495 netdev_err(dev, "%s %08x\n", ftq_arr[i].name, 6496 bnx2_reg_rd_ind(bp, ftq_arr[i].off)); 6497 6498 netdev_err(dev, "CPU states:\n"); 6499 for (reg = BNX2_TXP_CPU_MODE; reg <= BNX2_CP_CPU_MODE; reg += 0x40000) 6500 netdev_err(dev, "%06x mode %x state %x evt_mask %x pc %x pc %x instr %x\n", 6501 reg, bnx2_reg_rd_ind(bp, reg), 6502 bnx2_reg_rd_ind(bp, reg + 4), 6503 bnx2_reg_rd_ind(bp, reg + 8), 6504 bnx2_reg_rd_ind(bp, reg + 0x1c), 6505 bnx2_reg_rd_ind(bp, reg + 0x1c), 6506 bnx2_reg_rd_ind(bp, reg + 0x20)); 6507 6508 netdev_err(dev, "<--- end FTQ dump --->\n"); 6509 netdev_err(dev, "<--- start TBDC dump --->\n"); 6510 netdev_err(dev, "TBDC free cnt: %ld\n", 6511 BNX2_RD(bp, BNX2_TBDC_STATUS) & BNX2_TBDC_STATUS_FREE_CNT); 6512 netdev_err(dev, "LINE CID BIDX CMD VALIDS\n"); 6513 for (i = 0; i < 0x20; i++) { 6514 int j = 0; 6515 6516 BNX2_WR(bp, BNX2_TBDC_BD_ADDR, i); 6517 BNX2_WR(bp, BNX2_TBDC_CAM_OPCODE, 6518 BNX2_TBDC_CAM_OPCODE_OPCODE_CAM_READ); 6519 BNX2_WR(bp, BNX2_TBDC_COMMAND, BNX2_TBDC_COMMAND_CMD_REG_ARB); 6520 while ((BNX2_RD(bp, BNX2_TBDC_COMMAND) & 6521 BNX2_TBDC_COMMAND_CMD_REG_ARB) && j < 100) 6522 j++; 6523 6524 cid = BNX2_RD(bp, BNX2_TBDC_CID); 6525 bdidx = BNX2_RD(bp, BNX2_TBDC_BIDX); 6526 valid = BNX2_RD(bp, BNX2_TBDC_CAM_OPCODE); 6527 netdev_err(dev, "%02x %06x %04lx %02x [%x]\n", 6528 i, cid, bdidx & BNX2_TBDC_BDIDX_BDIDX, 6529 bdidx >> 24, (valid >> 8) & 0x0ff); 6530 } 6531 netdev_err(dev, "<--- end TBDC dump --->\n"); 6532 } 6533 6534 static void 6535 bnx2_dump_state(struct bnx2 *bp) 6536 { 6537 struct net_device *dev = bp->dev; 6538 u32 val1, val2; 6539 6540 pci_read_config_dword(bp->pdev, PCI_COMMAND, &val1); 6541 netdev_err(dev, "DEBUG: intr_sem[%x] PCI_CMD[%08x]\n", 6542 atomic_read(&bp->intr_sem), val1); 6543 pci_read_config_dword(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &val1); 6544 pci_read_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, &val2); 6545 netdev_err(dev, "DEBUG: PCI_PM[%08x] PCI_MISC_CFG[%08x]\n", val1, val2); 6546 netdev_err(dev, "DEBUG: EMAC_TX_STATUS[%08x] EMAC_RX_STATUS[%08x]\n", 6547 BNX2_RD(bp, BNX2_EMAC_TX_STATUS), 6548 BNX2_RD(bp, BNX2_EMAC_RX_STATUS)); 6549 netdev_err(dev, "DEBUG: RPM_MGMT_PKT_CTRL[%08x]\n", 6550 BNX2_RD(bp, BNX2_RPM_MGMT_PKT_CTRL)); 6551 netdev_err(dev, "DEBUG: HC_STATS_INTERRUPT_STATUS[%08x]\n", 6552 BNX2_RD(bp, BNX2_HC_STATS_INTERRUPT_STATUS)); 6553 if (bp->flags & BNX2_FLAG_USING_MSIX) 6554 netdev_err(dev, "DEBUG: PBA[%08x]\n", 6555 BNX2_RD(bp, BNX2_PCI_GRC_WINDOW3_BASE)); 6556 } 6557 6558 static void 6559 bnx2_tx_timeout(struct net_device *dev) 6560 { 6561 struct bnx2 *bp = netdev_priv(dev); 6562 6563 bnx2_dump_ftq(bp); 6564 bnx2_dump_state(bp); 6565 bnx2_dump_mcp_state(bp); 6566 6567 /* This allows the netif to be shutdown gracefully before resetting */ 6568 schedule_work(&bp->reset_task); 6569 } 6570 6571 /* Called with netif_tx_lock. 6572 * bnx2_tx_int() runs without netif_tx_lock unless it needs to call 6573 * netif_wake_queue(). 6574 */ 6575 static netdev_tx_t 6576 bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev) 6577 { 6578 struct bnx2 *bp = netdev_priv(dev); 6579 dma_addr_t mapping; 6580 struct bnx2_tx_bd *txbd; 6581 struct bnx2_sw_tx_bd *tx_buf; 6582 u32 len, vlan_tag_flags, last_frag, mss; 6583 u16 prod, ring_prod; 6584 int i; 6585 struct bnx2_napi *bnapi; 6586 struct bnx2_tx_ring_info *txr; 6587 struct netdev_queue *txq; 6588 6589 /* Determine which tx ring we will be placed on */ 6590 i = skb_get_queue_mapping(skb); 6591 bnapi = &bp->bnx2_napi[i]; 6592 txr = &bnapi->tx_ring; 6593 txq = netdev_get_tx_queue(dev, i); 6594 6595 if (unlikely(bnx2_tx_avail(bp, txr) < 6596 (skb_shinfo(skb)->nr_frags + 1))) { 6597 netif_tx_stop_queue(txq); 6598 netdev_err(dev, "BUG! Tx ring full when queue awake!\n"); 6599 6600 return NETDEV_TX_BUSY; 6601 } 6602 len = skb_headlen(skb); 6603 prod = txr->tx_prod; 6604 ring_prod = BNX2_TX_RING_IDX(prod); 6605 6606 vlan_tag_flags = 0; 6607 if (skb->ip_summed == CHECKSUM_PARTIAL) { 6608 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; 6609 } 6610 6611 if (skb_vlan_tag_present(skb)) { 6612 vlan_tag_flags |= 6613 (TX_BD_FLAGS_VLAN_TAG | (skb_vlan_tag_get(skb) << 16)); 6614 } 6615 6616 if ((mss = skb_shinfo(skb)->gso_size)) { 6617 u32 tcp_opt_len; 6618 struct iphdr *iph; 6619 6620 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO; 6621 6622 tcp_opt_len = tcp_optlen(skb); 6623 6624 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) { 6625 u32 tcp_off = skb_transport_offset(skb) - 6626 sizeof(struct ipv6hdr) - ETH_HLEN; 6627 6628 vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) | 6629 TX_BD_FLAGS_SW_FLAGS; 6630 if (likely(tcp_off == 0)) 6631 vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK; 6632 else { 6633 tcp_off >>= 3; 6634 vlan_tag_flags |= ((tcp_off & 0x3) << 6635 TX_BD_FLAGS_TCP6_OFF0_SHL) | 6636 ((tcp_off & 0x10) << 6637 TX_BD_FLAGS_TCP6_OFF4_SHL); 6638 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL; 6639 } 6640 } else { 6641 iph = ip_hdr(skb); 6642 if (tcp_opt_len || (iph->ihl > 5)) { 6643 vlan_tag_flags |= ((iph->ihl - 5) + 6644 (tcp_opt_len >> 2)) << 8; 6645 } 6646 } 6647 } else 6648 mss = 0; 6649 6650 mapping = dma_map_single(&bp->pdev->dev, skb->data, len, PCI_DMA_TODEVICE); 6651 if (dma_mapping_error(&bp->pdev->dev, mapping)) { 6652 dev_kfree_skb_any(skb); 6653 return NETDEV_TX_OK; 6654 } 6655 6656 tx_buf = &txr->tx_buf_ring[ring_prod]; 6657 tx_buf->skb = skb; 6658 dma_unmap_addr_set(tx_buf, mapping, mapping); 6659 6660 txbd = &txr->tx_desc_ring[ring_prod]; 6661 6662 txbd->tx_bd_haddr_hi = (u64) mapping >> 32; 6663 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff; 6664 txbd->tx_bd_mss_nbytes = len | (mss << 16); 6665 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START; 6666 6667 last_frag = skb_shinfo(skb)->nr_frags; 6668 tx_buf->nr_frags = last_frag; 6669 tx_buf->is_gso = skb_is_gso(skb); 6670 6671 for (i = 0; i < last_frag; i++) { 6672 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 6673 6674 prod = BNX2_NEXT_TX_BD(prod); 6675 ring_prod = BNX2_TX_RING_IDX(prod); 6676 txbd = &txr->tx_desc_ring[ring_prod]; 6677 6678 len = skb_frag_size(frag); 6679 mapping = skb_frag_dma_map(&bp->pdev->dev, frag, 0, len, 6680 DMA_TO_DEVICE); 6681 if (dma_mapping_error(&bp->pdev->dev, mapping)) 6682 goto dma_error; 6683 dma_unmap_addr_set(&txr->tx_buf_ring[ring_prod], mapping, 6684 mapping); 6685 6686 txbd->tx_bd_haddr_hi = (u64) mapping >> 32; 6687 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff; 6688 txbd->tx_bd_mss_nbytes = len | (mss << 16); 6689 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags; 6690 6691 } 6692 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END; 6693 6694 /* Sync BD data before updating TX mailbox */ 6695 wmb(); 6696 6697 netdev_tx_sent_queue(txq, skb->len); 6698 6699 prod = BNX2_NEXT_TX_BD(prod); 6700 txr->tx_prod_bseq += skb->len; 6701 6702 BNX2_WR16(bp, txr->tx_bidx_addr, prod); 6703 BNX2_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq); 6704 6705 mmiowb(); 6706 6707 txr->tx_prod = prod; 6708 6709 if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) { 6710 netif_tx_stop_queue(txq); 6711 6712 /* netif_tx_stop_queue() must be done before checking 6713 * tx index in bnx2_tx_avail() below, because in 6714 * bnx2_tx_int(), we update tx index before checking for 6715 * netif_tx_queue_stopped(). 6716 */ 6717 smp_mb(); 6718 if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh) 6719 netif_tx_wake_queue(txq); 6720 } 6721 6722 return NETDEV_TX_OK; 6723 dma_error: 6724 /* save value of frag that failed */ 6725 last_frag = i; 6726 6727 /* start back at beginning and unmap skb */ 6728 prod = txr->tx_prod; 6729 ring_prod = BNX2_TX_RING_IDX(prod); 6730 tx_buf = &txr->tx_buf_ring[ring_prod]; 6731 tx_buf->skb = NULL; 6732 dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping), 6733 skb_headlen(skb), PCI_DMA_TODEVICE); 6734 6735 /* unmap remaining mapped pages */ 6736 for (i = 0; i < last_frag; i++) { 6737 prod = BNX2_NEXT_TX_BD(prod); 6738 ring_prod = BNX2_TX_RING_IDX(prod); 6739 tx_buf = &txr->tx_buf_ring[ring_prod]; 6740 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping), 6741 skb_frag_size(&skb_shinfo(skb)->frags[i]), 6742 PCI_DMA_TODEVICE); 6743 } 6744 6745 dev_kfree_skb_any(skb); 6746 return NETDEV_TX_OK; 6747 } 6748 6749 /* Called with rtnl_lock */ 6750 static int 6751 bnx2_close(struct net_device *dev) 6752 { 6753 struct bnx2 *bp = netdev_priv(dev); 6754 6755 bnx2_disable_int_sync(bp); 6756 bnx2_napi_disable(bp); 6757 netif_tx_disable(dev); 6758 del_timer_sync(&bp->timer); 6759 bnx2_shutdown_chip(bp); 6760 bnx2_free_irq(bp); 6761 bnx2_free_skbs(bp); 6762 bnx2_free_mem(bp); 6763 bnx2_del_napi(bp); 6764 bp->link_up = 0; 6765 netif_carrier_off(bp->dev); 6766 return 0; 6767 } 6768 6769 static void 6770 bnx2_save_stats(struct bnx2 *bp) 6771 { 6772 u32 *hw_stats = (u32 *) bp->stats_blk; 6773 u32 *temp_stats = (u32 *) bp->temp_stats_blk; 6774 int i; 6775 6776 /* The 1st 10 counters are 64-bit counters */ 6777 for (i = 0; i < 20; i += 2) { 6778 u32 hi; 6779 u64 lo; 6780 6781 hi = temp_stats[i] + hw_stats[i]; 6782 lo = (u64) temp_stats[i + 1] + (u64) hw_stats[i + 1]; 6783 if (lo > 0xffffffff) 6784 hi++; 6785 temp_stats[i] = hi; 6786 temp_stats[i + 1] = lo & 0xffffffff; 6787 } 6788 6789 for ( ; i < sizeof(struct statistics_block) / 4; i++) 6790 temp_stats[i] += hw_stats[i]; 6791 } 6792 6793 #define GET_64BIT_NET_STATS64(ctr) \ 6794 (((u64) (ctr##_hi) << 32) + (u64) (ctr##_lo)) 6795 6796 #define GET_64BIT_NET_STATS(ctr) \ 6797 GET_64BIT_NET_STATS64(bp->stats_blk->ctr) + \ 6798 GET_64BIT_NET_STATS64(bp->temp_stats_blk->ctr) 6799 6800 #define GET_32BIT_NET_STATS(ctr) \ 6801 (unsigned long) (bp->stats_blk->ctr + \ 6802 bp->temp_stats_blk->ctr) 6803 6804 static struct rtnl_link_stats64 * 6805 bnx2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *net_stats) 6806 { 6807 struct bnx2 *bp = netdev_priv(dev); 6808 6809 if (bp->stats_blk == NULL) 6810 return net_stats; 6811 6812 net_stats->rx_packets = 6813 GET_64BIT_NET_STATS(stat_IfHCInUcastPkts) + 6814 GET_64BIT_NET_STATS(stat_IfHCInMulticastPkts) + 6815 GET_64BIT_NET_STATS(stat_IfHCInBroadcastPkts); 6816 6817 net_stats->tx_packets = 6818 GET_64BIT_NET_STATS(stat_IfHCOutUcastPkts) + 6819 GET_64BIT_NET_STATS(stat_IfHCOutMulticastPkts) + 6820 GET_64BIT_NET_STATS(stat_IfHCOutBroadcastPkts); 6821 6822 net_stats->rx_bytes = 6823 GET_64BIT_NET_STATS(stat_IfHCInOctets); 6824 6825 net_stats->tx_bytes = 6826 GET_64BIT_NET_STATS(stat_IfHCOutOctets); 6827 6828 net_stats->multicast = 6829 GET_64BIT_NET_STATS(stat_IfHCInMulticastPkts); 6830 6831 net_stats->collisions = 6832 GET_32BIT_NET_STATS(stat_EtherStatsCollisions); 6833 6834 net_stats->rx_length_errors = 6835 GET_32BIT_NET_STATS(stat_EtherStatsUndersizePkts) + 6836 GET_32BIT_NET_STATS(stat_EtherStatsOverrsizePkts); 6837 6838 net_stats->rx_over_errors = 6839 GET_32BIT_NET_STATS(stat_IfInFTQDiscards) + 6840 GET_32BIT_NET_STATS(stat_IfInMBUFDiscards); 6841 6842 net_stats->rx_frame_errors = 6843 GET_32BIT_NET_STATS(stat_Dot3StatsAlignmentErrors); 6844 6845 net_stats->rx_crc_errors = 6846 GET_32BIT_NET_STATS(stat_Dot3StatsFCSErrors); 6847 6848 net_stats->rx_errors = net_stats->rx_length_errors + 6849 net_stats->rx_over_errors + net_stats->rx_frame_errors + 6850 net_stats->rx_crc_errors; 6851 6852 net_stats->tx_aborted_errors = 6853 GET_32BIT_NET_STATS(stat_Dot3StatsExcessiveCollisions) + 6854 GET_32BIT_NET_STATS(stat_Dot3StatsLateCollisions); 6855 6856 if ((BNX2_CHIP(bp) == BNX2_CHIP_5706) || 6857 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0)) 6858 net_stats->tx_carrier_errors = 0; 6859 else { 6860 net_stats->tx_carrier_errors = 6861 GET_32BIT_NET_STATS(stat_Dot3StatsCarrierSenseErrors); 6862 } 6863 6864 net_stats->tx_errors = 6865 GET_32BIT_NET_STATS(stat_emac_tx_stat_dot3statsinternalmactransmiterrors) + 6866 net_stats->tx_aborted_errors + 6867 net_stats->tx_carrier_errors; 6868 6869 net_stats->rx_missed_errors = 6870 GET_32BIT_NET_STATS(stat_IfInFTQDiscards) + 6871 GET_32BIT_NET_STATS(stat_IfInMBUFDiscards) + 6872 GET_32BIT_NET_STATS(stat_FwRxDrop); 6873 6874 return net_stats; 6875 } 6876 6877 /* All ethtool functions called with rtnl_lock */ 6878 6879 static int 6880 bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 6881 { 6882 struct bnx2 *bp = netdev_priv(dev); 6883 int support_serdes = 0, support_copper = 0; 6884 6885 cmd->supported = SUPPORTED_Autoneg; 6886 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) { 6887 support_serdes = 1; 6888 support_copper = 1; 6889 } else if (bp->phy_port == PORT_FIBRE) 6890 support_serdes = 1; 6891 else 6892 support_copper = 1; 6893 6894 if (support_serdes) { 6895 cmd->supported |= SUPPORTED_1000baseT_Full | 6896 SUPPORTED_FIBRE; 6897 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) 6898 cmd->supported |= SUPPORTED_2500baseX_Full; 6899 6900 } 6901 if (support_copper) { 6902 cmd->supported |= SUPPORTED_10baseT_Half | 6903 SUPPORTED_10baseT_Full | 6904 SUPPORTED_100baseT_Half | 6905 SUPPORTED_100baseT_Full | 6906 SUPPORTED_1000baseT_Full | 6907 SUPPORTED_TP; 6908 6909 } 6910 6911 spin_lock_bh(&bp->phy_lock); 6912 cmd->port = bp->phy_port; 6913 cmd->advertising = bp->advertising; 6914 6915 if (bp->autoneg & AUTONEG_SPEED) { 6916 cmd->autoneg = AUTONEG_ENABLE; 6917 } else { 6918 cmd->autoneg = AUTONEG_DISABLE; 6919 } 6920 6921 if (netif_carrier_ok(dev)) { 6922 ethtool_cmd_speed_set(cmd, bp->line_speed); 6923 cmd->duplex = bp->duplex; 6924 if (!(bp->phy_flags & BNX2_PHY_FLAG_SERDES)) { 6925 if (bp->phy_flags & BNX2_PHY_FLAG_MDIX) 6926 cmd->eth_tp_mdix = ETH_TP_MDI_X; 6927 else 6928 cmd->eth_tp_mdix = ETH_TP_MDI; 6929 } 6930 } 6931 else { 6932 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN); 6933 cmd->duplex = DUPLEX_UNKNOWN; 6934 } 6935 spin_unlock_bh(&bp->phy_lock); 6936 6937 cmd->transceiver = XCVR_INTERNAL; 6938 cmd->phy_address = bp->phy_addr; 6939 6940 return 0; 6941 } 6942 6943 static int 6944 bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 6945 { 6946 struct bnx2 *bp = netdev_priv(dev); 6947 u8 autoneg = bp->autoneg; 6948 u8 req_duplex = bp->req_duplex; 6949 u16 req_line_speed = bp->req_line_speed; 6950 u32 advertising = bp->advertising; 6951 int err = -EINVAL; 6952 6953 spin_lock_bh(&bp->phy_lock); 6954 6955 if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE) 6956 goto err_out_unlock; 6957 6958 if (cmd->port != bp->phy_port && 6959 !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)) 6960 goto err_out_unlock; 6961 6962 /* If device is down, we can store the settings only if the user 6963 * is setting the currently active port. 6964 */ 6965 if (!netif_running(dev) && cmd->port != bp->phy_port) 6966 goto err_out_unlock; 6967 6968 if (cmd->autoneg == AUTONEG_ENABLE) { 6969 autoneg |= AUTONEG_SPEED; 6970 6971 advertising = cmd->advertising; 6972 if (cmd->port == PORT_TP) { 6973 advertising &= ETHTOOL_ALL_COPPER_SPEED; 6974 if (!advertising) 6975 advertising = ETHTOOL_ALL_COPPER_SPEED; 6976 } else { 6977 advertising &= ETHTOOL_ALL_FIBRE_SPEED; 6978 if (!advertising) 6979 advertising = ETHTOOL_ALL_FIBRE_SPEED; 6980 } 6981 advertising |= ADVERTISED_Autoneg; 6982 } 6983 else { 6984 u32 speed = ethtool_cmd_speed(cmd); 6985 if (cmd->port == PORT_FIBRE) { 6986 if ((speed != SPEED_1000 && 6987 speed != SPEED_2500) || 6988 (cmd->duplex != DUPLEX_FULL)) 6989 goto err_out_unlock; 6990 6991 if (speed == SPEED_2500 && 6992 !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) 6993 goto err_out_unlock; 6994 } else if (speed == SPEED_1000 || speed == SPEED_2500) 6995 goto err_out_unlock; 6996 6997 autoneg &= ~AUTONEG_SPEED; 6998 req_line_speed = speed; 6999 req_duplex = cmd->duplex; 7000 advertising = 0; 7001 } 7002 7003 bp->autoneg = autoneg; 7004 bp->advertising = advertising; 7005 bp->req_line_speed = req_line_speed; 7006 bp->req_duplex = req_duplex; 7007 7008 err = 0; 7009 /* If device is down, the new settings will be picked up when it is 7010 * brought up. 7011 */ 7012 if (netif_running(dev)) 7013 err = bnx2_setup_phy(bp, cmd->port); 7014 7015 err_out_unlock: 7016 spin_unlock_bh(&bp->phy_lock); 7017 7018 return err; 7019 } 7020 7021 static void 7022 bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 7023 { 7024 struct bnx2 *bp = netdev_priv(dev); 7025 7026 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); 7027 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version)); 7028 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info)); 7029 strlcpy(info->fw_version, bp->fw_version, sizeof(info->fw_version)); 7030 } 7031 7032 #define BNX2_REGDUMP_LEN (32 * 1024) 7033 7034 static int 7035 bnx2_get_regs_len(struct net_device *dev) 7036 { 7037 return BNX2_REGDUMP_LEN; 7038 } 7039 7040 static void 7041 bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p) 7042 { 7043 u32 *p = _p, i, offset; 7044 u8 *orig_p = _p; 7045 struct bnx2 *bp = netdev_priv(dev); 7046 static const u32 reg_boundaries[] = { 7047 0x0000, 0x0098, 0x0400, 0x045c, 7048 0x0800, 0x0880, 0x0c00, 0x0c10, 7049 0x0c30, 0x0d08, 0x1000, 0x101c, 7050 0x1040, 0x1048, 0x1080, 0x10a4, 7051 0x1400, 0x1490, 0x1498, 0x14f0, 7052 0x1500, 0x155c, 0x1580, 0x15dc, 7053 0x1600, 0x1658, 0x1680, 0x16d8, 7054 0x1800, 0x1820, 0x1840, 0x1854, 7055 0x1880, 0x1894, 0x1900, 0x1984, 7056 0x1c00, 0x1c0c, 0x1c40, 0x1c54, 7057 0x1c80, 0x1c94, 0x1d00, 0x1d84, 7058 0x2000, 0x2030, 0x23c0, 0x2400, 7059 0x2800, 0x2820, 0x2830, 0x2850, 7060 0x2b40, 0x2c10, 0x2fc0, 0x3058, 7061 0x3c00, 0x3c94, 0x4000, 0x4010, 7062 0x4080, 0x4090, 0x43c0, 0x4458, 7063 0x4c00, 0x4c18, 0x4c40, 0x4c54, 7064 0x4fc0, 0x5010, 0x53c0, 0x5444, 7065 0x5c00, 0x5c18, 0x5c80, 0x5c90, 7066 0x5fc0, 0x6000, 0x6400, 0x6428, 7067 0x6800, 0x6848, 0x684c, 0x6860, 7068 0x6888, 0x6910, 0x8000 7069 }; 7070 7071 regs->version = 0; 7072 7073 memset(p, 0, BNX2_REGDUMP_LEN); 7074 7075 if (!netif_running(bp->dev)) 7076 return; 7077 7078 i = 0; 7079 offset = reg_boundaries[0]; 7080 p += offset; 7081 while (offset < BNX2_REGDUMP_LEN) { 7082 *p++ = BNX2_RD(bp, offset); 7083 offset += 4; 7084 if (offset == reg_boundaries[i + 1]) { 7085 offset = reg_boundaries[i + 2]; 7086 p = (u32 *) (orig_p + offset); 7087 i += 2; 7088 } 7089 } 7090 } 7091 7092 static void 7093 bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 7094 { 7095 struct bnx2 *bp = netdev_priv(dev); 7096 7097 if (bp->flags & BNX2_FLAG_NO_WOL) { 7098 wol->supported = 0; 7099 wol->wolopts = 0; 7100 } 7101 else { 7102 wol->supported = WAKE_MAGIC; 7103 if (bp->wol) 7104 wol->wolopts = WAKE_MAGIC; 7105 else 7106 wol->wolopts = 0; 7107 } 7108 memset(&wol->sopass, 0, sizeof(wol->sopass)); 7109 } 7110 7111 static int 7112 bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 7113 { 7114 struct bnx2 *bp = netdev_priv(dev); 7115 7116 if (wol->wolopts & ~WAKE_MAGIC) 7117 return -EINVAL; 7118 7119 if (wol->wolopts & WAKE_MAGIC) { 7120 if (bp->flags & BNX2_FLAG_NO_WOL) 7121 return -EINVAL; 7122 7123 bp->wol = 1; 7124 } 7125 else { 7126 bp->wol = 0; 7127 } 7128 7129 device_set_wakeup_enable(&bp->pdev->dev, bp->wol); 7130 7131 return 0; 7132 } 7133 7134 static int 7135 bnx2_nway_reset(struct net_device *dev) 7136 { 7137 struct bnx2 *bp = netdev_priv(dev); 7138 u32 bmcr; 7139 7140 if (!netif_running(dev)) 7141 return -EAGAIN; 7142 7143 if (!(bp->autoneg & AUTONEG_SPEED)) { 7144 return -EINVAL; 7145 } 7146 7147 spin_lock_bh(&bp->phy_lock); 7148 7149 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) { 7150 int rc; 7151 7152 rc = bnx2_setup_remote_phy(bp, bp->phy_port); 7153 spin_unlock_bh(&bp->phy_lock); 7154 return rc; 7155 } 7156 7157 /* Force a link down visible on the other side */ 7158 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { 7159 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK); 7160 spin_unlock_bh(&bp->phy_lock); 7161 7162 msleep(20); 7163 7164 spin_lock_bh(&bp->phy_lock); 7165 7166 bp->current_interval = BNX2_SERDES_AN_TIMEOUT; 7167 bp->serdes_an_pending = 1; 7168 mod_timer(&bp->timer, jiffies + bp->current_interval); 7169 } 7170 7171 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); 7172 bmcr &= ~BMCR_LOOPBACK; 7173 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE); 7174 7175 spin_unlock_bh(&bp->phy_lock); 7176 7177 return 0; 7178 } 7179 7180 static u32 7181 bnx2_get_link(struct net_device *dev) 7182 { 7183 struct bnx2 *bp = netdev_priv(dev); 7184 7185 return bp->link_up; 7186 } 7187 7188 static int 7189 bnx2_get_eeprom_len(struct net_device *dev) 7190 { 7191 struct bnx2 *bp = netdev_priv(dev); 7192 7193 if (bp->flash_info == NULL) 7194 return 0; 7195 7196 return (int) bp->flash_size; 7197 } 7198 7199 static int 7200 bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, 7201 u8 *eebuf) 7202 { 7203 struct bnx2 *bp = netdev_priv(dev); 7204 int rc; 7205 7206 /* parameters already validated in ethtool_get_eeprom */ 7207 7208 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len); 7209 7210 return rc; 7211 } 7212 7213 static int 7214 bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, 7215 u8 *eebuf) 7216 { 7217 struct bnx2 *bp = netdev_priv(dev); 7218 int rc; 7219 7220 /* parameters already validated in ethtool_set_eeprom */ 7221 7222 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len); 7223 7224 return rc; 7225 } 7226 7227 static int 7228 bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal) 7229 { 7230 struct bnx2 *bp = netdev_priv(dev); 7231 7232 memset(coal, 0, sizeof(struct ethtool_coalesce)); 7233 7234 coal->rx_coalesce_usecs = bp->rx_ticks; 7235 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip; 7236 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int; 7237 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int; 7238 7239 coal->tx_coalesce_usecs = bp->tx_ticks; 7240 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip; 7241 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int; 7242 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int; 7243 7244 coal->stats_block_coalesce_usecs = bp->stats_ticks; 7245 7246 return 0; 7247 } 7248 7249 static int 7250 bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal) 7251 { 7252 struct bnx2 *bp = netdev_priv(dev); 7253 7254 bp->rx_ticks = (u16) coal->rx_coalesce_usecs; 7255 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff; 7256 7257 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames; 7258 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff; 7259 7260 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq; 7261 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff; 7262 7263 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq; 7264 if (bp->rx_quick_cons_trip_int > 0xff) 7265 bp->rx_quick_cons_trip_int = 0xff; 7266 7267 bp->tx_ticks = (u16) coal->tx_coalesce_usecs; 7268 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff; 7269 7270 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames; 7271 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff; 7272 7273 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq; 7274 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff; 7275 7276 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq; 7277 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int = 7278 0xff; 7279 7280 bp->stats_ticks = coal->stats_block_coalesce_usecs; 7281 if (bp->flags & BNX2_FLAG_BROKEN_STATS) { 7282 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC) 7283 bp->stats_ticks = USEC_PER_SEC; 7284 } 7285 if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS) 7286 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS; 7287 bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS; 7288 7289 if (netif_running(bp->dev)) { 7290 bnx2_netif_stop(bp, true); 7291 bnx2_init_nic(bp, 0); 7292 bnx2_netif_start(bp, true); 7293 } 7294 7295 return 0; 7296 } 7297 7298 static void 7299 bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) 7300 { 7301 struct bnx2 *bp = netdev_priv(dev); 7302 7303 ering->rx_max_pending = BNX2_MAX_TOTAL_RX_DESC_CNT; 7304 ering->rx_jumbo_max_pending = BNX2_MAX_TOTAL_RX_PG_DESC_CNT; 7305 7306 ering->rx_pending = bp->rx_ring_size; 7307 ering->rx_jumbo_pending = bp->rx_pg_ring_size; 7308 7309 ering->tx_max_pending = BNX2_MAX_TX_DESC_CNT; 7310 ering->tx_pending = bp->tx_ring_size; 7311 } 7312 7313 static int 7314 bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx, bool reset_irq) 7315 { 7316 if (netif_running(bp->dev)) { 7317 /* Reset will erase chipset stats; save them */ 7318 bnx2_save_stats(bp); 7319 7320 bnx2_netif_stop(bp, true); 7321 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET); 7322 if (reset_irq) { 7323 bnx2_free_irq(bp); 7324 bnx2_del_napi(bp); 7325 } else { 7326 __bnx2_free_irq(bp); 7327 } 7328 bnx2_free_skbs(bp); 7329 bnx2_free_mem(bp); 7330 } 7331 7332 bnx2_set_rx_ring_size(bp, rx); 7333 bp->tx_ring_size = tx; 7334 7335 if (netif_running(bp->dev)) { 7336 int rc = 0; 7337 7338 if (reset_irq) { 7339 rc = bnx2_setup_int_mode(bp, disable_msi); 7340 bnx2_init_napi(bp); 7341 } 7342 7343 if (!rc) 7344 rc = bnx2_alloc_mem(bp); 7345 7346 if (!rc) 7347 rc = bnx2_request_irq(bp); 7348 7349 if (!rc) 7350 rc = bnx2_init_nic(bp, 0); 7351 7352 if (rc) { 7353 bnx2_napi_enable(bp); 7354 dev_close(bp->dev); 7355 return rc; 7356 } 7357 #ifdef BCM_CNIC 7358 mutex_lock(&bp->cnic_lock); 7359 /* Let cnic know about the new status block. */ 7360 if (bp->cnic_eth_dev.drv_state & CNIC_DRV_STATE_REGD) 7361 bnx2_setup_cnic_irq_info(bp); 7362 mutex_unlock(&bp->cnic_lock); 7363 #endif 7364 bnx2_netif_start(bp, true); 7365 } 7366 return 0; 7367 } 7368 7369 static int 7370 bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) 7371 { 7372 struct bnx2 *bp = netdev_priv(dev); 7373 int rc; 7374 7375 if ((ering->rx_pending > BNX2_MAX_TOTAL_RX_DESC_CNT) || 7376 (ering->tx_pending > BNX2_MAX_TX_DESC_CNT) || 7377 (ering->tx_pending <= MAX_SKB_FRAGS)) { 7378 7379 return -EINVAL; 7380 } 7381 rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending, 7382 false); 7383 return rc; 7384 } 7385 7386 static void 7387 bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) 7388 { 7389 struct bnx2 *bp = netdev_priv(dev); 7390 7391 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0); 7392 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0); 7393 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0); 7394 } 7395 7396 static int 7397 bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) 7398 { 7399 struct bnx2 *bp = netdev_priv(dev); 7400 7401 bp->req_flow_ctrl = 0; 7402 if (epause->rx_pause) 7403 bp->req_flow_ctrl |= FLOW_CTRL_RX; 7404 if (epause->tx_pause) 7405 bp->req_flow_ctrl |= FLOW_CTRL_TX; 7406 7407 if (epause->autoneg) { 7408 bp->autoneg |= AUTONEG_FLOW_CTRL; 7409 } 7410 else { 7411 bp->autoneg &= ~AUTONEG_FLOW_CTRL; 7412 } 7413 7414 if (netif_running(dev)) { 7415 spin_lock_bh(&bp->phy_lock); 7416 bnx2_setup_phy(bp, bp->phy_port); 7417 spin_unlock_bh(&bp->phy_lock); 7418 } 7419 7420 return 0; 7421 } 7422 7423 static struct { 7424 char string[ETH_GSTRING_LEN]; 7425 } bnx2_stats_str_arr[] = { 7426 { "rx_bytes" }, 7427 { "rx_error_bytes" }, 7428 { "tx_bytes" }, 7429 { "tx_error_bytes" }, 7430 { "rx_ucast_packets" }, 7431 { "rx_mcast_packets" }, 7432 { "rx_bcast_packets" }, 7433 { "tx_ucast_packets" }, 7434 { "tx_mcast_packets" }, 7435 { "tx_bcast_packets" }, 7436 { "tx_mac_errors" }, 7437 { "tx_carrier_errors" }, 7438 { "rx_crc_errors" }, 7439 { "rx_align_errors" }, 7440 { "tx_single_collisions" }, 7441 { "tx_multi_collisions" }, 7442 { "tx_deferred" }, 7443 { "tx_excess_collisions" }, 7444 { "tx_late_collisions" }, 7445 { "tx_total_collisions" }, 7446 { "rx_fragments" }, 7447 { "rx_jabbers" }, 7448 { "rx_undersize_packets" }, 7449 { "rx_oversize_packets" }, 7450 { "rx_64_byte_packets" }, 7451 { "rx_65_to_127_byte_packets" }, 7452 { "rx_128_to_255_byte_packets" }, 7453 { "rx_256_to_511_byte_packets" }, 7454 { "rx_512_to_1023_byte_packets" }, 7455 { "rx_1024_to_1522_byte_packets" }, 7456 { "rx_1523_to_9022_byte_packets" }, 7457 { "tx_64_byte_packets" }, 7458 { "tx_65_to_127_byte_packets" }, 7459 { "tx_128_to_255_byte_packets" }, 7460 { "tx_256_to_511_byte_packets" }, 7461 { "tx_512_to_1023_byte_packets" }, 7462 { "tx_1024_to_1522_byte_packets" }, 7463 { "tx_1523_to_9022_byte_packets" }, 7464 { "rx_xon_frames" }, 7465 { "rx_xoff_frames" }, 7466 { "tx_xon_frames" }, 7467 { "tx_xoff_frames" }, 7468 { "rx_mac_ctrl_frames" }, 7469 { "rx_filtered_packets" }, 7470 { "rx_ftq_discards" }, 7471 { "rx_discards" }, 7472 { "rx_fw_discards" }, 7473 }; 7474 7475 #define BNX2_NUM_STATS ARRAY_SIZE(bnx2_stats_str_arr) 7476 7477 #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4) 7478 7479 static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = { 7480 STATS_OFFSET32(stat_IfHCInOctets_hi), 7481 STATS_OFFSET32(stat_IfHCInBadOctets_hi), 7482 STATS_OFFSET32(stat_IfHCOutOctets_hi), 7483 STATS_OFFSET32(stat_IfHCOutBadOctets_hi), 7484 STATS_OFFSET32(stat_IfHCInUcastPkts_hi), 7485 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi), 7486 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi), 7487 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi), 7488 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi), 7489 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi), 7490 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors), 7491 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors), 7492 STATS_OFFSET32(stat_Dot3StatsFCSErrors), 7493 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors), 7494 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames), 7495 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames), 7496 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions), 7497 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions), 7498 STATS_OFFSET32(stat_Dot3StatsLateCollisions), 7499 STATS_OFFSET32(stat_EtherStatsCollisions), 7500 STATS_OFFSET32(stat_EtherStatsFragments), 7501 STATS_OFFSET32(stat_EtherStatsJabbers), 7502 STATS_OFFSET32(stat_EtherStatsUndersizePkts), 7503 STATS_OFFSET32(stat_EtherStatsOverrsizePkts), 7504 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets), 7505 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets), 7506 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets), 7507 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets), 7508 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets), 7509 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets), 7510 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets), 7511 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets), 7512 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets), 7513 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets), 7514 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets), 7515 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets), 7516 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets), 7517 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets), 7518 STATS_OFFSET32(stat_XonPauseFramesReceived), 7519 STATS_OFFSET32(stat_XoffPauseFramesReceived), 7520 STATS_OFFSET32(stat_OutXonSent), 7521 STATS_OFFSET32(stat_OutXoffSent), 7522 STATS_OFFSET32(stat_MacControlFramesReceived), 7523 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards), 7524 STATS_OFFSET32(stat_IfInFTQDiscards), 7525 STATS_OFFSET32(stat_IfInMBUFDiscards), 7526 STATS_OFFSET32(stat_FwRxDrop), 7527 }; 7528 7529 /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are 7530 * skipped because of errata. 7531 */ 7532 static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = { 7533 8,0,8,8,8,8,8,8,8,8, 7534 4,0,4,4,4,4,4,4,4,4, 7535 4,4,4,4,4,4,4,4,4,4, 7536 4,4,4,4,4,4,4,4,4,4, 7537 4,4,4,4,4,4,4, 7538 }; 7539 7540 static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = { 7541 8,0,8,8,8,8,8,8,8,8, 7542 4,4,4,4,4,4,4,4,4,4, 7543 4,4,4,4,4,4,4,4,4,4, 7544 4,4,4,4,4,4,4,4,4,4, 7545 4,4,4,4,4,4,4, 7546 }; 7547 7548 #define BNX2_NUM_TESTS 6 7549 7550 static struct { 7551 char string[ETH_GSTRING_LEN]; 7552 } bnx2_tests_str_arr[BNX2_NUM_TESTS] = { 7553 { "register_test (offline)" }, 7554 { "memory_test (offline)" }, 7555 { "loopback_test (offline)" }, 7556 { "nvram_test (online)" }, 7557 { "interrupt_test (online)" }, 7558 { "link_test (online)" }, 7559 }; 7560 7561 static int 7562 bnx2_get_sset_count(struct net_device *dev, int sset) 7563 { 7564 switch (sset) { 7565 case ETH_SS_TEST: 7566 return BNX2_NUM_TESTS; 7567 case ETH_SS_STATS: 7568 return BNX2_NUM_STATS; 7569 default: 7570 return -EOPNOTSUPP; 7571 } 7572 } 7573 7574 static void 7575 bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf) 7576 { 7577 struct bnx2 *bp = netdev_priv(dev); 7578 7579 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS); 7580 if (etest->flags & ETH_TEST_FL_OFFLINE) { 7581 int i; 7582 7583 bnx2_netif_stop(bp, true); 7584 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG); 7585 bnx2_free_skbs(bp); 7586 7587 if (bnx2_test_registers(bp) != 0) { 7588 buf[0] = 1; 7589 etest->flags |= ETH_TEST_FL_FAILED; 7590 } 7591 if (bnx2_test_memory(bp) != 0) { 7592 buf[1] = 1; 7593 etest->flags |= ETH_TEST_FL_FAILED; 7594 } 7595 if ((buf[2] = bnx2_test_loopback(bp)) != 0) 7596 etest->flags |= ETH_TEST_FL_FAILED; 7597 7598 if (!netif_running(bp->dev)) 7599 bnx2_shutdown_chip(bp); 7600 else { 7601 bnx2_init_nic(bp, 1); 7602 bnx2_netif_start(bp, true); 7603 } 7604 7605 /* wait for link up */ 7606 for (i = 0; i < 7; i++) { 7607 if (bp->link_up) 7608 break; 7609 msleep_interruptible(1000); 7610 } 7611 } 7612 7613 if (bnx2_test_nvram(bp) != 0) { 7614 buf[3] = 1; 7615 etest->flags |= ETH_TEST_FL_FAILED; 7616 } 7617 if (bnx2_test_intr(bp) != 0) { 7618 buf[4] = 1; 7619 etest->flags |= ETH_TEST_FL_FAILED; 7620 } 7621 7622 if (bnx2_test_link(bp) != 0) { 7623 buf[5] = 1; 7624 etest->flags |= ETH_TEST_FL_FAILED; 7625 7626 } 7627 } 7628 7629 static void 7630 bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf) 7631 { 7632 switch (stringset) { 7633 case ETH_SS_STATS: 7634 memcpy(buf, bnx2_stats_str_arr, 7635 sizeof(bnx2_stats_str_arr)); 7636 break; 7637 case ETH_SS_TEST: 7638 memcpy(buf, bnx2_tests_str_arr, 7639 sizeof(bnx2_tests_str_arr)); 7640 break; 7641 } 7642 } 7643 7644 static void 7645 bnx2_get_ethtool_stats(struct net_device *dev, 7646 struct ethtool_stats *stats, u64 *buf) 7647 { 7648 struct bnx2 *bp = netdev_priv(dev); 7649 int i; 7650 u32 *hw_stats = (u32 *) bp->stats_blk; 7651 u32 *temp_stats = (u32 *) bp->temp_stats_blk; 7652 u8 *stats_len_arr = NULL; 7653 7654 if (hw_stats == NULL) { 7655 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS); 7656 return; 7657 } 7658 7659 if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) || 7660 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1) || 7661 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A2) || 7662 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0)) 7663 stats_len_arr = bnx2_5706_stats_len_arr; 7664 else 7665 stats_len_arr = bnx2_5708_stats_len_arr; 7666 7667 for (i = 0; i < BNX2_NUM_STATS; i++) { 7668 unsigned long offset; 7669 7670 if (stats_len_arr[i] == 0) { 7671 /* skip this counter */ 7672 buf[i] = 0; 7673 continue; 7674 } 7675 7676 offset = bnx2_stats_offset_arr[i]; 7677 if (stats_len_arr[i] == 4) { 7678 /* 4-byte counter */ 7679 buf[i] = (u64) *(hw_stats + offset) + 7680 *(temp_stats + offset); 7681 continue; 7682 } 7683 /* 8-byte counter */ 7684 buf[i] = (((u64) *(hw_stats + offset)) << 32) + 7685 *(hw_stats + offset + 1) + 7686 (((u64) *(temp_stats + offset)) << 32) + 7687 *(temp_stats + offset + 1); 7688 } 7689 } 7690 7691 static int 7692 bnx2_set_phys_id(struct net_device *dev, enum ethtool_phys_id_state state) 7693 { 7694 struct bnx2 *bp = netdev_priv(dev); 7695 7696 switch (state) { 7697 case ETHTOOL_ID_ACTIVE: 7698 bp->leds_save = BNX2_RD(bp, BNX2_MISC_CFG); 7699 BNX2_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC); 7700 return 1; /* cycle on/off once per second */ 7701 7702 case ETHTOOL_ID_ON: 7703 BNX2_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE | 7704 BNX2_EMAC_LED_1000MB_OVERRIDE | 7705 BNX2_EMAC_LED_100MB_OVERRIDE | 7706 BNX2_EMAC_LED_10MB_OVERRIDE | 7707 BNX2_EMAC_LED_TRAFFIC_OVERRIDE | 7708 BNX2_EMAC_LED_TRAFFIC); 7709 break; 7710 7711 case ETHTOOL_ID_OFF: 7712 BNX2_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE); 7713 break; 7714 7715 case ETHTOOL_ID_INACTIVE: 7716 BNX2_WR(bp, BNX2_EMAC_LED, 0); 7717 BNX2_WR(bp, BNX2_MISC_CFG, bp->leds_save); 7718 break; 7719 } 7720 7721 return 0; 7722 } 7723 7724 static int 7725 bnx2_set_features(struct net_device *dev, netdev_features_t features) 7726 { 7727 struct bnx2 *bp = netdev_priv(dev); 7728 7729 /* TSO with VLAN tag won't work with current firmware */ 7730 if (features & NETIF_F_HW_VLAN_CTAG_TX) 7731 dev->vlan_features |= (dev->hw_features & NETIF_F_ALL_TSO); 7732 else 7733 dev->vlan_features &= ~NETIF_F_ALL_TSO; 7734 7735 if ((!!(features & NETIF_F_HW_VLAN_CTAG_RX) != 7736 !!(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) && 7737 netif_running(dev)) { 7738 bnx2_netif_stop(bp, false); 7739 dev->features = features; 7740 bnx2_set_rx_mode(dev); 7741 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1); 7742 bnx2_netif_start(bp, false); 7743 return 1; 7744 } 7745 7746 return 0; 7747 } 7748 7749 static void bnx2_get_channels(struct net_device *dev, 7750 struct ethtool_channels *channels) 7751 { 7752 struct bnx2 *bp = netdev_priv(dev); 7753 u32 max_rx_rings = 1; 7754 u32 max_tx_rings = 1; 7755 7756 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !disable_msi) { 7757 max_rx_rings = RX_MAX_RINGS; 7758 max_tx_rings = TX_MAX_RINGS; 7759 } 7760 7761 channels->max_rx = max_rx_rings; 7762 channels->max_tx = max_tx_rings; 7763 channels->max_other = 0; 7764 channels->max_combined = 0; 7765 channels->rx_count = bp->num_rx_rings; 7766 channels->tx_count = bp->num_tx_rings; 7767 channels->other_count = 0; 7768 channels->combined_count = 0; 7769 } 7770 7771 static int bnx2_set_channels(struct net_device *dev, 7772 struct ethtool_channels *channels) 7773 { 7774 struct bnx2 *bp = netdev_priv(dev); 7775 u32 max_rx_rings = 1; 7776 u32 max_tx_rings = 1; 7777 int rc = 0; 7778 7779 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !disable_msi) { 7780 max_rx_rings = RX_MAX_RINGS; 7781 max_tx_rings = TX_MAX_RINGS; 7782 } 7783 if (channels->rx_count > max_rx_rings || 7784 channels->tx_count > max_tx_rings) 7785 return -EINVAL; 7786 7787 bp->num_req_rx_rings = channels->rx_count; 7788 bp->num_req_tx_rings = channels->tx_count; 7789 7790 if (netif_running(dev)) 7791 rc = bnx2_change_ring_size(bp, bp->rx_ring_size, 7792 bp->tx_ring_size, true); 7793 7794 return rc; 7795 } 7796 7797 static const struct ethtool_ops bnx2_ethtool_ops = { 7798 .get_settings = bnx2_get_settings, 7799 .set_settings = bnx2_set_settings, 7800 .get_drvinfo = bnx2_get_drvinfo, 7801 .get_regs_len = bnx2_get_regs_len, 7802 .get_regs = bnx2_get_regs, 7803 .get_wol = bnx2_get_wol, 7804 .set_wol = bnx2_set_wol, 7805 .nway_reset = bnx2_nway_reset, 7806 .get_link = bnx2_get_link, 7807 .get_eeprom_len = bnx2_get_eeprom_len, 7808 .get_eeprom = bnx2_get_eeprom, 7809 .set_eeprom = bnx2_set_eeprom, 7810 .get_coalesce = bnx2_get_coalesce, 7811 .set_coalesce = bnx2_set_coalesce, 7812 .get_ringparam = bnx2_get_ringparam, 7813 .set_ringparam = bnx2_set_ringparam, 7814 .get_pauseparam = bnx2_get_pauseparam, 7815 .set_pauseparam = bnx2_set_pauseparam, 7816 .self_test = bnx2_self_test, 7817 .get_strings = bnx2_get_strings, 7818 .set_phys_id = bnx2_set_phys_id, 7819 .get_ethtool_stats = bnx2_get_ethtool_stats, 7820 .get_sset_count = bnx2_get_sset_count, 7821 .get_channels = bnx2_get_channels, 7822 .set_channels = bnx2_set_channels, 7823 }; 7824 7825 /* Called with rtnl_lock */ 7826 static int 7827 bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 7828 { 7829 struct mii_ioctl_data *data = if_mii(ifr); 7830 struct bnx2 *bp = netdev_priv(dev); 7831 int err; 7832 7833 switch(cmd) { 7834 case SIOCGMIIPHY: 7835 data->phy_id = bp->phy_addr; 7836 7837 /* fallthru */ 7838 case SIOCGMIIREG: { 7839 u32 mii_regval; 7840 7841 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) 7842 return -EOPNOTSUPP; 7843 7844 if (!netif_running(dev)) 7845 return -EAGAIN; 7846 7847 spin_lock_bh(&bp->phy_lock); 7848 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval); 7849 spin_unlock_bh(&bp->phy_lock); 7850 7851 data->val_out = mii_regval; 7852 7853 return err; 7854 } 7855 7856 case SIOCSMIIREG: 7857 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) 7858 return -EOPNOTSUPP; 7859 7860 if (!netif_running(dev)) 7861 return -EAGAIN; 7862 7863 spin_lock_bh(&bp->phy_lock); 7864 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in); 7865 spin_unlock_bh(&bp->phy_lock); 7866 7867 return err; 7868 7869 default: 7870 /* do nothing */ 7871 break; 7872 } 7873 return -EOPNOTSUPP; 7874 } 7875 7876 /* Called with rtnl_lock */ 7877 static int 7878 bnx2_change_mac_addr(struct net_device *dev, void *p) 7879 { 7880 struct sockaddr *addr = p; 7881 struct bnx2 *bp = netdev_priv(dev); 7882 7883 if (!is_valid_ether_addr(addr->sa_data)) 7884 return -EADDRNOTAVAIL; 7885 7886 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 7887 if (netif_running(dev)) 7888 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0); 7889 7890 return 0; 7891 } 7892 7893 /* Called with rtnl_lock */ 7894 static int 7895 bnx2_change_mtu(struct net_device *dev, int new_mtu) 7896 { 7897 struct bnx2 *bp = netdev_priv(dev); 7898 7899 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) || 7900 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE)) 7901 return -EINVAL; 7902 7903 dev->mtu = new_mtu; 7904 return bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size, 7905 false); 7906 } 7907 7908 #ifdef CONFIG_NET_POLL_CONTROLLER 7909 static void 7910 poll_bnx2(struct net_device *dev) 7911 { 7912 struct bnx2 *bp = netdev_priv(dev); 7913 int i; 7914 7915 for (i = 0; i < bp->irq_nvecs; i++) { 7916 struct bnx2_irq *irq = &bp->irq_tbl[i]; 7917 7918 disable_irq(irq->vector); 7919 irq->handler(irq->vector, &bp->bnx2_napi[i]); 7920 enable_irq(irq->vector); 7921 } 7922 } 7923 #endif 7924 7925 static void 7926 bnx2_get_5709_media(struct bnx2 *bp) 7927 { 7928 u32 val = BNX2_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL); 7929 u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID; 7930 u32 strap; 7931 7932 if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) 7933 return; 7934 else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) { 7935 bp->phy_flags |= BNX2_PHY_FLAG_SERDES; 7936 return; 7937 } 7938 7939 if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) 7940 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21; 7941 else 7942 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8; 7943 7944 if (bp->func == 0) { 7945 switch (strap) { 7946 case 0x4: 7947 case 0x5: 7948 case 0x6: 7949 bp->phy_flags |= BNX2_PHY_FLAG_SERDES; 7950 return; 7951 } 7952 } else { 7953 switch (strap) { 7954 case 0x1: 7955 case 0x2: 7956 case 0x4: 7957 bp->phy_flags |= BNX2_PHY_FLAG_SERDES; 7958 return; 7959 } 7960 } 7961 } 7962 7963 static void 7964 bnx2_get_pci_speed(struct bnx2 *bp) 7965 { 7966 u32 reg; 7967 7968 reg = BNX2_RD(bp, BNX2_PCICFG_MISC_STATUS); 7969 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) { 7970 u32 clkreg; 7971 7972 bp->flags |= BNX2_FLAG_PCIX; 7973 7974 clkreg = BNX2_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS); 7975 7976 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; 7977 switch (clkreg) { 7978 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: 7979 bp->bus_speed_mhz = 133; 7980 break; 7981 7982 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: 7983 bp->bus_speed_mhz = 100; 7984 break; 7985 7986 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: 7987 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: 7988 bp->bus_speed_mhz = 66; 7989 break; 7990 7991 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: 7992 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: 7993 bp->bus_speed_mhz = 50; 7994 break; 7995 7996 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: 7997 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: 7998 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: 7999 bp->bus_speed_mhz = 33; 8000 break; 8001 } 8002 } 8003 else { 8004 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN) 8005 bp->bus_speed_mhz = 66; 8006 else 8007 bp->bus_speed_mhz = 33; 8008 } 8009 8010 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET) 8011 bp->flags |= BNX2_FLAG_PCI_32BIT; 8012 8013 } 8014 8015 static void 8016 bnx2_read_vpd_fw_ver(struct bnx2 *bp) 8017 { 8018 int rc, i, j; 8019 u8 *data; 8020 unsigned int block_end, rosize, len; 8021 8022 #define BNX2_VPD_NVRAM_OFFSET 0x300 8023 #define BNX2_VPD_LEN 128 8024 #define BNX2_MAX_VER_SLEN 30 8025 8026 data = kmalloc(256, GFP_KERNEL); 8027 if (!data) 8028 return; 8029 8030 rc = bnx2_nvram_read(bp, BNX2_VPD_NVRAM_OFFSET, data + BNX2_VPD_LEN, 8031 BNX2_VPD_LEN); 8032 if (rc) 8033 goto vpd_done; 8034 8035 for (i = 0; i < BNX2_VPD_LEN; i += 4) { 8036 data[i] = data[i + BNX2_VPD_LEN + 3]; 8037 data[i + 1] = data[i + BNX2_VPD_LEN + 2]; 8038 data[i + 2] = data[i + BNX2_VPD_LEN + 1]; 8039 data[i + 3] = data[i + BNX2_VPD_LEN]; 8040 } 8041 8042 i = pci_vpd_find_tag(data, 0, BNX2_VPD_LEN, PCI_VPD_LRDT_RO_DATA); 8043 if (i < 0) 8044 goto vpd_done; 8045 8046 rosize = pci_vpd_lrdt_size(&data[i]); 8047 i += PCI_VPD_LRDT_TAG_SIZE; 8048 block_end = i + rosize; 8049 8050 if (block_end > BNX2_VPD_LEN) 8051 goto vpd_done; 8052 8053 j = pci_vpd_find_info_keyword(data, i, rosize, 8054 PCI_VPD_RO_KEYWORD_MFR_ID); 8055 if (j < 0) 8056 goto vpd_done; 8057 8058 len = pci_vpd_info_field_size(&data[j]); 8059 8060 j += PCI_VPD_INFO_FLD_HDR_SIZE; 8061 if (j + len > block_end || len != 4 || 8062 memcmp(&data[j], "1028", 4)) 8063 goto vpd_done; 8064 8065 j = pci_vpd_find_info_keyword(data, i, rosize, 8066 PCI_VPD_RO_KEYWORD_VENDOR0); 8067 if (j < 0) 8068 goto vpd_done; 8069 8070 len = pci_vpd_info_field_size(&data[j]); 8071 8072 j += PCI_VPD_INFO_FLD_HDR_SIZE; 8073 if (j + len > block_end || len > BNX2_MAX_VER_SLEN) 8074 goto vpd_done; 8075 8076 memcpy(bp->fw_version, &data[j], len); 8077 bp->fw_version[len] = ' '; 8078 8079 vpd_done: 8080 kfree(data); 8081 } 8082 8083 static int 8084 bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) 8085 { 8086 struct bnx2 *bp; 8087 int rc, i, j; 8088 u32 reg; 8089 u64 dma_mask, persist_dma_mask; 8090 int err; 8091 8092 SET_NETDEV_DEV(dev, &pdev->dev); 8093 bp = netdev_priv(dev); 8094 8095 bp->flags = 0; 8096 bp->phy_flags = 0; 8097 8098 bp->temp_stats_blk = 8099 kzalloc(sizeof(struct statistics_block), GFP_KERNEL); 8100 8101 if (bp->temp_stats_blk == NULL) { 8102 rc = -ENOMEM; 8103 goto err_out; 8104 } 8105 8106 /* enable device (incl. PCI PM wakeup), and bus-mastering */ 8107 rc = pci_enable_device(pdev); 8108 if (rc) { 8109 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); 8110 goto err_out; 8111 } 8112 8113 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 8114 dev_err(&pdev->dev, 8115 "Cannot find PCI device base address, aborting\n"); 8116 rc = -ENODEV; 8117 goto err_out_disable; 8118 } 8119 8120 rc = pci_request_regions(pdev, DRV_MODULE_NAME); 8121 if (rc) { 8122 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); 8123 goto err_out_disable; 8124 } 8125 8126 pci_set_master(pdev); 8127 8128 bp->pm_cap = pdev->pm_cap; 8129 if (bp->pm_cap == 0) { 8130 dev_err(&pdev->dev, 8131 "Cannot find power management capability, aborting\n"); 8132 rc = -EIO; 8133 goto err_out_release; 8134 } 8135 8136 bp->dev = dev; 8137 bp->pdev = pdev; 8138 8139 spin_lock_init(&bp->phy_lock); 8140 spin_lock_init(&bp->indirect_lock); 8141 #ifdef BCM_CNIC 8142 mutex_init(&bp->cnic_lock); 8143 #endif 8144 INIT_WORK(&bp->reset_task, bnx2_reset_task); 8145 8146 bp->regview = pci_iomap(pdev, 0, MB_GET_CID_ADDR(TX_TSS_CID + 8147 TX_MAX_TSS_RINGS + 1)); 8148 if (!bp->regview) { 8149 dev_err(&pdev->dev, "Cannot map register space, aborting\n"); 8150 rc = -ENOMEM; 8151 goto err_out_release; 8152 } 8153 8154 /* Configure byte swap and enable write to the reg_window registers. 8155 * Rely on CPU to do target byte swapping on big endian systems 8156 * The chip's target access swapping will not swap all accesses 8157 */ 8158 BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG, 8159 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 8160 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP); 8161 8162 bp->chip_id = BNX2_RD(bp, BNX2_MISC_ID); 8163 8164 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { 8165 if (!pci_is_pcie(pdev)) { 8166 dev_err(&pdev->dev, "Not PCIE, aborting\n"); 8167 rc = -EIO; 8168 goto err_out_unmap; 8169 } 8170 bp->flags |= BNX2_FLAG_PCIE; 8171 if (BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Ax) 8172 bp->flags |= BNX2_FLAG_JUMBO_BROKEN; 8173 8174 /* AER (Advanced Error Reporting) hooks */ 8175 err = pci_enable_pcie_error_reporting(pdev); 8176 if (!err) 8177 bp->flags |= BNX2_FLAG_AER_ENABLED; 8178 8179 } else { 8180 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX); 8181 if (bp->pcix_cap == 0) { 8182 dev_err(&pdev->dev, 8183 "Cannot find PCIX capability, aborting\n"); 8184 rc = -EIO; 8185 goto err_out_unmap; 8186 } 8187 bp->flags |= BNX2_FLAG_BROKEN_STATS; 8188 } 8189 8190 if (BNX2_CHIP(bp) == BNX2_CHIP_5709 && 8191 BNX2_CHIP_REV(bp) != BNX2_CHIP_REV_Ax) { 8192 if (pdev->msix_cap) 8193 bp->flags |= BNX2_FLAG_MSIX_CAP; 8194 } 8195 8196 if (BNX2_CHIP_ID(bp) != BNX2_CHIP_ID_5706_A0 && 8197 BNX2_CHIP_ID(bp) != BNX2_CHIP_ID_5706_A1) { 8198 if (pdev->msi_cap) 8199 bp->flags |= BNX2_FLAG_MSI_CAP; 8200 } 8201 8202 /* 5708 cannot support DMA addresses > 40-bit. */ 8203 if (BNX2_CHIP(bp) == BNX2_CHIP_5708) 8204 persist_dma_mask = dma_mask = DMA_BIT_MASK(40); 8205 else 8206 persist_dma_mask = dma_mask = DMA_BIT_MASK(64); 8207 8208 /* Configure DMA attributes. */ 8209 if (pci_set_dma_mask(pdev, dma_mask) == 0) { 8210 dev->features |= NETIF_F_HIGHDMA; 8211 rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask); 8212 if (rc) { 8213 dev_err(&pdev->dev, 8214 "pci_set_consistent_dma_mask failed, aborting\n"); 8215 goto err_out_unmap; 8216 } 8217 } else if ((rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) != 0) { 8218 dev_err(&pdev->dev, "System does not support DMA, aborting\n"); 8219 goto err_out_unmap; 8220 } 8221 8222 if (!(bp->flags & BNX2_FLAG_PCIE)) 8223 bnx2_get_pci_speed(bp); 8224 8225 /* 5706A0 may falsely detect SERR and PERR. */ 8226 if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) { 8227 reg = BNX2_RD(bp, PCI_COMMAND); 8228 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY); 8229 BNX2_WR(bp, PCI_COMMAND, reg); 8230 } else if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1) && 8231 !(bp->flags & BNX2_FLAG_PCIX)) { 8232 8233 dev_err(&pdev->dev, 8234 "5706 A1 can only be used in a PCIX bus, aborting\n"); 8235 goto err_out_unmap; 8236 } 8237 8238 bnx2_init_nvram(bp); 8239 8240 reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE); 8241 8242 if (bnx2_reg_rd_ind(bp, BNX2_MCP_TOE_ID) & BNX2_MCP_TOE_ID_FUNCTION_ID) 8243 bp->func = 1; 8244 8245 if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) == 8246 BNX2_SHM_HDR_SIGNATURE_SIG) { 8247 u32 off = bp->func << 2; 8248 8249 bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off); 8250 } else 8251 bp->shmem_base = HOST_VIEW_SHMEM_BASE; 8252 8253 /* Get the permanent MAC address. First we need to make sure the 8254 * firmware is actually running. 8255 */ 8256 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE); 8257 8258 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) != 8259 BNX2_DEV_INFO_SIGNATURE_MAGIC) { 8260 dev_err(&pdev->dev, "Firmware not running, aborting\n"); 8261 rc = -ENODEV; 8262 goto err_out_unmap; 8263 } 8264 8265 bnx2_read_vpd_fw_ver(bp); 8266 8267 j = strlen(bp->fw_version); 8268 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV); 8269 for (i = 0; i < 3 && j < 24; i++) { 8270 u8 num, k, skip0; 8271 8272 if (i == 0) { 8273 bp->fw_version[j++] = 'b'; 8274 bp->fw_version[j++] = 'c'; 8275 bp->fw_version[j++] = ' '; 8276 } 8277 num = (u8) (reg >> (24 - (i * 8))); 8278 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) { 8279 if (num >= k || !skip0 || k == 1) { 8280 bp->fw_version[j++] = (num / k) + '0'; 8281 skip0 = 0; 8282 } 8283 } 8284 if (i != 2) 8285 bp->fw_version[j++] = '.'; 8286 } 8287 reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE); 8288 if (reg & BNX2_PORT_FEATURE_WOL_ENABLED) 8289 bp->wol = 1; 8290 8291 if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) { 8292 bp->flags |= BNX2_FLAG_ASF_ENABLE; 8293 8294 for (i = 0; i < 30; i++) { 8295 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION); 8296 if (reg & BNX2_CONDITION_MFW_RUN_MASK) 8297 break; 8298 msleep(10); 8299 } 8300 } 8301 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION); 8302 reg &= BNX2_CONDITION_MFW_RUN_MASK; 8303 if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN && 8304 reg != BNX2_CONDITION_MFW_RUN_NONE) { 8305 u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR); 8306 8307 if (j < 32) 8308 bp->fw_version[j++] = ' '; 8309 for (i = 0; i < 3 && j < 28; i++) { 8310 reg = bnx2_reg_rd_ind(bp, addr + i * 4); 8311 reg = be32_to_cpu(reg); 8312 memcpy(&bp->fw_version[j], ®, 4); 8313 j += 4; 8314 } 8315 } 8316 8317 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER); 8318 bp->mac_addr[0] = (u8) (reg >> 8); 8319 bp->mac_addr[1] = (u8) reg; 8320 8321 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER); 8322 bp->mac_addr[2] = (u8) (reg >> 24); 8323 bp->mac_addr[3] = (u8) (reg >> 16); 8324 bp->mac_addr[4] = (u8) (reg >> 8); 8325 bp->mac_addr[5] = (u8) reg; 8326 8327 bp->tx_ring_size = BNX2_MAX_TX_DESC_CNT; 8328 bnx2_set_rx_ring_size(bp, 255); 8329 8330 bp->tx_quick_cons_trip_int = 2; 8331 bp->tx_quick_cons_trip = 20; 8332 bp->tx_ticks_int = 18; 8333 bp->tx_ticks = 80; 8334 8335 bp->rx_quick_cons_trip_int = 2; 8336 bp->rx_quick_cons_trip = 12; 8337 bp->rx_ticks_int = 18; 8338 bp->rx_ticks = 18; 8339 8340 bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS; 8341 8342 bp->current_interval = BNX2_TIMER_INTERVAL; 8343 8344 bp->phy_addr = 1; 8345 8346 /* allocate stats_blk */ 8347 rc = bnx2_alloc_stats_blk(dev); 8348 if (rc) 8349 goto err_out_unmap; 8350 8351 /* Disable WOL support if we are running on a SERDES chip. */ 8352 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) 8353 bnx2_get_5709_media(bp); 8354 else if (BNX2_CHIP_BOND(bp) & BNX2_CHIP_BOND_SERDES_BIT) 8355 bp->phy_flags |= BNX2_PHY_FLAG_SERDES; 8356 8357 bp->phy_port = PORT_TP; 8358 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { 8359 bp->phy_port = PORT_FIBRE; 8360 reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG); 8361 if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) { 8362 bp->flags |= BNX2_FLAG_NO_WOL; 8363 bp->wol = 0; 8364 } 8365 if (BNX2_CHIP(bp) == BNX2_CHIP_5706) { 8366 /* Don't do parallel detect on this board because of 8367 * some board problems. The link will not go down 8368 * if we do parallel detect. 8369 */ 8370 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP && 8371 pdev->subsystem_device == 0x310c) 8372 bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL; 8373 } else { 8374 bp->phy_addr = 2; 8375 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G) 8376 bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE; 8377 } 8378 } else if (BNX2_CHIP(bp) == BNX2_CHIP_5706 || 8379 BNX2_CHIP(bp) == BNX2_CHIP_5708) 8380 bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX; 8381 else if (BNX2_CHIP(bp) == BNX2_CHIP_5709 && 8382 (BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Ax || 8383 BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Bx)) 8384 bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC; 8385 8386 bnx2_init_fw_cap(bp); 8387 8388 if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0) || 8389 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B0) || 8390 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B1) || 8391 !(BNX2_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) { 8392 bp->flags |= BNX2_FLAG_NO_WOL; 8393 bp->wol = 0; 8394 } 8395 8396 if (bp->flags & BNX2_FLAG_NO_WOL) 8397 device_set_wakeup_capable(&bp->pdev->dev, false); 8398 else 8399 device_set_wakeup_enable(&bp->pdev->dev, bp->wol); 8400 8401 if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) { 8402 bp->tx_quick_cons_trip_int = 8403 bp->tx_quick_cons_trip; 8404 bp->tx_ticks_int = bp->tx_ticks; 8405 bp->rx_quick_cons_trip_int = 8406 bp->rx_quick_cons_trip; 8407 bp->rx_ticks_int = bp->rx_ticks; 8408 bp->comp_prod_trip_int = bp->comp_prod_trip; 8409 bp->com_ticks_int = bp->com_ticks; 8410 bp->cmd_ticks_int = bp->cmd_ticks; 8411 } 8412 8413 /* Disable MSI on 5706 if AMD 8132 bridge is found. 8414 * 8415 * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes 8416 * with byte enables disabled on the unused 32-bit word. This is legal 8417 * but causes problems on the AMD 8132 which will eventually stop 8418 * responding after a while. 8419 * 8420 * AMD believes this incompatibility is unique to the 5706, and 8421 * prefers to locally disable MSI rather than globally disabling it. 8422 */ 8423 if (BNX2_CHIP(bp) == BNX2_CHIP_5706 && disable_msi == 0) { 8424 struct pci_dev *amd_8132 = NULL; 8425 8426 while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD, 8427 PCI_DEVICE_ID_AMD_8132_BRIDGE, 8428 amd_8132))) { 8429 8430 if (amd_8132->revision >= 0x10 && 8431 amd_8132->revision <= 0x13) { 8432 disable_msi = 1; 8433 pci_dev_put(amd_8132); 8434 break; 8435 } 8436 } 8437 } 8438 8439 bnx2_set_default_link(bp); 8440 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX; 8441 8442 init_timer(&bp->timer); 8443 bp->timer.expires = RUN_AT(BNX2_TIMER_INTERVAL); 8444 bp->timer.data = (unsigned long) bp; 8445 bp->timer.function = bnx2_timer; 8446 8447 #ifdef BCM_CNIC 8448 if (bnx2_shmem_rd(bp, BNX2_ISCSI_INITIATOR) & BNX2_ISCSI_INITIATOR_EN) 8449 bp->cnic_eth_dev.max_iscsi_conn = 8450 (bnx2_shmem_rd(bp, BNX2_ISCSI_MAX_CONN) & 8451 BNX2_ISCSI_MAX_CONN_MASK) >> BNX2_ISCSI_MAX_CONN_SHIFT; 8452 bp->cnic_probe = bnx2_cnic_probe; 8453 #endif 8454 pci_save_state(pdev); 8455 8456 return 0; 8457 8458 err_out_unmap: 8459 if (bp->flags & BNX2_FLAG_AER_ENABLED) { 8460 pci_disable_pcie_error_reporting(pdev); 8461 bp->flags &= ~BNX2_FLAG_AER_ENABLED; 8462 } 8463 8464 pci_iounmap(pdev, bp->regview); 8465 bp->regview = NULL; 8466 8467 err_out_release: 8468 pci_release_regions(pdev); 8469 8470 err_out_disable: 8471 pci_disable_device(pdev); 8472 8473 err_out: 8474 kfree(bp->temp_stats_blk); 8475 8476 return rc; 8477 } 8478 8479 static char * 8480 bnx2_bus_string(struct bnx2 *bp, char *str) 8481 { 8482 char *s = str; 8483 8484 if (bp->flags & BNX2_FLAG_PCIE) { 8485 s += sprintf(s, "PCI Express"); 8486 } else { 8487 s += sprintf(s, "PCI"); 8488 if (bp->flags & BNX2_FLAG_PCIX) 8489 s += sprintf(s, "-X"); 8490 if (bp->flags & BNX2_FLAG_PCI_32BIT) 8491 s += sprintf(s, " 32-bit"); 8492 else 8493 s += sprintf(s, " 64-bit"); 8494 s += sprintf(s, " %dMHz", bp->bus_speed_mhz); 8495 } 8496 return str; 8497 } 8498 8499 static void 8500 bnx2_del_napi(struct bnx2 *bp) 8501 { 8502 int i; 8503 8504 for (i = 0; i < bp->irq_nvecs; i++) 8505 netif_napi_del(&bp->bnx2_napi[i].napi); 8506 } 8507 8508 static void 8509 bnx2_init_napi(struct bnx2 *bp) 8510 { 8511 int i; 8512 8513 for (i = 0; i < bp->irq_nvecs; i++) { 8514 struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; 8515 int (*poll)(struct napi_struct *, int); 8516 8517 if (i == 0) 8518 poll = bnx2_poll; 8519 else 8520 poll = bnx2_poll_msix; 8521 8522 netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll, 64); 8523 bnapi->bp = bp; 8524 } 8525 } 8526 8527 static const struct net_device_ops bnx2_netdev_ops = { 8528 .ndo_open = bnx2_open, 8529 .ndo_start_xmit = bnx2_start_xmit, 8530 .ndo_stop = bnx2_close, 8531 .ndo_get_stats64 = bnx2_get_stats64, 8532 .ndo_set_rx_mode = bnx2_set_rx_mode, 8533 .ndo_do_ioctl = bnx2_ioctl, 8534 .ndo_validate_addr = eth_validate_addr, 8535 .ndo_set_mac_address = bnx2_change_mac_addr, 8536 .ndo_change_mtu = bnx2_change_mtu, 8537 .ndo_set_features = bnx2_set_features, 8538 .ndo_tx_timeout = bnx2_tx_timeout, 8539 #ifdef CONFIG_NET_POLL_CONTROLLER 8540 .ndo_poll_controller = poll_bnx2, 8541 #endif 8542 }; 8543 8544 static int 8545 bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 8546 { 8547 static int version_printed = 0; 8548 struct net_device *dev; 8549 struct bnx2 *bp; 8550 int rc; 8551 char str[40]; 8552 8553 if (version_printed++ == 0) 8554 pr_info("%s", version); 8555 8556 /* dev zeroed in init_etherdev */ 8557 dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS); 8558 if (!dev) 8559 return -ENOMEM; 8560 8561 rc = bnx2_init_board(pdev, dev); 8562 if (rc < 0) 8563 goto err_free; 8564 8565 dev->netdev_ops = &bnx2_netdev_ops; 8566 dev->watchdog_timeo = TX_TIMEOUT; 8567 dev->ethtool_ops = &bnx2_ethtool_ops; 8568 8569 bp = netdev_priv(dev); 8570 8571 pci_set_drvdata(pdev, dev); 8572 8573 rc = bnx2_request_firmware(bp); 8574 if (rc < 0) 8575 goto error; 8576 8577 8578 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET); 8579 memcpy(dev->dev_addr, bp->mac_addr, ETH_ALEN); 8580 8581 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG | 8582 NETIF_F_TSO | NETIF_F_TSO_ECN | 8583 NETIF_F_RXHASH | NETIF_F_RXCSUM; 8584 8585 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) 8586 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6; 8587 8588 dev->vlan_features = dev->hw_features; 8589 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; 8590 dev->features |= dev->hw_features; 8591 dev->priv_flags |= IFF_UNICAST_FLT; 8592 8593 if (!(bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)) 8594 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; 8595 8596 if ((rc = register_netdev(dev))) { 8597 dev_err(&pdev->dev, "Cannot register net device\n"); 8598 goto error; 8599 } 8600 8601 netdev_info(dev, "%s (%c%d) %s found at mem %lx, IRQ %d, " 8602 "node addr %pM\n", board_info[ent->driver_data].name, 8603 ((BNX2_CHIP_ID(bp) & 0xf000) >> 12) + 'A', 8604 ((BNX2_CHIP_ID(bp) & 0x0ff0) >> 4), 8605 bnx2_bus_string(bp, str), (long)pci_resource_start(pdev, 0), 8606 pdev->irq, dev->dev_addr); 8607 8608 return 0; 8609 8610 error: 8611 bnx2_release_firmware(bp); 8612 pci_iounmap(pdev, bp->regview); 8613 pci_release_regions(pdev); 8614 pci_disable_device(pdev); 8615 err_free: 8616 bnx2_free_stats_blk(dev); 8617 free_netdev(dev); 8618 return rc; 8619 } 8620 8621 static void 8622 bnx2_remove_one(struct pci_dev *pdev) 8623 { 8624 struct net_device *dev = pci_get_drvdata(pdev); 8625 struct bnx2 *bp = netdev_priv(dev); 8626 8627 unregister_netdev(dev); 8628 8629 del_timer_sync(&bp->timer); 8630 cancel_work_sync(&bp->reset_task); 8631 8632 pci_iounmap(bp->pdev, bp->regview); 8633 8634 bnx2_free_stats_blk(dev); 8635 kfree(bp->temp_stats_blk); 8636 8637 if (bp->flags & BNX2_FLAG_AER_ENABLED) { 8638 pci_disable_pcie_error_reporting(pdev); 8639 bp->flags &= ~BNX2_FLAG_AER_ENABLED; 8640 } 8641 8642 bnx2_release_firmware(bp); 8643 8644 free_netdev(dev); 8645 8646 pci_release_regions(pdev); 8647 pci_disable_device(pdev); 8648 } 8649 8650 #ifdef CONFIG_PM_SLEEP 8651 static int 8652 bnx2_suspend(struct device *device) 8653 { 8654 struct pci_dev *pdev = to_pci_dev(device); 8655 struct net_device *dev = pci_get_drvdata(pdev); 8656 struct bnx2 *bp = netdev_priv(dev); 8657 8658 if (netif_running(dev)) { 8659 cancel_work_sync(&bp->reset_task); 8660 bnx2_netif_stop(bp, true); 8661 netif_device_detach(dev); 8662 del_timer_sync(&bp->timer); 8663 bnx2_shutdown_chip(bp); 8664 __bnx2_free_irq(bp); 8665 bnx2_free_skbs(bp); 8666 } 8667 bnx2_setup_wol(bp); 8668 return 0; 8669 } 8670 8671 static int 8672 bnx2_resume(struct device *device) 8673 { 8674 struct pci_dev *pdev = to_pci_dev(device); 8675 struct net_device *dev = pci_get_drvdata(pdev); 8676 struct bnx2 *bp = netdev_priv(dev); 8677 8678 if (!netif_running(dev)) 8679 return 0; 8680 8681 bnx2_set_power_state(bp, PCI_D0); 8682 netif_device_attach(dev); 8683 bnx2_request_irq(bp); 8684 bnx2_init_nic(bp, 1); 8685 bnx2_netif_start(bp, true); 8686 return 0; 8687 } 8688 8689 static SIMPLE_DEV_PM_OPS(bnx2_pm_ops, bnx2_suspend, bnx2_resume); 8690 #define BNX2_PM_OPS (&bnx2_pm_ops) 8691 8692 #else 8693 8694 #define BNX2_PM_OPS NULL 8695 8696 #endif /* CONFIG_PM_SLEEP */ 8697 /** 8698 * bnx2_io_error_detected - called when PCI error is detected 8699 * @pdev: Pointer to PCI device 8700 * @state: The current pci connection state 8701 * 8702 * This function is called after a PCI bus error affecting 8703 * this device has been detected. 8704 */ 8705 static pci_ers_result_t bnx2_io_error_detected(struct pci_dev *pdev, 8706 pci_channel_state_t state) 8707 { 8708 struct net_device *dev = pci_get_drvdata(pdev); 8709 struct bnx2 *bp = netdev_priv(dev); 8710 8711 rtnl_lock(); 8712 netif_device_detach(dev); 8713 8714 if (state == pci_channel_io_perm_failure) { 8715 rtnl_unlock(); 8716 return PCI_ERS_RESULT_DISCONNECT; 8717 } 8718 8719 if (netif_running(dev)) { 8720 bnx2_netif_stop(bp, true); 8721 del_timer_sync(&bp->timer); 8722 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET); 8723 } 8724 8725 pci_disable_device(pdev); 8726 rtnl_unlock(); 8727 8728 /* Request a slot slot reset. */ 8729 return PCI_ERS_RESULT_NEED_RESET; 8730 } 8731 8732 /** 8733 * bnx2_io_slot_reset - called after the pci bus has been reset. 8734 * @pdev: Pointer to PCI device 8735 * 8736 * Restart the card from scratch, as if from a cold-boot. 8737 */ 8738 static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev) 8739 { 8740 struct net_device *dev = pci_get_drvdata(pdev); 8741 struct bnx2 *bp = netdev_priv(dev); 8742 pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT; 8743 int err = 0; 8744 8745 rtnl_lock(); 8746 if (pci_enable_device(pdev)) { 8747 dev_err(&pdev->dev, 8748 "Cannot re-enable PCI device after reset\n"); 8749 } else { 8750 pci_set_master(pdev); 8751 pci_restore_state(pdev); 8752 pci_save_state(pdev); 8753 8754 if (netif_running(dev)) 8755 err = bnx2_init_nic(bp, 1); 8756 8757 if (!err) 8758 result = PCI_ERS_RESULT_RECOVERED; 8759 } 8760 8761 if (result != PCI_ERS_RESULT_RECOVERED && netif_running(dev)) { 8762 bnx2_napi_enable(bp); 8763 dev_close(dev); 8764 } 8765 rtnl_unlock(); 8766 8767 if (!(bp->flags & BNX2_FLAG_AER_ENABLED)) 8768 return result; 8769 8770 err = pci_cleanup_aer_uncorrect_error_status(pdev); 8771 if (err) { 8772 dev_err(&pdev->dev, 8773 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", 8774 err); /* non-fatal, continue */ 8775 } 8776 8777 return result; 8778 } 8779 8780 /** 8781 * bnx2_io_resume - called when traffic can start flowing again. 8782 * @pdev: Pointer to PCI device 8783 * 8784 * This callback is called when the error recovery driver tells us that 8785 * its OK to resume normal operation. 8786 */ 8787 static void bnx2_io_resume(struct pci_dev *pdev) 8788 { 8789 struct net_device *dev = pci_get_drvdata(pdev); 8790 struct bnx2 *bp = netdev_priv(dev); 8791 8792 rtnl_lock(); 8793 if (netif_running(dev)) 8794 bnx2_netif_start(bp, true); 8795 8796 netif_device_attach(dev); 8797 rtnl_unlock(); 8798 } 8799 8800 static void bnx2_shutdown(struct pci_dev *pdev) 8801 { 8802 struct net_device *dev = pci_get_drvdata(pdev); 8803 struct bnx2 *bp; 8804 8805 if (!dev) 8806 return; 8807 8808 bp = netdev_priv(dev); 8809 if (!bp) 8810 return; 8811 8812 rtnl_lock(); 8813 if (netif_running(dev)) 8814 dev_close(bp->dev); 8815 8816 if (system_state == SYSTEM_POWER_OFF) 8817 bnx2_set_power_state(bp, PCI_D3hot); 8818 8819 rtnl_unlock(); 8820 } 8821 8822 static const struct pci_error_handlers bnx2_err_handler = { 8823 .error_detected = bnx2_io_error_detected, 8824 .slot_reset = bnx2_io_slot_reset, 8825 .resume = bnx2_io_resume, 8826 }; 8827 8828 static struct pci_driver bnx2_pci_driver = { 8829 .name = DRV_MODULE_NAME, 8830 .id_table = bnx2_pci_tbl, 8831 .probe = bnx2_init_one, 8832 .remove = bnx2_remove_one, 8833 .driver.pm = BNX2_PM_OPS, 8834 .err_handler = &bnx2_err_handler, 8835 .shutdown = bnx2_shutdown, 8836 }; 8837 8838 module_pci_driver(bnx2_pci_driver); 8839