1 /* bnx2.c: QLogic bnx2 network driver. 2 * 3 * Copyright (c) 2004-2014 Broadcom Corporation 4 * Copyright (c) 2014-2015 QLogic Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 * 10 * Written by: Michael Chan (mchan@broadcom.com) 11 */ 12 13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 14 15 #include <linux/module.h> 16 #include <linux/moduleparam.h> 17 18 #include <linux/stringify.h> 19 #include <linux/kernel.h> 20 #include <linux/timer.h> 21 #include <linux/errno.h> 22 #include <linux/ioport.h> 23 #include <linux/slab.h> 24 #include <linux/vmalloc.h> 25 #include <linux/interrupt.h> 26 #include <linux/pci.h> 27 #include <linux/netdevice.h> 28 #include <linux/etherdevice.h> 29 #include <linux/skbuff.h> 30 #include <linux/dma-mapping.h> 31 #include <linux/bitops.h> 32 #include <asm/io.h> 33 #include <asm/irq.h> 34 #include <linux/delay.h> 35 #include <asm/byteorder.h> 36 #include <asm/page.h> 37 #include <linux/time.h> 38 #include <linux/ethtool.h> 39 #include <linux/mii.h> 40 #include <linux/if.h> 41 #include <linux/if_vlan.h> 42 #include <net/ip.h> 43 #include <net/tcp.h> 44 #include <net/checksum.h> 45 #include <linux/workqueue.h> 46 #include <linux/crc32.h> 47 #include <linux/prefetch.h> 48 #include <linux/cache.h> 49 #include <linux/firmware.h> 50 #include <linux/log2.h> 51 #include <linux/crash_dump.h> 52 53 #if IS_ENABLED(CONFIG_CNIC) 54 #define BCM_CNIC 1 55 #include "cnic_if.h" 56 #endif 57 #include "bnx2.h" 58 #include "bnx2_fw.h" 59 60 #define DRV_MODULE_NAME "bnx2" 61 #define FW_MIPS_FILE_06 "bnx2/bnx2-mips-06-6.2.3.fw" 62 #define FW_RV2P_FILE_06 "bnx2/bnx2-rv2p-06-6.0.15.fw" 63 #define FW_MIPS_FILE_09 "bnx2/bnx2-mips-09-6.2.1b.fw" 64 #define FW_RV2P_FILE_09_Ax "bnx2/bnx2-rv2p-09ax-6.0.17.fw" 65 #define FW_RV2P_FILE_09 "bnx2/bnx2-rv2p-09-6.0.17.fw" 66 67 #define RUN_AT(x) (jiffies + (x)) 68 69 /* Time in jiffies before concluding the transmitter is hung. */ 70 #define TX_TIMEOUT (5*HZ) 71 72 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>"); 73 MODULE_DESCRIPTION("QLogic BCM5706/5708/5709/5716 Driver"); 74 MODULE_LICENSE("GPL"); 75 MODULE_FIRMWARE(FW_MIPS_FILE_06); 76 MODULE_FIRMWARE(FW_RV2P_FILE_06); 77 MODULE_FIRMWARE(FW_MIPS_FILE_09); 78 MODULE_FIRMWARE(FW_RV2P_FILE_09); 79 MODULE_FIRMWARE(FW_RV2P_FILE_09_Ax); 80 81 static int disable_msi = 0; 82 83 module_param(disable_msi, int, 0444); 84 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)"); 85 86 typedef enum { 87 BCM5706 = 0, 88 NC370T, 89 NC370I, 90 BCM5706S, 91 NC370F, 92 BCM5708, 93 BCM5708S, 94 BCM5709, 95 BCM5709S, 96 BCM5716, 97 BCM5716S, 98 } board_t; 99 100 /* indexed by board_t, above */ 101 static struct { 102 char *name; 103 } board_info[] = { 104 { "Broadcom NetXtreme II BCM5706 1000Base-T" }, 105 { "HP NC370T Multifunction Gigabit Server Adapter" }, 106 { "HP NC370i Multifunction Gigabit Server Adapter" }, 107 { "Broadcom NetXtreme II BCM5706 1000Base-SX" }, 108 { "HP NC370F Multifunction Gigabit Server Adapter" }, 109 { "Broadcom NetXtreme II BCM5708 1000Base-T" }, 110 { "Broadcom NetXtreme II BCM5708 1000Base-SX" }, 111 { "Broadcom NetXtreme II BCM5709 1000Base-T" }, 112 { "Broadcom NetXtreme II BCM5709 1000Base-SX" }, 113 { "Broadcom NetXtreme II BCM5716 1000Base-T" }, 114 { "Broadcom NetXtreme II BCM5716 1000Base-SX" }, 115 }; 116 117 static const struct pci_device_id bnx2_pci_tbl[] = { 118 { 119 PCI_VDEVICE_SUB(BROADCOM, PCI_DEVICE_ID_NX2_5706, 120 PCI_VENDOR_ID_HP, 0x3101), 121 .driver_data = NC370T, 122 }, { 123 PCI_VDEVICE_SUB(BROADCOM, PCI_DEVICE_ID_NX2_5706, 124 PCI_VENDOR_ID_HP, 0x3106), 125 .driver_data = NC370I, 126 }, { 127 PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_5706), 128 .driver_data = BCM5706, 129 }, { 130 PCI_VDEVICE_SUB(BROADCOM, PCI_DEVICE_ID_NX2_5708, 131 PCI_ANY_ID, PCI_ANY_ID), 132 .driver_data = BCM5708, 133 }, { 134 PCI_VDEVICE_SUB(BROADCOM, PCI_DEVICE_ID_NX2_5706S, 135 PCI_VENDOR_ID_HP, 0x3102), 136 .driver_data = NC370F, 137 }, { 138 PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_5706S), 139 .driver_data = BCM5706S, 140 }, { 141 PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_5708S), 142 .driver_data = BCM5708S, 143 }, { 144 PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_5709), 145 .driver_data = BCM5709, 146 }, { 147 PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_5709S), 148 .driver_data = BCM5709S, 149 }, { 150 PCI_VDEVICE(BROADCOM, 0x163b), 151 .driver_data = BCM5716, 152 }, { 153 PCI_VDEVICE(BROADCOM, 0x163c), 154 .driver_data = BCM5716S, 155 }, 156 { } 157 }; 158 159 static const struct flash_spec flash_table[] = 160 { 161 #define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE) 162 #define NONBUFFERED_FLAGS (BNX2_NV_WREN) 163 /* Slow EEPROM */ 164 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, 165 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 166 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 167 "EEPROM - slow"}, 168 /* Expansion entry 0001 */ 169 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, 170 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 171 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 172 "Entry 0001"}, 173 /* Saifun SA25F010 (non-buffered flash) */ 174 /* strap, cfg1, & write1 need updates */ 175 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, 176 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 177 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, 178 "Non-buffered flash (128kB)"}, 179 /* Saifun SA25F020 (non-buffered flash) */ 180 /* strap, cfg1, & write1 need updates */ 181 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, 182 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 183 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, 184 "Non-buffered flash (256kB)"}, 185 /* Expansion entry 0100 */ 186 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, 187 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 188 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 189 "Entry 0100"}, 190 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ 191 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, 192 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 193 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, 194 "Entry 0101: ST M45PE10 (128kB non-buffered)"}, 195 /* Entry 0110: ST M45PE20 (non-buffered flash)*/ 196 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, 197 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 198 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, 199 "Entry 0110: ST M45PE20 (256kB non-buffered)"}, 200 /* Saifun SA25F005 (non-buffered flash) */ 201 /* strap, cfg1, & write1 need updates */ 202 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, 203 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 204 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, 205 "Non-buffered flash (64kB)"}, 206 /* Fast EEPROM */ 207 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, 208 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 209 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 210 "EEPROM - fast"}, 211 /* Expansion entry 1001 */ 212 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, 213 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 214 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 215 "Entry 1001"}, 216 /* Expansion entry 1010 */ 217 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, 218 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 219 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 220 "Entry 1010"}, 221 /* ATMEL AT45DB011B (buffered flash) */ 222 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, 223 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 224 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, 225 "Buffered flash (128kB)"}, 226 /* Expansion entry 1100 */ 227 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, 228 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 229 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 230 "Entry 1100"}, 231 /* Expansion entry 1101 */ 232 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, 233 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 234 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 235 "Entry 1101"}, 236 /* Ateml Expansion entry 1110 */ 237 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, 238 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 239 BUFFERED_FLASH_BYTE_ADDR_MASK, 0, 240 "Entry 1110 (Atmel)"}, 241 /* ATMEL AT45DB021B (buffered flash) */ 242 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, 243 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 244 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, 245 "Buffered flash (256kB)"}, 246 }; 247 248 static const struct flash_spec flash_5709 = { 249 .flags = BNX2_NV_BUFFERED, 250 .page_bits = BCM5709_FLASH_PAGE_BITS, 251 .page_size = BCM5709_FLASH_PAGE_SIZE, 252 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK, 253 .total_size = BUFFERED_FLASH_TOTAL_SIZE*2, 254 .name = "5709 Buffered flash (256kB)", 255 }; 256 257 MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl); 258 259 static void bnx2_init_napi(struct bnx2 *bp); 260 static void bnx2_del_napi(struct bnx2 *bp); 261 262 static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr) 263 { 264 u32 diff; 265 266 /* The ring uses 256 indices for 255 entries, one of them 267 * needs to be skipped. 268 */ 269 diff = READ_ONCE(txr->tx_prod) - READ_ONCE(txr->tx_cons); 270 if (unlikely(diff >= BNX2_TX_DESC_CNT)) { 271 diff &= 0xffff; 272 if (diff == BNX2_TX_DESC_CNT) 273 diff = BNX2_MAX_TX_DESC_CNT; 274 } 275 return bp->tx_ring_size - diff; 276 } 277 278 static u32 279 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset) 280 { 281 unsigned long flags; 282 u32 val; 283 284 spin_lock_irqsave(&bp->indirect_lock, flags); 285 BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset); 286 val = BNX2_RD(bp, BNX2_PCICFG_REG_WINDOW); 287 spin_unlock_irqrestore(&bp->indirect_lock, flags); 288 return val; 289 } 290 291 static void 292 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val) 293 { 294 unsigned long flags; 295 296 spin_lock_irqsave(&bp->indirect_lock, flags); 297 BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset); 298 BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW, val); 299 spin_unlock_irqrestore(&bp->indirect_lock, flags); 300 } 301 302 static void 303 bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val) 304 { 305 bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val); 306 } 307 308 static u32 309 bnx2_shmem_rd(struct bnx2 *bp, u32 offset) 310 { 311 return bnx2_reg_rd_ind(bp, bp->shmem_base + offset); 312 } 313 314 static void 315 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val) 316 { 317 unsigned long flags; 318 319 offset += cid_addr; 320 spin_lock_irqsave(&bp->indirect_lock, flags); 321 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { 322 int i; 323 324 BNX2_WR(bp, BNX2_CTX_CTX_DATA, val); 325 BNX2_WR(bp, BNX2_CTX_CTX_CTRL, 326 offset | BNX2_CTX_CTX_CTRL_WRITE_REQ); 327 for (i = 0; i < 5; i++) { 328 val = BNX2_RD(bp, BNX2_CTX_CTX_CTRL); 329 if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0) 330 break; 331 udelay(5); 332 } 333 } else { 334 BNX2_WR(bp, BNX2_CTX_DATA_ADR, offset); 335 BNX2_WR(bp, BNX2_CTX_DATA, val); 336 } 337 spin_unlock_irqrestore(&bp->indirect_lock, flags); 338 } 339 340 #ifdef BCM_CNIC 341 static int 342 bnx2_drv_ctl(struct net_device *dev, struct drv_ctl_info *info) 343 { 344 struct bnx2 *bp = netdev_priv(dev); 345 struct drv_ctl_io *io = &info->data.io; 346 347 switch (info->cmd) { 348 case DRV_CTL_IO_WR_CMD: 349 bnx2_reg_wr_ind(bp, io->offset, io->data); 350 break; 351 case DRV_CTL_IO_RD_CMD: 352 io->data = bnx2_reg_rd_ind(bp, io->offset); 353 break; 354 case DRV_CTL_CTX_WR_CMD: 355 bnx2_ctx_wr(bp, io->cid_addr, io->offset, io->data); 356 break; 357 default: 358 return -EINVAL; 359 } 360 return 0; 361 } 362 363 static void bnx2_setup_cnic_irq_info(struct bnx2 *bp) 364 { 365 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 366 struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; 367 int sb_id; 368 369 if (bp->flags & BNX2_FLAG_USING_MSIX) { 370 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX; 371 bnapi->cnic_present = 0; 372 sb_id = bp->irq_nvecs; 373 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX; 374 } else { 375 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX; 376 bnapi->cnic_tag = bnapi->last_status_idx; 377 bnapi->cnic_present = 1; 378 sb_id = 0; 379 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX; 380 } 381 382 cp->irq_arr[0].vector = bp->irq_tbl[sb_id].vector; 383 cp->irq_arr[0].status_blk = (void *) 384 ((unsigned long) bnapi->status_blk.msi + 385 (BNX2_SBLK_MSIX_ALIGN_SIZE * sb_id)); 386 cp->irq_arr[0].status_blk_map = bp->status_blk_mapping; 387 cp->irq_arr[0].status_blk_num = sb_id; 388 cp->num_irq = 1; 389 } 390 391 static int bnx2_register_cnic(struct net_device *dev, struct cnic_ops *ops, 392 void *data) 393 { 394 struct bnx2 *bp = netdev_priv(dev); 395 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 396 397 if (!ops) 398 return -EINVAL; 399 400 if (cp->drv_state & CNIC_DRV_STATE_REGD) 401 return -EBUSY; 402 403 if (!bnx2_reg_rd_ind(bp, BNX2_FW_MAX_ISCSI_CONN)) 404 return -ENODEV; 405 406 bp->cnic_data = data; 407 rcu_assign_pointer(bp->cnic_ops, ops); 408 409 cp->num_irq = 0; 410 cp->drv_state = CNIC_DRV_STATE_REGD; 411 412 bnx2_setup_cnic_irq_info(bp); 413 414 return 0; 415 } 416 417 static int bnx2_unregister_cnic(struct net_device *dev) 418 { 419 struct bnx2 *bp = netdev_priv(dev); 420 struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; 421 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 422 423 mutex_lock(&bp->cnic_lock); 424 cp->drv_state = 0; 425 bnapi->cnic_present = 0; 426 RCU_INIT_POINTER(bp->cnic_ops, NULL); 427 mutex_unlock(&bp->cnic_lock); 428 synchronize_rcu(); 429 return 0; 430 } 431 432 static struct cnic_eth_dev *bnx2_cnic_probe(struct net_device *dev) 433 { 434 struct bnx2 *bp = netdev_priv(dev); 435 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 436 437 if (!cp->max_iscsi_conn) 438 return NULL; 439 440 cp->drv_owner = THIS_MODULE; 441 cp->chip_id = bp->chip_id; 442 cp->pdev = bp->pdev; 443 cp->io_base = bp->regview; 444 cp->drv_ctl = bnx2_drv_ctl; 445 cp->drv_register_cnic = bnx2_register_cnic; 446 cp->drv_unregister_cnic = bnx2_unregister_cnic; 447 448 return cp; 449 } 450 451 static void 452 bnx2_cnic_stop(struct bnx2 *bp) 453 { 454 struct cnic_ops *c_ops; 455 struct cnic_ctl_info info; 456 457 mutex_lock(&bp->cnic_lock); 458 c_ops = rcu_dereference_protected(bp->cnic_ops, 459 lockdep_is_held(&bp->cnic_lock)); 460 if (c_ops) { 461 info.cmd = CNIC_CTL_STOP_CMD; 462 c_ops->cnic_ctl(bp->cnic_data, &info); 463 } 464 mutex_unlock(&bp->cnic_lock); 465 } 466 467 static void 468 bnx2_cnic_start(struct bnx2 *bp) 469 { 470 struct cnic_ops *c_ops; 471 struct cnic_ctl_info info; 472 473 mutex_lock(&bp->cnic_lock); 474 c_ops = rcu_dereference_protected(bp->cnic_ops, 475 lockdep_is_held(&bp->cnic_lock)); 476 if (c_ops) { 477 if (!(bp->flags & BNX2_FLAG_USING_MSIX)) { 478 struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; 479 480 bnapi->cnic_tag = bnapi->last_status_idx; 481 } 482 info.cmd = CNIC_CTL_START_CMD; 483 c_ops->cnic_ctl(bp->cnic_data, &info); 484 } 485 mutex_unlock(&bp->cnic_lock); 486 } 487 488 #else 489 490 static void 491 bnx2_cnic_stop(struct bnx2 *bp) 492 { 493 } 494 495 static void 496 bnx2_cnic_start(struct bnx2 *bp) 497 { 498 } 499 500 #endif 501 502 static int 503 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val) 504 { 505 u32 val1; 506 int i, ret; 507 508 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) { 509 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); 510 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL; 511 512 BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1); 513 BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); 514 515 udelay(40); 516 } 517 518 val1 = (bp->phy_addr << 21) | (reg << 16) | 519 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT | 520 BNX2_EMAC_MDIO_COMM_START_BUSY; 521 BNX2_WR(bp, BNX2_EMAC_MDIO_COMM, val1); 522 523 for (i = 0; i < 50; i++) { 524 udelay(10); 525 526 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM); 527 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) { 528 udelay(5); 529 530 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM); 531 val1 &= BNX2_EMAC_MDIO_COMM_DATA; 532 533 break; 534 } 535 } 536 537 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) { 538 *val = 0x0; 539 ret = -EBUSY; 540 } 541 else { 542 *val = val1; 543 ret = 0; 544 } 545 546 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) { 547 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); 548 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL; 549 550 BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1); 551 BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); 552 553 udelay(40); 554 } 555 556 return ret; 557 } 558 559 static int 560 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val) 561 { 562 u32 val1; 563 int i, ret; 564 565 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) { 566 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); 567 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL; 568 569 BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1); 570 BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); 571 572 udelay(40); 573 } 574 575 val1 = (bp->phy_addr << 21) | (reg << 16) | val | 576 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE | 577 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT; 578 BNX2_WR(bp, BNX2_EMAC_MDIO_COMM, val1); 579 580 for (i = 0; i < 50; i++) { 581 udelay(10); 582 583 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM); 584 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) { 585 udelay(5); 586 break; 587 } 588 } 589 590 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) 591 ret = -EBUSY; 592 else 593 ret = 0; 594 595 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) { 596 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); 597 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL; 598 599 BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1); 600 BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); 601 602 udelay(40); 603 } 604 605 return ret; 606 } 607 608 static void 609 bnx2_disable_int(struct bnx2 *bp) 610 { 611 int i; 612 struct bnx2_napi *bnapi; 613 614 for (i = 0; i < bp->irq_nvecs; i++) { 615 bnapi = &bp->bnx2_napi[i]; 616 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num | 617 BNX2_PCICFG_INT_ACK_CMD_MASK_INT); 618 } 619 BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD); 620 } 621 622 static void 623 bnx2_enable_int(struct bnx2 *bp) 624 { 625 int i; 626 struct bnx2_napi *bnapi; 627 628 for (i = 0; i < bp->irq_nvecs; i++) { 629 bnapi = &bp->bnx2_napi[i]; 630 631 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num | 632 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | 633 BNX2_PCICFG_INT_ACK_CMD_MASK_INT | 634 bnapi->last_status_idx); 635 636 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num | 637 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | 638 bnapi->last_status_idx); 639 } 640 BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW); 641 } 642 643 static void 644 bnx2_disable_int_sync(struct bnx2 *bp) 645 { 646 int i; 647 648 atomic_inc(&bp->intr_sem); 649 if (!netif_running(bp->dev)) 650 return; 651 652 bnx2_disable_int(bp); 653 for (i = 0; i < bp->irq_nvecs; i++) 654 synchronize_irq(bp->irq_tbl[i].vector); 655 } 656 657 static void 658 bnx2_napi_disable(struct bnx2 *bp) 659 { 660 int i; 661 662 for (i = 0; i < bp->irq_nvecs; i++) 663 napi_disable(&bp->bnx2_napi[i].napi); 664 } 665 666 static void 667 bnx2_napi_enable(struct bnx2 *bp) 668 { 669 int i; 670 671 for (i = 0; i < bp->irq_nvecs; i++) 672 napi_enable(&bp->bnx2_napi[i].napi); 673 } 674 675 static void 676 bnx2_netif_stop(struct bnx2 *bp, bool stop_cnic) 677 { 678 if (stop_cnic) 679 bnx2_cnic_stop(bp); 680 if (netif_running(bp->dev)) { 681 bnx2_napi_disable(bp); 682 netif_tx_disable(bp->dev); 683 } 684 bnx2_disable_int_sync(bp); 685 netif_carrier_off(bp->dev); /* prevent tx timeout */ 686 } 687 688 static void 689 bnx2_netif_start(struct bnx2 *bp, bool start_cnic) 690 { 691 if (atomic_dec_and_test(&bp->intr_sem)) { 692 if (netif_running(bp->dev)) { 693 netif_tx_wake_all_queues(bp->dev); 694 spin_lock_bh(&bp->phy_lock); 695 if (bp->link_up) 696 netif_carrier_on(bp->dev); 697 spin_unlock_bh(&bp->phy_lock); 698 bnx2_napi_enable(bp); 699 bnx2_enable_int(bp); 700 if (start_cnic) 701 bnx2_cnic_start(bp); 702 } 703 } 704 } 705 706 static void 707 bnx2_free_tx_mem(struct bnx2 *bp) 708 { 709 int i; 710 711 for (i = 0; i < bp->num_tx_rings; i++) { 712 struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; 713 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; 714 715 if (txr->tx_desc_ring) { 716 dma_free_coherent(&bp->pdev->dev, TXBD_RING_SIZE, 717 txr->tx_desc_ring, 718 txr->tx_desc_mapping); 719 txr->tx_desc_ring = NULL; 720 } 721 kfree(txr->tx_buf_ring); 722 txr->tx_buf_ring = NULL; 723 } 724 } 725 726 static void 727 bnx2_free_rx_mem(struct bnx2 *bp) 728 { 729 int i; 730 731 for (i = 0; i < bp->num_rx_rings; i++) { 732 struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; 733 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; 734 int j; 735 736 for (j = 0; j < bp->rx_max_ring; j++) { 737 if (rxr->rx_desc_ring[j]) 738 dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE, 739 rxr->rx_desc_ring[j], 740 rxr->rx_desc_mapping[j]); 741 rxr->rx_desc_ring[j] = NULL; 742 } 743 vfree(rxr->rx_buf_ring); 744 rxr->rx_buf_ring = NULL; 745 746 for (j = 0; j < bp->rx_max_pg_ring; j++) { 747 if (rxr->rx_pg_desc_ring[j]) 748 dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE, 749 rxr->rx_pg_desc_ring[j], 750 rxr->rx_pg_desc_mapping[j]); 751 rxr->rx_pg_desc_ring[j] = NULL; 752 } 753 vfree(rxr->rx_pg_ring); 754 rxr->rx_pg_ring = NULL; 755 } 756 } 757 758 static int 759 bnx2_alloc_tx_mem(struct bnx2 *bp) 760 { 761 int i; 762 763 for (i = 0; i < bp->num_tx_rings; i++) { 764 struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; 765 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; 766 767 txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL); 768 if (!txr->tx_buf_ring) 769 return -ENOMEM; 770 771 txr->tx_desc_ring = 772 dma_alloc_coherent(&bp->pdev->dev, TXBD_RING_SIZE, 773 &txr->tx_desc_mapping, GFP_KERNEL); 774 if (!txr->tx_desc_ring) 775 return -ENOMEM; 776 } 777 return 0; 778 } 779 780 static int 781 bnx2_alloc_rx_mem(struct bnx2 *bp) 782 { 783 int i; 784 785 for (i = 0; i < bp->num_rx_rings; i++) { 786 struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; 787 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; 788 int j; 789 790 rxr->rx_buf_ring = 791 vzalloc(array_size(SW_RXBD_RING_SIZE, bp->rx_max_ring)); 792 if (!rxr->rx_buf_ring) 793 return -ENOMEM; 794 795 for (j = 0; j < bp->rx_max_ring; j++) { 796 rxr->rx_desc_ring[j] = 797 dma_alloc_coherent(&bp->pdev->dev, 798 RXBD_RING_SIZE, 799 &rxr->rx_desc_mapping[j], 800 GFP_KERNEL); 801 if (!rxr->rx_desc_ring[j]) 802 return -ENOMEM; 803 804 } 805 806 if (bp->rx_pg_ring_size) { 807 rxr->rx_pg_ring = 808 vzalloc(array_size(SW_RXPG_RING_SIZE, 809 bp->rx_max_pg_ring)); 810 if (!rxr->rx_pg_ring) 811 return -ENOMEM; 812 813 } 814 815 for (j = 0; j < bp->rx_max_pg_ring; j++) { 816 rxr->rx_pg_desc_ring[j] = 817 dma_alloc_coherent(&bp->pdev->dev, 818 RXBD_RING_SIZE, 819 &rxr->rx_pg_desc_mapping[j], 820 GFP_KERNEL); 821 if (!rxr->rx_pg_desc_ring[j]) 822 return -ENOMEM; 823 824 } 825 } 826 return 0; 827 } 828 829 static void 830 bnx2_free_stats_blk(struct net_device *dev) 831 { 832 struct bnx2 *bp = netdev_priv(dev); 833 834 if (bp->status_blk) { 835 dma_free_coherent(&bp->pdev->dev, bp->status_stats_size, 836 bp->status_blk, 837 bp->status_blk_mapping); 838 bp->status_blk = NULL; 839 bp->stats_blk = NULL; 840 } 841 } 842 843 static int 844 bnx2_alloc_stats_blk(struct net_device *dev) 845 { 846 int status_blk_size; 847 void *status_blk; 848 struct bnx2 *bp = netdev_priv(dev); 849 850 /* Combine status and statistics blocks into one allocation. */ 851 status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block)); 852 if (bp->flags & BNX2_FLAG_MSIX_CAP) 853 status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC * 854 BNX2_SBLK_MSIX_ALIGN_SIZE); 855 bp->status_stats_size = status_blk_size + 856 sizeof(struct statistics_block); 857 status_blk = dma_alloc_coherent(&bp->pdev->dev, bp->status_stats_size, 858 &bp->status_blk_mapping, GFP_KERNEL); 859 if (!status_blk) 860 return -ENOMEM; 861 862 bp->status_blk = status_blk; 863 bp->stats_blk = status_blk + status_blk_size; 864 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size; 865 866 return 0; 867 } 868 869 static void 870 bnx2_free_mem(struct bnx2 *bp) 871 { 872 int i; 873 struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; 874 875 bnx2_free_tx_mem(bp); 876 bnx2_free_rx_mem(bp); 877 878 for (i = 0; i < bp->ctx_pages; i++) { 879 if (bp->ctx_blk[i]) { 880 dma_free_coherent(&bp->pdev->dev, BNX2_PAGE_SIZE, 881 bp->ctx_blk[i], 882 bp->ctx_blk_mapping[i]); 883 bp->ctx_blk[i] = NULL; 884 } 885 } 886 887 if (bnapi->status_blk.msi) 888 bnapi->status_blk.msi = NULL; 889 } 890 891 static int 892 bnx2_alloc_mem(struct bnx2 *bp) 893 { 894 int i, err; 895 struct bnx2_napi *bnapi; 896 897 bnapi = &bp->bnx2_napi[0]; 898 bnapi->status_blk.msi = bp->status_blk; 899 bnapi->hw_tx_cons_ptr = 900 &bnapi->status_blk.msi->status_tx_quick_consumer_index0; 901 bnapi->hw_rx_cons_ptr = 902 &bnapi->status_blk.msi->status_rx_quick_consumer_index0; 903 if (bp->flags & BNX2_FLAG_MSIX_CAP) { 904 for (i = 1; i < bp->irq_nvecs; i++) { 905 struct status_block_msix *sblk; 906 907 bnapi = &bp->bnx2_napi[i]; 908 909 sblk = (bp->status_blk + BNX2_SBLK_MSIX_ALIGN_SIZE * i); 910 bnapi->status_blk.msix = sblk; 911 bnapi->hw_tx_cons_ptr = 912 &sblk->status_tx_quick_consumer_index; 913 bnapi->hw_rx_cons_ptr = 914 &sblk->status_rx_quick_consumer_index; 915 bnapi->int_num = i << 24; 916 } 917 } 918 919 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { 920 bp->ctx_pages = 0x2000 / BNX2_PAGE_SIZE; 921 if (bp->ctx_pages == 0) 922 bp->ctx_pages = 1; 923 for (i = 0; i < bp->ctx_pages; i++) { 924 bp->ctx_blk[i] = dma_alloc_coherent(&bp->pdev->dev, 925 BNX2_PAGE_SIZE, 926 &bp->ctx_blk_mapping[i], 927 GFP_KERNEL); 928 if (!bp->ctx_blk[i]) 929 goto alloc_mem_err; 930 } 931 } 932 933 err = bnx2_alloc_rx_mem(bp); 934 if (err) 935 goto alloc_mem_err; 936 937 err = bnx2_alloc_tx_mem(bp); 938 if (err) 939 goto alloc_mem_err; 940 941 return 0; 942 943 alloc_mem_err: 944 bnx2_free_mem(bp); 945 return -ENOMEM; 946 } 947 948 static void 949 bnx2_report_fw_link(struct bnx2 *bp) 950 { 951 u32 fw_link_status = 0; 952 953 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) 954 return; 955 956 if (bp->link_up) { 957 u32 bmsr; 958 959 switch (bp->line_speed) { 960 case SPEED_10: 961 if (bp->duplex == DUPLEX_HALF) 962 fw_link_status = BNX2_LINK_STATUS_10HALF; 963 else 964 fw_link_status = BNX2_LINK_STATUS_10FULL; 965 break; 966 case SPEED_100: 967 if (bp->duplex == DUPLEX_HALF) 968 fw_link_status = BNX2_LINK_STATUS_100HALF; 969 else 970 fw_link_status = BNX2_LINK_STATUS_100FULL; 971 break; 972 case SPEED_1000: 973 if (bp->duplex == DUPLEX_HALF) 974 fw_link_status = BNX2_LINK_STATUS_1000HALF; 975 else 976 fw_link_status = BNX2_LINK_STATUS_1000FULL; 977 break; 978 case SPEED_2500: 979 if (bp->duplex == DUPLEX_HALF) 980 fw_link_status = BNX2_LINK_STATUS_2500HALF; 981 else 982 fw_link_status = BNX2_LINK_STATUS_2500FULL; 983 break; 984 } 985 986 fw_link_status |= BNX2_LINK_STATUS_LINK_UP; 987 988 if (bp->autoneg) { 989 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED; 990 991 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); 992 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); 993 994 if (!(bmsr & BMSR_ANEGCOMPLETE) || 995 bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) 996 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET; 997 else 998 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE; 999 } 1000 } 1001 else 1002 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN; 1003 1004 bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status); 1005 } 1006 1007 static char * 1008 bnx2_xceiver_str(struct bnx2 *bp) 1009 { 1010 return (bp->phy_port == PORT_FIBRE) ? "SerDes" : 1011 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" : 1012 "Copper"); 1013 } 1014 1015 static void 1016 bnx2_report_link(struct bnx2 *bp) 1017 { 1018 if (bp->link_up) { 1019 netif_carrier_on(bp->dev); 1020 netdev_info(bp->dev, "NIC %s Link is Up, %d Mbps %s duplex", 1021 bnx2_xceiver_str(bp), 1022 bp->line_speed, 1023 bp->duplex == DUPLEX_FULL ? "full" : "half"); 1024 1025 if (bp->flow_ctrl) { 1026 if (bp->flow_ctrl & FLOW_CTRL_RX) { 1027 pr_cont(", receive "); 1028 if (bp->flow_ctrl & FLOW_CTRL_TX) 1029 pr_cont("& transmit "); 1030 } 1031 else { 1032 pr_cont(", transmit "); 1033 } 1034 pr_cont("flow control ON"); 1035 } 1036 pr_cont("\n"); 1037 } else { 1038 netif_carrier_off(bp->dev); 1039 netdev_err(bp->dev, "NIC %s Link is Down\n", 1040 bnx2_xceiver_str(bp)); 1041 } 1042 1043 bnx2_report_fw_link(bp); 1044 } 1045 1046 static void 1047 bnx2_resolve_flow_ctrl(struct bnx2 *bp) 1048 { 1049 u32 local_adv, remote_adv; 1050 1051 bp->flow_ctrl = 0; 1052 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) != 1053 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) { 1054 1055 if (bp->duplex == DUPLEX_FULL) { 1056 bp->flow_ctrl = bp->req_flow_ctrl; 1057 } 1058 return; 1059 } 1060 1061 if (bp->duplex != DUPLEX_FULL) { 1062 return; 1063 } 1064 1065 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && 1066 (BNX2_CHIP(bp) == BNX2_CHIP_5708)) { 1067 u32 val; 1068 1069 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val); 1070 if (val & BCM5708S_1000X_STAT1_TX_PAUSE) 1071 bp->flow_ctrl |= FLOW_CTRL_TX; 1072 if (val & BCM5708S_1000X_STAT1_RX_PAUSE) 1073 bp->flow_ctrl |= FLOW_CTRL_RX; 1074 return; 1075 } 1076 1077 bnx2_read_phy(bp, bp->mii_adv, &local_adv); 1078 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv); 1079 1080 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { 1081 u32 new_local_adv = 0; 1082 u32 new_remote_adv = 0; 1083 1084 if (local_adv & ADVERTISE_1000XPAUSE) 1085 new_local_adv |= ADVERTISE_PAUSE_CAP; 1086 if (local_adv & ADVERTISE_1000XPSE_ASYM) 1087 new_local_adv |= ADVERTISE_PAUSE_ASYM; 1088 if (remote_adv & ADVERTISE_1000XPAUSE) 1089 new_remote_adv |= ADVERTISE_PAUSE_CAP; 1090 if (remote_adv & ADVERTISE_1000XPSE_ASYM) 1091 new_remote_adv |= ADVERTISE_PAUSE_ASYM; 1092 1093 local_adv = new_local_adv; 1094 remote_adv = new_remote_adv; 1095 } 1096 1097 /* See Table 28B-3 of 802.3ab-1999 spec. */ 1098 if (local_adv & ADVERTISE_PAUSE_CAP) { 1099 if(local_adv & ADVERTISE_PAUSE_ASYM) { 1100 if (remote_adv & ADVERTISE_PAUSE_CAP) { 1101 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; 1102 } 1103 else if (remote_adv & ADVERTISE_PAUSE_ASYM) { 1104 bp->flow_ctrl = FLOW_CTRL_RX; 1105 } 1106 } 1107 else { 1108 if (remote_adv & ADVERTISE_PAUSE_CAP) { 1109 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; 1110 } 1111 } 1112 } 1113 else if (local_adv & ADVERTISE_PAUSE_ASYM) { 1114 if ((remote_adv & ADVERTISE_PAUSE_CAP) && 1115 (remote_adv & ADVERTISE_PAUSE_ASYM)) { 1116 1117 bp->flow_ctrl = FLOW_CTRL_TX; 1118 } 1119 } 1120 } 1121 1122 static int 1123 bnx2_5709s_linkup(struct bnx2 *bp) 1124 { 1125 u32 val, speed; 1126 1127 bp->link_up = 1; 1128 1129 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS); 1130 bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val); 1131 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0); 1132 1133 if ((bp->autoneg & AUTONEG_SPEED) == 0) { 1134 bp->line_speed = bp->req_line_speed; 1135 bp->duplex = bp->req_duplex; 1136 return 0; 1137 } 1138 speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK; 1139 switch (speed) { 1140 case MII_BNX2_GP_TOP_AN_SPEED_10: 1141 bp->line_speed = SPEED_10; 1142 break; 1143 case MII_BNX2_GP_TOP_AN_SPEED_100: 1144 bp->line_speed = SPEED_100; 1145 break; 1146 case MII_BNX2_GP_TOP_AN_SPEED_1G: 1147 case MII_BNX2_GP_TOP_AN_SPEED_1GKV: 1148 bp->line_speed = SPEED_1000; 1149 break; 1150 case MII_BNX2_GP_TOP_AN_SPEED_2_5G: 1151 bp->line_speed = SPEED_2500; 1152 break; 1153 } 1154 if (val & MII_BNX2_GP_TOP_AN_FD) 1155 bp->duplex = DUPLEX_FULL; 1156 else 1157 bp->duplex = DUPLEX_HALF; 1158 return 0; 1159 } 1160 1161 static int 1162 bnx2_5708s_linkup(struct bnx2 *bp) 1163 { 1164 u32 val; 1165 1166 bp->link_up = 1; 1167 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val); 1168 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) { 1169 case BCM5708S_1000X_STAT1_SPEED_10: 1170 bp->line_speed = SPEED_10; 1171 break; 1172 case BCM5708S_1000X_STAT1_SPEED_100: 1173 bp->line_speed = SPEED_100; 1174 break; 1175 case BCM5708S_1000X_STAT1_SPEED_1G: 1176 bp->line_speed = SPEED_1000; 1177 break; 1178 case BCM5708S_1000X_STAT1_SPEED_2G5: 1179 bp->line_speed = SPEED_2500; 1180 break; 1181 } 1182 if (val & BCM5708S_1000X_STAT1_FD) 1183 bp->duplex = DUPLEX_FULL; 1184 else 1185 bp->duplex = DUPLEX_HALF; 1186 1187 return 0; 1188 } 1189 1190 static int 1191 bnx2_5706s_linkup(struct bnx2 *bp) 1192 { 1193 u32 bmcr, local_adv, remote_adv, common; 1194 1195 bp->link_up = 1; 1196 bp->line_speed = SPEED_1000; 1197 1198 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); 1199 if (bmcr & BMCR_FULLDPLX) { 1200 bp->duplex = DUPLEX_FULL; 1201 } 1202 else { 1203 bp->duplex = DUPLEX_HALF; 1204 } 1205 1206 if (!(bmcr & BMCR_ANENABLE)) { 1207 return 0; 1208 } 1209 1210 bnx2_read_phy(bp, bp->mii_adv, &local_adv); 1211 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv); 1212 1213 common = local_adv & remote_adv; 1214 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) { 1215 1216 if (common & ADVERTISE_1000XFULL) { 1217 bp->duplex = DUPLEX_FULL; 1218 } 1219 else { 1220 bp->duplex = DUPLEX_HALF; 1221 } 1222 } 1223 1224 return 0; 1225 } 1226 1227 static int 1228 bnx2_copper_linkup(struct bnx2 *bp) 1229 { 1230 u32 bmcr; 1231 1232 bp->phy_flags &= ~BNX2_PHY_FLAG_MDIX; 1233 1234 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); 1235 if (bmcr & BMCR_ANENABLE) { 1236 u32 local_adv, remote_adv, common; 1237 1238 bnx2_read_phy(bp, MII_CTRL1000, &local_adv); 1239 bnx2_read_phy(bp, MII_STAT1000, &remote_adv); 1240 1241 common = local_adv & (remote_adv >> 2); 1242 if (common & ADVERTISE_1000FULL) { 1243 bp->line_speed = SPEED_1000; 1244 bp->duplex = DUPLEX_FULL; 1245 } 1246 else if (common & ADVERTISE_1000HALF) { 1247 bp->line_speed = SPEED_1000; 1248 bp->duplex = DUPLEX_HALF; 1249 } 1250 else { 1251 bnx2_read_phy(bp, bp->mii_adv, &local_adv); 1252 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv); 1253 1254 common = local_adv & remote_adv; 1255 if (common & ADVERTISE_100FULL) { 1256 bp->line_speed = SPEED_100; 1257 bp->duplex = DUPLEX_FULL; 1258 } 1259 else if (common & ADVERTISE_100HALF) { 1260 bp->line_speed = SPEED_100; 1261 bp->duplex = DUPLEX_HALF; 1262 } 1263 else if (common & ADVERTISE_10FULL) { 1264 bp->line_speed = SPEED_10; 1265 bp->duplex = DUPLEX_FULL; 1266 } 1267 else if (common & ADVERTISE_10HALF) { 1268 bp->line_speed = SPEED_10; 1269 bp->duplex = DUPLEX_HALF; 1270 } 1271 else { 1272 bp->line_speed = 0; 1273 bp->link_up = 0; 1274 } 1275 } 1276 } 1277 else { 1278 if (bmcr & BMCR_SPEED100) { 1279 bp->line_speed = SPEED_100; 1280 } 1281 else { 1282 bp->line_speed = SPEED_10; 1283 } 1284 if (bmcr & BMCR_FULLDPLX) { 1285 bp->duplex = DUPLEX_FULL; 1286 } 1287 else { 1288 bp->duplex = DUPLEX_HALF; 1289 } 1290 } 1291 1292 if (bp->link_up) { 1293 u32 ext_status; 1294 1295 bnx2_read_phy(bp, MII_BNX2_EXT_STATUS, &ext_status); 1296 if (ext_status & EXT_STATUS_MDIX) 1297 bp->phy_flags |= BNX2_PHY_FLAG_MDIX; 1298 } 1299 1300 return 0; 1301 } 1302 1303 static void 1304 bnx2_init_rx_context(struct bnx2 *bp, u32 cid) 1305 { 1306 u32 val, rx_cid_addr = GET_CID_ADDR(cid); 1307 1308 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE; 1309 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2; 1310 val |= 0x02 << 8; 1311 1312 if (bp->flow_ctrl & FLOW_CTRL_TX) 1313 val |= BNX2_L2CTX_FLOW_CTRL_ENABLE; 1314 1315 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val); 1316 } 1317 1318 static void 1319 bnx2_init_all_rx_contexts(struct bnx2 *bp) 1320 { 1321 int i; 1322 u32 cid; 1323 1324 for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) { 1325 if (i == 1) 1326 cid = RX_RSS_CID; 1327 bnx2_init_rx_context(bp, cid); 1328 } 1329 } 1330 1331 static void 1332 bnx2_set_mac_link(struct bnx2 *bp) 1333 { 1334 u32 val; 1335 1336 BNX2_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620); 1337 if (bp->link_up && (bp->line_speed == SPEED_1000) && 1338 (bp->duplex == DUPLEX_HALF)) { 1339 BNX2_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff); 1340 } 1341 1342 /* Configure the EMAC mode register. */ 1343 val = BNX2_RD(bp, BNX2_EMAC_MODE); 1344 1345 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX | 1346 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK | 1347 BNX2_EMAC_MODE_25G_MODE); 1348 1349 if (bp->link_up) { 1350 switch (bp->line_speed) { 1351 case SPEED_10: 1352 if (BNX2_CHIP(bp) != BNX2_CHIP_5706) { 1353 val |= BNX2_EMAC_MODE_PORT_MII_10M; 1354 break; 1355 } 1356 fallthrough; 1357 case SPEED_100: 1358 val |= BNX2_EMAC_MODE_PORT_MII; 1359 break; 1360 case SPEED_2500: 1361 val |= BNX2_EMAC_MODE_25G_MODE; 1362 fallthrough; 1363 case SPEED_1000: 1364 val |= BNX2_EMAC_MODE_PORT_GMII; 1365 break; 1366 } 1367 } 1368 else { 1369 val |= BNX2_EMAC_MODE_PORT_GMII; 1370 } 1371 1372 /* Set the MAC to operate in the appropriate duplex mode. */ 1373 if (bp->duplex == DUPLEX_HALF) 1374 val |= BNX2_EMAC_MODE_HALF_DUPLEX; 1375 BNX2_WR(bp, BNX2_EMAC_MODE, val); 1376 1377 /* Enable/disable rx PAUSE. */ 1378 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN; 1379 1380 if (bp->flow_ctrl & FLOW_CTRL_RX) 1381 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN; 1382 BNX2_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode); 1383 1384 /* Enable/disable tx PAUSE. */ 1385 val = BNX2_RD(bp, BNX2_EMAC_TX_MODE); 1386 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN; 1387 1388 if (bp->flow_ctrl & FLOW_CTRL_TX) 1389 val |= BNX2_EMAC_TX_MODE_FLOW_EN; 1390 BNX2_WR(bp, BNX2_EMAC_TX_MODE, val); 1391 1392 /* Acknowledge the interrupt. */ 1393 BNX2_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE); 1394 1395 bnx2_init_all_rx_contexts(bp); 1396 } 1397 1398 static void 1399 bnx2_enable_bmsr1(struct bnx2 *bp) 1400 { 1401 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && 1402 (BNX2_CHIP(bp) == BNX2_CHIP_5709)) 1403 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, 1404 MII_BNX2_BLK_ADDR_GP_STATUS); 1405 } 1406 1407 static void 1408 bnx2_disable_bmsr1(struct bnx2 *bp) 1409 { 1410 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && 1411 (BNX2_CHIP(bp) == BNX2_CHIP_5709)) 1412 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, 1413 MII_BNX2_BLK_ADDR_COMBO_IEEEB0); 1414 } 1415 1416 static int 1417 bnx2_test_and_enable_2g5(struct bnx2 *bp) 1418 { 1419 u32 up1; 1420 int ret = 1; 1421 1422 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) 1423 return 0; 1424 1425 if (bp->autoneg & AUTONEG_SPEED) 1426 bp->advertising |= ADVERTISED_2500baseX_Full; 1427 1428 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) 1429 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G); 1430 1431 bnx2_read_phy(bp, bp->mii_up1, &up1); 1432 if (!(up1 & BCM5708S_UP1_2G5)) { 1433 up1 |= BCM5708S_UP1_2G5; 1434 bnx2_write_phy(bp, bp->mii_up1, up1); 1435 ret = 0; 1436 } 1437 1438 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) 1439 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, 1440 MII_BNX2_BLK_ADDR_COMBO_IEEEB0); 1441 1442 return ret; 1443 } 1444 1445 static int 1446 bnx2_test_and_disable_2g5(struct bnx2 *bp) 1447 { 1448 u32 up1; 1449 int ret = 0; 1450 1451 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) 1452 return 0; 1453 1454 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) 1455 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G); 1456 1457 bnx2_read_phy(bp, bp->mii_up1, &up1); 1458 if (up1 & BCM5708S_UP1_2G5) { 1459 up1 &= ~BCM5708S_UP1_2G5; 1460 bnx2_write_phy(bp, bp->mii_up1, up1); 1461 ret = 1; 1462 } 1463 1464 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) 1465 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, 1466 MII_BNX2_BLK_ADDR_COMBO_IEEEB0); 1467 1468 return ret; 1469 } 1470 1471 static void 1472 bnx2_enable_forced_2g5(struct bnx2 *bp) 1473 { 1474 u32 bmcr; 1475 int err; 1476 1477 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) 1478 return; 1479 1480 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { 1481 u32 val; 1482 1483 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, 1484 MII_BNX2_BLK_ADDR_SERDES_DIG); 1485 if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) { 1486 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK; 1487 val |= MII_BNX2_SD_MISC1_FORCE | 1488 MII_BNX2_SD_MISC1_FORCE_2_5G; 1489 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val); 1490 } 1491 1492 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, 1493 MII_BNX2_BLK_ADDR_COMBO_IEEEB0); 1494 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); 1495 1496 } else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) { 1497 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); 1498 if (!err) 1499 bmcr |= BCM5708S_BMCR_FORCE_2500; 1500 } else { 1501 return; 1502 } 1503 1504 if (err) 1505 return; 1506 1507 if (bp->autoneg & AUTONEG_SPEED) { 1508 bmcr &= ~BMCR_ANENABLE; 1509 if (bp->req_duplex == DUPLEX_FULL) 1510 bmcr |= BMCR_FULLDPLX; 1511 } 1512 bnx2_write_phy(bp, bp->mii_bmcr, bmcr); 1513 } 1514 1515 static void 1516 bnx2_disable_forced_2g5(struct bnx2 *bp) 1517 { 1518 u32 bmcr; 1519 int err; 1520 1521 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) 1522 return; 1523 1524 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { 1525 u32 val; 1526 1527 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, 1528 MII_BNX2_BLK_ADDR_SERDES_DIG); 1529 if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) { 1530 val &= ~MII_BNX2_SD_MISC1_FORCE; 1531 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val); 1532 } 1533 1534 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, 1535 MII_BNX2_BLK_ADDR_COMBO_IEEEB0); 1536 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); 1537 1538 } else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) { 1539 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); 1540 if (!err) 1541 bmcr &= ~BCM5708S_BMCR_FORCE_2500; 1542 } else { 1543 return; 1544 } 1545 1546 if (err) 1547 return; 1548 1549 if (bp->autoneg & AUTONEG_SPEED) 1550 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART; 1551 bnx2_write_phy(bp, bp->mii_bmcr, bmcr); 1552 } 1553 1554 static void 1555 bnx2_5706s_force_link_dn(struct bnx2 *bp, int start) 1556 { 1557 u32 val; 1558 1559 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL); 1560 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val); 1561 if (start) 1562 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f); 1563 else 1564 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0); 1565 } 1566 1567 static int 1568 bnx2_set_link(struct bnx2 *bp) 1569 { 1570 u32 bmsr; 1571 u8 link_up; 1572 1573 if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) { 1574 bp->link_up = 1; 1575 return 0; 1576 } 1577 1578 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) 1579 return 0; 1580 1581 link_up = bp->link_up; 1582 1583 bnx2_enable_bmsr1(bp); 1584 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr); 1585 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr); 1586 bnx2_disable_bmsr1(bp); 1587 1588 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && 1589 (BNX2_CHIP(bp) == BNX2_CHIP_5706)) { 1590 u32 val, an_dbg; 1591 1592 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) { 1593 bnx2_5706s_force_link_dn(bp, 0); 1594 bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN; 1595 } 1596 val = BNX2_RD(bp, BNX2_EMAC_STATUS); 1597 1598 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG); 1599 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg); 1600 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg); 1601 1602 if ((val & BNX2_EMAC_STATUS_LINK) && 1603 !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC)) 1604 bmsr |= BMSR_LSTATUS; 1605 else 1606 bmsr &= ~BMSR_LSTATUS; 1607 } 1608 1609 if (bmsr & BMSR_LSTATUS) { 1610 bp->link_up = 1; 1611 1612 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { 1613 if (BNX2_CHIP(bp) == BNX2_CHIP_5706) 1614 bnx2_5706s_linkup(bp); 1615 else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) 1616 bnx2_5708s_linkup(bp); 1617 else if (BNX2_CHIP(bp) == BNX2_CHIP_5709) 1618 bnx2_5709s_linkup(bp); 1619 } 1620 else { 1621 bnx2_copper_linkup(bp); 1622 } 1623 bnx2_resolve_flow_ctrl(bp); 1624 } 1625 else { 1626 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && 1627 (bp->autoneg & AUTONEG_SPEED)) 1628 bnx2_disable_forced_2g5(bp); 1629 1630 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) { 1631 u32 bmcr; 1632 1633 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); 1634 bmcr |= BMCR_ANENABLE; 1635 bnx2_write_phy(bp, bp->mii_bmcr, bmcr); 1636 1637 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT; 1638 } 1639 bp->link_up = 0; 1640 } 1641 1642 if (bp->link_up != link_up) { 1643 bnx2_report_link(bp); 1644 } 1645 1646 bnx2_set_mac_link(bp); 1647 1648 return 0; 1649 } 1650 1651 static int 1652 bnx2_reset_phy(struct bnx2 *bp) 1653 { 1654 int i; 1655 u32 reg; 1656 1657 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET); 1658 1659 #define PHY_RESET_MAX_WAIT 100 1660 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) { 1661 udelay(10); 1662 1663 bnx2_read_phy(bp, bp->mii_bmcr, ®); 1664 if (!(reg & BMCR_RESET)) { 1665 udelay(20); 1666 break; 1667 } 1668 } 1669 if (i == PHY_RESET_MAX_WAIT) { 1670 return -EBUSY; 1671 } 1672 return 0; 1673 } 1674 1675 static u32 1676 bnx2_phy_get_pause_adv(struct bnx2 *bp) 1677 { 1678 u32 adv = 0; 1679 1680 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) == 1681 (FLOW_CTRL_RX | FLOW_CTRL_TX)) { 1682 1683 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { 1684 adv = ADVERTISE_1000XPAUSE; 1685 } 1686 else { 1687 adv = ADVERTISE_PAUSE_CAP; 1688 } 1689 } 1690 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) { 1691 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { 1692 adv = ADVERTISE_1000XPSE_ASYM; 1693 } 1694 else { 1695 adv = ADVERTISE_PAUSE_ASYM; 1696 } 1697 } 1698 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) { 1699 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { 1700 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM; 1701 } 1702 else { 1703 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; 1704 } 1705 } 1706 return adv; 1707 } 1708 1709 static int bnx2_fw_sync(struct bnx2 *, u32, int, int); 1710 1711 static int 1712 bnx2_setup_remote_phy(struct bnx2 *bp, u8 port) 1713 __releases(&bp->phy_lock) 1714 __acquires(&bp->phy_lock) 1715 { 1716 u32 speed_arg = 0, pause_adv; 1717 1718 pause_adv = bnx2_phy_get_pause_adv(bp); 1719 1720 if (bp->autoneg & AUTONEG_SPEED) { 1721 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG; 1722 if (bp->advertising & ADVERTISED_10baseT_Half) 1723 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF; 1724 if (bp->advertising & ADVERTISED_10baseT_Full) 1725 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL; 1726 if (bp->advertising & ADVERTISED_100baseT_Half) 1727 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF; 1728 if (bp->advertising & ADVERTISED_100baseT_Full) 1729 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL; 1730 if (bp->advertising & ADVERTISED_1000baseT_Full) 1731 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL; 1732 if (bp->advertising & ADVERTISED_2500baseX_Full) 1733 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL; 1734 } else { 1735 if (bp->req_line_speed == SPEED_2500) 1736 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL; 1737 else if (bp->req_line_speed == SPEED_1000) 1738 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL; 1739 else if (bp->req_line_speed == SPEED_100) { 1740 if (bp->req_duplex == DUPLEX_FULL) 1741 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL; 1742 else 1743 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF; 1744 } else if (bp->req_line_speed == SPEED_10) { 1745 if (bp->req_duplex == DUPLEX_FULL) 1746 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL; 1747 else 1748 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF; 1749 } 1750 } 1751 1752 if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP)) 1753 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE; 1754 if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM)) 1755 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE; 1756 1757 if (port == PORT_TP) 1758 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE | 1759 BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED; 1760 1761 bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg); 1762 1763 spin_unlock_bh(&bp->phy_lock); 1764 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0); 1765 spin_lock_bh(&bp->phy_lock); 1766 1767 return 0; 1768 } 1769 1770 static int 1771 bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port) 1772 __releases(&bp->phy_lock) 1773 __acquires(&bp->phy_lock) 1774 { 1775 u32 adv, bmcr; 1776 u32 new_adv = 0; 1777 1778 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) 1779 return bnx2_setup_remote_phy(bp, port); 1780 1781 if (!(bp->autoneg & AUTONEG_SPEED)) { 1782 u32 new_bmcr; 1783 int force_link_down = 0; 1784 1785 if (bp->req_line_speed == SPEED_2500) { 1786 if (!bnx2_test_and_enable_2g5(bp)) 1787 force_link_down = 1; 1788 } else if (bp->req_line_speed == SPEED_1000) { 1789 if (bnx2_test_and_disable_2g5(bp)) 1790 force_link_down = 1; 1791 } 1792 bnx2_read_phy(bp, bp->mii_adv, &adv); 1793 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF); 1794 1795 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); 1796 new_bmcr = bmcr & ~BMCR_ANENABLE; 1797 new_bmcr |= BMCR_SPEED1000; 1798 1799 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { 1800 if (bp->req_line_speed == SPEED_2500) 1801 bnx2_enable_forced_2g5(bp); 1802 else if (bp->req_line_speed == SPEED_1000) { 1803 bnx2_disable_forced_2g5(bp); 1804 new_bmcr &= ~0x2000; 1805 } 1806 1807 } else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) { 1808 if (bp->req_line_speed == SPEED_2500) 1809 new_bmcr |= BCM5708S_BMCR_FORCE_2500; 1810 else 1811 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500; 1812 } 1813 1814 if (bp->req_duplex == DUPLEX_FULL) { 1815 adv |= ADVERTISE_1000XFULL; 1816 new_bmcr |= BMCR_FULLDPLX; 1817 } 1818 else { 1819 adv |= ADVERTISE_1000XHALF; 1820 new_bmcr &= ~BMCR_FULLDPLX; 1821 } 1822 if ((new_bmcr != bmcr) || (force_link_down)) { 1823 /* Force a link down visible on the other side */ 1824 if (bp->link_up) { 1825 bnx2_write_phy(bp, bp->mii_adv, adv & 1826 ~(ADVERTISE_1000XFULL | 1827 ADVERTISE_1000XHALF)); 1828 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | 1829 BMCR_ANRESTART | BMCR_ANENABLE); 1830 1831 bp->link_up = 0; 1832 netif_carrier_off(bp->dev); 1833 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr); 1834 bnx2_report_link(bp); 1835 } 1836 bnx2_write_phy(bp, bp->mii_adv, adv); 1837 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr); 1838 } else { 1839 bnx2_resolve_flow_ctrl(bp); 1840 bnx2_set_mac_link(bp); 1841 } 1842 return 0; 1843 } 1844 1845 bnx2_test_and_enable_2g5(bp); 1846 1847 if (bp->advertising & ADVERTISED_1000baseT_Full) 1848 new_adv |= ADVERTISE_1000XFULL; 1849 1850 new_adv |= bnx2_phy_get_pause_adv(bp); 1851 1852 bnx2_read_phy(bp, bp->mii_adv, &adv); 1853 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); 1854 1855 bp->serdes_an_pending = 0; 1856 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) { 1857 /* Force a link down visible on the other side */ 1858 if (bp->link_up) { 1859 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK); 1860 spin_unlock_bh(&bp->phy_lock); 1861 msleep(20); 1862 spin_lock_bh(&bp->phy_lock); 1863 } 1864 1865 bnx2_write_phy(bp, bp->mii_adv, new_adv); 1866 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | 1867 BMCR_ANENABLE); 1868 /* Speed up link-up time when the link partner 1869 * does not autonegotiate which is very common 1870 * in blade servers. Some blade servers use 1871 * IPMI for kerboard input and it's important 1872 * to minimize link disruptions. Autoneg. involves 1873 * exchanging base pages plus 3 next pages and 1874 * normally completes in about 120 msec. 1875 */ 1876 bp->current_interval = BNX2_SERDES_AN_TIMEOUT; 1877 bp->serdes_an_pending = 1; 1878 mod_timer(&bp->timer, jiffies + bp->current_interval); 1879 } else { 1880 bnx2_resolve_flow_ctrl(bp); 1881 bnx2_set_mac_link(bp); 1882 } 1883 1884 return 0; 1885 } 1886 1887 #define ETHTOOL_ALL_FIBRE_SPEED \ 1888 (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ? \ 1889 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\ 1890 (ADVERTISED_1000baseT_Full) 1891 1892 #define ETHTOOL_ALL_COPPER_SPEED \ 1893 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \ 1894 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \ 1895 ADVERTISED_1000baseT_Full) 1896 1897 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \ 1898 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA) 1899 1900 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL) 1901 1902 static void 1903 bnx2_set_default_remote_link(struct bnx2 *bp) 1904 { 1905 u32 link; 1906 1907 if (bp->phy_port == PORT_TP) 1908 link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK); 1909 else 1910 link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK); 1911 1912 if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) { 1913 bp->req_line_speed = 0; 1914 bp->autoneg |= AUTONEG_SPEED; 1915 bp->advertising = ADVERTISED_Autoneg; 1916 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF) 1917 bp->advertising |= ADVERTISED_10baseT_Half; 1918 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL) 1919 bp->advertising |= ADVERTISED_10baseT_Full; 1920 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF) 1921 bp->advertising |= ADVERTISED_100baseT_Half; 1922 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL) 1923 bp->advertising |= ADVERTISED_100baseT_Full; 1924 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL) 1925 bp->advertising |= ADVERTISED_1000baseT_Full; 1926 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL) 1927 bp->advertising |= ADVERTISED_2500baseX_Full; 1928 } else { 1929 bp->autoneg = 0; 1930 bp->advertising = 0; 1931 bp->req_duplex = DUPLEX_FULL; 1932 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) { 1933 bp->req_line_speed = SPEED_10; 1934 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF) 1935 bp->req_duplex = DUPLEX_HALF; 1936 } 1937 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) { 1938 bp->req_line_speed = SPEED_100; 1939 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF) 1940 bp->req_duplex = DUPLEX_HALF; 1941 } 1942 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL) 1943 bp->req_line_speed = SPEED_1000; 1944 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL) 1945 bp->req_line_speed = SPEED_2500; 1946 } 1947 } 1948 1949 static void 1950 bnx2_set_default_link(struct bnx2 *bp) 1951 { 1952 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) { 1953 bnx2_set_default_remote_link(bp); 1954 return; 1955 } 1956 1957 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL; 1958 bp->req_line_speed = 0; 1959 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { 1960 u32 reg; 1961 1962 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg; 1963 1964 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG); 1965 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK; 1966 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) { 1967 bp->autoneg = 0; 1968 bp->req_line_speed = bp->line_speed = SPEED_1000; 1969 bp->req_duplex = DUPLEX_FULL; 1970 } 1971 } else 1972 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg; 1973 } 1974 1975 static void 1976 bnx2_send_heart_beat(struct bnx2 *bp) 1977 { 1978 u32 msg; 1979 u32 addr; 1980 1981 spin_lock(&bp->indirect_lock); 1982 msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK); 1983 addr = bp->shmem_base + BNX2_DRV_PULSE_MB; 1984 BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr); 1985 BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW, msg); 1986 spin_unlock(&bp->indirect_lock); 1987 } 1988 1989 static void 1990 bnx2_remote_phy_event(struct bnx2 *bp) 1991 { 1992 u32 msg; 1993 u8 link_up = bp->link_up; 1994 u8 old_port; 1995 1996 msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS); 1997 1998 if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED) 1999 bnx2_send_heart_beat(bp); 2000 2001 msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED; 2002 2003 if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN) 2004 bp->link_up = 0; 2005 else { 2006 u32 speed; 2007 2008 bp->link_up = 1; 2009 speed = msg & BNX2_LINK_STATUS_SPEED_MASK; 2010 bp->duplex = DUPLEX_FULL; 2011 switch (speed) { 2012 case BNX2_LINK_STATUS_10HALF: 2013 bp->duplex = DUPLEX_HALF; 2014 fallthrough; 2015 case BNX2_LINK_STATUS_10FULL: 2016 bp->line_speed = SPEED_10; 2017 break; 2018 case BNX2_LINK_STATUS_100HALF: 2019 bp->duplex = DUPLEX_HALF; 2020 fallthrough; 2021 case BNX2_LINK_STATUS_100BASE_T4: 2022 case BNX2_LINK_STATUS_100FULL: 2023 bp->line_speed = SPEED_100; 2024 break; 2025 case BNX2_LINK_STATUS_1000HALF: 2026 bp->duplex = DUPLEX_HALF; 2027 fallthrough; 2028 case BNX2_LINK_STATUS_1000FULL: 2029 bp->line_speed = SPEED_1000; 2030 break; 2031 case BNX2_LINK_STATUS_2500HALF: 2032 bp->duplex = DUPLEX_HALF; 2033 fallthrough; 2034 case BNX2_LINK_STATUS_2500FULL: 2035 bp->line_speed = SPEED_2500; 2036 break; 2037 default: 2038 bp->line_speed = 0; 2039 break; 2040 } 2041 2042 bp->flow_ctrl = 0; 2043 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) != 2044 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) { 2045 if (bp->duplex == DUPLEX_FULL) 2046 bp->flow_ctrl = bp->req_flow_ctrl; 2047 } else { 2048 if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED) 2049 bp->flow_ctrl |= FLOW_CTRL_TX; 2050 if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED) 2051 bp->flow_ctrl |= FLOW_CTRL_RX; 2052 } 2053 2054 old_port = bp->phy_port; 2055 if (msg & BNX2_LINK_STATUS_SERDES_LINK) 2056 bp->phy_port = PORT_FIBRE; 2057 else 2058 bp->phy_port = PORT_TP; 2059 2060 if (old_port != bp->phy_port) 2061 bnx2_set_default_link(bp); 2062 2063 } 2064 if (bp->link_up != link_up) 2065 bnx2_report_link(bp); 2066 2067 bnx2_set_mac_link(bp); 2068 } 2069 2070 static int 2071 bnx2_set_remote_link(struct bnx2 *bp) 2072 { 2073 u32 evt_code; 2074 2075 evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB); 2076 switch (evt_code) { 2077 case BNX2_FW_EVT_CODE_LINK_EVENT: 2078 bnx2_remote_phy_event(bp); 2079 break; 2080 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT: 2081 default: 2082 bnx2_send_heart_beat(bp); 2083 break; 2084 } 2085 return 0; 2086 } 2087 2088 static int 2089 bnx2_setup_copper_phy(struct bnx2 *bp) 2090 __releases(&bp->phy_lock) 2091 __acquires(&bp->phy_lock) 2092 { 2093 u32 bmcr, adv_reg, new_adv = 0; 2094 u32 new_bmcr; 2095 2096 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); 2097 2098 bnx2_read_phy(bp, bp->mii_adv, &adv_reg); 2099 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP | 2100 ADVERTISE_PAUSE_ASYM); 2101 2102 new_adv = ADVERTISE_CSMA | ethtool_adv_to_mii_adv_t(bp->advertising); 2103 2104 if (bp->autoneg & AUTONEG_SPEED) { 2105 u32 adv1000_reg; 2106 u32 new_adv1000 = 0; 2107 2108 new_adv |= bnx2_phy_get_pause_adv(bp); 2109 2110 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg); 2111 adv1000_reg &= PHY_ALL_1000_SPEED; 2112 2113 new_adv1000 |= ethtool_adv_to_mii_ctrl1000_t(bp->advertising); 2114 if ((adv1000_reg != new_adv1000) || 2115 (adv_reg != new_adv) || 2116 ((bmcr & BMCR_ANENABLE) == 0)) { 2117 2118 bnx2_write_phy(bp, bp->mii_adv, new_adv); 2119 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000); 2120 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART | 2121 BMCR_ANENABLE); 2122 } 2123 else if (bp->link_up) { 2124 /* Flow ctrl may have changed from auto to forced */ 2125 /* or vice-versa. */ 2126 2127 bnx2_resolve_flow_ctrl(bp); 2128 bnx2_set_mac_link(bp); 2129 } 2130 return 0; 2131 } 2132 2133 /* advertise nothing when forcing speed */ 2134 if (adv_reg != new_adv) 2135 bnx2_write_phy(bp, bp->mii_adv, new_adv); 2136 2137 new_bmcr = 0; 2138 if (bp->req_line_speed == SPEED_100) { 2139 new_bmcr |= BMCR_SPEED100; 2140 } 2141 if (bp->req_duplex == DUPLEX_FULL) { 2142 new_bmcr |= BMCR_FULLDPLX; 2143 } 2144 if (new_bmcr != bmcr) { 2145 u32 bmsr; 2146 2147 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); 2148 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); 2149 2150 if (bmsr & BMSR_LSTATUS) { 2151 /* Force link down */ 2152 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK); 2153 spin_unlock_bh(&bp->phy_lock); 2154 msleep(50); 2155 spin_lock_bh(&bp->phy_lock); 2156 2157 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); 2158 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); 2159 } 2160 2161 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr); 2162 2163 /* Normally, the new speed is setup after the link has 2164 * gone down and up again. In some cases, link will not go 2165 * down so we need to set up the new speed here. 2166 */ 2167 if (bmsr & BMSR_LSTATUS) { 2168 bp->line_speed = bp->req_line_speed; 2169 bp->duplex = bp->req_duplex; 2170 bnx2_resolve_flow_ctrl(bp); 2171 bnx2_set_mac_link(bp); 2172 } 2173 } else { 2174 bnx2_resolve_flow_ctrl(bp); 2175 bnx2_set_mac_link(bp); 2176 } 2177 return 0; 2178 } 2179 2180 static int 2181 bnx2_setup_phy(struct bnx2 *bp, u8 port) 2182 __releases(&bp->phy_lock) 2183 __acquires(&bp->phy_lock) 2184 { 2185 if (bp->loopback == MAC_LOOPBACK) 2186 return 0; 2187 2188 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { 2189 return bnx2_setup_serdes_phy(bp, port); 2190 } 2191 else { 2192 return bnx2_setup_copper_phy(bp); 2193 } 2194 } 2195 2196 static int 2197 bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy) 2198 { 2199 u32 val; 2200 2201 bp->mii_bmcr = MII_BMCR + 0x10; 2202 bp->mii_bmsr = MII_BMSR + 0x10; 2203 bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1; 2204 bp->mii_adv = MII_ADVERTISE + 0x10; 2205 bp->mii_lpa = MII_LPA + 0x10; 2206 bp->mii_up1 = MII_BNX2_OVER1G_UP1; 2207 2208 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER); 2209 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD); 2210 2211 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0); 2212 if (reset_phy) 2213 bnx2_reset_phy(bp); 2214 2215 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG); 2216 2217 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val); 2218 val &= ~MII_BNX2_SD_1000XCTL1_AUTODET; 2219 val |= MII_BNX2_SD_1000XCTL1_FIBER; 2220 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val); 2221 2222 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G); 2223 bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val); 2224 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) 2225 val |= BCM5708S_UP1_2G5; 2226 else 2227 val &= ~BCM5708S_UP1_2G5; 2228 bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val); 2229 2230 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG); 2231 bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val); 2232 val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM; 2233 bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val); 2234 2235 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0); 2236 2237 val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN | 2238 MII_BNX2_CL73_BAM_NP_AFT_BP_EN; 2239 bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val); 2240 2241 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0); 2242 2243 return 0; 2244 } 2245 2246 static int 2247 bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy) 2248 { 2249 u32 val; 2250 2251 if (reset_phy) 2252 bnx2_reset_phy(bp); 2253 2254 bp->mii_up1 = BCM5708S_UP1; 2255 2256 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3); 2257 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE); 2258 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG); 2259 2260 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val); 2261 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN; 2262 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val); 2263 2264 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val); 2265 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN; 2266 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val); 2267 2268 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) { 2269 bnx2_read_phy(bp, BCM5708S_UP1, &val); 2270 val |= BCM5708S_UP1_2G5; 2271 bnx2_write_phy(bp, BCM5708S_UP1, val); 2272 } 2273 2274 if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0) || 2275 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B0) || 2276 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B1)) { 2277 /* increase tx signal amplitude */ 2278 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, 2279 BCM5708S_BLK_ADDR_TX_MISC); 2280 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val); 2281 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM; 2282 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val); 2283 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG); 2284 } 2285 2286 val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) & 2287 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK; 2288 2289 if (val) { 2290 u32 is_backplane; 2291 2292 is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG); 2293 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) { 2294 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, 2295 BCM5708S_BLK_ADDR_TX_MISC); 2296 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val); 2297 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, 2298 BCM5708S_BLK_ADDR_DIG); 2299 } 2300 } 2301 return 0; 2302 } 2303 2304 static int 2305 bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy) 2306 { 2307 if (reset_phy) 2308 bnx2_reset_phy(bp); 2309 2310 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT; 2311 2312 if (BNX2_CHIP(bp) == BNX2_CHIP_5706) 2313 BNX2_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300); 2314 2315 if (bp->dev->mtu > ETH_DATA_LEN) { 2316 u32 val; 2317 2318 /* Set extended packet length bit */ 2319 bnx2_write_phy(bp, 0x18, 0x7); 2320 bnx2_read_phy(bp, 0x18, &val); 2321 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000); 2322 2323 bnx2_write_phy(bp, 0x1c, 0x6c00); 2324 bnx2_read_phy(bp, 0x1c, &val); 2325 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02); 2326 } 2327 else { 2328 u32 val; 2329 2330 bnx2_write_phy(bp, 0x18, 0x7); 2331 bnx2_read_phy(bp, 0x18, &val); 2332 bnx2_write_phy(bp, 0x18, val & ~0x4007); 2333 2334 bnx2_write_phy(bp, 0x1c, 0x6c00); 2335 bnx2_read_phy(bp, 0x1c, &val); 2336 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00); 2337 } 2338 2339 return 0; 2340 } 2341 2342 static int 2343 bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy) 2344 { 2345 u32 val; 2346 2347 if (reset_phy) 2348 bnx2_reset_phy(bp); 2349 2350 if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) { 2351 bnx2_write_phy(bp, 0x18, 0x0c00); 2352 bnx2_write_phy(bp, 0x17, 0x000a); 2353 bnx2_write_phy(bp, 0x15, 0x310b); 2354 bnx2_write_phy(bp, 0x17, 0x201f); 2355 bnx2_write_phy(bp, 0x15, 0x9506); 2356 bnx2_write_phy(bp, 0x17, 0x401f); 2357 bnx2_write_phy(bp, 0x15, 0x14e2); 2358 bnx2_write_phy(bp, 0x18, 0x0400); 2359 } 2360 2361 if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) { 2362 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, 2363 MII_BNX2_DSP_EXPAND_REG | 0x8); 2364 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val); 2365 val &= ~(1 << 8); 2366 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val); 2367 } 2368 2369 if (bp->dev->mtu > ETH_DATA_LEN) { 2370 /* Set extended packet length bit */ 2371 bnx2_write_phy(bp, 0x18, 0x7); 2372 bnx2_read_phy(bp, 0x18, &val); 2373 bnx2_write_phy(bp, 0x18, val | 0x4000); 2374 2375 bnx2_read_phy(bp, 0x10, &val); 2376 bnx2_write_phy(bp, 0x10, val | 0x1); 2377 } 2378 else { 2379 bnx2_write_phy(bp, 0x18, 0x7); 2380 bnx2_read_phy(bp, 0x18, &val); 2381 bnx2_write_phy(bp, 0x18, val & ~0x4007); 2382 2383 bnx2_read_phy(bp, 0x10, &val); 2384 bnx2_write_phy(bp, 0x10, val & ~0x1); 2385 } 2386 2387 /* ethernet@wirespeed */ 2388 bnx2_write_phy(bp, MII_BNX2_AUX_CTL, AUX_CTL_MISC_CTL); 2389 bnx2_read_phy(bp, MII_BNX2_AUX_CTL, &val); 2390 val |= AUX_CTL_MISC_CTL_WR | AUX_CTL_MISC_CTL_WIRESPEED; 2391 2392 /* auto-mdix */ 2393 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) 2394 val |= AUX_CTL_MISC_CTL_AUTOMDIX; 2395 2396 bnx2_write_phy(bp, MII_BNX2_AUX_CTL, val); 2397 return 0; 2398 } 2399 2400 2401 static int 2402 bnx2_init_phy(struct bnx2 *bp, int reset_phy) 2403 __releases(&bp->phy_lock) 2404 __acquires(&bp->phy_lock) 2405 { 2406 u32 val; 2407 int rc = 0; 2408 2409 bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK; 2410 bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY; 2411 2412 bp->mii_bmcr = MII_BMCR; 2413 bp->mii_bmsr = MII_BMSR; 2414 bp->mii_bmsr1 = MII_BMSR; 2415 bp->mii_adv = MII_ADVERTISE; 2416 bp->mii_lpa = MII_LPA; 2417 2418 BNX2_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK); 2419 2420 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) 2421 goto setup_phy; 2422 2423 bnx2_read_phy(bp, MII_PHYSID1, &val); 2424 bp->phy_id = val << 16; 2425 bnx2_read_phy(bp, MII_PHYSID2, &val); 2426 bp->phy_id |= val & 0xffff; 2427 2428 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { 2429 if (BNX2_CHIP(bp) == BNX2_CHIP_5706) 2430 rc = bnx2_init_5706s_phy(bp, reset_phy); 2431 else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) 2432 rc = bnx2_init_5708s_phy(bp, reset_phy); 2433 else if (BNX2_CHIP(bp) == BNX2_CHIP_5709) 2434 rc = bnx2_init_5709s_phy(bp, reset_phy); 2435 } 2436 else { 2437 rc = bnx2_init_copper_phy(bp, reset_phy); 2438 } 2439 2440 setup_phy: 2441 if (!rc) 2442 rc = bnx2_setup_phy(bp, bp->phy_port); 2443 2444 return rc; 2445 } 2446 2447 static int 2448 bnx2_set_mac_loopback(struct bnx2 *bp) 2449 { 2450 u32 mac_mode; 2451 2452 mac_mode = BNX2_RD(bp, BNX2_EMAC_MODE); 2453 mac_mode &= ~BNX2_EMAC_MODE_PORT; 2454 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK; 2455 BNX2_WR(bp, BNX2_EMAC_MODE, mac_mode); 2456 bp->link_up = 1; 2457 return 0; 2458 } 2459 2460 static int bnx2_test_link(struct bnx2 *); 2461 2462 static int 2463 bnx2_set_phy_loopback(struct bnx2 *bp) 2464 { 2465 u32 mac_mode; 2466 int rc, i; 2467 2468 spin_lock_bh(&bp->phy_lock); 2469 rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX | 2470 BMCR_SPEED1000); 2471 spin_unlock_bh(&bp->phy_lock); 2472 if (rc) 2473 return rc; 2474 2475 for (i = 0; i < 10; i++) { 2476 if (bnx2_test_link(bp) == 0) 2477 break; 2478 msleep(100); 2479 } 2480 2481 mac_mode = BNX2_RD(bp, BNX2_EMAC_MODE); 2482 mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX | 2483 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK | 2484 BNX2_EMAC_MODE_25G_MODE); 2485 2486 mac_mode |= BNX2_EMAC_MODE_PORT_GMII; 2487 BNX2_WR(bp, BNX2_EMAC_MODE, mac_mode); 2488 bp->link_up = 1; 2489 return 0; 2490 } 2491 2492 static void 2493 bnx2_dump_mcp_state(struct bnx2 *bp) 2494 { 2495 struct net_device *dev = bp->dev; 2496 u32 mcp_p0, mcp_p1; 2497 2498 netdev_err(dev, "<--- start MCP states dump --->\n"); 2499 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { 2500 mcp_p0 = BNX2_MCP_STATE_P0; 2501 mcp_p1 = BNX2_MCP_STATE_P1; 2502 } else { 2503 mcp_p0 = BNX2_MCP_STATE_P0_5708; 2504 mcp_p1 = BNX2_MCP_STATE_P1_5708; 2505 } 2506 netdev_err(dev, "DEBUG: MCP_STATE_P0[%08x] MCP_STATE_P1[%08x]\n", 2507 bnx2_reg_rd_ind(bp, mcp_p0), bnx2_reg_rd_ind(bp, mcp_p1)); 2508 netdev_err(dev, "DEBUG: MCP mode[%08x] state[%08x] evt_mask[%08x]\n", 2509 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_MODE), 2510 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_STATE), 2511 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_EVENT_MASK)); 2512 netdev_err(dev, "DEBUG: pc[%08x] pc[%08x] instr[%08x]\n", 2513 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_PROGRAM_COUNTER), 2514 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_PROGRAM_COUNTER), 2515 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_INSTRUCTION)); 2516 netdev_err(dev, "DEBUG: shmem states:\n"); 2517 netdev_err(dev, "DEBUG: drv_mb[%08x] fw_mb[%08x] link_status[%08x]", 2518 bnx2_shmem_rd(bp, BNX2_DRV_MB), 2519 bnx2_shmem_rd(bp, BNX2_FW_MB), 2520 bnx2_shmem_rd(bp, BNX2_LINK_STATUS)); 2521 pr_cont(" drv_pulse_mb[%08x]\n", bnx2_shmem_rd(bp, BNX2_DRV_PULSE_MB)); 2522 netdev_err(dev, "DEBUG: dev_info_signature[%08x] reset_type[%08x]", 2523 bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE), 2524 bnx2_shmem_rd(bp, BNX2_BC_STATE_RESET_TYPE)); 2525 pr_cont(" condition[%08x]\n", 2526 bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION)); 2527 DP_SHMEM_LINE(bp, BNX2_BC_RESET_TYPE); 2528 DP_SHMEM_LINE(bp, 0x3cc); 2529 DP_SHMEM_LINE(bp, 0x3dc); 2530 DP_SHMEM_LINE(bp, 0x3ec); 2531 netdev_err(dev, "DEBUG: 0x3fc[%08x]\n", bnx2_shmem_rd(bp, 0x3fc)); 2532 netdev_err(dev, "<--- end MCP states dump --->\n"); 2533 } 2534 2535 static int 2536 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent) 2537 { 2538 int i; 2539 u32 val; 2540 2541 bp->fw_wr_seq++; 2542 msg_data |= bp->fw_wr_seq; 2543 bp->fw_last_msg = msg_data; 2544 2545 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data); 2546 2547 if (!ack) 2548 return 0; 2549 2550 /* wait for an acknowledgement. */ 2551 for (i = 0; i < (BNX2_FW_ACK_TIME_OUT_MS / 10); i++) { 2552 msleep(10); 2553 2554 val = bnx2_shmem_rd(bp, BNX2_FW_MB); 2555 2556 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ)) 2557 break; 2558 } 2559 if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0) 2560 return 0; 2561 2562 /* If we timed out, inform the firmware that this is the case. */ 2563 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) { 2564 msg_data &= ~BNX2_DRV_MSG_CODE; 2565 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT; 2566 2567 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data); 2568 if (!silent) { 2569 pr_err("fw sync timeout, reset code = %x\n", msg_data); 2570 bnx2_dump_mcp_state(bp); 2571 } 2572 2573 return -EBUSY; 2574 } 2575 2576 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK) 2577 return -EIO; 2578 2579 return 0; 2580 } 2581 2582 static int 2583 bnx2_init_5709_context(struct bnx2 *bp) 2584 { 2585 int i, ret = 0; 2586 u32 val; 2587 2588 val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12); 2589 val |= (BNX2_PAGE_BITS - 8) << 16; 2590 BNX2_WR(bp, BNX2_CTX_COMMAND, val); 2591 for (i = 0; i < 10; i++) { 2592 val = BNX2_RD(bp, BNX2_CTX_COMMAND); 2593 if (!(val & BNX2_CTX_COMMAND_MEM_INIT)) 2594 break; 2595 udelay(2); 2596 } 2597 if (val & BNX2_CTX_COMMAND_MEM_INIT) 2598 return -EBUSY; 2599 2600 for (i = 0; i < bp->ctx_pages; i++) { 2601 int j; 2602 2603 if (bp->ctx_blk[i]) 2604 memset(bp->ctx_blk[i], 0, BNX2_PAGE_SIZE); 2605 else 2606 return -ENOMEM; 2607 2608 BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0, 2609 (bp->ctx_blk_mapping[i] & 0xffffffff) | 2610 BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID); 2611 BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1, 2612 (u64) bp->ctx_blk_mapping[i] >> 32); 2613 BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i | 2614 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ); 2615 for (j = 0; j < 10; j++) { 2616 2617 val = BNX2_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL); 2618 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ)) 2619 break; 2620 udelay(5); 2621 } 2622 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) { 2623 ret = -EBUSY; 2624 break; 2625 } 2626 } 2627 return ret; 2628 } 2629 2630 static void 2631 bnx2_init_context(struct bnx2 *bp) 2632 { 2633 u32 vcid; 2634 2635 vcid = 96; 2636 while (vcid) { 2637 u32 vcid_addr, pcid_addr, offset; 2638 int i; 2639 2640 vcid--; 2641 2642 if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) { 2643 u32 new_vcid; 2644 2645 vcid_addr = GET_PCID_ADDR(vcid); 2646 if (vcid & 0x8) { 2647 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7); 2648 } 2649 else { 2650 new_vcid = vcid; 2651 } 2652 pcid_addr = GET_PCID_ADDR(new_vcid); 2653 } 2654 else { 2655 vcid_addr = GET_CID_ADDR(vcid); 2656 pcid_addr = vcid_addr; 2657 } 2658 2659 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) { 2660 vcid_addr += (i << PHY_CTX_SHIFT); 2661 pcid_addr += (i << PHY_CTX_SHIFT); 2662 2663 BNX2_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr); 2664 BNX2_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr); 2665 2666 /* Zero out the context. */ 2667 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) 2668 bnx2_ctx_wr(bp, vcid_addr, offset, 0); 2669 } 2670 } 2671 } 2672 2673 static int 2674 bnx2_alloc_bad_rbuf(struct bnx2 *bp) 2675 { 2676 u16 *good_mbuf; 2677 u32 good_mbuf_cnt; 2678 u32 val; 2679 2680 good_mbuf = kmalloc_array(512, sizeof(u16), GFP_KERNEL); 2681 if (!good_mbuf) 2682 return -ENOMEM; 2683 2684 BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS, 2685 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE); 2686 2687 good_mbuf_cnt = 0; 2688 2689 /* Allocate a bunch of mbufs and save the good ones in an array. */ 2690 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1); 2691 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) { 2692 bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND, 2693 BNX2_RBUF_COMMAND_ALLOC_REQ); 2694 2695 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC); 2696 2697 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE; 2698 2699 /* The addresses with Bit 9 set are bad memory blocks. */ 2700 if (!(val & (1 << 9))) { 2701 good_mbuf[good_mbuf_cnt] = (u16) val; 2702 good_mbuf_cnt++; 2703 } 2704 2705 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1); 2706 } 2707 2708 /* Free the good ones back to the mbuf pool thus discarding 2709 * all the bad ones. */ 2710 while (good_mbuf_cnt) { 2711 good_mbuf_cnt--; 2712 2713 val = good_mbuf[good_mbuf_cnt]; 2714 val = (val << 9) | val | 1; 2715 2716 bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val); 2717 } 2718 kfree(good_mbuf); 2719 return 0; 2720 } 2721 2722 static void 2723 bnx2_set_mac_addr(struct bnx2 *bp, const u8 *mac_addr, u32 pos) 2724 { 2725 u32 val; 2726 2727 val = (mac_addr[0] << 8) | mac_addr[1]; 2728 2729 BNX2_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val); 2730 2731 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 2732 (mac_addr[4] << 8) | mac_addr[5]; 2733 2734 BNX2_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val); 2735 } 2736 2737 static inline int 2738 bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index, gfp_t gfp) 2739 { 2740 dma_addr_t mapping; 2741 struct bnx2_sw_pg *rx_pg = &rxr->rx_pg_ring[index]; 2742 struct bnx2_rx_bd *rxbd = 2743 &rxr->rx_pg_desc_ring[BNX2_RX_RING(index)][BNX2_RX_IDX(index)]; 2744 struct page *page = alloc_page(gfp); 2745 2746 if (!page) 2747 return -ENOMEM; 2748 mapping = dma_map_page(&bp->pdev->dev, page, 0, PAGE_SIZE, 2749 DMA_FROM_DEVICE); 2750 if (dma_mapping_error(&bp->pdev->dev, mapping)) { 2751 __free_page(page); 2752 return -EIO; 2753 } 2754 2755 rx_pg->page = page; 2756 dma_unmap_addr_set(rx_pg, mapping, mapping); 2757 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32; 2758 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff; 2759 return 0; 2760 } 2761 2762 static void 2763 bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index) 2764 { 2765 struct bnx2_sw_pg *rx_pg = &rxr->rx_pg_ring[index]; 2766 struct page *page = rx_pg->page; 2767 2768 if (!page) 2769 return; 2770 2771 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(rx_pg, mapping), 2772 PAGE_SIZE, DMA_FROM_DEVICE); 2773 2774 __free_page(page); 2775 rx_pg->page = NULL; 2776 } 2777 2778 static inline int 2779 bnx2_alloc_rx_data(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index, gfp_t gfp) 2780 { 2781 u8 *data; 2782 struct bnx2_sw_bd *rx_buf = &rxr->rx_buf_ring[index]; 2783 dma_addr_t mapping; 2784 struct bnx2_rx_bd *rxbd = 2785 &rxr->rx_desc_ring[BNX2_RX_RING(index)][BNX2_RX_IDX(index)]; 2786 2787 data = kmalloc(bp->rx_buf_size, gfp); 2788 if (!data) 2789 return -ENOMEM; 2790 2791 mapping = dma_map_single(&bp->pdev->dev, 2792 get_l2_fhdr(data), 2793 bp->rx_buf_use_size, 2794 DMA_FROM_DEVICE); 2795 if (dma_mapping_error(&bp->pdev->dev, mapping)) { 2796 kfree(data); 2797 return -EIO; 2798 } 2799 2800 rx_buf->data = data; 2801 dma_unmap_addr_set(rx_buf, mapping, mapping); 2802 2803 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32; 2804 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff; 2805 2806 rxr->rx_prod_bseq += bp->rx_buf_use_size; 2807 2808 return 0; 2809 } 2810 2811 static int 2812 bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event) 2813 { 2814 struct status_block *sblk = bnapi->status_blk.msi; 2815 u32 new_link_state, old_link_state; 2816 int is_set = 1; 2817 2818 new_link_state = sblk->status_attn_bits & event; 2819 old_link_state = sblk->status_attn_bits_ack & event; 2820 if (new_link_state != old_link_state) { 2821 if (new_link_state) 2822 BNX2_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event); 2823 else 2824 BNX2_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event); 2825 } else 2826 is_set = 0; 2827 2828 return is_set; 2829 } 2830 2831 static void 2832 bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi) 2833 { 2834 spin_lock(&bp->phy_lock); 2835 2836 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE)) 2837 bnx2_set_link(bp); 2838 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT)) 2839 bnx2_set_remote_link(bp); 2840 2841 spin_unlock(&bp->phy_lock); 2842 2843 } 2844 2845 static inline u16 2846 bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi) 2847 { 2848 u16 cons; 2849 2850 cons = READ_ONCE(*bnapi->hw_tx_cons_ptr); 2851 2852 if (unlikely((cons & BNX2_MAX_TX_DESC_CNT) == BNX2_MAX_TX_DESC_CNT)) 2853 cons++; 2854 return cons; 2855 } 2856 2857 static int 2858 bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget) 2859 { 2860 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; 2861 u16 hw_cons, sw_cons, sw_ring_cons; 2862 int tx_pkt = 0, index; 2863 unsigned int tx_bytes = 0; 2864 struct netdev_queue *txq; 2865 2866 index = (bnapi - bp->bnx2_napi); 2867 txq = netdev_get_tx_queue(bp->dev, index); 2868 2869 hw_cons = bnx2_get_hw_tx_cons(bnapi); 2870 sw_cons = txr->tx_cons; 2871 2872 while (sw_cons != hw_cons) { 2873 struct bnx2_sw_tx_bd *tx_buf; 2874 struct sk_buff *skb; 2875 int i, last; 2876 2877 sw_ring_cons = BNX2_TX_RING_IDX(sw_cons); 2878 2879 tx_buf = &txr->tx_buf_ring[sw_ring_cons]; 2880 skb = tx_buf->skb; 2881 2882 /* prefetch skb_end_pointer() to speedup skb_shinfo(skb) */ 2883 prefetch(&skb->end); 2884 2885 /* partial BD completions possible with TSO packets */ 2886 if (tx_buf->is_gso) { 2887 u16 last_idx, last_ring_idx; 2888 2889 last_idx = sw_cons + tx_buf->nr_frags + 1; 2890 last_ring_idx = sw_ring_cons + tx_buf->nr_frags + 1; 2891 if (unlikely(last_ring_idx >= BNX2_MAX_TX_DESC_CNT)) { 2892 last_idx++; 2893 } 2894 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) { 2895 break; 2896 } 2897 } 2898 2899 dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping), 2900 skb_headlen(skb), DMA_TO_DEVICE); 2901 2902 tx_buf->skb = NULL; 2903 last = tx_buf->nr_frags; 2904 2905 for (i = 0; i < last; i++) { 2906 struct bnx2_sw_tx_bd *tx_buf; 2907 2908 sw_cons = BNX2_NEXT_TX_BD(sw_cons); 2909 2910 tx_buf = &txr->tx_buf_ring[BNX2_TX_RING_IDX(sw_cons)]; 2911 dma_unmap_page(&bp->pdev->dev, 2912 dma_unmap_addr(tx_buf, mapping), 2913 skb_frag_size(&skb_shinfo(skb)->frags[i]), 2914 DMA_TO_DEVICE); 2915 } 2916 2917 sw_cons = BNX2_NEXT_TX_BD(sw_cons); 2918 2919 tx_bytes += skb->len; 2920 dev_kfree_skb_any(skb); 2921 tx_pkt++; 2922 if (tx_pkt == budget) 2923 break; 2924 2925 if (hw_cons == sw_cons) 2926 hw_cons = bnx2_get_hw_tx_cons(bnapi); 2927 } 2928 2929 netdev_tx_completed_queue(txq, tx_pkt, tx_bytes); 2930 txr->hw_tx_cons = hw_cons; 2931 txr->tx_cons = sw_cons; 2932 2933 /* Need to make the tx_cons update visible to bnx2_start_xmit() 2934 * before checking for netif_tx_queue_stopped(). Without the 2935 * memory barrier, there is a small possibility that bnx2_start_xmit() 2936 * will miss it and cause the queue to be stopped forever. 2937 */ 2938 smp_mb(); 2939 2940 if (unlikely(netif_tx_queue_stopped(txq)) && 2941 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) { 2942 __netif_tx_lock(txq, smp_processor_id()); 2943 if ((netif_tx_queue_stopped(txq)) && 2944 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) 2945 netif_tx_wake_queue(txq); 2946 __netif_tx_unlock(txq); 2947 } 2948 2949 return tx_pkt; 2950 } 2951 2952 static void 2953 bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, 2954 struct sk_buff *skb, int count) 2955 { 2956 struct bnx2_sw_pg *cons_rx_pg, *prod_rx_pg; 2957 struct bnx2_rx_bd *cons_bd, *prod_bd; 2958 int i; 2959 u16 hw_prod, prod; 2960 u16 cons = rxr->rx_pg_cons; 2961 2962 cons_rx_pg = &rxr->rx_pg_ring[cons]; 2963 2964 /* The caller was unable to allocate a new page to replace the 2965 * last one in the frags array, so we need to recycle that page 2966 * and then free the skb. 2967 */ 2968 if (skb) { 2969 struct page *page; 2970 struct skb_shared_info *shinfo; 2971 2972 shinfo = skb_shinfo(skb); 2973 shinfo->nr_frags--; 2974 page = skb_frag_page(&shinfo->frags[shinfo->nr_frags]); 2975 2976 cons_rx_pg->page = page; 2977 dev_kfree_skb(skb); 2978 } 2979 2980 hw_prod = rxr->rx_pg_prod; 2981 2982 for (i = 0; i < count; i++) { 2983 prod = BNX2_RX_PG_RING_IDX(hw_prod); 2984 2985 prod_rx_pg = &rxr->rx_pg_ring[prod]; 2986 cons_rx_pg = &rxr->rx_pg_ring[cons]; 2987 cons_bd = &rxr->rx_pg_desc_ring[BNX2_RX_RING(cons)] 2988 [BNX2_RX_IDX(cons)]; 2989 prod_bd = &rxr->rx_pg_desc_ring[BNX2_RX_RING(prod)] 2990 [BNX2_RX_IDX(prod)]; 2991 2992 if (prod != cons) { 2993 prod_rx_pg->page = cons_rx_pg->page; 2994 cons_rx_pg->page = NULL; 2995 dma_unmap_addr_set(prod_rx_pg, mapping, 2996 dma_unmap_addr(cons_rx_pg, mapping)); 2997 2998 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi; 2999 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo; 3000 3001 } 3002 cons = BNX2_RX_PG_RING_IDX(BNX2_NEXT_RX_BD(cons)); 3003 hw_prod = BNX2_NEXT_RX_BD(hw_prod); 3004 } 3005 rxr->rx_pg_prod = hw_prod; 3006 rxr->rx_pg_cons = cons; 3007 } 3008 3009 static inline void 3010 bnx2_reuse_rx_data(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, 3011 u8 *data, u16 cons, u16 prod) 3012 { 3013 struct bnx2_sw_bd *cons_rx_buf, *prod_rx_buf; 3014 struct bnx2_rx_bd *cons_bd, *prod_bd; 3015 3016 cons_rx_buf = &rxr->rx_buf_ring[cons]; 3017 prod_rx_buf = &rxr->rx_buf_ring[prod]; 3018 3019 dma_sync_single_for_device(&bp->pdev->dev, 3020 dma_unmap_addr(cons_rx_buf, mapping), 3021 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, DMA_FROM_DEVICE); 3022 3023 rxr->rx_prod_bseq += bp->rx_buf_use_size; 3024 3025 prod_rx_buf->data = data; 3026 3027 if (cons == prod) 3028 return; 3029 3030 dma_unmap_addr_set(prod_rx_buf, mapping, 3031 dma_unmap_addr(cons_rx_buf, mapping)); 3032 3033 cons_bd = &rxr->rx_desc_ring[BNX2_RX_RING(cons)][BNX2_RX_IDX(cons)]; 3034 prod_bd = &rxr->rx_desc_ring[BNX2_RX_RING(prod)][BNX2_RX_IDX(prod)]; 3035 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi; 3036 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo; 3037 } 3038 3039 static struct sk_buff * 3040 bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u8 *data, 3041 unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr, 3042 u32 ring_idx) 3043 { 3044 int err; 3045 u16 prod = ring_idx & 0xffff; 3046 struct sk_buff *skb; 3047 3048 err = bnx2_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC); 3049 if (unlikely(err)) { 3050 bnx2_reuse_rx_data(bp, rxr, data, (u16) (ring_idx >> 16), prod); 3051 error: 3052 if (hdr_len) { 3053 unsigned int raw_len = len + 4; 3054 int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT; 3055 3056 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages); 3057 } 3058 return NULL; 3059 } 3060 3061 dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size, 3062 DMA_FROM_DEVICE); 3063 skb = slab_build_skb(data); 3064 if (!skb) { 3065 kfree(data); 3066 goto error; 3067 } 3068 skb_reserve(skb, ((u8 *)get_l2_fhdr(data) - data) + BNX2_RX_OFFSET); 3069 if (hdr_len == 0) { 3070 skb_put(skb, len); 3071 return skb; 3072 } else { 3073 unsigned int i, frag_len, frag_size, pages; 3074 struct bnx2_sw_pg *rx_pg; 3075 u16 pg_cons = rxr->rx_pg_cons; 3076 u16 pg_prod = rxr->rx_pg_prod; 3077 3078 frag_size = len + 4 - hdr_len; 3079 pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT; 3080 skb_put(skb, hdr_len); 3081 3082 for (i = 0; i < pages; i++) { 3083 dma_addr_t mapping_old; 3084 3085 frag_len = min(frag_size, (unsigned int) PAGE_SIZE); 3086 if (unlikely(frag_len <= 4)) { 3087 unsigned int tail = 4 - frag_len; 3088 3089 rxr->rx_pg_cons = pg_cons; 3090 rxr->rx_pg_prod = pg_prod; 3091 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, 3092 pages - i); 3093 skb->len -= tail; 3094 if (i == 0) { 3095 skb->tail -= tail; 3096 } else { 3097 skb_frag_t *frag = 3098 &skb_shinfo(skb)->frags[i - 1]; 3099 skb_frag_size_sub(frag, tail); 3100 skb->data_len -= tail; 3101 } 3102 return skb; 3103 } 3104 rx_pg = &rxr->rx_pg_ring[pg_cons]; 3105 3106 /* Don't unmap yet. If we're unable to allocate a new 3107 * page, we need to recycle the page and the DMA addr. 3108 */ 3109 mapping_old = dma_unmap_addr(rx_pg, mapping); 3110 if (i == pages - 1) 3111 frag_len -= 4; 3112 3113 skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len); 3114 rx_pg->page = NULL; 3115 3116 err = bnx2_alloc_rx_page(bp, rxr, 3117 BNX2_RX_PG_RING_IDX(pg_prod), 3118 GFP_ATOMIC); 3119 if (unlikely(err)) { 3120 rxr->rx_pg_cons = pg_cons; 3121 rxr->rx_pg_prod = pg_prod; 3122 bnx2_reuse_rx_skb_pages(bp, rxr, skb, 3123 pages - i); 3124 return NULL; 3125 } 3126 3127 dma_unmap_page(&bp->pdev->dev, mapping_old, 3128 PAGE_SIZE, DMA_FROM_DEVICE); 3129 3130 frag_size -= frag_len; 3131 skb->data_len += frag_len; 3132 skb->truesize += PAGE_SIZE; 3133 skb->len += frag_len; 3134 3135 pg_prod = BNX2_NEXT_RX_BD(pg_prod); 3136 pg_cons = BNX2_RX_PG_RING_IDX(BNX2_NEXT_RX_BD(pg_cons)); 3137 } 3138 rxr->rx_pg_prod = pg_prod; 3139 rxr->rx_pg_cons = pg_cons; 3140 } 3141 return skb; 3142 } 3143 3144 static inline u16 3145 bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi) 3146 { 3147 u16 cons; 3148 3149 cons = READ_ONCE(*bnapi->hw_rx_cons_ptr); 3150 3151 if (unlikely((cons & BNX2_MAX_RX_DESC_CNT) == BNX2_MAX_RX_DESC_CNT)) 3152 cons++; 3153 return cons; 3154 } 3155 3156 static int 3157 bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget) 3158 { 3159 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; 3160 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod; 3161 struct l2_fhdr *rx_hdr; 3162 int rx_pkt = 0, pg_ring_used = 0; 3163 3164 if (budget <= 0) 3165 return rx_pkt; 3166 3167 hw_cons = bnx2_get_hw_rx_cons(bnapi); 3168 sw_cons = rxr->rx_cons; 3169 sw_prod = rxr->rx_prod; 3170 3171 /* Memory barrier necessary as speculative reads of the rx 3172 * buffer can be ahead of the index in the status block 3173 */ 3174 rmb(); 3175 while (sw_cons != hw_cons) { 3176 unsigned int len, hdr_len; 3177 u32 status; 3178 struct bnx2_sw_bd *rx_buf, *next_rx_buf; 3179 struct sk_buff *skb; 3180 dma_addr_t dma_addr; 3181 u8 *data; 3182 u16 next_ring_idx; 3183 3184 sw_ring_cons = BNX2_RX_RING_IDX(sw_cons); 3185 sw_ring_prod = BNX2_RX_RING_IDX(sw_prod); 3186 3187 rx_buf = &rxr->rx_buf_ring[sw_ring_cons]; 3188 data = rx_buf->data; 3189 rx_buf->data = NULL; 3190 3191 rx_hdr = get_l2_fhdr(data); 3192 prefetch(rx_hdr); 3193 3194 dma_addr = dma_unmap_addr(rx_buf, mapping); 3195 3196 dma_sync_single_for_cpu(&bp->pdev->dev, dma_addr, 3197 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, 3198 DMA_FROM_DEVICE); 3199 3200 next_ring_idx = BNX2_RX_RING_IDX(BNX2_NEXT_RX_BD(sw_cons)); 3201 next_rx_buf = &rxr->rx_buf_ring[next_ring_idx]; 3202 prefetch(get_l2_fhdr(next_rx_buf->data)); 3203 3204 len = rx_hdr->l2_fhdr_pkt_len; 3205 status = rx_hdr->l2_fhdr_status; 3206 3207 hdr_len = 0; 3208 if (status & L2_FHDR_STATUS_SPLIT) { 3209 hdr_len = rx_hdr->l2_fhdr_ip_xsum; 3210 pg_ring_used = 1; 3211 } else if (len > bp->rx_jumbo_thresh) { 3212 hdr_len = bp->rx_jumbo_thresh; 3213 pg_ring_used = 1; 3214 } 3215 3216 if (unlikely(status & (L2_FHDR_ERRORS_BAD_CRC | 3217 L2_FHDR_ERRORS_PHY_DECODE | 3218 L2_FHDR_ERRORS_ALIGNMENT | 3219 L2_FHDR_ERRORS_TOO_SHORT | 3220 L2_FHDR_ERRORS_GIANT_FRAME))) { 3221 3222 bnx2_reuse_rx_data(bp, rxr, data, sw_ring_cons, 3223 sw_ring_prod); 3224 if (pg_ring_used) { 3225 int pages; 3226 3227 pages = PAGE_ALIGN(len - hdr_len) >> PAGE_SHIFT; 3228 3229 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages); 3230 } 3231 goto next_rx; 3232 } 3233 3234 len -= 4; 3235 3236 if (len <= bp->rx_copy_thresh) { 3237 skb = netdev_alloc_skb(bp->dev, len + 6); 3238 if (!skb) { 3239 bnx2_reuse_rx_data(bp, rxr, data, sw_ring_cons, 3240 sw_ring_prod); 3241 goto next_rx; 3242 } 3243 3244 /* aligned copy */ 3245 memcpy(skb->data, 3246 (u8 *)rx_hdr + BNX2_RX_OFFSET - 6, 3247 len + 6); 3248 skb_reserve(skb, 6); 3249 skb_put(skb, len); 3250 3251 bnx2_reuse_rx_data(bp, rxr, data, 3252 sw_ring_cons, sw_ring_prod); 3253 3254 } else { 3255 skb = bnx2_rx_skb(bp, rxr, data, len, hdr_len, dma_addr, 3256 (sw_ring_cons << 16) | sw_ring_prod); 3257 if (!skb) 3258 goto next_rx; 3259 } 3260 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && 3261 !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) 3262 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), rx_hdr->l2_fhdr_vlan_tag); 3263 3264 skb->protocol = eth_type_trans(skb, bp->dev); 3265 3266 if (len > (bp->dev->mtu + ETH_HLEN) && 3267 skb->protocol != htons(0x8100) && 3268 skb->protocol != htons(ETH_P_8021AD)) { 3269 3270 dev_kfree_skb(skb); 3271 goto next_rx; 3272 3273 } 3274 3275 skb_checksum_none_assert(skb); 3276 if ((bp->dev->features & NETIF_F_RXCSUM) && 3277 (status & (L2_FHDR_STATUS_TCP_SEGMENT | 3278 L2_FHDR_STATUS_UDP_DATAGRAM))) { 3279 3280 if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM | 3281 L2_FHDR_ERRORS_UDP_XSUM)) == 0)) 3282 skb->ip_summed = CHECKSUM_UNNECESSARY; 3283 } 3284 if ((bp->dev->features & NETIF_F_RXHASH) && 3285 ((status & L2_FHDR_STATUS_USE_RXHASH) == 3286 L2_FHDR_STATUS_USE_RXHASH)) 3287 skb_set_hash(skb, rx_hdr->l2_fhdr_hash, 3288 PKT_HASH_TYPE_L3); 3289 3290 skb_record_rx_queue(skb, bnapi - &bp->bnx2_napi[0]); 3291 napi_gro_receive(&bnapi->napi, skb); 3292 rx_pkt++; 3293 3294 next_rx: 3295 sw_cons = BNX2_NEXT_RX_BD(sw_cons); 3296 sw_prod = BNX2_NEXT_RX_BD(sw_prod); 3297 3298 if (rx_pkt == budget) 3299 break; 3300 3301 /* Refresh hw_cons to see if there is new work */ 3302 if (sw_cons == hw_cons) { 3303 hw_cons = bnx2_get_hw_rx_cons(bnapi); 3304 rmb(); 3305 } 3306 } 3307 rxr->rx_cons = sw_cons; 3308 rxr->rx_prod = sw_prod; 3309 3310 if (pg_ring_used) 3311 BNX2_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod); 3312 3313 BNX2_WR16(bp, rxr->rx_bidx_addr, sw_prod); 3314 3315 BNX2_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq); 3316 3317 return rx_pkt; 3318 3319 } 3320 3321 /* MSI ISR - The only difference between this and the INTx ISR 3322 * is that the MSI interrupt is always serviced. 3323 */ 3324 static irqreturn_t 3325 bnx2_msi(int irq, void *dev_instance) 3326 { 3327 struct bnx2_napi *bnapi = dev_instance; 3328 struct bnx2 *bp = bnapi->bp; 3329 3330 prefetch(bnapi->status_blk.msi); 3331 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, 3332 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | 3333 BNX2_PCICFG_INT_ACK_CMD_MASK_INT); 3334 3335 /* Return here if interrupt is disabled. */ 3336 if (unlikely(atomic_read(&bp->intr_sem) != 0)) 3337 return IRQ_HANDLED; 3338 3339 napi_schedule(&bnapi->napi); 3340 3341 return IRQ_HANDLED; 3342 } 3343 3344 static irqreturn_t 3345 bnx2_msi_1shot(int irq, void *dev_instance) 3346 { 3347 struct bnx2_napi *bnapi = dev_instance; 3348 struct bnx2 *bp = bnapi->bp; 3349 3350 prefetch(bnapi->status_blk.msi); 3351 3352 /* Return here if interrupt is disabled. */ 3353 if (unlikely(atomic_read(&bp->intr_sem) != 0)) 3354 return IRQ_HANDLED; 3355 3356 napi_schedule(&bnapi->napi); 3357 3358 return IRQ_HANDLED; 3359 } 3360 3361 static irqreturn_t 3362 bnx2_interrupt(int irq, void *dev_instance) 3363 { 3364 struct bnx2_napi *bnapi = dev_instance; 3365 struct bnx2 *bp = bnapi->bp; 3366 struct status_block *sblk = bnapi->status_blk.msi; 3367 3368 /* When using INTx, it is possible for the interrupt to arrive 3369 * at the CPU before the status block posted prior to the 3370 * interrupt. Reading a register will flush the status block. 3371 * When using MSI, the MSI message will always complete after 3372 * the status block write. 3373 */ 3374 if ((sblk->status_idx == bnapi->last_status_idx) && 3375 (BNX2_RD(bp, BNX2_PCICFG_MISC_STATUS) & 3376 BNX2_PCICFG_MISC_STATUS_INTA_VALUE)) 3377 return IRQ_NONE; 3378 3379 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, 3380 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | 3381 BNX2_PCICFG_INT_ACK_CMD_MASK_INT); 3382 3383 /* Read back to deassert IRQ immediately to avoid too many 3384 * spurious interrupts. 3385 */ 3386 BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD); 3387 3388 /* Return here if interrupt is shared and is disabled. */ 3389 if (unlikely(atomic_read(&bp->intr_sem) != 0)) 3390 return IRQ_HANDLED; 3391 3392 if (napi_schedule_prep(&bnapi->napi)) { 3393 bnapi->last_status_idx = sblk->status_idx; 3394 __napi_schedule(&bnapi->napi); 3395 } 3396 3397 return IRQ_HANDLED; 3398 } 3399 3400 static inline int 3401 bnx2_has_fast_work(struct bnx2_napi *bnapi) 3402 { 3403 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; 3404 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; 3405 3406 if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) || 3407 (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)) 3408 return 1; 3409 return 0; 3410 } 3411 3412 #define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \ 3413 STATUS_ATTN_BITS_TIMER_ABORT) 3414 3415 static inline int 3416 bnx2_has_work(struct bnx2_napi *bnapi) 3417 { 3418 struct status_block *sblk = bnapi->status_blk.msi; 3419 3420 if (bnx2_has_fast_work(bnapi)) 3421 return 1; 3422 3423 #ifdef BCM_CNIC 3424 if (bnapi->cnic_present && (bnapi->cnic_tag != sblk->status_idx)) 3425 return 1; 3426 #endif 3427 3428 if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) != 3429 (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS)) 3430 return 1; 3431 3432 return 0; 3433 } 3434 3435 static void 3436 bnx2_chk_missed_msi(struct bnx2 *bp) 3437 { 3438 struct bnx2_napi *bnapi = &bp->bnx2_napi[0]; 3439 u32 msi_ctrl; 3440 3441 if (bnx2_has_work(bnapi)) { 3442 msi_ctrl = BNX2_RD(bp, BNX2_PCICFG_MSI_CONTROL); 3443 if (!(msi_ctrl & BNX2_PCICFG_MSI_CONTROL_ENABLE)) 3444 return; 3445 3446 if (bnapi->last_status_idx == bp->idle_chk_status_idx) { 3447 BNX2_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl & 3448 ~BNX2_PCICFG_MSI_CONTROL_ENABLE); 3449 BNX2_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl); 3450 bnx2_msi(bp->irq_tbl[0].vector, bnapi); 3451 } 3452 } 3453 3454 bp->idle_chk_status_idx = bnapi->last_status_idx; 3455 } 3456 3457 #ifdef BCM_CNIC 3458 static void bnx2_poll_cnic(struct bnx2 *bp, struct bnx2_napi *bnapi) 3459 { 3460 struct cnic_ops *c_ops; 3461 3462 if (!bnapi->cnic_present) 3463 return; 3464 3465 rcu_read_lock(); 3466 c_ops = rcu_dereference(bp->cnic_ops); 3467 if (c_ops) 3468 bnapi->cnic_tag = c_ops->cnic_handler(bp->cnic_data, 3469 bnapi->status_blk.msi); 3470 rcu_read_unlock(); 3471 } 3472 #endif 3473 3474 static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi) 3475 { 3476 struct status_block *sblk = bnapi->status_blk.msi; 3477 u32 status_attn_bits = sblk->status_attn_bits; 3478 u32 status_attn_bits_ack = sblk->status_attn_bits_ack; 3479 3480 if ((status_attn_bits & STATUS_ATTN_EVENTS) != 3481 (status_attn_bits_ack & STATUS_ATTN_EVENTS)) { 3482 3483 bnx2_phy_int(bp, bnapi); 3484 3485 /* This is needed to take care of transient status 3486 * during link changes. 3487 */ 3488 BNX2_WR(bp, BNX2_HC_COMMAND, 3489 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT); 3490 BNX2_RD(bp, BNX2_HC_COMMAND); 3491 } 3492 } 3493 3494 static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi, 3495 int work_done, int budget) 3496 { 3497 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; 3498 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; 3499 3500 if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons) 3501 bnx2_tx_int(bp, bnapi, 0); 3502 3503 if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) 3504 work_done += bnx2_rx_int(bp, bnapi, budget - work_done); 3505 3506 return work_done; 3507 } 3508 3509 static int bnx2_poll_msix(struct napi_struct *napi, int budget) 3510 { 3511 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi); 3512 struct bnx2 *bp = bnapi->bp; 3513 int work_done = 0; 3514 struct status_block_msix *sblk = bnapi->status_blk.msix; 3515 3516 while (1) { 3517 work_done = bnx2_poll_work(bp, bnapi, work_done, budget); 3518 if (unlikely(work_done >= budget)) 3519 break; 3520 3521 bnapi->last_status_idx = sblk->status_idx; 3522 /* status idx must be read before checking for more work. */ 3523 rmb(); 3524 if (likely(!bnx2_has_fast_work(bnapi))) { 3525 3526 napi_complete_done(napi, work_done); 3527 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num | 3528 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | 3529 bnapi->last_status_idx); 3530 break; 3531 } 3532 } 3533 return work_done; 3534 } 3535 3536 static int bnx2_poll(struct napi_struct *napi, int budget) 3537 { 3538 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi); 3539 struct bnx2 *bp = bnapi->bp; 3540 int work_done = 0; 3541 struct status_block *sblk = bnapi->status_blk.msi; 3542 3543 while (1) { 3544 bnx2_poll_link(bp, bnapi); 3545 3546 work_done = bnx2_poll_work(bp, bnapi, work_done, budget); 3547 3548 #ifdef BCM_CNIC 3549 bnx2_poll_cnic(bp, bnapi); 3550 #endif 3551 3552 /* bnapi->last_status_idx is used below to tell the hw how 3553 * much work has been processed, so we must read it before 3554 * checking for more work. 3555 */ 3556 bnapi->last_status_idx = sblk->status_idx; 3557 3558 if (unlikely(work_done >= budget)) 3559 break; 3560 3561 rmb(); 3562 if (likely(!bnx2_has_work(bnapi))) { 3563 napi_complete_done(napi, work_done); 3564 if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) { 3565 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, 3566 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | 3567 bnapi->last_status_idx); 3568 break; 3569 } 3570 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, 3571 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | 3572 BNX2_PCICFG_INT_ACK_CMD_MASK_INT | 3573 bnapi->last_status_idx); 3574 3575 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, 3576 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | 3577 bnapi->last_status_idx); 3578 break; 3579 } 3580 } 3581 3582 return work_done; 3583 } 3584 3585 /* Called with rtnl_lock from vlan functions and also netif_tx_lock 3586 * from set_multicast. 3587 */ 3588 static void 3589 bnx2_set_rx_mode(struct net_device *dev) 3590 { 3591 struct bnx2 *bp = netdev_priv(dev); 3592 u32 rx_mode, sort_mode; 3593 struct netdev_hw_addr *ha; 3594 int i; 3595 3596 if (!netif_running(dev)) 3597 return; 3598 3599 spin_lock_bh(&bp->phy_lock); 3600 3601 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS | 3602 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG); 3603 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN; 3604 if (!(dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 3605 (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)) 3606 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG; 3607 if (dev->flags & IFF_PROMISC) { 3608 /* Promiscuous mode. */ 3609 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS; 3610 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN | 3611 BNX2_RPM_SORT_USER0_PROM_VLAN; 3612 } 3613 else if (dev->flags & IFF_ALLMULTI) { 3614 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { 3615 BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4), 3616 0xffffffff); 3617 } 3618 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN; 3619 } 3620 else { 3621 /* Accept one or more multicast(s). */ 3622 u32 mc_filter[NUM_MC_HASH_REGISTERS]; 3623 u32 regidx; 3624 u32 bit; 3625 u32 crc; 3626 3627 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS); 3628 3629 netdev_for_each_mc_addr(ha, dev) { 3630 crc = ether_crc_le(ETH_ALEN, ha->addr); 3631 bit = crc & 0xff; 3632 regidx = (bit & 0xe0) >> 5; 3633 bit &= 0x1f; 3634 mc_filter[regidx] |= (1 << bit); 3635 } 3636 3637 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { 3638 BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4), 3639 mc_filter[i]); 3640 } 3641 3642 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN; 3643 } 3644 3645 if (netdev_uc_count(dev) > BNX2_MAX_UNICAST_ADDRESSES) { 3646 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS; 3647 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN | 3648 BNX2_RPM_SORT_USER0_PROM_VLAN; 3649 } else if (!(dev->flags & IFF_PROMISC)) { 3650 /* Add all entries into to the match filter list */ 3651 i = 0; 3652 netdev_for_each_uc_addr(ha, dev) { 3653 bnx2_set_mac_addr(bp, ha->addr, 3654 i + BNX2_START_UNICAST_ADDRESS_INDEX); 3655 sort_mode |= (1 << 3656 (i + BNX2_START_UNICAST_ADDRESS_INDEX)); 3657 i++; 3658 } 3659 3660 } 3661 3662 if (rx_mode != bp->rx_mode) { 3663 bp->rx_mode = rx_mode; 3664 BNX2_WR(bp, BNX2_EMAC_RX_MODE, rx_mode); 3665 } 3666 3667 BNX2_WR(bp, BNX2_RPM_SORT_USER0, 0x0); 3668 BNX2_WR(bp, BNX2_RPM_SORT_USER0, sort_mode); 3669 BNX2_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA); 3670 3671 spin_unlock_bh(&bp->phy_lock); 3672 } 3673 3674 static int 3675 check_fw_section(const struct firmware *fw, 3676 const struct bnx2_fw_file_section *section, 3677 u32 alignment, bool non_empty) 3678 { 3679 u32 offset = be32_to_cpu(section->offset); 3680 u32 len = be32_to_cpu(section->len); 3681 3682 if ((offset == 0 && len != 0) || offset >= fw->size || offset & 3) 3683 return -EINVAL; 3684 if ((non_empty && len == 0) || len > fw->size - offset || 3685 len & (alignment - 1)) 3686 return -EINVAL; 3687 return 0; 3688 } 3689 3690 static int 3691 check_mips_fw_entry(const struct firmware *fw, 3692 const struct bnx2_mips_fw_file_entry *entry) 3693 { 3694 if (check_fw_section(fw, &entry->text, 4, true) || 3695 check_fw_section(fw, &entry->data, 4, false) || 3696 check_fw_section(fw, &entry->rodata, 4, false)) 3697 return -EINVAL; 3698 return 0; 3699 } 3700 3701 static void bnx2_release_firmware(struct bnx2 *bp) 3702 { 3703 if (bp->rv2p_firmware) { 3704 release_firmware(bp->mips_firmware); 3705 release_firmware(bp->rv2p_firmware); 3706 bp->rv2p_firmware = NULL; 3707 } 3708 } 3709 3710 static int bnx2_request_uncached_firmware(struct bnx2 *bp) 3711 { 3712 const char *mips_fw_file, *rv2p_fw_file; 3713 const struct bnx2_mips_fw_file *mips_fw; 3714 const struct bnx2_rv2p_fw_file *rv2p_fw; 3715 int rc; 3716 3717 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { 3718 mips_fw_file = FW_MIPS_FILE_09; 3719 if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5709_A0) || 3720 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5709_A1)) 3721 rv2p_fw_file = FW_RV2P_FILE_09_Ax; 3722 else 3723 rv2p_fw_file = FW_RV2P_FILE_09; 3724 } else { 3725 mips_fw_file = FW_MIPS_FILE_06; 3726 rv2p_fw_file = FW_RV2P_FILE_06; 3727 } 3728 3729 rc = request_firmware(&bp->mips_firmware, mips_fw_file, &bp->pdev->dev); 3730 if (rc) { 3731 pr_err("Can't load firmware file \"%s\"\n", mips_fw_file); 3732 goto out; 3733 } 3734 3735 rc = request_firmware(&bp->rv2p_firmware, rv2p_fw_file, &bp->pdev->dev); 3736 if (rc) { 3737 pr_err("Can't load firmware file \"%s\"\n", rv2p_fw_file); 3738 goto err_release_mips_firmware; 3739 } 3740 mips_fw = (const struct bnx2_mips_fw_file *) bp->mips_firmware->data; 3741 rv2p_fw = (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data; 3742 if (bp->mips_firmware->size < sizeof(*mips_fw) || 3743 check_mips_fw_entry(bp->mips_firmware, &mips_fw->com) || 3744 check_mips_fw_entry(bp->mips_firmware, &mips_fw->cp) || 3745 check_mips_fw_entry(bp->mips_firmware, &mips_fw->rxp) || 3746 check_mips_fw_entry(bp->mips_firmware, &mips_fw->tpat) || 3747 check_mips_fw_entry(bp->mips_firmware, &mips_fw->txp)) { 3748 pr_err("Firmware file \"%s\" is invalid\n", mips_fw_file); 3749 rc = -EINVAL; 3750 goto err_release_firmware; 3751 } 3752 if (bp->rv2p_firmware->size < sizeof(*rv2p_fw) || 3753 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc1.rv2p, 8, true) || 3754 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc2.rv2p, 8, true)) { 3755 pr_err("Firmware file \"%s\" is invalid\n", rv2p_fw_file); 3756 rc = -EINVAL; 3757 goto err_release_firmware; 3758 } 3759 out: 3760 return rc; 3761 3762 err_release_firmware: 3763 release_firmware(bp->rv2p_firmware); 3764 bp->rv2p_firmware = NULL; 3765 err_release_mips_firmware: 3766 release_firmware(bp->mips_firmware); 3767 goto out; 3768 } 3769 3770 static int bnx2_request_firmware(struct bnx2 *bp) 3771 { 3772 return bp->rv2p_firmware ? 0 : bnx2_request_uncached_firmware(bp); 3773 } 3774 3775 static u32 3776 rv2p_fw_fixup(u32 rv2p_proc, int idx, u32 loc, u32 rv2p_code) 3777 { 3778 switch (idx) { 3779 case RV2P_P1_FIXUP_PAGE_SIZE_IDX: 3780 rv2p_code &= ~RV2P_BD_PAGE_SIZE_MSK; 3781 rv2p_code |= RV2P_BD_PAGE_SIZE; 3782 break; 3783 } 3784 return rv2p_code; 3785 } 3786 3787 static int 3788 load_rv2p_fw(struct bnx2 *bp, u32 rv2p_proc, 3789 const struct bnx2_rv2p_fw_file_entry *fw_entry) 3790 { 3791 u32 rv2p_code_len, file_offset; 3792 __be32 *rv2p_code; 3793 int i; 3794 u32 val, cmd, addr; 3795 3796 rv2p_code_len = be32_to_cpu(fw_entry->rv2p.len); 3797 file_offset = be32_to_cpu(fw_entry->rv2p.offset); 3798 3799 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset); 3800 3801 if (rv2p_proc == RV2P_PROC1) { 3802 cmd = BNX2_RV2P_PROC1_ADDR_CMD_RDWR; 3803 addr = BNX2_RV2P_PROC1_ADDR_CMD; 3804 } else { 3805 cmd = BNX2_RV2P_PROC2_ADDR_CMD_RDWR; 3806 addr = BNX2_RV2P_PROC2_ADDR_CMD; 3807 } 3808 3809 for (i = 0; i < rv2p_code_len; i += 8) { 3810 BNX2_WR(bp, BNX2_RV2P_INSTR_HIGH, be32_to_cpu(*rv2p_code)); 3811 rv2p_code++; 3812 BNX2_WR(bp, BNX2_RV2P_INSTR_LOW, be32_to_cpu(*rv2p_code)); 3813 rv2p_code++; 3814 3815 val = (i / 8) | cmd; 3816 BNX2_WR(bp, addr, val); 3817 } 3818 3819 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset); 3820 for (i = 0; i < 8; i++) { 3821 u32 loc, code; 3822 3823 loc = be32_to_cpu(fw_entry->fixup[i]); 3824 if (loc && ((loc * 4) < rv2p_code_len)) { 3825 code = be32_to_cpu(*(rv2p_code + loc - 1)); 3826 BNX2_WR(bp, BNX2_RV2P_INSTR_HIGH, code); 3827 code = be32_to_cpu(*(rv2p_code + loc)); 3828 code = rv2p_fw_fixup(rv2p_proc, i, loc, code); 3829 BNX2_WR(bp, BNX2_RV2P_INSTR_LOW, code); 3830 3831 val = (loc / 2) | cmd; 3832 BNX2_WR(bp, addr, val); 3833 } 3834 } 3835 3836 /* Reset the processor, un-stall is done later. */ 3837 if (rv2p_proc == RV2P_PROC1) { 3838 BNX2_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET); 3839 } 3840 else { 3841 BNX2_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET); 3842 } 3843 3844 return 0; 3845 } 3846 3847 static void 3848 load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg, 3849 const struct bnx2_mips_fw_file_entry *fw_entry) 3850 { 3851 u32 addr, len, file_offset; 3852 __be32 *data; 3853 u32 offset; 3854 u32 val; 3855 3856 /* Halt the CPU. */ 3857 val = bnx2_reg_rd_ind(bp, cpu_reg->mode); 3858 val |= cpu_reg->mode_value_halt; 3859 bnx2_reg_wr_ind(bp, cpu_reg->mode, val); 3860 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear); 3861 3862 /* Load the Text area. */ 3863 addr = be32_to_cpu(fw_entry->text.addr); 3864 len = be32_to_cpu(fw_entry->text.len); 3865 file_offset = be32_to_cpu(fw_entry->text.offset); 3866 data = (__be32 *)(bp->mips_firmware->data + file_offset); 3867 3868 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base); 3869 if (len) { 3870 int j; 3871 3872 for (j = 0; j < (len / 4); j++, offset += 4) 3873 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j])); 3874 } 3875 3876 /* Load the Data area. */ 3877 addr = be32_to_cpu(fw_entry->data.addr); 3878 len = be32_to_cpu(fw_entry->data.len); 3879 file_offset = be32_to_cpu(fw_entry->data.offset); 3880 data = (__be32 *)(bp->mips_firmware->data + file_offset); 3881 3882 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base); 3883 if (len) { 3884 int j; 3885 3886 for (j = 0; j < (len / 4); j++, offset += 4) 3887 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j])); 3888 } 3889 3890 /* Load the Read-Only area. */ 3891 addr = be32_to_cpu(fw_entry->rodata.addr); 3892 len = be32_to_cpu(fw_entry->rodata.len); 3893 file_offset = be32_to_cpu(fw_entry->rodata.offset); 3894 data = (__be32 *)(bp->mips_firmware->data + file_offset); 3895 3896 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base); 3897 if (len) { 3898 int j; 3899 3900 for (j = 0; j < (len / 4); j++, offset += 4) 3901 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j])); 3902 } 3903 3904 /* Clear the pre-fetch instruction. */ 3905 bnx2_reg_wr_ind(bp, cpu_reg->inst, 0); 3906 3907 val = be32_to_cpu(fw_entry->start_addr); 3908 bnx2_reg_wr_ind(bp, cpu_reg->pc, val); 3909 3910 /* Start the CPU. */ 3911 val = bnx2_reg_rd_ind(bp, cpu_reg->mode); 3912 val &= ~cpu_reg->mode_value_halt; 3913 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear); 3914 bnx2_reg_wr_ind(bp, cpu_reg->mode, val); 3915 } 3916 3917 static void 3918 bnx2_init_cpus(struct bnx2 *bp) 3919 { 3920 const struct bnx2_mips_fw_file *mips_fw = 3921 (const struct bnx2_mips_fw_file *) bp->mips_firmware->data; 3922 const struct bnx2_rv2p_fw_file *rv2p_fw = 3923 (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data; 3924 3925 /* Initialize the RV2P processor. */ 3926 load_rv2p_fw(bp, RV2P_PROC1, &rv2p_fw->proc1); 3927 load_rv2p_fw(bp, RV2P_PROC2, &rv2p_fw->proc2); 3928 3929 /* Initialize the RX Processor. */ 3930 load_cpu_fw(bp, &cpu_reg_rxp, &mips_fw->rxp); 3931 3932 /* Initialize the TX Processor. */ 3933 load_cpu_fw(bp, &cpu_reg_txp, &mips_fw->txp); 3934 3935 /* Initialize the TX Patch-up Processor. */ 3936 load_cpu_fw(bp, &cpu_reg_tpat, &mips_fw->tpat); 3937 3938 /* Initialize the Completion Processor. */ 3939 load_cpu_fw(bp, &cpu_reg_com, &mips_fw->com); 3940 3941 /* Initialize the Command Processor. */ 3942 load_cpu_fw(bp, &cpu_reg_cp, &mips_fw->cp); 3943 } 3944 3945 static void 3946 bnx2_setup_wol(struct bnx2 *bp) 3947 { 3948 int i; 3949 u32 val, wol_msg; 3950 3951 if (bp->wol) { 3952 u32 advertising; 3953 u8 autoneg; 3954 3955 autoneg = bp->autoneg; 3956 advertising = bp->advertising; 3957 3958 if (bp->phy_port == PORT_TP) { 3959 bp->autoneg = AUTONEG_SPEED; 3960 bp->advertising = ADVERTISED_10baseT_Half | 3961 ADVERTISED_10baseT_Full | 3962 ADVERTISED_100baseT_Half | 3963 ADVERTISED_100baseT_Full | 3964 ADVERTISED_Autoneg; 3965 } 3966 3967 spin_lock_bh(&bp->phy_lock); 3968 bnx2_setup_phy(bp, bp->phy_port); 3969 spin_unlock_bh(&bp->phy_lock); 3970 3971 bp->autoneg = autoneg; 3972 bp->advertising = advertising; 3973 3974 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0); 3975 3976 val = BNX2_RD(bp, BNX2_EMAC_MODE); 3977 3978 /* Enable port mode. */ 3979 val &= ~BNX2_EMAC_MODE_PORT; 3980 val |= BNX2_EMAC_MODE_MPKT_RCVD | 3981 BNX2_EMAC_MODE_ACPI_RCVD | 3982 BNX2_EMAC_MODE_MPKT; 3983 if (bp->phy_port == PORT_TP) { 3984 val |= BNX2_EMAC_MODE_PORT_MII; 3985 } else { 3986 val |= BNX2_EMAC_MODE_PORT_GMII; 3987 if (bp->line_speed == SPEED_2500) 3988 val |= BNX2_EMAC_MODE_25G_MODE; 3989 } 3990 3991 BNX2_WR(bp, BNX2_EMAC_MODE, val); 3992 3993 /* receive all multicast */ 3994 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { 3995 BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4), 3996 0xffffffff); 3997 } 3998 BNX2_WR(bp, BNX2_EMAC_RX_MODE, BNX2_EMAC_RX_MODE_SORT_MODE); 3999 4000 val = 1 | BNX2_RPM_SORT_USER0_BC_EN | BNX2_RPM_SORT_USER0_MC_EN; 4001 BNX2_WR(bp, BNX2_RPM_SORT_USER0, 0x0); 4002 BNX2_WR(bp, BNX2_RPM_SORT_USER0, val); 4003 BNX2_WR(bp, BNX2_RPM_SORT_USER0, val | BNX2_RPM_SORT_USER0_ENA); 4004 4005 /* Need to enable EMAC and RPM for WOL. */ 4006 BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS, 4007 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE | 4008 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE | 4009 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE); 4010 4011 val = BNX2_RD(bp, BNX2_RPM_CONFIG); 4012 val &= ~BNX2_RPM_CONFIG_ACPI_ENA; 4013 BNX2_WR(bp, BNX2_RPM_CONFIG, val); 4014 4015 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL; 4016 } else { 4017 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL; 4018 } 4019 4020 if (!(bp->flags & BNX2_FLAG_NO_WOL)) { 4021 u32 val; 4022 4023 wol_msg |= BNX2_DRV_MSG_DATA_WAIT3; 4024 if (bp->fw_last_msg || BNX2_CHIP(bp) != BNX2_CHIP_5709) { 4025 bnx2_fw_sync(bp, wol_msg, 1, 0); 4026 return; 4027 } 4028 /* Tell firmware not to power down the PHY yet, otherwise 4029 * the chip will take a long time to respond to MMIO reads. 4030 */ 4031 val = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE); 4032 bnx2_shmem_wr(bp, BNX2_PORT_FEATURE, 4033 val | BNX2_PORT_FEATURE_ASF_ENABLED); 4034 bnx2_fw_sync(bp, wol_msg, 1, 0); 4035 bnx2_shmem_wr(bp, BNX2_PORT_FEATURE, val); 4036 } 4037 4038 } 4039 4040 static int 4041 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state) 4042 { 4043 switch (state) { 4044 case PCI_D0: { 4045 u32 val; 4046 4047 pci_enable_wake(bp->pdev, PCI_D0, false); 4048 pci_set_power_state(bp->pdev, PCI_D0); 4049 4050 val = BNX2_RD(bp, BNX2_EMAC_MODE); 4051 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD; 4052 val &= ~BNX2_EMAC_MODE_MPKT; 4053 BNX2_WR(bp, BNX2_EMAC_MODE, val); 4054 4055 val = BNX2_RD(bp, BNX2_RPM_CONFIG); 4056 val &= ~BNX2_RPM_CONFIG_ACPI_ENA; 4057 BNX2_WR(bp, BNX2_RPM_CONFIG, val); 4058 break; 4059 } 4060 case PCI_D3hot: { 4061 bnx2_setup_wol(bp); 4062 pci_wake_from_d3(bp->pdev, bp->wol); 4063 if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) || 4064 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1)) { 4065 4066 if (bp->wol) 4067 pci_set_power_state(bp->pdev, PCI_D3hot); 4068 break; 4069 4070 } 4071 if (!bp->fw_last_msg && BNX2_CHIP(bp) == BNX2_CHIP_5709) { 4072 u32 val; 4073 4074 /* Tell firmware not to power down the PHY yet, 4075 * otherwise the other port may not respond to 4076 * MMIO reads. 4077 */ 4078 val = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION); 4079 val &= ~BNX2_CONDITION_PM_STATE_MASK; 4080 val |= BNX2_CONDITION_PM_STATE_UNPREP; 4081 bnx2_shmem_wr(bp, BNX2_BC_STATE_CONDITION, val); 4082 } 4083 pci_set_power_state(bp->pdev, PCI_D3hot); 4084 4085 /* No more memory access after this point until 4086 * device is brought back to D0. 4087 */ 4088 break; 4089 } 4090 default: 4091 return -EINVAL; 4092 } 4093 return 0; 4094 } 4095 4096 static int 4097 bnx2_acquire_nvram_lock(struct bnx2 *bp) 4098 { 4099 u32 val; 4100 int j; 4101 4102 /* Request access to the flash interface. */ 4103 BNX2_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2); 4104 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 4105 val = BNX2_RD(bp, BNX2_NVM_SW_ARB); 4106 if (val & BNX2_NVM_SW_ARB_ARB_ARB2) 4107 break; 4108 4109 udelay(5); 4110 } 4111 4112 if (j >= NVRAM_TIMEOUT_COUNT) 4113 return -EBUSY; 4114 4115 return 0; 4116 } 4117 4118 static int 4119 bnx2_release_nvram_lock(struct bnx2 *bp) 4120 { 4121 int j; 4122 u32 val; 4123 4124 /* Relinquish nvram interface. */ 4125 BNX2_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2); 4126 4127 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 4128 val = BNX2_RD(bp, BNX2_NVM_SW_ARB); 4129 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2)) 4130 break; 4131 4132 udelay(5); 4133 } 4134 4135 if (j >= NVRAM_TIMEOUT_COUNT) 4136 return -EBUSY; 4137 4138 return 0; 4139 } 4140 4141 4142 static int 4143 bnx2_enable_nvram_write(struct bnx2 *bp) 4144 { 4145 u32 val; 4146 4147 val = BNX2_RD(bp, BNX2_MISC_CFG); 4148 BNX2_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI); 4149 4150 if (bp->flash_info->flags & BNX2_NV_WREN) { 4151 int j; 4152 4153 BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE); 4154 BNX2_WR(bp, BNX2_NVM_COMMAND, 4155 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT); 4156 4157 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 4158 udelay(5); 4159 4160 val = BNX2_RD(bp, BNX2_NVM_COMMAND); 4161 if (val & BNX2_NVM_COMMAND_DONE) 4162 break; 4163 } 4164 4165 if (j >= NVRAM_TIMEOUT_COUNT) 4166 return -EBUSY; 4167 } 4168 return 0; 4169 } 4170 4171 static void 4172 bnx2_disable_nvram_write(struct bnx2 *bp) 4173 { 4174 u32 val; 4175 4176 val = BNX2_RD(bp, BNX2_MISC_CFG); 4177 BNX2_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN); 4178 } 4179 4180 4181 static void 4182 bnx2_enable_nvram_access(struct bnx2 *bp) 4183 { 4184 u32 val; 4185 4186 val = BNX2_RD(bp, BNX2_NVM_ACCESS_ENABLE); 4187 /* Enable both bits, even on read. */ 4188 BNX2_WR(bp, BNX2_NVM_ACCESS_ENABLE, 4189 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN); 4190 } 4191 4192 static void 4193 bnx2_disable_nvram_access(struct bnx2 *bp) 4194 { 4195 u32 val; 4196 4197 val = BNX2_RD(bp, BNX2_NVM_ACCESS_ENABLE); 4198 /* Disable both bits, even after read. */ 4199 BNX2_WR(bp, BNX2_NVM_ACCESS_ENABLE, 4200 val & ~(BNX2_NVM_ACCESS_ENABLE_EN | 4201 BNX2_NVM_ACCESS_ENABLE_WR_EN)); 4202 } 4203 4204 static int 4205 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset) 4206 { 4207 u32 cmd; 4208 int j; 4209 4210 if (bp->flash_info->flags & BNX2_NV_BUFFERED) 4211 /* Buffered flash, no erase needed */ 4212 return 0; 4213 4214 /* Build an erase command */ 4215 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR | 4216 BNX2_NVM_COMMAND_DOIT; 4217 4218 /* Need to clear DONE bit separately. */ 4219 BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE); 4220 4221 /* Address of the NVRAM to read from. */ 4222 BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE); 4223 4224 /* Issue an erase command. */ 4225 BNX2_WR(bp, BNX2_NVM_COMMAND, cmd); 4226 4227 /* Wait for completion. */ 4228 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 4229 u32 val; 4230 4231 udelay(5); 4232 4233 val = BNX2_RD(bp, BNX2_NVM_COMMAND); 4234 if (val & BNX2_NVM_COMMAND_DONE) 4235 break; 4236 } 4237 4238 if (j >= NVRAM_TIMEOUT_COUNT) 4239 return -EBUSY; 4240 4241 return 0; 4242 } 4243 4244 static int 4245 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags) 4246 { 4247 u32 cmd; 4248 int j; 4249 4250 /* Build the command word. */ 4251 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags; 4252 4253 /* Calculate an offset of a buffered flash, not needed for 5709. */ 4254 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) { 4255 offset = ((offset / bp->flash_info->page_size) << 4256 bp->flash_info->page_bits) + 4257 (offset % bp->flash_info->page_size); 4258 } 4259 4260 /* Need to clear DONE bit separately. */ 4261 BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE); 4262 4263 /* Address of the NVRAM to read from. */ 4264 BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE); 4265 4266 /* Issue a read command. */ 4267 BNX2_WR(bp, BNX2_NVM_COMMAND, cmd); 4268 4269 /* Wait for completion. */ 4270 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 4271 u32 val; 4272 4273 udelay(5); 4274 4275 val = BNX2_RD(bp, BNX2_NVM_COMMAND); 4276 if (val & BNX2_NVM_COMMAND_DONE) { 4277 __be32 v = cpu_to_be32(BNX2_RD(bp, BNX2_NVM_READ)); 4278 memcpy(ret_val, &v, 4); 4279 break; 4280 } 4281 } 4282 if (j >= NVRAM_TIMEOUT_COUNT) 4283 return -EBUSY; 4284 4285 return 0; 4286 } 4287 4288 4289 static int 4290 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags) 4291 { 4292 u32 cmd; 4293 __be32 val32; 4294 int j; 4295 4296 /* Build the command word. */ 4297 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags; 4298 4299 /* Calculate an offset of a buffered flash, not needed for 5709. */ 4300 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) { 4301 offset = ((offset / bp->flash_info->page_size) << 4302 bp->flash_info->page_bits) + 4303 (offset % bp->flash_info->page_size); 4304 } 4305 4306 /* Need to clear DONE bit separately. */ 4307 BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE); 4308 4309 memcpy(&val32, val, 4); 4310 4311 /* Write the data. */ 4312 BNX2_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32)); 4313 4314 /* Address of the NVRAM to write to. */ 4315 BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE); 4316 4317 /* Issue the write command. */ 4318 BNX2_WR(bp, BNX2_NVM_COMMAND, cmd); 4319 4320 /* Wait for completion. */ 4321 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 4322 udelay(5); 4323 4324 if (BNX2_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE) 4325 break; 4326 } 4327 if (j >= NVRAM_TIMEOUT_COUNT) 4328 return -EBUSY; 4329 4330 return 0; 4331 } 4332 4333 static int 4334 bnx2_init_nvram(struct bnx2 *bp) 4335 { 4336 u32 val; 4337 int j, entry_count, rc = 0; 4338 const struct flash_spec *flash; 4339 4340 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { 4341 bp->flash_info = &flash_5709; 4342 goto get_flash_size; 4343 } 4344 4345 /* Determine the selected interface. */ 4346 val = BNX2_RD(bp, BNX2_NVM_CFG1); 4347 4348 entry_count = ARRAY_SIZE(flash_table); 4349 4350 if (val & 0x40000000) { 4351 4352 /* Flash interface has been reconfigured */ 4353 for (j = 0, flash = &flash_table[0]; j < entry_count; 4354 j++, flash++) { 4355 if ((val & FLASH_BACKUP_STRAP_MASK) == 4356 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { 4357 bp->flash_info = flash; 4358 break; 4359 } 4360 } 4361 } 4362 else { 4363 u32 mask; 4364 /* Not yet been reconfigured */ 4365 4366 if (val & (1 << 23)) 4367 mask = FLASH_BACKUP_STRAP_MASK; 4368 else 4369 mask = FLASH_STRAP_MASK; 4370 4371 for (j = 0, flash = &flash_table[0]; j < entry_count; 4372 j++, flash++) { 4373 4374 if ((val & mask) == (flash->strapping & mask)) { 4375 bp->flash_info = flash; 4376 4377 /* Request access to the flash interface. */ 4378 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0) 4379 return rc; 4380 4381 /* Enable access to flash interface */ 4382 bnx2_enable_nvram_access(bp); 4383 4384 /* Reconfigure the flash interface */ 4385 BNX2_WR(bp, BNX2_NVM_CFG1, flash->config1); 4386 BNX2_WR(bp, BNX2_NVM_CFG2, flash->config2); 4387 BNX2_WR(bp, BNX2_NVM_CFG3, flash->config3); 4388 BNX2_WR(bp, BNX2_NVM_WRITE1, flash->write1); 4389 4390 /* Disable access to flash interface */ 4391 bnx2_disable_nvram_access(bp); 4392 bnx2_release_nvram_lock(bp); 4393 4394 break; 4395 } 4396 } 4397 } /* if (val & 0x40000000) */ 4398 4399 if (j == entry_count) { 4400 bp->flash_info = NULL; 4401 pr_alert("Unknown flash/EEPROM type\n"); 4402 return -ENODEV; 4403 } 4404 4405 get_flash_size: 4406 val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2); 4407 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK; 4408 if (val) 4409 bp->flash_size = val; 4410 else 4411 bp->flash_size = bp->flash_info->total_size; 4412 4413 return rc; 4414 } 4415 4416 static int 4417 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf, 4418 int buf_size) 4419 { 4420 int rc = 0; 4421 u32 cmd_flags, offset32, len32, extra; 4422 4423 if (buf_size == 0) 4424 return 0; 4425 4426 /* Request access to the flash interface. */ 4427 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0) 4428 return rc; 4429 4430 /* Enable access to flash interface */ 4431 bnx2_enable_nvram_access(bp); 4432 4433 len32 = buf_size; 4434 offset32 = offset; 4435 extra = 0; 4436 4437 cmd_flags = 0; 4438 4439 if (offset32 & 3) { 4440 u8 buf[4]; 4441 u32 pre_len; 4442 4443 offset32 &= ~3; 4444 pre_len = 4 - (offset & 3); 4445 4446 if (pre_len >= len32) { 4447 pre_len = len32; 4448 cmd_flags = BNX2_NVM_COMMAND_FIRST | 4449 BNX2_NVM_COMMAND_LAST; 4450 } 4451 else { 4452 cmd_flags = BNX2_NVM_COMMAND_FIRST; 4453 } 4454 4455 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags); 4456 4457 if (rc) 4458 return rc; 4459 4460 memcpy(ret_buf, buf + (offset & 3), pre_len); 4461 4462 offset32 += 4; 4463 ret_buf += pre_len; 4464 len32 -= pre_len; 4465 } 4466 if (len32 & 3) { 4467 extra = 4 - (len32 & 3); 4468 len32 = (len32 + 4) & ~3; 4469 } 4470 4471 if (len32 == 4) { 4472 u8 buf[4]; 4473 4474 if (cmd_flags) 4475 cmd_flags = BNX2_NVM_COMMAND_LAST; 4476 else 4477 cmd_flags = BNX2_NVM_COMMAND_FIRST | 4478 BNX2_NVM_COMMAND_LAST; 4479 4480 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags); 4481 4482 memcpy(ret_buf, buf, 4 - extra); 4483 } 4484 else if (len32 > 0) { 4485 u8 buf[4]; 4486 4487 /* Read the first word. */ 4488 if (cmd_flags) 4489 cmd_flags = 0; 4490 else 4491 cmd_flags = BNX2_NVM_COMMAND_FIRST; 4492 4493 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags); 4494 4495 /* Advance to the next dword. */ 4496 offset32 += 4; 4497 ret_buf += 4; 4498 len32 -= 4; 4499 4500 while (len32 > 4 && rc == 0) { 4501 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0); 4502 4503 /* Advance to the next dword. */ 4504 offset32 += 4; 4505 ret_buf += 4; 4506 len32 -= 4; 4507 } 4508 4509 if (rc) 4510 return rc; 4511 4512 cmd_flags = BNX2_NVM_COMMAND_LAST; 4513 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags); 4514 4515 memcpy(ret_buf, buf, 4 - extra); 4516 } 4517 4518 /* Disable access to flash interface */ 4519 bnx2_disable_nvram_access(bp); 4520 4521 bnx2_release_nvram_lock(bp); 4522 4523 return rc; 4524 } 4525 4526 static int 4527 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf, 4528 int buf_size) 4529 { 4530 u32 written, offset32, len32; 4531 u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL; 4532 int rc = 0; 4533 int align_start, align_end; 4534 4535 buf = data_buf; 4536 offset32 = offset; 4537 len32 = buf_size; 4538 align_start = align_end = 0; 4539 4540 if ((align_start = (offset32 & 3))) { 4541 offset32 &= ~3; 4542 len32 += align_start; 4543 if (len32 < 4) 4544 len32 = 4; 4545 if ((rc = bnx2_nvram_read(bp, offset32, start, 4))) 4546 return rc; 4547 } 4548 4549 if (len32 & 3) { 4550 align_end = 4 - (len32 & 3); 4551 len32 += align_end; 4552 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4))) 4553 return rc; 4554 } 4555 4556 if (align_start || align_end) { 4557 align_buf = kmalloc(len32, GFP_KERNEL); 4558 if (!align_buf) 4559 return -ENOMEM; 4560 if (align_start) { 4561 memcpy(align_buf, start, 4); 4562 } 4563 if (align_end) { 4564 memcpy(align_buf + len32 - 4, end, 4); 4565 } 4566 memcpy(align_buf + align_start, data_buf, buf_size); 4567 buf = align_buf; 4568 } 4569 4570 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) { 4571 flash_buffer = kmalloc(264, GFP_KERNEL); 4572 if (!flash_buffer) { 4573 rc = -ENOMEM; 4574 goto nvram_write_end; 4575 } 4576 } 4577 4578 written = 0; 4579 while ((written < len32) && (rc == 0)) { 4580 u32 page_start, page_end, data_start, data_end; 4581 u32 addr, cmd_flags; 4582 int i; 4583 4584 /* Find the page_start addr */ 4585 page_start = offset32 + written; 4586 page_start -= (page_start % bp->flash_info->page_size); 4587 /* Find the page_end addr */ 4588 page_end = page_start + bp->flash_info->page_size; 4589 /* Find the data_start addr */ 4590 data_start = (written == 0) ? offset32 : page_start; 4591 /* Find the data_end addr */ 4592 data_end = (page_end > offset32 + len32) ? 4593 (offset32 + len32) : page_end; 4594 4595 /* Request access to the flash interface. */ 4596 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0) 4597 goto nvram_write_end; 4598 4599 /* Enable access to flash interface */ 4600 bnx2_enable_nvram_access(bp); 4601 4602 cmd_flags = BNX2_NVM_COMMAND_FIRST; 4603 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) { 4604 int j; 4605 4606 /* Read the whole page into the buffer 4607 * (non-buffer flash only) */ 4608 for (j = 0; j < bp->flash_info->page_size; j += 4) { 4609 if (j == (bp->flash_info->page_size - 4)) { 4610 cmd_flags |= BNX2_NVM_COMMAND_LAST; 4611 } 4612 rc = bnx2_nvram_read_dword(bp, 4613 page_start + j, 4614 &flash_buffer[j], 4615 cmd_flags); 4616 4617 if (rc) 4618 goto nvram_write_end; 4619 4620 cmd_flags = 0; 4621 } 4622 } 4623 4624 /* Enable writes to flash interface (unlock write-protect) */ 4625 if ((rc = bnx2_enable_nvram_write(bp)) != 0) 4626 goto nvram_write_end; 4627 4628 /* Loop to write back the buffer data from page_start to 4629 * data_start */ 4630 i = 0; 4631 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) { 4632 /* Erase the page */ 4633 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0) 4634 goto nvram_write_end; 4635 4636 /* Re-enable the write again for the actual write */ 4637 bnx2_enable_nvram_write(bp); 4638 4639 for (addr = page_start; addr < data_start; 4640 addr += 4, i += 4) { 4641 4642 rc = bnx2_nvram_write_dword(bp, addr, 4643 &flash_buffer[i], cmd_flags); 4644 4645 if (rc != 0) 4646 goto nvram_write_end; 4647 4648 cmd_flags = 0; 4649 } 4650 } 4651 4652 /* Loop to write the new data from data_start to data_end */ 4653 for (addr = data_start; addr < data_end; addr += 4, i += 4) { 4654 if ((addr == page_end - 4) || 4655 ((bp->flash_info->flags & BNX2_NV_BUFFERED) && 4656 (addr == data_end - 4))) { 4657 4658 cmd_flags |= BNX2_NVM_COMMAND_LAST; 4659 } 4660 rc = bnx2_nvram_write_dword(bp, addr, buf, 4661 cmd_flags); 4662 4663 if (rc != 0) 4664 goto nvram_write_end; 4665 4666 cmd_flags = 0; 4667 buf += 4; 4668 } 4669 4670 /* Loop to write back the buffer data from data_end 4671 * to page_end */ 4672 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) { 4673 for (addr = data_end; addr < page_end; 4674 addr += 4, i += 4) { 4675 4676 if (addr == page_end-4) { 4677 cmd_flags = BNX2_NVM_COMMAND_LAST; 4678 } 4679 rc = bnx2_nvram_write_dword(bp, addr, 4680 &flash_buffer[i], cmd_flags); 4681 4682 if (rc != 0) 4683 goto nvram_write_end; 4684 4685 cmd_flags = 0; 4686 } 4687 } 4688 4689 /* Disable writes to flash interface (lock write-protect) */ 4690 bnx2_disable_nvram_write(bp); 4691 4692 /* Disable access to flash interface */ 4693 bnx2_disable_nvram_access(bp); 4694 bnx2_release_nvram_lock(bp); 4695 4696 /* Increment written */ 4697 written += data_end - data_start; 4698 } 4699 4700 nvram_write_end: 4701 kfree(flash_buffer); 4702 kfree(align_buf); 4703 return rc; 4704 } 4705 4706 static void 4707 bnx2_init_fw_cap(struct bnx2 *bp) 4708 { 4709 u32 val, sig = 0; 4710 4711 bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP; 4712 bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN; 4713 4714 if (!(bp->flags & BNX2_FLAG_ASF_ENABLE)) 4715 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN; 4716 4717 val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB); 4718 if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE) 4719 return; 4720 4721 if ((val & BNX2_FW_CAP_CAN_KEEP_VLAN) == BNX2_FW_CAP_CAN_KEEP_VLAN) { 4722 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN; 4723 sig |= BNX2_DRV_ACK_CAP_SIGNATURE | BNX2_FW_CAP_CAN_KEEP_VLAN; 4724 } 4725 4726 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && 4727 (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE)) { 4728 u32 link; 4729 4730 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP; 4731 4732 link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS); 4733 if (link & BNX2_LINK_STATUS_SERDES_LINK) 4734 bp->phy_port = PORT_FIBRE; 4735 else 4736 bp->phy_port = PORT_TP; 4737 4738 sig |= BNX2_DRV_ACK_CAP_SIGNATURE | 4739 BNX2_FW_CAP_REMOTE_PHY_CAPABLE; 4740 } 4741 4742 if (netif_running(bp->dev) && sig) 4743 bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig); 4744 } 4745 4746 static void 4747 bnx2_setup_msix_tbl(struct bnx2 *bp) 4748 { 4749 BNX2_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN); 4750 4751 BNX2_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR); 4752 BNX2_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR); 4753 } 4754 4755 static void 4756 bnx2_wait_dma_complete(struct bnx2 *bp) 4757 { 4758 u32 val; 4759 int i; 4760 4761 /* 4762 * Wait for the current PCI transaction to complete before 4763 * issuing a reset. 4764 */ 4765 if ((BNX2_CHIP(bp) == BNX2_CHIP_5706) || 4766 (BNX2_CHIP(bp) == BNX2_CHIP_5708)) { 4767 BNX2_WR(bp, BNX2_MISC_ENABLE_CLR_BITS, 4768 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | 4769 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | 4770 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | 4771 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); 4772 val = BNX2_RD(bp, BNX2_MISC_ENABLE_CLR_BITS); 4773 udelay(5); 4774 } else { /* 5709 */ 4775 val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL); 4776 val &= ~BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE; 4777 BNX2_WR(bp, BNX2_MISC_NEW_CORE_CTL, val); 4778 val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL); 4779 4780 for (i = 0; i < 100; i++) { 4781 msleep(1); 4782 val = BNX2_RD(bp, BNX2_PCICFG_DEVICE_CONTROL); 4783 if (!(val & BNX2_PCICFG_DEVICE_STATUS_NO_PEND)) 4784 break; 4785 } 4786 } 4787 4788 return; 4789 } 4790 4791 4792 static int 4793 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code) 4794 { 4795 u32 val; 4796 int i, rc = 0; 4797 u8 old_port; 4798 4799 /* Wait for the current PCI transaction to complete before 4800 * issuing a reset. */ 4801 bnx2_wait_dma_complete(bp); 4802 4803 /* Wait for the firmware to tell us it is ok to issue a reset. */ 4804 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1); 4805 4806 /* Deposit a driver reset signature so the firmware knows that 4807 * this is a soft reset. */ 4808 bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE, 4809 BNX2_DRV_RESET_SIGNATURE_MAGIC); 4810 4811 /* Do a dummy read to force the chip to complete all current transaction 4812 * before we issue a reset. */ 4813 val = BNX2_RD(bp, BNX2_MISC_ID); 4814 4815 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { 4816 BNX2_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET); 4817 BNX2_RD(bp, BNX2_MISC_COMMAND); 4818 udelay(5); 4819 4820 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 4821 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 4822 4823 BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG, val); 4824 4825 } else { 4826 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ | 4827 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 4828 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 4829 4830 /* Chip reset. */ 4831 BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG, val); 4832 4833 /* Reading back any register after chip reset will hang the 4834 * bus on 5706 A0 and A1. The msleep below provides plenty 4835 * of margin for write posting. 4836 */ 4837 if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) || 4838 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1)) 4839 msleep(20); 4840 4841 /* Reset takes approximate 30 usec */ 4842 for (i = 0; i < 10; i++) { 4843 val = BNX2_RD(bp, BNX2_PCICFG_MISC_CONFIG); 4844 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ | 4845 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) 4846 break; 4847 udelay(10); 4848 } 4849 4850 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ | 4851 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { 4852 pr_err("Chip reset did not complete\n"); 4853 return -EBUSY; 4854 } 4855 } 4856 4857 /* Make sure byte swapping is properly configured. */ 4858 val = BNX2_RD(bp, BNX2_PCI_SWAP_DIAG0); 4859 if (val != 0x01020304) { 4860 pr_err("Chip not in correct endian mode\n"); 4861 return -ENODEV; 4862 } 4863 4864 /* Wait for the firmware to finish its initialization. */ 4865 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0); 4866 if (rc) 4867 return rc; 4868 4869 spin_lock_bh(&bp->phy_lock); 4870 old_port = bp->phy_port; 4871 bnx2_init_fw_cap(bp); 4872 if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) && 4873 old_port != bp->phy_port) 4874 bnx2_set_default_remote_link(bp); 4875 spin_unlock_bh(&bp->phy_lock); 4876 4877 if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) { 4878 /* Adjust the voltage regular to two steps lower. The default 4879 * of this register is 0x0000000e. */ 4880 BNX2_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa); 4881 4882 /* Remove bad rbuf memory from the free pool. */ 4883 rc = bnx2_alloc_bad_rbuf(bp); 4884 } 4885 4886 if (bp->flags & BNX2_FLAG_USING_MSIX) { 4887 bnx2_setup_msix_tbl(bp); 4888 /* Prevent MSIX table reads and write from timing out */ 4889 BNX2_WR(bp, BNX2_MISC_ECO_HW_CTL, 4890 BNX2_MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN); 4891 } 4892 4893 return rc; 4894 } 4895 4896 static int 4897 bnx2_init_chip(struct bnx2 *bp) 4898 { 4899 u32 val, mtu; 4900 int rc, i; 4901 4902 /* Make sure the interrupt is not active. */ 4903 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT); 4904 4905 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP | 4906 BNX2_DMA_CONFIG_DATA_WORD_SWAP | 4907 #ifdef __BIG_ENDIAN 4908 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP | 4909 #endif 4910 BNX2_DMA_CONFIG_CNTL_WORD_SWAP | 4911 DMA_READ_CHANS << 12 | 4912 DMA_WRITE_CHANS << 16; 4913 4914 val |= (0x2 << 20) | (1 << 11); 4915 4916 if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133)) 4917 val |= (1 << 23); 4918 4919 if ((BNX2_CHIP(bp) == BNX2_CHIP_5706) && 4920 (BNX2_CHIP_ID(bp) != BNX2_CHIP_ID_5706_A0) && 4921 !(bp->flags & BNX2_FLAG_PCIX)) 4922 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA; 4923 4924 BNX2_WR(bp, BNX2_DMA_CONFIG, val); 4925 4926 if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) { 4927 val = BNX2_RD(bp, BNX2_TDMA_CONFIG); 4928 val |= BNX2_TDMA_CONFIG_ONE_DMA; 4929 BNX2_WR(bp, BNX2_TDMA_CONFIG, val); 4930 } 4931 4932 if (bp->flags & BNX2_FLAG_PCIX) { 4933 u16 val16; 4934 4935 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD, 4936 &val16); 4937 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD, 4938 val16 & ~PCI_X_CMD_ERO); 4939 } 4940 4941 BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS, 4942 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | 4943 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | 4944 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); 4945 4946 /* Initialize context mapping and zero out the quick contexts. The 4947 * context block must have already been enabled. */ 4948 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { 4949 rc = bnx2_init_5709_context(bp); 4950 if (rc) 4951 return rc; 4952 } else 4953 bnx2_init_context(bp); 4954 4955 bnx2_init_cpus(bp); 4956 4957 bnx2_init_nvram(bp); 4958 4959 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0); 4960 4961 val = BNX2_RD(bp, BNX2_MQ_CONFIG); 4962 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE; 4963 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; 4964 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { 4965 val |= BNX2_MQ_CONFIG_BIN_MQ_MODE; 4966 if (BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Ax) 4967 val |= BNX2_MQ_CONFIG_HALT_DIS; 4968 } 4969 4970 BNX2_WR(bp, BNX2_MQ_CONFIG, val); 4971 4972 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); 4973 BNX2_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val); 4974 BNX2_WR(bp, BNX2_MQ_KNL_WIND_END, val); 4975 4976 val = (BNX2_PAGE_BITS - 8) << 24; 4977 BNX2_WR(bp, BNX2_RV2P_CONFIG, val); 4978 4979 /* Configure page size. */ 4980 val = BNX2_RD(bp, BNX2_TBDR_CONFIG); 4981 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE; 4982 val |= (BNX2_PAGE_BITS - 8) << 24 | 0x40; 4983 BNX2_WR(bp, BNX2_TBDR_CONFIG, val); 4984 4985 val = bp->mac_addr[0] + 4986 (bp->mac_addr[1] << 8) + 4987 (bp->mac_addr[2] << 16) + 4988 bp->mac_addr[3] + 4989 (bp->mac_addr[4] << 8) + 4990 (bp->mac_addr[5] << 16); 4991 BNX2_WR(bp, BNX2_EMAC_BACKOFF_SEED, val); 4992 4993 /* Program the MTU. Also include 4 bytes for CRC32. */ 4994 mtu = bp->dev->mtu; 4995 val = mtu + ETH_HLEN + ETH_FCS_LEN; 4996 if (val > (MAX_ETHERNET_PACKET_SIZE + ETH_HLEN + 4)) 4997 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA; 4998 BNX2_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val); 4999 5000 if (mtu < ETH_DATA_LEN) 5001 mtu = ETH_DATA_LEN; 5002 5003 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu)); 5004 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu)); 5005 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu)); 5006 5007 memset(bp->bnx2_napi[0].status_blk.msi, 0, bp->status_stats_size); 5008 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) 5009 bp->bnx2_napi[i].last_status_idx = 0; 5010 5011 bp->idle_chk_status_idx = 0xffff; 5012 5013 /* Set up how to generate a link change interrupt. */ 5014 BNX2_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK); 5015 5016 BNX2_WR(bp, BNX2_HC_STATUS_ADDR_L, 5017 (u64) bp->status_blk_mapping & 0xffffffff); 5018 BNX2_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32); 5019 5020 BNX2_WR(bp, BNX2_HC_STATISTICS_ADDR_L, 5021 (u64) bp->stats_blk_mapping & 0xffffffff); 5022 BNX2_WR(bp, BNX2_HC_STATISTICS_ADDR_H, 5023 (u64) bp->stats_blk_mapping >> 32); 5024 5025 BNX2_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP, 5026 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip); 5027 5028 BNX2_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP, 5029 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip); 5030 5031 BNX2_WR(bp, BNX2_HC_COMP_PROD_TRIP, 5032 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip); 5033 5034 BNX2_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks); 5035 5036 BNX2_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks); 5037 5038 BNX2_WR(bp, BNX2_HC_COM_TICKS, 5039 (bp->com_ticks_int << 16) | bp->com_ticks); 5040 5041 BNX2_WR(bp, BNX2_HC_CMD_TICKS, 5042 (bp->cmd_ticks_int << 16) | bp->cmd_ticks); 5043 5044 if (bp->flags & BNX2_FLAG_BROKEN_STATS) 5045 BNX2_WR(bp, BNX2_HC_STATS_TICKS, 0); 5046 else 5047 BNX2_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks); 5048 BNX2_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ 5049 5050 if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1) 5051 val = BNX2_HC_CONFIG_COLLECT_STATS; 5052 else { 5053 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE | 5054 BNX2_HC_CONFIG_COLLECT_STATS; 5055 } 5056 5057 if (bp->flags & BNX2_FLAG_USING_MSIX) { 5058 BNX2_WR(bp, BNX2_HC_MSIX_BIT_VECTOR, 5059 BNX2_HC_MSIX_BIT_VECTOR_VAL); 5060 5061 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B; 5062 } 5063 5064 if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI) 5065 val |= BNX2_HC_CONFIG_ONE_SHOT | BNX2_HC_CONFIG_USE_INT_PARAM; 5066 5067 BNX2_WR(bp, BNX2_HC_CONFIG, val); 5068 5069 if (bp->rx_ticks < 25) 5070 bnx2_reg_wr_ind(bp, BNX2_FW_RX_LOW_LATENCY, 1); 5071 else 5072 bnx2_reg_wr_ind(bp, BNX2_FW_RX_LOW_LATENCY, 0); 5073 5074 for (i = 1; i < bp->irq_nvecs; i++) { 5075 u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) + 5076 BNX2_HC_SB_CONFIG_1; 5077 5078 BNX2_WR(bp, base, 5079 BNX2_HC_SB_CONFIG_1_TX_TMR_MODE | 5080 BNX2_HC_SB_CONFIG_1_RX_TMR_MODE | 5081 BNX2_HC_SB_CONFIG_1_ONE_SHOT); 5082 5083 BNX2_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF, 5084 (bp->tx_quick_cons_trip_int << 16) | 5085 bp->tx_quick_cons_trip); 5086 5087 BNX2_WR(bp, base + BNX2_HC_TX_TICKS_OFF, 5088 (bp->tx_ticks_int << 16) | bp->tx_ticks); 5089 5090 BNX2_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF, 5091 (bp->rx_quick_cons_trip_int << 16) | 5092 bp->rx_quick_cons_trip); 5093 5094 BNX2_WR(bp, base + BNX2_HC_RX_TICKS_OFF, 5095 (bp->rx_ticks_int << 16) | bp->rx_ticks); 5096 } 5097 5098 /* Clear internal stats counters. */ 5099 BNX2_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW); 5100 5101 BNX2_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS); 5102 5103 /* Initialize the receive filter. */ 5104 bnx2_set_rx_mode(bp->dev); 5105 5106 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { 5107 val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL); 5108 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE; 5109 BNX2_WR(bp, BNX2_MISC_NEW_CORE_CTL, val); 5110 } 5111 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET, 5112 1, 0); 5113 5114 BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT); 5115 BNX2_RD(bp, BNX2_MISC_ENABLE_SET_BITS); 5116 5117 udelay(20); 5118 5119 bp->hc_cmd = BNX2_RD(bp, BNX2_HC_COMMAND); 5120 5121 return rc; 5122 } 5123 5124 static void 5125 bnx2_clear_ring_states(struct bnx2 *bp) 5126 { 5127 struct bnx2_napi *bnapi; 5128 struct bnx2_tx_ring_info *txr; 5129 struct bnx2_rx_ring_info *rxr; 5130 int i; 5131 5132 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) { 5133 bnapi = &bp->bnx2_napi[i]; 5134 txr = &bnapi->tx_ring; 5135 rxr = &bnapi->rx_ring; 5136 5137 txr->tx_cons = 0; 5138 txr->hw_tx_cons = 0; 5139 rxr->rx_prod_bseq = 0; 5140 rxr->rx_prod = 0; 5141 rxr->rx_cons = 0; 5142 rxr->rx_pg_prod = 0; 5143 rxr->rx_pg_cons = 0; 5144 } 5145 } 5146 5147 static void 5148 bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr) 5149 { 5150 u32 val, offset0, offset1, offset2, offset3; 5151 u32 cid_addr = GET_CID_ADDR(cid); 5152 5153 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { 5154 offset0 = BNX2_L2CTX_TYPE_XI; 5155 offset1 = BNX2_L2CTX_CMD_TYPE_XI; 5156 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI; 5157 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI; 5158 } else { 5159 offset0 = BNX2_L2CTX_TYPE; 5160 offset1 = BNX2_L2CTX_CMD_TYPE; 5161 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI; 5162 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO; 5163 } 5164 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2; 5165 bnx2_ctx_wr(bp, cid_addr, offset0, val); 5166 5167 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); 5168 bnx2_ctx_wr(bp, cid_addr, offset1, val); 5169 5170 val = (u64) txr->tx_desc_mapping >> 32; 5171 bnx2_ctx_wr(bp, cid_addr, offset2, val); 5172 5173 val = (u64) txr->tx_desc_mapping & 0xffffffff; 5174 bnx2_ctx_wr(bp, cid_addr, offset3, val); 5175 } 5176 5177 static void 5178 bnx2_init_tx_ring(struct bnx2 *bp, int ring_num) 5179 { 5180 struct bnx2_tx_bd *txbd; 5181 u32 cid = TX_CID; 5182 struct bnx2_napi *bnapi; 5183 struct bnx2_tx_ring_info *txr; 5184 5185 bnapi = &bp->bnx2_napi[ring_num]; 5186 txr = &bnapi->tx_ring; 5187 5188 if (ring_num == 0) 5189 cid = TX_CID; 5190 else 5191 cid = TX_TSS_CID + ring_num - 1; 5192 5193 bp->tx_wake_thresh = bp->tx_ring_size / 2; 5194 5195 txbd = &txr->tx_desc_ring[BNX2_MAX_TX_DESC_CNT]; 5196 5197 txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32; 5198 txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff; 5199 5200 txr->tx_prod = 0; 5201 txr->tx_prod_bseq = 0; 5202 5203 txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX; 5204 txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ; 5205 5206 bnx2_init_tx_context(bp, cid, txr); 5207 } 5208 5209 static void 5210 bnx2_init_rxbd_rings(struct bnx2_rx_bd *rx_ring[], dma_addr_t dma[], 5211 u32 buf_size, int num_rings) 5212 { 5213 int i; 5214 struct bnx2_rx_bd *rxbd; 5215 5216 for (i = 0; i < num_rings; i++) { 5217 int j; 5218 5219 rxbd = &rx_ring[i][0]; 5220 for (j = 0; j < BNX2_MAX_RX_DESC_CNT; j++, rxbd++) { 5221 rxbd->rx_bd_len = buf_size; 5222 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END; 5223 } 5224 if (i == (num_rings - 1)) 5225 j = 0; 5226 else 5227 j = i + 1; 5228 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32; 5229 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff; 5230 } 5231 } 5232 5233 static void 5234 bnx2_init_rx_ring(struct bnx2 *bp, int ring_num) 5235 { 5236 int i; 5237 u16 prod, ring_prod; 5238 u32 cid, rx_cid_addr, val; 5239 struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num]; 5240 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; 5241 5242 if (ring_num == 0) 5243 cid = RX_CID; 5244 else 5245 cid = RX_RSS_CID + ring_num - 1; 5246 5247 rx_cid_addr = GET_CID_ADDR(cid); 5248 5249 bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping, 5250 bp->rx_buf_use_size, bp->rx_max_ring); 5251 5252 bnx2_init_rx_context(bp, cid); 5253 5254 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { 5255 val = BNX2_RD(bp, BNX2_MQ_MAP_L2_5); 5256 BNX2_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM); 5257 } 5258 5259 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0); 5260 if (bp->rx_pg_ring_size) { 5261 bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring, 5262 rxr->rx_pg_desc_mapping, 5263 PAGE_SIZE, bp->rx_max_pg_ring); 5264 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE; 5265 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val); 5266 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY, 5267 BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num); 5268 5269 val = (u64) rxr->rx_pg_desc_mapping[0] >> 32; 5270 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val); 5271 5272 val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff; 5273 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val); 5274 5275 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) 5276 BNX2_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT); 5277 } 5278 5279 val = (u64) rxr->rx_desc_mapping[0] >> 32; 5280 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val); 5281 5282 val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff; 5283 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val); 5284 5285 ring_prod = prod = rxr->rx_pg_prod; 5286 for (i = 0; i < bp->rx_pg_ring_size; i++) { 5287 if (bnx2_alloc_rx_page(bp, rxr, ring_prod, GFP_KERNEL) < 0) { 5288 netdev_warn(bp->dev, "init'ed rx page ring %d with %d/%d pages only\n", 5289 ring_num, i, bp->rx_pg_ring_size); 5290 break; 5291 } 5292 prod = BNX2_NEXT_RX_BD(prod); 5293 ring_prod = BNX2_RX_PG_RING_IDX(prod); 5294 } 5295 rxr->rx_pg_prod = prod; 5296 5297 ring_prod = prod = rxr->rx_prod; 5298 for (i = 0; i < bp->rx_ring_size; i++) { 5299 if (bnx2_alloc_rx_data(bp, rxr, ring_prod, GFP_KERNEL) < 0) { 5300 netdev_warn(bp->dev, "init'ed rx ring %d with %d/%d skbs only\n", 5301 ring_num, i, bp->rx_ring_size); 5302 break; 5303 } 5304 prod = BNX2_NEXT_RX_BD(prod); 5305 ring_prod = BNX2_RX_RING_IDX(prod); 5306 } 5307 rxr->rx_prod = prod; 5308 5309 rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX; 5310 rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ; 5311 rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX; 5312 5313 BNX2_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod); 5314 BNX2_WR16(bp, rxr->rx_bidx_addr, prod); 5315 5316 BNX2_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq); 5317 } 5318 5319 static void 5320 bnx2_init_all_rings(struct bnx2 *bp) 5321 { 5322 int i; 5323 u32 val; 5324 5325 bnx2_clear_ring_states(bp); 5326 5327 BNX2_WR(bp, BNX2_TSCH_TSS_CFG, 0); 5328 for (i = 0; i < bp->num_tx_rings; i++) 5329 bnx2_init_tx_ring(bp, i); 5330 5331 if (bp->num_tx_rings > 1) 5332 BNX2_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) | 5333 (TX_TSS_CID << 7)); 5334 5335 BNX2_WR(bp, BNX2_RLUP_RSS_CONFIG, 0); 5336 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0); 5337 5338 for (i = 0; i < bp->num_rx_rings; i++) 5339 bnx2_init_rx_ring(bp, i); 5340 5341 if (bp->num_rx_rings > 1) { 5342 u32 tbl_32 = 0; 5343 5344 for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) { 5345 int shift = (i % 8) << 2; 5346 5347 tbl_32 |= (i % (bp->num_rx_rings - 1)) << shift; 5348 if ((i % 8) == 7) { 5349 BNX2_WR(bp, BNX2_RLUP_RSS_DATA, tbl_32); 5350 BNX2_WR(bp, BNX2_RLUP_RSS_COMMAND, (i >> 3) | 5351 BNX2_RLUP_RSS_COMMAND_RSS_WRITE_MASK | 5352 BNX2_RLUP_RSS_COMMAND_WRITE | 5353 BNX2_RLUP_RSS_COMMAND_HASH_MASK); 5354 tbl_32 = 0; 5355 } 5356 } 5357 5358 val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI | 5359 BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI; 5360 5361 BNX2_WR(bp, BNX2_RLUP_RSS_CONFIG, val); 5362 5363 } 5364 } 5365 5366 static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size) 5367 { 5368 u32 max, num_rings = 1; 5369 5370 while (ring_size > BNX2_MAX_RX_DESC_CNT) { 5371 ring_size -= BNX2_MAX_RX_DESC_CNT; 5372 num_rings++; 5373 } 5374 /* round to next power of 2 */ 5375 max = max_size; 5376 while ((max & num_rings) == 0) 5377 max >>= 1; 5378 5379 if (num_rings != max) 5380 max <<= 1; 5381 5382 return max; 5383 } 5384 5385 static void 5386 bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size) 5387 { 5388 u32 rx_size, rx_space, jumbo_size; 5389 5390 /* 8 for CRC and VLAN */ 5391 rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8; 5392 5393 rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD + 5394 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 5395 5396 bp->rx_copy_thresh = BNX2_RX_COPY_THRESH; 5397 bp->rx_pg_ring_size = 0; 5398 bp->rx_max_pg_ring = 0; 5399 bp->rx_max_pg_ring_idx = 0; 5400 if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) { 5401 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT; 5402 5403 jumbo_size = size * pages; 5404 if (jumbo_size > BNX2_MAX_TOTAL_RX_PG_DESC_CNT) 5405 jumbo_size = BNX2_MAX_TOTAL_RX_PG_DESC_CNT; 5406 5407 bp->rx_pg_ring_size = jumbo_size; 5408 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size, 5409 BNX2_MAX_RX_PG_RINGS); 5410 bp->rx_max_pg_ring_idx = 5411 (bp->rx_max_pg_ring * BNX2_RX_DESC_CNT) - 1; 5412 rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET; 5413 bp->rx_copy_thresh = 0; 5414 } 5415 5416 bp->rx_buf_use_size = rx_size; 5417 /* hw alignment + build_skb() overhead*/ 5418 bp->rx_buf_size = kmalloc_size_roundup( 5419 SKB_DATA_ALIGN(bp->rx_buf_use_size + BNX2_RX_ALIGN) + 5420 NET_SKB_PAD + SKB_DATA_ALIGN(sizeof(struct skb_shared_info))); 5421 bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET; 5422 bp->rx_ring_size = size; 5423 bp->rx_max_ring = bnx2_find_max_ring(size, BNX2_MAX_RX_RINGS); 5424 bp->rx_max_ring_idx = (bp->rx_max_ring * BNX2_RX_DESC_CNT) - 1; 5425 } 5426 5427 static void 5428 bnx2_free_tx_skbs(struct bnx2 *bp) 5429 { 5430 int i; 5431 5432 for (i = 0; i < bp->num_tx_rings; i++) { 5433 struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; 5434 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; 5435 int j; 5436 5437 if (!txr->tx_buf_ring) 5438 continue; 5439 5440 for (j = 0; j < BNX2_TX_DESC_CNT; ) { 5441 struct bnx2_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j]; 5442 struct sk_buff *skb = tx_buf->skb; 5443 int k, last; 5444 5445 if (!skb) { 5446 j = BNX2_NEXT_TX_BD(j); 5447 continue; 5448 } 5449 5450 dma_unmap_single(&bp->pdev->dev, 5451 dma_unmap_addr(tx_buf, mapping), 5452 skb_headlen(skb), 5453 DMA_TO_DEVICE); 5454 5455 tx_buf->skb = NULL; 5456 5457 last = tx_buf->nr_frags; 5458 j = BNX2_NEXT_TX_BD(j); 5459 for (k = 0; k < last; k++, j = BNX2_NEXT_TX_BD(j)) { 5460 tx_buf = &txr->tx_buf_ring[BNX2_TX_RING_IDX(j)]; 5461 dma_unmap_page(&bp->pdev->dev, 5462 dma_unmap_addr(tx_buf, mapping), 5463 skb_frag_size(&skb_shinfo(skb)->frags[k]), 5464 DMA_TO_DEVICE); 5465 } 5466 dev_kfree_skb(skb); 5467 } 5468 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i)); 5469 } 5470 } 5471 5472 static void 5473 bnx2_free_rx_skbs(struct bnx2 *bp) 5474 { 5475 int i; 5476 5477 for (i = 0; i < bp->num_rx_rings; i++) { 5478 struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; 5479 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring; 5480 int j; 5481 5482 if (!rxr->rx_buf_ring) 5483 return; 5484 5485 for (j = 0; j < bp->rx_max_ring_idx; j++) { 5486 struct bnx2_sw_bd *rx_buf = &rxr->rx_buf_ring[j]; 5487 u8 *data = rx_buf->data; 5488 5489 if (!data) 5490 continue; 5491 5492 dma_unmap_single(&bp->pdev->dev, 5493 dma_unmap_addr(rx_buf, mapping), 5494 bp->rx_buf_use_size, 5495 DMA_FROM_DEVICE); 5496 5497 rx_buf->data = NULL; 5498 5499 kfree(data); 5500 } 5501 for (j = 0; j < bp->rx_max_pg_ring_idx; j++) 5502 bnx2_free_rx_page(bp, rxr, j); 5503 } 5504 } 5505 5506 static void 5507 bnx2_free_skbs(struct bnx2 *bp) 5508 { 5509 bnx2_free_tx_skbs(bp); 5510 bnx2_free_rx_skbs(bp); 5511 } 5512 5513 static int 5514 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code) 5515 { 5516 int rc; 5517 5518 rc = bnx2_reset_chip(bp, reset_code); 5519 bnx2_free_skbs(bp); 5520 if (rc) 5521 return rc; 5522 5523 if ((rc = bnx2_init_chip(bp)) != 0) 5524 return rc; 5525 5526 bnx2_init_all_rings(bp); 5527 return 0; 5528 } 5529 5530 static int 5531 bnx2_init_nic(struct bnx2 *bp, int reset_phy) 5532 { 5533 int rc; 5534 5535 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0) 5536 return rc; 5537 5538 spin_lock_bh(&bp->phy_lock); 5539 bnx2_init_phy(bp, reset_phy); 5540 bnx2_set_link(bp); 5541 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) 5542 bnx2_remote_phy_event(bp); 5543 spin_unlock_bh(&bp->phy_lock); 5544 return 0; 5545 } 5546 5547 static int 5548 bnx2_shutdown_chip(struct bnx2 *bp) 5549 { 5550 u32 reset_code; 5551 5552 if (bp->flags & BNX2_FLAG_NO_WOL) 5553 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN; 5554 else if (bp->wol) 5555 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL; 5556 else 5557 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL; 5558 5559 return bnx2_reset_chip(bp, reset_code); 5560 } 5561 5562 static int 5563 bnx2_test_registers(struct bnx2 *bp) 5564 { 5565 int ret; 5566 int i, is_5709; 5567 static const struct { 5568 u16 offset; 5569 u16 flags; 5570 #define BNX2_FL_NOT_5709 1 5571 u32 rw_mask; 5572 u32 ro_mask; 5573 } reg_tbl[] = { 5574 { 0x006c, 0, 0x00000000, 0x0000003f }, 5575 { 0x0090, 0, 0xffffffff, 0x00000000 }, 5576 { 0x0094, 0, 0x00000000, 0x00000000 }, 5577 5578 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 }, 5579 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, 5580 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, 5581 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff }, 5582 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 }, 5583 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 }, 5584 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff }, 5585 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, 5586 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, 5587 5588 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, 5589 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, 5590 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 }, 5591 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 }, 5592 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 }, 5593 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 }, 5594 5595 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 }, 5596 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 }, 5597 { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 }, 5598 5599 { 0x1000, 0, 0x00000000, 0x00000001 }, 5600 { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 }, 5601 5602 { 0x1408, 0, 0x01c00800, 0x00000000 }, 5603 { 0x149c, 0, 0x8000ffff, 0x00000000 }, 5604 { 0x14a8, 0, 0x00000000, 0x000001ff }, 5605 { 0x14ac, 0, 0x0fffffff, 0x10000000 }, 5606 { 0x14b0, 0, 0x00000002, 0x00000001 }, 5607 { 0x14b8, 0, 0x00000000, 0x00000000 }, 5608 { 0x14c0, 0, 0x00000000, 0x00000009 }, 5609 { 0x14c4, 0, 0x00003fff, 0x00000000 }, 5610 { 0x14cc, 0, 0x00000000, 0x00000001 }, 5611 { 0x14d0, 0, 0xffffffff, 0x00000000 }, 5612 5613 { 0x1800, 0, 0x00000000, 0x00000001 }, 5614 { 0x1804, 0, 0x00000000, 0x00000003 }, 5615 5616 { 0x2800, 0, 0x00000000, 0x00000001 }, 5617 { 0x2804, 0, 0x00000000, 0x00003f01 }, 5618 { 0x2808, 0, 0x0f3f3f03, 0x00000000 }, 5619 { 0x2810, 0, 0xffff0000, 0x00000000 }, 5620 { 0x2814, 0, 0xffff0000, 0x00000000 }, 5621 { 0x2818, 0, 0xffff0000, 0x00000000 }, 5622 { 0x281c, 0, 0xffff0000, 0x00000000 }, 5623 { 0x2834, 0, 0xffffffff, 0x00000000 }, 5624 { 0x2840, 0, 0x00000000, 0xffffffff }, 5625 { 0x2844, 0, 0x00000000, 0xffffffff }, 5626 { 0x2848, 0, 0xffffffff, 0x00000000 }, 5627 { 0x284c, 0, 0xf800f800, 0x07ff07ff }, 5628 5629 { 0x2c00, 0, 0x00000000, 0x00000011 }, 5630 { 0x2c04, 0, 0x00000000, 0x00030007 }, 5631 5632 { 0x3c00, 0, 0x00000000, 0x00000001 }, 5633 { 0x3c04, 0, 0x00000000, 0x00070000 }, 5634 { 0x3c08, 0, 0x00007f71, 0x07f00000 }, 5635 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 }, 5636 { 0x3c10, 0, 0xffffffff, 0x00000000 }, 5637 { 0x3c14, 0, 0x00000000, 0xffffffff }, 5638 { 0x3c18, 0, 0x00000000, 0xffffffff }, 5639 { 0x3c1c, 0, 0xfffff000, 0x00000000 }, 5640 { 0x3c20, 0, 0xffffff00, 0x00000000 }, 5641 5642 { 0x5004, 0, 0x00000000, 0x0000007f }, 5643 { 0x5008, 0, 0x0f0007ff, 0x00000000 }, 5644 5645 { 0x5c00, 0, 0x00000000, 0x00000001 }, 5646 { 0x5c04, 0, 0x00000000, 0x0003000f }, 5647 { 0x5c08, 0, 0x00000003, 0x00000000 }, 5648 { 0x5c0c, 0, 0x0000fff8, 0x00000000 }, 5649 { 0x5c10, 0, 0x00000000, 0xffffffff }, 5650 { 0x5c80, 0, 0x00000000, 0x0f7113f1 }, 5651 { 0x5c84, 0, 0x00000000, 0x0000f333 }, 5652 { 0x5c88, 0, 0x00000000, 0x00077373 }, 5653 { 0x5c8c, 0, 0x00000000, 0x0007f737 }, 5654 5655 { 0x6808, 0, 0x0000ff7f, 0x00000000 }, 5656 { 0x680c, 0, 0xffffffff, 0x00000000 }, 5657 { 0x6810, 0, 0xffffffff, 0x00000000 }, 5658 { 0x6814, 0, 0xffffffff, 0x00000000 }, 5659 { 0x6818, 0, 0xffffffff, 0x00000000 }, 5660 { 0x681c, 0, 0xffffffff, 0x00000000 }, 5661 { 0x6820, 0, 0x00ff00ff, 0x00000000 }, 5662 { 0x6824, 0, 0x00ff00ff, 0x00000000 }, 5663 { 0x6828, 0, 0x00ff00ff, 0x00000000 }, 5664 { 0x682c, 0, 0x03ff03ff, 0x00000000 }, 5665 { 0x6830, 0, 0x03ff03ff, 0x00000000 }, 5666 { 0x6834, 0, 0x03ff03ff, 0x00000000 }, 5667 { 0x6838, 0, 0x03ff03ff, 0x00000000 }, 5668 { 0x683c, 0, 0x0000ffff, 0x00000000 }, 5669 { 0x6840, 0, 0x00000ff0, 0x00000000 }, 5670 { 0x6844, 0, 0x00ffff00, 0x00000000 }, 5671 { 0x684c, 0, 0xffffffff, 0x00000000 }, 5672 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 }, 5673 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 }, 5674 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 }, 5675 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 }, 5676 { 0x6908, 0, 0x00000000, 0x0001ff0f }, 5677 { 0x690c, 0, 0x00000000, 0x0ffe00f0 }, 5678 5679 { 0xffff, 0, 0x00000000, 0x00000000 }, 5680 }; 5681 5682 ret = 0; 5683 is_5709 = 0; 5684 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) 5685 is_5709 = 1; 5686 5687 for (i = 0; reg_tbl[i].offset != 0xffff; i++) { 5688 u32 offset, rw_mask, ro_mask, save_val, val; 5689 u16 flags = reg_tbl[i].flags; 5690 5691 if (is_5709 && (flags & BNX2_FL_NOT_5709)) 5692 continue; 5693 5694 offset = (u32) reg_tbl[i].offset; 5695 rw_mask = reg_tbl[i].rw_mask; 5696 ro_mask = reg_tbl[i].ro_mask; 5697 5698 save_val = readl(bp->regview + offset); 5699 5700 writel(0, bp->regview + offset); 5701 5702 val = readl(bp->regview + offset); 5703 if ((val & rw_mask) != 0) { 5704 goto reg_test_err; 5705 } 5706 5707 if ((val & ro_mask) != (save_val & ro_mask)) { 5708 goto reg_test_err; 5709 } 5710 5711 writel(0xffffffff, bp->regview + offset); 5712 5713 val = readl(bp->regview + offset); 5714 if ((val & rw_mask) != rw_mask) { 5715 goto reg_test_err; 5716 } 5717 5718 if ((val & ro_mask) != (save_val & ro_mask)) { 5719 goto reg_test_err; 5720 } 5721 5722 writel(save_val, bp->regview + offset); 5723 continue; 5724 5725 reg_test_err: 5726 writel(save_val, bp->regview + offset); 5727 ret = -ENODEV; 5728 break; 5729 } 5730 return ret; 5731 } 5732 5733 static int 5734 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size) 5735 { 5736 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555, 5737 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa }; 5738 int i; 5739 5740 for (i = 0; i < sizeof(test_pattern) / 4; i++) { 5741 u32 offset; 5742 5743 for (offset = 0; offset < size; offset += 4) { 5744 5745 bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]); 5746 5747 if (bnx2_reg_rd_ind(bp, start + offset) != 5748 test_pattern[i]) { 5749 return -ENODEV; 5750 } 5751 } 5752 } 5753 return 0; 5754 } 5755 5756 static int 5757 bnx2_test_memory(struct bnx2 *bp) 5758 { 5759 int ret = 0; 5760 int i; 5761 static struct mem_entry { 5762 u32 offset; 5763 u32 len; 5764 } mem_tbl_5706[] = { 5765 { 0x60000, 0x4000 }, 5766 { 0xa0000, 0x3000 }, 5767 { 0xe0000, 0x4000 }, 5768 { 0x120000, 0x4000 }, 5769 { 0x1a0000, 0x4000 }, 5770 { 0x160000, 0x4000 }, 5771 { 0xffffffff, 0 }, 5772 }, 5773 mem_tbl_5709[] = { 5774 { 0x60000, 0x4000 }, 5775 { 0xa0000, 0x3000 }, 5776 { 0xe0000, 0x4000 }, 5777 { 0x120000, 0x4000 }, 5778 { 0x1a0000, 0x4000 }, 5779 { 0xffffffff, 0 }, 5780 }; 5781 struct mem_entry *mem_tbl; 5782 5783 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) 5784 mem_tbl = mem_tbl_5709; 5785 else 5786 mem_tbl = mem_tbl_5706; 5787 5788 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) { 5789 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset, 5790 mem_tbl[i].len)) != 0) { 5791 return ret; 5792 } 5793 } 5794 5795 return ret; 5796 } 5797 5798 #define BNX2_MAC_LOOPBACK 0 5799 #define BNX2_PHY_LOOPBACK 1 5800 5801 static int 5802 bnx2_run_loopback(struct bnx2 *bp, int loopback_mode) 5803 { 5804 unsigned int pkt_size, num_pkts, i; 5805 struct sk_buff *skb; 5806 u8 *data; 5807 unsigned char *packet; 5808 u16 rx_start_idx, rx_idx; 5809 dma_addr_t map; 5810 struct bnx2_tx_bd *txbd; 5811 struct bnx2_sw_bd *rx_buf; 5812 struct l2_fhdr *rx_hdr; 5813 int ret = -ENODEV; 5814 struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi; 5815 struct bnx2_tx_ring_info *txr; 5816 struct bnx2_rx_ring_info *rxr; 5817 5818 tx_napi = bnapi; 5819 5820 txr = &tx_napi->tx_ring; 5821 rxr = &bnapi->rx_ring; 5822 if (loopback_mode == BNX2_MAC_LOOPBACK) { 5823 bp->loopback = MAC_LOOPBACK; 5824 bnx2_set_mac_loopback(bp); 5825 } 5826 else if (loopback_mode == BNX2_PHY_LOOPBACK) { 5827 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) 5828 return 0; 5829 5830 bp->loopback = PHY_LOOPBACK; 5831 bnx2_set_phy_loopback(bp); 5832 } 5833 else 5834 return -EINVAL; 5835 5836 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4); 5837 skb = netdev_alloc_skb(bp->dev, pkt_size); 5838 if (!skb) 5839 return -ENOMEM; 5840 packet = skb_put(skb, pkt_size); 5841 memcpy(packet, bp->dev->dev_addr, ETH_ALEN); 5842 memset(packet + ETH_ALEN, 0x0, 8); 5843 for (i = 14; i < pkt_size; i++) 5844 packet[i] = (unsigned char) (i & 0xff); 5845 5846 map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size, 5847 DMA_TO_DEVICE); 5848 if (dma_mapping_error(&bp->pdev->dev, map)) { 5849 dev_kfree_skb(skb); 5850 return -EIO; 5851 } 5852 5853 BNX2_WR(bp, BNX2_HC_COMMAND, 5854 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT); 5855 5856 BNX2_RD(bp, BNX2_HC_COMMAND); 5857 5858 udelay(5); 5859 rx_start_idx = bnx2_get_hw_rx_cons(bnapi); 5860 5861 num_pkts = 0; 5862 5863 txbd = &txr->tx_desc_ring[BNX2_TX_RING_IDX(txr->tx_prod)]; 5864 5865 txbd->tx_bd_haddr_hi = (u64) map >> 32; 5866 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff; 5867 txbd->tx_bd_mss_nbytes = pkt_size; 5868 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END; 5869 5870 num_pkts++; 5871 txr->tx_prod = BNX2_NEXT_TX_BD(txr->tx_prod); 5872 txr->tx_prod_bseq += pkt_size; 5873 5874 BNX2_WR16(bp, txr->tx_bidx_addr, txr->tx_prod); 5875 BNX2_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq); 5876 5877 udelay(100); 5878 5879 BNX2_WR(bp, BNX2_HC_COMMAND, 5880 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT); 5881 5882 BNX2_RD(bp, BNX2_HC_COMMAND); 5883 5884 udelay(5); 5885 5886 dma_unmap_single(&bp->pdev->dev, map, pkt_size, DMA_TO_DEVICE); 5887 dev_kfree_skb(skb); 5888 5889 if (bnx2_get_hw_tx_cons(tx_napi) != txr->tx_prod) 5890 goto loopback_test_done; 5891 5892 rx_idx = bnx2_get_hw_rx_cons(bnapi); 5893 if (rx_idx != rx_start_idx + num_pkts) { 5894 goto loopback_test_done; 5895 } 5896 5897 rx_buf = &rxr->rx_buf_ring[rx_start_idx]; 5898 data = rx_buf->data; 5899 5900 rx_hdr = get_l2_fhdr(data); 5901 data = (u8 *)rx_hdr + BNX2_RX_OFFSET; 5902 5903 dma_sync_single_for_cpu(&bp->pdev->dev, 5904 dma_unmap_addr(rx_buf, mapping), 5905 bp->rx_buf_use_size, DMA_FROM_DEVICE); 5906 5907 if (rx_hdr->l2_fhdr_status & 5908 (L2_FHDR_ERRORS_BAD_CRC | 5909 L2_FHDR_ERRORS_PHY_DECODE | 5910 L2_FHDR_ERRORS_ALIGNMENT | 5911 L2_FHDR_ERRORS_TOO_SHORT | 5912 L2_FHDR_ERRORS_GIANT_FRAME)) { 5913 5914 goto loopback_test_done; 5915 } 5916 5917 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) { 5918 goto loopback_test_done; 5919 } 5920 5921 for (i = 14; i < pkt_size; i++) { 5922 if (*(data + i) != (unsigned char) (i & 0xff)) { 5923 goto loopback_test_done; 5924 } 5925 } 5926 5927 ret = 0; 5928 5929 loopback_test_done: 5930 bp->loopback = 0; 5931 return ret; 5932 } 5933 5934 #define BNX2_MAC_LOOPBACK_FAILED 1 5935 #define BNX2_PHY_LOOPBACK_FAILED 2 5936 #define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \ 5937 BNX2_PHY_LOOPBACK_FAILED) 5938 5939 static int 5940 bnx2_test_loopback(struct bnx2 *bp) 5941 { 5942 int rc = 0; 5943 5944 if (!netif_running(bp->dev)) 5945 return BNX2_LOOPBACK_FAILED; 5946 5947 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET); 5948 spin_lock_bh(&bp->phy_lock); 5949 bnx2_init_phy(bp, 1); 5950 spin_unlock_bh(&bp->phy_lock); 5951 if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK)) 5952 rc |= BNX2_MAC_LOOPBACK_FAILED; 5953 if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK)) 5954 rc |= BNX2_PHY_LOOPBACK_FAILED; 5955 return rc; 5956 } 5957 5958 #define NVRAM_SIZE 0x200 5959 #define CRC32_RESIDUAL 0xdebb20e3 5960 5961 static int 5962 bnx2_test_nvram(struct bnx2 *bp) 5963 { 5964 __be32 buf[NVRAM_SIZE / 4]; 5965 u8 *data = (u8 *) buf; 5966 int rc = 0; 5967 u32 magic, csum; 5968 5969 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0) 5970 goto test_nvram_done; 5971 5972 magic = be32_to_cpu(buf[0]); 5973 if (magic != 0x669955aa) { 5974 rc = -ENODEV; 5975 goto test_nvram_done; 5976 } 5977 5978 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0) 5979 goto test_nvram_done; 5980 5981 csum = ether_crc_le(0x100, data); 5982 if (csum != CRC32_RESIDUAL) { 5983 rc = -ENODEV; 5984 goto test_nvram_done; 5985 } 5986 5987 csum = ether_crc_le(0x100, data + 0x100); 5988 if (csum != CRC32_RESIDUAL) { 5989 rc = -ENODEV; 5990 } 5991 5992 test_nvram_done: 5993 return rc; 5994 } 5995 5996 static int 5997 bnx2_test_link(struct bnx2 *bp) 5998 { 5999 u32 bmsr; 6000 6001 if (!netif_running(bp->dev)) 6002 return -ENODEV; 6003 6004 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) { 6005 if (bp->link_up) 6006 return 0; 6007 return -ENODEV; 6008 } 6009 spin_lock_bh(&bp->phy_lock); 6010 bnx2_enable_bmsr1(bp); 6011 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr); 6012 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr); 6013 bnx2_disable_bmsr1(bp); 6014 spin_unlock_bh(&bp->phy_lock); 6015 6016 if (bmsr & BMSR_LSTATUS) { 6017 return 0; 6018 } 6019 return -ENODEV; 6020 } 6021 6022 static int 6023 bnx2_test_intr(struct bnx2 *bp) 6024 { 6025 int i; 6026 u16 status_idx; 6027 6028 if (!netif_running(bp->dev)) 6029 return -ENODEV; 6030 6031 status_idx = BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff; 6032 6033 /* This register is not touched during run-time. */ 6034 BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW); 6035 BNX2_RD(bp, BNX2_HC_COMMAND); 6036 6037 for (i = 0; i < 10; i++) { 6038 if ((BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) != 6039 status_idx) { 6040 6041 break; 6042 } 6043 6044 msleep_interruptible(10); 6045 } 6046 if (i < 10) 6047 return 0; 6048 6049 return -ENODEV; 6050 } 6051 6052 /* Determining link for parallel detection. */ 6053 static int 6054 bnx2_5706_serdes_has_link(struct bnx2 *bp) 6055 { 6056 u32 mode_ctl, an_dbg, exp; 6057 6058 if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL) 6059 return 0; 6060 6061 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL); 6062 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl); 6063 6064 if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET)) 6065 return 0; 6066 6067 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG); 6068 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg); 6069 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg); 6070 6071 if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID)) 6072 return 0; 6073 6074 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1); 6075 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp); 6076 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp); 6077 6078 if (exp & MII_EXPAND_REG1_RUDI_C) /* receiving CONFIG */ 6079 return 0; 6080 6081 return 1; 6082 } 6083 6084 static void 6085 bnx2_5706_serdes_timer(struct bnx2 *bp) 6086 { 6087 int check_link = 1; 6088 6089 spin_lock(&bp->phy_lock); 6090 if (bp->serdes_an_pending) { 6091 bp->serdes_an_pending--; 6092 check_link = 0; 6093 } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) { 6094 u32 bmcr; 6095 6096 bp->current_interval = BNX2_TIMER_INTERVAL; 6097 6098 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); 6099 6100 if (bmcr & BMCR_ANENABLE) { 6101 if (bnx2_5706_serdes_has_link(bp)) { 6102 bmcr &= ~BMCR_ANENABLE; 6103 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX; 6104 bnx2_write_phy(bp, bp->mii_bmcr, bmcr); 6105 bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT; 6106 } 6107 } 6108 } 6109 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) && 6110 (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) { 6111 u32 phy2; 6112 6113 bnx2_write_phy(bp, 0x17, 0x0f01); 6114 bnx2_read_phy(bp, 0x15, &phy2); 6115 if (phy2 & 0x20) { 6116 u32 bmcr; 6117 6118 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); 6119 bmcr |= BMCR_ANENABLE; 6120 bnx2_write_phy(bp, bp->mii_bmcr, bmcr); 6121 6122 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT; 6123 } 6124 } else 6125 bp->current_interval = BNX2_TIMER_INTERVAL; 6126 6127 if (check_link) { 6128 u32 val; 6129 6130 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG); 6131 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val); 6132 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val); 6133 6134 if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) { 6135 if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) { 6136 bnx2_5706s_force_link_dn(bp, 1); 6137 bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN; 6138 } else 6139 bnx2_set_link(bp); 6140 } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC)) 6141 bnx2_set_link(bp); 6142 } 6143 spin_unlock(&bp->phy_lock); 6144 } 6145 6146 static void 6147 bnx2_5708_serdes_timer(struct bnx2 *bp) 6148 { 6149 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) 6150 return; 6151 6152 if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) { 6153 bp->serdes_an_pending = 0; 6154 return; 6155 } 6156 6157 spin_lock(&bp->phy_lock); 6158 if (bp->serdes_an_pending) 6159 bp->serdes_an_pending--; 6160 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) { 6161 u32 bmcr; 6162 6163 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); 6164 if (bmcr & BMCR_ANENABLE) { 6165 bnx2_enable_forced_2g5(bp); 6166 bp->current_interval = BNX2_SERDES_FORCED_TIMEOUT; 6167 } else { 6168 bnx2_disable_forced_2g5(bp); 6169 bp->serdes_an_pending = 2; 6170 bp->current_interval = BNX2_TIMER_INTERVAL; 6171 } 6172 6173 } else 6174 bp->current_interval = BNX2_TIMER_INTERVAL; 6175 6176 spin_unlock(&bp->phy_lock); 6177 } 6178 6179 static void 6180 bnx2_timer(struct timer_list *t) 6181 { 6182 struct bnx2 *bp = timer_container_of(bp, t, timer); 6183 6184 if (!netif_running(bp->dev)) 6185 return; 6186 6187 if (atomic_read(&bp->intr_sem) != 0) 6188 goto bnx2_restart_timer; 6189 6190 if ((bp->flags & (BNX2_FLAG_USING_MSI | BNX2_FLAG_ONE_SHOT_MSI)) == 6191 BNX2_FLAG_USING_MSI) 6192 bnx2_chk_missed_msi(bp); 6193 6194 bnx2_send_heart_beat(bp); 6195 6196 bp->stats_blk->stat_FwRxDrop = 6197 bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT); 6198 6199 /* workaround occasional corrupted counters */ 6200 if ((bp->flags & BNX2_FLAG_BROKEN_STATS) && bp->stats_ticks) 6201 BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | 6202 BNX2_HC_COMMAND_STATS_NOW); 6203 6204 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { 6205 if (BNX2_CHIP(bp) == BNX2_CHIP_5706) 6206 bnx2_5706_serdes_timer(bp); 6207 else 6208 bnx2_5708_serdes_timer(bp); 6209 } 6210 6211 bnx2_restart_timer: 6212 mod_timer(&bp->timer, jiffies + bp->current_interval); 6213 } 6214 6215 static int 6216 bnx2_request_irq(struct bnx2 *bp) 6217 { 6218 unsigned long flags; 6219 struct bnx2_irq *irq; 6220 int rc = 0, i; 6221 6222 if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX) 6223 flags = 0; 6224 else 6225 flags = IRQF_SHARED; 6226 6227 for (i = 0; i < bp->irq_nvecs; i++) { 6228 irq = &bp->irq_tbl[i]; 6229 rc = request_irq(irq->vector, irq->handler, flags, irq->name, 6230 &bp->bnx2_napi[i]); 6231 if (rc) 6232 break; 6233 irq->requested = 1; 6234 } 6235 return rc; 6236 } 6237 6238 static void 6239 __bnx2_free_irq(struct bnx2 *bp) 6240 { 6241 struct bnx2_irq *irq; 6242 int i; 6243 6244 for (i = 0; i < bp->irq_nvecs; i++) { 6245 irq = &bp->irq_tbl[i]; 6246 if (irq->requested) 6247 free_irq(irq->vector, &bp->bnx2_napi[i]); 6248 irq->requested = 0; 6249 } 6250 } 6251 6252 static void 6253 bnx2_free_irq(struct bnx2 *bp) 6254 { 6255 6256 __bnx2_free_irq(bp); 6257 if (bp->flags & BNX2_FLAG_USING_MSI) 6258 pci_disable_msi(bp->pdev); 6259 else if (bp->flags & BNX2_FLAG_USING_MSIX) 6260 pci_disable_msix(bp->pdev); 6261 6262 bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI); 6263 } 6264 6265 static void 6266 bnx2_enable_msix(struct bnx2 *bp, int msix_vecs) 6267 { 6268 int i, total_vecs; 6269 struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC]; 6270 struct net_device *dev = bp->dev; 6271 const int len = sizeof(bp->irq_tbl[0].name); 6272 6273 bnx2_setup_msix_tbl(bp); 6274 BNX2_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1); 6275 BNX2_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE); 6276 BNX2_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE); 6277 6278 /* Need to flush the previous three writes to ensure MSI-X 6279 * is setup properly */ 6280 BNX2_RD(bp, BNX2_PCI_MSIX_CONTROL); 6281 6282 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) { 6283 msix_ent[i].entry = i; 6284 msix_ent[i].vector = 0; 6285 } 6286 6287 total_vecs = msix_vecs; 6288 #ifdef BCM_CNIC 6289 total_vecs++; 6290 #endif 6291 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, 6292 BNX2_MIN_MSIX_VEC, total_vecs); 6293 if (total_vecs < 0) 6294 return; 6295 6296 msix_vecs = total_vecs; 6297 #ifdef BCM_CNIC 6298 msix_vecs--; 6299 #endif 6300 bp->irq_nvecs = msix_vecs; 6301 bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI; 6302 for (i = 0; i < total_vecs; i++) { 6303 bp->irq_tbl[i].vector = msix_ent[i].vector; 6304 snprintf(bp->irq_tbl[i].name, len, "%s-%d", dev->name, i); 6305 bp->irq_tbl[i].handler = bnx2_msi_1shot; 6306 } 6307 } 6308 6309 static int 6310 bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi) 6311 { 6312 int cpus = netif_get_num_default_rss_queues(); 6313 int msix_vecs; 6314 6315 if (!bp->num_req_rx_rings) 6316 msix_vecs = max(cpus + 1, bp->num_req_tx_rings); 6317 else if (!bp->num_req_tx_rings) 6318 msix_vecs = max(cpus, bp->num_req_rx_rings); 6319 else 6320 msix_vecs = max(bp->num_req_rx_rings, bp->num_req_tx_rings); 6321 6322 msix_vecs = min(msix_vecs, RX_MAX_RINGS); 6323 6324 bp->irq_tbl[0].handler = bnx2_interrupt; 6325 strcpy(bp->irq_tbl[0].name, bp->dev->name); 6326 bp->irq_nvecs = 1; 6327 bp->irq_tbl[0].vector = bp->pdev->irq; 6328 6329 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi) 6330 bnx2_enable_msix(bp, msix_vecs); 6331 6332 if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi && 6333 !(bp->flags & BNX2_FLAG_USING_MSIX)) { 6334 if (pci_enable_msi(bp->pdev) == 0) { 6335 bp->flags |= BNX2_FLAG_USING_MSI; 6336 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { 6337 bp->flags |= BNX2_FLAG_ONE_SHOT_MSI; 6338 bp->irq_tbl[0].handler = bnx2_msi_1shot; 6339 } else 6340 bp->irq_tbl[0].handler = bnx2_msi; 6341 6342 bp->irq_tbl[0].vector = bp->pdev->irq; 6343 } 6344 } 6345 6346 if (!bp->num_req_tx_rings) 6347 bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs); 6348 else 6349 bp->num_tx_rings = min(bp->irq_nvecs, bp->num_req_tx_rings); 6350 6351 if (!bp->num_req_rx_rings) 6352 bp->num_rx_rings = bp->irq_nvecs; 6353 else 6354 bp->num_rx_rings = min(bp->irq_nvecs, bp->num_req_rx_rings); 6355 6356 netif_set_real_num_tx_queues(bp->dev, bp->num_tx_rings); 6357 6358 return netif_set_real_num_rx_queues(bp->dev, bp->num_rx_rings); 6359 } 6360 6361 /* Called with rtnl_lock */ 6362 static int 6363 bnx2_open(struct net_device *dev) 6364 { 6365 struct bnx2 *bp = netdev_priv(dev); 6366 int rc; 6367 6368 rc = bnx2_request_firmware(bp); 6369 if (rc < 0) 6370 goto out; 6371 6372 netif_carrier_off(dev); 6373 6374 bnx2_disable_int(bp); 6375 6376 rc = bnx2_setup_int_mode(bp, disable_msi); 6377 if (rc) 6378 goto open_err; 6379 bnx2_init_napi(bp); 6380 bnx2_napi_enable(bp); 6381 rc = bnx2_alloc_mem(bp); 6382 if (rc) 6383 goto open_err; 6384 6385 rc = bnx2_request_irq(bp); 6386 if (rc) 6387 goto open_err; 6388 6389 rc = bnx2_init_nic(bp, 1); 6390 if (rc) 6391 goto open_err; 6392 6393 mod_timer(&bp->timer, jiffies + bp->current_interval); 6394 6395 atomic_set(&bp->intr_sem, 0); 6396 6397 memset(bp->temp_stats_blk, 0, sizeof(struct statistics_block)); 6398 6399 bnx2_enable_int(bp); 6400 6401 if (bp->flags & BNX2_FLAG_USING_MSI) { 6402 /* Test MSI to make sure it is working 6403 * If MSI test fails, go back to INTx mode 6404 */ 6405 if (bnx2_test_intr(bp) != 0) { 6406 netdev_warn(bp->dev, "No interrupt was generated using MSI, switching to INTx mode. Please report this failure to the PCI maintainer and include system chipset information.\n"); 6407 6408 bnx2_disable_int(bp); 6409 bnx2_free_irq(bp); 6410 6411 bnx2_setup_int_mode(bp, 1); 6412 6413 rc = bnx2_init_nic(bp, 0); 6414 6415 if (!rc) 6416 rc = bnx2_request_irq(bp); 6417 6418 if (rc) { 6419 timer_delete_sync(&bp->timer); 6420 goto open_err; 6421 } 6422 bnx2_enable_int(bp); 6423 } 6424 } 6425 if (bp->flags & BNX2_FLAG_USING_MSI) 6426 netdev_info(dev, "using MSI\n"); 6427 else if (bp->flags & BNX2_FLAG_USING_MSIX) 6428 netdev_info(dev, "using MSIX\n"); 6429 6430 netif_tx_start_all_queues(dev); 6431 out: 6432 return rc; 6433 6434 open_err: 6435 bnx2_napi_disable(bp); 6436 bnx2_free_skbs(bp); 6437 bnx2_free_irq(bp); 6438 bnx2_free_mem(bp); 6439 bnx2_del_napi(bp); 6440 bnx2_release_firmware(bp); 6441 goto out; 6442 } 6443 6444 static void 6445 bnx2_reset_task(struct work_struct *work) 6446 { 6447 struct bnx2 *bp = container_of(work, struct bnx2, reset_task); 6448 int rc; 6449 u16 pcicmd; 6450 6451 rtnl_lock(); 6452 if (!netif_running(bp->dev)) { 6453 rtnl_unlock(); 6454 return; 6455 } 6456 6457 bnx2_netif_stop(bp, true); 6458 6459 pci_read_config_word(bp->pdev, PCI_COMMAND, &pcicmd); 6460 if (!(pcicmd & PCI_COMMAND_MEMORY)) { 6461 /* in case PCI block has reset */ 6462 pci_restore_state(bp->pdev); 6463 } 6464 rc = bnx2_init_nic(bp, 1); 6465 if (rc) { 6466 netdev_err(bp->dev, "failed to reset NIC, closing\n"); 6467 bnx2_napi_enable(bp); 6468 dev_close(bp->dev); 6469 rtnl_unlock(); 6470 return; 6471 } 6472 6473 atomic_set(&bp->intr_sem, 1); 6474 bnx2_netif_start(bp, true); 6475 rtnl_unlock(); 6476 } 6477 6478 #define BNX2_FTQ_ENTRY(ftq) { __stringify(ftq##FTQ_CTL), BNX2_##ftq##FTQ_CTL } 6479 6480 static void 6481 bnx2_dump_ftq(struct bnx2 *bp) 6482 { 6483 int i; 6484 u32 reg, bdidx, cid, valid; 6485 struct net_device *dev = bp->dev; 6486 static const struct ftq_reg { 6487 char *name; 6488 u32 off; 6489 } ftq_arr[] = { 6490 BNX2_FTQ_ENTRY(RV2P_P), 6491 BNX2_FTQ_ENTRY(RV2P_T), 6492 BNX2_FTQ_ENTRY(RV2P_M), 6493 BNX2_FTQ_ENTRY(TBDR_), 6494 BNX2_FTQ_ENTRY(TDMA_), 6495 BNX2_FTQ_ENTRY(TXP_), 6496 BNX2_FTQ_ENTRY(TXP_), 6497 BNX2_FTQ_ENTRY(TPAT_), 6498 BNX2_FTQ_ENTRY(RXP_C), 6499 BNX2_FTQ_ENTRY(RXP_), 6500 BNX2_FTQ_ENTRY(COM_COMXQ_), 6501 BNX2_FTQ_ENTRY(COM_COMTQ_), 6502 BNX2_FTQ_ENTRY(COM_COMQ_), 6503 BNX2_FTQ_ENTRY(CP_CPQ_), 6504 }; 6505 6506 netdev_err(dev, "<--- start FTQ dump --->\n"); 6507 for (i = 0; i < ARRAY_SIZE(ftq_arr); i++) 6508 netdev_err(dev, "%s %08x\n", ftq_arr[i].name, 6509 bnx2_reg_rd_ind(bp, ftq_arr[i].off)); 6510 6511 netdev_err(dev, "CPU states:\n"); 6512 for (reg = BNX2_TXP_CPU_MODE; reg <= BNX2_CP_CPU_MODE; reg += 0x40000) 6513 netdev_err(dev, "%06x mode %x state %x evt_mask %x pc %x pc %x instr %x\n", 6514 reg, bnx2_reg_rd_ind(bp, reg), 6515 bnx2_reg_rd_ind(bp, reg + 4), 6516 bnx2_reg_rd_ind(bp, reg + 8), 6517 bnx2_reg_rd_ind(bp, reg + 0x1c), 6518 bnx2_reg_rd_ind(bp, reg + 0x1c), 6519 bnx2_reg_rd_ind(bp, reg + 0x20)); 6520 6521 netdev_err(dev, "<--- end FTQ dump --->\n"); 6522 netdev_err(dev, "<--- start TBDC dump --->\n"); 6523 netdev_err(dev, "TBDC free cnt: %ld\n", 6524 BNX2_RD(bp, BNX2_TBDC_STATUS) & BNX2_TBDC_STATUS_FREE_CNT); 6525 netdev_err(dev, "LINE CID BIDX CMD VALIDS\n"); 6526 for (i = 0; i < 0x20; i++) { 6527 int j = 0; 6528 6529 BNX2_WR(bp, BNX2_TBDC_BD_ADDR, i); 6530 BNX2_WR(bp, BNX2_TBDC_CAM_OPCODE, 6531 BNX2_TBDC_CAM_OPCODE_OPCODE_CAM_READ); 6532 BNX2_WR(bp, BNX2_TBDC_COMMAND, BNX2_TBDC_COMMAND_CMD_REG_ARB); 6533 while ((BNX2_RD(bp, BNX2_TBDC_COMMAND) & 6534 BNX2_TBDC_COMMAND_CMD_REG_ARB) && j < 100) 6535 j++; 6536 6537 cid = BNX2_RD(bp, BNX2_TBDC_CID); 6538 bdidx = BNX2_RD(bp, BNX2_TBDC_BIDX); 6539 valid = BNX2_RD(bp, BNX2_TBDC_CAM_OPCODE); 6540 netdev_err(dev, "%02x %06x %04lx %02x [%x]\n", 6541 i, cid, bdidx & BNX2_TBDC_BDIDX_BDIDX, 6542 bdidx >> 24, (valid >> 8) & 0x0ff); 6543 } 6544 netdev_err(dev, "<--- end TBDC dump --->\n"); 6545 } 6546 6547 static void 6548 bnx2_dump_state(struct bnx2 *bp) 6549 { 6550 struct net_device *dev = bp->dev; 6551 u32 val1, val2; 6552 6553 pci_read_config_dword(bp->pdev, PCI_COMMAND, &val1); 6554 netdev_err(dev, "DEBUG: intr_sem[%x] PCI_CMD[%08x]\n", 6555 atomic_read(&bp->intr_sem), val1); 6556 pci_read_config_dword(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &val1); 6557 pci_read_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, &val2); 6558 netdev_err(dev, "DEBUG: PCI_PM[%08x] PCI_MISC_CFG[%08x]\n", val1, val2); 6559 netdev_err(dev, "DEBUG: EMAC_TX_STATUS[%08x] EMAC_RX_STATUS[%08x]\n", 6560 BNX2_RD(bp, BNX2_EMAC_TX_STATUS), 6561 BNX2_RD(bp, BNX2_EMAC_RX_STATUS)); 6562 netdev_err(dev, "DEBUG: RPM_MGMT_PKT_CTRL[%08x]\n", 6563 BNX2_RD(bp, BNX2_RPM_MGMT_PKT_CTRL)); 6564 netdev_err(dev, "DEBUG: HC_STATS_INTERRUPT_STATUS[%08x]\n", 6565 BNX2_RD(bp, BNX2_HC_STATS_INTERRUPT_STATUS)); 6566 if (bp->flags & BNX2_FLAG_USING_MSIX) 6567 netdev_err(dev, "DEBUG: PBA[%08x]\n", 6568 BNX2_RD(bp, BNX2_PCI_GRC_WINDOW3_BASE)); 6569 } 6570 6571 static void 6572 bnx2_tx_timeout(struct net_device *dev, unsigned int txqueue) 6573 { 6574 struct bnx2 *bp = netdev_priv(dev); 6575 6576 bnx2_dump_ftq(bp); 6577 bnx2_dump_state(bp); 6578 bnx2_dump_mcp_state(bp); 6579 6580 /* This allows the netif to be shutdown gracefully before resetting */ 6581 schedule_work(&bp->reset_task); 6582 } 6583 6584 /* Called with netif_tx_lock. 6585 * bnx2_tx_int() runs without netif_tx_lock unless it needs to call 6586 * netif_wake_queue(). 6587 */ 6588 static netdev_tx_t 6589 bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev) 6590 { 6591 struct bnx2 *bp = netdev_priv(dev); 6592 dma_addr_t mapping; 6593 struct bnx2_tx_bd *txbd; 6594 struct bnx2_sw_tx_bd *tx_buf; 6595 u32 len, vlan_tag_flags, last_frag, mss; 6596 u16 prod, ring_prod; 6597 int i; 6598 struct bnx2_napi *bnapi; 6599 struct bnx2_tx_ring_info *txr; 6600 struct netdev_queue *txq; 6601 6602 /* Determine which tx ring we will be placed on */ 6603 i = skb_get_queue_mapping(skb); 6604 bnapi = &bp->bnx2_napi[i]; 6605 txr = &bnapi->tx_ring; 6606 txq = netdev_get_tx_queue(dev, i); 6607 6608 if (unlikely(bnx2_tx_avail(bp, txr) < 6609 (skb_shinfo(skb)->nr_frags + 1))) { 6610 netif_tx_stop_queue(txq); 6611 netdev_err(dev, "BUG! Tx ring full when queue awake!\n"); 6612 6613 return NETDEV_TX_BUSY; 6614 } 6615 len = skb_headlen(skb); 6616 prod = txr->tx_prod; 6617 ring_prod = BNX2_TX_RING_IDX(prod); 6618 6619 vlan_tag_flags = 0; 6620 if (skb->ip_summed == CHECKSUM_PARTIAL) { 6621 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; 6622 } 6623 6624 if (skb_vlan_tag_present(skb)) { 6625 vlan_tag_flags |= 6626 (TX_BD_FLAGS_VLAN_TAG | (skb_vlan_tag_get(skb) << 16)); 6627 } 6628 6629 if ((mss = skb_shinfo(skb)->gso_size)) { 6630 u32 tcp_opt_len; 6631 struct iphdr *iph; 6632 6633 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO; 6634 6635 tcp_opt_len = tcp_optlen(skb); 6636 6637 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) { 6638 u32 tcp_off = skb_transport_offset(skb) - 6639 sizeof(struct ipv6hdr) - ETH_HLEN; 6640 6641 vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) | 6642 TX_BD_FLAGS_SW_FLAGS; 6643 if (likely(tcp_off == 0)) 6644 vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK; 6645 else { 6646 tcp_off >>= 3; 6647 vlan_tag_flags |= ((tcp_off & 0x3) << 6648 TX_BD_FLAGS_TCP6_OFF0_SHL) | 6649 ((tcp_off & 0x10) << 6650 TX_BD_FLAGS_TCP6_OFF4_SHL); 6651 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL; 6652 } 6653 } else { 6654 iph = ip_hdr(skb); 6655 if (tcp_opt_len || (iph->ihl > 5)) { 6656 vlan_tag_flags |= ((iph->ihl - 5) + 6657 (tcp_opt_len >> 2)) << 8; 6658 } 6659 } 6660 } else 6661 mss = 0; 6662 6663 mapping = dma_map_single(&bp->pdev->dev, skb->data, len, 6664 DMA_TO_DEVICE); 6665 if (dma_mapping_error(&bp->pdev->dev, mapping)) { 6666 dev_kfree_skb_any(skb); 6667 return NETDEV_TX_OK; 6668 } 6669 6670 tx_buf = &txr->tx_buf_ring[ring_prod]; 6671 tx_buf->skb = skb; 6672 dma_unmap_addr_set(tx_buf, mapping, mapping); 6673 6674 txbd = &txr->tx_desc_ring[ring_prod]; 6675 6676 txbd->tx_bd_haddr_hi = (u64) mapping >> 32; 6677 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff; 6678 txbd->tx_bd_mss_nbytes = len | (mss << 16); 6679 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START; 6680 6681 last_frag = skb_shinfo(skb)->nr_frags; 6682 tx_buf->nr_frags = last_frag; 6683 tx_buf->is_gso = skb_is_gso(skb); 6684 6685 for (i = 0; i < last_frag; i++) { 6686 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 6687 6688 prod = BNX2_NEXT_TX_BD(prod); 6689 ring_prod = BNX2_TX_RING_IDX(prod); 6690 txbd = &txr->tx_desc_ring[ring_prod]; 6691 6692 len = skb_frag_size(frag); 6693 mapping = skb_frag_dma_map(&bp->pdev->dev, frag, 0, len, 6694 DMA_TO_DEVICE); 6695 if (dma_mapping_error(&bp->pdev->dev, mapping)) 6696 goto dma_error; 6697 dma_unmap_addr_set(&txr->tx_buf_ring[ring_prod], mapping, 6698 mapping); 6699 6700 txbd->tx_bd_haddr_hi = (u64) mapping >> 32; 6701 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff; 6702 txbd->tx_bd_mss_nbytes = len | (mss << 16); 6703 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags; 6704 6705 } 6706 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END; 6707 6708 /* Sync BD data before updating TX mailbox */ 6709 wmb(); 6710 6711 netdev_tx_sent_queue(txq, skb->len); 6712 6713 prod = BNX2_NEXT_TX_BD(prod); 6714 txr->tx_prod_bseq += skb->len; 6715 6716 BNX2_WR16(bp, txr->tx_bidx_addr, prod); 6717 BNX2_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq); 6718 6719 txr->tx_prod = prod; 6720 6721 if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) { 6722 netif_tx_stop_queue(txq); 6723 6724 /* netif_tx_stop_queue() must be done before checking 6725 * tx index in bnx2_tx_avail() below, because in 6726 * bnx2_tx_int(), we update tx index before checking for 6727 * netif_tx_queue_stopped(). 6728 */ 6729 smp_mb(); 6730 if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh) 6731 netif_tx_wake_queue(txq); 6732 } 6733 6734 return NETDEV_TX_OK; 6735 dma_error: 6736 /* save value of frag that failed */ 6737 last_frag = i; 6738 6739 /* start back at beginning and unmap skb */ 6740 prod = txr->tx_prod; 6741 ring_prod = BNX2_TX_RING_IDX(prod); 6742 tx_buf = &txr->tx_buf_ring[ring_prod]; 6743 tx_buf->skb = NULL; 6744 dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping), 6745 skb_headlen(skb), DMA_TO_DEVICE); 6746 6747 /* unmap remaining mapped pages */ 6748 for (i = 0; i < last_frag; i++) { 6749 prod = BNX2_NEXT_TX_BD(prod); 6750 ring_prod = BNX2_TX_RING_IDX(prod); 6751 tx_buf = &txr->tx_buf_ring[ring_prod]; 6752 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping), 6753 skb_frag_size(&skb_shinfo(skb)->frags[i]), 6754 DMA_TO_DEVICE); 6755 } 6756 6757 dev_kfree_skb_any(skb); 6758 return NETDEV_TX_OK; 6759 } 6760 6761 /* Called with rtnl_lock */ 6762 static int 6763 bnx2_close(struct net_device *dev) 6764 { 6765 struct bnx2 *bp = netdev_priv(dev); 6766 6767 bnx2_disable_int_sync(bp); 6768 bnx2_napi_disable(bp); 6769 netif_tx_disable(dev); 6770 timer_delete_sync(&bp->timer); 6771 bnx2_shutdown_chip(bp); 6772 bnx2_free_irq(bp); 6773 bnx2_free_skbs(bp); 6774 bnx2_free_mem(bp); 6775 bnx2_del_napi(bp); 6776 bp->link_up = 0; 6777 netif_carrier_off(bp->dev); 6778 return 0; 6779 } 6780 6781 static void 6782 bnx2_save_stats(struct bnx2 *bp) 6783 { 6784 u32 *hw_stats = (u32 *) bp->stats_blk; 6785 u32 *temp_stats = (u32 *) bp->temp_stats_blk; 6786 int i; 6787 6788 /* The 1st 10 counters are 64-bit counters */ 6789 for (i = 0; i < 20; i += 2) { 6790 u32 hi; 6791 u64 lo; 6792 6793 hi = temp_stats[i] + hw_stats[i]; 6794 lo = (u64) temp_stats[i + 1] + (u64) hw_stats[i + 1]; 6795 if (lo > 0xffffffff) 6796 hi++; 6797 temp_stats[i] = hi; 6798 temp_stats[i + 1] = lo & 0xffffffff; 6799 } 6800 6801 for ( ; i < sizeof(struct statistics_block) / 4; i++) 6802 temp_stats[i] += hw_stats[i]; 6803 } 6804 6805 #define GET_64BIT_NET_STATS64(ctr) \ 6806 (((u64) (ctr##_hi) << 32) + (u64) (ctr##_lo)) 6807 6808 #define GET_64BIT_NET_STATS(ctr) \ 6809 GET_64BIT_NET_STATS64(bp->stats_blk->ctr) + \ 6810 GET_64BIT_NET_STATS64(bp->temp_stats_blk->ctr) 6811 6812 #define GET_32BIT_NET_STATS(ctr) \ 6813 (unsigned long) (bp->stats_blk->ctr + \ 6814 bp->temp_stats_blk->ctr) 6815 6816 static void 6817 bnx2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *net_stats) 6818 { 6819 struct bnx2 *bp = netdev_priv(dev); 6820 6821 if (!bp->stats_blk) 6822 return; 6823 6824 net_stats->rx_packets = 6825 GET_64BIT_NET_STATS(stat_IfHCInUcastPkts) + 6826 GET_64BIT_NET_STATS(stat_IfHCInMulticastPkts) + 6827 GET_64BIT_NET_STATS(stat_IfHCInBroadcastPkts); 6828 6829 net_stats->tx_packets = 6830 GET_64BIT_NET_STATS(stat_IfHCOutUcastPkts) + 6831 GET_64BIT_NET_STATS(stat_IfHCOutMulticastPkts) + 6832 GET_64BIT_NET_STATS(stat_IfHCOutBroadcastPkts); 6833 6834 net_stats->rx_bytes = 6835 GET_64BIT_NET_STATS(stat_IfHCInOctets); 6836 6837 net_stats->tx_bytes = 6838 GET_64BIT_NET_STATS(stat_IfHCOutOctets); 6839 6840 net_stats->multicast = 6841 GET_64BIT_NET_STATS(stat_IfHCInMulticastPkts); 6842 6843 net_stats->collisions = 6844 GET_32BIT_NET_STATS(stat_EtherStatsCollisions); 6845 6846 net_stats->rx_length_errors = 6847 GET_32BIT_NET_STATS(stat_EtherStatsUndersizePkts) + 6848 GET_32BIT_NET_STATS(stat_EtherStatsOverrsizePkts); 6849 6850 net_stats->rx_over_errors = 6851 GET_32BIT_NET_STATS(stat_IfInFTQDiscards) + 6852 GET_32BIT_NET_STATS(stat_IfInMBUFDiscards); 6853 6854 net_stats->rx_frame_errors = 6855 GET_32BIT_NET_STATS(stat_Dot3StatsAlignmentErrors); 6856 6857 net_stats->rx_crc_errors = 6858 GET_32BIT_NET_STATS(stat_Dot3StatsFCSErrors); 6859 6860 net_stats->rx_errors = net_stats->rx_length_errors + 6861 net_stats->rx_over_errors + net_stats->rx_frame_errors + 6862 net_stats->rx_crc_errors; 6863 6864 net_stats->tx_aborted_errors = 6865 GET_32BIT_NET_STATS(stat_Dot3StatsExcessiveCollisions) + 6866 GET_32BIT_NET_STATS(stat_Dot3StatsLateCollisions); 6867 6868 if ((BNX2_CHIP(bp) == BNX2_CHIP_5706) || 6869 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0)) 6870 net_stats->tx_carrier_errors = 0; 6871 else { 6872 net_stats->tx_carrier_errors = 6873 GET_32BIT_NET_STATS(stat_Dot3StatsCarrierSenseErrors); 6874 } 6875 6876 net_stats->tx_errors = 6877 GET_32BIT_NET_STATS(stat_emac_tx_stat_dot3statsinternalmactransmiterrors) + 6878 net_stats->tx_aborted_errors + 6879 net_stats->tx_carrier_errors; 6880 6881 net_stats->rx_missed_errors = 6882 GET_32BIT_NET_STATS(stat_IfInFTQDiscards) + 6883 GET_32BIT_NET_STATS(stat_IfInMBUFDiscards) + 6884 GET_32BIT_NET_STATS(stat_FwRxDrop); 6885 6886 } 6887 6888 /* All ethtool functions called with rtnl_lock */ 6889 6890 static int 6891 bnx2_get_link_ksettings(struct net_device *dev, 6892 struct ethtool_link_ksettings *cmd) 6893 { 6894 struct bnx2 *bp = netdev_priv(dev); 6895 int support_serdes = 0, support_copper = 0; 6896 u32 supported, advertising; 6897 6898 supported = SUPPORTED_Autoneg; 6899 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) { 6900 support_serdes = 1; 6901 support_copper = 1; 6902 } else if (bp->phy_port == PORT_FIBRE) 6903 support_serdes = 1; 6904 else 6905 support_copper = 1; 6906 6907 if (support_serdes) { 6908 supported |= SUPPORTED_1000baseT_Full | 6909 SUPPORTED_FIBRE; 6910 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) 6911 supported |= SUPPORTED_2500baseX_Full; 6912 } 6913 if (support_copper) { 6914 supported |= SUPPORTED_10baseT_Half | 6915 SUPPORTED_10baseT_Full | 6916 SUPPORTED_100baseT_Half | 6917 SUPPORTED_100baseT_Full | 6918 SUPPORTED_1000baseT_Full | 6919 SUPPORTED_TP; 6920 } 6921 6922 spin_lock_bh(&bp->phy_lock); 6923 cmd->base.port = bp->phy_port; 6924 advertising = bp->advertising; 6925 6926 if (bp->autoneg & AUTONEG_SPEED) { 6927 cmd->base.autoneg = AUTONEG_ENABLE; 6928 } else { 6929 cmd->base.autoneg = AUTONEG_DISABLE; 6930 } 6931 6932 if (netif_carrier_ok(dev)) { 6933 cmd->base.speed = bp->line_speed; 6934 cmd->base.duplex = bp->duplex; 6935 if (!(bp->phy_flags & BNX2_PHY_FLAG_SERDES)) { 6936 if (bp->phy_flags & BNX2_PHY_FLAG_MDIX) 6937 cmd->base.eth_tp_mdix = ETH_TP_MDI_X; 6938 else 6939 cmd->base.eth_tp_mdix = ETH_TP_MDI; 6940 } 6941 } 6942 else { 6943 cmd->base.speed = SPEED_UNKNOWN; 6944 cmd->base.duplex = DUPLEX_UNKNOWN; 6945 } 6946 spin_unlock_bh(&bp->phy_lock); 6947 6948 cmd->base.phy_address = bp->phy_addr; 6949 6950 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 6951 supported); 6952 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 6953 advertising); 6954 6955 return 0; 6956 } 6957 6958 static int 6959 bnx2_set_link_ksettings(struct net_device *dev, 6960 const struct ethtool_link_ksettings *cmd) 6961 { 6962 struct bnx2 *bp = netdev_priv(dev); 6963 u8 autoneg = bp->autoneg; 6964 u8 req_duplex = bp->req_duplex; 6965 u16 req_line_speed = bp->req_line_speed; 6966 u32 advertising = bp->advertising; 6967 int err = -EINVAL; 6968 6969 spin_lock_bh(&bp->phy_lock); 6970 6971 if (cmd->base.port != PORT_TP && cmd->base.port != PORT_FIBRE) 6972 goto err_out_unlock; 6973 6974 if (cmd->base.port != bp->phy_port && 6975 !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)) 6976 goto err_out_unlock; 6977 6978 /* If device is down, we can store the settings only if the user 6979 * is setting the currently active port. 6980 */ 6981 if (!netif_running(dev) && cmd->base.port != bp->phy_port) 6982 goto err_out_unlock; 6983 6984 if (cmd->base.autoneg == AUTONEG_ENABLE) { 6985 autoneg |= AUTONEG_SPEED; 6986 6987 ethtool_convert_link_mode_to_legacy_u32( 6988 &advertising, cmd->link_modes.advertising); 6989 6990 if (cmd->base.port == PORT_TP) { 6991 advertising &= ETHTOOL_ALL_COPPER_SPEED; 6992 if (!advertising) 6993 advertising = ETHTOOL_ALL_COPPER_SPEED; 6994 } else { 6995 advertising &= ETHTOOL_ALL_FIBRE_SPEED; 6996 if (!advertising) 6997 advertising = ETHTOOL_ALL_FIBRE_SPEED; 6998 } 6999 advertising |= ADVERTISED_Autoneg; 7000 } 7001 else { 7002 u32 speed = cmd->base.speed; 7003 7004 if (cmd->base.port == PORT_FIBRE) { 7005 if ((speed != SPEED_1000 && 7006 speed != SPEED_2500) || 7007 (cmd->base.duplex != DUPLEX_FULL)) 7008 goto err_out_unlock; 7009 7010 if (speed == SPEED_2500 && 7011 !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) 7012 goto err_out_unlock; 7013 } else if (speed == SPEED_1000 || speed == SPEED_2500) 7014 goto err_out_unlock; 7015 7016 autoneg &= ~AUTONEG_SPEED; 7017 req_line_speed = speed; 7018 req_duplex = cmd->base.duplex; 7019 advertising = 0; 7020 } 7021 7022 bp->autoneg = autoneg; 7023 bp->advertising = advertising; 7024 bp->req_line_speed = req_line_speed; 7025 bp->req_duplex = req_duplex; 7026 7027 err = 0; 7028 /* If device is down, the new settings will be picked up when it is 7029 * brought up. 7030 */ 7031 if (netif_running(dev)) 7032 err = bnx2_setup_phy(bp, cmd->base.port); 7033 7034 err_out_unlock: 7035 spin_unlock_bh(&bp->phy_lock); 7036 7037 return err; 7038 } 7039 7040 static void 7041 bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 7042 { 7043 struct bnx2 *bp = netdev_priv(dev); 7044 7045 strscpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); 7046 strscpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info)); 7047 strscpy(info->fw_version, bp->fw_version, sizeof(info->fw_version)); 7048 } 7049 7050 #define BNX2_REGDUMP_LEN (32 * 1024) 7051 7052 static int 7053 bnx2_get_regs_len(struct net_device *dev) 7054 { 7055 return BNX2_REGDUMP_LEN; 7056 } 7057 7058 static void 7059 bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p) 7060 { 7061 u32 *p = _p, i, offset; 7062 u8 *orig_p = _p; 7063 struct bnx2 *bp = netdev_priv(dev); 7064 static const u32 reg_boundaries[] = { 7065 0x0000, 0x0098, 0x0400, 0x045c, 7066 0x0800, 0x0880, 0x0c00, 0x0c10, 7067 0x0c30, 0x0d08, 0x1000, 0x101c, 7068 0x1040, 0x1048, 0x1080, 0x10a4, 7069 0x1400, 0x1490, 0x1498, 0x14f0, 7070 0x1500, 0x155c, 0x1580, 0x15dc, 7071 0x1600, 0x1658, 0x1680, 0x16d8, 7072 0x1800, 0x1820, 0x1840, 0x1854, 7073 0x1880, 0x1894, 0x1900, 0x1984, 7074 0x1c00, 0x1c0c, 0x1c40, 0x1c54, 7075 0x1c80, 0x1c94, 0x1d00, 0x1d84, 7076 0x2000, 0x2030, 0x23c0, 0x2400, 7077 0x2800, 0x2820, 0x2830, 0x2850, 7078 0x2b40, 0x2c10, 0x2fc0, 0x3058, 7079 0x3c00, 0x3c94, 0x4000, 0x4010, 7080 0x4080, 0x4090, 0x43c0, 0x4458, 7081 0x4c00, 0x4c18, 0x4c40, 0x4c54, 7082 0x4fc0, 0x5010, 0x53c0, 0x5444, 7083 0x5c00, 0x5c18, 0x5c80, 0x5c90, 7084 0x5fc0, 0x6000, 0x6400, 0x6428, 7085 0x6800, 0x6848, 0x684c, 0x6860, 7086 0x6888, 0x6910, 0x8000 7087 }; 7088 7089 regs->version = 0; 7090 7091 memset(p, 0, BNX2_REGDUMP_LEN); 7092 7093 if (!netif_running(bp->dev)) 7094 return; 7095 7096 i = 0; 7097 offset = reg_boundaries[0]; 7098 p += offset; 7099 while (offset < BNX2_REGDUMP_LEN) { 7100 *p++ = BNX2_RD(bp, offset); 7101 offset += 4; 7102 if (offset == reg_boundaries[i + 1]) { 7103 offset = reg_boundaries[i + 2]; 7104 p = (u32 *) (orig_p + offset); 7105 i += 2; 7106 } 7107 } 7108 } 7109 7110 static void 7111 bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 7112 { 7113 struct bnx2 *bp = netdev_priv(dev); 7114 7115 if (bp->flags & BNX2_FLAG_NO_WOL) { 7116 wol->supported = 0; 7117 wol->wolopts = 0; 7118 } 7119 else { 7120 wol->supported = WAKE_MAGIC; 7121 if (bp->wol) 7122 wol->wolopts = WAKE_MAGIC; 7123 else 7124 wol->wolopts = 0; 7125 } 7126 memset(&wol->sopass, 0, sizeof(wol->sopass)); 7127 } 7128 7129 static int 7130 bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 7131 { 7132 struct bnx2 *bp = netdev_priv(dev); 7133 7134 if (wol->wolopts & ~WAKE_MAGIC) 7135 return -EINVAL; 7136 7137 if (wol->wolopts & WAKE_MAGIC) { 7138 if (bp->flags & BNX2_FLAG_NO_WOL) 7139 return -EINVAL; 7140 7141 bp->wol = 1; 7142 } 7143 else { 7144 bp->wol = 0; 7145 } 7146 7147 device_set_wakeup_enable(&bp->pdev->dev, bp->wol); 7148 7149 return 0; 7150 } 7151 7152 static int 7153 bnx2_nway_reset(struct net_device *dev) 7154 { 7155 struct bnx2 *bp = netdev_priv(dev); 7156 u32 bmcr; 7157 7158 if (!netif_running(dev)) 7159 return -EAGAIN; 7160 7161 if (!(bp->autoneg & AUTONEG_SPEED)) { 7162 return -EINVAL; 7163 } 7164 7165 spin_lock_bh(&bp->phy_lock); 7166 7167 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) { 7168 int rc; 7169 7170 rc = bnx2_setup_remote_phy(bp, bp->phy_port); 7171 spin_unlock_bh(&bp->phy_lock); 7172 return rc; 7173 } 7174 7175 /* Force a link down visible on the other side */ 7176 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { 7177 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK); 7178 spin_unlock_bh(&bp->phy_lock); 7179 7180 msleep(20); 7181 7182 spin_lock_bh(&bp->phy_lock); 7183 7184 bp->current_interval = BNX2_SERDES_AN_TIMEOUT; 7185 bp->serdes_an_pending = 1; 7186 mod_timer(&bp->timer, jiffies + bp->current_interval); 7187 } 7188 7189 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); 7190 bmcr &= ~BMCR_LOOPBACK; 7191 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE); 7192 7193 spin_unlock_bh(&bp->phy_lock); 7194 7195 return 0; 7196 } 7197 7198 static u32 7199 bnx2_get_link(struct net_device *dev) 7200 { 7201 struct bnx2 *bp = netdev_priv(dev); 7202 7203 return bp->link_up; 7204 } 7205 7206 static int 7207 bnx2_get_eeprom_len(struct net_device *dev) 7208 { 7209 struct bnx2 *bp = netdev_priv(dev); 7210 7211 if (!bp->flash_info) 7212 return 0; 7213 7214 return (int) bp->flash_size; 7215 } 7216 7217 static int 7218 bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, 7219 u8 *eebuf) 7220 { 7221 struct bnx2 *bp = netdev_priv(dev); 7222 int rc; 7223 7224 /* parameters already validated in ethtool_get_eeprom */ 7225 7226 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len); 7227 7228 return rc; 7229 } 7230 7231 static int 7232 bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, 7233 u8 *eebuf) 7234 { 7235 struct bnx2 *bp = netdev_priv(dev); 7236 int rc; 7237 7238 /* parameters already validated in ethtool_set_eeprom */ 7239 7240 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len); 7241 7242 return rc; 7243 } 7244 7245 static int bnx2_get_coalesce(struct net_device *dev, 7246 struct ethtool_coalesce *coal, 7247 struct kernel_ethtool_coalesce *kernel_coal, 7248 struct netlink_ext_ack *extack) 7249 { 7250 struct bnx2 *bp = netdev_priv(dev); 7251 7252 memset(coal, 0, sizeof(struct ethtool_coalesce)); 7253 7254 coal->rx_coalesce_usecs = bp->rx_ticks; 7255 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip; 7256 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int; 7257 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int; 7258 7259 coal->tx_coalesce_usecs = bp->tx_ticks; 7260 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip; 7261 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int; 7262 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int; 7263 7264 coal->stats_block_coalesce_usecs = bp->stats_ticks; 7265 7266 return 0; 7267 } 7268 7269 static int bnx2_set_coalesce(struct net_device *dev, 7270 struct ethtool_coalesce *coal, 7271 struct kernel_ethtool_coalesce *kernel_coal, 7272 struct netlink_ext_ack *extack) 7273 { 7274 struct bnx2 *bp = netdev_priv(dev); 7275 7276 bp->rx_ticks = (u16) coal->rx_coalesce_usecs; 7277 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff; 7278 7279 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames; 7280 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff; 7281 7282 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq; 7283 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff; 7284 7285 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq; 7286 if (bp->rx_quick_cons_trip_int > 0xff) 7287 bp->rx_quick_cons_trip_int = 0xff; 7288 7289 bp->tx_ticks = (u16) coal->tx_coalesce_usecs; 7290 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff; 7291 7292 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames; 7293 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff; 7294 7295 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq; 7296 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff; 7297 7298 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq; 7299 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int = 7300 0xff; 7301 7302 bp->stats_ticks = coal->stats_block_coalesce_usecs; 7303 if (bp->flags & BNX2_FLAG_BROKEN_STATS) { 7304 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC) 7305 bp->stats_ticks = USEC_PER_SEC; 7306 } 7307 if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS) 7308 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS; 7309 bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS; 7310 7311 if (netif_running(bp->dev)) { 7312 bnx2_netif_stop(bp, true); 7313 bnx2_init_nic(bp, 0); 7314 bnx2_netif_start(bp, true); 7315 } 7316 7317 return 0; 7318 } 7319 7320 static void 7321 bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering, 7322 struct kernel_ethtool_ringparam *kernel_ering, 7323 struct netlink_ext_ack *extack) 7324 { 7325 struct bnx2 *bp = netdev_priv(dev); 7326 7327 ering->rx_max_pending = BNX2_MAX_TOTAL_RX_DESC_CNT; 7328 ering->rx_jumbo_max_pending = BNX2_MAX_TOTAL_RX_PG_DESC_CNT; 7329 7330 ering->rx_pending = bp->rx_ring_size; 7331 ering->rx_jumbo_pending = bp->rx_pg_ring_size; 7332 7333 ering->tx_max_pending = BNX2_MAX_TX_DESC_CNT; 7334 ering->tx_pending = bp->tx_ring_size; 7335 } 7336 7337 static int 7338 bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx, bool reset_irq) 7339 { 7340 if (netif_running(bp->dev)) { 7341 /* Reset will erase chipset stats; save them */ 7342 bnx2_save_stats(bp); 7343 7344 bnx2_netif_stop(bp, true); 7345 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET); 7346 if (reset_irq) { 7347 bnx2_free_irq(bp); 7348 bnx2_del_napi(bp); 7349 } else { 7350 __bnx2_free_irq(bp); 7351 } 7352 bnx2_free_skbs(bp); 7353 bnx2_free_mem(bp); 7354 } 7355 7356 bnx2_set_rx_ring_size(bp, rx); 7357 bp->tx_ring_size = tx; 7358 7359 if (netif_running(bp->dev)) { 7360 int rc = 0; 7361 7362 if (reset_irq) { 7363 rc = bnx2_setup_int_mode(bp, disable_msi); 7364 bnx2_init_napi(bp); 7365 } 7366 7367 if (!rc) 7368 rc = bnx2_alloc_mem(bp); 7369 7370 if (!rc) 7371 rc = bnx2_request_irq(bp); 7372 7373 if (!rc) 7374 rc = bnx2_init_nic(bp, 0); 7375 7376 if (rc) { 7377 bnx2_napi_enable(bp); 7378 dev_close(bp->dev); 7379 return rc; 7380 } 7381 #ifdef BCM_CNIC 7382 mutex_lock(&bp->cnic_lock); 7383 /* Let cnic know about the new status block. */ 7384 if (bp->cnic_eth_dev.drv_state & CNIC_DRV_STATE_REGD) 7385 bnx2_setup_cnic_irq_info(bp); 7386 mutex_unlock(&bp->cnic_lock); 7387 #endif 7388 bnx2_netif_start(bp, true); 7389 } 7390 return 0; 7391 } 7392 7393 static int 7394 bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering, 7395 struct kernel_ethtool_ringparam *kernel_ering, 7396 struct netlink_ext_ack *extack) 7397 { 7398 struct bnx2 *bp = netdev_priv(dev); 7399 int rc; 7400 7401 if ((ering->rx_pending > BNX2_MAX_TOTAL_RX_DESC_CNT) || 7402 (ering->tx_pending > BNX2_MAX_TX_DESC_CNT) || 7403 (ering->tx_pending <= MAX_SKB_FRAGS)) { 7404 7405 return -EINVAL; 7406 } 7407 rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending, 7408 false); 7409 return rc; 7410 } 7411 7412 static void 7413 bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) 7414 { 7415 struct bnx2 *bp = netdev_priv(dev); 7416 7417 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0); 7418 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0); 7419 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0); 7420 } 7421 7422 static int 7423 bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) 7424 { 7425 struct bnx2 *bp = netdev_priv(dev); 7426 7427 bp->req_flow_ctrl = 0; 7428 if (epause->rx_pause) 7429 bp->req_flow_ctrl |= FLOW_CTRL_RX; 7430 if (epause->tx_pause) 7431 bp->req_flow_ctrl |= FLOW_CTRL_TX; 7432 7433 if (epause->autoneg) { 7434 bp->autoneg |= AUTONEG_FLOW_CTRL; 7435 } 7436 else { 7437 bp->autoneg &= ~AUTONEG_FLOW_CTRL; 7438 } 7439 7440 if (netif_running(dev)) { 7441 spin_lock_bh(&bp->phy_lock); 7442 bnx2_setup_phy(bp, bp->phy_port); 7443 spin_unlock_bh(&bp->phy_lock); 7444 } 7445 7446 return 0; 7447 } 7448 7449 static struct { 7450 char string[ETH_GSTRING_LEN]; 7451 } bnx2_stats_str_arr[] = { 7452 { "rx_bytes" }, 7453 { "rx_error_bytes" }, 7454 { "tx_bytes" }, 7455 { "tx_error_bytes" }, 7456 { "rx_ucast_packets" }, 7457 { "rx_mcast_packets" }, 7458 { "rx_bcast_packets" }, 7459 { "tx_ucast_packets" }, 7460 { "tx_mcast_packets" }, 7461 { "tx_bcast_packets" }, 7462 { "tx_mac_errors" }, 7463 { "tx_carrier_errors" }, 7464 { "rx_crc_errors" }, 7465 { "rx_align_errors" }, 7466 { "tx_single_collisions" }, 7467 { "tx_multi_collisions" }, 7468 { "tx_deferred" }, 7469 { "tx_excess_collisions" }, 7470 { "tx_late_collisions" }, 7471 { "tx_total_collisions" }, 7472 { "rx_fragments" }, 7473 { "rx_jabbers" }, 7474 { "rx_undersize_packets" }, 7475 { "rx_oversize_packets" }, 7476 { "rx_64_byte_packets" }, 7477 { "rx_65_to_127_byte_packets" }, 7478 { "rx_128_to_255_byte_packets" }, 7479 { "rx_256_to_511_byte_packets" }, 7480 { "rx_512_to_1023_byte_packets" }, 7481 { "rx_1024_to_1522_byte_packets" }, 7482 { "rx_1523_to_9022_byte_packets" }, 7483 { "tx_64_byte_packets" }, 7484 { "tx_65_to_127_byte_packets" }, 7485 { "tx_128_to_255_byte_packets" }, 7486 { "tx_256_to_511_byte_packets" }, 7487 { "tx_512_to_1023_byte_packets" }, 7488 { "tx_1024_to_1522_byte_packets" }, 7489 { "tx_1523_to_9022_byte_packets" }, 7490 { "rx_xon_frames" }, 7491 { "rx_xoff_frames" }, 7492 { "tx_xon_frames" }, 7493 { "tx_xoff_frames" }, 7494 { "rx_mac_ctrl_frames" }, 7495 { "rx_filtered_packets" }, 7496 { "rx_ftq_discards" }, 7497 { "rx_discards" }, 7498 { "rx_fw_discards" }, 7499 }; 7500 7501 #define BNX2_NUM_STATS ARRAY_SIZE(bnx2_stats_str_arr) 7502 7503 #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4) 7504 7505 static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = { 7506 STATS_OFFSET32(stat_IfHCInOctets_hi), 7507 STATS_OFFSET32(stat_IfHCInBadOctets_hi), 7508 STATS_OFFSET32(stat_IfHCOutOctets_hi), 7509 STATS_OFFSET32(stat_IfHCOutBadOctets_hi), 7510 STATS_OFFSET32(stat_IfHCInUcastPkts_hi), 7511 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi), 7512 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi), 7513 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi), 7514 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi), 7515 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi), 7516 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors), 7517 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors), 7518 STATS_OFFSET32(stat_Dot3StatsFCSErrors), 7519 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors), 7520 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames), 7521 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames), 7522 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions), 7523 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions), 7524 STATS_OFFSET32(stat_Dot3StatsLateCollisions), 7525 STATS_OFFSET32(stat_EtherStatsCollisions), 7526 STATS_OFFSET32(stat_EtherStatsFragments), 7527 STATS_OFFSET32(stat_EtherStatsJabbers), 7528 STATS_OFFSET32(stat_EtherStatsUndersizePkts), 7529 STATS_OFFSET32(stat_EtherStatsOverrsizePkts), 7530 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets), 7531 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets), 7532 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets), 7533 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets), 7534 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets), 7535 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets), 7536 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets), 7537 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets), 7538 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets), 7539 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets), 7540 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets), 7541 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets), 7542 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets), 7543 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets), 7544 STATS_OFFSET32(stat_XonPauseFramesReceived), 7545 STATS_OFFSET32(stat_XoffPauseFramesReceived), 7546 STATS_OFFSET32(stat_OutXonSent), 7547 STATS_OFFSET32(stat_OutXoffSent), 7548 STATS_OFFSET32(stat_MacControlFramesReceived), 7549 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards), 7550 STATS_OFFSET32(stat_IfInFTQDiscards), 7551 STATS_OFFSET32(stat_IfInMBUFDiscards), 7552 STATS_OFFSET32(stat_FwRxDrop), 7553 }; 7554 7555 /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are 7556 * skipped because of errata. 7557 */ 7558 static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = { 7559 8,0,8,8,8,8,8,8,8,8, 7560 4,0,4,4,4,4,4,4,4,4, 7561 4,4,4,4,4,4,4,4,4,4, 7562 4,4,4,4,4,4,4,4,4,4, 7563 4,4,4,4,4,4,4, 7564 }; 7565 7566 static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = { 7567 8,0,8,8,8,8,8,8,8,8, 7568 4,4,4,4,4,4,4,4,4,4, 7569 4,4,4,4,4,4,4,4,4,4, 7570 4,4,4,4,4,4,4,4,4,4, 7571 4,4,4,4,4,4,4, 7572 }; 7573 7574 #define BNX2_NUM_TESTS 6 7575 7576 static struct { 7577 char string[ETH_GSTRING_LEN]; 7578 } bnx2_tests_str_arr[BNX2_NUM_TESTS] = { 7579 { "register_test (offline)" }, 7580 { "memory_test (offline)" }, 7581 { "loopback_test (offline)" }, 7582 { "nvram_test (online)" }, 7583 { "interrupt_test (online)" }, 7584 { "link_test (online)" }, 7585 }; 7586 7587 static int 7588 bnx2_get_sset_count(struct net_device *dev, int sset) 7589 { 7590 switch (sset) { 7591 case ETH_SS_TEST: 7592 return BNX2_NUM_TESTS; 7593 case ETH_SS_STATS: 7594 return BNX2_NUM_STATS; 7595 default: 7596 return -EOPNOTSUPP; 7597 } 7598 } 7599 7600 static void 7601 bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf) 7602 { 7603 struct bnx2 *bp = netdev_priv(dev); 7604 7605 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS); 7606 if (etest->flags & ETH_TEST_FL_OFFLINE) { 7607 int i; 7608 7609 bnx2_netif_stop(bp, true); 7610 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG); 7611 bnx2_free_skbs(bp); 7612 7613 if (bnx2_test_registers(bp) != 0) { 7614 buf[0] = 1; 7615 etest->flags |= ETH_TEST_FL_FAILED; 7616 } 7617 if (bnx2_test_memory(bp) != 0) { 7618 buf[1] = 1; 7619 etest->flags |= ETH_TEST_FL_FAILED; 7620 } 7621 if ((buf[2] = bnx2_test_loopback(bp)) != 0) 7622 etest->flags |= ETH_TEST_FL_FAILED; 7623 7624 if (!netif_running(bp->dev)) 7625 bnx2_shutdown_chip(bp); 7626 else { 7627 bnx2_init_nic(bp, 1); 7628 bnx2_netif_start(bp, true); 7629 } 7630 7631 /* wait for link up */ 7632 for (i = 0; i < 7; i++) { 7633 if (bp->link_up) 7634 break; 7635 msleep_interruptible(1000); 7636 } 7637 } 7638 7639 if (bnx2_test_nvram(bp) != 0) { 7640 buf[3] = 1; 7641 etest->flags |= ETH_TEST_FL_FAILED; 7642 } 7643 if (bnx2_test_intr(bp) != 0) { 7644 buf[4] = 1; 7645 etest->flags |= ETH_TEST_FL_FAILED; 7646 } 7647 7648 if (bnx2_test_link(bp) != 0) { 7649 buf[5] = 1; 7650 etest->flags |= ETH_TEST_FL_FAILED; 7651 7652 } 7653 } 7654 7655 static void 7656 bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf) 7657 { 7658 switch (stringset) { 7659 case ETH_SS_STATS: 7660 memcpy(buf, bnx2_stats_str_arr, 7661 sizeof(bnx2_stats_str_arr)); 7662 break; 7663 case ETH_SS_TEST: 7664 memcpy(buf, bnx2_tests_str_arr, 7665 sizeof(bnx2_tests_str_arr)); 7666 break; 7667 } 7668 } 7669 7670 static void 7671 bnx2_get_ethtool_stats(struct net_device *dev, 7672 struct ethtool_stats *stats, u64 *buf) 7673 { 7674 struct bnx2 *bp = netdev_priv(dev); 7675 int i; 7676 u32 *hw_stats = (u32 *) bp->stats_blk; 7677 u32 *temp_stats = (u32 *) bp->temp_stats_blk; 7678 u8 *stats_len_arr = NULL; 7679 7680 if (!hw_stats) { 7681 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS); 7682 return; 7683 } 7684 7685 if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) || 7686 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1) || 7687 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A2) || 7688 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0)) 7689 stats_len_arr = bnx2_5706_stats_len_arr; 7690 else 7691 stats_len_arr = bnx2_5708_stats_len_arr; 7692 7693 for (i = 0; i < BNX2_NUM_STATS; i++) { 7694 unsigned long offset; 7695 7696 if (stats_len_arr[i] == 0) { 7697 /* skip this counter */ 7698 buf[i] = 0; 7699 continue; 7700 } 7701 7702 offset = bnx2_stats_offset_arr[i]; 7703 if (stats_len_arr[i] == 4) { 7704 /* 4-byte counter */ 7705 buf[i] = (u64) *(hw_stats + offset) + 7706 *(temp_stats + offset); 7707 continue; 7708 } 7709 /* 8-byte counter */ 7710 buf[i] = (((u64) *(hw_stats + offset)) << 32) + 7711 *(hw_stats + offset + 1) + 7712 (((u64) *(temp_stats + offset)) << 32) + 7713 *(temp_stats + offset + 1); 7714 } 7715 } 7716 7717 static int 7718 bnx2_set_phys_id(struct net_device *dev, enum ethtool_phys_id_state state) 7719 { 7720 struct bnx2 *bp = netdev_priv(dev); 7721 7722 switch (state) { 7723 case ETHTOOL_ID_ACTIVE: 7724 bp->leds_save = BNX2_RD(bp, BNX2_MISC_CFG); 7725 BNX2_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC); 7726 return 1; /* cycle on/off once per second */ 7727 7728 case ETHTOOL_ID_ON: 7729 BNX2_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE | 7730 BNX2_EMAC_LED_1000MB_OVERRIDE | 7731 BNX2_EMAC_LED_100MB_OVERRIDE | 7732 BNX2_EMAC_LED_10MB_OVERRIDE | 7733 BNX2_EMAC_LED_TRAFFIC_OVERRIDE | 7734 BNX2_EMAC_LED_TRAFFIC); 7735 break; 7736 7737 case ETHTOOL_ID_OFF: 7738 BNX2_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE); 7739 break; 7740 7741 case ETHTOOL_ID_INACTIVE: 7742 BNX2_WR(bp, BNX2_EMAC_LED, 0); 7743 BNX2_WR(bp, BNX2_MISC_CFG, bp->leds_save); 7744 break; 7745 } 7746 7747 return 0; 7748 } 7749 7750 static int 7751 bnx2_set_features(struct net_device *dev, netdev_features_t features) 7752 { 7753 struct bnx2 *bp = netdev_priv(dev); 7754 7755 /* TSO with VLAN tag won't work with current firmware */ 7756 if (features & NETIF_F_HW_VLAN_CTAG_TX) 7757 dev->vlan_features |= (dev->hw_features & NETIF_F_ALL_TSO); 7758 else 7759 dev->vlan_features &= ~NETIF_F_ALL_TSO; 7760 7761 if ((!!(features & NETIF_F_HW_VLAN_CTAG_RX) != 7762 !!(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) && 7763 netif_running(dev)) { 7764 bnx2_netif_stop(bp, false); 7765 dev->features = features; 7766 bnx2_set_rx_mode(dev); 7767 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1); 7768 bnx2_netif_start(bp, false); 7769 return 1; 7770 } 7771 7772 return 0; 7773 } 7774 7775 static void bnx2_get_channels(struct net_device *dev, 7776 struct ethtool_channels *channels) 7777 { 7778 struct bnx2 *bp = netdev_priv(dev); 7779 u32 max_rx_rings = 1; 7780 u32 max_tx_rings = 1; 7781 7782 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !disable_msi) { 7783 max_rx_rings = RX_MAX_RINGS; 7784 max_tx_rings = TX_MAX_RINGS; 7785 } 7786 7787 channels->max_rx = max_rx_rings; 7788 channels->max_tx = max_tx_rings; 7789 channels->max_other = 0; 7790 channels->max_combined = 0; 7791 channels->rx_count = bp->num_rx_rings; 7792 channels->tx_count = bp->num_tx_rings; 7793 channels->other_count = 0; 7794 channels->combined_count = 0; 7795 } 7796 7797 static int bnx2_set_channels(struct net_device *dev, 7798 struct ethtool_channels *channels) 7799 { 7800 struct bnx2 *bp = netdev_priv(dev); 7801 u32 max_rx_rings = 1; 7802 u32 max_tx_rings = 1; 7803 int rc = 0; 7804 7805 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !disable_msi) { 7806 max_rx_rings = RX_MAX_RINGS; 7807 max_tx_rings = TX_MAX_RINGS; 7808 } 7809 if (channels->rx_count > max_rx_rings || 7810 channels->tx_count > max_tx_rings) 7811 return -EINVAL; 7812 7813 bp->num_req_rx_rings = channels->rx_count; 7814 bp->num_req_tx_rings = channels->tx_count; 7815 7816 if (netif_running(dev)) 7817 rc = bnx2_change_ring_size(bp, bp->rx_ring_size, 7818 bp->tx_ring_size, true); 7819 7820 return rc; 7821 } 7822 7823 static const struct ethtool_ops bnx2_ethtool_ops = { 7824 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 7825 ETHTOOL_COALESCE_MAX_FRAMES | 7826 ETHTOOL_COALESCE_USECS_IRQ | 7827 ETHTOOL_COALESCE_MAX_FRAMES_IRQ | 7828 ETHTOOL_COALESCE_STATS_BLOCK_USECS, 7829 .get_drvinfo = bnx2_get_drvinfo, 7830 .get_regs_len = bnx2_get_regs_len, 7831 .get_regs = bnx2_get_regs, 7832 .get_wol = bnx2_get_wol, 7833 .set_wol = bnx2_set_wol, 7834 .nway_reset = bnx2_nway_reset, 7835 .get_link = bnx2_get_link, 7836 .get_eeprom_len = bnx2_get_eeprom_len, 7837 .get_eeprom = bnx2_get_eeprom, 7838 .set_eeprom = bnx2_set_eeprom, 7839 .get_coalesce = bnx2_get_coalesce, 7840 .set_coalesce = bnx2_set_coalesce, 7841 .get_ringparam = bnx2_get_ringparam, 7842 .set_ringparam = bnx2_set_ringparam, 7843 .get_pauseparam = bnx2_get_pauseparam, 7844 .set_pauseparam = bnx2_set_pauseparam, 7845 .self_test = bnx2_self_test, 7846 .get_strings = bnx2_get_strings, 7847 .set_phys_id = bnx2_set_phys_id, 7848 .get_ethtool_stats = bnx2_get_ethtool_stats, 7849 .get_sset_count = bnx2_get_sset_count, 7850 .get_channels = bnx2_get_channels, 7851 .set_channels = bnx2_set_channels, 7852 .get_link_ksettings = bnx2_get_link_ksettings, 7853 .set_link_ksettings = bnx2_set_link_ksettings, 7854 }; 7855 7856 /* Called with rtnl_lock */ 7857 static int 7858 bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 7859 { 7860 struct mii_ioctl_data *data = if_mii(ifr); 7861 struct bnx2 *bp = netdev_priv(dev); 7862 int err; 7863 7864 switch(cmd) { 7865 case SIOCGMIIPHY: 7866 data->phy_id = bp->phy_addr; 7867 7868 fallthrough; 7869 case SIOCGMIIREG: { 7870 u32 mii_regval; 7871 7872 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) 7873 return -EOPNOTSUPP; 7874 7875 if (!netif_running(dev)) 7876 return -EAGAIN; 7877 7878 spin_lock_bh(&bp->phy_lock); 7879 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval); 7880 spin_unlock_bh(&bp->phy_lock); 7881 7882 data->val_out = mii_regval; 7883 7884 return err; 7885 } 7886 7887 case SIOCSMIIREG: 7888 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) 7889 return -EOPNOTSUPP; 7890 7891 if (!netif_running(dev)) 7892 return -EAGAIN; 7893 7894 spin_lock_bh(&bp->phy_lock); 7895 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in); 7896 spin_unlock_bh(&bp->phy_lock); 7897 7898 return err; 7899 7900 default: 7901 /* do nothing */ 7902 break; 7903 } 7904 return -EOPNOTSUPP; 7905 } 7906 7907 /* Called with rtnl_lock */ 7908 static int 7909 bnx2_change_mac_addr(struct net_device *dev, void *p) 7910 { 7911 struct sockaddr *addr = p; 7912 struct bnx2 *bp = netdev_priv(dev); 7913 7914 if (!is_valid_ether_addr(addr->sa_data)) 7915 return -EADDRNOTAVAIL; 7916 7917 eth_hw_addr_set(dev, addr->sa_data); 7918 if (netif_running(dev)) 7919 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0); 7920 7921 return 0; 7922 } 7923 7924 /* Called with rtnl_lock */ 7925 static int 7926 bnx2_change_mtu(struct net_device *dev, int new_mtu) 7927 { 7928 struct bnx2 *bp = netdev_priv(dev); 7929 7930 WRITE_ONCE(dev->mtu, new_mtu); 7931 return bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size, 7932 false); 7933 } 7934 7935 #ifdef CONFIG_NET_POLL_CONTROLLER 7936 static void 7937 poll_bnx2(struct net_device *dev) 7938 { 7939 struct bnx2 *bp = netdev_priv(dev); 7940 int i; 7941 7942 for (i = 0; i < bp->irq_nvecs; i++) { 7943 struct bnx2_irq *irq = &bp->irq_tbl[i]; 7944 7945 disable_irq(irq->vector); 7946 irq->handler(irq->vector, &bp->bnx2_napi[i]); 7947 enable_irq(irq->vector); 7948 } 7949 } 7950 #endif 7951 7952 static void 7953 bnx2_get_5709_media(struct bnx2 *bp) 7954 { 7955 u32 val = BNX2_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL); 7956 u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID; 7957 u32 strap; 7958 7959 if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) 7960 return; 7961 else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) { 7962 bp->phy_flags |= BNX2_PHY_FLAG_SERDES; 7963 return; 7964 } 7965 7966 if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) 7967 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21; 7968 else 7969 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8; 7970 7971 if (bp->func == 0) { 7972 switch (strap) { 7973 case 0x4: 7974 case 0x5: 7975 case 0x6: 7976 bp->phy_flags |= BNX2_PHY_FLAG_SERDES; 7977 return; 7978 } 7979 } else { 7980 switch (strap) { 7981 case 0x1: 7982 case 0x2: 7983 case 0x4: 7984 bp->phy_flags |= BNX2_PHY_FLAG_SERDES; 7985 return; 7986 } 7987 } 7988 } 7989 7990 static void 7991 bnx2_get_pci_speed(struct bnx2 *bp) 7992 { 7993 u32 reg; 7994 7995 reg = BNX2_RD(bp, BNX2_PCICFG_MISC_STATUS); 7996 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) { 7997 u32 clkreg; 7998 7999 bp->flags |= BNX2_FLAG_PCIX; 8000 8001 clkreg = BNX2_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS); 8002 8003 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; 8004 switch (clkreg) { 8005 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: 8006 bp->bus_speed_mhz = 133; 8007 break; 8008 8009 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: 8010 bp->bus_speed_mhz = 100; 8011 break; 8012 8013 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: 8014 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: 8015 bp->bus_speed_mhz = 66; 8016 break; 8017 8018 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: 8019 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: 8020 bp->bus_speed_mhz = 50; 8021 break; 8022 8023 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: 8024 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: 8025 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: 8026 bp->bus_speed_mhz = 33; 8027 break; 8028 } 8029 } 8030 else { 8031 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN) 8032 bp->bus_speed_mhz = 66; 8033 else 8034 bp->bus_speed_mhz = 33; 8035 } 8036 8037 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET) 8038 bp->flags |= BNX2_FLAG_PCI_32BIT; 8039 8040 } 8041 8042 static void 8043 bnx2_read_vpd_fw_ver(struct bnx2 *bp) 8044 { 8045 unsigned int len; 8046 int rc, i, j; 8047 u8 *data; 8048 8049 #define BNX2_VPD_NVRAM_OFFSET 0x300 8050 #define BNX2_VPD_LEN 128 8051 #define BNX2_MAX_VER_SLEN 30 8052 8053 data = kmalloc(BNX2_VPD_LEN, GFP_KERNEL); 8054 if (!data) 8055 return; 8056 8057 rc = bnx2_nvram_read(bp, BNX2_VPD_NVRAM_OFFSET, data, BNX2_VPD_LEN); 8058 if (rc) 8059 goto vpd_done; 8060 8061 for (i = 0; i < BNX2_VPD_LEN; i += 4) 8062 swab32s((u32 *)&data[i]); 8063 8064 j = pci_vpd_find_ro_info_keyword(data, BNX2_VPD_LEN, 8065 PCI_VPD_RO_KEYWORD_MFR_ID, &len); 8066 if (j < 0) 8067 goto vpd_done; 8068 8069 if (len != 4 || memcmp(&data[j], "1028", 4)) 8070 goto vpd_done; 8071 8072 j = pci_vpd_find_ro_info_keyword(data, BNX2_VPD_LEN, 8073 PCI_VPD_RO_KEYWORD_VENDOR0, 8074 &len); 8075 if (j < 0) 8076 goto vpd_done; 8077 8078 if (len > BNX2_MAX_VER_SLEN) 8079 goto vpd_done; 8080 8081 memcpy(bp->fw_version, &data[j], len); 8082 bp->fw_version[len] = ' '; 8083 8084 vpd_done: 8085 kfree(data); 8086 } 8087 8088 static int 8089 bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) 8090 { 8091 struct bnx2 *bp; 8092 int rc, i, j; 8093 u32 reg; 8094 u64 dma_mask, persist_dma_mask; 8095 8096 SET_NETDEV_DEV(dev, &pdev->dev); 8097 bp = netdev_priv(dev); 8098 8099 bp->flags = 0; 8100 bp->phy_flags = 0; 8101 8102 bp->temp_stats_blk = 8103 kzalloc_obj(struct statistics_block); 8104 8105 if (!bp->temp_stats_blk) { 8106 rc = -ENOMEM; 8107 goto err_out; 8108 } 8109 8110 /* enable device (incl. PCI PM wakeup), and bus-mastering */ 8111 rc = pci_enable_device(pdev); 8112 if (rc) { 8113 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); 8114 goto err_out; 8115 } 8116 8117 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 8118 dev_err(&pdev->dev, 8119 "Cannot find PCI device base address, aborting\n"); 8120 rc = -ENODEV; 8121 goto err_out_disable; 8122 } 8123 8124 rc = pci_request_regions(pdev, DRV_MODULE_NAME); 8125 if (rc) { 8126 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); 8127 goto err_out_disable; 8128 } 8129 8130 pci_set_master(pdev); 8131 8132 bp->pm_cap = pdev->pm_cap; 8133 if (bp->pm_cap == 0) { 8134 dev_err(&pdev->dev, 8135 "Cannot find power management capability, aborting\n"); 8136 rc = -EIO; 8137 goto err_out_release; 8138 } 8139 8140 bp->dev = dev; 8141 bp->pdev = pdev; 8142 8143 spin_lock_init(&bp->phy_lock); 8144 spin_lock_init(&bp->indirect_lock); 8145 #ifdef BCM_CNIC 8146 mutex_init(&bp->cnic_lock); 8147 #endif 8148 INIT_WORK(&bp->reset_task, bnx2_reset_task); 8149 8150 bp->regview = pci_iomap(pdev, 0, MB_GET_CID_ADDR(TX_TSS_CID + 8151 TX_MAX_TSS_RINGS + 1)); 8152 if (!bp->regview) { 8153 dev_err(&pdev->dev, "Cannot map register space, aborting\n"); 8154 rc = -ENOMEM; 8155 goto err_out_release; 8156 } 8157 8158 /* Configure byte swap and enable write to the reg_window registers. 8159 * Rely on CPU to do target byte swapping on big endian systems 8160 * The chip's target access swapping will not swap all accesses 8161 */ 8162 BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG, 8163 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 8164 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP); 8165 8166 bp->chip_id = BNX2_RD(bp, BNX2_MISC_ID); 8167 8168 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { 8169 if (!pci_is_pcie(pdev)) { 8170 dev_err(&pdev->dev, "Not PCIE, aborting\n"); 8171 rc = -EIO; 8172 goto err_out_unmap; 8173 } 8174 bp->flags |= BNX2_FLAG_PCIE; 8175 if (BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Ax) 8176 bp->flags |= BNX2_FLAG_JUMBO_BROKEN; 8177 } else { 8178 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX); 8179 if (bp->pcix_cap == 0) { 8180 dev_err(&pdev->dev, 8181 "Cannot find PCIX capability, aborting\n"); 8182 rc = -EIO; 8183 goto err_out_unmap; 8184 } 8185 bp->flags |= BNX2_FLAG_BROKEN_STATS; 8186 } 8187 8188 if (BNX2_CHIP(bp) == BNX2_CHIP_5709 && 8189 BNX2_CHIP_REV(bp) != BNX2_CHIP_REV_Ax) { 8190 if (pdev->msix_cap) 8191 bp->flags |= BNX2_FLAG_MSIX_CAP; 8192 } 8193 8194 if (BNX2_CHIP_ID(bp) != BNX2_CHIP_ID_5706_A0 && 8195 BNX2_CHIP_ID(bp) != BNX2_CHIP_ID_5706_A1) { 8196 if (pdev->msi_cap) 8197 bp->flags |= BNX2_FLAG_MSI_CAP; 8198 } 8199 8200 /* 5708 cannot support DMA addresses > 40-bit. */ 8201 if (BNX2_CHIP(bp) == BNX2_CHIP_5708) 8202 persist_dma_mask = dma_mask = DMA_BIT_MASK(40); 8203 else 8204 persist_dma_mask = dma_mask = DMA_BIT_MASK(64); 8205 8206 /* Configure DMA attributes. */ 8207 if (dma_set_mask(&pdev->dev, dma_mask) == 0) { 8208 dev->features |= NETIF_F_HIGHDMA; 8209 rc = dma_set_coherent_mask(&pdev->dev, persist_dma_mask); 8210 if (rc) { 8211 dev_err(&pdev->dev, 8212 "dma_set_coherent_mask failed, aborting\n"); 8213 goto err_out_unmap; 8214 } 8215 } else if ((rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) != 0) { 8216 dev_err(&pdev->dev, "System does not support DMA, aborting\n"); 8217 goto err_out_unmap; 8218 } 8219 8220 if (!(bp->flags & BNX2_FLAG_PCIE)) 8221 bnx2_get_pci_speed(bp); 8222 8223 /* 5706A0 may falsely detect SERR and PERR. */ 8224 if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) { 8225 reg = BNX2_RD(bp, PCI_COMMAND); 8226 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY); 8227 BNX2_WR(bp, PCI_COMMAND, reg); 8228 } else if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1) && 8229 !(bp->flags & BNX2_FLAG_PCIX)) { 8230 dev_err(&pdev->dev, 8231 "5706 A1 can only be used in a PCIX bus, aborting\n"); 8232 rc = -EPERM; 8233 goto err_out_unmap; 8234 } 8235 8236 bnx2_init_nvram(bp); 8237 8238 reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE); 8239 8240 if (bnx2_reg_rd_ind(bp, BNX2_MCP_TOE_ID) & BNX2_MCP_TOE_ID_FUNCTION_ID) 8241 bp->func = 1; 8242 8243 if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) == 8244 BNX2_SHM_HDR_SIGNATURE_SIG) { 8245 u32 off = bp->func << 2; 8246 8247 bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off); 8248 } else 8249 bp->shmem_base = HOST_VIEW_SHMEM_BASE; 8250 8251 /* Get the permanent MAC address. First we need to make sure the 8252 * firmware is actually running. 8253 */ 8254 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE); 8255 8256 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) != 8257 BNX2_DEV_INFO_SIGNATURE_MAGIC) { 8258 dev_err(&pdev->dev, "Firmware not running, aborting\n"); 8259 rc = -ENODEV; 8260 goto err_out_unmap; 8261 } 8262 8263 bnx2_read_vpd_fw_ver(bp); 8264 8265 j = strlen(bp->fw_version); 8266 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV); 8267 for (i = 0; i < 3 && j < 24; i++) { 8268 u8 num, k, skip0; 8269 8270 if (i == 0) { 8271 bp->fw_version[j++] = 'b'; 8272 bp->fw_version[j++] = 'c'; 8273 bp->fw_version[j++] = ' '; 8274 } 8275 num = (u8) (reg >> (24 - (i * 8))); 8276 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) { 8277 if (num >= k || !skip0 || k == 1) { 8278 bp->fw_version[j++] = (num / k) + '0'; 8279 skip0 = 0; 8280 } 8281 } 8282 if (i != 2) 8283 bp->fw_version[j++] = '.'; 8284 } 8285 reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE); 8286 if (reg & BNX2_PORT_FEATURE_WOL_ENABLED) 8287 bp->wol = 1; 8288 8289 if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) { 8290 bp->flags |= BNX2_FLAG_ASF_ENABLE; 8291 8292 for (i = 0; i < 30; i++) { 8293 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION); 8294 if (reg & BNX2_CONDITION_MFW_RUN_MASK) 8295 break; 8296 msleep(10); 8297 } 8298 } 8299 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION); 8300 reg &= BNX2_CONDITION_MFW_RUN_MASK; 8301 if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN && 8302 reg != BNX2_CONDITION_MFW_RUN_NONE) { 8303 u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR); 8304 8305 if (j < 32) 8306 bp->fw_version[j++] = ' '; 8307 for (i = 0; i < 3 && j < 28; i++) { 8308 reg = bnx2_reg_rd_ind(bp, addr + i * 4); 8309 reg = be32_to_cpu(reg); 8310 memcpy(&bp->fw_version[j], ®, 4); 8311 j += 4; 8312 } 8313 } 8314 8315 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER); 8316 bp->mac_addr[0] = (u8) (reg >> 8); 8317 bp->mac_addr[1] = (u8) reg; 8318 8319 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER); 8320 bp->mac_addr[2] = (u8) (reg >> 24); 8321 bp->mac_addr[3] = (u8) (reg >> 16); 8322 bp->mac_addr[4] = (u8) (reg >> 8); 8323 bp->mac_addr[5] = (u8) reg; 8324 8325 bp->tx_ring_size = BNX2_MAX_TX_DESC_CNT; 8326 bnx2_set_rx_ring_size(bp, 255); 8327 8328 bp->tx_quick_cons_trip_int = 2; 8329 bp->tx_quick_cons_trip = 20; 8330 bp->tx_ticks_int = 18; 8331 bp->tx_ticks = 80; 8332 8333 bp->rx_quick_cons_trip_int = 2; 8334 bp->rx_quick_cons_trip = 12; 8335 bp->rx_ticks_int = 18; 8336 bp->rx_ticks = 18; 8337 8338 bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS; 8339 8340 bp->current_interval = BNX2_TIMER_INTERVAL; 8341 8342 bp->phy_addr = 1; 8343 8344 /* allocate stats_blk */ 8345 rc = bnx2_alloc_stats_blk(dev); 8346 if (rc) 8347 goto err_out_unmap; 8348 8349 /* Disable WOL support if we are running on a SERDES chip. */ 8350 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) 8351 bnx2_get_5709_media(bp); 8352 else if (BNX2_CHIP_BOND(bp) & BNX2_CHIP_BOND_SERDES_BIT) 8353 bp->phy_flags |= BNX2_PHY_FLAG_SERDES; 8354 8355 bp->phy_port = PORT_TP; 8356 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { 8357 bp->phy_port = PORT_FIBRE; 8358 reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG); 8359 if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) { 8360 bp->flags |= BNX2_FLAG_NO_WOL; 8361 bp->wol = 0; 8362 } 8363 if (BNX2_CHIP(bp) == BNX2_CHIP_5706) { 8364 /* Don't do parallel detect on this board because of 8365 * some board problems. The link will not go down 8366 * if we do parallel detect. 8367 */ 8368 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP && 8369 pdev->subsystem_device == 0x310c) 8370 bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL; 8371 } else { 8372 bp->phy_addr = 2; 8373 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G) 8374 bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE; 8375 } 8376 } else if (BNX2_CHIP(bp) == BNX2_CHIP_5706 || 8377 BNX2_CHIP(bp) == BNX2_CHIP_5708) 8378 bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX; 8379 else if (BNX2_CHIP(bp) == BNX2_CHIP_5709 && 8380 (BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Ax || 8381 BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Bx)) 8382 bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC; 8383 8384 bnx2_init_fw_cap(bp); 8385 8386 if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0) || 8387 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B0) || 8388 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B1) || 8389 !(BNX2_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) { 8390 bp->flags |= BNX2_FLAG_NO_WOL; 8391 bp->wol = 0; 8392 } 8393 8394 if (bp->flags & BNX2_FLAG_NO_WOL) 8395 device_set_wakeup_capable(&bp->pdev->dev, false); 8396 else 8397 device_set_wakeup_enable(&bp->pdev->dev, bp->wol); 8398 8399 if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) { 8400 bp->tx_quick_cons_trip_int = 8401 bp->tx_quick_cons_trip; 8402 bp->tx_ticks_int = bp->tx_ticks; 8403 bp->rx_quick_cons_trip_int = 8404 bp->rx_quick_cons_trip; 8405 bp->rx_ticks_int = bp->rx_ticks; 8406 bp->comp_prod_trip_int = bp->comp_prod_trip; 8407 bp->com_ticks_int = bp->com_ticks; 8408 bp->cmd_ticks_int = bp->cmd_ticks; 8409 } 8410 8411 /* Disable MSI on 5706 if AMD 8132 bridge is found. 8412 * 8413 * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes 8414 * with byte enables disabled on the unused 32-bit word. This is legal 8415 * but causes problems on the AMD 8132 which will eventually stop 8416 * responding after a while. 8417 * 8418 * AMD believes this incompatibility is unique to the 5706, and 8419 * prefers to locally disable MSI rather than globally disabling it. 8420 */ 8421 if (BNX2_CHIP(bp) == BNX2_CHIP_5706 && disable_msi == 0) { 8422 struct pci_dev *amd_8132 = NULL; 8423 8424 while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD, 8425 PCI_DEVICE_ID_AMD_8132_BRIDGE, 8426 amd_8132))) { 8427 8428 if (amd_8132->revision >= 0x10 && 8429 amd_8132->revision <= 0x13) { 8430 disable_msi = 1; 8431 pci_dev_put(amd_8132); 8432 break; 8433 } 8434 } 8435 } 8436 8437 bnx2_set_default_link(bp); 8438 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX; 8439 8440 timer_setup(&bp->timer, bnx2_timer, 0); 8441 bp->timer.expires = RUN_AT(BNX2_TIMER_INTERVAL); 8442 8443 #ifdef BCM_CNIC 8444 if (bnx2_shmem_rd(bp, BNX2_ISCSI_INITIATOR) & BNX2_ISCSI_INITIATOR_EN) 8445 bp->cnic_eth_dev.max_iscsi_conn = 8446 (bnx2_shmem_rd(bp, BNX2_ISCSI_MAX_CONN) & 8447 BNX2_ISCSI_MAX_CONN_MASK) >> BNX2_ISCSI_MAX_CONN_SHIFT; 8448 bp->cnic_probe = bnx2_cnic_probe; 8449 #endif 8450 pci_save_state(pdev); 8451 8452 return 0; 8453 8454 err_out_unmap: 8455 pci_iounmap(pdev, bp->regview); 8456 bp->regview = NULL; 8457 8458 err_out_release: 8459 pci_release_regions(pdev); 8460 8461 err_out_disable: 8462 pci_disable_device(pdev); 8463 8464 err_out: 8465 kfree(bp->temp_stats_blk); 8466 8467 return rc; 8468 } 8469 8470 static char * 8471 bnx2_bus_string(struct bnx2 *bp, char *str) 8472 { 8473 char *s = str; 8474 8475 if (bp->flags & BNX2_FLAG_PCIE) { 8476 s += sprintf(s, "PCI Express"); 8477 } else { 8478 s += sprintf(s, "PCI"); 8479 if (bp->flags & BNX2_FLAG_PCIX) 8480 s += sprintf(s, "-X"); 8481 if (bp->flags & BNX2_FLAG_PCI_32BIT) 8482 s += sprintf(s, " 32-bit"); 8483 else 8484 s += sprintf(s, " 64-bit"); 8485 s += sprintf(s, " %dMHz", bp->bus_speed_mhz); 8486 } 8487 return str; 8488 } 8489 8490 static void 8491 bnx2_del_napi(struct bnx2 *bp) 8492 { 8493 int i; 8494 8495 for (i = 0; i < bp->irq_nvecs; i++) 8496 netif_napi_del(&bp->bnx2_napi[i].napi); 8497 } 8498 8499 static void 8500 bnx2_init_napi(struct bnx2 *bp) 8501 { 8502 int i; 8503 8504 for (i = 0; i < bp->irq_nvecs; i++) { 8505 struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; 8506 int (*poll)(struct napi_struct *, int); 8507 8508 if (i == 0) 8509 poll = bnx2_poll; 8510 else 8511 poll = bnx2_poll_msix; 8512 8513 netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll); 8514 bnapi->bp = bp; 8515 } 8516 } 8517 8518 static const struct net_device_ops bnx2_netdev_ops = { 8519 .ndo_open = bnx2_open, 8520 .ndo_start_xmit = bnx2_start_xmit, 8521 .ndo_stop = bnx2_close, 8522 .ndo_get_stats64 = bnx2_get_stats64, 8523 .ndo_set_rx_mode = bnx2_set_rx_mode, 8524 .ndo_eth_ioctl = bnx2_ioctl, 8525 .ndo_validate_addr = eth_validate_addr, 8526 .ndo_set_mac_address = bnx2_change_mac_addr, 8527 .ndo_change_mtu = bnx2_change_mtu, 8528 .ndo_set_features = bnx2_set_features, 8529 .ndo_tx_timeout = bnx2_tx_timeout, 8530 #ifdef CONFIG_NET_POLL_CONTROLLER 8531 .ndo_poll_controller = poll_bnx2, 8532 #endif 8533 }; 8534 8535 static int 8536 bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 8537 { 8538 struct net_device *dev; 8539 struct bnx2 *bp; 8540 int rc; 8541 char str[40]; 8542 8543 /* dev zeroed in init_etherdev */ 8544 dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS); 8545 if (!dev) 8546 return -ENOMEM; 8547 8548 rc = bnx2_init_board(pdev, dev); 8549 if (rc < 0) 8550 goto err_free; 8551 8552 dev->netdev_ops = &bnx2_netdev_ops; 8553 dev->watchdog_timeo = TX_TIMEOUT; 8554 dev->ethtool_ops = &bnx2_ethtool_ops; 8555 8556 bp = netdev_priv(dev); 8557 8558 pci_set_drvdata(pdev, dev); 8559 8560 /* 8561 * In-flight DMA from 1st kernel could continue going in kdump kernel. 8562 * New io-page table has been created before bnx2 does reset at open stage. 8563 * We have to wait for the in-flight DMA to complete to avoid it look up 8564 * into the newly created io-page table. 8565 */ 8566 if (is_kdump_kernel()) 8567 bnx2_wait_dma_complete(bp); 8568 8569 eth_hw_addr_set(dev, bp->mac_addr); 8570 8571 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG | 8572 NETIF_F_TSO | NETIF_F_TSO_ECN | 8573 NETIF_F_RXHASH | NETIF_F_RXCSUM; 8574 8575 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) 8576 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6; 8577 8578 dev->vlan_features = dev->hw_features; 8579 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; 8580 dev->features |= dev->hw_features; 8581 dev->priv_flags |= IFF_UNICAST_FLT; 8582 dev->min_mtu = MIN_ETHERNET_PACKET_SIZE; 8583 dev->max_mtu = MAX_ETHERNET_JUMBO_PACKET_SIZE; 8584 8585 if (!(bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)) 8586 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; 8587 8588 if ((rc = register_netdev(dev))) { 8589 dev_err(&pdev->dev, "Cannot register net device\n"); 8590 goto error; 8591 } 8592 8593 netdev_info(dev, "%s (%c%d) %s found at mem %lx, IRQ %d, " 8594 "node addr %pM\n", board_info[ent->driver_data].name, 8595 ((BNX2_CHIP_ID(bp) & 0xf000) >> 12) + 'A', 8596 ((BNX2_CHIP_ID(bp) & 0x0ff0) >> 4), 8597 bnx2_bus_string(bp, str), (long)pci_resource_start(pdev, 0), 8598 pdev->irq, dev->dev_addr); 8599 8600 return 0; 8601 8602 error: 8603 pci_iounmap(pdev, bp->regview); 8604 pci_release_regions(pdev); 8605 pci_disable_device(pdev); 8606 err_free: 8607 bnx2_free_stats_blk(dev); 8608 free_netdev(dev); 8609 return rc; 8610 } 8611 8612 static void 8613 bnx2_remove_one(struct pci_dev *pdev) 8614 { 8615 struct net_device *dev = pci_get_drvdata(pdev); 8616 struct bnx2 *bp = netdev_priv(dev); 8617 8618 unregister_netdev(dev); 8619 8620 timer_delete_sync(&bp->timer); 8621 cancel_work_sync(&bp->reset_task); 8622 8623 pci_iounmap(bp->pdev, bp->regview); 8624 8625 bnx2_free_stats_blk(dev); 8626 kfree(bp->temp_stats_blk); 8627 8628 bnx2_release_firmware(bp); 8629 8630 free_netdev(dev); 8631 8632 pci_release_regions(pdev); 8633 pci_disable_device(pdev); 8634 } 8635 8636 #ifdef CONFIG_PM_SLEEP 8637 static int 8638 bnx2_suspend(struct device *device) 8639 { 8640 struct net_device *dev = dev_get_drvdata(device); 8641 struct bnx2 *bp = netdev_priv(dev); 8642 8643 if (netif_running(dev)) { 8644 cancel_work_sync(&bp->reset_task); 8645 bnx2_netif_stop(bp, true); 8646 netif_device_detach(dev); 8647 timer_delete_sync(&bp->timer); 8648 bnx2_shutdown_chip(bp); 8649 __bnx2_free_irq(bp); 8650 bnx2_free_skbs(bp); 8651 } 8652 bnx2_setup_wol(bp); 8653 return 0; 8654 } 8655 8656 static int 8657 bnx2_resume(struct device *device) 8658 { 8659 struct net_device *dev = dev_get_drvdata(device); 8660 struct bnx2 *bp = netdev_priv(dev); 8661 8662 if (!netif_running(dev)) 8663 return 0; 8664 8665 bnx2_set_power_state(bp, PCI_D0); 8666 netif_device_attach(dev); 8667 bnx2_request_irq(bp); 8668 bnx2_init_nic(bp, 1); 8669 bnx2_netif_start(bp, true); 8670 return 0; 8671 } 8672 8673 static SIMPLE_DEV_PM_OPS(bnx2_pm_ops, bnx2_suspend, bnx2_resume); 8674 #define BNX2_PM_OPS (&bnx2_pm_ops) 8675 8676 #else 8677 8678 #define BNX2_PM_OPS NULL 8679 8680 #endif /* CONFIG_PM_SLEEP */ 8681 /** 8682 * bnx2_io_error_detected - called when PCI error is detected 8683 * @pdev: Pointer to PCI device 8684 * @state: The current pci connection state 8685 * 8686 * This function is called after a PCI bus error affecting 8687 * this device has been detected. 8688 */ 8689 static pci_ers_result_t bnx2_io_error_detected(struct pci_dev *pdev, 8690 pci_channel_state_t state) 8691 { 8692 struct net_device *dev = pci_get_drvdata(pdev); 8693 struct bnx2 *bp = netdev_priv(dev); 8694 8695 rtnl_lock(); 8696 netif_device_detach(dev); 8697 8698 if (state == pci_channel_io_perm_failure) { 8699 rtnl_unlock(); 8700 return PCI_ERS_RESULT_DISCONNECT; 8701 } 8702 8703 if (netif_running(dev)) { 8704 bnx2_netif_stop(bp, true); 8705 timer_delete_sync(&bp->timer); 8706 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET); 8707 } 8708 8709 pci_disable_device(pdev); 8710 rtnl_unlock(); 8711 8712 /* Request a slot slot reset. */ 8713 return PCI_ERS_RESULT_NEED_RESET; 8714 } 8715 8716 /** 8717 * bnx2_io_slot_reset - called after the pci bus has been reset. 8718 * @pdev: Pointer to PCI device 8719 * 8720 * Restart the card from scratch, as if from a cold-boot. 8721 */ 8722 static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev) 8723 { 8724 struct net_device *dev = pci_get_drvdata(pdev); 8725 struct bnx2 *bp = netdev_priv(dev); 8726 pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT; 8727 int err = 0; 8728 8729 rtnl_lock(); 8730 if (pci_enable_device(pdev)) { 8731 dev_err(&pdev->dev, 8732 "Cannot re-enable PCI device after reset\n"); 8733 } else { 8734 pci_set_master(pdev); 8735 pci_restore_state(pdev); 8736 8737 if (netif_running(dev)) 8738 err = bnx2_init_nic(bp, 1); 8739 8740 if (!err) 8741 result = PCI_ERS_RESULT_RECOVERED; 8742 } 8743 8744 if (result != PCI_ERS_RESULT_RECOVERED && netif_running(dev)) { 8745 bnx2_napi_enable(bp); 8746 dev_close(dev); 8747 } 8748 rtnl_unlock(); 8749 8750 return result; 8751 } 8752 8753 /** 8754 * bnx2_io_resume - called when traffic can start flowing again. 8755 * @pdev: Pointer to PCI device 8756 * 8757 * This callback is called when the error recovery driver tells us that 8758 * its OK to resume normal operation. 8759 */ 8760 static void bnx2_io_resume(struct pci_dev *pdev) 8761 { 8762 struct net_device *dev = pci_get_drvdata(pdev); 8763 struct bnx2 *bp = netdev_priv(dev); 8764 8765 rtnl_lock(); 8766 if (netif_running(dev)) 8767 bnx2_netif_start(bp, true); 8768 8769 netif_device_attach(dev); 8770 rtnl_unlock(); 8771 } 8772 8773 static void bnx2_shutdown(struct pci_dev *pdev) 8774 { 8775 struct net_device *dev = pci_get_drvdata(pdev); 8776 struct bnx2 *bp; 8777 8778 if (!dev) 8779 return; 8780 8781 bp = netdev_priv(dev); 8782 if (!bp) 8783 return; 8784 8785 rtnl_lock(); 8786 if (netif_running(dev)) 8787 dev_close(bp->dev); 8788 8789 if (system_state == SYSTEM_POWER_OFF) 8790 bnx2_set_power_state(bp, PCI_D3hot); 8791 8792 rtnl_unlock(); 8793 } 8794 8795 static const struct pci_error_handlers bnx2_err_handler = { 8796 .error_detected = bnx2_io_error_detected, 8797 .slot_reset = bnx2_io_slot_reset, 8798 .resume = bnx2_io_resume, 8799 }; 8800 8801 static struct pci_driver bnx2_pci_driver = { 8802 .name = DRV_MODULE_NAME, 8803 .id_table = bnx2_pci_tbl, 8804 .probe = bnx2_init_one, 8805 .remove = bnx2_remove_one, 8806 .driver.pm = BNX2_PM_OPS, 8807 .err_handler = &bnx2_err_handler, 8808 .shutdown = bnx2_shutdown, 8809 }; 8810 8811 module_pci_driver(bnx2_pci_driver); 8812