1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2025 Broadcom */ 3 4 #ifndef _BNGE_NETDEV_H_ 5 #define _BNGE_NETDEV_H_ 6 7 #include <linux/bnge/hsi.h> 8 #include <linux/io-64-nonatomic-lo-hi.h> 9 #include <linux/refcount.h> 10 #include <linux/u64_stats_sync.h> 11 #include <net/netdev_queues.h> 12 #include "bnge_db.h" 13 #include "bnge_hw_def.h" 14 #include "bnge_link.h" 15 16 struct tx_bd { 17 __le32 tx_bd_len_flags_type; 18 #define TX_BD_TYPE (0x3f << 0) 19 #define TX_BD_TYPE_SHORT_TX_BD (0x00 << 0) 20 #define TX_BD_TYPE_LONG_TX_BD (0x10 << 0) 21 #define TX_BD_FLAGS_PACKET_END (1 << 6) 22 #define TX_BD_FLAGS_NO_CMPL (1 << 7) 23 #define TX_BD_FLAGS_BD_CNT (0x1f << 8) 24 #define TX_BD_FLAGS_BD_CNT_SHIFT 8 25 #define TX_BD_FLAGS_LHINT (3 << 13) 26 #define TX_BD_FLAGS_LHINT_SHIFT 13 27 #define TX_BD_FLAGS_LHINT_512_AND_SMALLER (0 << 13) 28 #define TX_BD_FLAGS_LHINT_512_TO_1023 (1 << 13) 29 #define TX_BD_FLAGS_LHINT_1024_TO_2047 (2 << 13) 30 #define TX_BD_FLAGS_LHINT_2048_AND_LARGER (3 << 13) 31 #define TX_BD_FLAGS_COAL_NOW (1 << 15) 32 #define TX_BD_LEN (0xffff << 16) 33 #define TX_BD_LEN_SHIFT 16 34 u32 tx_bd_opaque; 35 __le64 tx_bd_haddr; 36 } __packed; 37 38 struct rx_bd { 39 __le32 rx_bd_len_flags_type; 40 #define RX_BD_TYPE (0x3f << 0) 41 #define RX_BD_TYPE_RX_PACKET_BD 0x4 42 #define RX_BD_TYPE_RX_BUFFER_BD 0x5 43 #define RX_BD_TYPE_RX_AGG_BD 0x6 44 #define RX_BD_TYPE_16B_BD_SIZE (0 << 4) 45 #define RX_BD_TYPE_32B_BD_SIZE (1 << 4) 46 #define RX_BD_TYPE_48B_BD_SIZE (2 << 4) 47 #define RX_BD_TYPE_64B_BD_SIZE (3 << 4) 48 #define RX_BD_FLAGS_SOP (1 << 6) 49 #define RX_BD_FLAGS_EOP (1 << 7) 50 #define RX_BD_FLAGS_BUFFERS (3 << 8) 51 #define RX_BD_FLAGS_1_BUFFER_PACKET (0 << 8) 52 #define RX_BD_FLAGS_2_BUFFER_PACKET (1 << 8) 53 #define RX_BD_FLAGS_3_BUFFER_PACKET (2 << 8) 54 #define RX_BD_FLAGS_4_BUFFER_PACKET (3 << 8) 55 #define RX_BD_LEN (0xffff << 16) 56 #define RX_BD_LEN_SHIFT 16 57 u32 rx_bd_opaque; 58 __le64 rx_bd_haddr; 59 }; 60 61 struct tx_cmp { 62 __le32 tx_cmp_flags_type; 63 #define CMP_TYPE (0x3f << 0) 64 #define CMP_TYPE_TX_L2_CMP 0 65 #define CMP_TYPE_TX_L2_COAL_CMP 2 66 #define CMP_TYPE_TX_L2_PKT_TS_CMP 4 67 #define CMP_TYPE_RX_L2_CMP 17 68 #define CMP_TYPE_RX_AGG_CMP 18 69 #define CMP_TYPE_RX_L2_TPA_START_CMP 19 70 #define CMP_TYPE_RX_L2_TPA_END_CMP 21 71 #define CMP_TYPE_RX_TPA_AGG_CMP 22 72 #define CMP_TYPE_RX_L2_V3_CMP 23 73 #define CMP_TYPE_RX_L2_TPA_START_V3_CMP 25 74 #define CMP_TYPE_STATUS_CMP 32 75 #define CMP_TYPE_REMOTE_DRIVER_REQ 34 76 #define CMP_TYPE_REMOTE_DRIVER_RESP 36 77 #define CMP_TYPE_ERROR_STATUS 48 78 #define CMPL_BASE_TYPE_STAT_EJECT 0x1aUL 79 #define CMPL_BASE_TYPE_HWRM_DONE 0x20UL 80 #define CMPL_BASE_TYPE_HWRM_FWD_REQ 0x22UL 81 #define CMPL_BASE_TYPE_HWRM_FWD_RESP 0x24UL 82 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 83 #define CMPL_BA_TY_HWRM_ASY_EVT CMPL_BASE_TYPE_HWRM_ASYNC_EVENT 84 #define TX_CMP_FLAGS_ERROR (1 << 6) 85 #define TX_CMP_FLAGS_PUSH (1 << 7) 86 u32 tx_cmp_opaque; 87 __le32 tx_cmp_errors_v; 88 #define TX_CMP_V (1 << 0) 89 #define TX_CMP_ERRORS_BUFFER_ERROR (7 << 1) 90 #define TX_CMP_ERRORS_BUFFER_ERROR_NO_ERROR 0 91 #define TX_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT 2 92 #define TX_CMP_ERRORS_BUFFER_ERROR_INVALID_STAG 4 93 #define TX_CMP_ERRORS_BUFFER_ERROR_STAG_BOUNDS 5 94 #define TX_CMP_ERRORS_ZERO_LENGTH_PKT (1 << 4) 95 #define TX_CMP_ERRORS_EXCESSIVE_BD_LEN (1 << 5) 96 #define TX_CMP_ERRORS_DMA_ERROR (1 << 6) 97 #define TX_CMP_ERRORS_HINT_TOO_SHORT (1 << 7) 98 __le32 sq_cons_idx; 99 #define TX_CMP_SQ_CONS_IDX_MASK 0x00ffffff 100 }; 101 102 struct bnge_sw_tx_bd { 103 struct sk_buff *skb; 104 DEFINE_DMA_UNMAP_ADDR(mapping); 105 DEFINE_DMA_UNMAP_LEN(len); 106 struct page *page; 107 u8 is_ts_pkt; 108 u8 is_push; 109 u8 action; 110 unsigned short nr_frags; 111 union { 112 u16 rx_prod; 113 u16 txts_prod; 114 }; 115 }; 116 117 struct bnge_sw_rx_bd { 118 void *data; 119 u8 *data_ptr; 120 dma_addr_t mapping; 121 }; 122 123 struct bnge_sw_rx_agg_bd { 124 netmem_ref netmem; 125 unsigned int offset; 126 dma_addr_t mapping; 127 }; 128 129 #define HWRM_RING_ALLOC_TX 0x1 130 #define HWRM_RING_ALLOC_RX 0x2 131 #define HWRM_RING_ALLOC_AGG 0x4 132 #define HWRM_RING_ALLOC_CMPL 0x8 133 #define HWRM_RING_ALLOC_NQ 0x10 134 135 struct bnge_ring_grp_info { 136 u16 fw_stats_ctx; 137 u16 fw_grp_id; 138 u16 rx_fw_ring_id; 139 u16 agg_fw_ring_id; 140 u16 nq_fw_ring_id; 141 }; 142 143 #define BNGE_DEFAULT_RX_COPYBREAK 256 144 #define BNGE_MAX_RX_COPYBREAK 1024 145 146 #define BNGE_HW_FEATURE_VLAN_ALL_RX \ 147 (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX) 148 #define BNGE_HW_FEATURE_VLAN_ALL_TX \ 149 (NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_STAG_TX) 150 151 enum { 152 BNGE_NET_EN_GRO = BIT(0), 153 BNGE_NET_EN_LRO = BIT(1), 154 BNGE_NET_EN_JUMBO = BIT(2), 155 }; 156 157 #define BNGE_NET_EN_TPA (BNGE_NET_EN_GRO | BNGE_NET_EN_LRO) 158 159 #define BNGE_NO_FW_ACCESS(bd) (pci_channel_offline((bd)->pdev)) 160 161 #define MAX_TPA 256 162 #define MAX_TPA_MASK (MAX_TPA - 1) 163 #define MAX_TPA_SEGS 0x3f 164 165 #define BNGE_TPA_INNER_L3_OFF(hdr_info) \ 166 (((hdr_info) >> 18) & 0x1ff) 167 168 #define BNGE_TPA_INNER_L2_OFF(hdr_info) \ 169 (((hdr_info) >> 9) & 0x1ff) 170 171 #define BNGE_TPA_OUTER_L3_OFF(hdr_info) \ 172 ((hdr_info) & 0x1ff) 173 174 struct bnge_tpa_idx_map { 175 u16 agg_id_tbl[1024]; 176 DECLARE_BITMAP(agg_idx_bmap, MAX_TPA); 177 }; 178 179 struct bnge_tpa_info { 180 void *data; 181 u8 *data_ptr; 182 dma_addr_t mapping; 183 u16 len; 184 unsigned short gso_type; 185 u32 flags2; 186 u32 metadata; 187 enum pkt_hash_types hash_type; 188 u32 rss_hash; 189 u32 hdr_info; 190 191 u16 cfa_code; /* cfa_code in TPA start compl */ 192 u8 agg_count; 193 bool vlan_valid; 194 bool cfa_code_valid; 195 struct rx_agg_cmp *agg_arr; 196 }; 197 198 /* Minimum TX BDs for a TX packet with MAX_SKB_FRAGS + 1. We need one extra 199 * BD because the first TX BD is always a long BD. 200 */ 201 #define BNGE_MIN_TX_DESC_CNT (MAX_SKB_FRAGS + 2) 202 203 #define RX_RING(bn, x) (((x) & (bn)->rx_ring_mask) >> (BNGE_PAGE_SHIFT - 4)) 204 #define RX_AGG_RING(bn, x) (((x) & (bn)->rx_agg_ring_mask) >> \ 205 (BNGE_PAGE_SHIFT - 4)) 206 #define RX_IDX(x) ((x) & (RX_DESC_CNT - 1)) 207 208 #define TX_RING(bn, x) (((x) & (bn)->tx_ring_mask) >> (BNGE_PAGE_SHIFT - 4)) 209 #define TX_IDX(x) ((x) & (TX_DESC_CNT - 1)) 210 211 #define CP_RING(x) (((x) & ~(CP_DESC_CNT - 1)) >> (BNGE_PAGE_SHIFT - 4)) 212 #define CP_IDX(x) ((x) & (CP_DESC_CNT - 1)) 213 214 #define RING_RX(bn, idx) ((idx) & (bn)->rx_ring_mask) 215 #define NEXT_RX(idx) ((idx) + 1) 216 217 #define RING_RX_AGG(bn, idx) ((idx) & (bn)->rx_agg_ring_mask) 218 #define NEXT_RX_AGG(idx) ((idx) + 1) 219 220 #define BNGE_NQ_HDL_IDX_MASK 0x00ffffff 221 #define BNGE_NQ_HDL_TYPE_MASK 0xff000000 222 #define BNGE_NQ_HDL_TYPE_SHIFT 24 223 #define BNGE_NQ_HDL_TYPE_RX 0x00 224 #define BNGE_NQ_HDL_TYPE_TX 0x01 225 226 #define BNGE_NQ_HDL_IDX(hdl) ((hdl) & BNGE_NQ_HDL_IDX_MASK) 227 #define BNGE_NQ_HDL_TYPE(hdl) (((hdl) & BNGE_NQ_HDL_TYPE_MASK) >> \ 228 BNGE_NQ_HDL_TYPE_SHIFT) 229 #define BNGE_GET_RING_STATS64(sw, counter) \ 230 (*((sw) + offsetof(struct ctx_hw_stats, counter) / 8)) 231 232 #define BNGE_GET_RX_PORT_STATS64(sw, counter) \ 233 (*((sw) + offsetof(struct rx_port_stats, counter) / 8)) 234 235 #define BNGE_GET_TX_PORT_STATS64(sw, counter) \ 236 (*((sw) + offsetof(struct tx_port_stats, counter) / 8)) 237 238 #define BNGE_PORT_STATS_SIZE \ 239 (sizeof(struct rx_port_stats) + sizeof(struct tx_port_stats) + 1024) 240 241 #define BNGE_TX_PORT_STATS_BYTE_OFFSET \ 242 (sizeof(struct rx_port_stats) + 512) 243 244 #define BNGE_RX_STATS_OFFSET(counter) \ 245 (offsetof(struct rx_port_stats, counter) / 8) 246 247 #define BNGE_TX_STATS_OFFSET(counter) \ 248 ((offsetof(struct tx_port_stats, counter) + \ 249 BNGE_TX_PORT_STATS_BYTE_OFFSET) / 8) 250 251 #define BNGE_RX_STATS_EXT_OFFSET(counter) \ 252 (offsetof(struct rx_port_stats_ext, counter) / 8) 253 254 #define BNGE_TX_STATS_EXT_OFFSET(counter) \ 255 (offsetof(struct tx_port_stats_ext, counter) / 8) 256 257 struct bnge_stats_mem { 258 u64 *sw_stats; 259 u64 *hw_masks; 260 void *hw_stats; 261 dma_addr_t hw_stats_map; 262 u32 len; 263 struct u64_stats_sync syncp; 264 }; 265 266 enum bnge_net_state { 267 BNGE_STATE_NAPI_DISABLED, 268 BNGE_STATE_STATS_ENABLE, 269 }; 270 271 #define BNGE_TIMER_INTERVAL HZ 272 273 enum bnge_net_flag { 274 BNGE_FLAG_PORT_STATS = BIT(0), 275 BNGE_FLAG_PORT_STATS_EXT = BIT(1), 276 }; 277 278 enum bnge_sp_event { 279 BNGE_LINK_CHNG_SP_EVENT, 280 BNGE_LINK_SPEED_CHNG_SP_EVENT, 281 BNGE_LINK_CFG_CHANGE_SP_EVENT, 282 BNGE_UPDATE_PHY_SP_EVENT, 283 BNGE_PERIODIC_STATS_SP_EVENT, 284 }; 285 286 struct bnge_net { 287 struct bnge_dev *bd; 288 struct net_device *netdev; 289 290 u32 priv_flags; 291 292 u32 rx_ring_size; 293 u32 rx_buf_size; 294 u32 rx_buf_use_size; /* usable size */ 295 u32 rx_agg_ring_size; 296 u32 rx_copybreak; 297 u32 rx_ring_mask; 298 u32 rx_agg_ring_mask; 299 u16 rx_nr_pages; 300 u16 rx_agg_nr_pages; 301 302 u32 tx_ring_size; 303 u32 tx_ring_mask; 304 u16 tx_nr_pages; 305 306 /* NQs and Completion rings */ 307 u32 cp_ring_size; 308 u32 cp_ring_mask; 309 u32 cp_bit; 310 u16 cp_nr_pages; 311 312 #define BNGE_L2_FLTR_HASH_SIZE 32 313 #define BNGE_L2_FLTR_HASH_MASK (BNGE_L2_FLTR_HASH_SIZE - 1) 314 struct hlist_head l2_fltr_hash_tbl[BNGE_L2_FLTR_HASH_SIZE]; 315 u32 hash_seed; 316 u64 toeplitz_prefix; 317 318 struct bnge_napi **bnapi; 319 320 struct bnge_rx_ring_info *rx_ring; 321 struct bnge_tx_ring_info *tx_ring; 322 323 u16 *tx_ring_map; 324 enum dma_data_direction rx_dir; 325 326 /* grp_info indexed by napi/nq index */ 327 struct bnge_ring_grp_info *grp_info; 328 struct bnge_vnic_info *vnic_info; 329 int nr_vnics; 330 int total_irqs; 331 332 u32 tx_wake_thresh; 333 u16 rx_offset; 334 u16 rx_dma_offset; 335 336 u8 rss_hash_key[HW_HASH_KEY_SIZE]; 337 u8 rss_hash_key_valid:1; 338 u8 rss_hash_key_updated:1; 339 int rsscos_nr_ctxs; 340 u32 stats_coal_ticks; 341 342 unsigned long state; 343 344 u32 msg_enable; 345 u16 max_tpa; 346 __be16 vxlan_port; 347 __be16 nge_port; 348 __be16 vxlan_gpe_port; 349 350 unsigned int current_interval; 351 struct timer_list timer; 352 struct workqueue_struct *bnge_pf_wq; 353 struct work_struct sp_task; 354 unsigned long sp_event; 355 356 struct bnge_ethtool_link_info eth_link_info; 357 358 u64 flags; 359 360 struct bnge_stats_mem port_stats; 361 struct bnge_stats_mem rx_port_stats_ext; 362 struct bnge_stats_mem tx_port_stats_ext; 363 u16 fw_rx_stats_ext_size; 364 u16 fw_tx_stats_ext_size; 365 366 struct netdev_queue_stats_rx rxq_prv_stats; 367 struct netdev_queue_stats_tx txq_prv_stats; 368 struct rtnl_link_stats64 prv_stats64; 369 spinlock_t stats_lock; 370 371 u8 pri2cos_idx[8]; 372 bool pri2cos_valid; 373 }; 374 375 #define BNGE_DEFAULT_RX_RING_SIZE 511 376 #define BNGE_DEFAULT_TX_RING_SIZE 511 377 378 int bnge_netdev_alloc(struct bnge_dev *bd, int max_irqs); 379 void bnge_netdev_free(struct bnge_dev *bd); 380 void bnge_set_ring_params(struct bnge_dev *bd); 381 382 #if (BNGE_PAGE_SHIFT == 16) 383 #define MAX_RX_PAGES_AGG_ENA 1 384 #define MAX_RX_PAGES 4 385 #define MAX_RX_AGG_PAGES 4 386 #define MAX_TX_PAGES 1 387 #define MAX_CP_PAGES 16 388 #else 389 #define MAX_RX_PAGES_AGG_ENA 8 390 #define MAX_RX_PAGES 32 391 #define MAX_RX_AGG_PAGES 32 392 #define MAX_TX_PAGES 8 393 #define MAX_CP_PAGES 128 394 #endif 395 396 #define BNGE_RX_PAGE_SIZE (1 << BNGE_RX_PAGE_SHIFT) 397 398 #define RX_DESC_CNT (BNGE_PAGE_SIZE / sizeof(struct rx_bd)) 399 #define TX_DESC_CNT (BNGE_PAGE_SIZE / sizeof(struct tx_bd)) 400 #define CP_DESC_CNT (BNGE_PAGE_SIZE / sizeof(struct tx_cmp)) 401 #define SW_RXBD_RING_SIZE (sizeof(struct bnge_sw_rx_bd) * RX_DESC_CNT) 402 #define HW_RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT) 403 #define SW_RXBD_AGG_RING_SIZE (sizeof(struct bnge_sw_rx_agg_bd) * RX_DESC_CNT) 404 #define SW_TXBD_RING_SIZE (sizeof(struct bnge_sw_tx_bd) * TX_DESC_CNT) 405 #define HW_TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT) 406 #define HW_CMPD_RING_SIZE (sizeof(struct tx_cmp) * CP_DESC_CNT) 407 #define BNGE_MAX_RX_DESC_CNT (RX_DESC_CNT * MAX_RX_PAGES - 1) 408 #define BNGE_MAX_RX_DESC_CNT_JUM_ENA (RX_DESC_CNT * MAX_RX_PAGES_AGG_ENA - 1) 409 #define BNGE_MAX_RX_JUM_DESC_CNT (RX_DESC_CNT * MAX_RX_AGG_PAGES - 1) 410 #define BNGE_MAX_TX_DESC_CNT (TX_DESC_CNT * MAX_TX_PAGES - 1) 411 412 #define BNGE_MAX_TXR_PER_NAPI 8 413 414 #define bnge_for_each_napi_tx(iter, bnapi, txr) \ 415 for (iter = 0, txr = (bnapi)->tx_ring[0]; txr; \ 416 txr = (iter < BNGE_MAX_TXR_PER_NAPI - 1) ? \ 417 (bnapi)->tx_ring[++iter] : NULL) 418 419 #define DB_EPOCH(db, idx) (((idx) & (db)->db_epoch_mask) << \ 420 ((db)->db_epoch_shift)) 421 422 #define DB_TOGGLE(tgl) ((tgl) << DBR_TOGGLE_SFT) 423 424 #define DB_RING_IDX(db, idx) (((idx) & (db)->db_ring_mask) | \ 425 DB_EPOCH(db, idx)) 426 427 #define BNGE_SET_NQ_HDL(cpr) \ 428 (((cpr)->cp_ring_type << BNGE_NQ_HDL_TYPE_SHIFT) | (cpr)->cp_idx) 429 430 #define BNGE_DB_NQ(bd, db, idx) \ 431 bnge_writeq(bd, (db)->db_key64 | DBR_TYPE_NQ | DB_RING_IDX(db, idx),\ 432 (db)->doorbell) 433 434 #define BNGE_DB_NQ_ARM(bd, db, idx) \ 435 bnge_writeq(bd, (db)->db_key64 | DBR_TYPE_NQ_ARM | \ 436 DB_RING_IDX(db, idx), (db)->doorbell) 437 438 struct nqe_cn { 439 __le16 type; 440 #define NQ_CN_TYPE_MASK 0x3fUL 441 #define NQ_CN_TYPE_SFT 0 442 #define NQ_CN_TYPE_CQ_NOTIFICATION 0x30UL 443 #define NQ_CN_TYPE_LAST NQ_CN_TYPE_CQ_NOTIFICATION 444 #define NQ_CN_TOGGLE_MASK 0xc0UL 445 #define NQ_CN_TOGGLE_SFT 6 446 __le16 reserved16; 447 __le32 cq_handle_low; 448 __le32 v; 449 #define NQ_CN_V 0x1UL 450 __le32 cq_handle_high; 451 }; 452 453 #define NQE_CN_TYPE(type) ((type) & NQ_CN_TYPE_MASK) 454 #define NQE_CN_TOGGLE(type) (((type) & NQ_CN_TOGGLE_MASK) >> \ 455 NQ_CN_TOGGLE_SFT) 456 457 struct bnge_cp_ring_info { 458 struct bnge_napi *bnapi; 459 dma_addr_t *desc_mapping; 460 struct tx_cmp **desc_ring; 461 struct bnge_ring_struct ring_struct; 462 u8 cp_ring_type; 463 u8 cp_idx; 464 u32 cp_raw_cons; 465 struct bnge_db_info cp_db; 466 bool had_work_done; 467 bool has_more_work; 468 bool had_nqe_notify; 469 u8 toggle; 470 }; 471 472 struct bnge_nq_ring_info { 473 struct bnge_napi *bnapi; 474 dma_addr_t *desc_mapping; 475 struct nqe_cn **desc_ring; 476 struct bnge_ring_struct ring_struct; 477 u32 nq_raw_cons; 478 struct bnge_db_info nq_db; 479 480 struct bnge_stats_mem stats; 481 u32 hw_stats_ctx_id; 482 bool has_more_work; 483 484 u16 cp_ring_count; 485 struct bnge_cp_ring_info *cp_ring_arr; 486 }; 487 488 struct bnge_rx_ring_info { 489 struct bnge_napi *bnapi; 490 struct bnge_cp_ring_info *rx_cpr; 491 u16 rx_prod; 492 u16 rx_agg_prod; 493 u16 rx_sw_agg_prod; 494 u16 rx_next_cons; 495 struct bnge_db_info rx_db; 496 struct bnge_db_info rx_agg_db; 497 498 struct rx_bd *rx_desc_ring[MAX_RX_PAGES]; 499 struct bnge_sw_rx_bd *rx_buf_ring; 500 501 struct rx_bd *rx_agg_desc_ring[MAX_RX_AGG_PAGES]; 502 struct bnge_sw_rx_agg_bd *rx_agg_buf_ring; 503 504 unsigned long *rx_agg_bmap; 505 u16 rx_agg_bmap_size; 506 507 dma_addr_t rx_desc_mapping[MAX_RX_PAGES]; 508 dma_addr_t rx_agg_desc_mapping[MAX_RX_AGG_PAGES]; 509 510 struct bnge_tpa_info *rx_tpa; 511 struct bnge_tpa_idx_map *rx_tpa_idx_map; 512 513 struct bnge_ring_struct rx_ring_struct; 514 struct bnge_ring_struct rx_agg_ring_struct; 515 struct page_pool *page_pool; 516 struct page_pool *head_pool; 517 bool need_head_pool; 518 }; 519 520 struct bnge_tx_ring_info { 521 struct bnge_napi *bnapi; 522 struct bnge_cp_ring_info *tx_cpr; 523 u16 tx_prod; 524 u16 tx_cons; 525 u16 tx_hw_cons; 526 u16 txq_index; 527 u8 tx_napi_idx; 528 u8 kick_pending; 529 struct bnge_db_info tx_db; 530 531 struct tx_bd *tx_desc_ring[MAX_TX_PAGES]; 532 struct bnge_sw_tx_bd *tx_buf_ring; 533 534 dma_addr_t tx_desc_mapping[MAX_TX_PAGES]; 535 536 u32 dev_state; 537 #define BNGE_DEV_STATE_CLOSING 0x1 538 539 struct bnge_ring_struct tx_ring_struct; 540 }; 541 542 struct bnge_napi { 543 struct napi_struct napi; 544 struct bnge_net *bn; 545 int index; 546 547 struct bnge_nq_ring_info nq_ring; 548 struct bnge_rx_ring_info *rx_ring; 549 struct bnge_tx_ring_info *tx_ring[BNGE_MAX_TXR_PER_NAPI]; 550 u8 events; 551 #define BNGE_RX_EVENT 1 552 #define BNGE_AGG_EVENT 2 553 #define BNGE_TX_EVENT 4 554 #define BNGE_REDIRECT_EVENT 8 555 #define BNGE_TX_CMP_EVENT 0x10 556 bool in_reset; 557 bool tx_fault; 558 }; 559 560 #define INVALID_STATS_CTX_ID -1 561 #define BNGE_VNIC_DEFAULT 0 562 #define BNGE_MAX_UC_ADDRS 4 563 564 struct bnge_vnic_info { 565 u16 fw_vnic_id; 566 #define BNGE_MAX_CTX_PER_VNIC 8 567 u16 fw_rss_cos_lb_ctx[BNGE_MAX_CTX_PER_VNIC]; 568 u16 mru; 569 /* index 0 always dev_addr */ 570 struct bnge_l2_filter *l2_filters[BNGE_MAX_UC_ADDRS]; 571 u16 uc_filter_count; 572 u8 *uc_list; 573 dma_addr_t rss_table_dma_addr; 574 __le16 *rss_table; 575 dma_addr_t rss_hash_key_dma_addr; 576 u64 *rss_hash_key; 577 int rss_table_size; 578 #define BNGE_RSS_TABLE_ENTRIES 64 579 #define BNGE_RSS_TABLE_SIZE (BNGE_RSS_TABLE_ENTRIES * 4) 580 #define BNGE_RSS_TABLE_MAX_TBL 8 581 #define BNGE_MAX_RSS_TABLE_SIZE \ 582 (BNGE_RSS_TABLE_SIZE * BNGE_RSS_TABLE_MAX_TBL) 583 u32 rx_mask; 584 585 u8 *mc_list; 586 int mc_list_size; 587 int mc_list_count; 588 dma_addr_t mc_list_mapping; 589 #define BNGE_MAX_MC_ADDRS 16 590 591 u32 flags; 592 #define BNGE_VNIC_RSS_FLAG 1 593 #define BNGE_VNIC_MCAST_FLAG 4 594 #define BNGE_VNIC_UCAST_FLAG 8 595 u32 vnic_id; 596 }; 597 598 struct bnge_filter_base { 599 struct hlist_node hash; 600 struct list_head list; 601 __le64 filter_id; 602 u8 type; 603 #define BNGE_FLTR_TYPE_L2 2 604 u8 flags; 605 u16 rxq; 606 u16 fw_vnic_id; 607 u16 vf_idx; 608 unsigned long state; 609 #define BNGE_FLTR_VALID 0 610 #define BNGE_FLTR_FW_DELETED 2 611 612 struct rcu_head rcu; 613 }; 614 615 struct bnge_l2_key { 616 union { 617 struct { 618 u8 dst_mac_addr[ETH_ALEN]; 619 u16 vlan; 620 }; 621 u32 filter_key; 622 }; 623 }; 624 625 #define BNGE_L2_KEY_SIZE (sizeof(struct bnge_l2_key) / 4) 626 struct bnge_l2_filter { 627 /* base filter must be the first member */ 628 struct bnge_filter_base base; 629 struct bnge_l2_key l2_key; 630 refcount_t refcnt; 631 }; 632 633 u16 bnge_cp_ring_for_rx(struct bnge_rx_ring_info *rxr); 634 u16 bnge_cp_ring_for_tx(struct bnge_tx_ring_info *txr); 635 void bnge_fill_hw_rss_tbl(struct bnge_net *bn, struct bnge_vnic_info *vnic); 636 int bnge_alloc_rx_data(struct bnge_net *bn, struct bnge_rx_ring_info *rxr, 637 u16 prod, gfp_t gfp); 638 u16 bnge_find_next_agg_idx(struct bnge_rx_ring_info *rxr, u16 idx); 639 u8 *__bnge_alloc_rx_frag(struct bnge_net *bn, dma_addr_t *mapping, 640 struct bnge_rx_ring_info *rxr, gfp_t gfp); 641 int bnge_alloc_rx_netmem(struct bnge_net *bn, struct bnge_rx_ring_info *rxr, 642 u16 prod, gfp_t gfp); 643 void __bnge_queue_sp_work(struct bnge_net *bn); 644 void bnge_copy_hw_masks(u64 *mask_arr, __le64 *hw_mask_arr, int count); 645 #endif /* _BNGE_NETDEV_H_ */ 646