1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2025 Broadcom */ 3 4 #ifndef _BNGE_NETDEV_H_ 5 #define _BNGE_NETDEV_H_ 6 7 #include <linux/bnxt/hsi.h> 8 #include <linux/io-64-nonatomic-lo-hi.h> 9 #include <linux/refcount.h> 10 #include "bnge_db.h" 11 12 struct tx_bd { 13 __le32 tx_bd_len_flags_type; 14 #define TX_BD_TYPE (0x3f << 0) 15 #define TX_BD_TYPE_SHORT_TX_BD (0x00 << 0) 16 #define TX_BD_TYPE_LONG_TX_BD (0x10 << 0) 17 #define TX_BD_FLAGS_PACKET_END (1 << 6) 18 #define TX_BD_FLAGS_NO_CMPL (1 << 7) 19 #define TX_BD_FLAGS_BD_CNT (0x1f << 8) 20 #define TX_BD_FLAGS_BD_CNT_SHIFT 8 21 #define TX_BD_FLAGS_LHINT (3 << 13) 22 #define TX_BD_FLAGS_LHINT_SHIFT 13 23 #define TX_BD_FLAGS_LHINT_512_AND_SMALLER (0 << 13) 24 #define TX_BD_FLAGS_LHINT_512_TO_1023 (1 << 13) 25 #define TX_BD_FLAGS_LHINT_1024_TO_2047 (2 << 13) 26 #define TX_BD_FLAGS_LHINT_2048_AND_LARGER (3 << 13) 27 #define TX_BD_FLAGS_COAL_NOW (1 << 15) 28 #define TX_BD_LEN (0xffff << 16) 29 #define TX_BD_LEN_SHIFT 16 30 u32 tx_bd_opaque; 31 __le64 tx_bd_haddr; 32 } __packed; 33 34 struct rx_bd { 35 __le32 rx_bd_len_flags_type; 36 #define RX_BD_TYPE (0x3f << 0) 37 #define RX_BD_TYPE_RX_PACKET_BD 0x4 38 #define RX_BD_TYPE_RX_BUFFER_BD 0x5 39 #define RX_BD_TYPE_RX_AGG_BD 0x6 40 #define RX_BD_TYPE_16B_BD_SIZE (0 << 4) 41 #define RX_BD_TYPE_32B_BD_SIZE (1 << 4) 42 #define RX_BD_TYPE_48B_BD_SIZE (2 << 4) 43 #define RX_BD_TYPE_64B_BD_SIZE (3 << 4) 44 #define RX_BD_FLAGS_SOP (1 << 6) 45 #define RX_BD_FLAGS_EOP (1 << 7) 46 #define RX_BD_FLAGS_BUFFERS (3 << 8) 47 #define RX_BD_FLAGS_1_BUFFER_PACKET (0 << 8) 48 #define RX_BD_FLAGS_2_BUFFER_PACKET (1 << 8) 49 #define RX_BD_FLAGS_3_BUFFER_PACKET (2 << 8) 50 #define RX_BD_FLAGS_4_BUFFER_PACKET (3 << 8) 51 #define RX_BD_LEN (0xffff << 16) 52 #define RX_BD_LEN_SHIFT 16 53 u32 rx_bd_opaque; 54 __le64 rx_bd_haddr; 55 }; 56 57 struct tx_cmp { 58 __le32 tx_cmp_flags_type; 59 #define CMP_TYPE (0x3f << 0) 60 #define CMP_TYPE_TX_L2_CMP 0 61 #define CMP_TYPE_TX_L2_COAL_CMP 2 62 #define CMP_TYPE_TX_L2_PKT_TS_CMP 4 63 #define CMP_TYPE_RX_L2_CMP 17 64 #define CMP_TYPE_RX_AGG_CMP 18 65 #define CMP_TYPE_RX_L2_TPA_START_CMP 19 66 #define CMP_TYPE_RX_L2_TPA_END_CMP 21 67 #define CMP_TYPE_RX_TPA_AGG_CMP 22 68 #define CMP_TYPE_RX_L2_V3_CMP 23 69 #define CMP_TYPE_RX_L2_TPA_START_V3_CMP 25 70 #define CMP_TYPE_STATUS_CMP 32 71 #define CMP_TYPE_REMOTE_DRIVER_REQ 34 72 #define CMP_TYPE_REMOTE_DRIVER_RESP 36 73 #define CMP_TYPE_ERROR_STATUS 48 74 #define CMPL_BASE_TYPE_STAT_EJECT 0x1aUL 75 #define CMPL_BASE_TYPE_HWRM_DONE 0x20UL 76 #define CMPL_BASE_TYPE_HWRM_FWD_REQ 0x22UL 77 #define CMPL_BASE_TYPE_HWRM_FWD_RESP 0x24UL 78 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 79 #define TX_CMP_FLAGS_ERROR (1 << 6) 80 #define TX_CMP_FLAGS_PUSH (1 << 7) 81 u32 tx_cmp_opaque; 82 __le32 tx_cmp_errors_v; 83 #define TX_CMP_V (1 << 0) 84 #define TX_CMP_ERRORS_BUFFER_ERROR (7 << 1) 85 #define TX_CMP_ERRORS_BUFFER_ERROR_NO_ERROR 0 86 #define TX_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT 2 87 #define TX_CMP_ERRORS_BUFFER_ERROR_INVALID_STAG 4 88 #define TX_CMP_ERRORS_BUFFER_ERROR_STAG_BOUNDS 5 89 #define TX_CMP_ERRORS_ZERO_LENGTH_PKT (1 << 4) 90 #define TX_CMP_ERRORS_EXCESSIVE_BD_LEN (1 << 5) 91 #define TX_CMP_ERRORS_DMA_ERROR (1 << 6) 92 #define TX_CMP_ERRORS_HINT_TOO_SHORT (1 << 7) 93 __le32 sq_cons_idx; 94 #define TX_CMP_SQ_CONS_IDX_MASK 0x00ffffff 95 }; 96 97 struct bnge_sw_tx_bd { 98 struct sk_buff *skb; 99 DEFINE_DMA_UNMAP_ADDR(mapping); 100 DEFINE_DMA_UNMAP_LEN(len); 101 struct page *page; 102 u8 is_ts_pkt; 103 u8 is_push; 104 u8 action; 105 unsigned short nr_frags; 106 union { 107 u16 rx_prod; 108 u16 txts_prod; 109 }; 110 }; 111 112 struct bnge_sw_rx_bd { 113 void *data; 114 u8 *data_ptr; 115 dma_addr_t mapping; 116 }; 117 118 struct bnge_sw_rx_agg_bd { 119 netmem_ref netmem; 120 unsigned int offset; 121 dma_addr_t mapping; 122 }; 123 124 #define HWRM_RING_ALLOC_TX 0x1 125 #define HWRM_RING_ALLOC_RX 0x2 126 #define HWRM_RING_ALLOC_AGG 0x4 127 #define HWRM_RING_ALLOC_CMPL 0x8 128 #define HWRM_RING_ALLOC_NQ 0x10 129 130 struct bnge_ring_grp_info { 131 u16 fw_stats_ctx; 132 u16 fw_grp_id; 133 u16 rx_fw_ring_id; 134 u16 agg_fw_ring_id; 135 u16 nq_fw_ring_id; 136 }; 137 138 #define BNGE_RX_COPY_THRESH 256 139 140 #define BNGE_HW_FEATURE_VLAN_ALL_RX \ 141 (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX) 142 #define BNGE_HW_FEATURE_VLAN_ALL_TX \ 143 (NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_STAG_TX) 144 145 enum { 146 BNGE_NET_EN_GRO = BIT(0), 147 BNGE_NET_EN_LRO = BIT(1), 148 BNGE_NET_EN_JUMBO = BIT(2), 149 }; 150 151 #define BNGE_NET_EN_TPA (BNGE_NET_EN_GRO | BNGE_NET_EN_LRO) 152 153 /* Minimum TX BDs for a TX packet with MAX_SKB_FRAGS + 1. We need one extra 154 * BD because the first TX BD is always a long BD. 155 */ 156 #define BNGE_MIN_TX_DESC_CNT (MAX_SKB_FRAGS + 2) 157 158 #define RX_RING(bn, x) (((x) & (bn)->rx_ring_mask) >> (BNGE_PAGE_SHIFT - 4)) 159 #define RX_AGG_RING(bn, x) (((x) & (bn)->rx_agg_ring_mask) >> \ 160 (BNGE_PAGE_SHIFT - 4)) 161 #define RX_IDX(x) ((x) & (RX_DESC_CNT - 1)) 162 163 #define TX_RING(bn, x) (((x) & (bn)->tx_ring_mask) >> (BNGE_PAGE_SHIFT - 4)) 164 #define TX_IDX(x) ((x) & (TX_DESC_CNT - 1)) 165 166 #define CP_RING(x) (((x) & ~(CP_DESC_CNT - 1)) >> (BNGE_PAGE_SHIFT - 4)) 167 #define CP_IDX(x) ((x) & (CP_DESC_CNT - 1)) 168 169 #define RING_RX(bn, idx) ((idx) & (bn)->rx_ring_mask) 170 #define NEXT_RX(idx) ((idx) + 1) 171 172 #define RING_RX_AGG(bn, idx) ((idx) & (bn)->rx_agg_ring_mask) 173 #define NEXT_RX_AGG(idx) ((idx) + 1) 174 175 #define BNGE_NQ_HDL_TYPE_SHIFT 24 176 #define BNGE_NQ_HDL_TYPE_RX 0x00 177 #define BNGE_NQ_HDL_TYPE_TX 0x01 178 179 struct bnge_net { 180 struct bnge_dev *bd; 181 struct net_device *netdev; 182 183 u32 priv_flags; 184 185 u32 rx_ring_size; 186 u32 rx_buf_size; 187 u32 rx_buf_use_size; /* usable size */ 188 u32 rx_agg_ring_size; 189 u32 rx_copy_thresh; 190 u32 rx_ring_mask; 191 u32 rx_agg_ring_mask; 192 u16 rx_nr_pages; 193 u16 rx_agg_nr_pages; 194 195 u32 tx_ring_size; 196 u32 tx_ring_mask; 197 u16 tx_nr_pages; 198 199 /* NQs and Completion rings */ 200 u32 cp_ring_size; 201 u32 cp_ring_mask; 202 u32 cp_bit; 203 u16 cp_nr_pages; 204 205 #define BNGE_L2_FLTR_HASH_SIZE 32 206 #define BNGE_L2_FLTR_HASH_MASK (BNGE_L2_FLTR_HASH_SIZE - 1) 207 struct hlist_head l2_fltr_hash_tbl[BNGE_L2_FLTR_HASH_SIZE]; 208 u32 hash_seed; 209 u64 toeplitz_prefix; 210 211 struct bnge_napi **bnapi; 212 213 struct bnge_rx_ring_info *rx_ring; 214 struct bnge_tx_ring_info *tx_ring; 215 216 u16 *tx_ring_map; 217 enum dma_data_direction rx_dir; 218 219 /* grp_info indexed by napi/nq index */ 220 struct bnge_ring_grp_info *grp_info; 221 struct bnge_vnic_info *vnic_info; 222 int nr_vnics; 223 int total_irqs; 224 225 u32 tx_wake_thresh; 226 u16 rx_offset; 227 u16 rx_dma_offset; 228 229 u8 rss_hash_key[HW_HASH_KEY_SIZE]; 230 u8 rss_hash_key_valid:1; 231 u8 rss_hash_key_updated:1; 232 int rsscos_nr_ctxs; 233 u32 stats_coal_ticks; 234 }; 235 236 #define BNGE_DEFAULT_RX_RING_SIZE 511 237 #define BNGE_DEFAULT_TX_RING_SIZE 511 238 239 int bnge_netdev_alloc(struct bnge_dev *bd, int max_irqs); 240 void bnge_netdev_free(struct bnge_dev *bd); 241 void bnge_set_ring_params(struct bnge_dev *bd); 242 243 #if (BNGE_PAGE_SHIFT == 16) 244 #define MAX_RX_PAGES_AGG_ENA 1 245 #define MAX_RX_PAGES 4 246 #define MAX_RX_AGG_PAGES 4 247 #define MAX_TX_PAGES 1 248 #define MAX_CP_PAGES 16 249 #else 250 #define MAX_RX_PAGES_AGG_ENA 8 251 #define MAX_RX_PAGES 32 252 #define MAX_RX_AGG_PAGES 32 253 #define MAX_TX_PAGES 8 254 #define MAX_CP_PAGES 128 255 #endif 256 257 #define BNGE_RX_PAGE_SIZE (1 << BNGE_RX_PAGE_SHIFT) 258 259 #define RX_DESC_CNT (BNGE_PAGE_SIZE / sizeof(struct rx_bd)) 260 #define TX_DESC_CNT (BNGE_PAGE_SIZE / sizeof(struct tx_bd)) 261 #define CP_DESC_CNT (BNGE_PAGE_SIZE / sizeof(struct tx_cmp)) 262 #define SW_RXBD_RING_SIZE (sizeof(struct bnge_sw_rx_bd) * RX_DESC_CNT) 263 #define HW_RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT) 264 #define SW_RXBD_AGG_RING_SIZE (sizeof(struct bnge_sw_rx_agg_bd) * RX_DESC_CNT) 265 #define SW_TXBD_RING_SIZE (sizeof(struct bnge_sw_tx_bd) * TX_DESC_CNT) 266 #define HW_TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT) 267 #define HW_CMPD_RING_SIZE (sizeof(struct tx_cmp) * CP_DESC_CNT) 268 #define BNGE_MAX_RX_DESC_CNT (RX_DESC_CNT * MAX_RX_PAGES - 1) 269 #define BNGE_MAX_RX_DESC_CNT_JUM_ENA (RX_DESC_CNT * MAX_RX_PAGES_AGG_ENA - 1) 270 #define BNGE_MAX_RX_JUM_DESC_CNT (RX_DESC_CNT * MAX_RX_AGG_PAGES - 1) 271 #define BNGE_MAX_TX_DESC_CNT (TX_DESC_CNT * MAX_TX_PAGES - 1) 272 273 #define BNGE_MAX_TXR_PER_NAPI 8 274 275 #define bnge_for_each_napi_tx(iter, bnapi, txr) \ 276 for (iter = 0, txr = (bnapi)->tx_ring[0]; txr; \ 277 txr = (iter < BNGE_MAX_TXR_PER_NAPI - 1) ? \ 278 (bnapi)->tx_ring[++iter] : NULL) 279 280 #define BNGE_SET_NQ_HDL(cpr) \ 281 (((cpr)->cp_ring_type << BNGE_NQ_HDL_TYPE_SHIFT) | (cpr)->cp_idx) 282 283 struct bnge_stats_mem { 284 u64 *sw_stats; 285 u64 *hw_masks; 286 void *hw_stats; 287 dma_addr_t hw_stats_map; 288 int len; 289 }; 290 291 struct bnge_cp_ring_info { 292 struct bnge_napi *bnapi; 293 dma_addr_t *desc_mapping; 294 struct tx_cmp **desc_ring; 295 struct bnge_ring_struct ring_struct; 296 u8 cp_ring_type; 297 u8 cp_idx; 298 u32 cp_raw_cons; 299 struct bnge_db_info cp_db; 300 }; 301 302 struct bnge_nq_ring_info { 303 struct bnge_napi *bnapi; 304 dma_addr_t *desc_mapping; 305 struct nqe_cn **desc_ring; 306 struct bnge_ring_struct ring_struct; 307 u32 nq_raw_cons; 308 struct bnge_db_info nq_db; 309 310 struct bnge_stats_mem stats; 311 u32 hw_stats_ctx_id; 312 313 int cp_ring_count; 314 struct bnge_cp_ring_info *cp_ring_arr; 315 }; 316 317 struct bnge_rx_ring_info { 318 struct bnge_napi *bnapi; 319 struct bnge_cp_ring_info *rx_cpr; 320 u16 rx_prod; 321 u16 rx_agg_prod; 322 u16 rx_sw_agg_prod; 323 u16 rx_next_cons; 324 struct bnge_db_info rx_db; 325 struct bnge_db_info rx_agg_db; 326 327 struct rx_bd *rx_desc_ring[MAX_RX_PAGES]; 328 struct bnge_sw_rx_bd *rx_buf_ring; 329 330 struct rx_bd *rx_agg_desc_ring[MAX_RX_AGG_PAGES]; 331 struct bnge_sw_rx_agg_bd *rx_agg_buf_ring; 332 333 unsigned long *rx_agg_bmap; 334 u16 rx_agg_bmap_size; 335 336 dma_addr_t rx_desc_mapping[MAX_RX_PAGES]; 337 dma_addr_t rx_agg_desc_mapping[MAX_RX_AGG_PAGES]; 338 339 struct bnge_ring_struct rx_ring_struct; 340 struct bnge_ring_struct rx_agg_ring_struct; 341 struct page_pool *page_pool; 342 struct page_pool *head_pool; 343 bool need_head_pool; 344 }; 345 346 struct bnge_tx_ring_info { 347 struct bnge_napi *bnapi; 348 struct bnge_cp_ring_info *tx_cpr; 349 u16 tx_prod; 350 u16 tx_cons; 351 u16 tx_hw_cons; 352 u16 txq_index; 353 u8 tx_napi_idx; 354 u8 kick_pending; 355 struct bnge_db_info tx_db; 356 357 struct tx_bd *tx_desc_ring[MAX_TX_PAGES]; 358 struct bnge_sw_tx_bd *tx_buf_ring; 359 360 dma_addr_t tx_desc_mapping[MAX_TX_PAGES]; 361 362 u32 dev_state; 363 #define BNGE_DEV_STATE_CLOSING 0x1 364 365 struct bnge_ring_struct tx_ring_struct; 366 }; 367 368 struct bnge_napi { 369 struct napi_struct napi; 370 struct bnge_net *bn; 371 int index; 372 373 struct bnge_nq_ring_info nq_ring; 374 struct bnge_rx_ring_info *rx_ring; 375 struct bnge_tx_ring_info *tx_ring[BNGE_MAX_TXR_PER_NAPI]; 376 }; 377 378 #define INVALID_STATS_CTX_ID -1 379 #define BNGE_VNIC_DEFAULT 0 380 #define BNGE_MAX_UC_ADDRS 4 381 382 struct bnge_vnic_info { 383 u16 fw_vnic_id; 384 #define BNGE_MAX_CTX_PER_VNIC 8 385 u16 fw_rss_cos_lb_ctx[BNGE_MAX_CTX_PER_VNIC]; 386 u16 mru; 387 /* index 0 always dev_addr */ 388 struct bnge_l2_filter *l2_filters[BNGE_MAX_UC_ADDRS]; 389 u16 uc_filter_count; 390 u8 *uc_list; 391 dma_addr_t rss_table_dma_addr; 392 __le16 *rss_table; 393 dma_addr_t rss_hash_key_dma_addr; 394 u64 *rss_hash_key; 395 int rss_table_size; 396 #define BNGE_RSS_TABLE_ENTRIES 64 397 #define BNGE_RSS_TABLE_SIZE (BNGE_RSS_TABLE_ENTRIES * 4) 398 #define BNGE_RSS_TABLE_MAX_TBL 8 399 #define BNGE_MAX_RSS_TABLE_SIZE \ 400 (BNGE_RSS_TABLE_SIZE * BNGE_RSS_TABLE_MAX_TBL) 401 u32 rx_mask; 402 403 u8 *mc_list; 404 int mc_list_size; 405 int mc_list_count; 406 dma_addr_t mc_list_mapping; 407 #define BNGE_MAX_MC_ADDRS 16 408 409 u32 flags; 410 #define BNGE_VNIC_RSS_FLAG 1 411 #define BNGE_VNIC_MCAST_FLAG 4 412 #define BNGE_VNIC_UCAST_FLAG 8 413 u32 vnic_id; 414 }; 415 416 struct bnge_filter_base { 417 struct hlist_node hash; 418 struct list_head list; 419 __le64 filter_id; 420 u8 type; 421 #define BNGE_FLTR_TYPE_L2 2 422 u8 flags; 423 u16 rxq; 424 u16 fw_vnic_id; 425 u16 vf_idx; 426 unsigned long state; 427 #define BNGE_FLTR_VALID 0 428 #define BNGE_FLTR_FW_DELETED 2 429 430 struct rcu_head rcu; 431 }; 432 433 struct bnge_l2_key { 434 union { 435 struct { 436 u8 dst_mac_addr[ETH_ALEN]; 437 u16 vlan; 438 }; 439 u32 filter_key; 440 }; 441 }; 442 443 #define BNGE_L2_KEY_SIZE (sizeof(struct bnge_l2_key) / 4) 444 struct bnge_l2_filter { 445 /* base filter must be the first member */ 446 struct bnge_filter_base base; 447 struct bnge_l2_key l2_key; 448 refcount_t refcnt; 449 }; 450 451 u16 bnge_cp_ring_for_rx(struct bnge_rx_ring_info *rxr); 452 u16 bnge_cp_ring_for_tx(struct bnge_tx_ring_info *txr); 453 void bnge_fill_hw_rss_tbl(struct bnge_net *bn, struct bnge_vnic_info *vnic); 454 #endif /* _BNGE_NETDEV_H_ */ 455