1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2025 Broadcom */ 3 4 #ifndef _BNGE_H_ 5 #define _BNGE_H_ 6 7 #define DRV_NAME "bng_en" 8 #define DRV_SUMMARY "Broadcom ThorUltra NIC Ethernet Driver" 9 10 #include <linux/etherdevice.h> 11 #include <linux/bnxt/hsi.h> 12 #include "bnge_rmem.h" 13 #include "bnge_resc.h" 14 #include "bnge_auxr.h" 15 16 #define DRV_VER_MAJ 1 17 #define DRV_VER_MIN 15 18 #define DRV_VER_UPD 1 19 20 extern char bnge_driver_name[]; 21 22 enum board_idx { 23 BCM57708, 24 }; 25 26 struct bnge_auxr_priv { 27 struct auxiliary_device aux_dev; 28 struct bnge_auxr_dev *auxr_dev; 29 int id; 30 }; 31 32 struct bnge_pf_info { 33 u16 fw_fid; 34 u16 port_id; 35 u8 mac_addr[ETH_ALEN]; 36 }; 37 38 #define INVALID_HW_RING_ID ((u16)-1) 39 40 enum { 41 BNGE_FW_CAP_SHORT_CMD = BIT_ULL(0), 42 BNGE_FW_CAP_LLDP_AGENT = BIT_ULL(1), 43 BNGE_FW_CAP_DCBX_AGENT = BIT_ULL(2), 44 BNGE_FW_CAP_IF_CHANGE = BIT_ULL(3), 45 BNGE_FW_CAP_KONG_MB_CHNL = BIT_ULL(4), 46 BNGE_FW_CAP_ERROR_RECOVERY = BIT_ULL(5), 47 BNGE_FW_CAP_PKG_VER = BIT_ULL(6), 48 BNGE_FW_CAP_CFA_ADV_FLOW = BIT_ULL(7), 49 BNGE_FW_CAP_CFA_RFS_RING_TBL_IDX_V2 = BIT_ULL(8), 50 BNGE_FW_CAP_PCIE_STATS_SUPPORTED = BIT_ULL(9), 51 BNGE_FW_CAP_EXT_STATS_SUPPORTED = BIT_ULL(10), 52 BNGE_FW_CAP_ERR_RECOVER_RELOAD = BIT_ULL(11), 53 BNGE_FW_CAP_HOT_RESET = BIT_ULL(12), 54 BNGE_FW_CAP_RX_ALL_PKT_TS = BIT_ULL(13), 55 BNGE_FW_CAP_VLAN_RX_STRIP = BIT_ULL(14), 56 BNGE_FW_CAP_VLAN_TX_INSERT = BIT_ULL(15), 57 BNGE_FW_CAP_EXT_HW_STATS_SUPPORTED = BIT_ULL(16), 58 BNGE_FW_CAP_LIVEPATCH = BIT_ULL(17), 59 BNGE_FW_CAP_HOT_RESET_IF = BIT_ULL(18), 60 BNGE_FW_CAP_RING_MONITOR = BIT_ULL(19), 61 BNGE_FW_CAP_DBG_QCAPS = BIT_ULL(20), 62 BNGE_FW_CAP_THRESHOLD_TEMP_SUPPORTED = BIT_ULL(21), 63 BNGE_FW_CAP_DFLT_VLAN_TPID_PCP = BIT_ULL(22), 64 BNGE_FW_CAP_VNIC_TUNNEL_TPA = BIT_ULL(23), 65 BNGE_FW_CAP_CFA_NTUPLE_RX_EXT_IP_PROTO = BIT_ULL(24), 66 BNGE_FW_CAP_CFA_RFS_RING_TBL_IDX_V3 = BIT_ULL(25), 67 BNGE_FW_CAP_VNIC_RE_FLUSH = BIT_ULL(26), 68 }; 69 70 enum { 71 BNGE_EN_ROCE_V1 = BIT_ULL(0), 72 BNGE_EN_ROCE_V2 = BIT_ULL(1), 73 BNGE_EN_STRIP_VLAN = BIT_ULL(2), 74 BNGE_EN_SHARED_CHNL = BIT_ULL(3), 75 BNGE_EN_UDP_GSO_SUPP = BIT_ULL(4), 76 }; 77 78 #define BNGE_EN_ROCE (BNGE_EN_ROCE_V1 | BNGE_EN_ROCE_V2) 79 80 enum { 81 BNGE_RSS_CAP_RSS_HASH_TYPE_DELTA = BIT(0), 82 BNGE_RSS_CAP_UDP_RSS_CAP = BIT(1), 83 BNGE_RSS_CAP_NEW_RSS_CAP = BIT(2), 84 BNGE_RSS_CAP_RSS_TCAM = BIT(3), 85 BNGE_RSS_CAP_AH_V4_RSS_CAP = BIT(4), 86 BNGE_RSS_CAP_AH_V6_RSS_CAP = BIT(5), 87 BNGE_RSS_CAP_ESP_V4_RSS_CAP = BIT(6), 88 BNGE_RSS_CAP_ESP_V6_RSS_CAP = BIT(7), 89 }; 90 91 #define BNGE_MAX_QUEUE 8 92 struct bnge_queue_info { 93 u8 queue_id; 94 u8 queue_profile; 95 }; 96 97 struct bnge_dev { 98 struct device *dev; 99 struct pci_dev *pdev; 100 struct net_device *netdev; 101 u64 dsn; 102 #define BNGE_VPD_FLD_LEN 32 103 char board_partno[BNGE_VPD_FLD_LEN]; 104 char board_serialno[BNGE_VPD_FLD_LEN]; 105 106 void __iomem *bar0; 107 void __iomem *bar1; 108 109 u16 chip_num; 110 u8 chip_rev; 111 112 #if BITS_PER_LONG == 32 113 /* ensure atomic 64-bit doorbell writes on 32-bit systems. */ 114 spinlock_t db_lock; 115 #endif 116 int db_offset; /* db_offset within db_size */ 117 int db_size; 118 119 /* HWRM members */ 120 u16 hwrm_cmd_seq; 121 u16 hwrm_cmd_kong_seq; 122 struct dma_pool *hwrm_dma_pool; 123 struct hlist_head hwrm_pending_list; 124 u16 hwrm_max_req_len; 125 u16 hwrm_max_ext_req_len; 126 unsigned int hwrm_cmd_timeout; 127 unsigned int hwrm_cmd_max_timeout; 128 struct mutex hwrm_cmd_lock; /* serialize hwrm messages */ 129 130 struct hwrm_ver_get_output ver_resp; 131 #define FW_VER_STR_LEN 32 132 char fw_ver_str[FW_VER_STR_LEN]; 133 char hwrm_ver_supp[FW_VER_STR_LEN]; 134 char nvm_cfg_ver[FW_VER_STR_LEN]; 135 u64 fw_ver_code; 136 #define BNGE_FW_VER_CODE(maj, min, bld, rsv) \ 137 ((u64)(maj) << 48 | (u64)(min) << 32 | (u64)(bld) << 16 | (rsv)) 138 139 struct bnge_pf_info pf; 140 141 unsigned long state; 142 #define BNGE_STATE_DRV_REGISTERED 0 143 #define BNGE_STATE_OPEN 1 144 145 u64 fw_cap; 146 147 /* Backing stores */ 148 struct bnge_ctx_mem_info *ctx; 149 150 u64 flags; 151 152 struct bnge_hw_resc hw_resc; 153 154 u16 tso_max_segs; 155 156 int max_fltr; 157 #define BNGE_L2_FLTR_MAX_FLTR 1024 158 159 u32 *rss_indir_tbl; 160 #define BNGE_RSS_TABLE_ENTRIES 64 161 #define BNGE_RSS_TABLE_SIZE (BNGE_RSS_TABLE_ENTRIES * 4) 162 #define BNGE_RSS_TABLE_MAX_TBL 8 163 #define BNGE_MAX_RSS_TABLE_SIZE \ 164 (BNGE_RSS_TABLE_SIZE * BNGE_RSS_TABLE_MAX_TBL) 165 #define BNGE_MAX_RSS_TABLE_ENTRIES \ 166 (BNGE_RSS_TABLE_ENTRIES * BNGE_RSS_TABLE_MAX_TBL) 167 u16 rss_indir_tbl_entries; 168 169 u32 rss_cap; 170 u32 rss_hash_cfg; 171 172 u16 rx_nr_rings; 173 u16 tx_nr_rings; 174 u16 tx_nr_rings_per_tc; 175 /* Number of NQs */ 176 u16 nq_nr_rings; 177 178 /* Aux device resources */ 179 u16 aux_num_msix; 180 u16 aux_num_stat_ctxs; 181 182 u16 max_mtu; 183 #define BNGE_MAX_MTU 9500 184 185 u16 hw_ring_stats_size; 186 #define BNGE_NUM_RX_RING_STATS 8 187 #define BNGE_NUM_TX_RING_STATS 8 188 #define BNGE_NUM_TPA_RING_STATS 6 189 #define BNGE_RING_STATS_SIZE \ 190 ((BNGE_NUM_RX_RING_STATS + BNGE_NUM_TX_RING_STATS + \ 191 BNGE_NUM_TPA_RING_STATS) * 8) 192 193 u16 max_tpa_v2; 194 #define BNGE_SUPPORTS_TPA(bd) ((bd)->max_tpa_v2) 195 196 u8 num_tc; 197 u8 max_tc; 198 u8 max_lltc; /* lossless TCs */ 199 struct bnge_queue_info q_info[BNGE_MAX_QUEUE]; 200 u8 tc_to_qidx[BNGE_MAX_QUEUE]; 201 u8 q_ids[BNGE_MAX_QUEUE]; 202 u8 max_q; 203 u8 port_count; 204 205 struct bnge_irq *irq_tbl; 206 u16 irqs_acquired; 207 208 struct bnge_auxr_priv *aux_priv; 209 struct bnge_auxr_dev *auxr_dev; 210 }; 211 212 static inline bool bnge_is_roce_en(struct bnge_dev *bd) 213 { 214 return bd->flags & BNGE_EN_ROCE; 215 } 216 217 static inline bool bnge_is_agg_reqd(struct bnge_dev *bd) 218 { 219 if (bd->netdev) { 220 struct bnge_net *bn = netdev_priv(bd->netdev); 221 222 if (bn->priv_flags & BNGE_NET_EN_TPA || 223 bn->priv_flags & BNGE_NET_EN_JUMBO) 224 return true; 225 else 226 return false; 227 } 228 229 return true; 230 } 231 232 static inline void bnge_writeq(struct bnge_dev *bd, u64 val, 233 void __iomem *addr) 234 { 235 #if BITS_PER_LONG == 32 236 spin_lock(&bd->db_lock); 237 lo_hi_writeq(val, addr); 238 spin_unlock(&bd->db_lock); 239 #else 240 writeq(val, addr); 241 #endif 242 } 243 244 /* For TX and RX ring doorbells */ 245 static inline void bnge_db_write(struct bnge_dev *bd, struct bnge_db_info *db, 246 u32 idx) 247 { 248 bnge_writeq(bd, db->db_key64 | DB_RING_IDX(db, idx), 249 db->doorbell); 250 } 251 252 bool bnge_aux_registered(struct bnge_dev *bd); 253 u16 bnge_aux_get_msix(struct bnge_dev *bd); 254 255 #endif /* _BNGE_H_ */ 256