1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2025 Broadcom */ 3 4 #ifndef _BNGE_H_ 5 #define _BNGE_H_ 6 7 #define DRV_NAME "bng_en" 8 #define DRV_SUMMARY "Broadcom 800G Ethernet Linux Driver" 9 10 #include <linux/etherdevice.h> 11 #include <linux/bnxt/hsi.h> 12 #include "bnge_rmem.h" 13 #include "bnge_resc.h" 14 15 #define DRV_VER_MAJ 1 16 #define DRV_VER_MIN 15 17 #define DRV_VER_UPD 1 18 19 extern char bnge_driver_name[]; 20 21 enum board_idx { 22 BCM57708, 23 }; 24 25 struct bnge_pf_info { 26 u16 fw_fid; 27 u16 port_id; 28 u8 mac_addr[ETH_ALEN]; 29 }; 30 31 #define INVALID_HW_RING_ID ((u16)-1) 32 33 enum { 34 BNGE_FW_CAP_SHORT_CMD = BIT_ULL(0), 35 BNGE_FW_CAP_LLDP_AGENT = BIT_ULL(1), 36 BNGE_FW_CAP_DCBX_AGENT = BIT_ULL(2), 37 BNGE_FW_CAP_IF_CHANGE = BIT_ULL(3), 38 BNGE_FW_CAP_KONG_MB_CHNL = BIT_ULL(4), 39 BNGE_FW_CAP_ERROR_RECOVERY = BIT_ULL(5), 40 BNGE_FW_CAP_PKG_VER = BIT_ULL(6), 41 BNGE_FW_CAP_CFA_ADV_FLOW = BIT_ULL(7), 42 BNGE_FW_CAP_CFA_RFS_RING_TBL_IDX_V2 = BIT_ULL(8), 43 BNGE_FW_CAP_PCIE_STATS_SUPPORTED = BIT_ULL(9), 44 BNGE_FW_CAP_EXT_STATS_SUPPORTED = BIT_ULL(10), 45 BNGE_FW_CAP_ERR_RECOVER_RELOAD = BIT_ULL(11), 46 BNGE_FW_CAP_HOT_RESET = BIT_ULL(12), 47 BNGE_FW_CAP_RX_ALL_PKT_TS = BIT_ULL(13), 48 BNGE_FW_CAP_VLAN_RX_STRIP = BIT_ULL(14), 49 BNGE_FW_CAP_VLAN_TX_INSERT = BIT_ULL(15), 50 BNGE_FW_CAP_EXT_HW_STATS_SUPPORTED = BIT_ULL(16), 51 BNGE_FW_CAP_LIVEPATCH = BIT_ULL(17), 52 BNGE_FW_CAP_HOT_RESET_IF = BIT_ULL(18), 53 BNGE_FW_CAP_RING_MONITOR = BIT_ULL(19), 54 BNGE_FW_CAP_DBG_QCAPS = BIT_ULL(20), 55 BNGE_FW_CAP_THRESHOLD_TEMP_SUPPORTED = BIT_ULL(21), 56 BNGE_FW_CAP_DFLT_VLAN_TPID_PCP = BIT_ULL(22), 57 BNGE_FW_CAP_VNIC_TUNNEL_TPA = BIT_ULL(23), 58 BNGE_FW_CAP_CFA_NTUPLE_RX_EXT_IP_PROTO = BIT_ULL(24), 59 BNGE_FW_CAP_CFA_RFS_RING_TBL_IDX_V3 = BIT_ULL(25), 60 BNGE_FW_CAP_VNIC_RE_FLUSH = BIT_ULL(26), 61 }; 62 63 enum { 64 BNGE_EN_ROCE_V1 = BIT_ULL(0), 65 BNGE_EN_ROCE_V2 = BIT_ULL(1), 66 BNGE_EN_STRIP_VLAN = BIT_ULL(2), 67 BNGE_EN_SHARED_CHNL = BIT_ULL(3), 68 BNGE_EN_UDP_GSO_SUPP = BIT_ULL(4), 69 }; 70 71 #define BNGE_EN_ROCE (BNGE_EN_ROCE_V1 | BNGE_EN_ROCE_V2) 72 73 enum { 74 BNGE_RSS_CAP_RSS_HASH_TYPE_DELTA = BIT(0), 75 BNGE_RSS_CAP_UDP_RSS_CAP = BIT(1), 76 BNGE_RSS_CAP_NEW_RSS_CAP = BIT(2), 77 BNGE_RSS_CAP_RSS_TCAM = BIT(3), 78 BNGE_RSS_CAP_AH_V4_RSS_CAP = BIT(4), 79 BNGE_RSS_CAP_AH_V6_RSS_CAP = BIT(5), 80 BNGE_RSS_CAP_ESP_V4_RSS_CAP = BIT(6), 81 BNGE_RSS_CAP_ESP_V6_RSS_CAP = BIT(7), 82 }; 83 84 #define BNGE_MAX_QUEUE 8 85 struct bnge_queue_info { 86 u8 queue_id; 87 u8 queue_profile; 88 }; 89 90 struct bnge_dev { 91 struct device *dev; 92 struct pci_dev *pdev; 93 struct net_device *netdev; 94 u64 dsn; 95 #define BNGE_VPD_FLD_LEN 32 96 char board_partno[BNGE_VPD_FLD_LEN]; 97 char board_serialno[BNGE_VPD_FLD_LEN]; 98 99 void __iomem *bar0; 100 void __iomem *bar1; 101 102 u16 chip_num; 103 u8 chip_rev; 104 105 #if BITS_PER_LONG == 32 106 /* ensure atomic 64-bit doorbell writes on 32-bit systems. */ 107 spinlock_t db_lock; 108 #endif 109 int db_offset; /* db_offset within db_size */ 110 int db_size; 111 112 /* HWRM members */ 113 u16 hwrm_cmd_seq; 114 u16 hwrm_cmd_kong_seq; 115 struct dma_pool *hwrm_dma_pool; 116 struct hlist_head hwrm_pending_list; 117 u16 hwrm_max_req_len; 118 u16 hwrm_max_ext_req_len; 119 unsigned int hwrm_cmd_timeout; 120 unsigned int hwrm_cmd_max_timeout; 121 struct mutex hwrm_cmd_lock; /* serialize hwrm messages */ 122 123 struct hwrm_ver_get_output ver_resp; 124 #define FW_VER_STR_LEN 32 125 char fw_ver_str[FW_VER_STR_LEN]; 126 char hwrm_ver_supp[FW_VER_STR_LEN]; 127 char nvm_cfg_ver[FW_VER_STR_LEN]; 128 u64 fw_ver_code; 129 #define BNGE_FW_VER_CODE(maj, min, bld, rsv) \ 130 ((u64)(maj) << 48 | (u64)(min) << 32 | (u64)(bld) << 16 | (rsv)) 131 132 struct bnge_pf_info pf; 133 134 unsigned long state; 135 #define BNGE_STATE_DRV_REGISTERED 0 136 #define BNGE_STATE_OPEN 1 137 138 u64 fw_cap; 139 140 /* Backing stores */ 141 struct bnge_ctx_mem_info *ctx; 142 143 u64 flags; 144 145 struct bnge_hw_resc hw_resc; 146 147 u16 tso_max_segs; 148 149 int max_fltr; 150 #define BNGE_L2_FLTR_MAX_FLTR 1024 151 152 u32 *rss_indir_tbl; 153 #define BNGE_RSS_TABLE_ENTRIES 64 154 #define BNGE_RSS_TABLE_SIZE (BNGE_RSS_TABLE_ENTRIES * 4) 155 #define BNGE_RSS_TABLE_MAX_TBL 8 156 #define BNGE_MAX_RSS_TABLE_SIZE \ 157 (BNGE_RSS_TABLE_SIZE * BNGE_RSS_TABLE_MAX_TBL) 158 #define BNGE_MAX_RSS_TABLE_ENTRIES \ 159 (BNGE_RSS_TABLE_ENTRIES * BNGE_RSS_TABLE_MAX_TBL) 160 u16 rss_indir_tbl_entries; 161 162 u32 rss_cap; 163 u32 rss_hash_cfg; 164 165 u16 rx_nr_rings; 166 u16 tx_nr_rings; 167 u16 tx_nr_rings_per_tc; 168 /* Number of NQs */ 169 u16 nq_nr_rings; 170 171 /* Aux device resources */ 172 u16 aux_num_msix; 173 u16 aux_num_stat_ctxs; 174 175 u16 max_mtu; 176 #define BNGE_MAX_MTU 9500 177 178 u16 hw_ring_stats_size; 179 #define BNGE_NUM_RX_RING_STATS 8 180 #define BNGE_NUM_TX_RING_STATS 8 181 #define BNGE_NUM_TPA_RING_STATS 6 182 #define BNGE_RING_STATS_SIZE \ 183 ((BNGE_NUM_RX_RING_STATS + BNGE_NUM_TX_RING_STATS + \ 184 BNGE_NUM_TPA_RING_STATS) * 8) 185 186 u16 max_tpa_v2; 187 #define BNGE_SUPPORTS_TPA(bd) ((bd)->max_tpa_v2) 188 189 u8 num_tc; 190 u8 max_tc; 191 u8 max_lltc; /* lossless TCs */ 192 struct bnge_queue_info q_info[BNGE_MAX_QUEUE]; 193 u8 tc_to_qidx[BNGE_MAX_QUEUE]; 194 u8 q_ids[BNGE_MAX_QUEUE]; 195 u8 max_q; 196 u8 port_count; 197 198 struct bnge_irq *irq_tbl; 199 u16 irqs_acquired; 200 }; 201 202 static inline bool bnge_is_roce_en(struct bnge_dev *bd) 203 { 204 return bd->flags & BNGE_EN_ROCE; 205 } 206 207 static inline bool bnge_is_agg_reqd(struct bnge_dev *bd) 208 { 209 if (bd->netdev) { 210 struct bnge_net *bn = netdev_priv(bd->netdev); 211 212 if (bn->priv_flags & BNGE_NET_EN_TPA || 213 bn->priv_flags & BNGE_NET_EN_JUMBO) 214 return true; 215 else 216 return false; 217 } 218 219 return true; 220 } 221 222 static inline void bnge_writeq(struct bnge_dev *bd, u64 val, 223 void __iomem *addr) 224 { 225 #if BITS_PER_LONG == 32 226 spin_lock(&bd->db_lock); 227 lo_hi_writeq(val, addr); 228 spin_unlock(&bd->db_lock); 229 #else 230 writeq(val, addr); 231 #endif 232 } 233 234 /* For TX and RX ring doorbells */ 235 static inline void bnge_db_write(struct bnge_dev *bd, struct bnge_db_info *db, 236 u32 idx) 237 { 238 bnge_writeq(bd, db->db_key64 | DB_RING_IDX(db, idx), 239 db->doorbell); 240 } 241 242 bool bnge_aux_registered(struct bnge_dev *bd); 243 u16 bnge_aux_get_msix(struct bnge_dev *bd); 244 245 #endif /* _BNGE_H_ */ 246