1 /* 2 * Driver for (BCM4706)? GBit MAC core on BCMA bus. 3 * 4 * Copyright (C) 2012 Rafał Miłecki <zajec5@gmail.com> 5 * 6 * Licensed under the GNU/GPL. See COPYING for details. 7 */ 8 9 #include "bgmac.h" 10 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/delay.h> 14 #include <linux/etherdevice.h> 15 #include <linux/mii.h> 16 #include <linux/phy.h> 17 #include <linux/phy_fixed.h> 18 #include <linux/interrupt.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/bcm47xx_nvram.h> 21 22 static const struct bcma_device_id bgmac_bcma_tbl[] = { 23 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_4706_MAC_GBIT, BCMA_ANY_REV, BCMA_ANY_CLASS), 24 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_MAC_GBIT, BCMA_ANY_REV, BCMA_ANY_CLASS), 25 {}, 26 }; 27 MODULE_DEVICE_TABLE(bcma, bgmac_bcma_tbl); 28 29 static inline bool bgmac_is_bcm4707_family(struct bgmac *bgmac) 30 { 31 switch (bgmac->core->bus->chipinfo.id) { 32 case BCMA_CHIP_ID_BCM4707: 33 case BCMA_CHIP_ID_BCM47094: 34 case BCMA_CHIP_ID_BCM53018: 35 return true; 36 default: 37 return false; 38 } 39 } 40 41 static bool bgmac_wait_value(struct bcma_device *core, u16 reg, u32 mask, 42 u32 value, int timeout) 43 { 44 u32 val; 45 int i; 46 47 for (i = 0; i < timeout / 10; i++) { 48 val = bcma_read32(core, reg); 49 if ((val & mask) == value) 50 return true; 51 udelay(10); 52 } 53 pr_err("Timeout waiting for reg 0x%X\n", reg); 54 return false; 55 } 56 57 /************************************************** 58 * DMA 59 **************************************************/ 60 61 static void bgmac_dma_tx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring) 62 { 63 u32 val; 64 int i; 65 66 if (!ring->mmio_base) 67 return; 68 69 /* Suspend DMA TX ring first. 70 * bgmac_wait_value doesn't support waiting for any of few values, so 71 * implement whole loop here. 72 */ 73 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 74 BGMAC_DMA_TX_SUSPEND); 75 for (i = 0; i < 10000 / 10; i++) { 76 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS); 77 val &= BGMAC_DMA_TX_STAT; 78 if (val == BGMAC_DMA_TX_STAT_DISABLED || 79 val == BGMAC_DMA_TX_STAT_IDLEWAIT || 80 val == BGMAC_DMA_TX_STAT_STOPPED) { 81 i = 0; 82 break; 83 } 84 udelay(10); 85 } 86 if (i) 87 bgmac_err(bgmac, "Timeout suspending DMA TX ring 0x%X (BGMAC_DMA_TX_STAT: 0x%08X)\n", 88 ring->mmio_base, val); 89 90 /* Remove SUSPEND bit */ 91 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 0); 92 if (!bgmac_wait_value(bgmac->core, 93 ring->mmio_base + BGMAC_DMA_TX_STATUS, 94 BGMAC_DMA_TX_STAT, BGMAC_DMA_TX_STAT_DISABLED, 95 10000)) { 96 bgmac_warn(bgmac, "DMA TX ring 0x%X wasn't disabled on time, waiting additional 300us\n", 97 ring->mmio_base); 98 udelay(300); 99 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS); 100 if ((val & BGMAC_DMA_TX_STAT) != BGMAC_DMA_TX_STAT_DISABLED) 101 bgmac_err(bgmac, "Reset of DMA TX ring 0x%X failed\n", 102 ring->mmio_base); 103 } 104 } 105 106 static void bgmac_dma_tx_enable(struct bgmac *bgmac, 107 struct bgmac_dma_ring *ring) 108 { 109 u32 ctl; 110 111 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL); 112 if (bgmac->core->id.rev >= 4) { 113 ctl &= ~BGMAC_DMA_TX_BL_MASK; 114 ctl |= BGMAC_DMA_TX_BL_128 << BGMAC_DMA_TX_BL_SHIFT; 115 116 ctl &= ~BGMAC_DMA_TX_MR_MASK; 117 ctl |= BGMAC_DMA_TX_MR_2 << BGMAC_DMA_TX_MR_SHIFT; 118 119 ctl &= ~BGMAC_DMA_TX_PC_MASK; 120 ctl |= BGMAC_DMA_TX_PC_16 << BGMAC_DMA_TX_PC_SHIFT; 121 122 ctl &= ~BGMAC_DMA_TX_PT_MASK; 123 ctl |= BGMAC_DMA_TX_PT_8 << BGMAC_DMA_TX_PT_SHIFT; 124 } 125 ctl |= BGMAC_DMA_TX_ENABLE; 126 ctl |= BGMAC_DMA_TX_PARITY_DISABLE; 127 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl); 128 } 129 130 static void 131 bgmac_dma_tx_add_buf(struct bgmac *bgmac, struct bgmac_dma_ring *ring, 132 int i, int len, u32 ctl0) 133 { 134 struct bgmac_slot_info *slot; 135 struct bgmac_dma_desc *dma_desc; 136 u32 ctl1; 137 138 if (i == BGMAC_TX_RING_SLOTS - 1) 139 ctl0 |= BGMAC_DESC_CTL0_EOT; 140 141 ctl1 = len & BGMAC_DESC_CTL1_LEN; 142 143 slot = &ring->slots[i]; 144 dma_desc = &ring->cpu_base[i]; 145 dma_desc->addr_low = cpu_to_le32(lower_32_bits(slot->dma_addr)); 146 dma_desc->addr_high = cpu_to_le32(upper_32_bits(slot->dma_addr)); 147 dma_desc->ctl0 = cpu_to_le32(ctl0); 148 dma_desc->ctl1 = cpu_to_le32(ctl1); 149 } 150 151 static netdev_tx_t bgmac_dma_tx_add(struct bgmac *bgmac, 152 struct bgmac_dma_ring *ring, 153 struct sk_buff *skb) 154 { 155 struct device *dma_dev = bgmac->core->dma_dev; 156 struct net_device *net_dev = bgmac->net_dev; 157 int index = ring->end % BGMAC_TX_RING_SLOTS; 158 struct bgmac_slot_info *slot = &ring->slots[index]; 159 int nr_frags; 160 u32 flags; 161 int i; 162 163 if (skb->len > BGMAC_DESC_CTL1_LEN) { 164 bgmac_err(bgmac, "Too long skb (%d)\n", skb->len); 165 goto err_drop; 166 } 167 168 if (skb->ip_summed == CHECKSUM_PARTIAL) 169 skb_checksum_help(skb); 170 171 nr_frags = skb_shinfo(skb)->nr_frags; 172 173 /* ring->end - ring->start will return the number of valid slots, 174 * even when ring->end overflows 175 */ 176 if (ring->end - ring->start + nr_frags + 1 >= BGMAC_TX_RING_SLOTS) { 177 bgmac_err(bgmac, "TX ring is full, queue should be stopped!\n"); 178 netif_stop_queue(net_dev); 179 return NETDEV_TX_BUSY; 180 } 181 182 slot->dma_addr = dma_map_single(dma_dev, skb->data, skb_headlen(skb), 183 DMA_TO_DEVICE); 184 if (unlikely(dma_mapping_error(dma_dev, slot->dma_addr))) 185 goto err_dma_head; 186 187 flags = BGMAC_DESC_CTL0_SOF; 188 if (!nr_frags) 189 flags |= BGMAC_DESC_CTL0_EOF | BGMAC_DESC_CTL0_IOC; 190 191 bgmac_dma_tx_add_buf(bgmac, ring, index, skb_headlen(skb), flags); 192 flags = 0; 193 194 for (i = 0; i < nr_frags; i++) { 195 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i]; 196 int len = skb_frag_size(frag); 197 198 index = (index + 1) % BGMAC_TX_RING_SLOTS; 199 slot = &ring->slots[index]; 200 slot->dma_addr = skb_frag_dma_map(dma_dev, frag, 0, 201 len, DMA_TO_DEVICE); 202 if (unlikely(dma_mapping_error(dma_dev, slot->dma_addr))) 203 goto err_dma; 204 205 if (i == nr_frags - 1) 206 flags |= BGMAC_DESC_CTL0_EOF | BGMAC_DESC_CTL0_IOC; 207 208 bgmac_dma_tx_add_buf(bgmac, ring, index, len, flags); 209 } 210 211 slot->skb = skb; 212 ring->end += nr_frags + 1; 213 netdev_sent_queue(net_dev, skb->len); 214 215 wmb(); 216 217 /* Increase ring->end to point empty slot. We tell hardware the first 218 * slot it should *not* read. 219 */ 220 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_INDEX, 221 ring->index_base + 222 (ring->end % BGMAC_TX_RING_SLOTS) * 223 sizeof(struct bgmac_dma_desc)); 224 225 if (ring->end - ring->start >= BGMAC_TX_RING_SLOTS - 8) 226 netif_stop_queue(net_dev); 227 228 return NETDEV_TX_OK; 229 230 err_dma: 231 dma_unmap_single(dma_dev, slot->dma_addr, skb_headlen(skb), 232 DMA_TO_DEVICE); 233 234 while (i > 0) { 235 int index = (ring->end + i) % BGMAC_TX_RING_SLOTS; 236 struct bgmac_slot_info *slot = &ring->slots[index]; 237 u32 ctl1 = le32_to_cpu(ring->cpu_base[index].ctl1); 238 int len = ctl1 & BGMAC_DESC_CTL1_LEN; 239 240 dma_unmap_page(dma_dev, slot->dma_addr, len, DMA_TO_DEVICE); 241 } 242 243 err_dma_head: 244 bgmac_err(bgmac, "Mapping error of skb on ring 0x%X\n", 245 ring->mmio_base); 246 247 err_drop: 248 dev_kfree_skb(skb); 249 net_dev->stats.tx_dropped++; 250 net_dev->stats.tx_errors++; 251 return NETDEV_TX_OK; 252 } 253 254 /* Free transmitted packets */ 255 static void bgmac_dma_tx_free(struct bgmac *bgmac, struct bgmac_dma_ring *ring) 256 { 257 struct device *dma_dev = bgmac->core->dma_dev; 258 int empty_slot; 259 bool freed = false; 260 unsigned bytes_compl = 0, pkts_compl = 0; 261 262 /* The last slot that hardware didn't consume yet */ 263 empty_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS); 264 empty_slot &= BGMAC_DMA_TX_STATDPTR; 265 empty_slot -= ring->index_base; 266 empty_slot &= BGMAC_DMA_TX_STATDPTR; 267 empty_slot /= sizeof(struct bgmac_dma_desc); 268 269 while (ring->start != ring->end) { 270 int slot_idx = ring->start % BGMAC_TX_RING_SLOTS; 271 struct bgmac_slot_info *slot = &ring->slots[slot_idx]; 272 u32 ctl1; 273 int len; 274 275 if (slot_idx == empty_slot) 276 break; 277 278 ctl1 = le32_to_cpu(ring->cpu_base[slot_idx].ctl1); 279 len = ctl1 & BGMAC_DESC_CTL1_LEN; 280 if (ctl1 & BGMAC_DESC_CTL0_SOF) 281 /* Unmap no longer used buffer */ 282 dma_unmap_single(dma_dev, slot->dma_addr, len, 283 DMA_TO_DEVICE); 284 else 285 dma_unmap_page(dma_dev, slot->dma_addr, len, 286 DMA_TO_DEVICE); 287 288 if (slot->skb) { 289 bgmac->net_dev->stats.tx_bytes += slot->skb->len; 290 bgmac->net_dev->stats.tx_packets++; 291 bytes_compl += slot->skb->len; 292 pkts_compl++; 293 294 /* Free memory! :) */ 295 dev_kfree_skb(slot->skb); 296 slot->skb = NULL; 297 } 298 299 slot->dma_addr = 0; 300 ring->start++; 301 freed = true; 302 } 303 304 if (!pkts_compl) 305 return; 306 307 netdev_completed_queue(bgmac->net_dev, pkts_compl, bytes_compl); 308 309 if (netif_queue_stopped(bgmac->net_dev)) 310 netif_wake_queue(bgmac->net_dev); 311 } 312 313 static void bgmac_dma_rx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring) 314 { 315 if (!ring->mmio_base) 316 return; 317 318 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, 0); 319 if (!bgmac_wait_value(bgmac->core, 320 ring->mmio_base + BGMAC_DMA_RX_STATUS, 321 BGMAC_DMA_RX_STAT, BGMAC_DMA_RX_STAT_DISABLED, 322 10000)) 323 bgmac_err(bgmac, "Reset of ring 0x%X RX failed\n", 324 ring->mmio_base); 325 } 326 327 static void bgmac_dma_rx_enable(struct bgmac *bgmac, 328 struct bgmac_dma_ring *ring) 329 { 330 u32 ctl; 331 332 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL); 333 if (bgmac->core->id.rev >= 4) { 334 ctl &= ~BGMAC_DMA_RX_BL_MASK; 335 ctl |= BGMAC_DMA_RX_BL_128 << BGMAC_DMA_RX_BL_SHIFT; 336 337 ctl &= ~BGMAC_DMA_RX_PC_MASK; 338 ctl |= BGMAC_DMA_RX_PC_8 << BGMAC_DMA_RX_PC_SHIFT; 339 340 ctl &= ~BGMAC_DMA_RX_PT_MASK; 341 ctl |= BGMAC_DMA_RX_PT_1 << BGMAC_DMA_RX_PT_SHIFT; 342 } 343 ctl &= BGMAC_DMA_RX_ADDREXT_MASK; 344 ctl |= BGMAC_DMA_RX_ENABLE; 345 ctl |= BGMAC_DMA_RX_PARITY_DISABLE; 346 ctl |= BGMAC_DMA_RX_OVERFLOW_CONT; 347 ctl |= BGMAC_RX_FRAME_OFFSET << BGMAC_DMA_RX_FRAME_OFFSET_SHIFT; 348 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, ctl); 349 } 350 351 static int bgmac_dma_rx_skb_for_slot(struct bgmac *bgmac, 352 struct bgmac_slot_info *slot) 353 { 354 struct device *dma_dev = bgmac->core->dma_dev; 355 dma_addr_t dma_addr; 356 struct bgmac_rx_header *rx; 357 void *buf; 358 359 /* Alloc skb */ 360 buf = netdev_alloc_frag(BGMAC_RX_ALLOC_SIZE); 361 if (!buf) 362 return -ENOMEM; 363 364 /* Poison - if everything goes fine, hardware will overwrite it */ 365 rx = buf + BGMAC_RX_BUF_OFFSET; 366 rx->len = cpu_to_le16(0xdead); 367 rx->flags = cpu_to_le16(0xbeef); 368 369 /* Map skb for the DMA */ 370 dma_addr = dma_map_single(dma_dev, buf + BGMAC_RX_BUF_OFFSET, 371 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE); 372 if (dma_mapping_error(dma_dev, dma_addr)) { 373 bgmac_err(bgmac, "DMA mapping error\n"); 374 put_page(virt_to_head_page(buf)); 375 return -ENOMEM; 376 } 377 378 /* Update the slot */ 379 slot->buf = buf; 380 slot->dma_addr = dma_addr; 381 382 return 0; 383 } 384 385 static void bgmac_dma_rx_update_index(struct bgmac *bgmac, 386 struct bgmac_dma_ring *ring) 387 { 388 dma_wmb(); 389 390 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_INDEX, 391 ring->index_base + 392 ring->end * sizeof(struct bgmac_dma_desc)); 393 } 394 395 static void bgmac_dma_rx_setup_desc(struct bgmac *bgmac, 396 struct bgmac_dma_ring *ring, int desc_idx) 397 { 398 struct bgmac_dma_desc *dma_desc = ring->cpu_base + desc_idx; 399 u32 ctl0 = 0, ctl1 = 0; 400 401 if (desc_idx == BGMAC_RX_RING_SLOTS - 1) 402 ctl0 |= BGMAC_DESC_CTL0_EOT; 403 ctl1 |= BGMAC_RX_BUF_SIZE & BGMAC_DESC_CTL1_LEN; 404 /* Is there any BGMAC device that requires extension? */ 405 /* ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT) & 406 * B43_DMA64_DCTL1_ADDREXT_MASK; 407 */ 408 409 dma_desc->addr_low = cpu_to_le32(lower_32_bits(ring->slots[desc_idx].dma_addr)); 410 dma_desc->addr_high = cpu_to_le32(upper_32_bits(ring->slots[desc_idx].dma_addr)); 411 dma_desc->ctl0 = cpu_to_le32(ctl0); 412 dma_desc->ctl1 = cpu_to_le32(ctl1); 413 414 ring->end = desc_idx; 415 } 416 417 static void bgmac_dma_rx_poison_buf(struct device *dma_dev, 418 struct bgmac_slot_info *slot) 419 { 420 struct bgmac_rx_header *rx = slot->buf + BGMAC_RX_BUF_OFFSET; 421 422 dma_sync_single_for_cpu(dma_dev, slot->dma_addr, BGMAC_RX_BUF_SIZE, 423 DMA_FROM_DEVICE); 424 rx->len = cpu_to_le16(0xdead); 425 rx->flags = cpu_to_le16(0xbeef); 426 dma_sync_single_for_device(dma_dev, slot->dma_addr, BGMAC_RX_BUF_SIZE, 427 DMA_FROM_DEVICE); 428 } 429 430 static int bgmac_dma_rx_read(struct bgmac *bgmac, struct bgmac_dma_ring *ring, 431 int weight) 432 { 433 u32 end_slot; 434 int handled = 0; 435 436 end_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_STATUS); 437 end_slot &= BGMAC_DMA_RX_STATDPTR; 438 end_slot -= ring->index_base; 439 end_slot &= BGMAC_DMA_RX_STATDPTR; 440 end_slot /= sizeof(struct bgmac_dma_desc); 441 442 while (ring->start != end_slot) { 443 struct device *dma_dev = bgmac->core->dma_dev; 444 struct bgmac_slot_info *slot = &ring->slots[ring->start]; 445 struct bgmac_rx_header *rx = slot->buf + BGMAC_RX_BUF_OFFSET; 446 struct sk_buff *skb; 447 void *buf = slot->buf; 448 dma_addr_t dma_addr = slot->dma_addr; 449 u16 len, flags; 450 451 do { 452 /* Prepare new skb as replacement */ 453 if (bgmac_dma_rx_skb_for_slot(bgmac, slot)) { 454 bgmac_dma_rx_poison_buf(dma_dev, slot); 455 break; 456 } 457 458 /* Unmap buffer to make it accessible to the CPU */ 459 dma_unmap_single(dma_dev, dma_addr, 460 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE); 461 462 /* Get info from the header */ 463 len = le16_to_cpu(rx->len); 464 flags = le16_to_cpu(rx->flags); 465 466 /* Check for poison and drop or pass the packet */ 467 if (len == 0xdead && flags == 0xbeef) { 468 bgmac_err(bgmac, "Found poisoned packet at slot %d, DMA issue!\n", 469 ring->start); 470 put_page(virt_to_head_page(buf)); 471 bgmac->net_dev->stats.rx_errors++; 472 break; 473 } 474 475 if (len > BGMAC_RX_ALLOC_SIZE) { 476 bgmac_err(bgmac, "Found oversized packet at slot %d, DMA issue!\n", 477 ring->start); 478 put_page(virt_to_head_page(buf)); 479 bgmac->net_dev->stats.rx_length_errors++; 480 bgmac->net_dev->stats.rx_errors++; 481 break; 482 } 483 484 /* Omit CRC. */ 485 len -= ETH_FCS_LEN; 486 487 skb = build_skb(buf, BGMAC_RX_ALLOC_SIZE); 488 if (unlikely(!skb)) { 489 bgmac_err(bgmac, "build_skb failed\n"); 490 put_page(virt_to_head_page(buf)); 491 bgmac->net_dev->stats.rx_errors++; 492 break; 493 } 494 skb_put(skb, BGMAC_RX_FRAME_OFFSET + 495 BGMAC_RX_BUF_OFFSET + len); 496 skb_pull(skb, BGMAC_RX_FRAME_OFFSET + 497 BGMAC_RX_BUF_OFFSET); 498 499 skb_checksum_none_assert(skb); 500 skb->protocol = eth_type_trans(skb, bgmac->net_dev); 501 bgmac->net_dev->stats.rx_bytes += len; 502 bgmac->net_dev->stats.rx_packets++; 503 napi_gro_receive(&bgmac->napi, skb); 504 handled++; 505 } while (0); 506 507 bgmac_dma_rx_setup_desc(bgmac, ring, ring->start); 508 509 if (++ring->start >= BGMAC_RX_RING_SLOTS) 510 ring->start = 0; 511 512 if (handled >= weight) /* Should never be greater */ 513 break; 514 } 515 516 bgmac_dma_rx_update_index(bgmac, ring); 517 518 return handled; 519 } 520 521 /* Does ring support unaligned addressing? */ 522 static bool bgmac_dma_unaligned(struct bgmac *bgmac, 523 struct bgmac_dma_ring *ring, 524 enum bgmac_dma_ring_type ring_type) 525 { 526 switch (ring_type) { 527 case BGMAC_DMA_RING_TX: 528 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO, 529 0xff0); 530 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO)) 531 return true; 532 break; 533 case BGMAC_DMA_RING_RX: 534 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO, 535 0xff0); 536 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO)) 537 return true; 538 break; 539 } 540 return false; 541 } 542 543 static void bgmac_dma_tx_ring_free(struct bgmac *bgmac, 544 struct bgmac_dma_ring *ring) 545 { 546 struct device *dma_dev = bgmac->core->dma_dev; 547 struct bgmac_dma_desc *dma_desc = ring->cpu_base; 548 struct bgmac_slot_info *slot; 549 int i; 550 551 for (i = 0; i < BGMAC_TX_RING_SLOTS; i++) { 552 int len = dma_desc[i].ctl1 & BGMAC_DESC_CTL1_LEN; 553 554 slot = &ring->slots[i]; 555 dev_kfree_skb(slot->skb); 556 557 if (!slot->dma_addr) 558 continue; 559 560 if (slot->skb) 561 dma_unmap_single(dma_dev, slot->dma_addr, 562 len, DMA_TO_DEVICE); 563 else 564 dma_unmap_page(dma_dev, slot->dma_addr, 565 len, DMA_TO_DEVICE); 566 } 567 } 568 569 static void bgmac_dma_rx_ring_free(struct bgmac *bgmac, 570 struct bgmac_dma_ring *ring) 571 { 572 struct device *dma_dev = bgmac->core->dma_dev; 573 struct bgmac_slot_info *slot; 574 int i; 575 576 for (i = 0; i < BGMAC_RX_RING_SLOTS; i++) { 577 slot = &ring->slots[i]; 578 if (!slot->dma_addr) 579 continue; 580 581 dma_unmap_single(dma_dev, slot->dma_addr, 582 BGMAC_RX_BUF_SIZE, 583 DMA_FROM_DEVICE); 584 put_page(virt_to_head_page(slot->buf)); 585 slot->dma_addr = 0; 586 } 587 } 588 589 static void bgmac_dma_ring_desc_free(struct bgmac *bgmac, 590 struct bgmac_dma_ring *ring, 591 int num_slots) 592 { 593 struct device *dma_dev = bgmac->core->dma_dev; 594 int size; 595 596 if (!ring->cpu_base) 597 return; 598 599 /* Free ring of descriptors */ 600 size = num_slots * sizeof(struct bgmac_dma_desc); 601 dma_free_coherent(dma_dev, size, ring->cpu_base, 602 ring->dma_base); 603 } 604 605 static void bgmac_dma_cleanup(struct bgmac *bgmac) 606 { 607 int i; 608 609 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) 610 bgmac_dma_tx_ring_free(bgmac, &bgmac->tx_ring[i]); 611 612 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) 613 bgmac_dma_rx_ring_free(bgmac, &bgmac->rx_ring[i]); 614 } 615 616 static void bgmac_dma_free(struct bgmac *bgmac) 617 { 618 int i; 619 620 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) 621 bgmac_dma_ring_desc_free(bgmac, &bgmac->tx_ring[i], 622 BGMAC_TX_RING_SLOTS); 623 624 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) 625 bgmac_dma_ring_desc_free(bgmac, &bgmac->rx_ring[i], 626 BGMAC_RX_RING_SLOTS); 627 } 628 629 static int bgmac_dma_alloc(struct bgmac *bgmac) 630 { 631 struct device *dma_dev = bgmac->core->dma_dev; 632 struct bgmac_dma_ring *ring; 633 static const u16 ring_base[] = { BGMAC_DMA_BASE0, BGMAC_DMA_BASE1, 634 BGMAC_DMA_BASE2, BGMAC_DMA_BASE3, }; 635 int size; /* ring size: different for Tx and Rx */ 636 int err; 637 int i; 638 639 BUILD_BUG_ON(BGMAC_MAX_TX_RINGS > ARRAY_SIZE(ring_base)); 640 BUILD_BUG_ON(BGMAC_MAX_RX_RINGS > ARRAY_SIZE(ring_base)); 641 642 if (!(bcma_aread32(bgmac->core, BCMA_IOST) & BCMA_IOST_DMA64)) { 643 bgmac_err(bgmac, "Core does not report 64-bit DMA\n"); 644 return -ENOTSUPP; 645 } 646 647 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) { 648 ring = &bgmac->tx_ring[i]; 649 ring->mmio_base = ring_base[i]; 650 651 /* Alloc ring of descriptors */ 652 size = BGMAC_TX_RING_SLOTS * sizeof(struct bgmac_dma_desc); 653 ring->cpu_base = dma_zalloc_coherent(dma_dev, size, 654 &ring->dma_base, 655 GFP_KERNEL); 656 if (!ring->cpu_base) { 657 bgmac_err(bgmac, "Allocation of TX ring 0x%X failed\n", 658 ring->mmio_base); 659 goto err_dma_free; 660 } 661 662 ring->unaligned = bgmac_dma_unaligned(bgmac, ring, 663 BGMAC_DMA_RING_TX); 664 if (ring->unaligned) 665 ring->index_base = lower_32_bits(ring->dma_base); 666 else 667 ring->index_base = 0; 668 669 /* No need to alloc TX slots yet */ 670 } 671 672 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) { 673 ring = &bgmac->rx_ring[i]; 674 ring->mmio_base = ring_base[i]; 675 676 /* Alloc ring of descriptors */ 677 size = BGMAC_RX_RING_SLOTS * sizeof(struct bgmac_dma_desc); 678 ring->cpu_base = dma_zalloc_coherent(dma_dev, size, 679 &ring->dma_base, 680 GFP_KERNEL); 681 if (!ring->cpu_base) { 682 bgmac_err(bgmac, "Allocation of RX ring 0x%X failed\n", 683 ring->mmio_base); 684 err = -ENOMEM; 685 goto err_dma_free; 686 } 687 688 ring->unaligned = bgmac_dma_unaligned(bgmac, ring, 689 BGMAC_DMA_RING_RX); 690 if (ring->unaligned) 691 ring->index_base = lower_32_bits(ring->dma_base); 692 else 693 ring->index_base = 0; 694 } 695 696 return 0; 697 698 err_dma_free: 699 bgmac_dma_free(bgmac); 700 return -ENOMEM; 701 } 702 703 static int bgmac_dma_init(struct bgmac *bgmac) 704 { 705 struct bgmac_dma_ring *ring; 706 int i, err; 707 708 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) { 709 ring = &bgmac->tx_ring[i]; 710 711 if (!ring->unaligned) 712 bgmac_dma_tx_enable(bgmac, ring); 713 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO, 714 lower_32_bits(ring->dma_base)); 715 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGHI, 716 upper_32_bits(ring->dma_base)); 717 if (ring->unaligned) 718 bgmac_dma_tx_enable(bgmac, ring); 719 720 ring->start = 0; 721 ring->end = 0; /* Points the slot that should *not* be read */ 722 } 723 724 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) { 725 int j; 726 727 ring = &bgmac->rx_ring[i]; 728 729 if (!ring->unaligned) 730 bgmac_dma_rx_enable(bgmac, ring); 731 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO, 732 lower_32_bits(ring->dma_base)); 733 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGHI, 734 upper_32_bits(ring->dma_base)); 735 if (ring->unaligned) 736 bgmac_dma_rx_enable(bgmac, ring); 737 738 ring->start = 0; 739 ring->end = 0; 740 for (j = 0; j < BGMAC_RX_RING_SLOTS; j++) { 741 err = bgmac_dma_rx_skb_for_slot(bgmac, &ring->slots[j]); 742 if (err) 743 goto error; 744 745 bgmac_dma_rx_setup_desc(bgmac, ring, j); 746 } 747 748 bgmac_dma_rx_update_index(bgmac, ring); 749 } 750 751 return 0; 752 753 error: 754 bgmac_dma_cleanup(bgmac); 755 return err; 756 } 757 758 /************************************************** 759 * PHY ops 760 **************************************************/ 761 762 static u16 bgmac_phy_read(struct bgmac *bgmac, u8 phyaddr, u8 reg) 763 { 764 struct bcma_device *core; 765 u16 phy_access_addr; 766 u16 phy_ctl_addr; 767 u32 tmp; 768 769 BUILD_BUG_ON(BGMAC_PA_DATA_MASK != BCMA_GMAC_CMN_PA_DATA_MASK); 770 BUILD_BUG_ON(BGMAC_PA_ADDR_MASK != BCMA_GMAC_CMN_PA_ADDR_MASK); 771 BUILD_BUG_ON(BGMAC_PA_ADDR_SHIFT != BCMA_GMAC_CMN_PA_ADDR_SHIFT); 772 BUILD_BUG_ON(BGMAC_PA_REG_MASK != BCMA_GMAC_CMN_PA_REG_MASK); 773 BUILD_BUG_ON(BGMAC_PA_REG_SHIFT != BCMA_GMAC_CMN_PA_REG_SHIFT); 774 BUILD_BUG_ON(BGMAC_PA_WRITE != BCMA_GMAC_CMN_PA_WRITE); 775 BUILD_BUG_ON(BGMAC_PA_START != BCMA_GMAC_CMN_PA_START); 776 BUILD_BUG_ON(BGMAC_PC_EPA_MASK != BCMA_GMAC_CMN_PC_EPA_MASK); 777 BUILD_BUG_ON(BGMAC_PC_MCT_MASK != BCMA_GMAC_CMN_PC_MCT_MASK); 778 BUILD_BUG_ON(BGMAC_PC_MCT_SHIFT != BCMA_GMAC_CMN_PC_MCT_SHIFT); 779 BUILD_BUG_ON(BGMAC_PC_MTE != BCMA_GMAC_CMN_PC_MTE); 780 781 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) { 782 core = bgmac->core->bus->drv_gmac_cmn.core; 783 phy_access_addr = BCMA_GMAC_CMN_PHY_ACCESS; 784 phy_ctl_addr = BCMA_GMAC_CMN_PHY_CTL; 785 } else { 786 core = bgmac->core; 787 phy_access_addr = BGMAC_PHY_ACCESS; 788 phy_ctl_addr = BGMAC_PHY_CNTL; 789 } 790 791 tmp = bcma_read32(core, phy_ctl_addr); 792 tmp &= ~BGMAC_PC_EPA_MASK; 793 tmp |= phyaddr; 794 bcma_write32(core, phy_ctl_addr, tmp); 795 796 tmp = BGMAC_PA_START; 797 tmp |= phyaddr << BGMAC_PA_ADDR_SHIFT; 798 tmp |= reg << BGMAC_PA_REG_SHIFT; 799 bcma_write32(core, phy_access_addr, tmp); 800 801 if (!bgmac_wait_value(core, phy_access_addr, BGMAC_PA_START, 0, 1000)) { 802 bgmac_err(bgmac, "Reading PHY %d register 0x%X failed\n", 803 phyaddr, reg); 804 return 0xffff; 805 } 806 807 return bcma_read32(core, phy_access_addr) & BGMAC_PA_DATA_MASK; 808 } 809 810 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphywr */ 811 static int bgmac_phy_write(struct bgmac *bgmac, u8 phyaddr, u8 reg, u16 value) 812 { 813 struct bcma_device *core; 814 u16 phy_access_addr; 815 u16 phy_ctl_addr; 816 u32 tmp; 817 818 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) { 819 core = bgmac->core->bus->drv_gmac_cmn.core; 820 phy_access_addr = BCMA_GMAC_CMN_PHY_ACCESS; 821 phy_ctl_addr = BCMA_GMAC_CMN_PHY_CTL; 822 } else { 823 core = bgmac->core; 824 phy_access_addr = BGMAC_PHY_ACCESS; 825 phy_ctl_addr = BGMAC_PHY_CNTL; 826 } 827 828 tmp = bcma_read32(core, phy_ctl_addr); 829 tmp &= ~BGMAC_PC_EPA_MASK; 830 tmp |= phyaddr; 831 bcma_write32(core, phy_ctl_addr, tmp); 832 833 bgmac_write(bgmac, BGMAC_INT_STATUS, BGMAC_IS_MDIO); 834 if (bgmac_read(bgmac, BGMAC_INT_STATUS) & BGMAC_IS_MDIO) 835 bgmac_warn(bgmac, "Error setting MDIO int\n"); 836 837 tmp = BGMAC_PA_START; 838 tmp |= BGMAC_PA_WRITE; 839 tmp |= phyaddr << BGMAC_PA_ADDR_SHIFT; 840 tmp |= reg << BGMAC_PA_REG_SHIFT; 841 tmp |= value; 842 bcma_write32(core, phy_access_addr, tmp); 843 844 if (!bgmac_wait_value(core, phy_access_addr, BGMAC_PA_START, 0, 1000)) { 845 bgmac_err(bgmac, "Writing to PHY %d register 0x%X failed\n", 846 phyaddr, reg); 847 return -ETIMEDOUT; 848 } 849 850 return 0; 851 } 852 853 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyinit */ 854 static void bgmac_phy_init(struct bgmac *bgmac) 855 { 856 struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo; 857 struct bcma_drv_cc *cc = &bgmac->core->bus->drv_cc; 858 u8 i; 859 860 if (ci->id == BCMA_CHIP_ID_BCM5356) { 861 for (i = 0; i < 5; i++) { 862 bgmac_phy_write(bgmac, i, 0x1f, 0x008b); 863 bgmac_phy_write(bgmac, i, 0x15, 0x0100); 864 bgmac_phy_write(bgmac, i, 0x1f, 0x000f); 865 bgmac_phy_write(bgmac, i, 0x12, 0x2aaa); 866 bgmac_phy_write(bgmac, i, 0x1f, 0x000b); 867 } 868 } 869 if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg != 10) || 870 (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg != 10) || 871 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg != 9)) { 872 bcma_chipco_chipctl_maskset(cc, 2, ~0xc0000000, 0); 873 bcma_chipco_chipctl_maskset(cc, 4, ~0x80000000, 0); 874 for (i = 0; i < 5; i++) { 875 bgmac_phy_write(bgmac, i, 0x1f, 0x000f); 876 bgmac_phy_write(bgmac, i, 0x16, 0x5284); 877 bgmac_phy_write(bgmac, i, 0x1f, 0x000b); 878 bgmac_phy_write(bgmac, i, 0x17, 0x0010); 879 bgmac_phy_write(bgmac, i, 0x1f, 0x000f); 880 bgmac_phy_write(bgmac, i, 0x16, 0x5296); 881 bgmac_phy_write(bgmac, i, 0x17, 0x1073); 882 bgmac_phy_write(bgmac, i, 0x17, 0x9073); 883 bgmac_phy_write(bgmac, i, 0x16, 0x52b6); 884 bgmac_phy_write(bgmac, i, 0x17, 0x9273); 885 bgmac_phy_write(bgmac, i, 0x1f, 0x000b); 886 } 887 } 888 } 889 890 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyreset */ 891 static void bgmac_phy_reset(struct bgmac *bgmac) 892 { 893 if (bgmac->phyaddr == BGMAC_PHY_NOREGS) 894 return; 895 896 bgmac_phy_write(bgmac, bgmac->phyaddr, MII_BMCR, BMCR_RESET); 897 udelay(100); 898 if (bgmac_phy_read(bgmac, bgmac->phyaddr, MII_BMCR) & BMCR_RESET) 899 bgmac_err(bgmac, "PHY reset failed\n"); 900 bgmac_phy_init(bgmac); 901 } 902 903 /************************************************** 904 * Chip ops 905 **************************************************/ 906 907 /* TODO: can we just drop @force? Can we don't reset MAC at all if there is 908 * nothing to change? Try if after stabilizng driver. 909 */ 910 static void bgmac_cmdcfg_maskset(struct bgmac *bgmac, u32 mask, u32 set, 911 bool force) 912 { 913 u32 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG); 914 u32 new_val = (cmdcfg & mask) | set; 915 916 bgmac_set(bgmac, BGMAC_CMDCFG, BGMAC_CMDCFG_SR(bgmac->core->id.rev)); 917 udelay(2); 918 919 if (new_val != cmdcfg || force) 920 bgmac_write(bgmac, BGMAC_CMDCFG, new_val); 921 922 bgmac_mask(bgmac, BGMAC_CMDCFG, ~BGMAC_CMDCFG_SR(bgmac->core->id.rev)); 923 udelay(2); 924 } 925 926 static void bgmac_write_mac_address(struct bgmac *bgmac, u8 *addr) 927 { 928 u32 tmp; 929 930 tmp = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]; 931 bgmac_write(bgmac, BGMAC_MACADDR_HIGH, tmp); 932 tmp = (addr[4] << 8) | addr[5]; 933 bgmac_write(bgmac, BGMAC_MACADDR_LOW, tmp); 934 } 935 936 static void bgmac_set_rx_mode(struct net_device *net_dev) 937 { 938 struct bgmac *bgmac = netdev_priv(net_dev); 939 940 if (net_dev->flags & IFF_PROMISC) 941 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_PROM, true); 942 else 943 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_PROM, 0, true); 944 } 945 946 #if 0 /* We don't use that regs yet */ 947 static void bgmac_chip_stats_update(struct bgmac *bgmac) 948 { 949 int i; 950 951 if (bgmac->core->id.id != BCMA_CORE_4706_MAC_GBIT) { 952 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++) 953 bgmac->mib_tx_regs[i] = 954 bgmac_read(bgmac, 955 BGMAC_TX_GOOD_OCTETS + (i * 4)); 956 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++) 957 bgmac->mib_rx_regs[i] = 958 bgmac_read(bgmac, 959 BGMAC_RX_GOOD_OCTETS + (i * 4)); 960 } 961 962 /* TODO: what else? how to handle BCM4706? Specs are needed */ 963 } 964 #endif 965 966 static void bgmac_clear_mib(struct bgmac *bgmac) 967 { 968 int i; 969 970 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) 971 return; 972 973 bgmac_set(bgmac, BGMAC_DEV_CTL, BGMAC_DC_MROR); 974 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++) 975 bgmac_read(bgmac, BGMAC_TX_GOOD_OCTETS + (i * 4)); 976 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++) 977 bgmac_read(bgmac, BGMAC_RX_GOOD_OCTETS + (i * 4)); 978 } 979 980 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_speed */ 981 static void bgmac_mac_speed(struct bgmac *bgmac) 982 { 983 u32 mask = ~(BGMAC_CMDCFG_ES_MASK | BGMAC_CMDCFG_HD); 984 u32 set = 0; 985 986 switch (bgmac->mac_speed) { 987 case SPEED_10: 988 set |= BGMAC_CMDCFG_ES_10; 989 break; 990 case SPEED_100: 991 set |= BGMAC_CMDCFG_ES_100; 992 break; 993 case SPEED_1000: 994 set |= BGMAC_CMDCFG_ES_1000; 995 break; 996 case SPEED_2500: 997 set |= BGMAC_CMDCFG_ES_2500; 998 break; 999 default: 1000 bgmac_err(bgmac, "Unsupported speed: %d\n", bgmac->mac_speed); 1001 } 1002 1003 if (bgmac->mac_duplex == DUPLEX_HALF) 1004 set |= BGMAC_CMDCFG_HD; 1005 1006 bgmac_cmdcfg_maskset(bgmac, mask, set, true); 1007 } 1008 1009 static void bgmac_miiconfig(struct bgmac *bgmac) 1010 { 1011 struct bcma_device *core = bgmac->core; 1012 u8 imode; 1013 1014 if (bgmac_is_bcm4707_family(bgmac)) { 1015 bcma_awrite32(core, BCMA_IOCTL, 1016 bcma_aread32(core, BCMA_IOCTL) | 0x40 | 1017 BGMAC_BCMA_IOCTL_SW_CLKEN); 1018 bgmac->mac_speed = SPEED_2500; 1019 bgmac->mac_duplex = DUPLEX_FULL; 1020 bgmac_mac_speed(bgmac); 1021 } else { 1022 imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & 1023 BGMAC_DS_MM_MASK) >> BGMAC_DS_MM_SHIFT; 1024 if (imode == 0 || imode == 1) { 1025 bgmac->mac_speed = SPEED_100; 1026 bgmac->mac_duplex = DUPLEX_FULL; 1027 bgmac_mac_speed(bgmac); 1028 } 1029 } 1030 } 1031 1032 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipreset */ 1033 static void bgmac_chip_reset(struct bgmac *bgmac) 1034 { 1035 struct bcma_device *core = bgmac->core; 1036 struct bcma_bus *bus = core->bus; 1037 struct bcma_chipinfo *ci = &bus->chipinfo; 1038 u32 flags; 1039 u32 iost; 1040 int i; 1041 1042 if (bcma_core_is_enabled(core)) { 1043 if (!bgmac->stats_grabbed) { 1044 /* bgmac_chip_stats_update(bgmac); */ 1045 bgmac->stats_grabbed = true; 1046 } 1047 1048 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) 1049 bgmac_dma_tx_reset(bgmac, &bgmac->tx_ring[i]); 1050 1051 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false); 1052 udelay(1); 1053 1054 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) 1055 bgmac_dma_rx_reset(bgmac, &bgmac->rx_ring[i]); 1056 1057 /* TODO: Clear software multicast filter list */ 1058 } 1059 1060 iost = bcma_aread32(core, BCMA_IOST); 1061 if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM47186) || 1062 (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg == 10) || 1063 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == BCMA_PKG_ID_BCM47188)) 1064 iost &= ~BGMAC_BCMA_IOST_ATTACHED; 1065 1066 /* 3GMAC: for BCM4707 & BCM47094, only do core reset at bgmac_probe() */ 1067 if (ci->id != BCMA_CHIP_ID_BCM4707 && 1068 ci->id != BCMA_CHIP_ID_BCM47094) { 1069 flags = 0; 1070 if (iost & BGMAC_BCMA_IOST_ATTACHED) { 1071 flags = BGMAC_BCMA_IOCTL_SW_CLKEN; 1072 if (!bgmac->has_robosw) 1073 flags |= BGMAC_BCMA_IOCTL_SW_RESET; 1074 } 1075 bcma_core_enable(core, flags); 1076 } 1077 1078 /* Request Misc PLL for corerev > 2 */ 1079 if (core->id.rev > 2 && !bgmac_is_bcm4707_family(bgmac)) { 1080 bgmac_set(bgmac, BCMA_CLKCTLST, 1081 BGMAC_BCMA_CLKCTLST_MISC_PLL_REQ); 1082 bgmac_wait_value(bgmac->core, BCMA_CLKCTLST, 1083 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST, 1084 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST, 1085 1000); 1086 } 1087 1088 if (ci->id == BCMA_CHIP_ID_BCM5357 || 1089 ci->id == BCMA_CHIP_ID_BCM4749 || 1090 ci->id == BCMA_CHIP_ID_BCM53572) { 1091 struct bcma_drv_cc *cc = &bgmac->core->bus->drv_cc; 1092 u8 et_swtype = 0; 1093 u8 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHY | 1094 BGMAC_CHIPCTL_1_IF_TYPE_MII; 1095 char buf[4]; 1096 1097 if (bcm47xx_nvram_getenv("et_swtype", buf, sizeof(buf)) > 0) { 1098 if (kstrtou8(buf, 0, &et_swtype)) 1099 bgmac_err(bgmac, "Failed to parse et_swtype (%s)\n", 1100 buf); 1101 et_swtype &= 0x0f; 1102 et_swtype <<= 4; 1103 sw_type = et_swtype; 1104 } else if (ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM5358) { 1105 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII; 1106 } else if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM47186) || 1107 (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg == 10) || 1108 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == BCMA_PKG_ID_BCM47188)) { 1109 sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RGMII | 1110 BGMAC_CHIPCTL_1_SW_TYPE_RGMII; 1111 } 1112 bcma_chipco_chipctl_maskset(cc, 1, 1113 ~(BGMAC_CHIPCTL_1_IF_TYPE_MASK | 1114 BGMAC_CHIPCTL_1_SW_TYPE_MASK), 1115 sw_type); 1116 } 1117 1118 if (iost & BGMAC_BCMA_IOST_ATTACHED && !bgmac->has_robosw) 1119 bcma_awrite32(core, BCMA_IOCTL, 1120 bcma_aread32(core, BCMA_IOCTL) & 1121 ~BGMAC_BCMA_IOCTL_SW_RESET); 1122 1123 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_reset 1124 * Specs don't say about using BGMAC_CMDCFG_SR, but in this routine 1125 * BGMAC_CMDCFG is read _after_ putting chip in a reset. So it has to 1126 * be keps until taking MAC out of the reset. 1127 */ 1128 bgmac_cmdcfg_maskset(bgmac, 1129 ~(BGMAC_CMDCFG_TE | 1130 BGMAC_CMDCFG_RE | 1131 BGMAC_CMDCFG_RPI | 1132 BGMAC_CMDCFG_TAI | 1133 BGMAC_CMDCFG_HD | 1134 BGMAC_CMDCFG_ML | 1135 BGMAC_CMDCFG_CFE | 1136 BGMAC_CMDCFG_RL | 1137 BGMAC_CMDCFG_RED | 1138 BGMAC_CMDCFG_PE | 1139 BGMAC_CMDCFG_TPI | 1140 BGMAC_CMDCFG_PAD_EN | 1141 BGMAC_CMDCFG_PF), 1142 BGMAC_CMDCFG_PROM | 1143 BGMAC_CMDCFG_NLC | 1144 BGMAC_CMDCFG_CFE | 1145 BGMAC_CMDCFG_SR(core->id.rev), 1146 false); 1147 bgmac->mac_speed = SPEED_UNKNOWN; 1148 bgmac->mac_duplex = DUPLEX_UNKNOWN; 1149 1150 bgmac_clear_mib(bgmac); 1151 if (core->id.id == BCMA_CORE_4706_MAC_GBIT) 1152 bcma_maskset32(bgmac->cmn, BCMA_GMAC_CMN_PHY_CTL, ~0, 1153 BCMA_GMAC_CMN_PC_MTE); 1154 else 1155 bgmac_set(bgmac, BGMAC_PHY_CNTL, BGMAC_PC_MTE); 1156 bgmac_miiconfig(bgmac); 1157 bgmac_phy_init(bgmac); 1158 1159 netdev_reset_queue(bgmac->net_dev); 1160 } 1161 1162 static void bgmac_chip_intrs_on(struct bgmac *bgmac) 1163 { 1164 bgmac_write(bgmac, BGMAC_INT_MASK, bgmac->int_mask); 1165 } 1166 1167 static void bgmac_chip_intrs_off(struct bgmac *bgmac) 1168 { 1169 bgmac_write(bgmac, BGMAC_INT_MASK, 0); 1170 bgmac_read(bgmac, BGMAC_INT_MASK); 1171 } 1172 1173 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_enable */ 1174 static void bgmac_enable(struct bgmac *bgmac) 1175 { 1176 struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo; 1177 u32 cmdcfg; 1178 u32 mode; 1179 u32 rxq_ctl; 1180 u32 fl_ctl; 1181 u16 bp_clk; 1182 u8 mdp; 1183 1184 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG); 1185 bgmac_cmdcfg_maskset(bgmac, ~(BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE), 1186 BGMAC_CMDCFG_SR(bgmac->core->id.rev), true); 1187 udelay(2); 1188 cmdcfg |= BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE; 1189 bgmac_write(bgmac, BGMAC_CMDCFG, cmdcfg); 1190 1191 mode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >> 1192 BGMAC_DS_MM_SHIFT; 1193 if (ci->id != BCMA_CHIP_ID_BCM47162 || mode != 0) 1194 bgmac_set(bgmac, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT); 1195 if (ci->id == BCMA_CHIP_ID_BCM47162 && mode == 2) 1196 bcma_chipco_chipctl_maskset(&bgmac->core->bus->drv_cc, 1, ~0, 1197 BGMAC_CHIPCTL_1_RXC_DLL_BYPASS); 1198 1199 switch (ci->id) { 1200 case BCMA_CHIP_ID_BCM5357: 1201 case BCMA_CHIP_ID_BCM4749: 1202 case BCMA_CHIP_ID_BCM53572: 1203 case BCMA_CHIP_ID_BCM4716: 1204 case BCMA_CHIP_ID_BCM47162: 1205 fl_ctl = 0x03cb04cb; 1206 if (ci->id == BCMA_CHIP_ID_BCM5357 || 1207 ci->id == BCMA_CHIP_ID_BCM4749 || 1208 ci->id == BCMA_CHIP_ID_BCM53572) 1209 fl_ctl = 0x2300e1; 1210 bgmac_write(bgmac, BGMAC_FLOW_CTL_THRESH, fl_ctl); 1211 bgmac_write(bgmac, BGMAC_PAUSE_CTL, 0x27fff); 1212 break; 1213 } 1214 1215 if (!bgmac_is_bcm4707_family(bgmac)) { 1216 rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL); 1217 rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK; 1218 bp_clk = bcma_pmu_get_bus_clock(&bgmac->core->bus->drv_cc) / 1219 1000000; 1220 mdp = (bp_clk * 128 / 1000) - 3; 1221 rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT); 1222 bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl); 1223 } 1224 } 1225 1226 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */ 1227 static void bgmac_chip_init(struct bgmac *bgmac) 1228 { 1229 /* 1 interrupt per received frame */ 1230 bgmac_write(bgmac, BGMAC_INT_RECV_LAZY, 1 << BGMAC_IRL_FC_SHIFT); 1231 1232 /* Enable 802.3x tx flow control (honor received PAUSE frames) */ 1233 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_RPI, 0, true); 1234 1235 bgmac_set_rx_mode(bgmac->net_dev); 1236 1237 bgmac_write_mac_address(bgmac, bgmac->net_dev->dev_addr); 1238 1239 if (bgmac->loopback) 1240 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false); 1241 else 1242 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_ML, 0, false); 1243 1244 bgmac_write(bgmac, BGMAC_RXMAX_LENGTH, 32 + ETHER_MAX_LEN); 1245 1246 bgmac_chip_intrs_on(bgmac); 1247 1248 bgmac_enable(bgmac); 1249 } 1250 1251 static irqreturn_t bgmac_interrupt(int irq, void *dev_id) 1252 { 1253 struct bgmac *bgmac = netdev_priv(dev_id); 1254 1255 u32 int_status = bgmac_read(bgmac, BGMAC_INT_STATUS); 1256 int_status &= bgmac->int_mask; 1257 1258 if (!int_status) 1259 return IRQ_NONE; 1260 1261 int_status &= ~(BGMAC_IS_TX0 | BGMAC_IS_RX); 1262 if (int_status) 1263 bgmac_err(bgmac, "Unknown IRQs: 0x%08X\n", int_status); 1264 1265 /* Disable new interrupts until handling existing ones */ 1266 bgmac_chip_intrs_off(bgmac); 1267 1268 napi_schedule(&bgmac->napi); 1269 1270 return IRQ_HANDLED; 1271 } 1272 1273 static int bgmac_poll(struct napi_struct *napi, int weight) 1274 { 1275 struct bgmac *bgmac = container_of(napi, struct bgmac, napi); 1276 int handled = 0; 1277 1278 /* Ack */ 1279 bgmac_write(bgmac, BGMAC_INT_STATUS, ~0); 1280 1281 bgmac_dma_tx_free(bgmac, &bgmac->tx_ring[0]); 1282 handled += bgmac_dma_rx_read(bgmac, &bgmac->rx_ring[0], weight); 1283 1284 /* Poll again if more events arrived in the meantime */ 1285 if (bgmac_read(bgmac, BGMAC_INT_STATUS) & (BGMAC_IS_TX0 | BGMAC_IS_RX)) 1286 return weight; 1287 1288 if (handled < weight) { 1289 napi_complete(napi); 1290 bgmac_chip_intrs_on(bgmac); 1291 } 1292 1293 return handled; 1294 } 1295 1296 /************************************************** 1297 * net_device_ops 1298 **************************************************/ 1299 1300 static int bgmac_open(struct net_device *net_dev) 1301 { 1302 struct bgmac *bgmac = netdev_priv(net_dev); 1303 int err = 0; 1304 1305 bgmac_chip_reset(bgmac); 1306 1307 err = bgmac_dma_init(bgmac); 1308 if (err) 1309 return err; 1310 1311 /* Specs say about reclaiming rings here, but we do that in DMA init */ 1312 bgmac_chip_init(bgmac); 1313 1314 err = request_irq(bgmac->core->irq, bgmac_interrupt, IRQF_SHARED, 1315 KBUILD_MODNAME, net_dev); 1316 if (err < 0) { 1317 bgmac_err(bgmac, "IRQ request error: %d!\n", err); 1318 bgmac_dma_cleanup(bgmac); 1319 return err; 1320 } 1321 napi_enable(&bgmac->napi); 1322 1323 phy_start(bgmac->phy_dev); 1324 1325 netif_carrier_on(net_dev); 1326 return 0; 1327 } 1328 1329 static int bgmac_stop(struct net_device *net_dev) 1330 { 1331 struct bgmac *bgmac = netdev_priv(net_dev); 1332 1333 netif_carrier_off(net_dev); 1334 1335 phy_stop(bgmac->phy_dev); 1336 1337 napi_disable(&bgmac->napi); 1338 bgmac_chip_intrs_off(bgmac); 1339 free_irq(bgmac->core->irq, net_dev); 1340 1341 bgmac_chip_reset(bgmac); 1342 bgmac_dma_cleanup(bgmac); 1343 1344 return 0; 1345 } 1346 1347 static netdev_tx_t bgmac_start_xmit(struct sk_buff *skb, 1348 struct net_device *net_dev) 1349 { 1350 struct bgmac *bgmac = netdev_priv(net_dev); 1351 struct bgmac_dma_ring *ring; 1352 1353 /* No QOS support yet */ 1354 ring = &bgmac->tx_ring[0]; 1355 return bgmac_dma_tx_add(bgmac, ring, skb); 1356 } 1357 1358 static int bgmac_set_mac_address(struct net_device *net_dev, void *addr) 1359 { 1360 struct bgmac *bgmac = netdev_priv(net_dev); 1361 int ret; 1362 1363 ret = eth_prepare_mac_addr_change(net_dev, addr); 1364 if (ret < 0) 1365 return ret; 1366 bgmac_write_mac_address(bgmac, (u8 *)addr); 1367 eth_commit_mac_addr_change(net_dev, addr); 1368 return 0; 1369 } 1370 1371 static int bgmac_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) 1372 { 1373 struct bgmac *bgmac = netdev_priv(net_dev); 1374 1375 if (!netif_running(net_dev)) 1376 return -EINVAL; 1377 1378 return phy_mii_ioctl(bgmac->phy_dev, ifr, cmd); 1379 } 1380 1381 static const struct net_device_ops bgmac_netdev_ops = { 1382 .ndo_open = bgmac_open, 1383 .ndo_stop = bgmac_stop, 1384 .ndo_start_xmit = bgmac_start_xmit, 1385 .ndo_set_rx_mode = bgmac_set_rx_mode, 1386 .ndo_set_mac_address = bgmac_set_mac_address, 1387 .ndo_validate_addr = eth_validate_addr, 1388 .ndo_do_ioctl = bgmac_ioctl, 1389 }; 1390 1391 /************************************************** 1392 * ethtool_ops 1393 **************************************************/ 1394 1395 struct bgmac_stat { 1396 u8 size; 1397 u32 offset; 1398 const char *name; 1399 }; 1400 1401 static struct bgmac_stat bgmac_get_strings_stats[] = { 1402 { 8, BGMAC_TX_GOOD_OCTETS, "tx_good_octets" }, 1403 { 4, BGMAC_TX_GOOD_PKTS, "tx_good" }, 1404 { 8, BGMAC_TX_OCTETS, "tx_octets" }, 1405 { 4, BGMAC_TX_PKTS, "tx_pkts" }, 1406 { 4, BGMAC_TX_BROADCAST_PKTS, "tx_broadcast" }, 1407 { 4, BGMAC_TX_MULTICAST_PKTS, "tx_multicast" }, 1408 { 4, BGMAC_TX_LEN_64, "tx_64" }, 1409 { 4, BGMAC_TX_LEN_65_TO_127, "tx_65_127" }, 1410 { 4, BGMAC_TX_LEN_128_TO_255, "tx_128_255" }, 1411 { 4, BGMAC_TX_LEN_256_TO_511, "tx_256_511" }, 1412 { 4, BGMAC_TX_LEN_512_TO_1023, "tx_512_1023" }, 1413 { 4, BGMAC_TX_LEN_1024_TO_1522, "tx_1024_1522" }, 1414 { 4, BGMAC_TX_LEN_1523_TO_2047, "tx_1523_2047" }, 1415 { 4, BGMAC_TX_LEN_2048_TO_4095, "tx_2048_4095" }, 1416 { 4, BGMAC_TX_LEN_4096_TO_8191, "tx_4096_8191" }, 1417 { 4, BGMAC_TX_LEN_8192_TO_MAX, "tx_8192_max" }, 1418 { 4, BGMAC_TX_JABBER_PKTS, "tx_jabber" }, 1419 { 4, BGMAC_TX_OVERSIZE_PKTS, "tx_oversize" }, 1420 { 4, BGMAC_TX_FRAGMENT_PKTS, "tx_fragment" }, 1421 { 4, BGMAC_TX_UNDERRUNS, "tx_underruns" }, 1422 { 4, BGMAC_TX_TOTAL_COLS, "tx_total_cols" }, 1423 { 4, BGMAC_TX_SINGLE_COLS, "tx_single_cols" }, 1424 { 4, BGMAC_TX_MULTIPLE_COLS, "tx_multiple_cols" }, 1425 { 4, BGMAC_TX_EXCESSIVE_COLS, "tx_excessive_cols" }, 1426 { 4, BGMAC_TX_LATE_COLS, "tx_late_cols" }, 1427 { 4, BGMAC_TX_DEFERED, "tx_defered" }, 1428 { 4, BGMAC_TX_CARRIER_LOST, "tx_carrier_lost" }, 1429 { 4, BGMAC_TX_PAUSE_PKTS, "tx_pause" }, 1430 { 4, BGMAC_TX_UNI_PKTS, "tx_unicast" }, 1431 { 4, BGMAC_TX_Q0_PKTS, "tx_q0" }, 1432 { 8, BGMAC_TX_Q0_OCTETS, "tx_q0_octets" }, 1433 { 4, BGMAC_TX_Q1_PKTS, "tx_q1" }, 1434 { 8, BGMAC_TX_Q1_OCTETS, "tx_q1_octets" }, 1435 { 4, BGMAC_TX_Q2_PKTS, "tx_q2" }, 1436 { 8, BGMAC_TX_Q2_OCTETS, "tx_q2_octets" }, 1437 { 4, BGMAC_TX_Q3_PKTS, "tx_q3" }, 1438 { 8, BGMAC_TX_Q3_OCTETS, "tx_q3_octets" }, 1439 { 8, BGMAC_RX_GOOD_OCTETS, "rx_good_octets" }, 1440 { 4, BGMAC_RX_GOOD_PKTS, "rx_good" }, 1441 { 8, BGMAC_RX_OCTETS, "rx_octets" }, 1442 { 4, BGMAC_RX_PKTS, "rx_pkts" }, 1443 { 4, BGMAC_RX_BROADCAST_PKTS, "rx_broadcast" }, 1444 { 4, BGMAC_RX_MULTICAST_PKTS, "rx_multicast" }, 1445 { 4, BGMAC_RX_LEN_64, "rx_64" }, 1446 { 4, BGMAC_RX_LEN_65_TO_127, "rx_65_127" }, 1447 { 4, BGMAC_RX_LEN_128_TO_255, "rx_128_255" }, 1448 { 4, BGMAC_RX_LEN_256_TO_511, "rx_256_511" }, 1449 { 4, BGMAC_RX_LEN_512_TO_1023, "rx_512_1023" }, 1450 { 4, BGMAC_RX_LEN_1024_TO_1522, "rx_1024_1522" }, 1451 { 4, BGMAC_RX_LEN_1523_TO_2047, "rx_1523_2047" }, 1452 { 4, BGMAC_RX_LEN_2048_TO_4095, "rx_2048_4095" }, 1453 { 4, BGMAC_RX_LEN_4096_TO_8191, "rx_4096_8191" }, 1454 { 4, BGMAC_RX_LEN_8192_TO_MAX, "rx_8192_max" }, 1455 { 4, BGMAC_RX_JABBER_PKTS, "rx_jabber" }, 1456 { 4, BGMAC_RX_OVERSIZE_PKTS, "rx_oversize" }, 1457 { 4, BGMAC_RX_FRAGMENT_PKTS, "rx_fragment" }, 1458 { 4, BGMAC_RX_MISSED_PKTS, "rx_missed" }, 1459 { 4, BGMAC_RX_CRC_ALIGN_ERRS, "rx_crc_align" }, 1460 { 4, BGMAC_RX_UNDERSIZE, "rx_undersize" }, 1461 { 4, BGMAC_RX_CRC_ERRS, "rx_crc" }, 1462 { 4, BGMAC_RX_ALIGN_ERRS, "rx_align" }, 1463 { 4, BGMAC_RX_SYMBOL_ERRS, "rx_symbol" }, 1464 { 4, BGMAC_RX_PAUSE_PKTS, "rx_pause" }, 1465 { 4, BGMAC_RX_NONPAUSE_PKTS, "rx_nonpause" }, 1466 { 4, BGMAC_RX_SACHANGES, "rx_sa_changes" }, 1467 { 4, BGMAC_RX_UNI_PKTS, "rx_unicast" }, 1468 }; 1469 1470 #define BGMAC_STATS_LEN ARRAY_SIZE(bgmac_get_strings_stats) 1471 1472 static int bgmac_get_sset_count(struct net_device *dev, int string_set) 1473 { 1474 switch (string_set) { 1475 case ETH_SS_STATS: 1476 return BGMAC_STATS_LEN; 1477 } 1478 1479 return -EOPNOTSUPP; 1480 } 1481 1482 static void bgmac_get_strings(struct net_device *dev, u32 stringset, 1483 u8 *data) 1484 { 1485 int i; 1486 1487 if (stringset != ETH_SS_STATS) 1488 return; 1489 1490 for (i = 0; i < BGMAC_STATS_LEN; i++) 1491 strlcpy(data + i * ETH_GSTRING_LEN, 1492 bgmac_get_strings_stats[i].name, ETH_GSTRING_LEN); 1493 } 1494 1495 static void bgmac_get_ethtool_stats(struct net_device *dev, 1496 struct ethtool_stats *ss, uint64_t *data) 1497 { 1498 struct bgmac *bgmac = netdev_priv(dev); 1499 const struct bgmac_stat *s; 1500 unsigned int i; 1501 u64 val; 1502 1503 if (!netif_running(dev)) 1504 return; 1505 1506 for (i = 0; i < BGMAC_STATS_LEN; i++) { 1507 s = &bgmac_get_strings_stats[i]; 1508 val = 0; 1509 if (s->size == 8) 1510 val = (u64)bgmac_read(bgmac, s->offset + 4) << 32; 1511 val |= bgmac_read(bgmac, s->offset); 1512 data[i] = val; 1513 } 1514 } 1515 1516 static int bgmac_get_settings(struct net_device *net_dev, 1517 struct ethtool_cmd *cmd) 1518 { 1519 struct bgmac *bgmac = netdev_priv(net_dev); 1520 1521 return phy_ethtool_gset(bgmac->phy_dev, cmd); 1522 } 1523 1524 static int bgmac_set_settings(struct net_device *net_dev, 1525 struct ethtool_cmd *cmd) 1526 { 1527 struct bgmac *bgmac = netdev_priv(net_dev); 1528 1529 return phy_ethtool_sset(bgmac->phy_dev, cmd); 1530 } 1531 1532 static void bgmac_get_drvinfo(struct net_device *net_dev, 1533 struct ethtool_drvinfo *info) 1534 { 1535 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver)); 1536 strlcpy(info->bus_info, "BCMA", sizeof(info->bus_info)); 1537 } 1538 1539 static const struct ethtool_ops bgmac_ethtool_ops = { 1540 .get_strings = bgmac_get_strings, 1541 .get_sset_count = bgmac_get_sset_count, 1542 .get_ethtool_stats = bgmac_get_ethtool_stats, 1543 .get_settings = bgmac_get_settings, 1544 .set_settings = bgmac_set_settings, 1545 .get_drvinfo = bgmac_get_drvinfo, 1546 }; 1547 1548 /************************************************** 1549 * MII 1550 **************************************************/ 1551 1552 static int bgmac_mii_read(struct mii_bus *bus, int mii_id, int regnum) 1553 { 1554 return bgmac_phy_read(bus->priv, mii_id, regnum); 1555 } 1556 1557 static int bgmac_mii_write(struct mii_bus *bus, int mii_id, int regnum, 1558 u16 value) 1559 { 1560 return bgmac_phy_write(bus->priv, mii_id, regnum, value); 1561 } 1562 1563 static void bgmac_adjust_link(struct net_device *net_dev) 1564 { 1565 struct bgmac *bgmac = netdev_priv(net_dev); 1566 struct phy_device *phy_dev = bgmac->phy_dev; 1567 bool update = false; 1568 1569 if (phy_dev->link) { 1570 if (phy_dev->speed != bgmac->mac_speed) { 1571 bgmac->mac_speed = phy_dev->speed; 1572 update = true; 1573 } 1574 1575 if (phy_dev->duplex != bgmac->mac_duplex) { 1576 bgmac->mac_duplex = phy_dev->duplex; 1577 update = true; 1578 } 1579 } 1580 1581 if (update) { 1582 bgmac_mac_speed(bgmac); 1583 phy_print_status(phy_dev); 1584 } 1585 } 1586 1587 static int bgmac_fixed_phy_register(struct bgmac *bgmac) 1588 { 1589 struct fixed_phy_status fphy_status = { 1590 .link = 1, 1591 .speed = SPEED_1000, 1592 .duplex = DUPLEX_FULL, 1593 }; 1594 struct phy_device *phy_dev; 1595 int err; 1596 1597 phy_dev = fixed_phy_register(PHY_POLL, &fphy_status, -1, NULL); 1598 if (!phy_dev || IS_ERR(phy_dev)) { 1599 bgmac_err(bgmac, "Failed to register fixed PHY device\n"); 1600 return -ENODEV; 1601 } 1602 1603 err = phy_connect_direct(bgmac->net_dev, phy_dev, bgmac_adjust_link, 1604 PHY_INTERFACE_MODE_MII); 1605 if (err) { 1606 bgmac_err(bgmac, "Connecting PHY failed\n"); 1607 return err; 1608 } 1609 1610 bgmac->phy_dev = phy_dev; 1611 1612 return err; 1613 } 1614 1615 static int bgmac_mii_register(struct bgmac *bgmac) 1616 { 1617 struct mii_bus *mii_bus; 1618 struct phy_device *phy_dev; 1619 char bus_id[MII_BUS_ID_SIZE + 3]; 1620 int err = 0; 1621 1622 if (bgmac_is_bcm4707_family(bgmac)) 1623 return bgmac_fixed_phy_register(bgmac); 1624 1625 mii_bus = mdiobus_alloc(); 1626 if (!mii_bus) 1627 return -ENOMEM; 1628 1629 mii_bus->name = "bgmac mii bus"; 1630 sprintf(mii_bus->id, "%s-%d-%d", "bgmac", bgmac->core->bus->num, 1631 bgmac->core->core_unit); 1632 mii_bus->priv = bgmac; 1633 mii_bus->read = bgmac_mii_read; 1634 mii_bus->write = bgmac_mii_write; 1635 mii_bus->parent = &bgmac->core->dev; 1636 mii_bus->phy_mask = ~(1 << bgmac->phyaddr); 1637 1638 err = mdiobus_register(mii_bus); 1639 if (err) { 1640 bgmac_err(bgmac, "Registration of mii bus failed\n"); 1641 goto err_free_bus; 1642 } 1643 1644 bgmac->mii_bus = mii_bus; 1645 1646 /* Connect to the PHY */ 1647 snprintf(bus_id, sizeof(bus_id), PHY_ID_FMT, mii_bus->id, 1648 bgmac->phyaddr); 1649 phy_dev = phy_connect(bgmac->net_dev, bus_id, &bgmac_adjust_link, 1650 PHY_INTERFACE_MODE_MII); 1651 if (IS_ERR(phy_dev)) { 1652 bgmac_err(bgmac, "PHY connection failed\n"); 1653 err = PTR_ERR(phy_dev); 1654 goto err_unregister_bus; 1655 } 1656 bgmac->phy_dev = phy_dev; 1657 1658 return err; 1659 1660 err_unregister_bus: 1661 mdiobus_unregister(mii_bus); 1662 err_free_bus: 1663 mdiobus_free(mii_bus); 1664 return err; 1665 } 1666 1667 static void bgmac_mii_unregister(struct bgmac *bgmac) 1668 { 1669 struct mii_bus *mii_bus = bgmac->mii_bus; 1670 1671 mdiobus_unregister(mii_bus); 1672 mdiobus_free(mii_bus); 1673 } 1674 1675 /************************************************** 1676 * BCMA bus ops 1677 **************************************************/ 1678 1679 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipattach */ 1680 static int bgmac_probe(struct bcma_device *core) 1681 { 1682 struct net_device *net_dev; 1683 struct bgmac *bgmac; 1684 struct ssb_sprom *sprom = &core->bus->sprom; 1685 u8 *mac; 1686 int err; 1687 1688 switch (core->core_unit) { 1689 case 0: 1690 mac = sprom->et0mac; 1691 break; 1692 case 1: 1693 mac = sprom->et1mac; 1694 break; 1695 case 2: 1696 mac = sprom->et2mac; 1697 break; 1698 default: 1699 pr_err("Unsupported core_unit %d\n", core->core_unit); 1700 return -ENOTSUPP; 1701 } 1702 1703 if (!is_valid_ether_addr(mac)) { 1704 dev_err(&core->dev, "Invalid MAC addr: %pM\n", mac); 1705 eth_random_addr(mac); 1706 dev_warn(&core->dev, "Using random MAC: %pM\n", mac); 1707 } 1708 1709 /* This (reset &) enable is not preset in specs or reference driver but 1710 * Broadcom does it in arch PCI code when enabling fake PCI device. 1711 */ 1712 bcma_core_enable(core, 0); 1713 1714 /* Allocation and references */ 1715 net_dev = alloc_etherdev(sizeof(*bgmac)); 1716 if (!net_dev) 1717 return -ENOMEM; 1718 net_dev->netdev_ops = &bgmac_netdev_ops; 1719 net_dev->irq = core->irq; 1720 net_dev->ethtool_ops = &bgmac_ethtool_ops; 1721 bgmac = netdev_priv(net_dev); 1722 bgmac->net_dev = net_dev; 1723 bgmac->core = core; 1724 bcma_set_drvdata(core, bgmac); 1725 SET_NETDEV_DEV(net_dev, &core->dev); 1726 1727 /* Defaults */ 1728 memcpy(bgmac->net_dev->dev_addr, mac, ETH_ALEN); 1729 1730 /* On BCM4706 we need common core to access PHY */ 1731 if (core->id.id == BCMA_CORE_4706_MAC_GBIT && 1732 !core->bus->drv_gmac_cmn.core) { 1733 bgmac_err(bgmac, "GMAC CMN core not found (required for BCM4706)\n"); 1734 err = -ENODEV; 1735 goto err_netdev_free; 1736 } 1737 bgmac->cmn = core->bus->drv_gmac_cmn.core; 1738 1739 switch (core->core_unit) { 1740 case 0: 1741 bgmac->phyaddr = sprom->et0phyaddr; 1742 break; 1743 case 1: 1744 bgmac->phyaddr = sprom->et1phyaddr; 1745 break; 1746 case 2: 1747 bgmac->phyaddr = sprom->et2phyaddr; 1748 break; 1749 } 1750 bgmac->phyaddr &= BGMAC_PHY_MASK; 1751 if (bgmac->phyaddr == BGMAC_PHY_MASK) { 1752 bgmac_err(bgmac, "No PHY found\n"); 1753 err = -ENODEV; 1754 goto err_netdev_free; 1755 } 1756 bgmac_info(bgmac, "Found PHY addr: %d%s\n", bgmac->phyaddr, 1757 bgmac->phyaddr == BGMAC_PHY_NOREGS ? " (NOREGS)" : ""); 1758 1759 if (core->bus->hosttype == BCMA_HOSTTYPE_PCI) { 1760 bgmac_err(bgmac, "PCI setup not implemented\n"); 1761 err = -ENOTSUPP; 1762 goto err_netdev_free; 1763 } 1764 1765 bgmac_chip_reset(bgmac); 1766 1767 /* For Northstar, we have to take all GMAC core out of reset */ 1768 if (bgmac_is_bcm4707_family(bgmac)) { 1769 struct bcma_device *ns_core; 1770 int ns_gmac; 1771 1772 /* Northstar has 4 GMAC cores */ 1773 for (ns_gmac = 0; ns_gmac < 4; ns_gmac++) { 1774 /* As Northstar requirement, we have to reset all GMACs 1775 * before accessing one. bgmac_chip_reset() call 1776 * bcma_core_enable() for this core. Then the other 1777 * three GMACs didn't reset. We do it here. 1778 */ 1779 ns_core = bcma_find_core_unit(core->bus, 1780 BCMA_CORE_MAC_GBIT, 1781 ns_gmac); 1782 if (ns_core && !bcma_core_is_enabled(ns_core)) 1783 bcma_core_enable(ns_core, 0); 1784 } 1785 } 1786 1787 err = bgmac_dma_alloc(bgmac); 1788 if (err) { 1789 bgmac_err(bgmac, "Unable to alloc memory for DMA\n"); 1790 goto err_netdev_free; 1791 } 1792 1793 bgmac->int_mask = BGMAC_IS_ERRMASK | BGMAC_IS_RX | BGMAC_IS_TX_MASK; 1794 if (bcm47xx_nvram_getenv("et0_no_txint", NULL, 0) == 0) 1795 bgmac->int_mask &= ~BGMAC_IS_TX_MASK; 1796 1797 /* TODO: reset the external phy. Specs are needed */ 1798 bgmac_phy_reset(bgmac); 1799 1800 bgmac->has_robosw = !!(core->bus->sprom.boardflags_lo & 1801 BGMAC_BFL_ENETROBO); 1802 if (bgmac->has_robosw) 1803 bgmac_warn(bgmac, "Support for Roboswitch not implemented\n"); 1804 1805 if (core->bus->sprom.boardflags_lo & BGMAC_BFL_ENETADM) 1806 bgmac_warn(bgmac, "Support for ADMtek ethernet switch not implemented\n"); 1807 1808 netif_napi_add(net_dev, &bgmac->napi, bgmac_poll, BGMAC_WEIGHT); 1809 1810 err = bgmac_mii_register(bgmac); 1811 if (err) { 1812 bgmac_err(bgmac, "Cannot register MDIO\n"); 1813 goto err_dma_free; 1814 } 1815 1816 net_dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 1817 net_dev->hw_features = net_dev->features; 1818 net_dev->vlan_features = net_dev->features; 1819 1820 err = register_netdev(bgmac->net_dev); 1821 if (err) { 1822 bgmac_err(bgmac, "Cannot register net device\n"); 1823 goto err_mii_unregister; 1824 } 1825 1826 netif_carrier_off(net_dev); 1827 1828 return 0; 1829 1830 err_mii_unregister: 1831 bgmac_mii_unregister(bgmac); 1832 err_dma_free: 1833 bgmac_dma_free(bgmac); 1834 1835 err_netdev_free: 1836 bcma_set_drvdata(core, NULL); 1837 free_netdev(net_dev); 1838 1839 return err; 1840 } 1841 1842 static void bgmac_remove(struct bcma_device *core) 1843 { 1844 struct bgmac *bgmac = bcma_get_drvdata(core); 1845 1846 unregister_netdev(bgmac->net_dev); 1847 bgmac_mii_unregister(bgmac); 1848 netif_napi_del(&bgmac->napi); 1849 bgmac_dma_free(bgmac); 1850 bcma_set_drvdata(core, NULL); 1851 free_netdev(bgmac->net_dev); 1852 } 1853 1854 static struct bcma_driver bgmac_bcma_driver = { 1855 .name = KBUILD_MODNAME, 1856 .id_table = bgmac_bcma_tbl, 1857 .probe = bgmac_probe, 1858 .remove = bgmac_remove, 1859 }; 1860 1861 static int __init bgmac_init(void) 1862 { 1863 int err; 1864 1865 err = bcma_driver_register(&bgmac_bcma_driver); 1866 if (err) 1867 return err; 1868 pr_info("Broadcom 47xx GBit MAC driver loaded\n"); 1869 1870 return 0; 1871 } 1872 1873 static void __exit bgmac_exit(void) 1874 { 1875 bcma_driver_unregister(&bgmac_bcma_driver); 1876 } 1877 1878 module_init(bgmac_init) 1879 module_exit(bgmac_exit) 1880 1881 MODULE_AUTHOR("Rafał Miłecki"); 1882 MODULE_LICENSE("GPL"); 1883