1 /* 2 * Driver for (BCM4706)? GBit MAC core on BCMA bus. 3 * 4 * Copyright (C) 2012 Rafał Miłecki <zajec5@gmail.com> 5 * 6 * Licensed under the GNU/GPL. See COPYING for details. 7 */ 8 9 #include "bgmac.h" 10 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/delay.h> 14 #include <linux/etherdevice.h> 15 #include <linux/mii.h> 16 #include <linux/phy.h> 17 #include <linux/interrupt.h> 18 #include <linux/dma-mapping.h> 19 #include <bcm47xx_nvram.h> 20 21 static const struct bcma_device_id bgmac_bcma_tbl[] = { 22 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_4706_MAC_GBIT, BCMA_ANY_REV, BCMA_ANY_CLASS), 23 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_MAC_GBIT, BCMA_ANY_REV, BCMA_ANY_CLASS), 24 {}, 25 }; 26 MODULE_DEVICE_TABLE(bcma, bgmac_bcma_tbl); 27 28 static bool bgmac_wait_value(struct bcma_device *core, u16 reg, u32 mask, 29 u32 value, int timeout) 30 { 31 u32 val; 32 int i; 33 34 for (i = 0; i < timeout / 10; i++) { 35 val = bcma_read32(core, reg); 36 if ((val & mask) == value) 37 return true; 38 udelay(10); 39 } 40 pr_err("Timeout waiting for reg 0x%X\n", reg); 41 return false; 42 } 43 44 /************************************************** 45 * DMA 46 **************************************************/ 47 48 static void bgmac_dma_tx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring) 49 { 50 u32 val; 51 int i; 52 53 if (!ring->mmio_base) 54 return; 55 56 /* Suspend DMA TX ring first. 57 * bgmac_wait_value doesn't support waiting for any of few values, so 58 * implement whole loop here. 59 */ 60 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 61 BGMAC_DMA_TX_SUSPEND); 62 for (i = 0; i < 10000 / 10; i++) { 63 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS); 64 val &= BGMAC_DMA_TX_STAT; 65 if (val == BGMAC_DMA_TX_STAT_DISABLED || 66 val == BGMAC_DMA_TX_STAT_IDLEWAIT || 67 val == BGMAC_DMA_TX_STAT_STOPPED) { 68 i = 0; 69 break; 70 } 71 udelay(10); 72 } 73 if (i) 74 bgmac_err(bgmac, "Timeout suspending DMA TX ring 0x%X (BGMAC_DMA_TX_STAT: 0x%08X)\n", 75 ring->mmio_base, val); 76 77 /* Remove SUSPEND bit */ 78 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 0); 79 if (!bgmac_wait_value(bgmac->core, 80 ring->mmio_base + BGMAC_DMA_TX_STATUS, 81 BGMAC_DMA_TX_STAT, BGMAC_DMA_TX_STAT_DISABLED, 82 10000)) { 83 bgmac_warn(bgmac, "DMA TX ring 0x%X wasn't disabled on time, waiting additional 300us\n", 84 ring->mmio_base); 85 udelay(300); 86 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS); 87 if ((val & BGMAC_DMA_TX_STAT) != BGMAC_DMA_TX_STAT_DISABLED) 88 bgmac_err(bgmac, "Reset of DMA TX ring 0x%X failed\n", 89 ring->mmio_base); 90 } 91 } 92 93 static void bgmac_dma_tx_enable(struct bgmac *bgmac, 94 struct bgmac_dma_ring *ring) 95 { 96 u32 ctl; 97 98 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL); 99 if (bgmac->core->id.rev >= 4) { 100 ctl &= ~BGMAC_DMA_TX_BL_MASK; 101 ctl |= BGMAC_DMA_TX_BL_128 << BGMAC_DMA_TX_BL_SHIFT; 102 103 ctl &= ~BGMAC_DMA_TX_MR_MASK; 104 ctl |= BGMAC_DMA_TX_MR_2 << BGMAC_DMA_TX_MR_SHIFT; 105 106 ctl &= ~BGMAC_DMA_TX_PC_MASK; 107 ctl |= BGMAC_DMA_TX_PC_16 << BGMAC_DMA_TX_PC_SHIFT; 108 109 ctl &= ~BGMAC_DMA_TX_PT_MASK; 110 ctl |= BGMAC_DMA_TX_PT_8 << BGMAC_DMA_TX_PT_SHIFT; 111 } 112 ctl |= BGMAC_DMA_TX_ENABLE; 113 ctl |= BGMAC_DMA_TX_PARITY_DISABLE; 114 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl); 115 } 116 117 static netdev_tx_t bgmac_dma_tx_add(struct bgmac *bgmac, 118 struct bgmac_dma_ring *ring, 119 struct sk_buff *skb) 120 { 121 struct device *dma_dev = bgmac->core->dma_dev; 122 struct net_device *net_dev = bgmac->net_dev; 123 struct bgmac_dma_desc *dma_desc; 124 struct bgmac_slot_info *slot; 125 u32 ctl0, ctl1; 126 int free_slots; 127 128 if (skb->len > BGMAC_DESC_CTL1_LEN) { 129 bgmac_err(bgmac, "Too long skb (%d)\n", skb->len); 130 goto err_stop_drop; 131 } 132 133 if (ring->start <= ring->end) 134 free_slots = ring->start - ring->end + BGMAC_TX_RING_SLOTS; 135 else 136 free_slots = ring->start - ring->end; 137 if (free_slots == 1) { 138 bgmac_err(bgmac, "TX ring is full, queue should be stopped!\n"); 139 netif_stop_queue(net_dev); 140 return NETDEV_TX_BUSY; 141 } 142 143 slot = &ring->slots[ring->end]; 144 slot->skb = skb; 145 slot->dma_addr = dma_map_single(dma_dev, skb->data, skb->len, 146 DMA_TO_DEVICE); 147 if (dma_mapping_error(dma_dev, slot->dma_addr)) { 148 bgmac_err(bgmac, "Mapping error of skb on ring 0x%X\n", 149 ring->mmio_base); 150 goto err_stop_drop; 151 } 152 153 ctl0 = BGMAC_DESC_CTL0_IOC | BGMAC_DESC_CTL0_SOF | BGMAC_DESC_CTL0_EOF; 154 if (ring->end == ring->num_slots - 1) 155 ctl0 |= BGMAC_DESC_CTL0_EOT; 156 ctl1 = skb->len & BGMAC_DESC_CTL1_LEN; 157 158 dma_desc = ring->cpu_base; 159 dma_desc += ring->end; 160 dma_desc->addr_low = cpu_to_le32(lower_32_bits(slot->dma_addr)); 161 dma_desc->addr_high = cpu_to_le32(upper_32_bits(slot->dma_addr)); 162 dma_desc->ctl0 = cpu_to_le32(ctl0); 163 dma_desc->ctl1 = cpu_to_le32(ctl1); 164 165 netdev_sent_queue(net_dev, skb->len); 166 167 wmb(); 168 169 /* Increase ring->end to point empty slot. We tell hardware the first 170 * slot it should *not* read. 171 */ 172 if (++ring->end >= BGMAC_TX_RING_SLOTS) 173 ring->end = 0; 174 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_INDEX, 175 ring->index_base + 176 ring->end * sizeof(struct bgmac_dma_desc)); 177 178 /* Always keep one slot free to allow detecting bugged calls. */ 179 if (--free_slots == 1) 180 netif_stop_queue(net_dev); 181 182 return NETDEV_TX_OK; 183 184 err_stop_drop: 185 netif_stop_queue(net_dev); 186 dev_kfree_skb(skb); 187 return NETDEV_TX_OK; 188 } 189 190 /* Free transmitted packets */ 191 static void bgmac_dma_tx_free(struct bgmac *bgmac, struct bgmac_dma_ring *ring) 192 { 193 struct device *dma_dev = bgmac->core->dma_dev; 194 int empty_slot; 195 bool freed = false; 196 unsigned bytes_compl = 0, pkts_compl = 0; 197 198 /* The last slot that hardware didn't consume yet */ 199 empty_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS); 200 empty_slot &= BGMAC_DMA_TX_STATDPTR; 201 empty_slot -= ring->index_base; 202 empty_slot &= BGMAC_DMA_TX_STATDPTR; 203 empty_slot /= sizeof(struct bgmac_dma_desc); 204 205 while (ring->start != empty_slot) { 206 struct bgmac_slot_info *slot = &ring->slots[ring->start]; 207 208 if (slot->skb) { 209 /* Unmap no longer used buffer */ 210 dma_unmap_single(dma_dev, slot->dma_addr, 211 slot->skb->len, DMA_TO_DEVICE); 212 slot->dma_addr = 0; 213 214 bytes_compl += slot->skb->len; 215 pkts_compl++; 216 217 /* Free memory! :) */ 218 dev_kfree_skb(slot->skb); 219 slot->skb = NULL; 220 } else { 221 bgmac_err(bgmac, "Hardware reported transmission for empty TX ring slot %d! End of ring: %d\n", 222 ring->start, ring->end); 223 } 224 225 if (++ring->start >= BGMAC_TX_RING_SLOTS) 226 ring->start = 0; 227 freed = true; 228 } 229 230 netdev_completed_queue(bgmac->net_dev, pkts_compl, bytes_compl); 231 232 if (freed && netif_queue_stopped(bgmac->net_dev)) 233 netif_wake_queue(bgmac->net_dev); 234 } 235 236 static void bgmac_dma_rx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring) 237 { 238 if (!ring->mmio_base) 239 return; 240 241 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, 0); 242 if (!bgmac_wait_value(bgmac->core, 243 ring->mmio_base + BGMAC_DMA_RX_STATUS, 244 BGMAC_DMA_RX_STAT, BGMAC_DMA_RX_STAT_DISABLED, 245 10000)) 246 bgmac_err(bgmac, "Reset of ring 0x%X RX failed\n", 247 ring->mmio_base); 248 } 249 250 static void bgmac_dma_rx_enable(struct bgmac *bgmac, 251 struct bgmac_dma_ring *ring) 252 { 253 u32 ctl; 254 255 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL); 256 if (bgmac->core->id.rev >= 4) { 257 ctl &= ~BGMAC_DMA_RX_BL_MASK; 258 ctl |= BGMAC_DMA_RX_BL_128 << BGMAC_DMA_RX_BL_SHIFT; 259 260 ctl &= ~BGMAC_DMA_RX_PC_MASK; 261 ctl |= BGMAC_DMA_RX_PC_8 << BGMAC_DMA_RX_PC_SHIFT; 262 263 ctl &= ~BGMAC_DMA_RX_PT_MASK; 264 ctl |= BGMAC_DMA_RX_PT_1 << BGMAC_DMA_RX_PT_SHIFT; 265 } 266 ctl &= BGMAC_DMA_RX_ADDREXT_MASK; 267 ctl |= BGMAC_DMA_RX_ENABLE; 268 ctl |= BGMAC_DMA_RX_PARITY_DISABLE; 269 ctl |= BGMAC_DMA_RX_OVERFLOW_CONT; 270 ctl |= BGMAC_RX_FRAME_OFFSET << BGMAC_DMA_RX_FRAME_OFFSET_SHIFT; 271 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, ctl); 272 } 273 274 static int bgmac_dma_rx_skb_for_slot(struct bgmac *bgmac, 275 struct bgmac_slot_info *slot) 276 { 277 struct device *dma_dev = bgmac->core->dma_dev; 278 struct sk_buff *skb; 279 dma_addr_t dma_addr; 280 struct bgmac_rx_header *rx; 281 282 /* Alloc skb */ 283 skb = netdev_alloc_skb(bgmac->net_dev, BGMAC_RX_BUF_SIZE); 284 if (!skb) 285 return -ENOMEM; 286 287 /* Poison - if everything goes fine, hardware will overwrite it */ 288 rx = (struct bgmac_rx_header *)skb->data; 289 rx->len = cpu_to_le16(0xdead); 290 rx->flags = cpu_to_le16(0xbeef); 291 292 /* Map skb for the DMA */ 293 dma_addr = dma_map_single(dma_dev, skb->data, 294 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE); 295 if (dma_mapping_error(dma_dev, dma_addr)) { 296 bgmac_err(bgmac, "DMA mapping error\n"); 297 dev_kfree_skb(skb); 298 return -ENOMEM; 299 } 300 301 /* Update the slot */ 302 slot->skb = skb; 303 slot->dma_addr = dma_addr; 304 305 return 0; 306 } 307 308 static void bgmac_dma_rx_setup_desc(struct bgmac *bgmac, 309 struct bgmac_dma_ring *ring, int desc_idx) 310 { 311 struct bgmac_dma_desc *dma_desc = ring->cpu_base + desc_idx; 312 u32 ctl0 = 0, ctl1 = 0; 313 314 if (desc_idx == ring->num_slots - 1) 315 ctl0 |= BGMAC_DESC_CTL0_EOT; 316 ctl1 |= BGMAC_RX_BUF_SIZE & BGMAC_DESC_CTL1_LEN; 317 /* Is there any BGMAC device that requires extension? */ 318 /* ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT) & 319 * B43_DMA64_DCTL1_ADDREXT_MASK; 320 */ 321 322 dma_desc->addr_low = cpu_to_le32(lower_32_bits(ring->slots[desc_idx].dma_addr)); 323 dma_desc->addr_high = cpu_to_le32(upper_32_bits(ring->slots[desc_idx].dma_addr)); 324 dma_desc->ctl0 = cpu_to_le32(ctl0); 325 dma_desc->ctl1 = cpu_to_le32(ctl1); 326 } 327 328 static int bgmac_dma_rx_read(struct bgmac *bgmac, struct bgmac_dma_ring *ring, 329 int weight) 330 { 331 u32 end_slot; 332 int handled = 0; 333 334 end_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_STATUS); 335 end_slot &= BGMAC_DMA_RX_STATDPTR; 336 end_slot -= ring->index_base; 337 end_slot &= BGMAC_DMA_RX_STATDPTR; 338 end_slot /= sizeof(struct bgmac_dma_desc); 339 340 ring->end = end_slot; 341 342 while (ring->start != ring->end) { 343 struct device *dma_dev = bgmac->core->dma_dev; 344 struct bgmac_slot_info *slot = &ring->slots[ring->start]; 345 struct sk_buff *skb = slot->skb; 346 struct bgmac_rx_header *rx; 347 u16 len, flags; 348 349 /* Unmap buffer to make it accessible to the CPU */ 350 dma_sync_single_for_cpu(dma_dev, slot->dma_addr, 351 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE); 352 353 /* Get info from the header */ 354 rx = (struct bgmac_rx_header *)skb->data; 355 len = le16_to_cpu(rx->len); 356 flags = le16_to_cpu(rx->flags); 357 358 do { 359 dma_addr_t old_dma_addr = slot->dma_addr; 360 int err; 361 362 /* Check for poison and drop or pass the packet */ 363 if (len == 0xdead && flags == 0xbeef) { 364 bgmac_err(bgmac, "Found poisoned packet at slot %d, DMA issue!\n", 365 ring->start); 366 dma_sync_single_for_device(dma_dev, 367 slot->dma_addr, 368 BGMAC_RX_BUF_SIZE, 369 DMA_FROM_DEVICE); 370 break; 371 } 372 373 /* Omit CRC. */ 374 len -= ETH_FCS_LEN; 375 376 /* Prepare new skb as replacement */ 377 err = bgmac_dma_rx_skb_for_slot(bgmac, slot); 378 if (err) { 379 /* Poison the old skb */ 380 rx->len = cpu_to_le16(0xdead); 381 rx->flags = cpu_to_le16(0xbeef); 382 383 dma_sync_single_for_device(dma_dev, 384 slot->dma_addr, 385 BGMAC_RX_BUF_SIZE, 386 DMA_FROM_DEVICE); 387 break; 388 } 389 bgmac_dma_rx_setup_desc(bgmac, ring, ring->start); 390 391 /* Unmap old skb, we'll pass it to the netfif */ 392 dma_unmap_single(dma_dev, old_dma_addr, 393 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE); 394 395 skb_put(skb, BGMAC_RX_FRAME_OFFSET + len); 396 skb_pull(skb, BGMAC_RX_FRAME_OFFSET); 397 398 skb_checksum_none_assert(skb); 399 skb->protocol = eth_type_trans(skb, bgmac->net_dev); 400 netif_receive_skb(skb); 401 handled++; 402 } while (0); 403 404 if (++ring->start >= BGMAC_RX_RING_SLOTS) 405 ring->start = 0; 406 407 if (handled >= weight) /* Should never be greater */ 408 break; 409 } 410 411 return handled; 412 } 413 414 /* Does ring support unaligned addressing? */ 415 static bool bgmac_dma_unaligned(struct bgmac *bgmac, 416 struct bgmac_dma_ring *ring, 417 enum bgmac_dma_ring_type ring_type) 418 { 419 switch (ring_type) { 420 case BGMAC_DMA_RING_TX: 421 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO, 422 0xff0); 423 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO)) 424 return true; 425 break; 426 case BGMAC_DMA_RING_RX: 427 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO, 428 0xff0); 429 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO)) 430 return true; 431 break; 432 } 433 return false; 434 } 435 436 static void bgmac_dma_ring_free(struct bgmac *bgmac, 437 struct bgmac_dma_ring *ring) 438 { 439 struct device *dma_dev = bgmac->core->dma_dev; 440 struct bgmac_slot_info *slot; 441 int size; 442 int i; 443 444 for (i = 0; i < ring->num_slots; i++) { 445 slot = &ring->slots[i]; 446 if (slot->skb) { 447 if (slot->dma_addr) 448 dma_unmap_single(dma_dev, slot->dma_addr, 449 slot->skb->len, DMA_TO_DEVICE); 450 dev_kfree_skb(slot->skb); 451 } 452 } 453 454 if (ring->cpu_base) { 455 /* Free ring of descriptors */ 456 size = ring->num_slots * sizeof(struct bgmac_dma_desc); 457 dma_free_coherent(dma_dev, size, ring->cpu_base, 458 ring->dma_base); 459 } 460 } 461 462 static void bgmac_dma_free(struct bgmac *bgmac) 463 { 464 int i; 465 466 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) 467 bgmac_dma_ring_free(bgmac, &bgmac->tx_ring[i]); 468 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) 469 bgmac_dma_ring_free(bgmac, &bgmac->rx_ring[i]); 470 } 471 472 static int bgmac_dma_alloc(struct bgmac *bgmac) 473 { 474 struct device *dma_dev = bgmac->core->dma_dev; 475 struct bgmac_dma_ring *ring; 476 static const u16 ring_base[] = { BGMAC_DMA_BASE0, BGMAC_DMA_BASE1, 477 BGMAC_DMA_BASE2, BGMAC_DMA_BASE3, }; 478 int size; /* ring size: different for Tx and Rx */ 479 int err; 480 int i; 481 482 BUILD_BUG_ON(BGMAC_MAX_TX_RINGS > ARRAY_SIZE(ring_base)); 483 BUILD_BUG_ON(BGMAC_MAX_RX_RINGS > ARRAY_SIZE(ring_base)); 484 485 if (!(bcma_aread32(bgmac->core, BCMA_IOST) & BCMA_IOST_DMA64)) { 486 bgmac_err(bgmac, "Core does not report 64-bit DMA\n"); 487 return -ENOTSUPP; 488 } 489 490 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) { 491 ring = &bgmac->tx_ring[i]; 492 ring->num_slots = BGMAC_TX_RING_SLOTS; 493 ring->mmio_base = ring_base[i]; 494 495 /* Alloc ring of descriptors */ 496 size = ring->num_slots * sizeof(struct bgmac_dma_desc); 497 ring->cpu_base = dma_zalloc_coherent(dma_dev, size, 498 &ring->dma_base, 499 GFP_KERNEL); 500 if (!ring->cpu_base) { 501 bgmac_err(bgmac, "Allocation of TX ring 0x%X failed\n", 502 ring->mmio_base); 503 goto err_dma_free; 504 } 505 506 ring->unaligned = bgmac_dma_unaligned(bgmac, ring, 507 BGMAC_DMA_RING_TX); 508 if (ring->unaligned) 509 ring->index_base = lower_32_bits(ring->dma_base); 510 else 511 ring->index_base = 0; 512 513 /* No need to alloc TX slots yet */ 514 } 515 516 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) { 517 int j; 518 519 ring = &bgmac->rx_ring[i]; 520 ring->num_slots = BGMAC_RX_RING_SLOTS; 521 ring->mmio_base = ring_base[i]; 522 523 /* Alloc ring of descriptors */ 524 size = ring->num_slots * sizeof(struct bgmac_dma_desc); 525 ring->cpu_base = dma_zalloc_coherent(dma_dev, size, 526 &ring->dma_base, 527 GFP_KERNEL); 528 if (!ring->cpu_base) { 529 bgmac_err(bgmac, "Allocation of RX ring 0x%X failed\n", 530 ring->mmio_base); 531 err = -ENOMEM; 532 goto err_dma_free; 533 } 534 535 ring->unaligned = bgmac_dma_unaligned(bgmac, ring, 536 BGMAC_DMA_RING_RX); 537 if (ring->unaligned) 538 ring->index_base = lower_32_bits(ring->dma_base); 539 else 540 ring->index_base = 0; 541 542 /* Alloc RX slots */ 543 for (j = 0; j < ring->num_slots; j++) { 544 err = bgmac_dma_rx_skb_for_slot(bgmac, &ring->slots[j]); 545 if (err) { 546 bgmac_err(bgmac, "Can't allocate skb for slot in RX ring\n"); 547 goto err_dma_free; 548 } 549 } 550 } 551 552 return 0; 553 554 err_dma_free: 555 bgmac_dma_free(bgmac); 556 return -ENOMEM; 557 } 558 559 static void bgmac_dma_init(struct bgmac *bgmac) 560 { 561 struct bgmac_dma_ring *ring; 562 int i; 563 564 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) { 565 ring = &bgmac->tx_ring[i]; 566 567 if (!ring->unaligned) 568 bgmac_dma_tx_enable(bgmac, ring); 569 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO, 570 lower_32_bits(ring->dma_base)); 571 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGHI, 572 upper_32_bits(ring->dma_base)); 573 if (ring->unaligned) 574 bgmac_dma_tx_enable(bgmac, ring); 575 576 ring->start = 0; 577 ring->end = 0; /* Points the slot that should *not* be read */ 578 } 579 580 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) { 581 int j; 582 583 ring = &bgmac->rx_ring[i]; 584 585 if (!ring->unaligned) 586 bgmac_dma_rx_enable(bgmac, ring); 587 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO, 588 lower_32_bits(ring->dma_base)); 589 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGHI, 590 upper_32_bits(ring->dma_base)); 591 if (ring->unaligned) 592 bgmac_dma_rx_enable(bgmac, ring); 593 594 for (j = 0; j < ring->num_slots; j++) 595 bgmac_dma_rx_setup_desc(bgmac, ring, j); 596 597 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_INDEX, 598 ring->index_base + 599 ring->num_slots * sizeof(struct bgmac_dma_desc)); 600 601 ring->start = 0; 602 ring->end = 0; 603 } 604 } 605 606 /************************************************** 607 * PHY ops 608 **************************************************/ 609 610 static u16 bgmac_phy_read(struct bgmac *bgmac, u8 phyaddr, u8 reg) 611 { 612 struct bcma_device *core; 613 u16 phy_access_addr; 614 u16 phy_ctl_addr; 615 u32 tmp; 616 617 BUILD_BUG_ON(BGMAC_PA_DATA_MASK != BCMA_GMAC_CMN_PA_DATA_MASK); 618 BUILD_BUG_ON(BGMAC_PA_ADDR_MASK != BCMA_GMAC_CMN_PA_ADDR_MASK); 619 BUILD_BUG_ON(BGMAC_PA_ADDR_SHIFT != BCMA_GMAC_CMN_PA_ADDR_SHIFT); 620 BUILD_BUG_ON(BGMAC_PA_REG_MASK != BCMA_GMAC_CMN_PA_REG_MASK); 621 BUILD_BUG_ON(BGMAC_PA_REG_SHIFT != BCMA_GMAC_CMN_PA_REG_SHIFT); 622 BUILD_BUG_ON(BGMAC_PA_WRITE != BCMA_GMAC_CMN_PA_WRITE); 623 BUILD_BUG_ON(BGMAC_PA_START != BCMA_GMAC_CMN_PA_START); 624 BUILD_BUG_ON(BGMAC_PC_EPA_MASK != BCMA_GMAC_CMN_PC_EPA_MASK); 625 BUILD_BUG_ON(BGMAC_PC_MCT_MASK != BCMA_GMAC_CMN_PC_MCT_MASK); 626 BUILD_BUG_ON(BGMAC_PC_MCT_SHIFT != BCMA_GMAC_CMN_PC_MCT_SHIFT); 627 BUILD_BUG_ON(BGMAC_PC_MTE != BCMA_GMAC_CMN_PC_MTE); 628 629 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) { 630 core = bgmac->core->bus->drv_gmac_cmn.core; 631 phy_access_addr = BCMA_GMAC_CMN_PHY_ACCESS; 632 phy_ctl_addr = BCMA_GMAC_CMN_PHY_CTL; 633 } else { 634 core = bgmac->core; 635 phy_access_addr = BGMAC_PHY_ACCESS; 636 phy_ctl_addr = BGMAC_PHY_CNTL; 637 } 638 639 tmp = bcma_read32(core, phy_ctl_addr); 640 tmp &= ~BGMAC_PC_EPA_MASK; 641 tmp |= phyaddr; 642 bcma_write32(core, phy_ctl_addr, tmp); 643 644 tmp = BGMAC_PA_START; 645 tmp |= phyaddr << BGMAC_PA_ADDR_SHIFT; 646 tmp |= reg << BGMAC_PA_REG_SHIFT; 647 bcma_write32(core, phy_access_addr, tmp); 648 649 if (!bgmac_wait_value(core, phy_access_addr, BGMAC_PA_START, 0, 1000)) { 650 bgmac_err(bgmac, "Reading PHY %d register 0x%X failed\n", 651 phyaddr, reg); 652 return 0xffff; 653 } 654 655 return bcma_read32(core, phy_access_addr) & BGMAC_PA_DATA_MASK; 656 } 657 658 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphywr */ 659 static int bgmac_phy_write(struct bgmac *bgmac, u8 phyaddr, u8 reg, u16 value) 660 { 661 struct bcma_device *core; 662 u16 phy_access_addr; 663 u16 phy_ctl_addr; 664 u32 tmp; 665 666 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) { 667 core = bgmac->core->bus->drv_gmac_cmn.core; 668 phy_access_addr = BCMA_GMAC_CMN_PHY_ACCESS; 669 phy_ctl_addr = BCMA_GMAC_CMN_PHY_CTL; 670 } else { 671 core = bgmac->core; 672 phy_access_addr = BGMAC_PHY_ACCESS; 673 phy_ctl_addr = BGMAC_PHY_CNTL; 674 } 675 676 tmp = bcma_read32(core, phy_ctl_addr); 677 tmp &= ~BGMAC_PC_EPA_MASK; 678 tmp |= phyaddr; 679 bcma_write32(core, phy_ctl_addr, tmp); 680 681 bgmac_write(bgmac, BGMAC_INT_STATUS, BGMAC_IS_MDIO); 682 if (bgmac_read(bgmac, BGMAC_INT_STATUS) & BGMAC_IS_MDIO) 683 bgmac_warn(bgmac, "Error setting MDIO int\n"); 684 685 tmp = BGMAC_PA_START; 686 tmp |= BGMAC_PA_WRITE; 687 tmp |= phyaddr << BGMAC_PA_ADDR_SHIFT; 688 tmp |= reg << BGMAC_PA_REG_SHIFT; 689 tmp |= value; 690 bcma_write32(core, phy_access_addr, tmp); 691 692 if (!bgmac_wait_value(core, phy_access_addr, BGMAC_PA_START, 0, 1000)) { 693 bgmac_err(bgmac, "Writing to PHY %d register 0x%X failed\n", 694 phyaddr, reg); 695 return -ETIMEDOUT; 696 } 697 698 return 0; 699 } 700 701 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyinit */ 702 static void bgmac_phy_init(struct bgmac *bgmac) 703 { 704 struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo; 705 struct bcma_drv_cc *cc = &bgmac->core->bus->drv_cc; 706 u8 i; 707 708 if (ci->id == BCMA_CHIP_ID_BCM5356) { 709 for (i = 0; i < 5; i++) { 710 bgmac_phy_write(bgmac, i, 0x1f, 0x008b); 711 bgmac_phy_write(bgmac, i, 0x15, 0x0100); 712 bgmac_phy_write(bgmac, i, 0x1f, 0x000f); 713 bgmac_phy_write(bgmac, i, 0x12, 0x2aaa); 714 bgmac_phy_write(bgmac, i, 0x1f, 0x000b); 715 } 716 } 717 if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg != 10) || 718 (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg != 10) || 719 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg != 9)) { 720 bcma_chipco_chipctl_maskset(cc, 2, ~0xc0000000, 0); 721 bcma_chipco_chipctl_maskset(cc, 4, ~0x80000000, 0); 722 for (i = 0; i < 5; i++) { 723 bgmac_phy_write(bgmac, i, 0x1f, 0x000f); 724 bgmac_phy_write(bgmac, i, 0x16, 0x5284); 725 bgmac_phy_write(bgmac, i, 0x1f, 0x000b); 726 bgmac_phy_write(bgmac, i, 0x17, 0x0010); 727 bgmac_phy_write(bgmac, i, 0x1f, 0x000f); 728 bgmac_phy_write(bgmac, i, 0x16, 0x5296); 729 bgmac_phy_write(bgmac, i, 0x17, 0x1073); 730 bgmac_phy_write(bgmac, i, 0x17, 0x9073); 731 bgmac_phy_write(bgmac, i, 0x16, 0x52b6); 732 bgmac_phy_write(bgmac, i, 0x17, 0x9273); 733 bgmac_phy_write(bgmac, i, 0x1f, 0x000b); 734 } 735 } 736 } 737 738 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyreset */ 739 static void bgmac_phy_reset(struct bgmac *bgmac) 740 { 741 if (bgmac->phyaddr == BGMAC_PHY_NOREGS) 742 return; 743 744 bgmac_phy_write(bgmac, bgmac->phyaddr, MII_BMCR, BMCR_RESET); 745 udelay(100); 746 if (bgmac_phy_read(bgmac, bgmac->phyaddr, MII_BMCR) & BMCR_RESET) 747 bgmac_err(bgmac, "PHY reset failed\n"); 748 bgmac_phy_init(bgmac); 749 } 750 751 /************************************************** 752 * Chip ops 753 **************************************************/ 754 755 /* TODO: can we just drop @force? Can we don't reset MAC at all if there is 756 * nothing to change? Try if after stabilizng driver. 757 */ 758 static void bgmac_cmdcfg_maskset(struct bgmac *bgmac, u32 mask, u32 set, 759 bool force) 760 { 761 u32 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG); 762 u32 new_val = (cmdcfg & mask) | set; 763 764 bgmac_set(bgmac, BGMAC_CMDCFG, BGMAC_CMDCFG_SR(bgmac->core->id.rev)); 765 udelay(2); 766 767 if (new_val != cmdcfg || force) 768 bgmac_write(bgmac, BGMAC_CMDCFG, new_val); 769 770 bgmac_mask(bgmac, BGMAC_CMDCFG, ~BGMAC_CMDCFG_SR(bgmac->core->id.rev)); 771 udelay(2); 772 } 773 774 static void bgmac_write_mac_address(struct bgmac *bgmac, u8 *addr) 775 { 776 u32 tmp; 777 778 tmp = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]; 779 bgmac_write(bgmac, BGMAC_MACADDR_HIGH, tmp); 780 tmp = (addr[4] << 8) | addr[5]; 781 bgmac_write(bgmac, BGMAC_MACADDR_LOW, tmp); 782 } 783 784 static void bgmac_set_rx_mode(struct net_device *net_dev) 785 { 786 struct bgmac *bgmac = netdev_priv(net_dev); 787 788 if (net_dev->flags & IFF_PROMISC) 789 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_PROM, true); 790 else 791 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_PROM, 0, true); 792 } 793 794 #if 0 /* We don't use that regs yet */ 795 static void bgmac_chip_stats_update(struct bgmac *bgmac) 796 { 797 int i; 798 799 if (bgmac->core->id.id != BCMA_CORE_4706_MAC_GBIT) { 800 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++) 801 bgmac->mib_tx_regs[i] = 802 bgmac_read(bgmac, 803 BGMAC_TX_GOOD_OCTETS + (i * 4)); 804 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++) 805 bgmac->mib_rx_regs[i] = 806 bgmac_read(bgmac, 807 BGMAC_RX_GOOD_OCTETS + (i * 4)); 808 } 809 810 /* TODO: what else? how to handle BCM4706? Specs are needed */ 811 } 812 #endif 813 814 static void bgmac_clear_mib(struct bgmac *bgmac) 815 { 816 int i; 817 818 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) 819 return; 820 821 bgmac_set(bgmac, BGMAC_DEV_CTL, BGMAC_DC_MROR); 822 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++) 823 bgmac_read(bgmac, BGMAC_TX_GOOD_OCTETS + (i * 4)); 824 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++) 825 bgmac_read(bgmac, BGMAC_RX_GOOD_OCTETS + (i * 4)); 826 } 827 828 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_speed */ 829 static void bgmac_mac_speed(struct bgmac *bgmac) 830 { 831 u32 mask = ~(BGMAC_CMDCFG_ES_MASK | BGMAC_CMDCFG_HD); 832 u32 set = 0; 833 834 switch (bgmac->mac_speed) { 835 case SPEED_10: 836 set |= BGMAC_CMDCFG_ES_10; 837 break; 838 case SPEED_100: 839 set |= BGMAC_CMDCFG_ES_100; 840 break; 841 case SPEED_1000: 842 set |= BGMAC_CMDCFG_ES_1000; 843 break; 844 case SPEED_2500: 845 set |= BGMAC_CMDCFG_ES_2500; 846 break; 847 default: 848 bgmac_err(bgmac, "Unsupported speed: %d\n", bgmac->mac_speed); 849 } 850 851 if (bgmac->mac_duplex == DUPLEX_HALF) 852 set |= BGMAC_CMDCFG_HD; 853 854 bgmac_cmdcfg_maskset(bgmac, mask, set, true); 855 } 856 857 static void bgmac_miiconfig(struct bgmac *bgmac) 858 { 859 struct bcma_device *core = bgmac->core; 860 struct bcma_chipinfo *ci = &core->bus->chipinfo; 861 u8 imode; 862 863 if (ci->id == BCMA_CHIP_ID_BCM4707 || 864 ci->id == BCMA_CHIP_ID_BCM53018) { 865 bcma_awrite32(core, BCMA_IOCTL, 866 bcma_aread32(core, BCMA_IOCTL) | 0x40 | 867 BGMAC_BCMA_IOCTL_SW_CLKEN); 868 bgmac->mac_speed = SPEED_2500; 869 bgmac->mac_duplex = DUPLEX_FULL; 870 bgmac_mac_speed(bgmac); 871 } else { 872 imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & 873 BGMAC_DS_MM_MASK) >> BGMAC_DS_MM_SHIFT; 874 if (imode == 0 || imode == 1) { 875 bgmac->mac_speed = SPEED_100; 876 bgmac->mac_duplex = DUPLEX_FULL; 877 bgmac_mac_speed(bgmac); 878 } 879 } 880 } 881 882 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipreset */ 883 static void bgmac_chip_reset(struct bgmac *bgmac) 884 { 885 struct bcma_device *core = bgmac->core; 886 struct bcma_bus *bus = core->bus; 887 struct bcma_chipinfo *ci = &bus->chipinfo; 888 u32 flags; 889 u32 iost; 890 int i; 891 892 if (bcma_core_is_enabled(core)) { 893 if (!bgmac->stats_grabbed) { 894 /* bgmac_chip_stats_update(bgmac); */ 895 bgmac->stats_grabbed = true; 896 } 897 898 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) 899 bgmac_dma_tx_reset(bgmac, &bgmac->tx_ring[i]); 900 901 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false); 902 udelay(1); 903 904 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) 905 bgmac_dma_rx_reset(bgmac, &bgmac->rx_ring[i]); 906 907 /* TODO: Clear software multicast filter list */ 908 } 909 910 iost = bcma_aread32(core, BCMA_IOST); 911 if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM47186) || 912 (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg == 10) || 913 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == BCMA_PKG_ID_BCM47188)) 914 iost &= ~BGMAC_BCMA_IOST_ATTACHED; 915 916 /* 3GMAC: for BCM4707, only do core reset at bgmac_probe() */ 917 if (ci->id != BCMA_CHIP_ID_BCM4707) { 918 flags = 0; 919 if (iost & BGMAC_BCMA_IOST_ATTACHED) { 920 flags = BGMAC_BCMA_IOCTL_SW_CLKEN; 921 if (!bgmac->has_robosw) 922 flags |= BGMAC_BCMA_IOCTL_SW_RESET; 923 } 924 bcma_core_enable(core, flags); 925 } 926 927 /* Request Misc PLL for corerev > 2 */ 928 if (core->id.rev > 2 && 929 ci->id != BCMA_CHIP_ID_BCM4707 && 930 ci->id != BCMA_CHIP_ID_BCM53018) { 931 bgmac_set(bgmac, BCMA_CLKCTLST, 932 BGMAC_BCMA_CLKCTLST_MISC_PLL_REQ); 933 bgmac_wait_value(bgmac->core, BCMA_CLKCTLST, 934 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST, 935 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST, 936 1000); 937 } 938 939 if (ci->id == BCMA_CHIP_ID_BCM5357 || 940 ci->id == BCMA_CHIP_ID_BCM4749 || 941 ci->id == BCMA_CHIP_ID_BCM53572) { 942 struct bcma_drv_cc *cc = &bgmac->core->bus->drv_cc; 943 u8 et_swtype = 0; 944 u8 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHY | 945 BGMAC_CHIPCTL_1_IF_TYPE_MII; 946 char buf[4]; 947 948 if (bcm47xx_nvram_getenv("et_swtype", buf, sizeof(buf)) > 0) { 949 if (kstrtou8(buf, 0, &et_swtype)) 950 bgmac_err(bgmac, "Failed to parse et_swtype (%s)\n", 951 buf); 952 et_swtype &= 0x0f; 953 et_swtype <<= 4; 954 sw_type = et_swtype; 955 } else if (ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM5358) { 956 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII; 957 } else if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM47186) || 958 (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg == 10) || 959 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == BCMA_PKG_ID_BCM47188)) { 960 sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RGMII | 961 BGMAC_CHIPCTL_1_SW_TYPE_RGMII; 962 } 963 bcma_chipco_chipctl_maskset(cc, 1, 964 ~(BGMAC_CHIPCTL_1_IF_TYPE_MASK | 965 BGMAC_CHIPCTL_1_SW_TYPE_MASK), 966 sw_type); 967 } 968 969 if (iost & BGMAC_BCMA_IOST_ATTACHED && !bgmac->has_robosw) 970 bcma_awrite32(core, BCMA_IOCTL, 971 bcma_aread32(core, BCMA_IOCTL) & 972 ~BGMAC_BCMA_IOCTL_SW_RESET); 973 974 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_reset 975 * Specs don't say about using BGMAC_CMDCFG_SR, but in this routine 976 * BGMAC_CMDCFG is read _after_ putting chip in a reset. So it has to 977 * be keps until taking MAC out of the reset. 978 */ 979 bgmac_cmdcfg_maskset(bgmac, 980 ~(BGMAC_CMDCFG_TE | 981 BGMAC_CMDCFG_RE | 982 BGMAC_CMDCFG_RPI | 983 BGMAC_CMDCFG_TAI | 984 BGMAC_CMDCFG_HD | 985 BGMAC_CMDCFG_ML | 986 BGMAC_CMDCFG_CFE | 987 BGMAC_CMDCFG_RL | 988 BGMAC_CMDCFG_RED | 989 BGMAC_CMDCFG_PE | 990 BGMAC_CMDCFG_TPI | 991 BGMAC_CMDCFG_PAD_EN | 992 BGMAC_CMDCFG_PF), 993 BGMAC_CMDCFG_PROM | 994 BGMAC_CMDCFG_NLC | 995 BGMAC_CMDCFG_CFE | 996 BGMAC_CMDCFG_SR(core->id.rev), 997 false); 998 bgmac->mac_speed = SPEED_UNKNOWN; 999 bgmac->mac_duplex = DUPLEX_UNKNOWN; 1000 1001 bgmac_clear_mib(bgmac); 1002 if (core->id.id == BCMA_CORE_4706_MAC_GBIT) 1003 bcma_maskset32(bgmac->cmn, BCMA_GMAC_CMN_PHY_CTL, ~0, 1004 BCMA_GMAC_CMN_PC_MTE); 1005 else 1006 bgmac_set(bgmac, BGMAC_PHY_CNTL, BGMAC_PC_MTE); 1007 bgmac_miiconfig(bgmac); 1008 bgmac_phy_init(bgmac); 1009 1010 netdev_reset_queue(bgmac->net_dev); 1011 1012 bgmac->int_status = 0; 1013 } 1014 1015 static void bgmac_chip_intrs_on(struct bgmac *bgmac) 1016 { 1017 bgmac_write(bgmac, BGMAC_INT_MASK, bgmac->int_mask); 1018 } 1019 1020 static void bgmac_chip_intrs_off(struct bgmac *bgmac) 1021 { 1022 bgmac_write(bgmac, BGMAC_INT_MASK, 0); 1023 bgmac_read(bgmac, BGMAC_INT_MASK); 1024 } 1025 1026 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_enable */ 1027 static void bgmac_enable(struct bgmac *bgmac) 1028 { 1029 struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo; 1030 u32 cmdcfg; 1031 u32 mode; 1032 u32 rxq_ctl; 1033 u32 fl_ctl; 1034 u16 bp_clk; 1035 u8 mdp; 1036 1037 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG); 1038 bgmac_cmdcfg_maskset(bgmac, ~(BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE), 1039 BGMAC_CMDCFG_SR(bgmac->core->id.rev), true); 1040 udelay(2); 1041 cmdcfg |= BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE; 1042 bgmac_write(bgmac, BGMAC_CMDCFG, cmdcfg); 1043 1044 mode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >> 1045 BGMAC_DS_MM_SHIFT; 1046 if (ci->id != BCMA_CHIP_ID_BCM47162 || mode != 0) 1047 bgmac_set(bgmac, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT); 1048 if (ci->id == BCMA_CHIP_ID_BCM47162 && mode == 2) 1049 bcma_chipco_chipctl_maskset(&bgmac->core->bus->drv_cc, 1, ~0, 1050 BGMAC_CHIPCTL_1_RXC_DLL_BYPASS); 1051 1052 switch (ci->id) { 1053 case BCMA_CHIP_ID_BCM5357: 1054 case BCMA_CHIP_ID_BCM4749: 1055 case BCMA_CHIP_ID_BCM53572: 1056 case BCMA_CHIP_ID_BCM4716: 1057 case BCMA_CHIP_ID_BCM47162: 1058 fl_ctl = 0x03cb04cb; 1059 if (ci->id == BCMA_CHIP_ID_BCM5357 || 1060 ci->id == BCMA_CHIP_ID_BCM4749 || 1061 ci->id == BCMA_CHIP_ID_BCM53572) 1062 fl_ctl = 0x2300e1; 1063 bgmac_write(bgmac, BGMAC_FLOW_CTL_THRESH, fl_ctl); 1064 bgmac_write(bgmac, BGMAC_PAUSE_CTL, 0x27fff); 1065 break; 1066 } 1067 1068 if (ci->id != BCMA_CHIP_ID_BCM4707 && 1069 ci->id != BCMA_CHIP_ID_BCM53018) { 1070 rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL); 1071 rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK; 1072 bp_clk = bcma_pmu_get_bus_clock(&bgmac->core->bus->drv_cc) / 1073 1000000; 1074 mdp = (bp_clk * 128 / 1000) - 3; 1075 rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT); 1076 bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl); 1077 } 1078 } 1079 1080 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */ 1081 static void bgmac_chip_init(struct bgmac *bgmac, bool full_init) 1082 { 1083 struct bgmac_dma_ring *ring; 1084 int i; 1085 1086 /* 1 interrupt per received frame */ 1087 bgmac_write(bgmac, BGMAC_INT_RECV_LAZY, 1 << BGMAC_IRL_FC_SHIFT); 1088 1089 /* Enable 802.3x tx flow control (honor received PAUSE frames) */ 1090 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_RPI, 0, true); 1091 1092 bgmac_set_rx_mode(bgmac->net_dev); 1093 1094 bgmac_write_mac_address(bgmac, bgmac->net_dev->dev_addr); 1095 1096 if (bgmac->loopback) 1097 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false); 1098 else 1099 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_ML, 0, false); 1100 1101 bgmac_write(bgmac, BGMAC_RXMAX_LENGTH, 32 + ETHER_MAX_LEN); 1102 1103 if (full_init) { 1104 bgmac_dma_init(bgmac); 1105 if (1) /* FIXME: is there any case we don't want IRQs? */ 1106 bgmac_chip_intrs_on(bgmac); 1107 } else { 1108 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) { 1109 ring = &bgmac->rx_ring[i]; 1110 bgmac_dma_rx_enable(bgmac, ring); 1111 } 1112 } 1113 1114 bgmac_enable(bgmac); 1115 } 1116 1117 static irqreturn_t bgmac_interrupt(int irq, void *dev_id) 1118 { 1119 struct bgmac *bgmac = netdev_priv(dev_id); 1120 1121 u32 int_status = bgmac_read(bgmac, BGMAC_INT_STATUS); 1122 int_status &= bgmac->int_mask; 1123 1124 if (!int_status) 1125 return IRQ_NONE; 1126 1127 /* Ack */ 1128 bgmac_write(bgmac, BGMAC_INT_STATUS, int_status); 1129 1130 /* Disable new interrupts until handling existing ones */ 1131 bgmac_chip_intrs_off(bgmac); 1132 1133 bgmac->int_status = int_status; 1134 1135 napi_schedule(&bgmac->napi); 1136 1137 return IRQ_HANDLED; 1138 } 1139 1140 static int bgmac_poll(struct napi_struct *napi, int weight) 1141 { 1142 struct bgmac *bgmac = container_of(napi, struct bgmac, napi); 1143 struct bgmac_dma_ring *ring; 1144 int handled = 0; 1145 1146 if (bgmac->int_status & BGMAC_IS_TX0) { 1147 ring = &bgmac->tx_ring[0]; 1148 bgmac_dma_tx_free(bgmac, ring); 1149 bgmac->int_status &= ~BGMAC_IS_TX0; 1150 } 1151 1152 if (bgmac->int_status & BGMAC_IS_RX) { 1153 ring = &bgmac->rx_ring[0]; 1154 handled += bgmac_dma_rx_read(bgmac, ring, weight); 1155 bgmac->int_status &= ~BGMAC_IS_RX; 1156 } 1157 1158 if (bgmac->int_status) { 1159 bgmac_err(bgmac, "Unknown IRQs: 0x%08X\n", bgmac->int_status); 1160 bgmac->int_status = 0; 1161 } 1162 1163 if (handled < weight) { 1164 napi_complete(napi); 1165 bgmac_chip_intrs_on(bgmac); 1166 } 1167 1168 return handled; 1169 } 1170 1171 /************************************************** 1172 * net_device_ops 1173 **************************************************/ 1174 1175 static int bgmac_open(struct net_device *net_dev) 1176 { 1177 struct bgmac *bgmac = netdev_priv(net_dev); 1178 int err = 0; 1179 1180 bgmac_chip_reset(bgmac); 1181 /* Specs say about reclaiming rings here, but we do that in DMA init */ 1182 bgmac_chip_init(bgmac, true); 1183 1184 err = request_irq(bgmac->core->irq, bgmac_interrupt, IRQF_SHARED, 1185 KBUILD_MODNAME, net_dev); 1186 if (err < 0) { 1187 bgmac_err(bgmac, "IRQ request error: %d!\n", err); 1188 goto err_out; 1189 } 1190 napi_enable(&bgmac->napi); 1191 1192 phy_start(bgmac->phy_dev); 1193 1194 netif_carrier_on(net_dev); 1195 1196 err_out: 1197 return err; 1198 } 1199 1200 static int bgmac_stop(struct net_device *net_dev) 1201 { 1202 struct bgmac *bgmac = netdev_priv(net_dev); 1203 1204 netif_carrier_off(net_dev); 1205 1206 phy_stop(bgmac->phy_dev); 1207 1208 napi_disable(&bgmac->napi); 1209 bgmac_chip_intrs_off(bgmac); 1210 free_irq(bgmac->core->irq, net_dev); 1211 1212 bgmac_chip_reset(bgmac); 1213 1214 return 0; 1215 } 1216 1217 static netdev_tx_t bgmac_start_xmit(struct sk_buff *skb, 1218 struct net_device *net_dev) 1219 { 1220 struct bgmac *bgmac = netdev_priv(net_dev); 1221 struct bgmac_dma_ring *ring; 1222 1223 /* No QOS support yet */ 1224 ring = &bgmac->tx_ring[0]; 1225 return bgmac_dma_tx_add(bgmac, ring, skb); 1226 } 1227 1228 static int bgmac_set_mac_address(struct net_device *net_dev, void *addr) 1229 { 1230 struct bgmac *bgmac = netdev_priv(net_dev); 1231 int ret; 1232 1233 ret = eth_prepare_mac_addr_change(net_dev, addr); 1234 if (ret < 0) 1235 return ret; 1236 bgmac_write_mac_address(bgmac, (u8 *)addr); 1237 eth_commit_mac_addr_change(net_dev, addr); 1238 return 0; 1239 } 1240 1241 static int bgmac_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) 1242 { 1243 struct bgmac *bgmac = netdev_priv(net_dev); 1244 1245 if (!netif_running(net_dev)) 1246 return -EINVAL; 1247 1248 return phy_mii_ioctl(bgmac->phy_dev, ifr, cmd); 1249 } 1250 1251 static const struct net_device_ops bgmac_netdev_ops = { 1252 .ndo_open = bgmac_open, 1253 .ndo_stop = bgmac_stop, 1254 .ndo_start_xmit = bgmac_start_xmit, 1255 .ndo_set_rx_mode = bgmac_set_rx_mode, 1256 .ndo_set_mac_address = bgmac_set_mac_address, 1257 .ndo_validate_addr = eth_validate_addr, 1258 .ndo_do_ioctl = bgmac_ioctl, 1259 }; 1260 1261 /************************************************** 1262 * ethtool_ops 1263 **************************************************/ 1264 1265 static int bgmac_get_settings(struct net_device *net_dev, 1266 struct ethtool_cmd *cmd) 1267 { 1268 struct bgmac *bgmac = netdev_priv(net_dev); 1269 1270 return phy_ethtool_gset(bgmac->phy_dev, cmd); 1271 } 1272 1273 static int bgmac_set_settings(struct net_device *net_dev, 1274 struct ethtool_cmd *cmd) 1275 { 1276 struct bgmac *bgmac = netdev_priv(net_dev); 1277 1278 return phy_ethtool_sset(bgmac->phy_dev, cmd); 1279 } 1280 1281 static void bgmac_get_drvinfo(struct net_device *net_dev, 1282 struct ethtool_drvinfo *info) 1283 { 1284 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver)); 1285 strlcpy(info->bus_info, "BCMA", sizeof(info->bus_info)); 1286 } 1287 1288 static const struct ethtool_ops bgmac_ethtool_ops = { 1289 .get_settings = bgmac_get_settings, 1290 .set_settings = bgmac_set_settings, 1291 .get_drvinfo = bgmac_get_drvinfo, 1292 }; 1293 1294 /************************************************** 1295 * MII 1296 **************************************************/ 1297 1298 static int bgmac_mii_read(struct mii_bus *bus, int mii_id, int regnum) 1299 { 1300 return bgmac_phy_read(bus->priv, mii_id, regnum); 1301 } 1302 1303 static int bgmac_mii_write(struct mii_bus *bus, int mii_id, int regnum, 1304 u16 value) 1305 { 1306 return bgmac_phy_write(bus->priv, mii_id, regnum, value); 1307 } 1308 1309 static void bgmac_adjust_link(struct net_device *net_dev) 1310 { 1311 struct bgmac *bgmac = netdev_priv(net_dev); 1312 struct phy_device *phy_dev = bgmac->phy_dev; 1313 bool update = false; 1314 1315 if (phy_dev->link) { 1316 if (phy_dev->speed != bgmac->mac_speed) { 1317 bgmac->mac_speed = phy_dev->speed; 1318 update = true; 1319 } 1320 1321 if (phy_dev->duplex != bgmac->mac_duplex) { 1322 bgmac->mac_duplex = phy_dev->duplex; 1323 update = true; 1324 } 1325 } 1326 1327 if (update) { 1328 bgmac_mac_speed(bgmac); 1329 phy_print_status(phy_dev); 1330 } 1331 } 1332 1333 static int bgmac_mii_register(struct bgmac *bgmac) 1334 { 1335 struct mii_bus *mii_bus; 1336 struct phy_device *phy_dev; 1337 char bus_id[MII_BUS_ID_SIZE + 3]; 1338 int i, err = 0; 1339 1340 mii_bus = mdiobus_alloc(); 1341 if (!mii_bus) 1342 return -ENOMEM; 1343 1344 mii_bus->name = "bgmac mii bus"; 1345 sprintf(mii_bus->id, "%s-%d-%d", "bgmac", bgmac->core->bus->num, 1346 bgmac->core->core_unit); 1347 mii_bus->priv = bgmac; 1348 mii_bus->read = bgmac_mii_read; 1349 mii_bus->write = bgmac_mii_write; 1350 mii_bus->parent = &bgmac->core->dev; 1351 mii_bus->phy_mask = ~(1 << bgmac->phyaddr); 1352 1353 mii_bus->irq = kmalloc_array(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL); 1354 if (!mii_bus->irq) { 1355 err = -ENOMEM; 1356 goto err_free_bus; 1357 } 1358 for (i = 0; i < PHY_MAX_ADDR; i++) 1359 mii_bus->irq[i] = PHY_POLL; 1360 1361 err = mdiobus_register(mii_bus); 1362 if (err) { 1363 bgmac_err(bgmac, "Registration of mii bus failed\n"); 1364 goto err_free_irq; 1365 } 1366 1367 bgmac->mii_bus = mii_bus; 1368 1369 /* Connect to the PHY */ 1370 snprintf(bus_id, sizeof(bus_id), PHY_ID_FMT, mii_bus->id, 1371 bgmac->phyaddr); 1372 phy_dev = phy_connect(bgmac->net_dev, bus_id, &bgmac_adjust_link, 1373 PHY_INTERFACE_MODE_MII); 1374 if (IS_ERR(phy_dev)) { 1375 bgmac_err(bgmac, "PHY connecton failed\n"); 1376 err = PTR_ERR(phy_dev); 1377 goto err_unregister_bus; 1378 } 1379 bgmac->phy_dev = phy_dev; 1380 1381 return err; 1382 1383 err_unregister_bus: 1384 mdiobus_unregister(mii_bus); 1385 err_free_irq: 1386 kfree(mii_bus->irq); 1387 err_free_bus: 1388 mdiobus_free(mii_bus); 1389 return err; 1390 } 1391 1392 static void bgmac_mii_unregister(struct bgmac *bgmac) 1393 { 1394 struct mii_bus *mii_bus = bgmac->mii_bus; 1395 1396 mdiobus_unregister(mii_bus); 1397 kfree(mii_bus->irq); 1398 mdiobus_free(mii_bus); 1399 } 1400 1401 /************************************************** 1402 * BCMA bus ops 1403 **************************************************/ 1404 1405 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipattach */ 1406 static int bgmac_probe(struct bcma_device *core) 1407 { 1408 struct bcma_chipinfo *ci = &core->bus->chipinfo; 1409 struct net_device *net_dev; 1410 struct bgmac *bgmac; 1411 struct ssb_sprom *sprom = &core->bus->sprom; 1412 u8 *mac = core->core_unit ? sprom->et1mac : sprom->et0mac; 1413 int err; 1414 1415 /* We don't support 2nd, 3rd, ... units, SPROM has to be adjusted */ 1416 if (core->core_unit > 1) { 1417 pr_err("Unsupported core_unit %d\n", core->core_unit); 1418 return -ENOTSUPP; 1419 } 1420 1421 if (!is_valid_ether_addr(mac)) { 1422 dev_err(&core->dev, "Invalid MAC addr: %pM\n", mac); 1423 eth_random_addr(mac); 1424 dev_warn(&core->dev, "Using random MAC: %pM\n", mac); 1425 } 1426 1427 /* Allocation and references */ 1428 net_dev = alloc_etherdev(sizeof(*bgmac)); 1429 if (!net_dev) 1430 return -ENOMEM; 1431 net_dev->netdev_ops = &bgmac_netdev_ops; 1432 net_dev->irq = core->irq; 1433 net_dev->ethtool_ops = &bgmac_ethtool_ops; 1434 bgmac = netdev_priv(net_dev); 1435 bgmac->net_dev = net_dev; 1436 bgmac->core = core; 1437 bcma_set_drvdata(core, bgmac); 1438 1439 /* Defaults */ 1440 memcpy(bgmac->net_dev->dev_addr, mac, ETH_ALEN); 1441 1442 /* On BCM4706 we need common core to access PHY */ 1443 if (core->id.id == BCMA_CORE_4706_MAC_GBIT && 1444 !core->bus->drv_gmac_cmn.core) { 1445 bgmac_err(bgmac, "GMAC CMN core not found (required for BCM4706)\n"); 1446 err = -ENODEV; 1447 goto err_netdev_free; 1448 } 1449 bgmac->cmn = core->bus->drv_gmac_cmn.core; 1450 1451 bgmac->phyaddr = core->core_unit ? sprom->et1phyaddr : 1452 sprom->et0phyaddr; 1453 bgmac->phyaddr &= BGMAC_PHY_MASK; 1454 if (bgmac->phyaddr == BGMAC_PHY_MASK) { 1455 bgmac_err(bgmac, "No PHY found\n"); 1456 err = -ENODEV; 1457 goto err_netdev_free; 1458 } 1459 bgmac_info(bgmac, "Found PHY addr: %d%s\n", bgmac->phyaddr, 1460 bgmac->phyaddr == BGMAC_PHY_NOREGS ? " (NOREGS)" : ""); 1461 1462 if (core->bus->hosttype == BCMA_HOSTTYPE_PCI) { 1463 bgmac_err(bgmac, "PCI setup not implemented\n"); 1464 err = -ENOTSUPP; 1465 goto err_netdev_free; 1466 } 1467 1468 bgmac_chip_reset(bgmac); 1469 1470 /* For Northstar, we have to take all GMAC core out of reset */ 1471 if (ci->id == BCMA_CHIP_ID_BCM4707 || 1472 ci->id == BCMA_CHIP_ID_BCM53018) { 1473 struct bcma_device *ns_core; 1474 int ns_gmac; 1475 1476 /* Northstar has 4 GMAC cores */ 1477 for (ns_gmac = 0; ns_gmac < 4; ns_gmac++) { 1478 /* As Northstar requirement, we have to reset all GMACs 1479 * before accessing one. bgmac_chip_reset() call 1480 * bcma_core_enable() for this core. Then the other 1481 * three GMACs didn't reset. We do it here. 1482 */ 1483 ns_core = bcma_find_core_unit(core->bus, 1484 BCMA_CORE_MAC_GBIT, 1485 ns_gmac); 1486 if (ns_core && !bcma_core_is_enabled(ns_core)) 1487 bcma_core_enable(ns_core, 0); 1488 } 1489 } 1490 1491 err = bgmac_dma_alloc(bgmac); 1492 if (err) { 1493 bgmac_err(bgmac, "Unable to alloc memory for DMA\n"); 1494 goto err_netdev_free; 1495 } 1496 1497 bgmac->int_mask = BGMAC_IS_ERRMASK | BGMAC_IS_RX | BGMAC_IS_TX_MASK; 1498 if (bcm47xx_nvram_getenv("et0_no_txint", NULL, 0) == 0) 1499 bgmac->int_mask &= ~BGMAC_IS_TX_MASK; 1500 1501 /* TODO: reset the external phy. Specs are needed */ 1502 bgmac_phy_reset(bgmac); 1503 1504 bgmac->has_robosw = !!(core->bus->sprom.boardflags_lo & 1505 BGMAC_BFL_ENETROBO); 1506 if (bgmac->has_robosw) 1507 bgmac_warn(bgmac, "Support for Roboswitch not implemented\n"); 1508 1509 if (core->bus->sprom.boardflags_lo & BGMAC_BFL_ENETADM) 1510 bgmac_warn(bgmac, "Support for ADMtek ethernet switch not implemented\n"); 1511 1512 netif_napi_add(net_dev, &bgmac->napi, bgmac_poll, BGMAC_WEIGHT); 1513 1514 err = bgmac_mii_register(bgmac); 1515 if (err) { 1516 bgmac_err(bgmac, "Cannot register MDIO\n"); 1517 goto err_dma_free; 1518 } 1519 1520 err = register_netdev(bgmac->net_dev); 1521 if (err) { 1522 bgmac_err(bgmac, "Cannot register net device\n"); 1523 goto err_mii_unregister; 1524 } 1525 1526 netif_carrier_off(net_dev); 1527 1528 return 0; 1529 1530 err_mii_unregister: 1531 bgmac_mii_unregister(bgmac); 1532 err_dma_free: 1533 bgmac_dma_free(bgmac); 1534 1535 err_netdev_free: 1536 bcma_set_drvdata(core, NULL); 1537 free_netdev(net_dev); 1538 1539 return err; 1540 } 1541 1542 static void bgmac_remove(struct bcma_device *core) 1543 { 1544 struct bgmac *bgmac = bcma_get_drvdata(core); 1545 1546 unregister_netdev(bgmac->net_dev); 1547 bgmac_mii_unregister(bgmac); 1548 netif_napi_del(&bgmac->napi); 1549 bgmac_dma_free(bgmac); 1550 bcma_set_drvdata(core, NULL); 1551 free_netdev(bgmac->net_dev); 1552 } 1553 1554 static struct bcma_driver bgmac_bcma_driver = { 1555 .name = KBUILD_MODNAME, 1556 .id_table = bgmac_bcma_tbl, 1557 .probe = bgmac_probe, 1558 .remove = bgmac_remove, 1559 }; 1560 1561 static int __init bgmac_init(void) 1562 { 1563 int err; 1564 1565 err = bcma_driver_register(&bgmac_bcma_driver); 1566 if (err) 1567 return err; 1568 pr_info("Broadcom 47xx GBit MAC driver loaded\n"); 1569 1570 return 0; 1571 } 1572 1573 static void __exit bgmac_exit(void) 1574 { 1575 bcma_driver_unregister(&bgmac_bcma_driver); 1576 } 1577 1578 module_init(bgmac_init) 1579 module_exit(bgmac_exit) 1580 1581 MODULE_AUTHOR("Rafał Miłecki"); 1582 MODULE_LICENSE("GPL"); 1583