1 /* 2 * Broadcom BCM7xxx System Port Ethernet MAC driver 3 * 4 * Copyright (C) 2014 Broadcom Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 12 13 #include <linux/init.h> 14 #include <linux/interrupt.h> 15 #include <linux/module.h> 16 #include <linux/kernel.h> 17 #include <linux/netdevice.h> 18 #include <linux/etherdevice.h> 19 #include <linux/platform_device.h> 20 #include <linux/of.h> 21 #include <linux/of_net.h> 22 #include <linux/of_mdio.h> 23 #include <linux/phy.h> 24 #include <linux/phy_fixed.h> 25 #include <net/ip.h> 26 #include <net/ipv6.h> 27 28 #include "bcmsysport.h" 29 30 /* I/O accessors register helpers */ 31 #define BCM_SYSPORT_IO_MACRO(name, offset) \ 32 static inline u32 name##_readl(struct bcm_sysport_priv *priv, u32 off) \ 33 { \ 34 u32 reg = __raw_readl(priv->base + offset + off); \ 35 return reg; \ 36 } \ 37 static inline void name##_writel(struct bcm_sysport_priv *priv, \ 38 u32 val, u32 off) \ 39 { \ 40 __raw_writel(val, priv->base + offset + off); \ 41 } \ 42 43 BCM_SYSPORT_IO_MACRO(intrl2_0, SYS_PORT_INTRL2_0_OFFSET); 44 BCM_SYSPORT_IO_MACRO(intrl2_1, SYS_PORT_INTRL2_1_OFFSET); 45 BCM_SYSPORT_IO_MACRO(umac, SYS_PORT_UMAC_OFFSET); 46 BCM_SYSPORT_IO_MACRO(gib, SYS_PORT_GIB_OFFSET); 47 BCM_SYSPORT_IO_MACRO(tdma, SYS_PORT_TDMA_OFFSET); 48 BCM_SYSPORT_IO_MACRO(rxchk, SYS_PORT_RXCHK_OFFSET); 49 BCM_SYSPORT_IO_MACRO(txchk, SYS_PORT_TXCHK_OFFSET); 50 BCM_SYSPORT_IO_MACRO(rbuf, SYS_PORT_RBUF_OFFSET); 51 BCM_SYSPORT_IO_MACRO(tbuf, SYS_PORT_TBUF_OFFSET); 52 BCM_SYSPORT_IO_MACRO(topctrl, SYS_PORT_TOPCTRL_OFFSET); 53 54 /* On SYSTEMPORT Lite, any register after RDMA_STATUS has the exact 55 * same layout, except it has been moved by 4 bytes up, *sigh* 56 */ 57 static inline u32 rdma_readl(struct bcm_sysport_priv *priv, u32 off) 58 { 59 if (priv->is_lite && off >= RDMA_STATUS) 60 off += 4; 61 return __raw_readl(priv->base + SYS_PORT_RDMA_OFFSET + off); 62 } 63 64 static inline void rdma_writel(struct bcm_sysport_priv *priv, u32 val, u32 off) 65 { 66 if (priv->is_lite && off >= RDMA_STATUS) 67 off += 4; 68 __raw_writel(val, priv->base + SYS_PORT_RDMA_OFFSET + off); 69 } 70 71 static inline u32 tdma_control_bit(struct bcm_sysport_priv *priv, u32 bit) 72 { 73 if (!priv->is_lite) { 74 return BIT(bit); 75 } else { 76 if (bit >= ACB_ALGO) 77 return BIT(bit + 1); 78 else 79 return BIT(bit); 80 } 81 } 82 83 /* L2-interrupt masking/unmasking helpers, does automatic saving of the applied 84 * mask in a software copy to avoid CPU_MASK_STATUS reads in hot-paths. 85 */ 86 #define BCM_SYSPORT_INTR_L2(which) \ 87 static inline void intrl2_##which##_mask_clear(struct bcm_sysport_priv *priv, \ 88 u32 mask) \ 89 { \ 90 priv->irq##which##_mask &= ~(mask); \ 91 intrl2_##which##_writel(priv, mask, INTRL2_CPU_MASK_CLEAR); \ 92 } \ 93 static inline void intrl2_##which##_mask_set(struct bcm_sysport_priv *priv, \ 94 u32 mask) \ 95 { \ 96 intrl2_## which##_writel(priv, mask, INTRL2_CPU_MASK_SET); \ 97 priv->irq##which##_mask |= (mask); \ 98 } \ 99 100 BCM_SYSPORT_INTR_L2(0) 101 BCM_SYSPORT_INTR_L2(1) 102 103 /* Register accesses to GISB/RBUS registers are expensive (few hundred 104 * nanoseconds), so keep the check for 64-bits explicit here to save 105 * one register write per-packet on 32-bits platforms. 106 */ 107 static inline void dma_desc_set_addr(struct bcm_sysport_priv *priv, 108 void __iomem *d, 109 dma_addr_t addr) 110 { 111 #ifdef CONFIG_PHYS_ADDR_T_64BIT 112 __raw_writel(upper_32_bits(addr) & DESC_ADDR_HI_MASK, 113 d + DESC_ADDR_HI_STATUS_LEN); 114 #endif 115 __raw_writel(lower_32_bits(addr), d + DESC_ADDR_LO); 116 } 117 118 static inline void tdma_port_write_desc_addr(struct bcm_sysport_priv *priv, 119 struct dma_desc *desc, 120 unsigned int port) 121 { 122 /* Ports are latched, so write upper address first */ 123 tdma_writel(priv, desc->addr_status_len, TDMA_WRITE_PORT_HI(port)); 124 tdma_writel(priv, desc->addr_lo, TDMA_WRITE_PORT_LO(port)); 125 } 126 127 /* Ethtool operations */ 128 static int bcm_sysport_set_rx_csum(struct net_device *dev, 129 netdev_features_t wanted) 130 { 131 struct bcm_sysport_priv *priv = netdev_priv(dev); 132 u32 reg; 133 134 priv->rx_chk_en = !!(wanted & NETIF_F_RXCSUM); 135 reg = rxchk_readl(priv, RXCHK_CONTROL); 136 if (priv->rx_chk_en) 137 reg |= RXCHK_EN; 138 else 139 reg &= ~RXCHK_EN; 140 141 /* If UniMAC forwards CRC, we need to skip over it to get 142 * a valid CHK bit to be set in the per-packet status word 143 */ 144 if (priv->rx_chk_en && priv->crc_fwd) 145 reg |= RXCHK_SKIP_FCS; 146 else 147 reg &= ~RXCHK_SKIP_FCS; 148 149 /* If Broadcom tags are enabled (e.g: using a switch), make 150 * sure we tell the RXCHK hardware to expect a 4-bytes Broadcom 151 * tag after the Ethernet MAC Source Address. 152 */ 153 if (netdev_uses_dsa(dev)) 154 reg |= RXCHK_BRCM_TAG_EN; 155 else 156 reg &= ~RXCHK_BRCM_TAG_EN; 157 158 rxchk_writel(priv, reg, RXCHK_CONTROL); 159 160 return 0; 161 } 162 163 static int bcm_sysport_set_tx_csum(struct net_device *dev, 164 netdev_features_t wanted) 165 { 166 struct bcm_sysport_priv *priv = netdev_priv(dev); 167 u32 reg; 168 169 /* Hardware transmit checksum requires us to enable the Transmit status 170 * block prepended to the packet contents 171 */ 172 priv->tsb_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)); 173 reg = tdma_readl(priv, TDMA_CONTROL); 174 if (priv->tsb_en) 175 reg |= tdma_control_bit(priv, TSB_EN); 176 else 177 reg &= ~tdma_control_bit(priv, TSB_EN); 178 tdma_writel(priv, reg, TDMA_CONTROL); 179 180 return 0; 181 } 182 183 static int bcm_sysport_set_features(struct net_device *dev, 184 netdev_features_t features) 185 { 186 netdev_features_t changed = features ^ dev->features; 187 netdev_features_t wanted = dev->wanted_features; 188 int ret = 0; 189 190 if (changed & NETIF_F_RXCSUM) 191 ret = bcm_sysport_set_rx_csum(dev, wanted); 192 if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)) 193 ret = bcm_sysport_set_tx_csum(dev, wanted); 194 195 return ret; 196 } 197 198 /* Hardware counters must be kept in sync because the order/offset 199 * is important here (order in structure declaration = order in hardware) 200 */ 201 static const struct bcm_sysport_stats bcm_sysport_gstrings_stats[] = { 202 /* general stats */ 203 STAT_NETDEV(rx_packets), 204 STAT_NETDEV(tx_packets), 205 STAT_NETDEV(rx_bytes), 206 STAT_NETDEV(tx_bytes), 207 STAT_NETDEV(rx_errors), 208 STAT_NETDEV(tx_errors), 209 STAT_NETDEV(rx_dropped), 210 STAT_NETDEV(tx_dropped), 211 STAT_NETDEV(multicast), 212 /* UniMAC RSV counters */ 213 STAT_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64), 214 STAT_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127), 215 STAT_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255), 216 STAT_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511), 217 STAT_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023), 218 STAT_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518), 219 STAT_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv), 220 STAT_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047), 221 STAT_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095), 222 STAT_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216), 223 STAT_MIB_RX("rx_pkts", mib.rx.pkt), 224 STAT_MIB_RX("rx_bytes", mib.rx.bytes), 225 STAT_MIB_RX("rx_multicast", mib.rx.mca), 226 STAT_MIB_RX("rx_broadcast", mib.rx.bca), 227 STAT_MIB_RX("rx_fcs", mib.rx.fcs), 228 STAT_MIB_RX("rx_control", mib.rx.cf), 229 STAT_MIB_RX("rx_pause", mib.rx.pf), 230 STAT_MIB_RX("rx_unknown", mib.rx.uo), 231 STAT_MIB_RX("rx_align", mib.rx.aln), 232 STAT_MIB_RX("rx_outrange", mib.rx.flr), 233 STAT_MIB_RX("rx_code", mib.rx.cde), 234 STAT_MIB_RX("rx_carrier", mib.rx.fcr), 235 STAT_MIB_RX("rx_oversize", mib.rx.ovr), 236 STAT_MIB_RX("rx_jabber", mib.rx.jbr), 237 STAT_MIB_RX("rx_mtu_err", mib.rx.mtue), 238 STAT_MIB_RX("rx_good_pkts", mib.rx.pok), 239 STAT_MIB_RX("rx_unicast", mib.rx.uc), 240 STAT_MIB_RX("rx_ppp", mib.rx.ppp), 241 STAT_MIB_RX("rx_crc", mib.rx.rcrc), 242 /* UniMAC TSV counters */ 243 STAT_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64), 244 STAT_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127), 245 STAT_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255), 246 STAT_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511), 247 STAT_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023), 248 STAT_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518), 249 STAT_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv), 250 STAT_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047), 251 STAT_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095), 252 STAT_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216), 253 STAT_MIB_TX("tx_pkts", mib.tx.pkts), 254 STAT_MIB_TX("tx_multicast", mib.tx.mca), 255 STAT_MIB_TX("tx_broadcast", mib.tx.bca), 256 STAT_MIB_TX("tx_pause", mib.tx.pf), 257 STAT_MIB_TX("tx_control", mib.tx.cf), 258 STAT_MIB_TX("tx_fcs_err", mib.tx.fcs), 259 STAT_MIB_TX("tx_oversize", mib.tx.ovr), 260 STAT_MIB_TX("tx_defer", mib.tx.drf), 261 STAT_MIB_TX("tx_excess_defer", mib.tx.edf), 262 STAT_MIB_TX("tx_single_col", mib.tx.scl), 263 STAT_MIB_TX("tx_multi_col", mib.tx.mcl), 264 STAT_MIB_TX("tx_late_col", mib.tx.lcl), 265 STAT_MIB_TX("tx_excess_col", mib.tx.ecl), 266 STAT_MIB_TX("tx_frags", mib.tx.frg), 267 STAT_MIB_TX("tx_total_col", mib.tx.ncl), 268 STAT_MIB_TX("tx_jabber", mib.tx.jbr), 269 STAT_MIB_TX("tx_bytes", mib.tx.bytes), 270 STAT_MIB_TX("tx_good_pkts", mib.tx.pok), 271 STAT_MIB_TX("tx_unicast", mib.tx.uc), 272 /* UniMAC RUNT counters */ 273 STAT_RUNT("rx_runt_pkts", mib.rx_runt_cnt), 274 STAT_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs), 275 STAT_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align), 276 STAT_RUNT("rx_runt_bytes", mib.rx_runt_bytes), 277 /* RXCHK misc statistics */ 278 STAT_RXCHK("rxchk_bad_csum", mib.rxchk_bad_csum, RXCHK_BAD_CSUM_CNTR), 279 STAT_RXCHK("rxchk_other_pkt_disc", mib.rxchk_other_pkt_disc, 280 RXCHK_OTHER_DISC_CNTR), 281 /* RBUF misc statistics */ 282 STAT_RBUF("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt, RBUF_OVFL_DISC_CNTR), 283 STAT_RBUF("rbuf_err_cnt", mib.rbuf_err_cnt, RBUF_ERR_PKT_CNTR), 284 STAT_MIB_SOFT("alloc_rx_buff_failed", mib.alloc_rx_buff_failed), 285 STAT_MIB_SOFT("rx_dma_failed", mib.rx_dma_failed), 286 STAT_MIB_SOFT("tx_dma_failed", mib.tx_dma_failed), 287 }; 288 289 #define BCM_SYSPORT_STATS_LEN ARRAY_SIZE(bcm_sysport_gstrings_stats) 290 291 static void bcm_sysport_get_drvinfo(struct net_device *dev, 292 struct ethtool_drvinfo *info) 293 { 294 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver)); 295 strlcpy(info->version, "0.1", sizeof(info->version)); 296 strlcpy(info->bus_info, "platform", sizeof(info->bus_info)); 297 } 298 299 static u32 bcm_sysport_get_msglvl(struct net_device *dev) 300 { 301 struct bcm_sysport_priv *priv = netdev_priv(dev); 302 303 return priv->msg_enable; 304 } 305 306 static void bcm_sysport_set_msglvl(struct net_device *dev, u32 enable) 307 { 308 struct bcm_sysport_priv *priv = netdev_priv(dev); 309 310 priv->msg_enable = enable; 311 } 312 313 static inline bool bcm_sysport_lite_stat_valid(enum bcm_sysport_stat_type type) 314 { 315 switch (type) { 316 case BCM_SYSPORT_STAT_NETDEV: 317 case BCM_SYSPORT_STAT_RXCHK: 318 case BCM_SYSPORT_STAT_RBUF: 319 case BCM_SYSPORT_STAT_SOFT: 320 return true; 321 default: 322 return false; 323 } 324 } 325 326 static int bcm_sysport_get_sset_count(struct net_device *dev, int string_set) 327 { 328 struct bcm_sysport_priv *priv = netdev_priv(dev); 329 const struct bcm_sysport_stats *s; 330 unsigned int i, j; 331 332 switch (string_set) { 333 case ETH_SS_STATS: 334 for (i = 0, j = 0; i < BCM_SYSPORT_STATS_LEN; i++) { 335 s = &bcm_sysport_gstrings_stats[i]; 336 if (priv->is_lite && 337 !bcm_sysport_lite_stat_valid(s->type)) 338 continue; 339 j++; 340 } 341 return j; 342 default: 343 return -EOPNOTSUPP; 344 } 345 } 346 347 static void bcm_sysport_get_strings(struct net_device *dev, 348 u32 stringset, u8 *data) 349 { 350 struct bcm_sysport_priv *priv = netdev_priv(dev); 351 const struct bcm_sysport_stats *s; 352 int i, j; 353 354 switch (stringset) { 355 case ETH_SS_STATS: 356 for (i = 0, j = 0; i < BCM_SYSPORT_STATS_LEN; i++) { 357 s = &bcm_sysport_gstrings_stats[i]; 358 if (priv->is_lite && 359 !bcm_sysport_lite_stat_valid(s->type)) 360 continue; 361 362 memcpy(data + j * ETH_GSTRING_LEN, s->stat_string, 363 ETH_GSTRING_LEN); 364 j++; 365 } 366 break; 367 default: 368 break; 369 } 370 } 371 372 static void bcm_sysport_update_mib_counters(struct bcm_sysport_priv *priv) 373 { 374 int i, j = 0; 375 376 for (i = 0; i < BCM_SYSPORT_STATS_LEN; i++) { 377 const struct bcm_sysport_stats *s; 378 u8 offset = 0; 379 u32 val = 0; 380 char *p; 381 382 s = &bcm_sysport_gstrings_stats[i]; 383 switch (s->type) { 384 case BCM_SYSPORT_STAT_NETDEV: 385 case BCM_SYSPORT_STAT_SOFT: 386 continue; 387 case BCM_SYSPORT_STAT_MIB_RX: 388 case BCM_SYSPORT_STAT_MIB_TX: 389 case BCM_SYSPORT_STAT_RUNT: 390 if (priv->is_lite) 391 continue; 392 393 if (s->type != BCM_SYSPORT_STAT_MIB_RX) 394 offset = UMAC_MIB_STAT_OFFSET; 395 val = umac_readl(priv, UMAC_MIB_START + j + offset); 396 break; 397 case BCM_SYSPORT_STAT_RXCHK: 398 val = rxchk_readl(priv, s->reg_offset); 399 if (val == ~0) 400 rxchk_writel(priv, 0, s->reg_offset); 401 break; 402 case BCM_SYSPORT_STAT_RBUF: 403 val = rbuf_readl(priv, s->reg_offset); 404 if (val == ~0) 405 rbuf_writel(priv, 0, s->reg_offset); 406 break; 407 } 408 409 j += s->stat_sizeof; 410 p = (char *)priv + s->stat_offset; 411 *(u32 *)p = val; 412 } 413 414 netif_dbg(priv, hw, priv->netdev, "updated MIB counters\n"); 415 } 416 417 static void bcm_sysport_get_stats(struct net_device *dev, 418 struct ethtool_stats *stats, u64 *data) 419 { 420 struct bcm_sysport_priv *priv = netdev_priv(dev); 421 int i, j; 422 423 if (netif_running(dev)) 424 bcm_sysport_update_mib_counters(priv); 425 426 for (i = 0, j = 0; i < BCM_SYSPORT_STATS_LEN; i++) { 427 const struct bcm_sysport_stats *s; 428 char *p; 429 430 s = &bcm_sysport_gstrings_stats[i]; 431 if (s->type == BCM_SYSPORT_STAT_NETDEV) 432 p = (char *)&dev->stats; 433 else 434 p = (char *)priv; 435 p += s->stat_offset; 436 data[j] = *(unsigned long *)p; 437 j++; 438 } 439 } 440 441 static void bcm_sysport_get_wol(struct net_device *dev, 442 struct ethtool_wolinfo *wol) 443 { 444 struct bcm_sysport_priv *priv = netdev_priv(dev); 445 u32 reg; 446 447 wol->supported = WAKE_MAGIC | WAKE_MAGICSECURE; 448 wol->wolopts = priv->wolopts; 449 450 if (!(priv->wolopts & WAKE_MAGICSECURE)) 451 return; 452 453 /* Return the programmed SecureOn password */ 454 reg = umac_readl(priv, UMAC_PSW_MS); 455 put_unaligned_be16(reg, &wol->sopass[0]); 456 reg = umac_readl(priv, UMAC_PSW_LS); 457 put_unaligned_be32(reg, &wol->sopass[2]); 458 } 459 460 static int bcm_sysport_set_wol(struct net_device *dev, 461 struct ethtool_wolinfo *wol) 462 { 463 struct bcm_sysport_priv *priv = netdev_priv(dev); 464 struct device *kdev = &priv->pdev->dev; 465 u32 supported = WAKE_MAGIC | WAKE_MAGICSECURE; 466 467 if (!device_can_wakeup(kdev)) 468 return -ENOTSUPP; 469 470 if (wol->wolopts & ~supported) 471 return -EINVAL; 472 473 /* Program the SecureOn password */ 474 if (wol->wolopts & WAKE_MAGICSECURE) { 475 umac_writel(priv, get_unaligned_be16(&wol->sopass[0]), 476 UMAC_PSW_MS); 477 umac_writel(priv, get_unaligned_be32(&wol->sopass[2]), 478 UMAC_PSW_LS); 479 } 480 481 /* Flag the device and relevant IRQ as wakeup capable */ 482 if (wol->wolopts) { 483 device_set_wakeup_enable(kdev, 1); 484 if (priv->wol_irq_disabled) 485 enable_irq_wake(priv->wol_irq); 486 priv->wol_irq_disabled = 0; 487 } else { 488 device_set_wakeup_enable(kdev, 0); 489 /* Avoid unbalanced disable_irq_wake calls */ 490 if (!priv->wol_irq_disabled) 491 disable_irq_wake(priv->wol_irq); 492 priv->wol_irq_disabled = 1; 493 } 494 495 priv->wolopts = wol->wolopts; 496 497 return 0; 498 } 499 500 static int bcm_sysport_get_coalesce(struct net_device *dev, 501 struct ethtool_coalesce *ec) 502 { 503 struct bcm_sysport_priv *priv = netdev_priv(dev); 504 u32 reg; 505 506 reg = tdma_readl(priv, TDMA_DESC_RING_INTR_CONTROL(0)); 507 508 ec->tx_coalesce_usecs = (reg >> RING_TIMEOUT_SHIFT) * 8192 / 1000; 509 ec->tx_max_coalesced_frames = reg & RING_INTR_THRESH_MASK; 510 511 reg = rdma_readl(priv, RDMA_MBDONE_INTR); 512 513 ec->rx_coalesce_usecs = (reg >> RDMA_TIMEOUT_SHIFT) * 8192 / 1000; 514 ec->rx_max_coalesced_frames = reg & RDMA_INTR_THRESH_MASK; 515 516 return 0; 517 } 518 519 static int bcm_sysport_set_coalesce(struct net_device *dev, 520 struct ethtool_coalesce *ec) 521 { 522 struct bcm_sysport_priv *priv = netdev_priv(dev); 523 unsigned int i; 524 u32 reg; 525 526 /* Base system clock is 125Mhz, DMA timeout is this reference clock 527 * divided by 1024, which yield roughly 8.192 us, our maximum value has 528 * to fit in the RING_TIMEOUT_MASK (16 bits). 529 */ 530 if (ec->tx_max_coalesced_frames > RING_INTR_THRESH_MASK || 531 ec->tx_coalesce_usecs > (RING_TIMEOUT_MASK * 8) + 1 || 532 ec->rx_max_coalesced_frames > RDMA_INTR_THRESH_MASK || 533 ec->rx_coalesce_usecs > (RDMA_TIMEOUT_MASK * 8) + 1) 534 return -EINVAL; 535 536 if ((ec->tx_coalesce_usecs == 0 && ec->tx_max_coalesced_frames == 0) || 537 (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0)) 538 return -EINVAL; 539 540 for (i = 0; i < dev->num_tx_queues; i++) { 541 reg = tdma_readl(priv, TDMA_DESC_RING_INTR_CONTROL(i)); 542 reg &= ~(RING_INTR_THRESH_MASK | 543 RING_TIMEOUT_MASK << RING_TIMEOUT_SHIFT); 544 reg |= ec->tx_max_coalesced_frames; 545 reg |= DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000, 8192) << 546 RING_TIMEOUT_SHIFT; 547 tdma_writel(priv, reg, TDMA_DESC_RING_INTR_CONTROL(i)); 548 } 549 550 reg = rdma_readl(priv, RDMA_MBDONE_INTR); 551 reg &= ~(RDMA_INTR_THRESH_MASK | 552 RDMA_TIMEOUT_MASK << RDMA_TIMEOUT_SHIFT); 553 reg |= ec->rx_max_coalesced_frames; 554 reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192) << 555 RDMA_TIMEOUT_SHIFT; 556 rdma_writel(priv, reg, RDMA_MBDONE_INTR); 557 558 return 0; 559 } 560 561 static void bcm_sysport_free_cb(struct bcm_sysport_cb *cb) 562 { 563 dev_kfree_skb_any(cb->skb); 564 cb->skb = NULL; 565 dma_unmap_addr_set(cb, dma_addr, 0); 566 } 567 568 static struct sk_buff *bcm_sysport_rx_refill(struct bcm_sysport_priv *priv, 569 struct bcm_sysport_cb *cb) 570 { 571 struct device *kdev = &priv->pdev->dev; 572 struct net_device *ndev = priv->netdev; 573 struct sk_buff *skb, *rx_skb; 574 dma_addr_t mapping; 575 576 /* Allocate a new SKB for a new packet */ 577 skb = netdev_alloc_skb(priv->netdev, RX_BUF_LENGTH); 578 if (!skb) { 579 priv->mib.alloc_rx_buff_failed++; 580 netif_err(priv, rx_err, ndev, "SKB alloc failed\n"); 581 return NULL; 582 } 583 584 mapping = dma_map_single(kdev, skb->data, 585 RX_BUF_LENGTH, DMA_FROM_DEVICE); 586 if (dma_mapping_error(kdev, mapping)) { 587 priv->mib.rx_dma_failed++; 588 dev_kfree_skb_any(skb); 589 netif_err(priv, rx_err, ndev, "DMA mapping failure\n"); 590 return NULL; 591 } 592 593 /* Grab the current SKB on the ring */ 594 rx_skb = cb->skb; 595 if (likely(rx_skb)) 596 dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr), 597 RX_BUF_LENGTH, DMA_FROM_DEVICE); 598 599 /* Put the new SKB on the ring */ 600 cb->skb = skb; 601 dma_unmap_addr_set(cb, dma_addr, mapping); 602 dma_desc_set_addr(priv, cb->bd_addr, mapping); 603 604 netif_dbg(priv, rx_status, ndev, "RX refill\n"); 605 606 /* Return the current SKB to the caller */ 607 return rx_skb; 608 } 609 610 static int bcm_sysport_alloc_rx_bufs(struct bcm_sysport_priv *priv) 611 { 612 struct bcm_sysport_cb *cb; 613 struct sk_buff *skb; 614 unsigned int i; 615 616 for (i = 0; i < priv->num_rx_bds; i++) { 617 cb = &priv->rx_cbs[i]; 618 skb = bcm_sysport_rx_refill(priv, cb); 619 if (skb) 620 dev_kfree_skb(skb); 621 if (!cb->skb) 622 return -ENOMEM; 623 } 624 625 return 0; 626 } 627 628 /* Poll the hardware for up to budget packets to process */ 629 static unsigned int bcm_sysport_desc_rx(struct bcm_sysport_priv *priv, 630 unsigned int budget) 631 { 632 struct net_device *ndev = priv->netdev; 633 unsigned int processed = 0, to_process; 634 struct bcm_sysport_cb *cb; 635 struct sk_buff *skb; 636 unsigned int p_index; 637 u16 len, status; 638 struct bcm_rsb *rsb; 639 640 /* Determine how much we should process since last call, SYSTEMPORT Lite 641 * groups the producer and consumer indexes into the same 32-bit 642 * which we access using RDMA_CONS_INDEX 643 */ 644 if (!priv->is_lite) 645 p_index = rdma_readl(priv, RDMA_PROD_INDEX); 646 else 647 p_index = rdma_readl(priv, RDMA_CONS_INDEX); 648 p_index &= RDMA_PROD_INDEX_MASK; 649 650 if (p_index < priv->rx_c_index) 651 to_process = (RDMA_CONS_INDEX_MASK + 1) - 652 priv->rx_c_index + p_index; 653 else 654 to_process = p_index - priv->rx_c_index; 655 656 netif_dbg(priv, rx_status, ndev, 657 "p_index=%d rx_c_index=%d to_process=%d\n", 658 p_index, priv->rx_c_index, to_process); 659 660 while ((processed < to_process) && (processed < budget)) { 661 cb = &priv->rx_cbs[priv->rx_read_ptr]; 662 skb = bcm_sysport_rx_refill(priv, cb); 663 664 665 /* We do not have a backing SKB, so we do not a corresponding 666 * DMA mapping for this incoming packet since 667 * bcm_sysport_rx_refill always either has both skb and mapping 668 * or none. 669 */ 670 if (unlikely(!skb)) { 671 netif_err(priv, rx_err, ndev, "out of memory!\n"); 672 ndev->stats.rx_dropped++; 673 ndev->stats.rx_errors++; 674 goto next; 675 } 676 677 /* Extract the Receive Status Block prepended */ 678 rsb = (struct bcm_rsb *)skb->data; 679 len = (rsb->rx_status_len >> DESC_LEN_SHIFT) & DESC_LEN_MASK; 680 status = (rsb->rx_status_len >> DESC_STATUS_SHIFT) & 681 DESC_STATUS_MASK; 682 683 netif_dbg(priv, rx_status, ndev, 684 "p=%d, c=%d, rd_ptr=%d, len=%d, flag=0x%04x\n", 685 p_index, priv->rx_c_index, priv->rx_read_ptr, 686 len, status); 687 688 if (unlikely(len > RX_BUF_LENGTH)) { 689 netif_err(priv, rx_status, ndev, "oversized packet\n"); 690 ndev->stats.rx_length_errors++; 691 ndev->stats.rx_errors++; 692 dev_kfree_skb_any(skb); 693 goto next; 694 } 695 696 if (unlikely(!(status & DESC_EOP) || !(status & DESC_SOP))) { 697 netif_err(priv, rx_status, ndev, "fragmented packet!\n"); 698 ndev->stats.rx_dropped++; 699 ndev->stats.rx_errors++; 700 dev_kfree_skb_any(skb); 701 goto next; 702 } 703 704 if (unlikely(status & (RX_STATUS_ERR | RX_STATUS_OVFLOW))) { 705 netif_err(priv, rx_err, ndev, "error packet\n"); 706 if (status & RX_STATUS_OVFLOW) 707 ndev->stats.rx_over_errors++; 708 ndev->stats.rx_dropped++; 709 ndev->stats.rx_errors++; 710 dev_kfree_skb_any(skb); 711 goto next; 712 } 713 714 skb_put(skb, len); 715 716 /* Hardware validated our checksum */ 717 if (likely(status & DESC_L4_CSUM)) 718 skb->ip_summed = CHECKSUM_UNNECESSARY; 719 720 /* Hardware pre-pends packets with 2bytes before Ethernet 721 * header plus we have the Receive Status Block, strip off all 722 * of this from the SKB. 723 */ 724 skb_pull(skb, sizeof(*rsb) + 2); 725 len -= (sizeof(*rsb) + 2); 726 727 /* UniMAC may forward CRC */ 728 if (priv->crc_fwd) { 729 skb_trim(skb, len - ETH_FCS_LEN); 730 len -= ETH_FCS_LEN; 731 } 732 733 skb->protocol = eth_type_trans(skb, ndev); 734 ndev->stats.rx_packets++; 735 ndev->stats.rx_bytes += len; 736 737 napi_gro_receive(&priv->napi, skb); 738 next: 739 processed++; 740 priv->rx_read_ptr++; 741 742 if (priv->rx_read_ptr == priv->num_rx_bds) 743 priv->rx_read_ptr = 0; 744 } 745 746 return processed; 747 } 748 749 static void bcm_sysport_tx_reclaim_one(struct bcm_sysport_priv *priv, 750 struct bcm_sysport_cb *cb, 751 unsigned int *bytes_compl, 752 unsigned int *pkts_compl) 753 { 754 struct device *kdev = &priv->pdev->dev; 755 struct net_device *ndev = priv->netdev; 756 757 if (cb->skb) { 758 ndev->stats.tx_bytes += cb->skb->len; 759 *bytes_compl += cb->skb->len; 760 dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr), 761 dma_unmap_len(cb, dma_len), 762 DMA_TO_DEVICE); 763 ndev->stats.tx_packets++; 764 (*pkts_compl)++; 765 bcm_sysport_free_cb(cb); 766 /* SKB fragment */ 767 } else if (dma_unmap_addr(cb, dma_addr)) { 768 ndev->stats.tx_bytes += dma_unmap_len(cb, dma_len); 769 dma_unmap_page(kdev, dma_unmap_addr(cb, dma_addr), 770 dma_unmap_len(cb, dma_len), DMA_TO_DEVICE); 771 dma_unmap_addr_set(cb, dma_addr, 0); 772 } 773 } 774 775 /* Reclaim queued SKBs for transmission completion, lockless version */ 776 static unsigned int __bcm_sysport_tx_reclaim(struct bcm_sysport_priv *priv, 777 struct bcm_sysport_tx_ring *ring) 778 { 779 struct net_device *ndev = priv->netdev; 780 unsigned int c_index, last_c_index, last_tx_cn, num_tx_cbs; 781 unsigned int pkts_compl = 0, bytes_compl = 0; 782 struct bcm_sysport_cb *cb; 783 u32 hw_ind; 784 785 /* Compute how many descriptors have been processed since last call */ 786 hw_ind = tdma_readl(priv, TDMA_DESC_RING_PROD_CONS_INDEX(ring->index)); 787 c_index = (hw_ind >> RING_CONS_INDEX_SHIFT) & RING_CONS_INDEX_MASK; 788 ring->p_index = (hw_ind & RING_PROD_INDEX_MASK); 789 790 last_c_index = ring->c_index; 791 num_tx_cbs = ring->size; 792 793 c_index &= (num_tx_cbs - 1); 794 795 if (c_index >= last_c_index) 796 last_tx_cn = c_index - last_c_index; 797 else 798 last_tx_cn = num_tx_cbs - last_c_index + c_index; 799 800 netif_dbg(priv, tx_done, ndev, 801 "ring=%d c_index=%d last_tx_cn=%d last_c_index=%d\n", 802 ring->index, c_index, last_tx_cn, last_c_index); 803 804 while (last_tx_cn-- > 0) { 805 cb = ring->cbs + last_c_index; 806 bcm_sysport_tx_reclaim_one(priv, cb, &bytes_compl, &pkts_compl); 807 808 ring->desc_count++; 809 last_c_index++; 810 last_c_index &= (num_tx_cbs - 1); 811 } 812 813 ring->c_index = c_index; 814 815 netif_dbg(priv, tx_done, ndev, 816 "ring=%d c_index=%d pkts_compl=%d, bytes_compl=%d\n", 817 ring->index, ring->c_index, pkts_compl, bytes_compl); 818 819 return pkts_compl; 820 } 821 822 /* Locked version of the per-ring TX reclaim routine */ 823 static unsigned int bcm_sysport_tx_reclaim(struct bcm_sysport_priv *priv, 824 struct bcm_sysport_tx_ring *ring) 825 { 826 struct netdev_queue *txq; 827 unsigned int released; 828 unsigned long flags; 829 830 txq = netdev_get_tx_queue(priv->netdev, ring->index); 831 832 spin_lock_irqsave(&ring->lock, flags); 833 released = __bcm_sysport_tx_reclaim(priv, ring); 834 if (released) 835 netif_tx_wake_queue(txq); 836 837 spin_unlock_irqrestore(&ring->lock, flags); 838 839 return released; 840 } 841 842 /* Locked version of the per-ring TX reclaim, but does not wake the queue */ 843 static void bcm_sysport_tx_clean(struct bcm_sysport_priv *priv, 844 struct bcm_sysport_tx_ring *ring) 845 { 846 unsigned long flags; 847 848 spin_lock_irqsave(&ring->lock, flags); 849 __bcm_sysport_tx_reclaim(priv, ring); 850 spin_unlock_irqrestore(&ring->lock, flags); 851 } 852 853 static int bcm_sysport_tx_poll(struct napi_struct *napi, int budget) 854 { 855 struct bcm_sysport_tx_ring *ring = 856 container_of(napi, struct bcm_sysport_tx_ring, napi); 857 unsigned int work_done = 0; 858 859 work_done = bcm_sysport_tx_reclaim(ring->priv, ring); 860 861 if (work_done == 0) { 862 napi_complete(napi); 863 /* re-enable TX interrupt */ 864 if (!ring->priv->is_lite) 865 intrl2_1_mask_clear(ring->priv, BIT(ring->index)); 866 else 867 intrl2_0_mask_clear(ring->priv, BIT(ring->index + 868 INTRL2_0_TDMA_MBDONE_SHIFT)); 869 870 return 0; 871 } 872 873 return budget; 874 } 875 876 static void bcm_sysport_tx_reclaim_all(struct bcm_sysport_priv *priv) 877 { 878 unsigned int q; 879 880 for (q = 0; q < priv->netdev->num_tx_queues; q++) 881 bcm_sysport_tx_reclaim(priv, &priv->tx_rings[q]); 882 } 883 884 static int bcm_sysport_poll(struct napi_struct *napi, int budget) 885 { 886 struct bcm_sysport_priv *priv = 887 container_of(napi, struct bcm_sysport_priv, napi); 888 unsigned int work_done = 0; 889 890 work_done = bcm_sysport_desc_rx(priv, budget); 891 892 priv->rx_c_index += work_done; 893 priv->rx_c_index &= RDMA_CONS_INDEX_MASK; 894 895 /* SYSTEMPORT Lite groups the producer/consumer index, producer is 896 * maintained by HW, but writes to it will be ignore while RDMA 897 * is active 898 */ 899 if (!priv->is_lite) 900 rdma_writel(priv, priv->rx_c_index, RDMA_CONS_INDEX); 901 else 902 rdma_writel(priv, priv->rx_c_index << 16, RDMA_CONS_INDEX); 903 904 if (work_done < budget) { 905 napi_complete_done(napi, work_done); 906 /* re-enable RX interrupts */ 907 intrl2_0_mask_clear(priv, INTRL2_0_RDMA_MBDONE); 908 } 909 910 return work_done; 911 } 912 913 static void bcm_sysport_resume_from_wol(struct bcm_sysport_priv *priv) 914 { 915 u32 reg; 916 917 /* Stop monitoring MPD interrupt */ 918 intrl2_0_mask_set(priv, INTRL2_0_MPD); 919 920 /* Clear the MagicPacket detection logic */ 921 reg = umac_readl(priv, UMAC_MPD_CTRL); 922 reg &= ~MPD_EN; 923 umac_writel(priv, reg, UMAC_MPD_CTRL); 924 925 netif_dbg(priv, wol, priv->netdev, "resumed from WOL\n"); 926 } 927 928 /* RX and misc interrupt routine */ 929 static irqreturn_t bcm_sysport_rx_isr(int irq, void *dev_id) 930 { 931 struct net_device *dev = dev_id; 932 struct bcm_sysport_priv *priv = netdev_priv(dev); 933 struct bcm_sysport_tx_ring *txr; 934 unsigned int ring, ring_bit; 935 936 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) & 937 ~intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS); 938 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR); 939 940 if (unlikely(priv->irq0_stat == 0)) { 941 netdev_warn(priv->netdev, "spurious RX interrupt\n"); 942 return IRQ_NONE; 943 } 944 945 if (priv->irq0_stat & INTRL2_0_RDMA_MBDONE) { 946 if (likely(napi_schedule_prep(&priv->napi))) { 947 /* disable RX interrupts */ 948 intrl2_0_mask_set(priv, INTRL2_0_RDMA_MBDONE); 949 __napi_schedule_irqoff(&priv->napi); 950 } 951 } 952 953 /* TX ring is full, perform a full reclaim since we do not know 954 * which one would trigger this interrupt 955 */ 956 if (priv->irq0_stat & INTRL2_0_TX_RING_FULL) 957 bcm_sysport_tx_reclaim_all(priv); 958 959 if (priv->irq0_stat & INTRL2_0_MPD) { 960 netdev_info(priv->netdev, "Wake-on-LAN interrupt!\n"); 961 bcm_sysport_resume_from_wol(priv); 962 } 963 964 if (!priv->is_lite) 965 goto out; 966 967 for (ring = 0; ring < dev->num_tx_queues; ring++) { 968 ring_bit = BIT(ring + INTRL2_0_TDMA_MBDONE_SHIFT); 969 if (!(priv->irq0_stat & ring_bit)) 970 continue; 971 972 txr = &priv->tx_rings[ring]; 973 974 if (likely(napi_schedule_prep(&txr->napi))) { 975 intrl2_0_mask_set(priv, ring_bit); 976 __napi_schedule(&txr->napi); 977 } 978 } 979 out: 980 return IRQ_HANDLED; 981 } 982 983 /* TX interrupt service routine */ 984 static irqreturn_t bcm_sysport_tx_isr(int irq, void *dev_id) 985 { 986 struct net_device *dev = dev_id; 987 struct bcm_sysport_priv *priv = netdev_priv(dev); 988 struct bcm_sysport_tx_ring *txr; 989 unsigned int ring; 990 991 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) & 992 ~intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS); 993 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 994 995 if (unlikely(priv->irq1_stat == 0)) { 996 netdev_warn(priv->netdev, "spurious TX interrupt\n"); 997 return IRQ_NONE; 998 } 999 1000 for (ring = 0; ring < dev->num_tx_queues; ring++) { 1001 if (!(priv->irq1_stat & BIT(ring))) 1002 continue; 1003 1004 txr = &priv->tx_rings[ring]; 1005 1006 if (likely(napi_schedule_prep(&txr->napi))) { 1007 intrl2_1_mask_set(priv, BIT(ring)); 1008 __napi_schedule_irqoff(&txr->napi); 1009 } 1010 } 1011 1012 return IRQ_HANDLED; 1013 } 1014 1015 static irqreturn_t bcm_sysport_wol_isr(int irq, void *dev_id) 1016 { 1017 struct bcm_sysport_priv *priv = dev_id; 1018 1019 pm_wakeup_event(&priv->pdev->dev, 0); 1020 1021 return IRQ_HANDLED; 1022 } 1023 1024 #ifdef CONFIG_NET_POLL_CONTROLLER 1025 static void bcm_sysport_poll_controller(struct net_device *dev) 1026 { 1027 struct bcm_sysport_priv *priv = netdev_priv(dev); 1028 1029 disable_irq(priv->irq0); 1030 bcm_sysport_rx_isr(priv->irq0, priv); 1031 enable_irq(priv->irq0); 1032 1033 if (!priv->is_lite) { 1034 disable_irq(priv->irq1); 1035 bcm_sysport_tx_isr(priv->irq1, priv); 1036 enable_irq(priv->irq1); 1037 } 1038 } 1039 #endif 1040 1041 static struct sk_buff *bcm_sysport_insert_tsb(struct sk_buff *skb, 1042 struct net_device *dev) 1043 { 1044 struct sk_buff *nskb; 1045 struct bcm_tsb *tsb; 1046 u32 csum_info; 1047 u8 ip_proto; 1048 u16 csum_start; 1049 u16 ip_ver; 1050 1051 /* Re-allocate SKB if needed */ 1052 if (unlikely(skb_headroom(skb) < sizeof(*tsb))) { 1053 nskb = skb_realloc_headroom(skb, sizeof(*tsb)); 1054 dev_kfree_skb(skb); 1055 if (!nskb) { 1056 dev->stats.tx_errors++; 1057 dev->stats.tx_dropped++; 1058 return NULL; 1059 } 1060 skb = nskb; 1061 } 1062 1063 tsb = (struct bcm_tsb *)skb_push(skb, sizeof(*tsb)); 1064 /* Zero-out TSB by default */ 1065 memset(tsb, 0, sizeof(*tsb)); 1066 1067 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1068 ip_ver = htons(skb->protocol); 1069 switch (ip_ver) { 1070 case ETH_P_IP: 1071 ip_proto = ip_hdr(skb)->protocol; 1072 break; 1073 case ETH_P_IPV6: 1074 ip_proto = ipv6_hdr(skb)->nexthdr; 1075 break; 1076 default: 1077 return skb; 1078 } 1079 1080 /* Get the checksum offset and the L4 (transport) offset */ 1081 csum_start = skb_checksum_start_offset(skb) - sizeof(*tsb); 1082 csum_info = (csum_start + skb->csum_offset) & L4_CSUM_PTR_MASK; 1083 csum_info |= (csum_start << L4_PTR_SHIFT); 1084 1085 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) { 1086 csum_info |= L4_LENGTH_VALID; 1087 if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP) 1088 csum_info |= L4_UDP; 1089 } else { 1090 csum_info = 0; 1091 } 1092 1093 tsb->l4_ptr_dest_map = csum_info; 1094 } 1095 1096 return skb; 1097 } 1098 1099 static netdev_tx_t bcm_sysport_xmit(struct sk_buff *skb, 1100 struct net_device *dev) 1101 { 1102 struct bcm_sysport_priv *priv = netdev_priv(dev); 1103 struct device *kdev = &priv->pdev->dev; 1104 struct bcm_sysport_tx_ring *ring; 1105 struct bcm_sysport_cb *cb; 1106 struct netdev_queue *txq; 1107 struct dma_desc *desc; 1108 unsigned int skb_len; 1109 unsigned long flags; 1110 dma_addr_t mapping; 1111 u32 len_status; 1112 u16 queue; 1113 int ret; 1114 1115 queue = skb_get_queue_mapping(skb); 1116 txq = netdev_get_tx_queue(dev, queue); 1117 ring = &priv->tx_rings[queue]; 1118 1119 /* lock against tx reclaim in BH context and TX ring full interrupt */ 1120 spin_lock_irqsave(&ring->lock, flags); 1121 if (unlikely(ring->desc_count == 0)) { 1122 netif_tx_stop_queue(txq); 1123 netdev_err(dev, "queue %d awake and ring full!\n", queue); 1124 ret = NETDEV_TX_BUSY; 1125 goto out; 1126 } 1127 1128 /* The Ethernet switch we are interfaced with needs packets to be at 1129 * least 64 bytes (including FCS) otherwise they will be discarded when 1130 * they enter the switch port logic. When Broadcom tags are enabled, we 1131 * need to make sure that packets are at least 68 bytes 1132 * (including FCS and tag) because the length verification is done after 1133 * the Broadcom tag is stripped off the ingress packet. 1134 */ 1135 if (skb_put_padto(skb, ETH_ZLEN + ENET_BRCM_TAG_LEN)) { 1136 ret = NETDEV_TX_OK; 1137 goto out; 1138 } 1139 1140 /* Insert TSB and checksum infos */ 1141 if (priv->tsb_en) { 1142 skb = bcm_sysport_insert_tsb(skb, dev); 1143 if (!skb) { 1144 ret = NETDEV_TX_OK; 1145 goto out; 1146 } 1147 } 1148 1149 skb_len = skb->len; 1150 1151 mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE); 1152 if (dma_mapping_error(kdev, mapping)) { 1153 priv->mib.tx_dma_failed++; 1154 netif_err(priv, tx_err, dev, "DMA map failed at %p (len=%d)\n", 1155 skb->data, skb_len); 1156 ret = NETDEV_TX_OK; 1157 goto out; 1158 } 1159 1160 /* Remember the SKB for future freeing */ 1161 cb = &ring->cbs[ring->curr_desc]; 1162 cb->skb = skb; 1163 dma_unmap_addr_set(cb, dma_addr, mapping); 1164 dma_unmap_len_set(cb, dma_len, skb_len); 1165 1166 /* Fetch a descriptor entry from our pool */ 1167 desc = ring->desc_cpu; 1168 1169 desc->addr_lo = lower_32_bits(mapping); 1170 len_status = upper_32_bits(mapping) & DESC_ADDR_HI_MASK; 1171 len_status |= (skb_len << DESC_LEN_SHIFT); 1172 len_status |= (DESC_SOP | DESC_EOP | TX_STATUS_APP_CRC) << 1173 DESC_STATUS_SHIFT; 1174 if (skb->ip_summed == CHECKSUM_PARTIAL) 1175 len_status |= (DESC_L4_CSUM << DESC_STATUS_SHIFT); 1176 1177 ring->curr_desc++; 1178 if (ring->curr_desc == ring->size) 1179 ring->curr_desc = 0; 1180 ring->desc_count--; 1181 1182 /* Ensure write completion of the descriptor status/length 1183 * in DRAM before the System Port WRITE_PORT register latches 1184 * the value 1185 */ 1186 wmb(); 1187 desc->addr_status_len = len_status; 1188 wmb(); 1189 1190 /* Write this descriptor address to the RING write port */ 1191 tdma_port_write_desc_addr(priv, desc, ring->index); 1192 1193 /* Check ring space and update SW control flow */ 1194 if (ring->desc_count == 0) 1195 netif_tx_stop_queue(txq); 1196 1197 netif_dbg(priv, tx_queued, dev, "ring=%d desc_count=%d, curr_desc=%d\n", 1198 ring->index, ring->desc_count, ring->curr_desc); 1199 1200 ret = NETDEV_TX_OK; 1201 out: 1202 spin_unlock_irqrestore(&ring->lock, flags); 1203 return ret; 1204 } 1205 1206 static void bcm_sysport_tx_timeout(struct net_device *dev) 1207 { 1208 netdev_warn(dev, "transmit timeout!\n"); 1209 1210 netif_trans_update(dev); 1211 dev->stats.tx_errors++; 1212 1213 netif_tx_wake_all_queues(dev); 1214 } 1215 1216 /* phylib adjust link callback */ 1217 static void bcm_sysport_adj_link(struct net_device *dev) 1218 { 1219 struct bcm_sysport_priv *priv = netdev_priv(dev); 1220 struct phy_device *phydev = dev->phydev; 1221 unsigned int changed = 0; 1222 u32 cmd_bits = 0, reg; 1223 1224 if (priv->old_link != phydev->link) { 1225 changed = 1; 1226 priv->old_link = phydev->link; 1227 } 1228 1229 if (priv->old_duplex != phydev->duplex) { 1230 changed = 1; 1231 priv->old_duplex = phydev->duplex; 1232 } 1233 1234 if (priv->is_lite) 1235 goto out; 1236 1237 switch (phydev->speed) { 1238 case SPEED_2500: 1239 cmd_bits = CMD_SPEED_2500; 1240 break; 1241 case SPEED_1000: 1242 cmd_bits = CMD_SPEED_1000; 1243 break; 1244 case SPEED_100: 1245 cmd_bits = CMD_SPEED_100; 1246 break; 1247 case SPEED_10: 1248 cmd_bits = CMD_SPEED_10; 1249 break; 1250 default: 1251 break; 1252 } 1253 cmd_bits <<= CMD_SPEED_SHIFT; 1254 1255 if (phydev->duplex == DUPLEX_HALF) 1256 cmd_bits |= CMD_HD_EN; 1257 1258 if (priv->old_pause != phydev->pause) { 1259 changed = 1; 1260 priv->old_pause = phydev->pause; 1261 } 1262 1263 if (!phydev->pause) 1264 cmd_bits |= CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE; 1265 1266 if (!changed) 1267 return; 1268 1269 if (phydev->link) { 1270 reg = umac_readl(priv, UMAC_CMD); 1271 reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) | 1272 CMD_HD_EN | CMD_RX_PAUSE_IGNORE | 1273 CMD_TX_PAUSE_IGNORE); 1274 reg |= cmd_bits; 1275 umac_writel(priv, reg, UMAC_CMD); 1276 } 1277 out: 1278 if (changed) 1279 phy_print_status(phydev); 1280 } 1281 1282 static int bcm_sysport_init_tx_ring(struct bcm_sysport_priv *priv, 1283 unsigned int index) 1284 { 1285 struct bcm_sysport_tx_ring *ring = &priv->tx_rings[index]; 1286 struct device *kdev = &priv->pdev->dev; 1287 size_t size; 1288 void *p; 1289 u32 reg; 1290 1291 /* Simple descriptors partitioning for now */ 1292 size = 256; 1293 1294 /* We just need one DMA descriptor which is DMA-able, since writing to 1295 * the port will allocate a new descriptor in its internal linked-list 1296 */ 1297 p = dma_zalloc_coherent(kdev, sizeof(struct dma_desc), &ring->desc_dma, 1298 GFP_KERNEL); 1299 if (!p) { 1300 netif_err(priv, hw, priv->netdev, "DMA alloc failed\n"); 1301 return -ENOMEM; 1302 } 1303 1304 ring->cbs = kcalloc(size, sizeof(struct bcm_sysport_cb), GFP_KERNEL); 1305 if (!ring->cbs) { 1306 netif_err(priv, hw, priv->netdev, "CB allocation failed\n"); 1307 return -ENOMEM; 1308 } 1309 1310 /* Initialize SW view of the ring */ 1311 spin_lock_init(&ring->lock); 1312 ring->priv = priv; 1313 netif_tx_napi_add(priv->netdev, &ring->napi, bcm_sysport_tx_poll, 64); 1314 ring->index = index; 1315 ring->size = size; 1316 ring->alloc_size = ring->size; 1317 ring->desc_cpu = p; 1318 ring->desc_count = ring->size; 1319 ring->curr_desc = 0; 1320 1321 /* Initialize HW ring */ 1322 tdma_writel(priv, RING_EN, TDMA_DESC_RING_HEAD_TAIL_PTR(index)); 1323 tdma_writel(priv, 0, TDMA_DESC_RING_COUNT(index)); 1324 tdma_writel(priv, 1, TDMA_DESC_RING_INTR_CONTROL(index)); 1325 tdma_writel(priv, 0, TDMA_DESC_RING_PROD_CONS_INDEX(index)); 1326 tdma_writel(priv, RING_IGNORE_STATUS, TDMA_DESC_RING_MAPPING(index)); 1327 tdma_writel(priv, 0, TDMA_DESC_RING_PCP_DEI_VID(index)); 1328 1329 /* Program the number of descriptors as MAX_THRESHOLD and half of 1330 * its size for the hysteresis trigger 1331 */ 1332 tdma_writel(priv, ring->size | 1333 1 << RING_HYST_THRESH_SHIFT, 1334 TDMA_DESC_RING_MAX_HYST(index)); 1335 1336 /* Enable the ring queue in the arbiter */ 1337 reg = tdma_readl(priv, TDMA_TIER1_ARB_0_QUEUE_EN); 1338 reg |= (1 << index); 1339 tdma_writel(priv, reg, TDMA_TIER1_ARB_0_QUEUE_EN); 1340 1341 napi_enable(&ring->napi); 1342 1343 netif_dbg(priv, hw, priv->netdev, 1344 "TDMA cfg, size=%d, desc_cpu=%p\n", 1345 ring->size, ring->desc_cpu); 1346 1347 return 0; 1348 } 1349 1350 static void bcm_sysport_fini_tx_ring(struct bcm_sysport_priv *priv, 1351 unsigned int index) 1352 { 1353 struct bcm_sysport_tx_ring *ring = &priv->tx_rings[index]; 1354 struct device *kdev = &priv->pdev->dev; 1355 u32 reg; 1356 1357 /* Caller should stop the TDMA engine */ 1358 reg = tdma_readl(priv, TDMA_STATUS); 1359 if (!(reg & TDMA_DISABLED)) 1360 netdev_warn(priv->netdev, "TDMA not stopped!\n"); 1361 1362 /* ring->cbs is the last part in bcm_sysport_init_tx_ring which could 1363 * fail, so by checking this pointer we know whether the TX ring was 1364 * fully initialized or not. 1365 */ 1366 if (!ring->cbs) 1367 return; 1368 1369 napi_disable(&ring->napi); 1370 netif_napi_del(&ring->napi); 1371 1372 bcm_sysport_tx_clean(priv, ring); 1373 1374 kfree(ring->cbs); 1375 ring->cbs = NULL; 1376 1377 if (ring->desc_dma) { 1378 dma_free_coherent(kdev, sizeof(struct dma_desc), 1379 ring->desc_cpu, ring->desc_dma); 1380 ring->desc_dma = 0; 1381 } 1382 ring->size = 0; 1383 ring->alloc_size = 0; 1384 1385 netif_dbg(priv, hw, priv->netdev, "TDMA fini done\n"); 1386 } 1387 1388 /* RDMA helper */ 1389 static inline int rdma_enable_set(struct bcm_sysport_priv *priv, 1390 unsigned int enable) 1391 { 1392 unsigned int timeout = 1000; 1393 u32 reg; 1394 1395 reg = rdma_readl(priv, RDMA_CONTROL); 1396 if (enable) 1397 reg |= RDMA_EN; 1398 else 1399 reg &= ~RDMA_EN; 1400 rdma_writel(priv, reg, RDMA_CONTROL); 1401 1402 /* Poll for RMDA disabling completion */ 1403 do { 1404 reg = rdma_readl(priv, RDMA_STATUS); 1405 if (!!(reg & RDMA_DISABLED) == !enable) 1406 return 0; 1407 usleep_range(1000, 2000); 1408 } while (timeout-- > 0); 1409 1410 netdev_err(priv->netdev, "timeout waiting for RDMA to finish\n"); 1411 1412 return -ETIMEDOUT; 1413 } 1414 1415 /* TDMA helper */ 1416 static inline int tdma_enable_set(struct bcm_sysport_priv *priv, 1417 unsigned int enable) 1418 { 1419 unsigned int timeout = 1000; 1420 u32 reg; 1421 1422 reg = tdma_readl(priv, TDMA_CONTROL); 1423 if (enable) 1424 reg |= tdma_control_bit(priv, TDMA_EN); 1425 else 1426 reg &= ~tdma_control_bit(priv, TDMA_EN); 1427 tdma_writel(priv, reg, TDMA_CONTROL); 1428 1429 /* Poll for TMDA disabling completion */ 1430 do { 1431 reg = tdma_readl(priv, TDMA_STATUS); 1432 if (!!(reg & TDMA_DISABLED) == !enable) 1433 return 0; 1434 1435 usleep_range(1000, 2000); 1436 } while (timeout-- > 0); 1437 1438 netdev_err(priv->netdev, "timeout waiting for TDMA to finish\n"); 1439 1440 return -ETIMEDOUT; 1441 } 1442 1443 static int bcm_sysport_init_rx_ring(struct bcm_sysport_priv *priv) 1444 { 1445 struct bcm_sysport_cb *cb; 1446 u32 reg; 1447 int ret; 1448 int i; 1449 1450 /* Initialize SW view of the RX ring */ 1451 priv->num_rx_bds = priv->num_rx_desc_words / WORDS_PER_DESC; 1452 priv->rx_bds = priv->base + SYS_PORT_RDMA_OFFSET; 1453 priv->rx_c_index = 0; 1454 priv->rx_read_ptr = 0; 1455 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct bcm_sysport_cb), 1456 GFP_KERNEL); 1457 if (!priv->rx_cbs) { 1458 netif_err(priv, hw, priv->netdev, "CB allocation failed\n"); 1459 return -ENOMEM; 1460 } 1461 1462 for (i = 0; i < priv->num_rx_bds; i++) { 1463 cb = priv->rx_cbs + i; 1464 cb->bd_addr = priv->rx_bds + i * DESC_SIZE; 1465 } 1466 1467 ret = bcm_sysport_alloc_rx_bufs(priv); 1468 if (ret) { 1469 netif_err(priv, hw, priv->netdev, "SKB allocation failed\n"); 1470 return ret; 1471 } 1472 1473 /* Initialize HW, ensure RDMA is disabled */ 1474 reg = rdma_readl(priv, RDMA_STATUS); 1475 if (!(reg & RDMA_DISABLED)) 1476 rdma_enable_set(priv, 0); 1477 1478 rdma_writel(priv, 0, RDMA_WRITE_PTR_LO); 1479 rdma_writel(priv, 0, RDMA_WRITE_PTR_HI); 1480 rdma_writel(priv, 0, RDMA_PROD_INDEX); 1481 rdma_writel(priv, 0, RDMA_CONS_INDEX); 1482 rdma_writel(priv, priv->num_rx_bds << RDMA_RING_SIZE_SHIFT | 1483 RX_BUF_LENGTH, RDMA_RING_BUF_SIZE); 1484 /* Operate the queue in ring mode */ 1485 rdma_writel(priv, 0, RDMA_START_ADDR_HI); 1486 rdma_writel(priv, 0, RDMA_START_ADDR_LO); 1487 rdma_writel(priv, 0, RDMA_END_ADDR_HI); 1488 rdma_writel(priv, priv->num_rx_desc_words - 1, RDMA_END_ADDR_LO); 1489 1490 rdma_writel(priv, 1, RDMA_MBDONE_INTR); 1491 1492 netif_dbg(priv, hw, priv->netdev, 1493 "RDMA cfg, num_rx_bds=%d, rx_bds=%p\n", 1494 priv->num_rx_bds, priv->rx_bds); 1495 1496 return 0; 1497 } 1498 1499 static void bcm_sysport_fini_rx_ring(struct bcm_sysport_priv *priv) 1500 { 1501 struct bcm_sysport_cb *cb; 1502 unsigned int i; 1503 u32 reg; 1504 1505 /* Caller should ensure RDMA is disabled */ 1506 reg = rdma_readl(priv, RDMA_STATUS); 1507 if (!(reg & RDMA_DISABLED)) 1508 netdev_warn(priv->netdev, "RDMA not stopped!\n"); 1509 1510 for (i = 0; i < priv->num_rx_bds; i++) { 1511 cb = &priv->rx_cbs[i]; 1512 if (dma_unmap_addr(cb, dma_addr)) 1513 dma_unmap_single(&priv->pdev->dev, 1514 dma_unmap_addr(cb, dma_addr), 1515 RX_BUF_LENGTH, DMA_FROM_DEVICE); 1516 bcm_sysport_free_cb(cb); 1517 } 1518 1519 kfree(priv->rx_cbs); 1520 priv->rx_cbs = NULL; 1521 1522 netif_dbg(priv, hw, priv->netdev, "RDMA fini done\n"); 1523 } 1524 1525 static void bcm_sysport_set_rx_mode(struct net_device *dev) 1526 { 1527 struct bcm_sysport_priv *priv = netdev_priv(dev); 1528 u32 reg; 1529 1530 if (priv->is_lite) 1531 return; 1532 1533 reg = umac_readl(priv, UMAC_CMD); 1534 if (dev->flags & IFF_PROMISC) 1535 reg |= CMD_PROMISC; 1536 else 1537 reg &= ~CMD_PROMISC; 1538 umac_writel(priv, reg, UMAC_CMD); 1539 1540 /* No support for ALLMULTI */ 1541 if (dev->flags & IFF_ALLMULTI) 1542 return; 1543 } 1544 1545 static inline void umac_enable_set(struct bcm_sysport_priv *priv, 1546 u32 mask, unsigned int enable) 1547 { 1548 u32 reg; 1549 1550 if (!priv->is_lite) { 1551 reg = umac_readl(priv, UMAC_CMD); 1552 if (enable) 1553 reg |= mask; 1554 else 1555 reg &= ~mask; 1556 umac_writel(priv, reg, UMAC_CMD); 1557 } else { 1558 reg = gib_readl(priv, GIB_CONTROL); 1559 if (enable) 1560 reg |= mask; 1561 else 1562 reg &= ~mask; 1563 gib_writel(priv, reg, GIB_CONTROL); 1564 } 1565 1566 /* UniMAC stops on a packet boundary, wait for a full-sized packet 1567 * to be processed (1 msec). 1568 */ 1569 if (enable == 0) 1570 usleep_range(1000, 2000); 1571 } 1572 1573 static inline void umac_reset(struct bcm_sysport_priv *priv) 1574 { 1575 u32 reg; 1576 1577 if (priv->is_lite) 1578 return; 1579 1580 reg = umac_readl(priv, UMAC_CMD); 1581 reg |= CMD_SW_RESET; 1582 umac_writel(priv, reg, UMAC_CMD); 1583 udelay(10); 1584 reg = umac_readl(priv, UMAC_CMD); 1585 reg &= ~CMD_SW_RESET; 1586 umac_writel(priv, reg, UMAC_CMD); 1587 } 1588 1589 static void umac_set_hw_addr(struct bcm_sysport_priv *priv, 1590 unsigned char *addr) 1591 { 1592 u32 mac0 = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | 1593 addr[3]; 1594 u32 mac1 = (addr[4] << 8) | addr[5]; 1595 1596 if (!priv->is_lite) { 1597 umac_writel(priv, mac0, UMAC_MAC0); 1598 umac_writel(priv, mac1, UMAC_MAC1); 1599 } else { 1600 gib_writel(priv, mac0, GIB_MAC0); 1601 gib_writel(priv, mac1, GIB_MAC1); 1602 } 1603 } 1604 1605 static void topctrl_flush(struct bcm_sysport_priv *priv) 1606 { 1607 topctrl_writel(priv, RX_FLUSH, RX_FLUSH_CNTL); 1608 topctrl_writel(priv, TX_FLUSH, TX_FLUSH_CNTL); 1609 mdelay(1); 1610 topctrl_writel(priv, 0, RX_FLUSH_CNTL); 1611 topctrl_writel(priv, 0, TX_FLUSH_CNTL); 1612 } 1613 1614 static int bcm_sysport_change_mac(struct net_device *dev, void *p) 1615 { 1616 struct bcm_sysport_priv *priv = netdev_priv(dev); 1617 struct sockaddr *addr = p; 1618 1619 if (!is_valid_ether_addr(addr->sa_data)) 1620 return -EINVAL; 1621 1622 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 1623 1624 /* interface is disabled, changes to MAC will be reflected on next 1625 * open call 1626 */ 1627 if (!netif_running(dev)) 1628 return 0; 1629 1630 umac_set_hw_addr(priv, dev->dev_addr); 1631 1632 return 0; 1633 } 1634 1635 static void bcm_sysport_netif_start(struct net_device *dev) 1636 { 1637 struct bcm_sysport_priv *priv = netdev_priv(dev); 1638 1639 /* Enable NAPI */ 1640 napi_enable(&priv->napi); 1641 1642 /* Enable RX interrupt and TX ring full interrupt */ 1643 intrl2_0_mask_clear(priv, INTRL2_0_RDMA_MBDONE | INTRL2_0_TX_RING_FULL); 1644 1645 phy_start(dev->phydev); 1646 1647 /* Enable TX interrupts for the TXQs */ 1648 if (!priv->is_lite) 1649 intrl2_1_mask_clear(priv, 0xffffffff); 1650 else 1651 intrl2_0_mask_clear(priv, INTRL2_0_TDMA_MBDONE_MASK); 1652 1653 /* Last call before we start the real business */ 1654 netif_tx_start_all_queues(dev); 1655 } 1656 1657 static void rbuf_init(struct bcm_sysport_priv *priv) 1658 { 1659 u32 reg; 1660 1661 reg = rbuf_readl(priv, RBUF_CONTROL); 1662 reg |= RBUF_4B_ALGN | RBUF_RSB_EN; 1663 /* Set a correct RSB format on SYSTEMPORT Lite */ 1664 if (priv->is_lite) { 1665 reg &= ~RBUF_RSB_SWAP1; 1666 reg |= RBUF_RSB_SWAP0; 1667 } 1668 rbuf_writel(priv, reg, RBUF_CONTROL); 1669 } 1670 1671 static inline void bcm_sysport_mask_all_intrs(struct bcm_sysport_priv *priv) 1672 { 1673 intrl2_0_mask_set(priv, 0xffffffff); 1674 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 1675 if (!priv->is_lite) { 1676 intrl2_1_mask_set(priv, 0xffffffff); 1677 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 1678 } 1679 } 1680 1681 static inline void gib_set_pad_extension(struct bcm_sysport_priv *priv) 1682 { 1683 u32 __maybe_unused reg; 1684 1685 /* Include Broadcom tag in pad extension */ 1686 if (netdev_uses_dsa(priv->netdev)) { 1687 reg = gib_readl(priv, GIB_CONTROL); 1688 reg &= ~(GIB_PAD_EXTENSION_MASK << GIB_PAD_EXTENSION_SHIFT); 1689 reg |= ENET_BRCM_TAG_LEN << GIB_PAD_EXTENSION_SHIFT; 1690 gib_writel(priv, reg, GIB_CONTROL); 1691 } 1692 } 1693 1694 static int bcm_sysport_open(struct net_device *dev) 1695 { 1696 struct bcm_sysport_priv *priv = netdev_priv(dev); 1697 struct phy_device *phydev; 1698 unsigned int i; 1699 int ret; 1700 1701 /* Reset UniMAC */ 1702 umac_reset(priv); 1703 1704 /* Flush TX and RX FIFOs at TOPCTRL level */ 1705 topctrl_flush(priv); 1706 1707 /* Disable the UniMAC RX/TX */ 1708 umac_enable_set(priv, CMD_RX_EN | CMD_TX_EN, 0); 1709 1710 /* Enable RBUF 2bytes alignment and Receive Status Block */ 1711 rbuf_init(priv); 1712 1713 /* Set maximum frame length */ 1714 if (!priv->is_lite) 1715 umac_writel(priv, UMAC_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN); 1716 else 1717 gib_set_pad_extension(priv); 1718 1719 /* Set MAC address */ 1720 umac_set_hw_addr(priv, dev->dev_addr); 1721 1722 /* Read CRC forward */ 1723 if (!priv->is_lite) 1724 priv->crc_fwd = !!(umac_readl(priv, UMAC_CMD) & CMD_CRC_FWD); 1725 else 1726 priv->crc_fwd = !!(gib_readl(priv, GIB_CONTROL) & 1727 GIB_FCS_STRIP); 1728 1729 phydev = of_phy_connect(dev, priv->phy_dn, bcm_sysport_adj_link, 1730 0, priv->phy_interface); 1731 if (!phydev) { 1732 netdev_err(dev, "could not attach to PHY\n"); 1733 return -ENODEV; 1734 } 1735 1736 /* Reset house keeping link status */ 1737 priv->old_duplex = -1; 1738 priv->old_link = -1; 1739 priv->old_pause = -1; 1740 1741 /* mask all interrupts and request them */ 1742 bcm_sysport_mask_all_intrs(priv); 1743 1744 ret = request_irq(priv->irq0, bcm_sysport_rx_isr, 0, dev->name, dev); 1745 if (ret) { 1746 netdev_err(dev, "failed to request RX interrupt\n"); 1747 goto out_phy_disconnect; 1748 } 1749 1750 if (!priv->is_lite) { 1751 ret = request_irq(priv->irq1, bcm_sysport_tx_isr, 0, 1752 dev->name, dev); 1753 if (ret) { 1754 netdev_err(dev, "failed to request TX interrupt\n"); 1755 goto out_free_irq0; 1756 } 1757 } 1758 1759 /* Initialize both hardware and software ring */ 1760 for (i = 0; i < dev->num_tx_queues; i++) { 1761 ret = bcm_sysport_init_tx_ring(priv, i); 1762 if (ret) { 1763 netdev_err(dev, "failed to initialize TX ring %d\n", 1764 i); 1765 goto out_free_tx_ring; 1766 } 1767 } 1768 1769 /* Initialize linked-list */ 1770 tdma_writel(priv, TDMA_LL_RAM_INIT_BUSY, TDMA_STATUS); 1771 1772 /* Initialize RX ring */ 1773 ret = bcm_sysport_init_rx_ring(priv); 1774 if (ret) { 1775 netdev_err(dev, "failed to initialize RX ring\n"); 1776 goto out_free_rx_ring; 1777 } 1778 1779 /* Turn on RDMA */ 1780 ret = rdma_enable_set(priv, 1); 1781 if (ret) 1782 goto out_free_rx_ring; 1783 1784 /* Turn on TDMA */ 1785 ret = tdma_enable_set(priv, 1); 1786 if (ret) 1787 goto out_clear_rx_int; 1788 1789 /* Turn on UniMAC TX/RX */ 1790 umac_enable_set(priv, CMD_RX_EN | CMD_TX_EN, 1); 1791 1792 bcm_sysport_netif_start(dev); 1793 1794 return 0; 1795 1796 out_clear_rx_int: 1797 intrl2_0_mask_set(priv, INTRL2_0_RDMA_MBDONE | INTRL2_0_TX_RING_FULL); 1798 out_free_rx_ring: 1799 bcm_sysport_fini_rx_ring(priv); 1800 out_free_tx_ring: 1801 for (i = 0; i < dev->num_tx_queues; i++) 1802 bcm_sysport_fini_tx_ring(priv, i); 1803 if (!priv->is_lite) 1804 free_irq(priv->irq1, dev); 1805 out_free_irq0: 1806 free_irq(priv->irq0, dev); 1807 out_phy_disconnect: 1808 phy_disconnect(phydev); 1809 return ret; 1810 } 1811 1812 static void bcm_sysport_netif_stop(struct net_device *dev) 1813 { 1814 struct bcm_sysport_priv *priv = netdev_priv(dev); 1815 1816 /* stop all software from updating hardware */ 1817 netif_tx_stop_all_queues(dev); 1818 napi_disable(&priv->napi); 1819 phy_stop(dev->phydev); 1820 1821 /* mask all interrupts */ 1822 bcm_sysport_mask_all_intrs(priv); 1823 } 1824 1825 static int bcm_sysport_stop(struct net_device *dev) 1826 { 1827 struct bcm_sysport_priv *priv = netdev_priv(dev); 1828 unsigned int i; 1829 int ret; 1830 1831 bcm_sysport_netif_stop(dev); 1832 1833 /* Disable UniMAC RX */ 1834 umac_enable_set(priv, CMD_RX_EN, 0); 1835 1836 ret = tdma_enable_set(priv, 0); 1837 if (ret) { 1838 netdev_err(dev, "timeout disabling RDMA\n"); 1839 return ret; 1840 } 1841 1842 /* Wait for a maximum packet size to be drained */ 1843 usleep_range(2000, 3000); 1844 1845 ret = rdma_enable_set(priv, 0); 1846 if (ret) { 1847 netdev_err(dev, "timeout disabling TDMA\n"); 1848 return ret; 1849 } 1850 1851 /* Disable UniMAC TX */ 1852 umac_enable_set(priv, CMD_TX_EN, 0); 1853 1854 /* Free RX/TX rings SW structures */ 1855 for (i = 0; i < dev->num_tx_queues; i++) 1856 bcm_sysport_fini_tx_ring(priv, i); 1857 bcm_sysport_fini_rx_ring(priv); 1858 1859 free_irq(priv->irq0, dev); 1860 if (!priv->is_lite) 1861 free_irq(priv->irq1, dev); 1862 1863 /* Disconnect from PHY */ 1864 phy_disconnect(dev->phydev); 1865 1866 return 0; 1867 } 1868 1869 static const struct ethtool_ops bcm_sysport_ethtool_ops = { 1870 .get_drvinfo = bcm_sysport_get_drvinfo, 1871 .get_msglevel = bcm_sysport_get_msglvl, 1872 .set_msglevel = bcm_sysport_set_msglvl, 1873 .get_link = ethtool_op_get_link, 1874 .get_strings = bcm_sysport_get_strings, 1875 .get_ethtool_stats = bcm_sysport_get_stats, 1876 .get_sset_count = bcm_sysport_get_sset_count, 1877 .get_wol = bcm_sysport_get_wol, 1878 .set_wol = bcm_sysport_set_wol, 1879 .get_coalesce = bcm_sysport_get_coalesce, 1880 .set_coalesce = bcm_sysport_set_coalesce, 1881 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1882 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1883 }; 1884 1885 static const struct net_device_ops bcm_sysport_netdev_ops = { 1886 .ndo_start_xmit = bcm_sysport_xmit, 1887 .ndo_tx_timeout = bcm_sysport_tx_timeout, 1888 .ndo_open = bcm_sysport_open, 1889 .ndo_stop = bcm_sysport_stop, 1890 .ndo_set_features = bcm_sysport_set_features, 1891 .ndo_set_rx_mode = bcm_sysport_set_rx_mode, 1892 .ndo_set_mac_address = bcm_sysport_change_mac, 1893 #ifdef CONFIG_NET_POLL_CONTROLLER 1894 .ndo_poll_controller = bcm_sysport_poll_controller, 1895 #endif 1896 }; 1897 1898 #define REV_FMT "v%2x.%02x" 1899 1900 static const struct bcm_sysport_hw_params bcm_sysport_params[] = { 1901 [SYSTEMPORT] = { 1902 .is_lite = false, 1903 .num_rx_desc_words = SP_NUM_HW_RX_DESC_WORDS, 1904 }, 1905 [SYSTEMPORT_LITE] = { 1906 .is_lite = true, 1907 .num_rx_desc_words = SP_LT_NUM_HW_RX_DESC_WORDS, 1908 }, 1909 }; 1910 1911 static const struct of_device_id bcm_sysport_of_match[] = { 1912 { .compatible = "brcm,systemportlite-v1.00", 1913 .data = &bcm_sysport_params[SYSTEMPORT_LITE] }, 1914 { .compatible = "brcm,systemport-v1.00", 1915 .data = &bcm_sysport_params[SYSTEMPORT] }, 1916 { .compatible = "brcm,systemport", 1917 .data = &bcm_sysport_params[SYSTEMPORT] }, 1918 { /* sentinel */ } 1919 }; 1920 MODULE_DEVICE_TABLE(of, bcm_sysport_of_match); 1921 1922 static int bcm_sysport_probe(struct platform_device *pdev) 1923 { 1924 const struct bcm_sysport_hw_params *params; 1925 const struct of_device_id *of_id = NULL; 1926 struct bcm_sysport_priv *priv; 1927 struct device_node *dn; 1928 struct net_device *dev; 1929 const void *macaddr; 1930 struct resource *r; 1931 u32 txq, rxq; 1932 int ret; 1933 1934 dn = pdev->dev.of_node; 1935 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1936 of_id = of_match_node(bcm_sysport_of_match, dn); 1937 if (!of_id || !of_id->data) 1938 return -EINVAL; 1939 1940 /* Fairly quickly we need to know the type of adapter we have */ 1941 params = of_id->data; 1942 1943 /* Read the Transmit/Receive Queue properties */ 1944 if (of_property_read_u32(dn, "systemport,num-txq", &txq)) 1945 txq = TDMA_NUM_RINGS; 1946 if (of_property_read_u32(dn, "systemport,num-rxq", &rxq)) 1947 rxq = 1; 1948 1949 /* Sanity check the number of transmit queues */ 1950 if (!txq || txq > TDMA_NUM_RINGS) 1951 return -EINVAL; 1952 1953 dev = alloc_etherdev_mqs(sizeof(*priv), txq, rxq); 1954 if (!dev) 1955 return -ENOMEM; 1956 1957 /* Initialize private members */ 1958 priv = netdev_priv(dev); 1959 1960 /* Allocate number of TX rings */ 1961 priv->tx_rings = devm_kcalloc(&pdev->dev, txq, 1962 sizeof(struct bcm_sysport_tx_ring), 1963 GFP_KERNEL); 1964 if (!priv->tx_rings) 1965 return -ENOMEM; 1966 1967 priv->is_lite = params->is_lite; 1968 priv->num_rx_desc_words = params->num_rx_desc_words; 1969 1970 priv->irq0 = platform_get_irq(pdev, 0); 1971 if (!priv->is_lite) 1972 priv->irq1 = platform_get_irq(pdev, 1); 1973 priv->wol_irq = platform_get_irq(pdev, 2); 1974 if (priv->irq0 <= 0 || (priv->irq1 <= 0 && !priv->is_lite)) { 1975 dev_err(&pdev->dev, "invalid interrupts\n"); 1976 ret = -EINVAL; 1977 goto err_free_netdev; 1978 } 1979 1980 priv->base = devm_ioremap_resource(&pdev->dev, r); 1981 if (IS_ERR(priv->base)) { 1982 ret = PTR_ERR(priv->base); 1983 goto err_free_netdev; 1984 } 1985 1986 priv->netdev = dev; 1987 priv->pdev = pdev; 1988 1989 priv->phy_interface = of_get_phy_mode(dn); 1990 /* Default to GMII interface mode */ 1991 if (priv->phy_interface < 0) 1992 priv->phy_interface = PHY_INTERFACE_MODE_GMII; 1993 1994 /* In the case of a fixed PHY, the DT node associated 1995 * to the PHY is the Ethernet MAC DT node. 1996 */ 1997 if (of_phy_is_fixed_link(dn)) { 1998 ret = of_phy_register_fixed_link(dn); 1999 if (ret) { 2000 dev_err(&pdev->dev, "failed to register fixed PHY\n"); 2001 goto err_free_netdev; 2002 } 2003 2004 priv->phy_dn = dn; 2005 } 2006 2007 /* Initialize netdevice members */ 2008 macaddr = of_get_mac_address(dn); 2009 if (!macaddr || !is_valid_ether_addr(macaddr)) { 2010 dev_warn(&pdev->dev, "using random Ethernet MAC\n"); 2011 eth_hw_addr_random(dev); 2012 } else { 2013 ether_addr_copy(dev->dev_addr, macaddr); 2014 } 2015 2016 SET_NETDEV_DEV(dev, &pdev->dev); 2017 dev_set_drvdata(&pdev->dev, dev); 2018 dev->ethtool_ops = &bcm_sysport_ethtool_ops; 2019 dev->netdev_ops = &bcm_sysport_netdev_ops; 2020 netif_napi_add(dev, &priv->napi, bcm_sysport_poll, 64); 2021 2022 /* HW supported features, none enabled by default */ 2023 dev->hw_features |= NETIF_F_RXCSUM | NETIF_F_HIGHDMA | 2024 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 2025 2026 /* Request the WOL interrupt and advertise suspend if available */ 2027 priv->wol_irq_disabled = 1; 2028 ret = devm_request_irq(&pdev->dev, priv->wol_irq, 2029 bcm_sysport_wol_isr, 0, dev->name, priv); 2030 if (!ret) 2031 device_set_wakeup_capable(&pdev->dev, 1); 2032 2033 /* Set the needed headroom once and for all */ 2034 BUILD_BUG_ON(sizeof(struct bcm_tsb) != 8); 2035 dev->needed_headroom += sizeof(struct bcm_tsb); 2036 2037 /* libphy will adjust the link state accordingly */ 2038 netif_carrier_off(dev); 2039 2040 ret = register_netdev(dev); 2041 if (ret) { 2042 dev_err(&pdev->dev, "failed to register net_device\n"); 2043 goto err_deregister_fixed_link; 2044 } 2045 2046 priv->rev = topctrl_readl(priv, REV_CNTL) & REV_MASK; 2047 dev_info(&pdev->dev, 2048 "Broadcom SYSTEMPORT%s" REV_FMT 2049 " at 0x%p (irqs: %d, %d, TXQs: %d, RXQs: %d)\n", 2050 priv->is_lite ? " Lite" : "", 2051 (priv->rev >> 8) & 0xff, priv->rev & 0xff, 2052 priv->base, priv->irq0, priv->irq1, txq, rxq); 2053 2054 return 0; 2055 2056 err_deregister_fixed_link: 2057 if (of_phy_is_fixed_link(dn)) 2058 of_phy_deregister_fixed_link(dn); 2059 err_free_netdev: 2060 free_netdev(dev); 2061 return ret; 2062 } 2063 2064 static int bcm_sysport_remove(struct platform_device *pdev) 2065 { 2066 struct net_device *dev = dev_get_drvdata(&pdev->dev); 2067 struct device_node *dn = pdev->dev.of_node; 2068 2069 /* Not much to do, ndo_close has been called 2070 * and we use managed allocations 2071 */ 2072 unregister_netdev(dev); 2073 if (of_phy_is_fixed_link(dn)) 2074 of_phy_deregister_fixed_link(dn); 2075 free_netdev(dev); 2076 dev_set_drvdata(&pdev->dev, NULL); 2077 2078 return 0; 2079 } 2080 2081 #ifdef CONFIG_PM_SLEEP 2082 static int bcm_sysport_suspend_to_wol(struct bcm_sysport_priv *priv) 2083 { 2084 struct net_device *ndev = priv->netdev; 2085 unsigned int timeout = 1000; 2086 u32 reg; 2087 2088 /* Password has already been programmed */ 2089 reg = umac_readl(priv, UMAC_MPD_CTRL); 2090 reg |= MPD_EN; 2091 reg &= ~PSW_EN; 2092 if (priv->wolopts & WAKE_MAGICSECURE) 2093 reg |= PSW_EN; 2094 umac_writel(priv, reg, UMAC_MPD_CTRL); 2095 2096 /* Make sure RBUF entered WoL mode as result */ 2097 do { 2098 reg = rbuf_readl(priv, RBUF_STATUS); 2099 if (reg & RBUF_WOL_MODE) 2100 break; 2101 2102 udelay(10); 2103 } while (timeout-- > 0); 2104 2105 /* Do not leave the UniMAC RBUF matching only MPD packets */ 2106 if (!timeout) { 2107 reg = umac_readl(priv, UMAC_MPD_CTRL); 2108 reg &= ~MPD_EN; 2109 umac_writel(priv, reg, UMAC_MPD_CTRL); 2110 netif_err(priv, wol, ndev, "failed to enter WOL mode\n"); 2111 return -ETIMEDOUT; 2112 } 2113 2114 /* UniMAC receive needs to be turned on */ 2115 umac_enable_set(priv, CMD_RX_EN, 1); 2116 2117 /* Enable the interrupt wake-up source */ 2118 intrl2_0_mask_clear(priv, INTRL2_0_MPD); 2119 2120 netif_dbg(priv, wol, ndev, "entered WOL mode\n"); 2121 2122 return 0; 2123 } 2124 2125 static int bcm_sysport_suspend(struct device *d) 2126 { 2127 struct net_device *dev = dev_get_drvdata(d); 2128 struct bcm_sysport_priv *priv = netdev_priv(dev); 2129 unsigned int i; 2130 int ret = 0; 2131 u32 reg; 2132 2133 if (!netif_running(dev)) 2134 return 0; 2135 2136 bcm_sysport_netif_stop(dev); 2137 2138 phy_suspend(dev->phydev); 2139 2140 netif_device_detach(dev); 2141 2142 /* Disable UniMAC RX */ 2143 umac_enable_set(priv, CMD_RX_EN, 0); 2144 2145 ret = rdma_enable_set(priv, 0); 2146 if (ret) { 2147 netdev_err(dev, "RDMA timeout!\n"); 2148 return ret; 2149 } 2150 2151 /* Disable RXCHK if enabled */ 2152 if (priv->rx_chk_en) { 2153 reg = rxchk_readl(priv, RXCHK_CONTROL); 2154 reg &= ~RXCHK_EN; 2155 rxchk_writel(priv, reg, RXCHK_CONTROL); 2156 } 2157 2158 /* Flush RX pipe */ 2159 if (!priv->wolopts) 2160 topctrl_writel(priv, RX_FLUSH, RX_FLUSH_CNTL); 2161 2162 ret = tdma_enable_set(priv, 0); 2163 if (ret) { 2164 netdev_err(dev, "TDMA timeout!\n"); 2165 return ret; 2166 } 2167 2168 /* Wait for a packet boundary */ 2169 usleep_range(2000, 3000); 2170 2171 umac_enable_set(priv, CMD_TX_EN, 0); 2172 2173 topctrl_writel(priv, TX_FLUSH, TX_FLUSH_CNTL); 2174 2175 /* Free RX/TX rings SW structures */ 2176 for (i = 0; i < dev->num_tx_queues; i++) 2177 bcm_sysport_fini_tx_ring(priv, i); 2178 bcm_sysport_fini_rx_ring(priv); 2179 2180 /* Get prepared for Wake-on-LAN */ 2181 if (device_may_wakeup(d) && priv->wolopts) 2182 ret = bcm_sysport_suspend_to_wol(priv); 2183 2184 return ret; 2185 } 2186 2187 static int bcm_sysport_resume(struct device *d) 2188 { 2189 struct net_device *dev = dev_get_drvdata(d); 2190 struct bcm_sysport_priv *priv = netdev_priv(dev); 2191 unsigned int i; 2192 u32 reg; 2193 int ret; 2194 2195 if (!netif_running(dev)) 2196 return 0; 2197 2198 umac_reset(priv); 2199 2200 /* We may have been suspended and never received a WOL event that 2201 * would turn off MPD detection, take care of that now 2202 */ 2203 bcm_sysport_resume_from_wol(priv); 2204 2205 /* Initialize both hardware and software ring */ 2206 for (i = 0; i < dev->num_tx_queues; i++) { 2207 ret = bcm_sysport_init_tx_ring(priv, i); 2208 if (ret) { 2209 netdev_err(dev, "failed to initialize TX ring %d\n", 2210 i); 2211 goto out_free_tx_rings; 2212 } 2213 } 2214 2215 /* Initialize linked-list */ 2216 tdma_writel(priv, TDMA_LL_RAM_INIT_BUSY, TDMA_STATUS); 2217 2218 /* Initialize RX ring */ 2219 ret = bcm_sysport_init_rx_ring(priv); 2220 if (ret) { 2221 netdev_err(dev, "failed to initialize RX ring\n"); 2222 goto out_free_rx_ring; 2223 } 2224 2225 netif_device_attach(dev); 2226 2227 /* RX pipe enable */ 2228 topctrl_writel(priv, 0, RX_FLUSH_CNTL); 2229 2230 ret = rdma_enable_set(priv, 1); 2231 if (ret) { 2232 netdev_err(dev, "failed to enable RDMA\n"); 2233 goto out_free_rx_ring; 2234 } 2235 2236 /* Enable rxhck */ 2237 if (priv->rx_chk_en) { 2238 reg = rxchk_readl(priv, RXCHK_CONTROL); 2239 reg |= RXCHK_EN; 2240 rxchk_writel(priv, reg, RXCHK_CONTROL); 2241 } 2242 2243 rbuf_init(priv); 2244 2245 /* Set maximum frame length */ 2246 if (!priv->is_lite) 2247 umac_writel(priv, UMAC_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN); 2248 else 2249 gib_set_pad_extension(priv); 2250 2251 /* Set MAC address */ 2252 umac_set_hw_addr(priv, dev->dev_addr); 2253 2254 umac_enable_set(priv, CMD_RX_EN, 1); 2255 2256 /* TX pipe enable */ 2257 topctrl_writel(priv, 0, TX_FLUSH_CNTL); 2258 2259 umac_enable_set(priv, CMD_TX_EN, 1); 2260 2261 ret = tdma_enable_set(priv, 1); 2262 if (ret) { 2263 netdev_err(dev, "TDMA timeout!\n"); 2264 goto out_free_rx_ring; 2265 } 2266 2267 phy_resume(dev->phydev); 2268 2269 bcm_sysport_netif_start(dev); 2270 2271 return 0; 2272 2273 out_free_rx_ring: 2274 bcm_sysport_fini_rx_ring(priv); 2275 out_free_tx_rings: 2276 for (i = 0; i < dev->num_tx_queues; i++) 2277 bcm_sysport_fini_tx_ring(priv, i); 2278 return ret; 2279 } 2280 #endif 2281 2282 static SIMPLE_DEV_PM_OPS(bcm_sysport_pm_ops, 2283 bcm_sysport_suspend, bcm_sysport_resume); 2284 2285 static struct platform_driver bcm_sysport_driver = { 2286 .probe = bcm_sysport_probe, 2287 .remove = bcm_sysport_remove, 2288 .driver = { 2289 .name = "brcm-systemport", 2290 .of_match_table = bcm_sysport_of_match, 2291 .pm = &bcm_sysport_pm_ops, 2292 }, 2293 }; 2294 module_platform_driver(bcm_sysport_driver); 2295 2296 MODULE_AUTHOR("Broadcom Corporation"); 2297 MODULE_DESCRIPTION("Broadcom System Port Ethernet MAC driver"); 2298 MODULE_ALIAS("platform:brcm-systemport"); 2299 MODULE_LICENSE("GPL"); 2300