1 /* 2 * Broadcom BCM7xxx System Port Ethernet MAC driver 3 * 4 * Copyright (C) 2014 Broadcom Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 12 13 #include <linux/init.h> 14 #include <linux/interrupt.h> 15 #include <linux/module.h> 16 #include <linux/kernel.h> 17 #include <linux/netdevice.h> 18 #include <linux/etherdevice.h> 19 #include <linux/platform_device.h> 20 #include <linux/of.h> 21 #include <linux/of_net.h> 22 #include <linux/of_mdio.h> 23 #include <linux/phy.h> 24 #include <linux/phy_fixed.h> 25 #include <net/dsa.h> 26 #include <net/ip.h> 27 #include <net/ipv6.h> 28 29 #include "bcmsysport.h" 30 31 /* I/O accessors register helpers */ 32 #define BCM_SYSPORT_IO_MACRO(name, offset) \ 33 static inline u32 name##_readl(struct bcm_sysport_priv *priv, u32 off) \ 34 { \ 35 u32 reg = readl_relaxed(priv->base + offset + off); \ 36 return reg; \ 37 } \ 38 static inline void name##_writel(struct bcm_sysport_priv *priv, \ 39 u32 val, u32 off) \ 40 { \ 41 writel_relaxed(val, priv->base + offset + off); \ 42 } \ 43 44 BCM_SYSPORT_IO_MACRO(intrl2_0, SYS_PORT_INTRL2_0_OFFSET); 45 BCM_SYSPORT_IO_MACRO(intrl2_1, SYS_PORT_INTRL2_1_OFFSET); 46 BCM_SYSPORT_IO_MACRO(umac, SYS_PORT_UMAC_OFFSET); 47 BCM_SYSPORT_IO_MACRO(gib, SYS_PORT_GIB_OFFSET); 48 BCM_SYSPORT_IO_MACRO(tdma, SYS_PORT_TDMA_OFFSET); 49 BCM_SYSPORT_IO_MACRO(rxchk, SYS_PORT_RXCHK_OFFSET); 50 BCM_SYSPORT_IO_MACRO(txchk, SYS_PORT_TXCHK_OFFSET); 51 BCM_SYSPORT_IO_MACRO(rbuf, SYS_PORT_RBUF_OFFSET); 52 BCM_SYSPORT_IO_MACRO(tbuf, SYS_PORT_TBUF_OFFSET); 53 BCM_SYSPORT_IO_MACRO(topctrl, SYS_PORT_TOPCTRL_OFFSET); 54 55 /* On SYSTEMPORT Lite, any register after RDMA_STATUS has the exact 56 * same layout, except it has been moved by 4 bytes up, *sigh* 57 */ 58 static inline u32 rdma_readl(struct bcm_sysport_priv *priv, u32 off) 59 { 60 if (priv->is_lite && off >= RDMA_STATUS) 61 off += 4; 62 return readl_relaxed(priv->base + SYS_PORT_RDMA_OFFSET + off); 63 } 64 65 static inline void rdma_writel(struct bcm_sysport_priv *priv, u32 val, u32 off) 66 { 67 if (priv->is_lite && off >= RDMA_STATUS) 68 off += 4; 69 writel_relaxed(val, priv->base + SYS_PORT_RDMA_OFFSET + off); 70 } 71 72 static inline u32 tdma_control_bit(struct bcm_sysport_priv *priv, u32 bit) 73 { 74 if (!priv->is_lite) { 75 return BIT(bit); 76 } else { 77 if (bit >= ACB_ALGO) 78 return BIT(bit + 1); 79 else 80 return BIT(bit); 81 } 82 } 83 84 /* L2-interrupt masking/unmasking helpers, does automatic saving of the applied 85 * mask in a software copy to avoid CPU_MASK_STATUS reads in hot-paths. 86 */ 87 #define BCM_SYSPORT_INTR_L2(which) \ 88 static inline void intrl2_##which##_mask_clear(struct bcm_sysport_priv *priv, \ 89 u32 mask) \ 90 { \ 91 priv->irq##which##_mask &= ~(mask); \ 92 intrl2_##which##_writel(priv, mask, INTRL2_CPU_MASK_CLEAR); \ 93 } \ 94 static inline void intrl2_##which##_mask_set(struct bcm_sysport_priv *priv, \ 95 u32 mask) \ 96 { \ 97 intrl2_## which##_writel(priv, mask, INTRL2_CPU_MASK_SET); \ 98 priv->irq##which##_mask |= (mask); \ 99 } \ 100 101 BCM_SYSPORT_INTR_L2(0) 102 BCM_SYSPORT_INTR_L2(1) 103 104 /* Register accesses to GISB/RBUS registers are expensive (few hundred 105 * nanoseconds), so keep the check for 64-bits explicit here to save 106 * one register write per-packet on 32-bits platforms. 107 */ 108 static inline void dma_desc_set_addr(struct bcm_sysport_priv *priv, 109 void __iomem *d, 110 dma_addr_t addr) 111 { 112 #ifdef CONFIG_PHYS_ADDR_T_64BIT 113 writel_relaxed(upper_32_bits(addr) & DESC_ADDR_HI_MASK, 114 d + DESC_ADDR_HI_STATUS_LEN); 115 #endif 116 writel_relaxed(lower_32_bits(addr), d + DESC_ADDR_LO); 117 } 118 119 static inline void tdma_port_write_desc_addr(struct bcm_sysport_priv *priv, 120 struct dma_desc *desc, 121 unsigned int port) 122 { 123 /* Ports are latched, so write upper address first */ 124 tdma_writel(priv, desc->addr_status_len, TDMA_WRITE_PORT_HI(port)); 125 tdma_writel(priv, desc->addr_lo, TDMA_WRITE_PORT_LO(port)); 126 } 127 128 /* Ethtool operations */ 129 static int bcm_sysport_set_rx_csum(struct net_device *dev, 130 netdev_features_t wanted) 131 { 132 struct bcm_sysport_priv *priv = netdev_priv(dev); 133 u32 reg; 134 135 priv->rx_chk_en = !!(wanted & NETIF_F_RXCSUM); 136 reg = rxchk_readl(priv, RXCHK_CONTROL); 137 if (priv->rx_chk_en) 138 reg |= RXCHK_EN; 139 else 140 reg &= ~RXCHK_EN; 141 142 /* If UniMAC forwards CRC, we need to skip over it to get 143 * a valid CHK bit to be set in the per-packet status word 144 */ 145 if (priv->rx_chk_en && priv->crc_fwd) 146 reg |= RXCHK_SKIP_FCS; 147 else 148 reg &= ~RXCHK_SKIP_FCS; 149 150 /* If Broadcom tags are enabled (e.g: using a switch), make 151 * sure we tell the RXCHK hardware to expect a 4-bytes Broadcom 152 * tag after the Ethernet MAC Source Address. 153 */ 154 if (netdev_uses_dsa(dev)) 155 reg |= RXCHK_BRCM_TAG_EN; 156 else 157 reg &= ~RXCHK_BRCM_TAG_EN; 158 159 rxchk_writel(priv, reg, RXCHK_CONTROL); 160 161 return 0; 162 } 163 164 static int bcm_sysport_set_tx_csum(struct net_device *dev, 165 netdev_features_t wanted) 166 { 167 struct bcm_sysport_priv *priv = netdev_priv(dev); 168 u32 reg; 169 170 /* Hardware transmit checksum requires us to enable the Transmit status 171 * block prepended to the packet contents 172 */ 173 priv->tsb_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)); 174 reg = tdma_readl(priv, TDMA_CONTROL); 175 if (priv->tsb_en) 176 reg |= tdma_control_bit(priv, TSB_EN); 177 else 178 reg &= ~tdma_control_bit(priv, TSB_EN); 179 tdma_writel(priv, reg, TDMA_CONTROL); 180 181 return 0; 182 } 183 184 static int bcm_sysport_set_features(struct net_device *dev, 185 netdev_features_t features) 186 { 187 netdev_features_t changed = features ^ dev->features; 188 netdev_features_t wanted = dev->wanted_features; 189 int ret = 0; 190 191 if (changed & NETIF_F_RXCSUM) 192 ret = bcm_sysport_set_rx_csum(dev, wanted); 193 if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)) 194 ret = bcm_sysport_set_tx_csum(dev, wanted); 195 196 return ret; 197 } 198 199 /* Hardware counters must be kept in sync because the order/offset 200 * is important here (order in structure declaration = order in hardware) 201 */ 202 static const struct bcm_sysport_stats bcm_sysport_gstrings_stats[] = { 203 /* general stats */ 204 STAT_NETDEV64(rx_packets), 205 STAT_NETDEV64(tx_packets), 206 STAT_NETDEV64(rx_bytes), 207 STAT_NETDEV64(tx_bytes), 208 STAT_NETDEV(rx_errors), 209 STAT_NETDEV(tx_errors), 210 STAT_NETDEV(rx_dropped), 211 STAT_NETDEV(tx_dropped), 212 STAT_NETDEV(multicast), 213 /* UniMAC RSV counters */ 214 STAT_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64), 215 STAT_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127), 216 STAT_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255), 217 STAT_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511), 218 STAT_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023), 219 STAT_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518), 220 STAT_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv), 221 STAT_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047), 222 STAT_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095), 223 STAT_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216), 224 STAT_MIB_RX("rx_pkts", mib.rx.pkt), 225 STAT_MIB_RX("rx_bytes", mib.rx.bytes), 226 STAT_MIB_RX("rx_multicast", mib.rx.mca), 227 STAT_MIB_RX("rx_broadcast", mib.rx.bca), 228 STAT_MIB_RX("rx_fcs", mib.rx.fcs), 229 STAT_MIB_RX("rx_control", mib.rx.cf), 230 STAT_MIB_RX("rx_pause", mib.rx.pf), 231 STAT_MIB_RX("rx_unknown", mib.rx.uo), 232 STAT_MIB_RX("rx_align", mib.rx.aln), 233 STAT_MIB_RX("rx_outrange", mib.rx.flr), 234 STAT_MIB_RX("rx_code", mib.rx.cde), 235 STAT_MIB_RX("rx_carrier", mib.rx.fcr), 236 STAT_MIB_RX("rx_oversize", mib.rx.ovr), 237 STAT_MIB_RX("rx_jabber", mib.rx.jbr), 238 STAT_MIB_RX("rx_mtu_err", mib.rx.mtue), 239 STAT_MIB_RX("rx_good_pkts", mib.rx.pok), 240 STAT_MIB_RX("rx_unicast", mib.rx.uc), 241 STAT_MIB_RX("rx_ppp", mib.rx.ppp), 242 STAT_MIB_RX("rx_crc", mib.rx.rcrc), 243 /* UniMAC TSV counters */ 244 STAT_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64), 245 STAT_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127), 246 STAT_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255), 247 STAT_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511), 248 STAT_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023), 249 STAT_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518), 250 STAT_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv), 251 STAT_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047), 252 STAT_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095), 253 STAT_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216), 254 STAT_MIB_TX("tx_pkts", mib.tx.pkts), 255 STAT_MIB_TX("tx_multicast", mib.tx.mca), 256 STAT_MIB_TX("tx_broadcast", mib.tx.bca), 257 STAT_MIB_TX("tx_pause", mib.tx.pf), 258 STAT_MIB_TX("tx_control", mib.tx.cf), 259 STAT_MIB_TX("tx_fcs_err", mib.tx.fcs), 260 STAT_MIB_TX("tx_oversize", mib.tx.ovr), 261 STAT_MIB_TX("tx_defer", mib.tx.drf), 262 STAT_MIB_TX("tx_excess_defer", mib.tx.edf), 263 STAT_MIB_TX("tx_single_col", mib.tx.scl), 264 STAT_MIB_TX("tx_multi_col", mib.tx.mcl), 265 STAT_MIB_TX("tx_late_col", mib.tx.lcl), 266 STAT_MIB_TX("tx_excess_col", mib.tx.ecl), 267 STAT_MIB_TX("tx_frags", mib.tx.frg), 268 STAT_MIB_TX("tx_total_col", mib.tx.ncl), 269 STAT_MIB_TX("tx_jabber", mib.tx.jbr), 270 STAT_MIB_TX("tx_bytes", mib.tx.bytes), 271 STAT_MIB_TX("tx_good_pkts", mib.tx.pok), 272 STAT_MIB_TX("tx_unicast", mib.tx.uc), 273 /* UniMAC RUNT counters */ 274 STAT_RUNT("rx_runt_pkts", mib.rx_runt_cnt), 275 STAT_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs), 276 STAT_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align), 277 STAT_RUNT("rx_runt_bytes", mib.rx_runt_bytes), 278 /* RXCHK misc statistics */ 279 STAT_RXCHK("rxchk_bad_csum", mib.rxchk_bad_csum, RXCHK_BAD_CSUM_CNTR), 280 STAT_RXCHK("rxchk_other_pkt_disc", mib.rxchk_other_pkt_disc, 281 RXCHK_OTHER_DISC_CNTR), 282 /* RBUF misc statistics */ 283 STAT_RBUF("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt, RBUF_OVFL_DISC_CNTR), 284 STAT_RBUF("rbuf_err_cnt", mib.rbuf_err_cnt, RBUF_ERR_PKT_CNTR), 285 STAT_MIB_SOFT("alloc_rx_buff_failed", mib.alloc_rx_buff_failed), 286 STAT_MIB_SOFT("rx_dma_failed", mib.rx_dma_failed), 287 STAT_MIB_SOFT("tx_dma_failed", mib.tx_dma_failed), 288 /* Per TX-queue statistics are dynamically appended */ 289 }; 290 291 #define BCM_SYSPORT_STATS_LEN ARRAY_SIZE(bcm_sysport_gstrings_stats) 292 293 static void bcm_sysport_get_drvinfo(struct net_device *dev, 294 struct ethtool_drvinfo *info) 295 { 296 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver)); 297 strlcpy(info->version, "0.1", sizeof(info->version)); 298 strlcpy(info->bus_info, "platform", sizeof(info->bus_info)); 299 } 300 301 static u32 bcm_sysport_get_msglvl(struct net_device *dev) 302 { 303 struct bcm_sysport_priv *priv = netdev_priv(dev); 304 305 return priv->msg_enable; 306 } 307 308 static void bcm_sysport_set_msglvl(struct net_device *dev, u32 enable) 309 { 310 struct bcm_sysport_priv *priv = netdev_priv(dev); 311 312 priv->msg_enable = enable; 313 } 314 315 static inline bool bcm_sysport_lite_stat_valid(enum bcm_sysport_stat_type type) 316 { 317 switch (type) { 318 case BCM_SYSPORT_STAT_NETDEV: 319 case BCM_SYSPORT_STAT_NETDEV64: 320 case BCM_SYSPORT_STAT_RXCHK: 321 case BCM_SYSPORT_STAT_RBUF: 322 case BCM_SYSPORT_STAT_SOFT: 323 return true; 324 default: 325 return false; 326 } 327 } 328 329 static int bcm_sysport_get_sset_count(struct net_device *dev, int string_set) 330 { 331 struct bcm_sysport_priv *priv = netdev_priv(dev); 332 const struct bcm_sysport_stats *s; 333 unsigned int i, j; 334 335 switch (string_set) { 336 case ETH_SS_STATS: 337 for (i = 0, j = 0; i < BCM_SYSPORT_STATS_LEN; i++) { 338 s = &bcm_sysport_gstrings_stats[i]; 339 if (priv->is_lite && 340 !bcm_sysport_lite_stat_valid(s->type)) 341 continue; 342 j++; 343 } 344 /* Include per-queue statistics */ 345 return j + dev->num_tx_queues * NUM_SYSPORT_TXQ_STAT; 346 default: 347 return -EOPNOTSUPP; 348 } 349 } 350 351 static void bcm_sysport_get_strings(struct net_device *dev, 352 u32 stringset, u8 *data) 353 { 354 struct bcm_sysport_priv *priv = netdev_priv(dev); 355 const struct bcm_sysport_stats *s; 356 char buf[128]; 357 int i, j; 358 359 switch (stringset) { 360 case ETH_SS_STATS: 361 for (i = 0, j = 0; i < BCM_SYSPORT_STATS_LEN; i++) { 362 s = &bcm_sysport_gstrings_stats[i]; 363 if (priv->is_lite && 364 !bcm_sysport_lite_stat_valid(s->type)) 365 continue; 366 367 memcpy(data + j * ETH_GSTRING_LEN, s->stat_string, 368 ETH_GSTRING_LEN); 369 j++; 370 } 371 372 for (i = 0; i < dev->num_tx_queues; i++) { 373 snprintf(buf, sizeof(buf), "txq%d_packets", i); 374 memcpy(data + j * ETH_GSTRING_LEN, buf, 375 ETH_GSTRING_LEN); 376 j++; 377 378 snprintf(buf, sizeof(buf), "txq%d_bytes", i); 379 memcpy(data + j * ETH_GSTRING_LEN, buf, 380 ETH_GSTRING_LEN); 381 j++; 382 } 383 break; 384 default: 385 break; 386 } 387 } 388 389 static void bcm_sysport_update_mib_counters(struct bcm_sysport_priv *priv) 390 { 391 int i, j = 0; 392 393 for (i = 0; i < BCM_SYSPORT_STATS_LEN; i++) { 394 const struct bcm_sysport_stats *s; 395 u8 offset = 0; 396 u32 val = 0; 397 char *p; 398 399 s = &bcm_sysport_gstrings_stats[i]; 400 switch (s->type) { 401 case BCM_SYSPORT_STAT_NETDEV: 402 case BCM_SYSPORT_STAT_NETDEV64: 403 case BCM_SYSPORT_STAT_SOFT: 404 continue; 405 case BCM_SYSPORT_STAT_MIB_RX: 406 case BCM_SYSPORT_STAT_MIB_TX: 407 case BCM_SYSPORT_STAT_RUNT: 408 if (priv->is_lite) 409 continue; 410 411 if (s->type != BCM_SYSPORT_STAT_MIB_RX) 412 offset = UMAC_MIB_STAT_OFFSET; 413 val = umac_readl(priv, UMAC_MIB_START + j + offset); 414 break; 415 case BCM_SYSPORT_STAT_RXCHK: 416 val = rxchk_readl(priv, s->reg_offset); 417 if (val == ~0) 418 rxchk_writel(priv, 0, s->reg_offset); 419 break; 420 case BCM_SYSPORT_STAT_RBUF: 421 val = rbuf_readl(priv, s->reg_offset); 422 if (val == ~0) 423 rbuf_writel(priv, 0, s->reg_offset); 424 break; 425 } 426 427 j += s->stat_sizeof; 428 p = (char *)priv + s->stat_offset; 429 *(u32 *)p = val; 430 } 431 432 netif_dbg(priv, hw, priv->netdev, "updated MIB counters\n"); 433 } 434 435 static void bcm_sysport_get_stats(struct net_device *dev, 436 struct ethtool_stats *stats, u64 *data) 437 { 438 struct bcm_sysport_priv *priv = netdev_priv(dev); 439 struct bcm_sysport_stats64 *stats64 = &priv->stats64; 440 struct u64_stats_sync *syncp = &priv->syncp; 441 struct bcm_sysport_tx_ring *ring; 442 unsigned int start; 443 int i, j; 444 445 if (netif_running(dev)) 446 bcm_sysport_update_mib_counters(priv); 447 448 for (i = 0, j = 0; i < BCM_SYSPORT_STATS_LEN; i++) { 449 const struct bcm_sysport_stats *s; 450 char *p; 451 452 s = &bcm_sysport_gstrings_stats[i]; 453 if (s->type == BCM_SYSPORT_STAT_NETDEV) 454 p = (char *)&dev->stats; 455 else if (s->type == BCM_SYSPORT_STAT_NETDEV64) 456 p = (char *)stats64; 457 else 458 p = (char *)priv; 459 460 if (priv->is_lite && !bcm_sysport_lite_stat_valid(s->type)) 461 continue; 462 p += s->stat_offset; 463 464 if (s->stat_sizeof == sizeof(u64)) 465 do { 466 start = u64_stats_fetch_begin_irq(syncp); 467 data[i] = *(u64 *)p; 468 } while (u64_stats_fetch_retry_irq(syncp, start)); 469 else 470 data[i] = *(u32 *)p; 471 j++; 472 } 473 474 /* For SYSTEMPORT Lite since we have holes in our statistics, j would 475 * be equal to BCM_SYSPORT_STATS_LEN at the end of the loop, but it 476 * needs to point to how many total statistics we have minus the 477 * number of per TX queue statistics 478 */ 479 j = bcm_sysport_get_sset_count(dev, ETH_SS_STATS) - 480 dev->num_tx_queues * NUM_SYSPORT_TXQ_STAT; 481 482 for (i = 0; i < dev->num_tx_queues; i++) { 483 ring = &priv->tx_rings[i]; 484 data[j] = ring->packets; 485 j++; 486 data[j] = ring->bytes; 487 j++; 488 } 489 } 490 491 static void bcm_sysport_get_wol(struct net_device *dev, 492 struct ethtool_wolinfo *wol) 493 { 494 struct bcm_sysport_priv *priv = netdev_priv(dev); 495 u32 reg; 496 497 wol->supported = WAKE_MAGIC | WAKE_MAGICSECURE; 498 wol->wolopts = priv->wolopts; 499 500 if (!(priv->wolopts & WAKE_MAGICSECURE)) 501 return; 502 503 /* Return the programmed SecureOn password */ 504 reg = umac_readl(priv, UMAC_PSW_MS); 505 put_unaligned_be16(reg, &wol->sopass[0]); 506 reg = umac_readl(priv, UMAC_PSW_LS); 507 put_unaligned_be32(reg, &wol->sopass[2]); 508 } 509 510 static int bcm_sysport_set_wol(struct net_device *dev, 511 struct ethtool_wolinfo *wol) 512 { 513 struct bcm_sysport_priv *priv = netdev_priv(dev); 514 struct device *kdev = &priv->pdev->dev; 515 u32 supported = WAKE_MAGIC | WAKE_MAGICSECURE; 516 517 if (!device_can_wakeup(kdev)) 518 return -ENOTSUPP; 519 520 if (wol->wolopts & ~supported) 521 return -EINVAL; 522 523 /* Program the SecureOn password */ 524 if (wol->wolopts & WAKE_MAGICSECURE) { 525 umac_writel(priv, get_unaligned_be16(&wol->sopass[0]), 526 UMAC_PSW_MS); 527 umac_writel(priv, get_unaligned_be32(&wol->sopass[2]), 528 UMAC_PSW_LS); 529 } 530 531 /* Flag the device and relevant IRQ as wakeup capable */ 532 if (wol->wolopts) { 533 device_set_wakeup_enable(kdev, 1); 534 if (priv->wol_irq_disabled) 535 enable_irq_wake(priv->wol_irq); 536 priv->wol_irq_disabled = 0; 537 } else { 538 device_set_wakeup_enable(kdev, 0); 539 /* Avoid unbalanced disable_irq_wake calls */ 540 if (!priv->wol_irq_disabled) 541 disable_irq_wake(priv->wol_irq); 542 priv->wol_irq_disabled = 1; 543 } 544 545 priv->wolopts = wol->wolopts; 546 547 return 0; 548 } 549 550 static int bcm_sysport_get_coalesce(struct net_device *dev, 551 struct ethtool_coalesce *ec) 552 { 553 struct bcm_sysport_priv *priv = netdev_priv(dev); 554 u32 reg; 555 556 reg = tdma_readl(priv, TDMA_DESC_RING_INTR_CONTROL(0)); 557 558 ec->tx_coalesce_usecs = (reg >> RING_TIMEOUT_SHIFT) * 8192 / 1000; 559 ec->tx_max_coalesced_frames = reg & RING_INTR_THRESH_MASK; 560 561 reg = rdma_readl(priv, RDMA_MBDONE_INTR); 562 563 ec->rx_coalesce_usecs = (reg >> RDMA_TIMEOUT_SHIFT) * 8192 / 1000; 564 ec->rx_max_coalesced_frames = reg & RDMA_INTR_THRESH_MASK; 565 566 return 0; 567 } 568 569 static int bcm_sysport_set_coalesce(struct net_device *dev, 570 struct ethtool_coalesce *ec) 571 { 572 struct bcm_sysport_priv *priv = netdev_priv(dev); 573 unsigned int i; 574 u32 reg; 575 576 /* Base system clock is 125Mhz, DMA timeout is this reference clock 577 * divided by 1024, which yield roughly 8.192 us, our maximum value has 578 * to fit in the RING_TIMEOUT_MASK (16 bits). 579 */ 580 if (ec->tx_max_coalesced_frames > RING_INTR_THRESH_MASK || 581 ec->tx_coalesce_usecs > (RING_TIMEOUT_MASK * 8) + 1 || 582 ec->rx_max_coalesced_frames > RDMA_INTR_THRESH_MASK || 583 ec->rx_coalesce_usecs > (RDMA_TIMEOUT_MASK * 8) + 1) 584 return -EINVAL; 585 586 if ((ec->tx_coalesce_usecs == 0 && ec->tx_max_coalesced_frames == 0) || 587 (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0)) 588 return -EINVAL; 589 590 for (i = 0; i < dev->num_tx_queues; i++) { 591 reg = tdma_readl(priv, TDMA_DESC_RING_INTR_CONTROL(i)); 592 reg &= ~(RING_INTR_THRESH_MASK | 593 RING_TIMEOUT_MASK << RING_TIMEOUT_SHIFT); 594 reg |= ec->tx_max_coalesced_frames; 595 reg |= DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000, 8192) << 596 RING_TIMEOUT_SHIFT; 597 tdma_writel(priv, reg, TDMA_DESC_RING_INTR_CONTROL(i)); 598 } 599 600 reg = rdma_readl(priv, RDMA_MBDONE_INTR); 601 reg &= ~(RDMA_INTR_THRESH_MASK | 602 RDMA_TIMEOUT_MASK << RDMA_TIMEOUT_SHIFT); 603 reg |= ec->rx_max_coalesced_frames; 604 reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192) << 605 RDMA_TIMEOUT_SHIFT; 606 rdma_writel(priv, reg, RDMA_MBDONE_INTR); 607 608 return 0; 609 } 610 611 static void bcm_sysport_free_cb(struct bcm_sysport_cb *cb) 612 { 613 dev_consume_skb_any(cb->skb); 614 cb->skb = NULL; 615 dma_unmap_addr_set(cb, dma_addr, 0); 616 } 617 618 static struct sk_buff *bcm_sysport_rx_refill(struct bcm_sysport_priv *priv, 619 struct bcm_sysport_cb *cb) 620 { 621 struct device *kdev = &priv->pdev->dev; 622 struct net_device *ndev = priv->netdev; 623 struct sk_buff *skb, *rx_skb; 624 dma_addr_t mapping; 625 626 /* Allocate a new SKB for a new packet */ 627 skb = netdev_alloc_skb(priv->netdev, RX_BUF_LENGTH); 628 if (!skb) { 629 priv->mib.alloc_rx_buff_failed++; 630 netif_err(priv, rx_err, ndev, "SKB alloc failed\n"); 631 return NULL; 632 } 633 634 mapping = dma_map_single(kdev, skb->data, 635 RX_BUF_LENGTH, DMA_FROM_DEVICE); 636 if (dma_mapping_error(kdev, mapping)) { 637 priv->mib.rx_dma_failed++; 638 dev_kfree_skb_any(skb); 639 netif_err(priv, rx_err, ndev, "DMA mapping failure\n"); 640 return NULL; 641 } 642 643 /* Grab the current SKB on the ring */ 644 rx_skb = cb->skb; 645 if (likely(rx_skb)) 646 dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr), 647 RX_BUF_LENGTH, DMA_FROM_DEVICE); 648 649 /* Put the new SKB on the ring */ 650 cb->skb = skb; 651 dma_unmap_addr_set(cb, dma_addr, mapping); 652 dma_desc_set_addr(priv, cb->bd_addr, mapping); 653 654 netif_dbg(priv, rx_status, ndev, "RX refill\n"); 655 656 /* Return the current SKB to the caller */ 657 return rx_skb; 658 } 659 660 static int bcm_sysport_alloc_rx_bufs(struct bcm_sysport_priv *priv) 661 { 662 struct bcm_sysport_cb *cb; 663 struct sk_buff *skb; 664 unsigned int i; 665 666 for (i = 0; i < priv->num_rx_bds; i++) { 667 cb = &priv->rx_cbs[i]; 668 skb = bcm_sysport_rx_refill(priv, cb); 669 if (skb) 670 dev_kfree_skb(skb); 671 if (!cb->skb) 672 return -ENOMEM; 673 } 674 675 return 0; 676 } 677 678 /* Poll the hardware for up to budget packets to process */ 679 static unsigned int bcm_sysport_desc_rx(struct bcm_sysport_priv *priv, 680 unsigned int budget) 681 { 682 struct bcm_sysport_stats64 *stats64 = &priv->stats64; 683 struct net_device *ndev = priv->netdev; 684 unsigned int processed = 0, to_process; 685 struct bcm_sysport_cb *cb; 686 struct sk_buff *skb; 687 unsigned int p_index; 688 u16 len, status; 689 struct bcm_rsb *rsb; 690 691 /* Clear status before servicing to reduce spurious interrupts */ 692 intrl2_0_writel(priv, INTRL2_0_RDMA_MBDONE, INTRL2_CPU_CLEAR); 693 694 /* Determine how much we should process since last call, SYSTEMPORT Lite 695 * groups the producer and consumer indexes into the same 32-bit 696 * which we access using RDMA_CONS_INDEX 697 */ 698 if (!priv->is_lite) 699 p_index = rdma_readl(priv, RDMA_PROD_INDEX); 700 else 701 p_index = rdma_readl(priv, RDMA_CONS_INDEX); 702 p_index &= RDMA_PROD_INDEX_MASK; 703 704 to_process = (p_index - priv->rx_c_index) & RDMA_CONS_INDEX_MASK; 705 706 netif_dbg(priv, rx_status, ndev, 707 "p_index=%d rx_c_index=%d to_process=%d\n", 708 p_index, priv->rx_c_index, to_process); 709 710 while ((processed < to_process) && (processed < budget)) { 711 cb = &priv->rx_cbs[priv->rx_read_ptr]; 712 skb = bcm_sysport_rx_refill(priv, cb); 713 714 715 /* We do not have a backing SKB, so we do not a corresponding 716 * DMA mapping for this incoming packet since 717 * bcm_sysport_rx_refill always either has both skb and mapping 718 * or none. 719 */ 720 if (unlikely(!skb)) { 721 netif_err(priv, rx_err, ndev, "out of memory!\n"); 722 ndev->stats.rx_dropped++; 723 ndev->stats.rx_errors++; 724 goto next; 725 } 726 727 /* Extract the Receive Status Block prepended */ 728 rsb = (struct bcm_rsb *)skb->data; 729 len = (rsb->rx_status_len >> DESC_LEN_SHIFT) & DESC_LEN_MASK; 730 status = (rsb->rx_status_len >> DESC_STATUS_SHIFT) & 731 DESC_STATUS_MASK; 732 733 netif_dbg(priv, rx_status, ndev, 734 "p=%d, c=%d, rd_ptr=%d, len=%d, flag=0x%04x\n", 735 p_index, priv->rx_c_index, priv->rx_read_ptr, 736 len, status); 737 738 if (unlikely(len > RX_BUF_LENGTH)) { 739 netif_err(priv, rx_status, ndev, "oversized packet\n"); 740 ndev->stats.rx_length_errors++; 741 ndev->stats.rx_errors++; 742 dev_kfree_skb_any(skb); 743 goto next; 744 } 745 746 if (unlikely(!(status & DESC_EOP) || !(status & DESC_SOP))) { 747 netif_err(priv, rx_status, ndev, "fragmented packet!\n"); 748 ndev->stats.rx_dropped++; 749 ndev->stats.rx_errors++; 750 dev_kfree_skb_any(skb); 751 goto next; 752 } 753 754 if (unlikely(status & (RX_STATUS_ERR | RX_STATUS_OVFLOW))) { 755 netif_err(priv, rx_err, ndev, "error packet\n"); 756 if (status & RX_STATUS_OVFLOW) 757 ndev->stats.rx_over_errors++; 758 ndev->stats.rx_dropped++; 759 ndev->stats.rx_errors++; 760 dev_kfree_skb_any(skb); 761 goto next; 762 } 763 764 skb_put(skb, len); 765 766 /* Hardware validated our checksum */ 767 if (likely(status & DESC_L4_CSUM)) 768 skb->ip_summed = CHECKSUM_UNNECESSARY; 769 770 /* Hardware pre-pends packets with 2bytes before Ethernet 771 * header plus we have the Receive Status Block, strip off all 772 * of this from the SKB. 773 */ 774 skb_pull(skb, sizeof(*rsb) + 2); 775 len -= (sizeof(*rsb) + 2); 776 777 /* UniMAC may forward CRC */ 778 if (priv->crc_fwd) { 779 skb_trim(skb, len - ETH_FCS_LEN); 780 len -= ETH_FCS_LEN; 781 } 782 783 skb->protocol = eth_type_trans(skb, ndev); 784 ndev->stats.rx_packets++; 785 ndev->stats.rx_bytes += len; 786 u64_stats_update_begin(&priv->syncp); 787 stats64->rx_packets++; 788 stats64->rx_bytes += len; 789 u64_stats_update_end(&priv->syncp); 790 791 napi_gro_receive(&priv->napi, skb); 792 next: 793 processed++; 794 priv->rx_read_ptr++; 795 796 if (priv->rx_read_ptr == priv->num_rx_bds) 797 priv->rx_read_ptr = 0; 798 } 799 800 return processed; 801 } 802 803 static void bcm_sysport_tx_reclaim_one(struct bcm_sysport_tx_ring *ring, 804 struct bcm_sysport_cb *cb, 805 unsigned int *bytes_compl, 806 unsigned int *pkts_compl) 807 { 808 struct bcm_sysport_priv *priv = ring->priv; 809 struct device *kdev = &priv->pdev->dev; 810 811 if (cb->skb) { 812 *bytes_compl += cb->skb->len; 813 dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr), 814 dma_unmap_len(cb, dma_len), 815 DMA_TO_DEVICE); 816 (*pkts_compl)++; 817 bcm_sysport_free_cb(cb); 818 /* SKB fragment */ 819 } else if (dma_unmap_addr(cb, dma_addr)) { 820 *bytes_compl += dma_unmap_len(cb, dma_len); 821 dma_unmap_page(kdev, dma_unmap_addr(cb, dma_addr), 822 dma_unmap_len(cb, dma_len), DMA_TO_DEVICE); 823 dma_unmap_addr_set(cb, dma_addr, 0); 824 } 825 } 826 827 /* Reclaim queued SKBs for transmission completion, lockless version */ 828 static unsigned int __bcm_sysport_tx_reclaim(struct bcm_sysport_priv *priv, 829 struct bcm_sysport_tx_ring *ring) 830 { 831 unsigned int c_index, last_c_index, last_tx_cn, num_tx_cbs; 832 unsigned int pkts_compl = 0, bytes_compl = 0; 833 struct net_device *ndev = priv->netdev; 834 struct bcm_sysport_cb *cb; 835 u32 hw_ind; 836 837 /* Clear status before servicing to reduce spurious interrupts */ 838 if (!ring->priv->is_lite) 839 intrl2_1_writel(ring->priv, BIT(ring->index), INTRL2_CPU_CLEAR); 840 else 841 intrl2_0_writel(ring->priv, BIT(ring->index + 842 INTRL2_0_TDMA_MBDONE_SHIFT), INTRL2_CPU_CLEAR); 843 844 /* Compute how many descriptors have been processed since last call */ 845 hw_ind = tdma_readl(priv, TDMA_DESC_RING_PROD_CONS_INDEX(ring->index)); 846 c_index = (hw_ind >> RING_CONS_INDEX_SHIFT) & RING_CONS_INDEX_MASK; 847 ring->p_index = (hw_ind & RING_PROD_INDEX_MASK); 848 849 last_c_index = ring->c_index; 850 num_tx_cbs = ring->size; 851 852 c_index &= (num_tx_cbs - 1); 853 854 if (c_index >= last_c_index) 855 last_tx_cn = c_index - last_c_index; 856 else 857 last_tx_cn = num_tx_cbs - last_c_index + c_index; 858 859 netif_dbg(priv, tx_done, ndev, 860 "ring=%d c_index=%d last_tx_cn=%d last_c_index=%d\n", 861 ring->index, c_index, last_tx_cn, last_c_index); 862 863 while (last_tx_cn-- > 0) { 864 cb = ring->cbs + last_c_index; 865 bcm_sysport_tx_reclaim_one(ring, cb, &bytes_compl, &pkts_compl); 866 867 ring->desc_count++; 868 last_c_index++; 869 last_c_index &= (num_tx_cbs - 1); 870 } 871 872 u64_stats_update_begin(&priv->syncp); 873 ring->packets += pkts_compl; 874 ring->bytes += bytes_compl; 875 u64_stats_update_end(&priv->syncp); 876 877 ring->c_index = c_index; 878 879 netif_dbg(priv, tx_done, ndev, 880 "ring=%d c_index=%d pkts_compl=%d, bytes_compl=%d\n", 881 ring->index, ring->c_index, pkts_compl, bytes_compl); 882 883 return pkts_compl; 884 } 885 886 /* Locked version of the per-ring TX reclaim routine */ 887 static unsigned int bcm_sysport_tx_reclaim(struct bcm_sysport_priv *priv, 888 struct bcm_sysport_tx_ring *ring) 889 { 890 struct netdev_queue *txq; 891 unsigned int released; 892 unsigned long flags; 893 894 txq = netdev_get_tx_queue(priv->netdev, ring->index); 895 896 spin_lock_irqsave(&ring->lock, flags); 897 released = __bcm_sysport_tx_reclaim(priv, ring); 898 if (released) 899 netif_tx_wake_queue(txq); 900 901 spin_unlock_irqrestore(&ring->lock, flags); 902 903 return released; 904 } 905 906 /* Locked version of the per-ring TX reclaim, but does not wake the queue */ 907 static void bcm_sysport_tx_clean(struct bcm_sysport_priv *priv, 908 struct bcm_sysport_tx_ring *ring) 909 { 910 unsigned long flags; 911 912 spin_lock_irqsave(&ring->lock, flags); 913 __bcm_sysport_tx_reclaim(priv, ring); 914 spin_unlock_irqrestore(&ring->lock, flags); 915 } 916 917 static int bcm_sysport_tx_poll(struct napi_struct *napi, int budget) 918 { 919 struct bcm_sysport_tx_ring *ring = 920 container_of(napi, struct bcm_sysport_tx_ring, napi); 921 unsigned int work_done = 0; 922 923 work_done = bcm_sysport_tx_reclaim(ring->priv, ring); 924 925 if (work_done == 0) { 926 napi_complete(napi); 927 /* re-enable TX interrupt */ 928 if (!ring->priv->is_lite) 929 intrl2_1_mask_clear(ring->priv, BIT(ring->index)); 930 else 931 intrl2_0_mask_clear(ring->priv, BIT(ring->index + 932 INTRL2_0_TDMA_MBDONE_SHIFT)); 933 934 return 0; 935 } 936 937 return budget; 938 } 939 940 static void bcm_sysport_tx_reclaim_all(struct bcm_sysport_priv *priv) 941 { 942 unsigned int q; 943 944 for (q = 0; q < priv->netdev->num_tx_queues; q++) 945 bcm_sysport_tx_reclaim(priv, &priv->tx_rings[q]); 946 } 947 948 static int bcm_sysport_poll(struct napi_struct *napi, int budget) 949 { 950 struct bcm_sysport_priv *priv = 951 container_of(napi, struct bcm_sysport_priv, napi); 952 unsigned int work_done = 0; 953 954 work_done = bcm_sysport_desc_rx(priv, budget); 955 956 priv->rx_c_index += work_done; 957 priv->rx_c_index &= RDMA_CONS_INDEX_MASK; 958 959 /* SYSTEMPORT Lite groups the producer/consumer index, producer is 960 * maintained by HW, but writes to it will be ignore while RDMA 961 * is active 962 */ 963 if (!priv->is_lite) 964 rdma_writel(priv, priv->rx_c_index, RDMA_CONS_INDEX); 965 else 966 rdma_writel(priv, priv->rx_c_index << 16, RDMA_CONS_INDEX); 967 968 if (work_done < budget) { 969 napi_complete_done(napi, work_done); 970 /* re-enable RX interrupts */ 971 intrl2_0_mask_clear(priv, INTRL2_0_RDMA_MBDONE); 972 } 973 974 return work_done; 975 } 976 977 static void bcm_sysport_resume_from_wol(struct bcm_sysport_priv *priv) 978 { 979 u32 reg; 980 981 /* Stop monitoring MPD interrupt */ 982 intrl2_0_mask_set(priv, INTRL2_0_MPD); 983 984 /* Clear the MagicPacket detection logic */ 985 reg = umac_readl(priv, UMAC_MPD_CTRL); 986 reg &= ~MPD_EN; 987 umac_writel(priv, reg, UMAC_MPD_CTRL); 988 989 netif_dbg(priv, wol, priv->netdev, "resumed from WOL\n"); 990 } 991 992 /* RX and misc interrupt routine */ 993 static irqreturn_t bcm_sysport_rx_isr(int irq, void *dev_id) 994 { 995 struct net_device *dev = dev_id; 996 struct bcm_sysport_priv *priv = netdev_priv(dev); 997 struct bcm_sysport_tx_ring *txr; 998 unsigned int ring, ring_bit; 999 1000 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) & 1001 ~intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS); 1002 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR); 1003 1004 if (unlikely(priv->irq0_stat == 0)) { 1005 netdev_warn(priv->netdev, "spurious RX interrupt\n"); 1006 return IRQ_NONE; 1007 } 1008 1009 if (priv->irq0_stat & INTRL2_0_RDMA_MBDONE) { 1010 if (likely(napi_schedule_prep(&priv->napi))) { 1011 /* disable RX interrupts */ 1012 intrl2_0_mask_set(priv, INTRL2_0_RDMA_MBDONE); 1013 __napi_schedule_irqoff(&priv->napi); 1014 } 1015 } 1016 1017 /* TX ring is full, perform a full reclaim since we do not know 1018 * which one would trigger this interrupt 1019 */ 1020 if (priv->irq0_stat & INTRL2_0_TX_RING_FULL) 1021 bcm_sysport_tx_reclaim_all(priv); 1022 1023 if (priv->irq0_stat & INTRL2_0_MPD) { 1024 netdev_info(priv->netdev, "Wake-on-LAN interrupt!\n"); 1025 bcm_sysport_resume_from_wol(priv); 1026 } 1027 1028 if (!priv->is_lite) 1029 goto out; 1030 1031 for (ring = 0; ring < dev->num_tx_queues; ring++) { 1032 ring_bit = BIT(ring + INTRL2_0_TDMA_MBDONE_SHIFT); 1033 if (!(priv->irq0_stat & ring_bit)) 1034 continue; 1035 1036 txr = &priv->tx_rings[ring]; 1037 1038 if (likely(napi_schedule_prep(&txr->napi))) { 1039 intrl2_0_mask_set(priv, ring_bit); 1040 __napi_schedule(&txr->napi); 1041 } 1042 } 1043 out: 1044 return IRQ_HANDLED; 1045 } 1046 1047 /* TX interrupt service routine */ 1048 static irqreturn_t bcm_sysport_tx_isr(int irq, void *dev_id) 1049 { 1050 struct net_device *dev = dev_id; 1051 struct bcm_sysport_priv *priv = netdev_priv(dev); 1052 struct bcm_sysport_tx_ring *txr; 1053 unsigned int ring; 1054 1055 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) & 1056 ~intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS); 1057 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 1058 1059 if (unlikely(priv->irq1_stat == 0)) { 1060 netdev_warn(priv->netdev, "spurious TX interrupt\n"); 1061 return IRQ_NONE; 1062 } 1063 1064 for (ring = 0; ring < dev->num_tx_queues; ring++) { 1065 if (!(priv->irq1_stat & BIT(ring))) 1066 continue; 1067 1068 txr = &priv->tx_rings[ring]; 1069 1070 if (likely(napi_schedule_prep(&txr->napi))) { 1071 intrl2_1_mask_set(priv, BIT(ring)); 1072 __napi_schedule_irqoff(&txr->napi); 1073 } 1074 } 1075 1076 return IRQ_HANDLED; 1077 } 1078 1079 static irqreturn_t bcm_sysport_wol_isr(int irq, void *dev_id) 1080 { 1081 struct bcm_sysport_priv *priv = dev_id; 1082 1083 pm_wakeup_event(&priv->pdev->dev, 0); 1084 1085 return IRQ_HANDLED; 1086 } 1087 1088 #ifdef CONFIG_NET_POLL_CONTROLLER 1089 static void bcm_sysport_poll_controller(struct net_device *dev) 1090 { 1091 struct bcm_sysport_priv *priv = netdev_priv(dev); 1092 1093 disable_irq(priv->irq0); 1094 bcm_sysport_rx_isr(priv->irq0, priv); 1095 enable_irq(priv->irq0); 1096 1097 if (!priv->is_lite) { 1098 disable_irq(priv->irq1); 1099 bcm_sysport_tx_isr(priv->irq1, priv); 1100 enable_irq(priv->irq1); 1101 } 1102 } 1103 #endif 1104 1105 static struct sk_buff *bcm_sysport_insert_tsb(struct sk_buff *skb, 1106 struct net_device *dev) 1107 { 1108 struct sk_buff *nskb; 1109 struct bcm_tsb *tsb; 1110 u32 csum_info; 1111 u8 ip_proto; 1112 u16 csum_start; 1113 u16 ip_ver; 1114 1115 /* Re-allocate SKB if needed */ 1116 if (unlikely(skb_headroom(skb) < sizeof(*tsb))) { 1117 nskb = skb_realloc_headroom(skb, sizeof(*tsb)); 1118 dev_kfree_skb(skb); 1119 if (!nskb) { 1120 dev->stats.tx_errors++; 1121 dev->stats.tx_dropped++; 1122 return NULL; 1123 } 1124 skb = nskb; 1125 } 1126 1127 tsb = skb_push(skb, sizeof(*tsb)); 1128 /* Zero-out TSB by default */ 1129 memset(tsb, 0, sizeof(*tsb)); 1130 1131 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1132 ip_ver = htons(skb->protocol); 1133 switch (ip_ver) { 1134 case ETH_P_IP: 1135 ip_proto = ip_hdr(skb)->protocol; 1136 break; 1137 case ETH_P_IPV6: 1138 ip_proto = ipv6_hdr(skb)->nexthdr; 1139 break; 1140 default: 1141 return skb; 1142 } 1143 1144 /* Get the checksum offset and the L4 (transport) offset */ 1145 csum_start = skb_checksum_start_offset(skb) - sizeof(*tsb); 1146 csum_info = (csum_start + skb->csum_offset) & L4_CSUM_PTR_MASK; 1147 csum_info |= (csum_start << L4_PTR_SHIFT); 1148 1149 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) { 1150 csum_info |= L4_LENGTH_VALID; 1151 if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP) 1152 csum_info |= L4_UDP; 1153 } else { 1154 csum_info = 0; 1155 } 1156 1157 tsb->l4_ptr_dest_map = csum_info; 1158 } 1159 1160 return skb; 1161 } 1162 1163 static netdev_tx_t bcm_sysport_xmit(struct sk_buff *skb, 1164 struct net_device *dev) 1165 { 1166 struct bcm_sysport_priv *priv = netdev_priv(dev); 1167 struct device *kdev = &priv->pdev->dev; 1168 struct bcm_sysport_tx_ring *ring; 1169 struct bcm_sysport_cb *cb; 1170 struct netdev_queue *txq; 1171 struct dma_desc *desc; 1172 unsigned int skb_len; 1173 unsigned long flags; 1174 dma_addr_t mapping; 1175 u32 len_status; 1176 u16 queue; 1177 int ret; 1178 1179 queue = skb_get_queue_mapping(skb); 1180 txq = netdev_get_tx_queue(dev, queue); 1181 ring = &priv->tx_rings[queue]; 1182 1183 /* lock against tx reclaim in BH context and TX ring full interrupt */ 1184 spin_lock_irqsave(&ring->lock, flags); 1185 if (unlikely(ring->desc_count == 0)) { 1186 netif_tx_stop_queue(txq); 1187 netdev_err(dev, "queue %d awake and ring full!\n", queue); 1188 ret = NETDEV_TX_BUSY; 1189 goto out; 1190 } 1191 1192 /* The Ethernet switch we are interfaced with needs packets to be at 1193 * least 64 bytes (including FCS) otherwise they will be discarded when 1194 * they enter the switch port logic. When Broadcom tags are enabled, we 1195 * need to make sure that packets are at least 68 bytes 1196 * (including FCS and tag) because the length verification is done after 1197 * the Broadcom tag is stripped off the ingress packet. 1198 */ 1199 if (skb_put_padto(skb, ETH_ZLEN + ENET_BRCM_TAG_LEN)) { 1200 ret = NETDEV_TX_OK; 1201 goto out; 1202 } 1203 1204 /* Insert TSB and checksum infos */ 1205 if (priv->tsb_en) { 1206 skb = bcm_sysport_insert_tsb(skb, dev); 1207 if (!skb) { 1208 ret = NETDEV_TX_OK; 1209 goto out; 1210 } 1211 } 1212 1213 skb_len = skb->len; 1214 1215 mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE); 1216 if (dma_mapping_error(kdev, mapping)) { 1217 priv->mib.tx_dma_failed++; 1218 netif_err(priv, tx_err, dev, "DMA map failed at %p (len=%d)\n", 1219 skb->data, skb_len); 1220 ret = NETDEV_TX_OK; 1221 goto out; 1222 } 1223 1224 /* Remember the SKB for future freeing */ 1225 cb = &ring->cbs[ring->curr_desc]; 1226 cb->skb = skb; 1227 dma_unmap_addr_set(cb, dma_addr, mapping); 1228 dma_unmap_len_set(cb, dma_len, skb_len); 1229 1230 /* Fetch a descriptor entry from our pool */ 1231 desc = ring->desc_cpu; 1232 1233 desc->addr_lo = lower_32_bits(mapping); 1234 len_status = upper_32_bits(mapping) & DESC_ADDR_HI_MASK; 1235 len_status |= (skb_len << DESC_LEN_SHIFT); 1236 len_status |= (DESC_SOP | DESC_EOP | TX_STATUS_APP_CRC) << 1237 DESC_STATUS_SHIFT; 1238 if (skb->ip_summed == CHECKSUM_PARTIAL) 1239 len_status |= (DESC_L4_CSUM << DESC_STATUS_SHIFT); 1240 1241 ring->curr_desc++; 1242 if (ring->curr_desc == ring->size) 1243 ring->curr_desc = 0; 1244 ring->desc_count--; 1245 1246 /* Ensure write completion of the descriptor status/length 1247 * in DRAM before the System Port WRITE_PORT register latches 1248 * the value 1249 */ 1250 wmb(); 1251 desc->addr_status_len = len_status; 1252 wmb(); 1253 1254 /* Write this descriptor address to the RING write port */ 1255 tdma_port_write_desc_addr(priv, desc, ring->index); 1256 1257 /* Check ring space and update SW control flow */ 1258 if (ring->desc_count == 0) 1259 netif_tx_stop_queue(txq); 1260 1261 netif_dbg(priv, tx_queued, dev, "ring=%d desc_count=%d, curr_desc=%d\n", 1262 ring->index, ring->desc_count, ring->curr_desc); 1263 1264 ret = NETDEV_TX_OK; 1265 out: 1266 spin_unlock_irqrestore(&ring->lock, flags); 1267 return ret; 1268 } 1269 1270 static void bcm_sysport_tx_timeout(struct net_device *dev) 1271 { 1272 netdev_warn(dev, "transmit timeout!\n"); 1273 1274 netif_trans_update(dev); 1275 dev->stats.tx_errors++; 1276 1277 netif_tx_wake_all_queues(dev); 1278 } 1279 1280 /* phylib adjust link callback */ 1281 static void bcm_sysport_adj_link(struct net_device *dev) 1282 { 1283 struct bcm_sysport_priv *priv = netdev_priv(dev); 1284 struct phy_device *phydev = dev->phydev; 1285 unsigned int changed = 0; 1286 u32 cmd_bits = 0, reg; 1287 1288 if (priv->old_link != phydev->link) { 1289 changed = 1; 1290 priv->old_link = phydev->link; 1291 } 1292 1293 if (priv->old_duplex != phydev->duplex) { 1294 changed = 1; 1295 priv->old_duplex = phydev->duplex; 1296 } 1297 1298 if (priv->is_lite) 1299 goto out; 1300 1301 switch (phydev->speed) { 1302 case SPEED_2500: 1303 cmd_bits = CMD_SPEED_2500; 1304 break; 1305 case SPEED_1000: 1306 cmd_bits = CMD_SPEED_1000; 1307 break; 1308 case SPEED_100: 1309 cmd_bits = CMD_SPEED_100; 1310 break; 1311 case SPEED_10: 1312 cmd_bits = CMD_SPEED_10; 1313 break; 1314 default: 1315 break; 1316 } 1317 cmd_bits <<= CMD_SPEED_SHIFT; 1318 1319 if (phydev->duplex == DUPLEX_HALF) 1320 cmd_bits |= CMD_HD_EN; 1321 1322 if (priv->old_pause != phydev->pause) { 1323 changed = 1; 1324 priv->old_pause = phydev->pause; 1325 } 1326 1327 if (!phydev->pause) 1328 cmd_bits |= CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE; 1329 1330 if (!changed) 1331 return; 1332 1333 if (phydev->link) { 1334 reg = umac_readl(priv, UMAC_CMD); 1335 reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) | 1336 CMD_HD_EN | CMD_RX_PAUSE_IGNORE | 1337 CMD_TX_PAUSE_IGNORE); 1338 reg |= cmd_bits; 1339 umac_writel(priv, reg, UMAC_CMD); 1340 } 1341 out: 1342 if (changed) 1343 phy_print_status(phydev); 1344 } 1345 1346 static int bcm_sysport_init_tx_ring(struct bcm_sysport_priv *priv, 1347 unsigned int index) 1348 { 1349 struct bcm_sysport_tx_ring *ring = &priv->tx_rings[index]; 1350 struct device *kdev = &priv->pdev->dev; 1351 size_t size; 1352 void *p; 1353 u32 reg; 1354 1355 /* Simple descriptors partitioning for now */ 1356 size = 256; 1357 1358 /* We just need one DMA descriptor which is DMA-able, since writing to 1359 * the port will allocate a new descriptor in its internal linked-list 1360 */ 1361 p = dma_zalloc_coherent(kdev, sizeof(struct dma_desc), &ring->desc_dma, 1362 GFP_KERNEL); 1363 if (!p) { 1364 netif_err(priv, hw, priv->netdev, "DMA alloc failed\n"); 1365 return -ENOMEM; 1366 } 1367 1368 ring->cbs = kcalloc(size, sizeof(struct bcm_sysport_cb), GFP_KERNEL); 1369 if (!ring->cbs) { 1370 dma_free_coherent(kdev, sizeof(struct dma_desc), 1371 ring->desc_cpu, ring->desc_dma); 1372 netif_err(priv, hw, priv->netdev, "CB allocation failed\n"); 1373 return -ENOMEM; 1374 } 1375 1376 /* Initialize SW view of the ring */ 1377 spin_lock_init(&ring->lock); 1378 ring->priv = priv; 1379 netif_tx_napi_add(priv->netdev, &ring->napi, bcm_sysport_tx_poll, 64); 1380 ring->index = index; 1381 ring->size = size; 1382 ring->alloc_size = ring->size; 1383 ring->desc_cpu = p; 1384 ring->desc_count = ring->size; 1385 ring->curr_desc = 0; 1386 1387 /* Initialize HW ring */ 1388 tdma_writel(priv, RING_EN, TDMA_DESC_RING_HEAD_TAIL_PTR(index)); 1389 tdma_writel(priv, 0, TDMA_DESC_RING_COUNT(index)); 1390 tdma_writel(priv, 1, TDMA_DESC_RING_INTR_CONTROL(index)); 1391 tdma_writel(priv, 0, TDMA_DESC_RING_PROD_CONS_INDEX(index)); 1392 tdma_writel(priv, RING_IGNORE_STATUS, TDMA_DESC_RING_MAPPING(index)); 1393 tdma_writel(priv, 0, TDMA_DESC_RING_PCP_DEI_VID(index)); 1394 1395 /* Do not use tdma_control_bit() here because TSB_SWAP1 collides 1396 * with the original definition of ACB_ALGO 1397 */ 1398 reg = tdma_readl(priv, TDMA_CONTROL); 1399 if (priv->is_lite) 1400 reg &= ~BIT(TSB_SWAP1); 1401 /* Set a correct TSB format based on host endian */ 1402 if (!IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 1403 reg |= tdma_control_bit(priv, TSB_SWAP0); 1404 else 1405 reg &= ~tdma_control_bit(priv, TSB_SWAP0); 1406 tdma_writel(priv, reg, TDMA_CONTROL); 1407 1408 /* Program the number of descriptors as MAX_THRESHOLD and half of 1409 * its size for the hysteresis trigger 1410 */ 1411 tdma_writel(priv, ring->size | 1412 1 << RING_HYST_THRESH_SHIFT, 1413 TDMA_DESC_RING_MAX_HYST(index)); 1414 1415 /* Enable the ring queue in the arbiter */ 1416 reg = tdma_readl(priv, TDMA_TIER1_ARB_0_QUEUE_EN); 1417 reg |= (1 << index); 1418 tdma_writel(priv, reg, TDMA_TIER1_ARB_0_QUEUE_EN); 1419 1420 napi_enable(&ring->napi); 1421 1422 netif_dbg(priv, hw, priv->netdev, 1423 "TDMA cfg, size=%d, desc_cpu=%p\n", 1424 ring->size, ring->desc_cpu); 1425 1426 return 0; 1427 } 1428 1429 static void bcm_sysport_fini_tx_ring(struct bcm_sysport_priv *priv, 1430 unsigned int index) 1431 { 1432 struct bcm_sysport_tx_ring *ring = &priv->tx_rings[index]; 1433 struct device *kdev = &priv->pdev->dev; 1434 u32 reg; 1435 1436 /* Caller should stop the TDMA engine */ 1437 reg = tdma_readl(priv, TDMA_STATUS); 1438 if (!(reg & TDMA_DISABLED)) 1439 netdev_warn(priv->netdev, "TDMA not stopped!\n"); 1440 1441 /* ring->cbs is the last part in bcm_sysport_init_tx_ring which could 1442 * fail, so by checking this pointer we know whether the TX ring was 1443 * fully initialized or not. 1444 */ 1445 if (!ring->cbs) 1446 return; 1447 1448 napi_disable(&ring->napi); 1449 netif_napi_del(&ring->napi); 1450 1451 bcm_sysport_tx_clean(priv, ring); 1452 1453 kfree(ring->cbs); 1454 ring->cbs = NULL; 1455 1456 if (ring->desc_dma) { 1457 dma_free_coherent(kdev, sizeof(struct dma_desc), 1458 ring->desc_cpu, ring->desc_dma); 1459 ring->desc_dma = 0; 1460 } 1461 ring->size = 0; 1462 ring->alloc_size = 0; 1463 1464 netif_dbg(priv, hw, priv->netdev, "TDMA fini done\n"); 1465 } 1466 1467 /* RDMA helper */ 1468 static inline int rdma_enable_set(struct bcm_sysport_priv *priv, 1469 unsigned int enable) 1470 { 1471 unsigned int timeout = 1000; 1472 u32 reg; 1473 1474 reg = rdma_readl(priv, RDMA_CONTROL); 1475 if (enable) 1476 reg |= RDMA_EN; 1477 else 1478 reg &= ~RDMA_EN; 1479 rdma_writel(priv, reg, RDMA_CONTROL); 1480 1481 /* Poll for RMDA disabling completion */ 1482 do { 1483 reg = rdma_readl(priv, RDMA_STATUS); 1484 if (!!(reg & RDMA_DISABLED) == !enable) 1485 return 0; 1486 usleep_range(1000, 2000); 1487 } while (timeout-- > 0); 1488 1489 netdev_err(priv->netdev, "timeout waiting for RDMA to finish\n"); 1490 1491 return -ETIMEDOUT; 1492 } 1493 1494 /* TDMA helper */ 1495 static inline int tdma_enable_set(struct bcm_sysport_priv *priv, 1496 unsigned int enable) 1497 { 1498 unsigned int timeout = 1000; 1499 u32 reg; 1500 1501 reg = tdma_readl(priv, TDMA_CONTROL); 1502 if (enable) 1503 reg |= tdma_control_bit(priv, TDMA_EN); 1504 else 1505 reg &= ~tdma_control_bit(priv, TDMA_EN); 1506 tdma_writel(priv, reg, TDMA_CONTROL); 1507 1508 /* Poll for TMDA disabling completion */ 1509 do { 1510 reg = tdma_readl(priv, TDMA_STATUS); 1511 if (!!(reg & TDMA_DISABLED) == !enable) 1512 return 0; 1513 1514 usleep_range(1000, 2000); 1515 } while (timeout-- > 0); 1516 1517 netdev_err(priv->netdev, "timeout waiting for TDMA to finish\n"); 1518 1519 return -ETIMEDOUT; 1520 } 1521 1522 static int bcm_sysport_init_rx_ring(struct bcm_sysport_priv *priv) 1523 { 1524 struct bcm_sysport_cb *cb; 1525 u32 reg; 1526 int ret; 1527 int i; 1528 1529 /* Initialize SW view of the RX ring */ 1530 priv->num_rx_bds = priv->num_rx_desc_words / WORDS_PER_DESC; 1531 priv->rx_bds = priv->base + SYS_PORT_RDMA_OFFSET; 1532 priv->rx_c_index = 0; 1533 priv->rx_read_ptr = 0; 1534 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct bcm_sysport_cb), 1535 GFP_KERNEL); 1536 if (!priv->rx_cbs) { 1537 netif_err(priv, hw, priv->netdev, "CB allocation failed\n"); 1538 return -ENOMEM; 1539 } 1540 1541 for (i = 0; i < priv->num_rx_bds; i++) { 1542 cb = priv->rx_cbs + i; 1543 cb->bd_addr = priv->rx_bds + i * DESC_SIZE; 1544 } 1545 1546 ret = bcm_sysport_alloc_rx_bufs(priv); 1547 if (ret) { 1548 netif_err(priv, hw, priv->netdev, "SKB allocation failed\n"); 1549 return ret; 1550 } 1551 1552 /* Initialize HW, ensure RDMA is disabled */ 1553 reg = rdma_readl(priv, RDMA_STATUS); 1554 if (!(reg & RDMA_DISABLED)) 1555 rdma_enable_set(priv, 0); 1556 1557 rdma_writel(priv, 0, RDMA_WRITE_PTR_LO); 1558 rdma_writel(priv, 0, RDMA_WRITE_PTR_HI); 1559 rdma_writel(priv, 0, RDMA_PROD_INDEX); 1560 rdma_writel(priv, 0, RDMA_CONS_INDEX); 1561 rdma_writel(priv, priv->num_rx_bds << RDMA_RING_SIZE_SHIFT | 1562 RX_BUF_LENGTH, RDMA_RING_BUF_SIZE); 1563 /* Operate the queue in ring mode */ 1564 rdma_writel(priv, 0, RDMA_START_ADDR_HI); 1565 rdma_writel(priv, 0, RDMA_START_ADDR_LO); 1566 rdma_writel(priv, 0, RDMA_END_ADDR_HI); 1567 rdma_writel(priv, priv->num_rx_desc_words - 1, RDMA_END_ADDR_LO); 1568 1569 rdma_writel(priv, 1, RDMA_MBDONE_INTR); 1570 1571 netif_dbg(priv, hw, priv->netdev, 1572 "RDMA cfg, num_rx_bds=%d, rx_bds=%p\n", 1573 priv->num_rx_bds, priv->rx_bds); 1574 1575 return 0; 1576 } 1577 1578 static void bcm_sysport_fini_rx_ring(struct bcm_sysport_priv *priv) 1579 { 1580 struct bcm_sysport_cb *cb; 1581 unsigned int i; 1582 u32 reg; 1583 1584 /* Caller should ensure RDMA is disabled */ 1585 reg = rdma_readl(priv, RDMA_STATUS); 1586 if (!(reg & RDMA_DISABLED)) 1587 netdev_warn(priv->netdev, "RDMA not stopped!\n"); 1588 1589 for (i = 0; i < priv->num_rx_bds; i++) { 1590 cb = &priv->rx_cbs[i]; 1591 if (dma_unmap_addr(cb, dma_addr)) 1592 dma_unmap_single(&priv->pdev->dev, 1593 dma_unmap_addr(cb, dma_addr), 1594 RX_BUF_LENGTH, DMA_FROM_DEVICE); 1595 bcm_sysport_free_cb(cb); 1596 } 1597 1598 kfree(priv->rx_cbs); 1599 priv->rx_cbs = NULL; 1600 1601 netif_dbg(priv, hw, priv->netdev, "RDMA fini done\n"); 1602 } 1603 1604 static void bcm_sysport_set_rx_mode(struct net_device *dev) 1605 { 1606 struct bcm_sysport_priv *priv = netdev_priv(dev); 1607 u32 reg; 1608 1609 if (priv->is_lite) 1610 return; 1611 1612 reg = umac_readl(priv, UMAC_CMD); 1613 if (dev->flags & IFF_PROMISC) 1614 reg |= CMD_PROMISC; 1615 else 1616 reg &= ~CMD_PROMISC; 1617 umac_writel(priv, reg, UMAC_CMD); 1618 1619 /* No support for ALLMULTI */ 1620 if (dev->flags & IFF_ALLMULTI) 1621 return; 1622 } 1623 1624 static inline void umac_enable_set(struct bcm_sysport_priv *priv, 1625 u32 mask, unsigned int enable) 1626 { 1627 u32 reg; 1628 1629 if (!priv->is_lite) { 1630 reg = umac_readl(priv, UMAC_CMD); 1631 if (enable) 1632 reg |= mask; 1633 else 1634 reg &= ~mask; 1635 umac_writel(priv, reg, UMAC_CMD); 1636 } else { 1637 reg = gib_readl(priv, GIB_CONTROL); 1638 if (enable) 1639 reg |= mask; 1640 else 1641 reg &= ~mask; 1642 gib_writel(priv, reg, GIB_CONTROL); 1643 } 1644 1645 /* UniMAC stops on a packet boundary, wait for a full-sized packet 1646 * to be processed (1 msec). 1647 */ 1648 if (enable == 0) 1649 usleep_range(1000, 2000); 1650 } 1651 1652 static inline void umac_reset(struct bcm_sysport_priv *priv) 1653 { 1654 u32 reg; 1655 1656 if (priv->is_lite) 1657 return; 1658 1659 reg = umac_readl(priv, UMAC_CMD); 1660 reg |= CMD_SW_RESET; 1661 umac_writel(priv, reg, UMAC_CMD); 1662 udelay(10); 1663 reg = umac_readl(priv, UMAC_CMD); 1664 reg &= ~CMD_SW_RESET; 1665 umac_writel(priv, reg, UMAC_CMD); 1666 } 1667 1668 static void umac_set_hw_addr(struct bcm_sysport_priv *priv, 1669 unsigned char *addr) 1670 { 1671 u32 mac0 = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | 1672 addr[3]; 1673 u32 mac1 = (addr[4] << 8) | addr[5]; 1674 1675 if (!priv->is_lite) { 1676 umac_writel(priv, mac0, UMAC_MAC0); 1677 umac_writel(priv, mac1, UMAC_MAC1); 1678 } else { 1679 gib_writel(priv, mac0, GIB_MAC0); 1680 gib_writel(priv, mac1, GIB_MAC1); 1681 } 1682 } 1683 1684 static void topctrl_flush(struct bcm_sysport_priv *priv) 1685 { 1686 topctrl_writel(priv, RX_FLUSH, RX_FLUSH_CNTL); 1687 topctrl_writel(priv, TX_FLUSH, TX_FLUSH_CNTL); 1688 mdelay(1); 1689 topctrl_writel(priv, 0, RX_FLUSH_CNTL); 1690 topctrl_writel(priv, 0, TX_FLUSH_CNTL); 1691 } 1692 1693 static int bcm_sysport_change_mac(struct net_device *dev, void *p) 1694 { 1695 struct bcm_sysport_priv *priv = netdev_priv(dev); 1696 struct sockaddr *addr = p; 1697 1698 if (!is_valid_ether_addr(addr->sa_data)) 1699 return -EINVAL; 1700 1701 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 1702 1703 /* interface is disabled, changes to MAC will be reflected on next 1704 * open call 1705 */ 1706 if (!netif_running(dev)) 1707 return 0; 1708 1709 umac_set_hw_addr(priv, dev->dev_addr); 1710 1711 return 0; 1712 } 1713 1714 static void bcm_sysport_get_stats64(struct net_device *dev, 1715 struct rtnl_link_stats64 *stats) 1716 { 1717 struct bcm_sysport_priv *priv = netdev_priv(dev); 1718 struct bcm_sysport_stats64 *stats64 = &priv->stats64; 1719 struct bcm_sysport_tx_ring *ring; 1720 u64 tx_packets = 0, tx_bytes = 0; 1721 unsigned int start; 1722 unsigned int q; 1723 1724 netdev_stats_to_stats64(stats, &dev->stats); 1725 1726 for (q = 0; q < dev->num_tx_queues; q++) { 1727 ring = &priv->tx_rings[q]; 1728 do { 1729 start = u64_stats_fetch_begin_irq(&priv->syncp); 1730 tx_bytes = ring->bytes; 1731 tx_packets = ring->packets; 1732 } while (u64_stats_fetch_retry_irq(&priv->syncp, start)); 1733 1734 stats->tx_bytes += tx_bytes; 1735 stats->tx_packets += tx_packets; 1736 } 1737 1738 /* lockless update tx_bytes and tx_packets */ 1739 u64_stats_update_begin(&priv->syncp); 1740 stats64->tx_bytes = stats->tx_bytes; 1741 stats64->tx_packets = stats->tx_packets; 1742 u64_stats_update_end(&priv->syncp); 1743 1744 do { 1745 start = u64_stats_fetch_begin_irq(&priv->syncp); 1746 stats->rx_packets = stats64->rx_packets; 1747 stats->rx_bytes = stats64->rx_bytes; 1748 } while (u64_stats_fetch_retry_irq(&priv->syncp, start)); 1749 } 1750 1751 static void bcm_sysport_netif_start(struct net_device *dev) 1752 { 1753 struct bcm_sysport_priv *priv = netdev_priv(dev); 1754 1755 /* Enable NAPI */ 1756 napi_enable(&priv->napi); 1757 1758 /* Enable RX interrupt and TX ring full interrupt */ 1759 intrl2_0_mask_clear(priv, INTRL2_0_RDMA_MBDONE | INTRL2_0_TX_RING_FULL); 1760 1761 phy_start(dev->phydev); 1762 1763 /* Enable TX interrupts for the TXQs */ 1764 if (!priv->is_lite) 1765 intrl2_1_mask_clear(priv, 0xffffffff); 1766 else 1767 intrl2_0_mask_clear(priv, INTRL2_0_TDMA_MBDONE_MASK); 1768 1769 /* Last call before we start the real business */ 1770 netif_tx_start_all_queues(dev); 1771 } 1772 1773 static void rbuf_init(struct bcm_sysport_priv *priv) 1774 { 1775 u32 reg; 1776 1777 reg = rbuf_readl(priv, RBUF_CONTROL); 1778 reg |= RBUF_4B_ALGN | RBUF_RSB_EN; 1779 /* Set a correct RSB format on SYSTEMPORT Lite */ 1780 if (priv->is_lite) 1781 reg &= ~RBUF_RSB_SWAP1; 1782 1783 /* Set a correct RSB format based on host endian */ 1784 if (!IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 1785 reg |= RBUF_RSB_SWAP0; 1786 else 1787 reg &= ~RBUF_RSB_SWAP0; 1788 rbuf_writel(priv, reg, RBUF_CONTROL); 1789 } 1790 1791 static inline void bcm_sysport_mask_all_intrs(struct bcm_sysport_priv *priv) 1792 { 1793 intrl2_0_mask_set(priv, 0xffffffff); 1794 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 1795 if (!priv->is_lite) { 1796 intrl2_1_mask_set(priv, 0xffffffff); 1797 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 1798 } 1799 } 1800 1801 static inline void gib_set_pad_extension(struct bcm_sysport_priv *priv) 1802 { 1803 u32 __maybe_unused reg; 1804 1805 /* Include Broadcom tag in pad extension */ 1806 if (netdev_uses_dsa(priv->netdev)) { 1807 reg = gib_readl(priv, GIB_CONTROL); 1808 reg &= ~(GIB_PAD_EXTENSION_MASK << GIB_PAD_EXTENSION_SHIFT); 1809 reg |= ENET_BRCM_TAG_LEN << GIB_PAD_EXTENSION_SHIFT; 1810 gib_writel(priv, reg, GIB_CONTROL); 1811 } 1812 } 1813 1814 static int bcm_sysport_open(struct net_device *dev) 1815 { 1816 struct bcm_sysport_priv *priv = netdev_priv(dev); 1817 struct phy_device *phydev; 1818 unsigned int i; 1819 int ret; 1820 1821 /* Reset UniMAC */ 1822 umac_reset(priv); 1823 1824 /* Flush TX and RX FIFOs at TOPCTRL level */ 1825 topctrl_flush(priv); 1826 1827 /* Disable the UniMAC RX/TX */ 1828 umac_enable_set(priv, CMD_RX_EN | CMD_TX_EN, 0); 1829 1830 /* Enable RBUF 2bytes alignment and Receive Status Block */ 1831 rbuf_init(priv); 1832 1833 /* Set maximum frame length */ 1834 if (!priv->is_lite) 1835 umac_writel(priv, UMAC_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN); 1836 else 1837 gib_set_pad_extension(priv); 1838 1839 /* Set MAC address */ 1840 umac_set_hw_addr(priv, dev->dev_addr); 1841 1842 /* Read CRC forward */ 1843 if (!priv->is_lite) 1844 priv->crc_fwd = !!(umac_readl(priv, UMAC_CMD) & CMD_CRC_FWD); 1845 else 1846 priv->crc_fwd = !!(gib_readl(priv, GIB_CONTROL) & 1847 GIB_FCS_STRIP); 1848 1849 phydev = of_phy_connect(dev, priv->phy_dn, bcm_sysport_adj_link, 1850 0, priv->phy_interface); 1851 if (!phydev) { 1852 netdev_err(dev, "could not attach to PHY\n"); 1853 return -ENODEV; 1854 } 1855 1856 /* Reset house keeping link status */ 1857 priv->old_duplex = -1; 1858 priv->old_link = -1; 1859 priv->old_pause = -1; 1860 1861 /* mask all interrupts and request them */ 1862 bcm_sysport_mask_all_intrs(priv); 1863 1864 ret = request_irq(priv->irq0, bcm_sysport_rx_isr, 0, dev->name, dev); 1865 if (ret) { 1866 netdev_err(dev, "failed to request RX interrupt\n"); 1867 goto out_phy_disconnect; 1868 } 1869 1870 if (!priv->is_lite) { 1871 ret = request_irq(priv->irq1, bcm_sysport_tx_isr, 0, 1872 dev->name, dev); 1873 if (ret) { 1874 netdev_err(dev, "failed to request TX interrupt\n"); 1875 goto out_free_irq0; 1876 } 1877 } 1878 1879 /* Initialize both hardware and software ring */ 1880 for (i = 0; i < dev->num_tx_queues; i++) { 1881 ret = bcm_sysport_init_tx_ring(priv, i); 1882 if (ret) { 1883 netdev_err(dev, "failed to initialize TX ring %d\n", 1884 i); 1885 goto out_free_tx_ring; 1886 } 1887 } 1888 1889 /* Initialize linked-list */ 1890 tdma_writel(priv, TDMA_LL_RAM_INIT_BUSY, TDMA_STATUS); 1891 1892 /* Initialize RX ring */ 1893 ret = bcm_sysport_init_rx_ring(priv); 1894 if (ret) { 1895 netdev_err(dev, "failed to initialize RX ring\n"); 1896 goto out_free_rx_ring; 1897 } 1898 1899 /* Turn on RDMA */ 1900 ret = rdma_enable_set(priv, 1); 1901 if (ret) 1902 goto out_free_rx_ring; 1903 1904 /* Turn on TDMA */ 1905 ret = tdma_enable_set(priv, 1); 1906 if (ret) 1907 goto out_clear_rx_int; 1908 1909 /* Turn on UniMAC TX/RX */ 1910 umac_enable_set(priv, CMD_RX_EN | CMD_TX_EN, 1); 1911 1912 bcm_sysport_netif_start(dev); 1913 1914 return 0; 1915 1916 out_clear_rx_int: 1917 intrl2_0_mask_set(priv, INTRL2_0_RDMA_MBDONE | INTRL2_0_TX_RING_FULL); 1918 out_free_rx_ring: 1919 bcm_sysport_fini_rx_ring(priv); 1920 out_free_tx_ring: 1921 for (i = 0; i < dev->num_tx_queues; i++) 1922 bcm_sysport_fini_tx_ring(priv, i); 1923 if (!priv->is_lite) 1924 free_irq(priv->irq1, dev); 1925 out_free_irq0: 1926 free_irq(priv->irq0, dev); 1927 out_phy_disconnect: 1928 phy_disconnect(phydev); 1929 return ret; 1930 } 1931 1932 static void bcm_sysport_netif_stop(struct net_device *dev) 1933 { 1934 struct bcm_sysport_priv *priv = netdev_priv(dev); 1935 1936 /* stop all software from updating hardware */ 1937 netif_tx_stop_all_queues(dev); 1938 napi_disable(&priv->napi); 1939 phy_stop(dev->phydev); 1940 1941 /* mask all interrupts */ 1942 bcm_sysport_mask_all_intrs(priv); 1943 } 1944 1945 static int bcm_sysport_stop(struct net_device *dev) 1946 { 1947 struct bcm_sysport_priv *priv = netdev_priv(dev); 1948 unsigned int i; 1949 int ret; 1950 1951 bcm_sysport_netif_stop(dev); 1952 1953 /* Disable UniMAC RX */ 1954 umac_enable_set(priv, CMD_RX_EN, 0); 1955 1956 ret = tdma_enable_set(priv, 0); 1957 if (ret) { 1958 netdev_err(dev, "timeout disabling RDMA\n"); 1959 return ret; 1960 } 1961 1962 /* Wait for a maximum packet size to be drained */ 1963 usleep_range(2000, 3000); 1964 1965 ret = rdma_enable_set(priv, 0); 1966 if (ret) { 1967 netdev_err(dev, "timeout disabling TDMA\n"); 1968 return ret; 1969 } 1970 1971 /* Disable UniMAC TX */ 1972 umac_enable_set(priv, CMD_TX_EN, 0); 1973 1974 /* Free RX/TX rings SW structures */ 1975 for (i = 0; i < dev->num_tx_queues; i++) 1976 bcm_sysport_fini_tx_ring(priv, i); 1977 bcm_sysport_fini_rx_ring(priv); 1978 1979 free_irq(priv->irq0, dev); 1980 if (!priv->is_lite) 1981 free_irq(priv->irq1, dev); 1982 1983 /* Disconnect from PHY */ 1984 phy_disconnect(dev->phydev); 1985 1986 return 0; 1987 } 1988 1989 static const struct ethtool_ops bcm_sysport_ethtool_ops = { 1990 .get_drvinfo = bcm_sysport_get_drvinfo, 1991 .get_msglevel = bcm_sysport_get_msglvl, 1992 .set_msglevel = bcm_sysport_set_msglvl, 1993 .get_link = ethtool_op_get_link, 1994 .get_strings = bcm_sysport_get_strings, 1995 .get_ethtool_stats = bcm_sysport_get_stats, 1996 .get_sset_count = bcm_sysport_get_sset_count, 1997 .get_wol = bcm_sysport_get_wol, 1998 .set_wol = bcm_sysport_set_wol, 1999 .get_coalesce = bcm_sysport_get_coalesce, 2000 .set_coalesce = bcm_sysport_set_coalesce, 2001 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2002 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2003 }; 2004 2005 static const struct net_device_ops bcm_sysport_netdev_ops = { 2006 .ndo_start_xmit = bcm_sysport_xmit, 2007 .ndo_tx_timeout = bcm_sysport_tx_timeout, 2008 .ndo_open = bcm_sysport_open, 2009 .ndo_stop = bcm_sysport_stop, 2010 .ndo_set_features = bcm_sysport_set_features, 2011 .ndo_set_rx_mode = bcm_sysport_set_rx_mode, 2012 .ndo_set_mac_address = bcm_sysport_change_mac, 2013 #ifdef CONFIG_NET_POLL_CONTROLLER 2014 .ndo_poll_controller = bcm_sysport_poll_controller, 2015 #endif 2016 .ndo_get_stats64 = bcm_sysport_get_stats64, 2017 }; 2018 2019 #define REV_FMT "v%2x.%02x" 2020 2021 static const struct bcm_sysport_hw_params bcm_sysport_params[] = { 2022 [SYSTEMPORT] = { 2023 .is_lite = false, 2024 .num_rx_desc_words = SP_NUM_HW_RX_DESC_WORDS, 2025 }, 2026 [SYSTEMPORT_LITE] = { 2027 .is_lite = true, 2028 .num_rx_desc_words = SP_LT_NUM_HW_RX_DESC_WORDS, 2029 }, 2030 }; 2031 2032 static const struct of_device_id bcm_sysport_of_match[] = { 2033 { .compatible = "brcm,systemportlite-v1.00", 2034 .data = &bcm_sysport_params[SYSTEMPORT_LITE] }, 2035 { .compatible = "brcm,systemport-v1.00", 2036 .data = &bcm_sysport_params[SYSTEMPORT] }, 2037 { .compatible = "brcm,systemport", 2038 .data = &bcm_sysport_params[SYSTEMPORT] }, 2039 { /* sentinel */ } 2040 }; 2041 MODULE_DEVICE_TABLE(of, bcm_sysport_of_match); 2042 2043 static int bcm_sysport_probe(struct platform_device *pdev) 2044 { 2045 const struct bcm_sysport_hw_params *params; 2046 const struct of_device_id *of_id = NULL; 2047 struct bcm_sysport_priv *priv; 2048 struct device_node *dn; 2049 struct net_device *dev; 2050 const void *macaddr; 2051 struct resource *r; 2052 u32 txq, rxq; 2053 int ret; 2054 2055 dn = pdev->dev.of_node; 2056 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2057 of_id = of_match_node(bcm_sysport_of_match, dn); 2058 if (!of_id || !of_id->data) 2059 return -EINVAL; 2060 2061 /* Fairly quickly we need to know the type of adapter we have */ 2062 params = of_id->data; 2063 2064 /* Read the Transmit/Receive Queue properties */ 2065 if (of_property_read_u32(dn, "systemport,num-txq", &txq)) 2066 txq = TDMA_NUM_RINGS; 2067 if (of_property_read_u32(dn, "systemport,num-rxq", &rxq)) 2068 rxq = 1; 2069 2070 /* Sanity check the number of transmit queues */ 2071 if (!txq || txq > TDMA_NUM_RINGS) 2072 return -EINVAL; 2073 2074 dev = alloc_etherdev_mqs(sizeof(*priv), txq, rxq); 2075 if (!dev) 2076 return -ENOMEM; 2077 2078 /* Initialize private members */ 2079 priv = netdev_priv(dev); 2080 2081 /* Allocate number of TX rings */ 2082 priv->tx_rings = devm_kcalloc(&pdev->dev, txq, 2083 sizeof(struct bcm_sysport_tx_ring), 2084 GFP_KERNEL); 2085 if (!priv->tx_rings) 2086 return -ENOMEM; 2087 2088 priv->is_lite = params->is_lite; 2089 priv->num_rx_desc_words = params->num_rx_desc_words; 2090 2091 priv->irq0 = platform_get_irq(pdev, 0); 2092 if (!priv->is_lite) { 2093 priv->irq1 = platform_get_irq(pdev, 1); 2094 priv->wol_irq = platform_get_irq(pdev, 2); 2095 } else { 2096 priv->wol_irq = platform_get_irq(pdev, 1); 2097 } 2098 if (priv->irq0 <= 0 || (priv->irq1 <= 0 && !priv->is_lite)) { 2099 dev_err(&pdev->dev, "invalid interrupts\n"); 2100 ret = -EINVAL; 2101 goto err_free_netdev; 2102 } 2103 2104 priv->base = devm_ioremap_resource(&pdev->dev, r); 2105 if (IS_ERR(priv->base)) { 2106 ret = PTR_ERR(priv->base); 2107 goto err_free_netdev; 2108 } 2109 2110 priv->netdev = dev; 2111 priv->pdev = pdev; 2112 2113 priv->phy_interface = of_get_phy_mode(dn); 2114 /* Default to GMII interface mode */ 2115 if (priv->phy_interface < 0) 2116 priv->phy_interface = PHY_INTERFACE_MODE_GMII; 2117 2118 /* In the case of a fixed PHY, the DT node associated 2119 * to the PHY is the Ethernet MAC DT node. 2120 */ 2121 if (of_phy_is_fixed_link(dn)) { 2122 ret = of_phy_register_fixed_link(dn); 2123 if (ret) { 2124 dev_err(&pdev->dev, "failed to register fixed PHY\n"); 2125 goto err_free_netdev; 2126 } 2127 2128 priv->phy_dn = dn; 2129 } 2130 2131 /* Initialize netdevice members */ 2132 macaddr = of_get_mac_address(dn); 2133 if (!macaddr || !is_valid_ether_addr(macaddr)) { 2134 dev_warn(&pdev->dev, "using random Ethernet MAC\n"); 2135 eth_hw_addr_random(dev); 2136 } else { 2137 ether_addr_copy(dev->dev_addr, macaddr); 2138 } 2139 2140 SET_NETDEV_DEV(dev, &pdev->dev); 2141 dev_set_drvdata(&pdev->dev, dev); 2142 dev->ethtool_ops = &bcm_sysport_ethtool_ops; 2143 dev->netdev_ops = &bcm_sysport_netdev_ops; 2144 netif_napi_add(dev, &priv->napi, bcm_sysport_poll, 64); 2145 2146 /* HW supported features, none enabled by default */ 2147 dev->hw_features |= NETIF_F_RXCSUM | NETIF_F_HIGHDMA | 2148 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 2149 2150 /* Request the WOL interrupt and advertise suspend if available */ 2151 priv->wol_irq_disabled = 1; 2152 ret = devm_request_irq(&pdev->dev, priv->wol_irq, 2153 bcm_sysport_wol_isr, 0, dev->name, priv); 2154 if (!ret) 2155 device_set_wakeup_capable(&pdev->dev, 1); 2156 2157 /* Set the needed headroom once and for all */ 2158 BUILD_BUG_ON(sizeof(struct bcm_tsb) != 8); 2159 dev->needed_headroom += sizeof(struct bcm_tsb); 2160 2161 /* libphy will adjust the link state accordingly */ 2162 netif_carrier_off(dev); 2163 2164 u64_stats_init(&priv->syncp); 2165 2166 ret = register_netdev(dev); 2167 if (ret) { 2168 dev_err(&pdev->dev, "failed to register net_device\n"); 2169 goto err_deregister_fixed_link; 2170 } 2171 2172 priv->rev = topctrl_readl(priv, REV_CNTL) & REV_MASK; 2173 dev_info(&pdev->dev, 2174 "Broadcom SYSTEMPORT%s" REV_FMT 2175 " at 0x%p (irqs: %d, %d, TXQs: %d, RXQs: %d)\n", 2176 priv->is_lite ? " Lite" : "", 2177 (priv->rev >> 8) & 0xff, priv->rev & 0xff, 2178 priv->base, priv->irq0, priv->irq1, txq, rxq); 2179 2180 return 0; 2181 2182 err_deregister_fixed_link: 2183 if (of_phy_is_fixed_link(dn)) 2184 of_phy_deregister_fixed_link(dn); 2185 err_free_netdev: 2186 free_netdev(dev); 2187 return ret; 2188 } 2189 2190 static int bcm_sysport_remove(struct platform_device *pdev) 2191 { 2192 struct net_device *dev = dev_get_drvdata(&pdev->dev); 2193 struct device_node *dn = pdev->dev.of_node; 2194 2195 /* Not much to do, ndo_close has been called 2196 * and we use managed allocations 2197 */ 2198 unregister_netdev(dev); 2199 if (of_phy_is_fixed_link(dn)) 2200 of_phy_deregister_fixed_link(dn); 2201 free_netdev(dev); 2202 dev_set_drvdata(&pdev->dev, NULL); 2203 2204 return 0; 2205 } 2206 2207 #ifdef CONFIG_PM_SLEEP 2208 static int bcm_sysport_suspend_to_wol(struct bcm_sysport_priv *priv) 2209 { 2210 struct net_device *ndev = priv->netdev; 2211 unsigned int timeout = 1000; 2212 u32 reg; 2213 2214 /* Password has already been programmed */ 2215 reg = umac_readl(priv, UMAC_MPD_CTRL); 2216 reg |= MPD_EN; 2217 reg &= ~PSW_EN; 2218 if (priv->wolopts & WAKE_MAGICSECURE) 2219 reg |= PSW_EN; 2220 umac_writel(priv, reg, UMAC_MPD_CTRL); 2221 2222 /* Make sure RBUF entered WoL mode as result */ 2223 do { 2224 reg = rbuf_readl(priv, RBUF_STATUS); 2225 if (reg & RBUF_WOL_MODE) 2226 break; 2227 2228 udelay(10); 2229 } while (timeout-- > 0); 2230 2231 /* Do not leave the UniMAC RBUF matching only MPD packets */ 2232 if (!timeout) { 2233 reg = umac_readl(priv, UMAC_MPD_CTRL); 2234 reg &= ~MPD_EN; 2235 umac_writel(priv, reg, UMAC_MPD_CTRL); 2236 netif_err(priv, wol, ndev, "failed to enter WOL mode\n"); 2237 return -ETIMEDOUT; 2238 } 2239 2240 /* UniMAC receive needs to be turned on */ 2241 umac_enable_set(priv, CMD_RX_EN, 1); 2242 2243 /* Enable the interrupt wake-up source */ 2244 intrl2_0_mask_clear(priv, INTRL2_0_MPD); 2245 2246 netif_dbg(priv, wol, ndev, "entered WOL mode\n"); 2247 2248 return 0; 2249 } 2250 2251 static int bcm_sysport_suspend(struct device *d) 2252 { 2253 struct net_device *dev = dev_get_drvdata(d); 2254 struct bcm_sysport_priv *priv = netdev_priv(dev); 2255 unsigned int i; 2256 int ret = 0; 2257 u32 reg; 2258 2259 if (!netif_running(dev)) 2260 return 0; 2261 2262 bcm_sysport_netif_stop(dev); 2263 2264 phy_suspend(dev->phydev); 2265 2266 netif_device_detach(dev); 2267 2268 /* Disable UniMAC RX */ 2269 umac_enable_set(priv, CMD_RX_EN, 0); 2270 2271 ret = rdma_enable_set(priv, 0); 2272 if (ret) { 2273 netdev_err(dev, "RDMA timeout!\n"); 2274 return ret; 2275 } 2276 2277 /* Disable RXCHK if enabled */ 2278 if (priv->rx_chk_en) { 2279 reg = rxchk_readl(priv, RXCHK_CONTROL); 2280 reg &= ~RXCHK_EN; 2281 rxchk_writel(priv, reg, RXCHK_CONTROL); 2282 } 2283 2284 /* Flush RX pipe */ 2285 if (!priv->wolopts) 2286 topctrl_writel(priv, RX_FLUSH, RX_FLUSH_CNTL); 2287 2288 ret = tdma_enable_set(priv, 0); 2289 if (ret) { 2290 netdev_err(dev, "TDMA timeout!\n"); 2291 return ret; 2292 } 2293 2294 /* Wait for a packet boundary */ 2295 usleep_range(2000, 3000); 2296 2297 umac_enable_set(priv, CMD_TX_EN, 0); 2298 2299 topctrl_writel(priv, TX_FLUSH, TX_FLUSH_CNTL); 2300 2301 /* Free RX/TX rings SW structures */ 2302 for (i = 0; i < dev->num_tx_queues; i++) 2303 bcm_sysport_fini_tx_ring(priv, i); 2304 bcm_sysport_fini_rx_ring(priv); 2305 2306 /* Get prepared for Wake-on-LAN */ 2307 if (device_may_wakeup(d) && priv->wolopts) 2308 ret = bcm_sysport_suspend_to_wol(priv); 2309 2310 return ret; 2311 } 2312 2313 static int bcm_sysport_resume(struct device *d) 2314 { 2315 struct net_device *dev = dev_get_drvdata(d); 2316 struct bcm_sysport_priv *priv = netdev_priv(dev); 2317 unsigned int i; 2318 u32 reg; 2319 int ret; 2320 2321 if (!netif_running(dev)) 2322 return 0; 2323 2324 umac_reset(priv); 2325 2326 /* We may have been suspended and never received a WOL event that 2327 * would turn off MPD detection, take care of that now 2328 */ 2329 bcm_sysport_resume_from_wol(priv); 2330 2331 /* Initialize both hardware and software ring */ 2332 for (i = 0; i < dev->num_tx_queues; i++) { 2333 ret = bcm_sysport_init_tx_ring(priv, i); 2334 if (ret) { 2335 netdev_err(dev, "failed to initialize TX ring %d\n", 2336 i); 2337 goto out_free_tx_rings; 2338 } 2339 } 2340 2341 /* Initialize linked-list */ 2342 tdma_writel(priv, TDMA_LL_RAM_INIT_BUSY, TDMA_STATUS); 2343 2344 /* Initialize RX ring */ 2345 ret = bcm_sysport_init_rx_ring(priv); 2346 if (ret) { 2347 netdev_err(dev, "failed to initialize RX ring\n"); 2348 goto out_free_rx_ring; 2349 } 2350 2351 netif_device_attach(dev); 2352 2353 /* RX pipe enable */ 2354 topctrl_writel(priv, 0, RX_FLUSH_CNTL); 2355 2356 ret = rdma_enable_set(priv, 1); 2357 if (ret) { 2358 netdev_err(dev, "failed to enable RDMA\n"); 2359 goto out_free_rx_ring; 2360 } 2361 2362 /* Enable rxhck */ 2363 if (priv->rx_chk_en) { 2364 reg = rxchk_readl(priv, RXCHK_CONTROL); 2365 reg |= RXCHK_EN; 2366 rxchk_writel(priv, reg, RXCHK_CONTROL); 2367 } 2368 2369 rbuf_init(priv); 2370 2371 /* Set maximum frame length */ 2372 if (!priv->is_lite) 2373 umac_writel(priv, UMAC_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN); 2374 else 2375 gib_set_pad_extension(priv); 2376 2377 /* Set MAC address */ 2378 umac_set_hw_addr(priv, dev->dev_addr); 2379 2380 umac_enable_set(priv, CMD_RX_EN, 1); 2381 2382 /* TX pipe enable */ 2383 topctrl_writel(priv, 0, TX_FLUSH_CNTL); 2384 2385 umac_enable_set(priv, CMD_TX_EN, 1); 2386 2387 ret = tdma_enable_set(priv, 1); 2388 if (ret) { 2389 netdev_err(dev, "TDMA timeout!\n"); 2390 goto out_free_rx_ring; 2391 } 2392 2393 phy_resume(dev->phydev); 2394 2395 bcm_sysport_netif_start(dev); 2396 2397 return 0; 2398 2399 out_free_rx_ring: 2400 bcm_sysport_fini_rx_ring(priv); 2401 out_free_tx_rings: 2402 for (i = 0; i < dev->num_tx_queues; i++) 2403 bcm_sysport_fini_tx_ring(priv, i); 2404 return ret; 2405 } 2406 #endif 2407 2408 static SIMPLE_DEV_PM_OPS(bcm_sysport_pm_ops, 2409 bcm_sysport_suspend, bcm_sysport_resume); 2410 2411 static struct platform_driver bcm_sysport_driver = { 2412 .probe = bcm_sysport_probe, 2413 .remove = bcm_sysport_remove, 2414 .driver = { 2415 .name = "brcm-systemport", 2416 .of_match_table = bcm_sysport_of_match, 2417 .pm = &bcm_sysport_pm_ops, 2418 }, 2419 }; 2420 module_platform_driver(bcm_sysport_driver); 2421 2422 MODULE_AUTHOR("Broadcom Corporation"); 2423 MODULE_DESCRIPTION("Broadcom System Port Ethernet MAC driver"); 2424 MODULE_ALIAS("platform:brcm-systemport"); 2425 MODULE_LICENSE("GPL"); 2426