1 /* 2 * Broadcom BCM7xxx System Port Ethernet MAC driver 3 * 4 * Copyright (C) 2014 Broadcom Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 12 13 #include <linux/init.h> 14 #include <linux/interrupt.h> 15 #include <linux/module.h> 16 #include <linux/kernel.h> 17 #include <linux/netdevice.h> 18 #include <linux/etherdevice.h> 19 #include <linux/platform_device.h> 20 #include <linux/of.h> 21 #include <linux/of_net.h> 22 #include <linux/of_mdio.h> 23 #include <linux/phy.h> 24 #include <linux/phy_fixed.h> 25 #include <net/ip.h> 26 #include <net/ipv6.h> 27 28 #include "bcmsysport.h" 29 30 /* I/O accessors register helpers */ 31 #define BCM_SYSPORT_IO_MACRO(name, offset) \ 32 static inline u32 name##_readl(struct bcm_sysport_priv *priv, u32 off) \ 33 { \ 34 u32 reg = __raw_readl(priv->base + offset + off); \ 35 return reg; \ 36 } \ 37 static inline void name##_writel(struct bcm_sysport_priv *priv, \ 38 u32 val, u32 off) \ 39 { \ 40 __raw_writel(val, priv->base + offset + off); \ 41 } \ 42 43 BCM_SYSPORT_IO_MACRO(intrl2_0, SYS_PORT_INTRL2_0_OFFSET); 44 BCM_SYSPORT_IO_MACRO(intrl2_1, SYS_PORT_INTRL2_1_OFFSET); 45 BCM_SYSPORT_IO_MACRO(umac, SYS_PORT_UMAC_OFFSET); 46 BCM_SYSPORT_IO_MACRO(tdma, SYS_PORT_TDMA_OFFSET); 47 BCM_SYSPORT_IO_MACRO(rdma, SYS_PORT_RDMA_OFFSET); 48 BCM_SYSPORT_IO_MACRO(rxchk, SYS_PORT_RXCHK_OFFSET); 49 BCM_SYSPORT_IO_MACRO(txchk, SYS_PORT_TXCHK_OFFSET); 50 BCM_SYSPORT_IO_MACRO(rbuf, SYS_PORT_RBUF_OFFSET); 51 BCM_SYSPORT_IO_MACRO(tbuf, SYS_PORT_TBUF_OFFSET); 52 BCM_SYSPORT_IO_MACRO(topctrl, SYS_PORT_TOPCTRL_OFFSET); 53 54 /* L2-interrupt masking/unmasking helpers, does automatic saving of the applied 55 * mask in a software copy to avoid CPU_MASK_STATUS reads in hot-paths. 56 */ 57 #define BCM_SYSPORT_INTR_L2(which) \ 58 static inline void intrl2_##which##_mask_clear(struct bcm_sysport_priv *priv, \ 59 u32 mask) \ 60 { \ 61 intrl2_##which##_writel(priv, mask, INTRL2_CPU_MASK_CLEAR); \ 62 priv->irq##which##_mask &= ~(mask); \ 63 } \ 64 static inline void intrl2_##which##_mask_set(struct bcm_sysport_priv *priv, \ 65 u32 mask) \ 66 { \ 67 intrl2_## which##_writel(priv, mask, INTRL2_CPU_MASK_SET); \ 68 priv->irq##which##_mask |= (mask); \ 69 } \ 70 71 BCM_SYSPORT_INTR_L2(0) 72 BCM_SYSPORT_INTR_L2(1) 73 74 /* Register accesses to GISB/RBUS registers are expensive (few hundred 75 * nanoseconds), so keep the check for 64-bits explicit here to save 76 * one register write per-packet on 32-bits platforms. 77 */ 78 static inline void dma_desc_set_addr(struct bcm_sysport_priv *priv, 79 void __iomem *d, 80 dma_addr_t addr) 81 { 82 #ifdef CONFIG_PHYS_ADDR_T_64BIT 83 __raw_writel(upper_32_bits(addr) & DESC_ADDR_HI_MASK, 84 d + DESC_ADDR_HI_STATUS_LEN); 85 #endif 86 __raw_writel(lower_32_bits(addr), d + DESC_ADDR_LO); 87 } 88 89 static inline void tdma_port_write_desc_addr(struct bcm_sysport_priv *priv, 90 struct dma_desc *desc, 91 unsigned int port) 92 { 93 /* Ports are latched, so write upper address first */ 94 tdma_writel(priv, desc->addr_status_len, TDMA_WRITE_PORT_HI(port)); 95 tdma_writel(priv, desc->addr_lo, TDMA_WRITE_PORT_LO(port)); 96 } 97 98 /* Ethtool operations */ 99 static int bcm_sysport_set_settings(struct net_device *dev, 100 struct ethtool_cmd *cmd) 101 { 102 struct bcm_sysport_priv *priv = netdev_priv(dev); 103 104 if (!netif_running(dev)) 105 return -EINVAL; 106 107 return phy_ethtool_sset(priv->phydev, cmd); 108 } 109 110 static int bcm_sysport_get_settings(struct net_device *dev, 111 struct ethtool_cmd *cmd) 112 { 113 struct bcm_sysport_priv *priv = netdev_priv(dev); 114 115 if (!netif_running(dev)) 116 return -EINVAL; 117 118 return phy_ethtool_gset(priv->phydev, cmd); 119 } 120 121 static int bcm_sysport_set_rx_csum(struct net_device *dev, 122 netdev_features_t wanted) 123 { 124 struct bcm_sysport_priv *priv = netdev_priv(dev); 125 u32 reg; 126 127 priv->rx_chk_en = !!(wanted & NETIF_F_RXCSUM); 128 reg = rxchk_readl(priv, RXCHK_CONTROL); 129 if (priv->rx_chk_en) 130 reg |= RXCHK_EN; 131 else 132 reg &= ~RXCHK_EN; 133 134 /* If UniMAC forwards CRC, we need to skip over it to get 135 * a valid CHK bit to be set in the per-packet status word 136 */ 137 if (priv->rx_chk_en && priv->crc_fwd) 138 reg |= RXCHK_SKIP_FCS; 139 else 140 reg &= ~RXCHK_SKIP_FCS; 141 142 /* If Broadcom tags are enabled (e.g: using a switch), make 143 * sure we tell the RXCHK hardware to expect a 4-bytes Broadcom 144 * tag after the Ethernet MAC Source Address. 145 */ 146 if (netdev_uses_dsa(dev)) 147 reg |= RXCHK_BRCM_TAG_EN; 148 else 149 reg &= ~RXCHK_BRCM_TAG_EN; 150 151 rxchk_writel(priv, reg, RXCHK_CONTROL); 152 153 return 0; 154 } 155 156 static int bcm_sysport_set_tx_csum(struct net_device *dev, 157 netdev_features_t wanted) 158 { 159 struct bcm_sysport_priv *priv = netdev_priv(dev); 160 u32 reg; 161 162 /* Hardware transmit checksum requires us to enable the Transmit status 163 * block prepended to the packet contents 164 */ 165 priv->tsb_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)); 166 reg = tdma_readl(priv, TDMA_CONTROL); 167 if (priv->tsb_en) 168 reg |= TSB_EN; 169 else 170 reg &= ~TSB_EN; 171 tdma_writel(priv, reg, TDMA_CONTROL); 172 173 return 0; 174 } 175 176 static int bcm_sysport_set_features(struct net_device *dev, 177 netdev_features_t features) 178 { 179 netdev_features_t changed = features ^ dev->features; 180 netdev_features_t wanted = dev->wanted_features; 181 int ret = 0; 182 183 if (changed & NETIF_F_RXCSUM) 184 ret = bcm_sysport_set_rx_csum(dev, wanted); 185 if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)) 186 ret = bcm_sysport_set_tx_csum(dev, wanted); 187 188 return ret; 189 } 190 191 /* Hardware counters must be kept in sync because the order/offset 192 * is important here (order in structure declaration = order in hardware) 193 */ 194 static const struct bcm_sysport_stats bcm_sysport_gstrings_stats[] = { 195 /* general stats */ 196 STAT_NETDEV(rx_packets), 197 STAT_NETDEV(tx_packets), 198 STAT_NETDEV(rx_bytes), 199 STAT_NETDEV(tx_bytes), 200 STAT_NETDEV(rx_errors), 201 STAT_NETDEV(tx_errors), 202 STAT_NETDEV(rx_dropped), 203 STAT_NETDEV(tx_dropped), 204 STAT_NETDEV(multicast), 205 /* UniMAC RSV counters */ 206 STAT_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64), 207 STAT_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127), 208 STAT_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255), 209 STAT_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511), 210 STAT_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023), 211 STAT_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518), 212 STAT_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv), 213 STAT_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047), 214 STAT_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095), 215 STAT_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216), 216 STAT_MIB_RX("rx_pkts", mib.rx.pkt), 217 STAT_MIB_RX("rx_bytes", mib.rx.bytes), 218 STAT_MIB_RX("rx_multicast", mib.rx.mca), 219 STAT_MIB_RX("rx_broadcast", mib.rx.bca), 220 STAT_MIB_RX("rx_fcs", mib.rx.fcs), 221 STAT_MIB_RX("rx_control", mib.rx.cf), 222 STAT_MIB_RX("rx_pause", mib.rx.pf), 223 STAT_MIB_RX("rx_unknown", mib.rx.uo), 224 STAT_MIB_RX("rx_align", mib.rx.aln), 225 STAT_MIB_RX("rx_outrange", mib.rx.flr), 226 STAT_MIB_RX("rx_code", mib.rx.cde), 227 STAT_MIB_RX("rx_carrier", mib.rx.fcr), 228 STAT_MIB_RX("rx_oversize", mib.rx.ovr), 229 STAT_MIB_RX("rx_jabber", mib.rx.jbr), 230 STAT_MIB_RX("rx_mtu_err", mib.rx.mtue), 231 STAT_MIB_RX("rx_good_pkts", mib.rx.pok), 232 STAT_MIB_RX("rx_unicast", mib.rx.uc), 233 STAT_MIB_RX("rx_ppp", mib.rx.ppp), 234 STAT_MIB_RX("rx_crc", mib.rx.rcrc), 235 /* UniMAC TSV counters */ 236 STAT_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64), 237 STAT_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127), 238 STAT_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255), 239 STAT_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511), 240 STAT_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023), 241 STAT_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518), 242 STAT_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv), 243 STAT_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047), 244 STAT_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095), 245 STAT_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216), 246 STAT_MIB_TX("tx_pkts", mib.tx.pkts), 247 STAT_MIB_TX("tx_multicast", mib.tx.mca), 248 STAT_MIB_TX("tx_broadcast", mib.tx.bca), 249 STAT_MIB_TX("tx_pause", mib.tx.pf), 250 STAT_MIB_TX("tx_control", mib.tx.cf), 251 STAT_MIB_TX("tx_fcs_err", mib.tx.fcs), 252 STAT_MIB_TX("tx_oversize", mib.tx.ovr), 253 STAT_MIB_TX("tx_defer", mib.tx.drf), 254 STAT_MIB_TX("tx_excess_defer", mib.tx.edf), 255 STAT_MIB_TX("tx_single_col", mib.tx.scl), 256 STAT_MIB_TX("tx_multi_col", mib.tx.mcl), 257 STAT_MIB_TX("tx_late_col", mib.tx.lcl), 258 STAT_MIB_TX("tx_excess_col", mib.tx.ecl), 259 STAT_MIB_TX("tx_frags", mib.tx.frg), 260 STAT_MIB_TX("tx_total_col", mib.tx.ncl), 261 STAT_MIB_TX("tx_jabber", mib.tx.jbr), 262 STAT_MIB_TX("tx_bytes", mib.tx.bytes), 263 STAT_MIB_TX("tx_good_pkts", mib.tx.pok), 264 STAT_MIB_TX("tx_unicast", mib.tx.uc), 265 /* UniMAC RUNT counters */ 266 STAT_RUNT("rx_runt_pkts", mib.rx_runt_cnt), 267 STAT_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs), 268 STAT_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align), 269 STAT_RUNT("rx_runt_bytes", mib.rx_runt_bytes), 270 /* RXCHK misc statistics */ 271 STAT_RXCHK("rxchk_bad_csum", mib.rxchk_bad_csum, RXCHK_BAD_CSUM_CNTR), 272 STAT_RXCHK("rxchk_other_pkt_disc", mib.rxchk_other_pkt_disc, 273 RXCHK_OTHER_DISC_CNTR), 274 /* RBUF misc statistics */ 275 STAT_RBUF("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt, RBUF_OVFL_DISC_CNTR), 276 STAT_RBUF("rbuf_err_cnt", mib.rbuf_err_cnt, RBUF_ERR_PKT_CNTR), 277 STAT_MIB_SOFT("alloc_rx_buff_failed", mib.alloc_rx_buff_failed), 278 STAT_MIB_SOFT("rx_dma_failed", mib.rx_dma_failed), 279 STAT_MIB_SOFT("tx_dma_failed", mib.tx_dma_failed), 280 }; 281 282 #define BCM_SYSPORT_STATS_LEN ARRAY_SIZE(bcm_sysport_gstrings_stats) 283 284 static void bcm_sysport_get_drvinfo(struct net_device *dev, 285 struct ethtool_drvinfo *info) 286 { 287 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver)); 288 strlcpy(info->version, "0.1", sizeof(info->version)); 289 strlcpy(info->bus_info, "platform", sizeof(info->bus_info)); 290 info->n_stats = BCM_SYSPORT_STATS_LEN; 291 } 292 293 static u32 bcm_sysport_get_msglvl(struct net_device *dev) 294 { 295 struct bcm_sysport_priv *priv = netdev_priv(dev); 296 297 return priv->msg_enable; 298 } 299 300 static void bcm_sysport_set_msglvl(struct net_device *dev, u32 enable) 301 { 302 struct bcm_sysport_priv *priv = netdev_priv(dev); 303 304 priv->msg_enable = enable; 305 } 306 307 static int bcm_sysport_get_sset_count(struct net_device *dev, int string_set) 308 { 309 switch (string_set) { 310 case ETH_SS_STATS: 311 return BCM_SYSPORT_STATS_LEN; 312 default: 313 return -EOPNOTSUPP; 314 } 315 } 316 317 static void bcm_sysport_get_strings(struct net_device *dev, 318 u32 stringset, u8 *data) 319 { 320 int i; 321 322 switch (stringset) { 323 case ETH_SS_STATS: 324 for (i = 0; i < BCM_SYSPORT_STATS_LEN; i++) { 325 memcpy(data + i * ETH_GSTRING_LEN, 326 bcm_sysport_gstrings_stats[i].stat_string, 327 ETH_GSTRING_LEN); 328 } 329 break; 330 default: 331 break; 332 } 333 } 334 335 static void bcm_sysport_update_mib_counters(struct bcm_sysport_priv *priv) 336 { 337 int i, j = 0; 338 339 for (i = 0; i < BCM_SYSPORT_STATS_LEN; i++) { 340 const struct bcm_sysport_stats *s; 341 u8 offset = 0; 342 u32 val = 0; 343 char *p; 344 345 s = &bcm_sysport_gstrings_stats[i]; 346 switch (s->type) { 347 case BCM_SYSPORT_STAT_NETDEV: 348 case BCM_SYSPORT_STAT_SOFT: 349 continue; 350 case BCM_SYSPORT_STAT_MIB_RX: 351 case BCM_SYSPORT_STAT_MIB_TX: 352 case BCM_SYSPORT_STAT_RUNT: 353 if (s->type != BCM_SYSPORT_STAT_MIB_RX) 354 offset = UMAC_MIB_STAT_OFFSET; 355 val = umac_readl(priv, UMAC_MIB_START + j + offset); 356 break; 357 case BCM_SYSPORT_STAT_RXCHK: 358 val = rxchk_readl(priv, s->reg_offset); 359 if (val == ~0) 360 rxchk_writel(priv, 0, s->reg_offset); 361 break; 362 case BCM_SYSPORT_STAT_RBUF: 363 val = rbuf_readl(priv, s->reg_offset); 364 if (val == ~0) 365 rbuf_writel(priv, 0, s->reg_offset); 366 break; 367 } 368 369 j += s->stat_sizeof; 370 p = (char *)priv + s->stat_offset; 371 *(u32 *)p = val; 372 } 373 374 netif_dbg(priv, hw, priv->netdev, "updated MIB counters\n"); 375 } 376 377 static void bcm_sysport_get_stats(struct net_device *dev, 378 struct ethtool_stats *stats, u64 *data) 379 { 380 struct bcm_sysport_priv *priv = netdev_priv(dev); 381 int i; 382 383 if (netif_running(dev)) 384 bcm_sysport_update_mib_counters(priv); 385 386 for (i = 0; i < BCM_SYSPORT_STATS_LEN; i++) { 387 const struct bcm_sysport_stats *s; 388 char *p; 389 390 s = &bcm_sysport_gstrings_stats[i]; 391 if (s->type == BCM_SYSPORT_STAT_NETDEV) 392 p = (char *)&dev->stats; 393 else 394 p = (char *)priv; 395 p += s->stat_offset; 396 data[i] = *(u32 *)p; 397 } 398 } 399 400 static void bcm_sysport_get_wol(struct net_device *dev, 401 struct ethtool_wolinfo *wol) 402 { 403 struct bcm_sysport_priv *priv = netdev_priv(dev); 404 u32 reg; 405 406 wol->supported = WAKE_MAGIC | WAKE_MAGICSECURE; 407 wol->wolopts = priv->wolopts; 408 409 if (!(priv->wolopts & WAKE_MAGICSECURE)) 410 return; 411 412 /* Return the programmed SecureOn password */ 413 reg = umac_readl(priv, UMAC_PSW_MS); 414 put_unaligned_be16(reg, &wol->sopass[0]); 415 reg = umac_readl(priv, UMAC_PSW_LS); 416 put_unaligned_be32(reg, &wol->sopass[2]); 417 } 418 419 static int bcm_sysport_set_wol(struct net_device *dev, 420 struct ethtool_wolinfo *wol) 421 { 422 struct bcm_sysport_priv *priv = netdev_priv(dev); 423 struct device *kdev = &priv->pdev->dev; 424 u32 supported = WAKE_MAGIC | WAKE_MAGICSECURE; 425 426 if (!device_can_wakeup(kdev)) 427 return -ENOTSUPP; 428 429 if (wol->wolopts & ~supported) 430 return -EINVAL; 431 432 /* Program the SecureOn password */ 433 if (wol->wolopts & WAKE_MAGICSECURE) { 434 umac_writel(priv, get_unaligned_be16(&wol->sopass[0]), 435 UMAC_PSW_MS); 436 umac_writel(priv, get_unaligned_be32(&wol->sopass[2]), 437 UMAC_PSW_LS); 438 } 439 440 /* Flag the device and relevant IRQ as wakeup capable */ 441 if (wol->wolopts) { 442 device_set_wakeup_enable(kdev, 1); 443 if (priv->wol_irq_disabled) 444 enable_irq_wake(priv->wol_irq); 445 priv->wol_irq_disabled = 0; 446 } else { 447 device_set_wakeup_enable(kdev, 0); 448 /* Avoid unbalanced disable_irq_wake calls */ 449 if (!priv->wol_irq_disabled) 450 disable_irq_wake(priv->wol_irq); 451 priv->wol_irq_disabled = 1; 452 } 453 454 priv->wolopts = wol->wolopts; 455 456 return 0; 457 } 458 459 static int bcm_sysport_get_coalesce(struct net_device *dev, 460 struct ethtool_coalesce *ec) 461 { 462 struct bcm_sysport_priv *priv = netdev_priv(dev); 463 u32 reg; 464 465 reg = tdma_readl(priv, TDMA_DESC_RING_INTR_CONTROL(0)); 466 467 ec->tx_coalesce_usecs = (reg >> RING_TIMEOUT_SHIFT) * 8192 / 1000; 468 ec->tx_max_coalesced_frames = reg & RING_INTR_THRESH_MASK; 469 470 reg = rdma_readl(priv, RDMA_MBDONE_INTR); 471 472 ec->rx_coalesce_usecs = (reg >> RDMA_TIMEOUT_SHIFT) * 8192 / 1000; 473 ec->rx_max_coalesced_frames = reg & RDMA_INTR_THRESH_MASK; 474 475 return 0; 476 } 477 478 static int bcm_sysport_set_coalesce(struct net_device *dev, 479 struct ethtool_coalesce *ec) 480 { 481 struct bcm_sysport_priv *priv = netdev_priv(dev); 482 unsigned int i; 483 u32 reg; 484 485 /* Base system clock is 125Mhz, DMA timeout is this reference clock 486 * divided by 1024, which yield roughly 8.192 us, our maximum value has 487 * to fit in the RING_TIMEOUT_MASK (16 bits). 488 */ 489 if (ec->tx_max_coalesced_frames > RING_INTR_THRESH_MASK || 490 ec->tx_coalesce_usecs > (RING_TIMEOUT_MASK * 8) + 1 || 491 ec->rx_max_coalesced_frames > RDMA_INTR_THRESH_MASK || 492 ec->rx_coalesce_usecs > (RDMA_TIMEOUT_MASK * 8) + 1) 493 return -EINVAL; 494 495 if ((ec->tx_coalesce_usecs == 0 && ec->tx_max_coalesced_frames == 0) || 496 (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0)) 497 return -EINVAL; 498 499 for (i = 0; i < dev->num_tx_queues; i++) { 500 reg = tdma_readl(priv, TDMA_DESC_RING_INTR_CONTROL(i)); 501 reg &= ~(RING_INTR_THRESH_MASK | 502 RING_TIMEOUT_MASK << RING_TIMEOUT_SHIFT); 503 reg |= ec->tx_max_coalesced_frames; 504 reg |= DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000, 8192) << 505 RING_TIMEOUT_SHIFT; 506 tdma_writel(priv, reg, TDMA_DESC_RING_INTR_CONTROL(i)); 507 } 508 509 reg = rdma_readl(priv, RDMA_MBDONE_INTR); 510 reg &= ~(RDMA_INTR_THRESH_MASK | 511 RDMA_TIMEOUT_MASK << RDMA_TIMEOUT_SHIFT); 512 reg |= ec->rx_max_coalesced_frames; 513 reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192) << 514 RDMA_TIMEOUT_SHIFT; 515 rdma_writel(priv, reg, RDMA_MBDONE_INTR); 516 517 return 0; 518 } 519 520 static void bcm_sysport_free_cb(struct bcm_sysport_cb *cb) 521 { 522 dev_kfree_skb_any(cb->skb); 523 cb->skb = NULL; 524 dma_unmap_addr_set(cb, dma_addr, 0); 525 } 526 527 static struct sk_buff *bcm_sysport_rx_refill(struct bcm_sysport_priv *priv, 528 struct bcm_sysport_cb *cb) 529 { 530 struct device *kdev = &priv->pdev->dev; 531 struct net_device *ndev = priv->netdev; 532 struct sk_buff *skb, *rx_skb; 533 dma_addr_t mapping; 534 535 /* Allocate a new SKB for a new packet */ 536 skb = netdev_alloc_skb(priv->netdev, RX_BUF_LENGTH); 537 if (!skb) { 538 priv->mib.alloc_rx_buff_failed++; 539 netif_err(priv, rx_err, ndev, "SKB alloc failed\n"); 540 return NULL; 541 } 542 543 mapping = dma_map_single(kdev, skb->data, 544 RX_BUF_LENGTH, DMA_FROM_DEVICE); 545 if (dma_mapping_error(kdev, mapping)) { 546 priv->mib.rx_dma_failed++; 547 dev_kfree_skb_any(skb); 548 netif_err(priv, rx_err, ndev, "DMA mapping failure\n"); 549 return NULL; 550 } 551 552 /* Grab the current SKB on the ring */ 553 rx_skb = cb->skb; 554 if (likely(rx_skb)) 555 dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr), 556 RX_BUF_LENGTH, DMA_FROM_DEVICE); 557 558 /* Put the new SKB on the ring */ 559 cb->skb = skb; 560 dma_unmap_addr_set(cb, dma_addr, mapping); 561 dma_desc_set_addr(priv, cb->bd_addr, mapping); 562 563 netif_dbg(priv, rx_status, ndev, "RX refill\n"); 564 565 /* Return the current SKB to the caller */ 566 return rx_skb; 567 } 568 569 static int bcm_sysport_alloc_rx_bufs(struct bcm_sysport_priv *priv) 570 { 571 struct bcm_sysport_cb *cb; 572 struct sk_buff *skb; 573 unsigned int i; 574 575 for (i = 0; i < priv->num_rx_bds; i++) { 576 cb = &priv->rx_cbs[i]; 577 skb = bcm_sysport_rx_refill(priv, cb); 578 if (skb) 579 dev_kfree_skb(skb); 580 if (!cb->skb) 581 return -ENOMEM; 582 } 583 584 return 0; 585 } 586 587 /* Poll the hardware for up to budget packets to process */ 588 static unsigned int bcm_sysport_desc_rx(struct bcm_sysport_priv *priv, 589 unsigned int budget) 590 { 591 struct net_device *ndev = priv->netdev; 592 unsigned int processed = 0, to_process; 593 struct bcm_sysport_cb *cb; 594 struct sk_buff *skb; 595 unsigned int p_index; 596 u16 len, status; 597 struct bcm_rsb *rsb; 598 599 /* Determine how much we should process since last call */ 600 p_index = rdma_readl(priv, RDMA_PROD_INDEX); 601 p_index &= RDMA_PROD_INDEX_MASK; 602 603 if (p_index < priv->rx_c_index) 604 to_process = (RDMA_CONS_INDEX_MASK + 1) - 605 priv->rx_c_index + p_index; 606 else 607 to_process = p_index - priv->rx_c_index; 608 609 netif_dbg(priv, rx_status, ndev, 610 "p_index=%d rx_c_index=%d to_process=%d\n", 611 p_index, priv->rx_c_index, to_process); 612 613 while ((processed < to_process) && (processed < budget)) { 614 cb = &priv->rx_cbs[priv->rx_read_ptr]; 615 skb = bcm_sysport_rx_refill(priv, cb); 616 617 618 /* We do not have a backing SKB, so we do not a corresponding 619 * DMA mapping for this incoming packet since 620 * bcm_sysport_rx_refill always either has both skb and mapping 621 * or none. 622 */ 623 if (unlikely(!skb)) { 624 netif_err(priv, rx_err, ndev, "out of memory!\n"); 625 ndev->stats.rx_dropped++; 626 ndev->stats.rx_errors++; 627 goto next; 628 } 629 630 /* Extract the Receive Status Block prepended */ 631 rsb = (struct bcm_rsb *)skb->data; 632 len = (rsb->rx_status_len >> DESC_LEN_SHIFT) & DESC_LEN_MASK; 633 status = (rsb->rx_status_len >> DESC_STATUS_SHIFT) & 634 DESC_STATUS_MASK; 635 636 netif_dbg(priv, rx_status, ndev, 637 "p=%d, c=%d, rd_ptr=%d, len=%d, flag=0x%04x\n", 638 p_index, priv->rx_c_index, priv->rx_read_ptr, 639 len, status); 640 641 if (unlikely(len > RX_BUF_LENGTH)) { 642 netif_err(priv, rx_status, ndev, "oversized packet\n"); 643 ndev->stats.rx_length_errors++; 644 ndev->stats.rx_errors++; 645 dev_kfree_skb_any(skb); 646 goto next; 647 } 648 649 if (unlikely(!(status & DESC_EOP) || !(status & DESC_SOP))) { 650 netif_err(priv, rx_status, ndev, "fragmented packet!\n"); 651 ndev->stats.rx_dropped++; 652 ndev->stats.rx_errors++; 653 dev_kfree_skb_any(skb); 654 goto next; 655 } 656 657 if (unlikely(status & (RX_STATUS_ERR | RX_STATUS_OVFLOW))) { 658 netif_err(priv, rx_err, ndev, "error packet\n"); 659 if (status & RX_STATUS_OVFLOW) 660 ndev->stats.rx_over_errors++; 661 ndev->stats.rx_dropped++; 662 ndev->stats.rx_errors++; 663 dev_kfree_skb_any(skb); 664 goto next; 665 } 666 667 skb_put(skb, len); 668 669 /* Hardware validated our checksum */ 670 if (likely(status & DESC_L4_CSUM)) 671 skb->ip_summed = CHECKSUM_UNNECESSARY; 672 673 /* Hardware pre-pends packets with 2bytes before Ethernet 674 * header plus we have the Receive Status Block, strip off all 675 * of this from the SKB. 676 */ 677 skb_pull(skb, sizeof(*rsb) + 2); 678 len -= (sizeof(*rsb) + 2); 679 680 /* UniMAC may forward CRC */ 681 if (priv->crc_fwd) { 682 skb_trim(skb, len - ETH_FCS_LEN); 683 len -= ETH_FCS_LEN; 684 } 685 686 skb->protocol = eth_type_trans(skb, ndev); 687 ndev->stats.rx_packets++; 688 ndev->stats.rx_bytes += len; 689 690 napi_gro_receive(&priv->napi, skb); 691 next: 692 processed++; 693 priv->rx_read_ptr++; 694 695 if (priv->rx_read_ptr == priv->num_rx_bds) 696 priv->rx_read_ptr = 0; 697 } 698 699 return processed; 700 } 701 702 static void bcm_sysport_tx_reclaim_one(struct bcm_sysport_priv *priv, 703 struct bcm_sysport_cb *cb, 704 unsigned int *bytes_compl, 705 unsigned int *pkts_compl) 706 { 707 struct device *kdev = &priv->pdev->dev; 708 struct net_device *ndev = priv->netdev; 709 710 if (cb->skb) { 711 ndev->stats.tx_bytes += cb->skb->len; 712 *bytes_compl += cb->skb->len; 713 dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr), 714 dma_unmap_len(cb, dma_len), 715 DMA_TO_DEVICE); 716 ndev->stats.tx_packets++; 717 (*pkts_compl)++; 718 bcm_sysport_free_cb(cb); 719 /* SKB fragment */ 720 } else if (dma_unmap_addr(cb, dma_addr)) { 721 ndev->stats.tx_bytes += dma_unmap_len(cb, dma_len); 722 dma_unmap_page(kdev, dma_unmap_addr(cb, dma_addr), 723 dma_unmap_len(cb, dma_len), DMA_TO_DEVICE); 724 dma_unmap_addr_set(cb, dma_addr, 0); 725 } 726 } 727 728 /* Reclaim queued SKBs for transmission completion, lockless version */ 729 static unsigned int __bcm_sysport_tx_reclaim(struct bcm_sysport_priv *priv, 730 struct bcm_sysport_tx_ring *ring) 731 { 732 struct net_device *ndev = priv->netdev; 733 unsigned int c_index, last_c_index, last_tx_cn, num_tx_cbs; 734 unsigned int pkts_compl = 0, bytes_compl = 0; 735 struct bcm_sysport_cb *cb; 736 struct netdev_queue *txq; 737 u32 hw_ind; 738 739 txq = netdev_get_tx_queue(ndev, ring->index); 740 741 /* Compute how many descriptors have been processed since last call */ 742 hw_ind = tdma_readl(priv, TDMA_DESC_RING_PROD_CONS_INDEX(ring->index)); 743 c_index = (hw_ind >> RING_CONS_INDEX_SHIFT) & RING_CONS_INDEX_MASK; 744 ring->p_index = (hw_ind & RING_PROD_INDEX_MASK); 745 746 last_c_index = ring->c_index; 747 num_tx_cbs = ring->size; 748 749 c_index &= (num_tx_cbs - 1); 750 751 if (c_index >= last_c_index) 752 last_tx_cn = c_index - last_c_index; 753 else 754 last_tx_cn = num_tx_cbs - last_c_index + c_index; 755 756 netif_dbg(priv, tx_done, ndev, 757 "ring=%d c_index=%d last_tx_cn=%d last_c_index=%d\n", 758 ring->index, c_index, last_tx_cn, last_c_index); 759 760 while (last_tx_cn-- > 0) { 761 cb = ring->cbs + last_c_index; 762 bcm_sysport_tx_reclaim_one(priv, cb, &bytes_compl, &pkts_compl); 763 764 ring->desc_count++; 765 last_c_index++; 766 last_c_index &= (num_tx_cbs - 1); 767 } 768 769 ring->c_index = c_index; 770 771 if (netif_tx_queue_stopped(txq) && pkts_compl) 772 netif_tx_wake_queue(txq); 773 774 netif_dbg(priv, tx_done, ndev, 775 "ring=%d c_index=%d pkts_compl=%d, bytes_compl=%d\n", 776 ring->index, ring->c_index, pkts_compl, bytes_compl); 777 778 return pkts_compl; 779 } 780 781 /* Locked version of the per-ring TX reclaim routine */ 782 static unsigned int bcm_sysport_tx_reclaim(struct bcm_sysport_priv *priv, 783 struct bcm_sysport_tx_ring *ring) 784 { 785 unsigned int released; 786 unsigned long flags; 787 788 spin_lock_irqsave(&ring->lock, flags); 789 released = __bcm_sysport_tx_reclaim(priv, ring); 790 spin_unlock_irqrestore(&ring->lock, flags); 791 792 return released; 793 } 794 795 static int bcm_sysport_tx_poll(struct napi_struct *napi, int budget) 796 { 797 struct bcm_sysport_tx_ring *ring = 798 container_of(napi, struct bcm_sysport_tx_ring, napi); 799 unsigned int work_done = 0; 800 801 work_done = bcm_sysport_tx_reclaim(ring->priv, ring); 802 803 if (work_done == 0) { 804 napi_complete(napi); 805 /* re-enable TX interrupt */ 806 intrl2_1_mask_clear(ring->priv, BIT(ring->index)); 807 808 return 0; 809 } 810 811 return budget; 812 } 813 814 static void bcm_sysport_tx_reclaim_all(struct bcm_sysport_priv *priv) 815 { 816 unsigned int q; 817 818 for (q = 0; q < priv->netdev->num_tx_queues; q++) 819 bcm_sysport_tx_reclaim(priv, &priv->tx_rings[q]); 820 } 821 822 static int bcm_sysport_poll(struct napi_struct *napi, int budget) 823 { 824 struct bcm_sysport_priv *priv = 825 container_of(napi, struct bcm_sysport_priv, napi); 826 unsigned int work_done = 0; 827 828 work_done = bcm_sysport_desc_rx(priv, budget); 829 830 priv->rx_c_index += work_done; 831 priv->rx_c_index &= RDMA_CONS_INDEX_MASK; 832 rdma_writel(priv, priv->rx_c_index, RDMA_CONS_INDEX); 833 834 if (work_done < budget) { 835 napi_complete(napi); 836 /* re-enable RX interrupts */ 837 intrl2_0_mask_clear(priv, INTRL2_0_RDMA_MBDONE); 838 } 839 840 return work_done; 841 } 842 843 static void bcm_sysport_resume_from_wol(struct bcm_sysport_priv *priv) 844 { 845 u32 reg; 846 847 /* Stop monitoring MPD interrupt */ 848 intrl2_0_mask_set(priv, INTRL2_0_MPD); 849 850 /* Clear the MagicPacket detection logic */ 851 reg = umac_readl(priv, UMAC_MPD_CTRL); 852 reg &= ~MPD_EN; 853 umac_writel(priv, reg, UMAC_MPD_CTRL); 854 855 netif_dbg(priv, wol, priv->netdev, "resumed from WOL\n"); 856 } 857 858 /* RX and misc interrupt routine */ 859 static irqreturn_t bcm_sysport_rx_isr(int irq, void *dev_id) 860 { 861 struct net_device *dev = dev_id; 862 struct bcm_sysport_priv *priv = netdev_priv(dev); 863 864 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) & 865 ~intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS); 866 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR); 867 868 if (unlikely(priv->irq0_stat == 0)) { 869 netdev_warn(priv->netdev, "spurious RX interrupt\n"); 870 return IRQ_NONE; 871 } 872 873 if (priv->irq0_stat & INTRL2_0_RDMA_MBDONE) { 874 if (likely(napi_schedule_prep(&priv->napi))) { 875 /* disable RX interrupts */ 876 intrl2_0_mask_set(priv, INTRL2_0_RDMA_MBDONE); 877 __napi_schedule(&priv->napi); 878 } 879 } 880 881 /* TX ring is full, perform a full reclaim since we do not know 882 * which one would trigger this interrupt 883 */ 884 if (priv->irq0_stat & INTRL2_0_TX_RING_FULL) 885 bcm_sysport_tx_reclaim_all(priv); 886 887 if (priv->irq0_stat & INTRL2_0_MPD) { 888 netdev_info(priv->netdev, "Wake-on-LAN interrupt!\n"); 889 bcm_sysport_resume_from_wol(priv); 890 } 891 892 return IRQ_HANDLED; 893 } 894 895 /* TX interrupt service routine */ 896 static irqreturn_t bcm_sysport_tx_isr(int irq, void *dev_id) 897 { 898 struct net_device *dev = dev_id; 899 struct bcm_sysport_priv *priv = netdev_priv(dev); 900 struct bcm_sysport_tx_ring *txr; 901 unsigned int ring; 902 903 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) & 904 ~intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS); 905 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 906 907 if (unlikely(priv->irq1_stat == 0)) { 908 netdev_warn(priv->netdev, "spurious TX interrupt\n"); 909 return IRQ_NONE; 910 } 911 912 for (ring = 0; ring < dev->num_tx_queues; ring++) { 913 if (!(priv->irq1_stat & BIT(ring))) 914 continue; 915 916 txr = &priv->tx_rings[ring]; 917 918 if (likely(napi_schedule_prep(&txr->napi))) { 919 intrl2_1_mask_set(priv, BIT(ring)); 920 __napi_schedule(&txr->napi); 921 } 922 } 923 924 return IRQ_HANDLED; 925 } 926 927 static irqreturn_t bcm_sysport_wol_isr(int irq, void *dev_id) 928 { 929 struct bcm_sysport_priv *priv = dev_id; 930 931 pm_wakeup_event(&priv->pdev->dev, 0); 932 933 return IRQ_HANDLED; 934 } 935 936 static struct sk_buff *bcm_sysport_insert_tsb(struct sk_buff *skb, 937 struct net_device *dev) 938 { 939 struct sk_buff *nskb; 940 struct bcm_tsb *tsb; 941 u32 csum_info; 942 u8 ip_proto; 943 u16 csum_start; 944 u16 ip_ver; 945 946 /* Re-allocate SKB if needed */ 947 if (unlikely(skb_headroom(skb) < sizeof(*tsb))) { 948 nskb = skb_realloc_headroom(skb, sizeof(*tsb)); 949 dev_kfree_skb(skb); 950 if (!nskb) { 951 dev->stats.tx_errors++; 952 dev->stats.tx_dropped++; 953 return NULL; 954 } 955 skb = nskb; 956 } 957 958 tsb = (struct bcm_tsb *)skb_push(skb, sizeof(*tsb)); 959 /* Zero-out TSB by default */ 960 memset(tsb, 0, sizeof(*tsb)); 961 962 if (skb->ip_summed == CHECKSUM_PARTIAL) { 963 ip_ver = htons(skb->protocol); 964 switch (ip_ver) { 965 case ETH_P_IP: 966 ip_proto = ip_hdr(skb)->protocol; 967 break; 968 case ETH_P_IPV6: 969 ip_proto = ipv6_hdr(skb)->nexthdr; 970 break; 971 default: 972 return skb; 973 } 974 975 /* Get the checksum offset and the L4 (transport) offset */ 976 csum_start = skb_checksum_start_offset(skb) - sizeof(*tsb); 977 csum_info = (csum_start + skb->csum_offset) & L4_CSUM_PTR_MASK; 978 csum_info |= (csum_start << L4_PTR_SHIFT); 979 980 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) { 981 csum_info |= L4_LENGTH_VALID; 982 if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP) 983 csum_info |= L4_UDP; 984 } else { 985 csum_info = 0; 986 } 987 988 tsb->l4_ptr_dest_map = csum_info; 989 } 990 991 return skb; 992 } 993 994 static netdev_tx_t bcm_sysport_xmit(struct sk_buff *skb, 995 struct net_device *dev) 996 { 997 struct bcm_sysport_priv *priv = netdev_priv(dev); 998 struct device *kdev = &priv->pdev->dev; 999 struct bcm_sysport_tx_ring *ring; 1000 struct bcm_sysport_cb *cb; 1001 struct netdev_queue *txq; 1002 struct dma_desc *desc; 1003 unsigned int skb_len; 1004 unsigned long flags; 1005 dma_addr_t mapping; 1006 u32 len_status; 1007 u16 queue; 1008 int ret; 1009 1010 queue = skb_get_queue_mapping(skb); 1011 txq = netdev_get_tx_queue(dev, queue); 1012 ring = &priv->tx_rings[queue]; 1013 1014 /* lock against tx reclaim in BH context and TX ring full interrupt */ 1015 spin_lock_irqsave(&ring->lock, flags); 1016 if (unlikely(ring->desc_count == 0)) { 1017 netif_tx_stop_queue(txq); 1018 netdev_err(dev, "queue %d awake and ring full!\n", queue); 1019 ret = NETDEV_TX_BUSY; 1020 goto out; 1021 } 1022 1023 /* Insert TSB and checksum infos */ 1024 if (priv->tsb_en) { 1025 skb = bcm_sysport_insert_tsb(skb, dev); 1026 if (!skb) { 1027 ret = NETDEV_TX_OK; 1028 goto out; 1029 } 1030 } 1031 1032 /* The Ethernet switch we are interfaced with needs packets to be at 1033 * least 64 bytes (including FCS) otherwise they will be discarded when 1034 * they enter the switch port logic. When Broadcom tags are enabled, we 1035 * need to make sure that packets are at least 68 bytes 1036 * (including FCS and tag) because the length verification is done after 1037 * the Broadcom tag is stripped off the ingress packet. 1038 */ 1039 if (skb_padto(skb, ETH_ZLEN + ENET_BRCM_TAG_LEN)) { 1040 ret = NETDEV_TX_OK; 1041 goto out; 1042 } 1043 1044 skb_len = skb->len < ETH_ZLEN + ENET_BRCM_TAG_LEN ? 1045 ETH_ZLEN + ENET_BRCM_TAG_LEN : skb->len; 1046 1047 mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE); 1048 if (dma_mapping_error(kdev, mapping)) { 1049 priv->mib.tx_dma_failed++; 1050 netif_err(priv, tx_err, dev, "DMA map failed at %p (len=%d)\n", 1051 skb->data, skb_len); 1052 ret = NETDEV_TX_OK; 1053 goto out; 1054 } 1055 1056 /* Remember the SKB for future freeing */ 1057 cb = &ring->cbs[ring->curr_desc]; 1058 cb->skb = skb; 1059 dma_unmap_addr_set(cb, dma_addr, mapping); 1060 dma_unmap_len_set(cb, dma_len, skb_len); 1061 1062 /* Fetch a descriptor entry from our pool */ 1063 desc = ring->desc_cpu; 1064 1065 desc->addr_lo = lower_32_bits(mapping); 1066 len_status = upper_32_bits(mapping) & DESC_ADDR_HI_MASK; 1067 len_status |= (skb_len << DESC_LEN_SHIFT); 1068 len_status |= (DESC_SOP | DESC_EOP | TX_STATUS_APP_CRC) << 1069 DESC_STATUS_SHIFT; 1070 if (skb->ip_summed == CHECKSUM_PARTIAL) 1071 len_status |= (DESC_L4_CSUM << DESC_STATUS_SHIFT); 1072 1073 ring->curr_desc++; 1074 if (ring->curr_desc == ring->size) 1075 ring->curr_desc = 0; 1076 ring->desc_count--; 1077 1078 /* Ensure write completion of the descriptor status/length 1079 * in DRAM before the System Port WRITE_PORT register latches 1080 * the value 1081 */ 1082 wmb(); 1083 desc->addr_status_len = len_status; 1084 wmb(); 1085 1086 /* Write this descriptor address to the RING write port */ 1087 tdma_port_write_desc_addr(priv, desc, ring->index); 1088 1089 /* Check ring space and update SW control flow */ 1090 if (ring->desc_count == 0) 1091 netif_tx_stop_queue(txq); 1092 1093 netif_dbg(priv, tx_queued, dev, "ring=%d desc_count=%d, curr_desc=%d\n", 1094 ring->index, ring->desc_count, ring->curr_desc); 1095 1096 ret = NETDEV_TX_OK; 1097 out: 1098 spin_unlock_irqrestore(&ring->lock, flags); 1099 return ret; 1100 } 1101 1102 static void bcm_sysport_tx_timeout(struct net_device *dev) 1103 { 1104 netdev_warn(dev, "transmit timeout!\n"); 1105 1106 dev->trans_start = jiffies; 1107 dev->stats.tx_errors++; 1108 1109 netif_tx_wake_all_queues(dev); 1110 } 1111 1112 /* phylib adjust link callback */ 1113 static void bcm_sysport_adj_link(struct net_device *dev) 1114 { 1115 struct bcm_sysport_priv *priv = netdev_priv(dev); 1116 struct phy_device *phydev = priv->phydev; 1117 unsigned int changed = 0; 1118 u32 cmd_bits = 0, reg; 1119 1120 if (priv->old_link != phydev->link) { 1121 changed = 1; 1122 priv->old_link = phydev->link; 1123 } 1124 1125 if (priv->old_duplex != phydev->duplex) { 1126 changed = 1; 1127 priv->old_duplex = phydev->duplex; 1128 } 1129 1130 switch (phydev->speed) { 1131 case SPEED_2500: 1132 cmd_bits = CMD_SPEED_2500; 1133 break; 1134 case SPEED_1000: 1135 cmd_bits = CMD_SPEED_1000; 1136 break; 1137 case SPEED_100: 1138 cmd_bits = CMD_SPEED_100; 1139 break; 1140 case SPEED_10: 1141 cmd_bits = CMD_SPEED_10; 1142 break; 1143 default: 1144 break; 1145 } 1146 cmd_bits <<= CMD_SPEED_SHIFT; 1147 1148 if (phydev->duplex == DUPLEX_HALF) 1149 cmd_bits |= CMD_HD_EN; 1150 1151 if (priv->old_pause != phydev->pause) { 1152 changed = 1; 1153 priv->old_pause = phydev->pause; 1154 } 1155 1156 if (!phydev->pause) 1157 cmd_bits |= CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE; 1158 1159 if (!changed) 1160 return; 1161 1162 if (phydev->link) { 1163 reg = umac_readl(priv, UMAC_CMD); 1164 reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) | 1165 CMD_HD_EN | CMD_RX_PAUSE_IGNORE | 1166 CMD_TX_PAUSE_IGNORE); 1167 reg |= cmd_bits; 1168 umac_writel(priv, reg, UMAC_CMD); 1169 } 1170 1171 phy_print_status(priv->phydev); 1172 } 1173 1174 static int bcm_sysport_init_tx_ring(struct bcm_sysport_priv *priv, 1175 unsigned int index) 1176 { 1177 struct bcm_sysport_tx_ring *ring = &priv->tx_rings[index]; 1178 struct device *kdev = &priv->pdev->dev; 1179 size_t size; 1180 void *p; 1181 u32 reg; 1182 1183 /* Simple descriptors partitioning for now */ 1184 size = 256; 1185 1186 /* We just need one DMA descriptor which is DMA-able, since writing to 1187 * the port will allocate a new descriptor in its internal linked-list 1188 */ 1189 p = dma_zalloc_coherent(kdev, sizeof(struct dma_desc), &ring->desc_dma, 1190 GFP_KERNEL); 1191 if (!p) { 1192 netif_err(priv, hw, priv->netdev, "DMA alloc failed\n"); 1193 return -ENOMEM; 1194 } 1195 1196 ring->cbs = kcalloc(size, sizeof(struct bcm_sysport_cb), GFP_KERNEL); 1197 if (!ring->cbs) { 1198 netif_err(priv, hw, priv->netdev, "CB allocation failed\n"); 1199 return -ENOMEM; 1200 } 1201 1202 /* Initialize SW view of the ring */ 1203 spin_lock_init(&ring->lock); 1204 ring->priv = priv; 1205 netif_napi_add(priv->netdev, &ring->napi, bcm_sysport_tx_poll, 64); 1206 ring->index = index; 1207 ring->size = size; 1208 ring->alloc_size = ring->size; 1209 ring->desc_cpu = p; 1210 ring->desc_count = ring->size; 1211 ring->curr_desc = 0; 1212 1213 /* Initialize HW ring */ 1214 tdma_writel(priv, RING_EN, TDMA_DESC_RING_HEAD_TAIL_PTR(index)); 1215 tdma_writel(priv, 0, TDMA_DESC_RING_COUNT(index)); 1216 tdma_writel(priv, 1, TDMA_DESC_RING_INTR_CONTROL(index)); 1217 tdma_writel(priv, 0, TDMA_DESC_RING_PROD_CONS_INDEX(index)); 1218 tdma_writel(priv, RING_IGNORE_STATUS, TDMA_DESC_RING_MAPPING(index)); 1219 tdma_writel(priv, 0, TDMA_DESC_RING_PCP_DEI_VID(index)); 1220 1221 /* Program the number of descriptors as MAX_THRESHOLD and half of 1222 * its size for the hysteresis trigger 1223 */ 1224 tdma_writel(priv, ring->size | 1225 1 << RING_HYST_THRESH_SHIFT, 1226 TDMA_DESC_RING_MAX_HYST(index)); 1227 1228 /* Enable the ring queue in the arbiter */ 1229 reg = tdma_readl(priv, TDMA_TIER1_ARB_0_QUEUE_EN); 1230 reg |= (1 << index); 1231 tdma_writel(priv, reg, TDMA_TIER1_ARB_0_QUEUE_EN); 1232 1233 napi_enable(&ring->napi); 1234 1235 netif_dbg(priv, hw, priv->netdev, 1236 "TDMA cfg, size=%d, desc_cpu=%p\n", 1237 ring->size, ring->desc_cpu); 1238 1239 return 0; 1240 } 1241 1242 static void bcm_sysport_fini_tx_ring(struct bcm_sysport_priv *priv, 1243 unsigned int index) 1244 { 1245 struct bcm_sysport_tx_ring *ring = &priv->tx_rings[index]; 1246 struct device *kdev = &priv->pdev->dev; 1247 u32 reg; 1248 1249 /* Caller should stop the TDMA engine */ 1250 reg = tdma_readl(priv, TDMA_STATUS); 1251 if (!(reg & TDMA_DISABLED)) 1252 netdev_warn(priv->netdev, "TDMA not stopped!\n"); 1253 1254 /* ring->cbs is the last part in bcm_sysport_init_tx_ring which could 1255 * fail, so by checking this pointer we know whether the TX ring was 1256 * fully initialized or not. 1257 */ 1258 if (!ring->cbs) 1259 return; 1260 1261 napi_disable(&ring->napi); 1262 netif_napi_del(&ring->napi); 1263 1264 bcm_sysport_tx_reclaim(priv, ring); 1265 1266 kfree(ring->cbs); 1267 ring->cbs = NULL; 1268 1269 if (ring->desc_dma) { 1270 dma_free_coherent(kdev, sizeof(struct dma_desc), 1271 ring->desc_cpu, ring->desc_dma); 1272 ring->desc_dma = 0; 1273 } 1274 ring->size = 0; 1275 ring->alloc_size = 0; 1276 1277 netif_dbg(priv, hw, priv->netdev, "TDMA fini done\n"); 1278 } 1279 1280 /* RDMA helper */ 1281 static inline int rdma_enable_set(struct bcm_sysport_priv *priv, 1282 unsigned int enable) 1283 { 1284 unsigned int timeout = 1000; 1285 u32 reg; 1286 1287 reg = rdma_readl(priv, RDMA_CONTROL); 1288 if (enable) 1289 reg |= RDMA_EN; 1290 else 1291 reg &= ~RDMA_EN; 1292 rdma_writel(priv, reg, RDMA_CONTROL); 1293 1294 /* Poll for RMDA disabling completion */ 1295 do { 1296 reg = rdma_readl(priv, RDMA_STATUS); 1297 if (!!(reg & RDMA_DISABLED) == !enable) 1298 return 0; 1299 usleep_range(1000, 2000); 1300 } while (timeout-- > 0); 1301 1302 netdev_err(priv->netdev, "timeout waiting for RDMA to finish\n"); 1303 1304 return -ETIMEDOUT; 1305 } 1306 1307 /* TDMA helper */ 1308 static inline int tdma_enable_set(struct bcm_sysport_priv *priv, 1309 unsigned int enable) 1310 { 1311 unsigned int timeout = 1000; 1312 u32 reg; 1313 1314 reg = tdma_readl(priv, TDMA_CONTROL); 1315 if (enable) 1316 reg |= TDMA_EN; 1317 else 1318 reg &= ~TDMA_EN; 1319 tdma_writel(priv, reg, TDMA_CONTROL); 1320 1321 /* Poll for TMDA disabling completion */ 1322 do { 1323 reg = tdma_readl(priv, TDMA_STATUS); 1324 if (!!(reg & TDMA_DISABLED) == !enable) 1325 return 0; 1326 1327 usleep_range(1000, 2000); 1328 } while (timeout-- > 0); 1329 1330 netdev_err(priv->netdev, "timeout waiting for TDMA to finish\n"); 1331 1332 return -ETIMEDOUT; 1333 } 1334 1335 static int bcm_sysport_init_rx_ring(struct bcm_sysport_priv *priv) 1336 { 1337 struct bcm_sysport_cb *cb; 1338 u32 reg; 1339 int ret; 1340 int i; 1341 1342 /* Initialize SW view of the RX ring */ 1343 priv->num_rx_bds = NUM_RX_DESC; 1344 priv->rx_bds = priv->base + SYS_PORT_RDMA_OFFSET; 1345 priv->rx_c_index = 0; 1346 priv->rx_read_ptr = 0; 1347 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct bcm_sysport_cb), 1348 GFP_KERNEL); 1349 if (!priv->rx_cbs) { 1350 netif_err(priv, hw, priv->netdev, "CB allocation failed\n"); 1351 return -ENOMEM; 1352 } 1353 1354 for (i = 0; i < priv->num_rx_bds; i++) { 1355 cb = priv->rx_cbs + i; 1356 cb->bd_addr = priv->rx_bds + i * DESC_SIZE; 1357 } 1358 1359 ret = bcm_sysport_alloc_rx_bufs(priv); 1360 if (ret) { 1361 netif_err(priv, hw, priv->netdev, "SKB allocation failed\n"); 1362 return ret; 1363 } 1364 1365 /* Initialize HW, ensure RDMA is disabled */ 1366 reg = rdma_readl(priv, RDMA_STATUS); 1367 if (!(reg & RDMA_DISABLED)) 1368 rdma_enable_set(priv, 0); 1369 1370 rdma_writel(priv, 0, RDMA_WRITE_PTR_LO); 1371 rdma_writel(priv, 0, RDMA_WRITE_PTR_HI); 1372 rdma_writel(priv, 0, RDMA_PROD_INDEX); 1373 rdma_writel(priv, 0, RDMA_CONS_INDEX); 1374 rdma_writel(priv, priv->num_rx_bds << RDMA_RING_SIZE_SHIFT | 1375 RX_BUF_LENGTH, RDMA_RING_BUF_SIZE); 1376 /* Operate the queue in ring mode */ 1377 rdma_writel(priv, 0, RDMA_START_ADDR_HI); 1378 rdma_writel(priv, 0, RDMA_START_ADDR_LO); 1379 rdma_writel(priv, 0, RDMA_END_ADDR_HI); 1380 rdma_writel(priv, NUM_HW_RX_DESC_WORDS - 1, RDMA_END_ADDR_LO); 1381 1382 rdma_writel(priv, 1, RDMA_MBDONE_INTR); 1383 1384 netif_dbg(priv, hw, priv->netdev, 1385 "RDMA cfg, num_rx_bds=%d, rx_bds=%p\n", 1386 priv->num_rx_bds, priv->rx_bds); 1387 1388 return 0; 1389 } 1390 1391 static void bcm_sysport_fini_rx_ring(struct bcm_sysport_priv *priv) 1392 { 1393 struct bcm_sysport_cb *cb; 1394 unsigned int i; 1395 u32 reg; 1396 1397 /* Caller should ensure RDMA is disabled */ 1398 reg = rdma_readl(priv, RDMA_STATUS); 1399 if (!(reg & RDMA_DISABLED)) 1400 netdev_warn(priv->netdev, "RDMA not stopped!\n"); 1401 1402 for (i = 0; i < priv->num_rx_bds; i++) { 1403 cb = &priv->rx_cbs[i]; 1404 if (dma_unmap_addr(cb, dma_addr)) 1405 dma_unmap_single(&priv->pdev->dev, 1406 dma_unmap_addr(cb, dma_addr), 1407 RX_BUF_LENGTH, DMA_FROM_DEVICE); 1408 bcm_sysport_free_cb(cb); 1409 } 1410 1411 kfree(priv->rx_cbs); 1412 priv->rx_cbs = NULL; 1413 1414 netif_dbg(priv, hw, priv->netdev, "RDMA fini done\n"); 1415 } 1416 1417 static void bcm_sysport_set_rx_mode(struct net_device *dev) 1418 { 1419 struct bcm_sysport_priv *priv = netdev_priv(dev); 1420 u32 reg; 1421 1422 reg = umac_readl(priv, UMAC_CMD); 1423 if (dev->flags & IFF_PROMISC) 1424 reg |= CMD_PROMISC; 1425 else 1426 reg &= ~CMD_PROMISC; 1427 umac_writel(priv, reg, UMAC_CMD); 1428 1429 /* No support for ALLMULTI */ 1430 if (dev->flags & IFF_ALLMULTI) 1431 return; 1432 } 1433 1434 static inline void umac_enable_set(struct bcm_sysport_priv *priv, 1435 u32 mask, unsigned int enable) 1436 { 1437 u32 reg; 1438 1439 reg = umac_readl(priv, UMAC_CMD); 1440 if (enable) 1441 reg |= mask; 1442 else 1443 reg &= ~mask; 1444 umac_writel(priv, reg, UMAC_CMD); 1445 1446 /* UniMAC stops on a packet boundary, wait for a full-sized packet 1447 * to be processed (1 msec). 1448 */ 1449 if (enable == 0) 1450 usleep_range(1000, 2000); 1451 } 1452 1453 static inline void umac_reset(struct bcm_sysport_priv *priv) 1454 { 1455 u32 reg; 1456 1457 reg = umac_readl(priv, UMAC_CMD); 1458 reg |= CMD_SW_RESET; 1459 umac_writel(priv, reg, UMAC_CMD); 1460 udelay(10); 1461 reg = umac_readl(priv, UMAC_CMD); 1462 reg &= ~CMD_SW_RESET; 1463 umac_writel(priv, reg, UMAC_CMD); 1464 } 1465 1466 static void umac_set_hw_addr(struct bcm_sysport_priv *priv, 1467 unsigned char *addr) 1468 { 1469 umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) | 1470 (addr[2] << 8) | addr[3], UMAC_MAC0); 1471 umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1); 1472 } 1473 1474 static void topctrl_flush(struct bcm_sysport_priv *priv) 1475 { 1476 topctrl_writel(priv, RX_FLUSH, RX_FLUSH_CNTL); 1477 topctrl_writel(priv, TX_FLUSH, TX_FLUSH_CNTL); 1478 mdelay(1); 1479 topctrl_writel(priv, 0, RX_FLUSH_CNTL); 1480 topctrl_writel(priv, 0, TX_FLUSH_CNTL); 1481 } 1482 1483 static int bcm_sysport_change_mac(struct net_device *dev, void *p) 1484 { 1485 struct bcm_sysport_priv *priv = netdev_priv(dev); 1486 struct sockaddr *addr = p; 1487 1488 if (!is_valid_ether_addr(addr->sa_data)) 1489 return -EINVAL; 1490 1491 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 1492 1493 /* interface is disabled, changes to MAC will be reflected on next 1494 * open call 1495 */ 1496 if (!netif_running(dev)) 1497 return 0; 1498 1499 umac_set_hw_addr(priv, dev->dev_addr); 1500 1501 return 0; 1502 } 1503 1504 static void bcm_sysport_netif_start(struct net_device *dev) 1505 { 1506 struct bcm_sysport_priv *priv = netdev_priv(dev); 1507 1508 /* Enable NAPI */ 1509 napi_enable(&priv->napi); 1510 1511 /* Enable RX interrupt and TX ring full interrupt */ 1512 intrl2_0_mask_clear(priv, INTRL2_0_RDMA_MBDONE | INTRL2_0_TX_RING_FULL); 1513 1514 phy_start(priv->phydev); 1515 1516 /* Enable TX interrupts for the 32 TXQs */ 1517 intrl2_1_mask_clear(priv, 0xffffffff); 1518 1519 /* Last call before we start the real business */ 1520 netif_tx_start_all_queues(dev); 1521 } 1522 1523 static void rbuf_init(struct bcm_sysport_priv *priv) 1524 { 1525 u32 reg; 1526 1527 reg = rbuf_readl(priv, RBUF_CONTROL); 1528 reg |= RBUF_4B_ALGN | RBUF_RSB_EN; 1529 rbuf_writel(priv, reg, RBUF_CONTROL); 1530 } 1531 1532 static int bcm_sysport_open(struct net_device *dev) 1533 { 1534 struct bcm_sysport_priv *priv = netdev_priv(dev); 1535 unsigned int i; 1536 int ret; 1537 1538 /* Reset UniMAC */ 1539 umac_reset(priv); 1540 1541 /* Flush TX and RX FIFOs at TOPCTRL level */ 1542 topctrl_flush(priv); 1543 1544 /* Disable the UniMAC RX/TX */ 1545 umac_enable_set(priv, CMD_RX_EN | CMD_TX_EN, 0); 1546 1547 /* Enable RBUF 2bytes alignment and Receive Status Block */ 1548 rbuf_init(priv); 1549 1550 /* Set maximum frame length */ 1551 umac_writel(priv, UMAC_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN); 1552 1553 /* Set MAC address */ 1554 umac_set_hw_addr(priv, dev->dev_addr); 1555 1556 /* Read CRC forward */ 1557 priv->crc_fwd = !!(umac_readl(priv, UMAC_CMD) & CMD_CRC_FWD); 1558 1559 priv->phydev = of_phy_connect(dev, priv->phy_dn, bcm_sysport_adj_link, 1560 0, priv->phy_interface); 1561 if (!priv->phydev) { 1562 netdev_err(dev, "could not attach to PHY\n"); 1563 return -ENODEV; 1564 } 1565 1566 /* Reset house keeping link status */ 1567 priv->old_duplex = -1; 1568 priv->old_link = -1; 1569 priv->old_pause = -1; 1570 1571 /* mask all interrupts and request them */ 1572 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_MASK_SET); 1573 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 1574 intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR); 1575 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_MASK_SET); 1576 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 1577 intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR); 1578 1579 ret = request_irq(priv->irq0, bcm_sysport_rx_isr, 0, dev->name, dev); 1580 if (ret) { 1581 netdev_err(dev, "failed to request RX interrupt\n"); 1582 goto out_phy_disconnect; 1583 } 1584 1585 ret = request_irq(priv->irq1, bcm_sysport_tx_isr, 0, dev->name, dev); 1586 if (ret) { 1587 netdev_err(dev, "failed to request TX interrupt\n"); 1588 goto out_free_irq0; 1589 } 1590 1591 /* Initialize both hardware and software ring */ 1592 for (i = 0; i < dev->num_tx_queues; i++) { 1593 ret = bcm_sysport_init_tx_ring(priv, i); 1594 if (ret) { 1595 netdev_err(dev, "failed to initialize TX ring %d\n", 1596 i); 1597 goto out_free_tx_ring; 1598 } 1599 } 1600 1601 /* Initialize linked-list */ 1602 tdma_writel(priv, TDMA_LL_RAM_INIT_BUSY, TDMA_STATUS); 1603 1604 /* Initialize RX ring */ 1605 ret = bcm_sysport_init_rx_ring(priv); 1606 if (ret) { 1607 netdev_err(dev, "failed to initialize RX ring\n"); 1608 goto out_free_rx_ring; 1609 } 1610 1611 /* Turn on RDMA */ 1612 ret = rdma_enable_set(priv, 1); 1613 if (ret) 1614 goto out_free_rx_ring; 1615 1616 /* Turn on TDMA */ 1617 ret = tdma_enable_set(priv, 1); 1618 if (ret) 1619 goto out_clear_rx_int; 1620 1621 /* Turn on UniMAC TX/RX */ 1622 umac_enable_set(priv, CMD_RX_EN | CMD_TX_EN, 1); 1623 1624 bcm_sysport_netif_start(dev); 1625 1626 return 0; 1627 1628 out_clear_rx_int: 1629 intrl2_0_mask_set(priv, INTRL2_0_RDMA_MBDONE | INTRL2_0_TX_RING_FULL); 1630 out_free_rx_ring: 1631 bcm_sysport_fini_rx_ring(priv); 1632 out_free_tx_ring: 1633 for (i = 0; i < dev->num_tx_queues; i++) 1634 bcm_sysport_fini_tx_ring(priv, i); 1635 free_irq(priv->irq1, dev); 1636 out_free_irq0: 1637 free_irq(priv->irq0, dev); 1638 out_phy_disconnect: 1639 phy_disconnect(priv->phydev); 1640 return ret; 1641 } 1642 1643 static void bcm_sysport_netif_stop(struct net_device *dev) 1644 { 1645 struct bcm_sysport_priv *priv = netdev_priv(dev); 1646 1647 /* stop all software from updating hardware */ 1648 netif_tx_stop_all_queues(dev); 1649 napi_disable(&priv->napi); 1650 phy_stop(priv->phydev); 1651 1652 /* mask all interrupts */ 1653 intrl2_0_mask_set(priv, 0xffffffff); 1654 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 1655 intrl2_1_mask_set(priv, 0xffffffff); 1656 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 1657 } 1658 1659 static int bcm_sysport_stop(struct net_device *dev) 1660 { 1661 struct bcm_sysport_priv *priv = netdev_priv(dev); 1662 unsigned int i; 1663 int ret; 1664 1665 bcm_sysport_netif_stop(dev); 1666 1667 /* Disable UniMAC RX */ 1668 umac_enable_set(priv, CMD_RX_EN, 0); 1669 1670 ret = tdma_enable_set(priv, 0); 1671 if (ret) { 1672 netdev_err(dev, "timeout disabling RDMA\n"); 1673 return ret; 1674 } 1675 1676 /* Wait for a maximum packet size to be drained */ 1677 usleep_range(2000, 3000); 1678 1679 ret = rdma_enable_set(priv, 0); 1680 if (ret) { 1681 netdev_err(dev, "timeout disabling TDMA\n"); 1682 return ret; 1683 } 1684 1685 /* Disable UniMAC TX */ 1686 umac_enable_set(priv, CMD_TX_EN, 0); 1687 1688 /* Free RX/TX rings SW structures */ 1689 for (i = 0; i < dev->num_tx_queues; i++) 1690 bcm_sysport_fini_tx_ring(priv, i); 1691 bcm_sysport_fini_rx_ring(priv); 1692 1693 free_irq(priv->irq0, dev); 1694 free_irq(priv->irq1, dev); 1695 1696 /* Disconnect from PHY */ 1697 phy_disconnect(priv->phydev); 1698 1699 return 0; 1700 } 1701 1702 static struct ethtool_ops bcm_sysport_ethtool_ops = { 1703 .get_settings = bcm_sysport_get_settings, 1704 .set_settings = bcm_sysport_set_settings, 1705 .get_drvinfo = bcm_sysport_get_drvinfo, 1706 .get_msglevel = bcm_sysport_get_msglvl, 1707 .set_msglevel = bcm_sysport_set_msglvl, 1708 .get_link = ethtool_op_get_link, 1709 .get_strings = bcm_sysport_get_strings, 1710 .get_ethtool_stats = bcm_sysport_get_stats, 1711 .get_sset_count = bcm_sysport_get_sset_count, 1712 .get_wol = bcm_sysport_get_wol, 1713 .set_wol = bcm_sysport_set_wol, 1714 .get_coalesce = bcm_sysport_get_coalesce, 1715 .set_coalesce = bcm_sysport_set_coalesce, 1716 }; 1717 1718 static const struct net_device_ops bcm_sysport_netdev_ops = { 1719 .ndo_start_xmit = bcm_sysport_xmit, 1720 .ndo_tx_timeout = bcm_sysport_tx_timeout, 1721 .ndo_open = bcm_sysport_open, 1722 .ndo_stop = bcm_sysport_stop, 1723 .ndo_set_features = bcm_sysport_set_features, 1724 .ndo_set_rx_mode = bcm_sysport_set_rx_mode, 1725 .ndo_set_mac_address = bcm_sysport_change_mac, 1726 }; 1727 1728 #define REV_FMT "v%2x.%02x" 1729 1730 static int bcm_sysport_probe(struct platform_device *pdev) 1731 { 1732 struct bcm_sysport_priv *priv; 1733 struct device_node *dn; 1734 struct net_device *dev; 1735 const void *macaddr; 1736 struct resource *r; 1737 u32 txq, rxq; 1738 int ret; 1739 1740 dn = pdev->dev.of_node; 1741 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1742 1743 /* Read the Transmit/Receive Queue properties */ 1744 if (of_property_read_u32(dn, "systemport,num-txq", &txq)) 1745 txq = TDMA_NUM_RINGS; 1746 if (of_property_read_u32(dn, "systemport,num-rxq", &rxq)) 1747 rxq = 1; 1748 1749 dev = alloc_etherdev_mqs(sizeof(*priv), txq, rxq); 1750 if (!dev) 1751 return -ENOMEM; 1752 1753 /* Initialize private members */ 1754 priv = netdev_priv(dev); 1755 1756 priv->irq0 = platform_get_irq(pdev, 0); 1757 priv->irq1 = platform_get_irq(pdev, 1); 1758 priv->wol_irq = platform_get_irq(pdev, 2); 1759 if (priv->irq0 <= 0 || priv->irq1 <= 0) { 1760 dev_err(&pdev->dev, "invalid interrupts\n"); 1761 ret = -EINVAL; 1762 goto err; 1763 } 1764 1765 priv->base = devm_ioremap_resource(&pdev->dev, r); 1766 if (IS_ERR(priv->base)) { 1767 ret = PTR_ERR(priv->base); 1768 goto err; 1769 } 1770 1771 priv->netdev = dev; 1772 priv->pdev = pdev; 1773 1774 priv->phy_interface = of_get_phy_mode(dn); 1775 /* Default to GMII interface mode */ 1776 if (priv->phy_interface < 0) 1777 priv->phy_interface = PHY_INTERFACE_MODE_GMII; 1778 1779 /* In the case of a fixed PHY, the DT node associated 1780 * to the PHY is the Ethernet MAC DT node. 1781 */ 1782 if (of_phy_is_fixed_link(dn)) { 1783 ret = of_phy_register_fixed_link(dn); 1784 if (ret) { 1785 dev_err(&pdev->dev, "failed to register fixed PHY\n"); 1786 goto err; 1787 } 1788 1789 priv->phy_dn = dn; 1790 } 1791 1792 /* Initialize netdevice members */ 1793 macaddr = of_get_mac_address(dn); 1794 if (!macaddr || !is_valid_ether_addr(macaddr)) { 1795 dev_warn(&pdev->dev, "using random Ethernet MAC\n"); 1796 random_ether_addr(dev->dev_addr); 1797 } else { 1798 ether_addr_copy(dev->dev_addr, macaddr); 1799 } 1800 1801 SET_NETDEV_DEV(dev, &pdev->dev); 1802 dev_set_drvdata(&pdev->dev, dev); 1803 dev->ethtool_ops = &bcm_sysport_ethtool_ops; 1804 dev->netdev_ops = &bcm_sysport_netdev_ops; 1805 netif_napi_add(dev, &priv->napi, bcm_sysport_poll, 64); 1806 1807 /* HW supported features, none enabled by default */ 1808 dev->hw_features |= NETIF_F_RXCSUM | NETIF_F_HIGHDMA | 1809 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 1810 1811 /* Request the WOL interrupt and advertise suspend if available */ 1812 priv->wol_irq_disabled = 1; 1813 ret = devm_request_irq(&pdev->dev, priv->wol_irq, 1814 bcm_sysport_wol_isr, 0, dev->name, priv); 1815 if (!ret) 1816 device_set_wakeup_capable(&pdev->dev, 1); 1817 1818 /* Set the needed headroom once and for all */ 1819 BUILD_BUG_ON(sizeof(struct bcm_tsb) != 8); 1820 dev->needed_headroom += sizeof(struct bcm_tsb); 1821 1822 /* libphy will adjust the link state accordingly */ 1823 netif_carrier_off(dev); 1824 1825 ret = register_netdev(dev); 1826 if (ret) { 1827 dev_err(&pdev->dev, "failed to register net_device\n"); 1828 goto err; 1829 } 1830 1831 priv->rev = topctrl_readl(priv, REV_CNTL) & REV_MASK; 1832 dev_info(&pdev->dev, 1833 "Broadcom SYSTEMPORT" REV_FMT 1834 " at 0x%p (irqs: %d, %d, TXQs: %d, RXQs: %d)\n", 1835 (priv->rev >> 8) & 0xff, priv->rev & 0xff, 1836 priv->base, priv->irq0, priv->irq1, txq, rxq); 1837 1838 return 0; 1839 err: 1840 free_netdev(dev); 1841 return ret; 1842 } 1843 1844 static int bcm_sysport_remove(struct platform_device *pdev) 1845 { 1846 struct net_device *dev = dev_get_drvdata(&pdev->dev); 1847 1848 /* Not much to do, ndo_close has been called 1849 * and we use managed allocations 1850 */ 1851 unregister_netdev(dev); 1852 free_netdev(dev); 1853 dev_set_drvdata(&pdev->dev, NULL); 1854 1855 return 0; 1856 } 1857 1858 #ifdef CONFIG_PM_SLEEP 1859 static int bcm_sysport_suspend_to_wol(struct bcm_sysport_priv *priv) 1860 { 1861 struct net_device *ndev = priv->netdev; 1862 unsigned int timeout = 1000; 1863 u32 reg; 1864 1865 /* Password has already been programmed */ 1866 reg = umac_readl(priv, UMAC_MPD_CTRL); 1867 reg |= MPD_EN; 1868 reg &= ~PSW_EN; 1869 if (priv->wolopts & WAKE_MAGICSECURE) 1870 reg |= PSW_EN; 1871 umac_writel(priv, reg, UMAC_MPD_CTRL); 1872 1873 /* Make sure RBUF entered WoL mode as result */ 1874 do { 1875 reg = rbuf_readl(priv, RBUF_STATUS); 1876 if (reg & RBUF_WOL_MODE) 1877 break; 1878 1879 udelay(10); 1880 } while (timeout-- > 0); 1881 1882 /* Do not leave the UniMAC RBUF matching only MPD packets */ 1883 if (!timeout) { 1884 reg = umac_readl(priv, UMAC_MPD_CTRL); 1885 reg &= ~MPD_EN; 1886 umac_writel(priv, reg, UMAC_MPD_CTRL); 1887 netif_err(priv, wol, ndev, "failed to enter WOL mode\n"); 1888 return -ETIMEDOUT; 1889 } 1890 1891 /* UniMAC receive needs to be turned on */ 1892 umac_enable_set(priv, CMD_RX_EN, 1); 1893 1894 /* Enable the interrupt wake-up source */ 1895 intrl2_0_mask_clear(priv, INTRL2_0_MPD); 1896 1897 netif_dbg(priv, wol, ndev, "entered WOL mode\n"); 1898 1899 return 0; 1900 } 1901 1902 static int bcm_sysport_suspend(struct device *d) 1903 { 1904 struct net_device *dev = dev_get_drvdata(d); 1905 struct bcm_sysport_priv *priv = netdev_priv(dev); 1906 unsigned int i; 1907 int ret = 0; 1908 u32 reg; 1909 1910 if (!netif_running(dev)) 1911 return 0; 1912 1913 bcm_sysport_netif_stop(dev); 1914 1915 phy_suspend(priv->phydev); 1916 1917 netif_device_detach(dev); 1918 1919 /* Disable UniMAC RX */ 1920 umac_enable_set(priv, CMD_RX_EN, 0); 1921 1922 ret = rdma_enable_set(priv, 0); 1923 if (ret) { 1924 netdev_err(dev, "RDMA timeout!\n"); 1925 return ret; 1926 } 1927 1928 /* Disable RXCHK if enabled */ 1929 if (priv->rx_chk_en) { 1930 reg = rxchk_readl(priv, RXCHK_CONTROL); 1931 reg &= ~RXCHK_EN; 1932 rxchk_writel(priv, reg, RXCHK_CONTROL); 1933 } 1934 1935 /* Flush RX pipe */ 1936 if (!priv->wolopts) 1937 topctrl_writel(priv, RX_FLUSH, RX_FLUSH_CNTL); 1938 1939 ret = tdma_enable_set(priv, 0); 1940 if (ret) { 1941 netdev_err(dev, "TDMA timeout!\n"); 1942 return ret; 1943 } 1944 1945 /* Wait for a packet boundary */ 1946 usleep_range(2000, 3000); 1947 1948 umac_enable_set(priv, CMD_TX_EN, 0); 1949 1950 topctrl_writel(priv, TX_FLUSH, TX_FLUSH_CNTL); 1951 1952 /* Free RX/TX rings SW structures */ 1953 for (i = 0; i < dev->num_tx_queues; i++) 1954 bcm_sysport_fini_tx_ring(priv, i); 1955 bcm_sysport_fini_rx_ring(priv); 1956 1957 /* Get prepared for Wake-on-LAN */ 1958 if (device_may_wakeup(d) && priv->wolopts) 1959 ret = bcm_sysport_suspend_to_wol(priv); 1960 1961 return ret; 1962 } 1963 1964 static int bcm_sysport_resume(struct device *d) 1965 { 1966 struct net_device *dev = dev_get_drvdata(d); 1967 struct bcm_sysport_priv *priv = netdev_priv(dev); 1968 unsigned int i; 1969 u32 reg; 1970 int ret; 1971 1972 if (!netif_running(dev)) 1973 return 0; 1974 1975 umac_reset(priv); 1976 1977 /* We may have been suspended and never received a WOL event that 1978 * would turn off MPD detection, take care of that now 1979 */ 1980 bcm_sysport_resume_from_wol(priv); 1981 1982 /* Initialize both hardware and software ring */ 1983 for (i = 0; i < dev->num_tx_queues; i++) { 1984 ret = bcm_sysport_init_tx_ring(priv, i); 1985 if (ret) { 1986 netdev_err(dev, "failed to initialize TX ring %d\n", 1987 i); 1988 goto out_free_tx_rings; 1989 } 1990 } 1991 1992 /* Initialize linked-list */ 1993 tdma_writel(priv, TDMA_LL_RAM_INIT_BUSY, TDMA_STATUS); 1994 1995 /* Initialize RX ring */ 1996 ret = bcm_sysport_init_rx_ring(priv); 1997 if (ret) { 1998 netdev_err(dev, "failed to initialize RX ring\n"); 1999 goto out_free_rx_ring; 2000 } 2001 2002 netif_device_attach(dev); 2003 2004 /* RX pipe enable */ 2005 topctrl_writel(priv, 0, RX_FLUSH_CNTL); 2006 2007 ret = rdma_enable_set(priv, 1); 2008 if (ret) { 2009 netdev_err(dev, "failed to enable RDMA\n"); 2010 goto out_free_rx_ring; 2011 } 2012 2013 /* Enable rxhck */ 2014 if (priv->rx_chk_en) { 2015 reg = rxchk_readl(priv, RXCHK_CONTROL); 2016 reg |= RXCHK_EN; 2017 rxchk_writel(priv, reg, RXCHK_CONTROL); 2018 } 2019 2020 rbuf_init(priv); 2021 2022 /* Set maximum frame length */ 2023 umac_writel(priv, UMAC_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN); 2024 2025 /* Set MAC address */ 2026 umac_set_hw_addr(priv, dev->dev_addr); 2027 2028 umac_enable_set(priv, CMD_RX_EN, 1); 2029 2030 /* TX pipe enable */ 2031 topctrl_writel(priv, 0, TX_FLUSH_CNTL); 2032 2033 umac_enable_set(priv, CMD_TX_EN, 1); 2034 2035 ret = tdma_enable_set(priv, 1); 2036 if (ret) { 2037 netdev_err(dev, "TDMA timeout!\n"); 2038 goto out_free_rx_ring; 2039 } 2040 2041 phy_resume(priv->phydev); 2042 2043 bcm_sysport_netif_start(dev); 2044 2045 return 0; 2046 2047 out_free_rx_ring: 2048 bcm_sysport_fini_rx_ring(priv); 2049 out_free_tx_rings: 2050 for (i = 0; i < dev->num_tx_queues; i++) 2051 bcm_sysport_fini_tx_ring(priv, i); 2052 return ret; 2053 } 2054 #endif 2055 2056 static SIMPLE_DEV_PM_OPS(bcm_sysport_pm_ops, 2057 bcm_sysport_suspend, bcm_sysport_resume); 2058 2059 static const struct of_device_id bcm_sysport_of_match[] = { 2060 { .compatible = "brcm,systemport-v1.00" }, 2061 { .compatible = "brcm,systemport" }, 2062 { /* sentinel */ } 2063 }; 2064 2065 static struct platform_driver bcm_sysport_driver = { 2066 .probe = bcm_sysport_probe, 2067 .remove = bcm_sysport_remove, 2068 .driver = { 2069 .name = "brcm-systemport", 2070 .of_match_table = bcm_sysport_of_match, 2071 .pm = &bcm_sysport_pm_ops, 2072 }, 2073 }; 2074 module_platform_driver(bcm_sysport_driver); 2075 2076 MODULE_AUTHOR("Broadcom Corporation"); 2077 MODULE_DESCRIPTION("Broadcom System Port Ethernet MAC driver"); 2078 MODULE_ALIAS("platform:brcm-systemport"); 2079 MODULE_LICENSE("GPL"); 2080