1 // SPDX-License-Identifier: GPL-2.0 2 #define pr_fmt(fmt) "bcmasp_intf: " fmt 3 4 #include <asm/byteorder.h> 5 #include <linux/brcmphy.h> 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/etherdevice.h> 9 #include <linux/netdevice.h> 10 #include <linux/of_net.h> 11 #include <linux/of_mdio.h> 12 #include <linux/phy.h> 13 #include <linux/phy_fixed.h> 14 #include <linux/ptp_classify.h> 15 #include <linux/platform_device.h> 16 #include <net/ip.h> 17 #include <net/ipv6.h> 18 19 #include "bcmasp.h" 20 #include "bcmasp_intf_defs.h" 21 22 static int incr_ring(int index, int ring_count) 23 { 24 index++; 25 if (index == ring_count) 26 return 0; 27 28 return index; 29 } 30 31 /* Points to last byte of descriptor */ 32 static dma_addr_t incr_last_byte(dma_addr_t addr, dma_addr_t beg, 33 int ring_count) 34 { 35 dma_addr_t end = beg + (ring_count * DESC_SIZE); 36 37 addr += DESC_SIZE; 38 if (addr > end) 39 return beg + DESC_SIZE - 1; 40 41 return addr; 42 } 43 44 /* Points to first byte of descriptor */ 45 static dma_addr_t incr_first_byte(dma_addr_t addr, dma_addr_t beg, 46 int ring_count) 47 { 48 dma_addr_t end = beg + (ring_count * DESC_SIZE); 49 50 addr += DESC_SIZE; 51 if (addr >= end) 52 return beg; 53 54 return addr; 55 } 56 57 static void bcmasp_enable_tx(struct bcmasp_intf *intf, int en) 58 { 59 if (en) { 60 tx_spb_ctrl_wl(intf, TX_SPB_CTRL_ENABLE_EN, TX_SPB_CTRL_ENABLE); 61 tx_epkt_core_wl(intf, (TX_EPKT_C_CFG_MISC_EN | 62 TX_EPKT_C_CFG_MISC_PT | 63 (intf->port << TX_EPKT_C_CFG_MISC_PS_SHIFT)), 64 TX_EPKT_C_CFG_MISC); 65 } else { 66 tx_spb_ctrl_wl(intf, 0x0, TX_SPB_CTRL_ENABLE); 67 tx_epkt_core_wl(intf, 0x0, TX_EPKT_C_CFG_MISC); 68 } 69 } 70 71 static void bcmasp_enable_rx(struct bcmasp_intf *intf, int en) 72 { 73 if (en) 74 rx_edpkt_cfg_wl(intf, RX_EDPKT_CFG_ENABLE_EN, 75 RX_EDPKT_CFG_ENABLE); 76 else 77 rx_edpkt_cfg_wl(intf, 0x0, RX_EDPKT_CFG_ENABLE); 78 } 79 80 static void bcmasp_set_rx_mode(struct net_device *dev) 81 { 82 unsigned char mask[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 83 struct bcmasp_intf *intf = netdev_priv(dev); 84 struct netdev_hw_addr *ha; 85 int ret; 86 87 spin_lock_bh(&intf->parent->mda_lock); 88 89 bcmasp_disable_all_filters(intf); 90 91 if (dev->flags & IFF_PROMISC) 92 goto set_promisc; 93 94 bcmasp_set_promisc(intf, 0); 95 96 bcmasp_set_broad(intf, 1); 97 98 bcmasp_set_oaddr(intf, dev->dev_addr, 1); 99 100 if (dev->flags & IFF_ALLMULTI) { 101 bcmasp_set_allmulti(intf, 1); 102 } else { 103 bcmasp_set_allmulti(intf, 0); 104 105 netdev_for_each_mc_addr(ha, dev) { 106 ret = bcmasp_set_en_mda_filter(intf, ha->addr, mask); 107 if (ret) { 108 intf->mib.mc_filters_full_cnt++; 109 goto set_promisc; 110 } 111 } 112 } 113 114 netdev_for_each_uc_addr(ha, dev) { 115 ret = bcmasp_set_en_mda_filter(intf, ha->addr, mask); 116 if (ret) { 117 intf->mib.uc_filters_full_cnt++; 118 goto set_promisc; 119 } 120 } 121 122 spin_unlock_bh(&intf->parent->mda_lock); 123 return; 124 125 set_promisc: 126 bcmasp_set_promisc(intf, 1); 127 intf->mib.promisc_filters_cnt++; 128 129 /* disable all filters used by this port */ 130 bcmasp_disable_all_filters(intf); 131 132 spin_unlock_bh(&intf->parent->mda_lock); 133 } 134 135 static void bcmasp_clean_txcb(struct bcmasp_intf *intf, int index) 136 { 137 struct bcmasp_tx_cb *txcb = &intf->tx_cbs[index]; 138 139 txcb->skb = NULL; 140 dma_unmap_addr_set(txcb, dma_addr, 0); 141 dma_unmap_len_set(txcb, dma_len, 0); 142 txcb->last = false; 143 } 144 145 static int tx_spb_ring_full(struct bcmasp_intf *intf, int cnt) 146 { 147 int next_index, i; 148 149 /* Check if we have enough room for cnt descriptors */ 150 for (i = 0; i < cnt; i++) { 151 next_index = incr_ring(intf->tx_spb_index, DESC_RING_COUNT); 152 if (next_index == intf->tx_spb_clean_index) 153 return 1; 154 } 155 156 return 0; 157 } 158 159 static struct sk_buff *bcmasp_csum_offload(struct net_device *dev, 160 struct sk_buff *skb, 161 bool *csum_hw) 162 { 163 struct bcmasp_intf *intf = netdev_priv(dev); 164 u32 header = 0, header2 = 0, epkt = 0; 165 struct bcmasp_pkt_offload *offload; 166 unsigned int header_cnt = 0; 167 u8 ip_proto; 168 int ret; 169 170 if (skb->ip_summed != CHECKSUM_PARTIAL) 171 return skb; 172 173 ret = skb_cow_head(skb, sizeof(*offload)); 174 if (ret < 0) { 175 intf->mib.tx_realloc_offload_failed++; 176 goto help; 177 } 178 179 switch (skb->protocol) { 180 case htons(ETH_P_IP): 181 header |= PKT_OFFLOAD_HDR_SIZE_2((ip_hdrlen(skb) >> 8) & 0xf); 182 header2 |= PKT_OFFLOAD_HDR2_SIZE_2(ip_hdrlen(skb) & 0xff); 183 epkt |= PKT_OFFLOAD_EPKT_IP(0) | PKT_OFFLOAD_EPKT_CSUM_L2; 184 ip_proto = ip_hdr(skb)->protocol; 185 header_cnt += 2; 186 break; 187 case htons(ETH_P_IPV6): 188 header |= PKT_OFFLOAD_HDR_SIZE_2((IP6_HLEN >> 8) & 0xf); 189 header2 |= PKT_OFFLOAD_HDR2_SIZE_2(IP6_HLEN & 0xff); 190 epkt |= PKT_OFFLOAD_EPKT_IP(1) | PKT_OFFLOAD_EPKT_CSUM_L2; 191 ip_proto = ipv6_hdr(skb)->nexthdr; 192 header_cnt += 2; 193 break; 194 default: 195 goto help; 196 } 197 198 switch (ip_proto) { 199 case IPPROTO_TCP: 200 header2 |= PKT_OFFLOAD_HDR2_SIZE_3(tcp_hdrlen(skb)); 201 epkt |= PKT_OFFLOAD_EPKT_TP(0) | PKT_OFFLOAD_EPKT_CSUM_L3; 202 header_cnt++; 203 break; 204 case IPPROTO_UDP: 205 header2 |= PKT_OFFLOAD_HDR2_SIZE_3(UDP_HLEN); 206 epkt |= PKT_OFFLOAD_EPKT_TP(1) | PKT_OFFLOAD_EPKT_CSUM_L3; 207 header_cnt++; 208 break; 209 default: 210 goto help; 211 } 212 213 offload = (struct bcmasp_pkt_offload *)skb_push(skb, sizeof(*offload)); 214 215 header |= PKT_OFFLOAD_HDR_OP | PKT_OFFLOAD_HDR_COUNT(header_cnt) | 216 PKT_OFFLOAD_HDR_SIZE_1(ETH_HLEN); 217 epkt |= PKT_OFFLOAD_EPKT_OP; 218 219 offload->nop = htonl(PKT_OFFLOAD_NOP); 220 offload->header = htonl(header); 221 offload->header2 = htonl(header2); 222 offload->epkt = htonl(epkt); 223 offload->end = htonl(PKT_OFFLOAD_END_OP); 224 *csum_hw = true; 225 226 return skb; 227 228 help: 229 skb_checksum_help(skb); 230 231 return skb; 232 } 233 234 static unsigned long bcmasp_rx_edpkt_dma_rq(struct bcmasp_intf *intf) 235 { 236 return rx_edpkt_dma_rq(intf, RX_EDPKT_DMA_VALID); 237 } 238 239 static void bcmasp_rx_edpkt_cfg_wq(struct bcmasp_intf *intf, dma_addr_t addr) 240 { 241 rx_edpkt_cfg_wq(intf, addr, RX_EDPKT_RING_BUFFER_READ); 242 } 243 244 static void bcmasp_rx_edpkt_dma_wq(struct bcmasp_intf *intf, dma_addr_t addr) 245 { 246 rx_edpkt_dma_wq(intf, addr, RX_EDPKT_DMA_READ); 247 } 248 249 static unsigned long bcmasp_tx_spb_dma_rq(struct bcmasp_intf *intf) 250 { 251 return tx_spb_dma_rq(intf, TX_SPB_DMA_READ); 252 } 253 254 static void bcmasp_tx_spb_dma_wq(struct bcmasp_intf *intf, dma_addr_t addr) 255 { 256 tx_spb_dma_wq(intf, addr, TX_SPB_DMA_VALID); 257 } 258 259 static const struct bcmasp_intf_ops bcmasp_intf_ops = { 260 .rx_desc_read = bcmasp_rx_edpkt_dma_rq, 261 .rx_buffer_write = bcmasp_rx_edpkt_cfg_wq, 262 .rx_desc_write = bcmasp_rx_edpkt_dma_wq, 263 .tx_read = bcmasp_tx_spb_dma_rq, 264 .tx_write = bcmasp_tx_spb_dma_wq, 265 }; 266 267 static netdev_tx_t bcmasp_xmit(struct sk_buff *skb, struct net_device *dev) 268 { 269 struct bcmasp_intf *intf = netdev_priv(dev); 270 unsigned int total_bytes, size; 271 int spb_index, nr_frags, i, j; 272 struct bcmasp_tx_cb *txcb; 273 dma_addr_t mapping, valid; 274 struct bcmasp_desc *desc; 275 bool csum_hw = false; 276 struct device *kdev; 277 skb_frag_t *frag; 278 279 kdev = &intf->parent->pdev->dev; 280 281 nr_frags = skb_shinfo(skb)->nr_frags; 282 283 if (tx_spb_ring_full(intf, nr_frags + 1)) { 284 netif_stop_queue(dev); 285 if (net_ratelimit()) 286 netdev_err(dev, "Tx Ring Full!\n"); 287 return NETDEV_TX_BUSY; 288 } 289 290 /* Save skb len before adding csum offload header */ 291 total_bytes = skb->len; 292 skb = bcmasp_csum_offload(dev, skb, &csum_hw); 293 if (!skb) 294 return NETDEV_TX_OK; 295 296 spb_index = intf->tx_spb_index; 297 valid = intf->tx_spb_dma_valid; 298 for (i = 0; i <= nr_frags; i++) { 299 if (!i) { 300 size = skb_headlen(skb); 301 if (!nr_frags && size < (ETH_ZLEN + ETH_FCS_LEN)) { 302 if (skb_put_padto(skb, ETH_ZLEN + ETH_FCS_LEN)) 303 return NETDEV_TX_OK; 304 size = skb->len; 305 } 306 mapping = dma_map_single(kdev, skb->data, size, 307 DMA_TO_DEVICE); 308 } else { 309 frag = &skb_shinfo(skb)->frags[i - 1]; 310 size = skb_frag_size(frag); 311 mapping = skb_frag_dma_map(kdev, frag, 0, size, 312 DMA_TO_DEVICE); 313 } 314 315 if (dma_mapping_error(kdev, mapping)) { 316 intf->mib.tx_dma_failed++; 317 spb_index = intf->tx_spb_index; 318 for (j = 0; j < i; j++) { 319 bcmasp_clean_txcb(intf, spb_index); 320 spb_index = incr_ring(spb_index, 321 DESC_RING_COUNT); 322 } 323 /* Rewind so we do not have a hole */ 324 spb_index = intf->tx_spb_index; 325 dev_kfree_skb(skb); 326 return NETDEV_TX_OK; 327 } 328 329 txcb = &intf->tx_cbs[spb_index]; 330 desc = &intf->tx_spb_cpu[spb_index]; 331 memset(desc, 0, sizeof(*desc)); 332 txcb->skb = skb; 333 txcb->bytes_sent = total_bytes; 334 dma_unmap_addr_set(txcb, dma_addr, mapping); 335 dma_unmap_len_set(txcb, dma_len, size); 336 if (!i) { 337 desc->flags |= DESC_SOF; 338 if (csum_hw) 339 desc->flags |= DESC_EPKT_CMD; 340 } 341 342 if (i == nr_frags) { 343 desc->flags |= DESC_EOF; 344 txcb->last = true; 345 } 346 347 desc->buf = mapping; 348 desc->size = size; 349 desc->flags |= DESC_INT_EN; 350 351 netif_dbg(intf, tx_queued, dev, 352 "%s dma_buf=%pad dma_len=0x%x flags=0x%x index=0x%x\n", 353 __func__, &mapping, desc->size, desc->flags, 354 spb_index); 355 356 spb_index = incr_ring(spb_index, DESC_RING_COUNT); 357 valid = incr_last_byte(valid, intf->tx_spb_dma_addr, 358 DESC_RING_COUNT); 359 } 360 361 /* Ensure all descriptors have been written to DRAM for the 362 * hardware to see up-to-date contents. 363 */ 364 wmb(); 365 366 intf->tx_spb_index = spb_index; 367 intf->tx_spb_dma_valid = valid; 368 bcmasp_intf_tx_write(intf, intf->tx_spb_dma_valid); 369 370 if (tx_spb_ring_full(intf, MAX_SKB_FRAGS + 1)) 371 netif_stop_queue(dev); 372 373 return NETDEV_TX_OK; 374 } 375 376 static void bcmasp_netif_start(struct net_device *dev) 377 { 378 struct bcmasp_intf *intf = netdev_priv(dev); 379 380 bcmasp_set_rx_mode(dev); 381 napi_enable(&intf->tx_napi); 382 napi_enable(&intf->rx_napi); 383 384 bcmasp_enable_rx_irq(intf, 1); 385 bcmasp_enable_tx_irq(intf, 1); 386 bcmasp_enable_phy_irq(intf, 1); 387 388 phy_start(dev->phydev); 389 } 390 391 static void umac_reset(struct bcmasp_intf *intf) 392 { 393 umac_wl(intf, 0x0, UMC_CMD); 394 umac_wl(intf, UMC_CMD_SW_RESET, UMC_CMD); 395 usleep_range(10, 100); 396 /* We hold the umac in reset and bring it out of 397 * reset when phy link is up. 398 */ 399 } 400 401 static void umac_set_hw_addr(struct bcmasp_intf *intf, 402 const unsigned char *addr) 403 { 404 u32 mac0 = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | 405 addr[3]; 406 u32 mac1 = (addr[4] << 8) | addr[5]; 407 408 umac_wl(intf, mac0, UMC_MAC0); 409 umac_wl(intf, mac1, UMC_MAC1); 410 } 411 412 static void umac_enable_set(struct bcmasp_intf *intf, u32 mask, 413 unsigned int enable) 414 { 415 u32 reg; 416 417 reg = umac_rl(intf, UMC_CMD); 418 if (reg & UMC_CMD_SW_RESET) 419 return; 420 if (enable) 421 reg |= mask; 422 else 423 reg &= ~mask; 424 umac_wl(intf, reg, UMC_CMD); 425 426 /* UniMAC stops on a packet boundary, wait for a full-sized packet 427 * to be processed (1 msec). 428 */ 429 if (enable == 0) 430 usleep_range(1000, 2000); 431 } 432 433 static void umac_init(struct bcmasp_intf *intf) 434 { 435 umac_wl(intf, 0x800, UMC_FRM_LEN); 436 umac_wl(intf, 0xffff, UMC_PAUSE_CNTRL); 437 umac_wl(intf, 0x800, UMC_RX_MAX_PKT_SZ); 438 } 439 440 static int bcmasp_tx_reclaim(struct bcmasp_intf *intf) 441 { 442 struct bcmasp_intf_stats64 *stats = &intf->stats64; 443 struct device *kdev = &intf->parent->pdev->dev; 444 unsigned long read, released = 0; 445 struct bcmasp_tx_cb *txcb; 446 struct bcmasp_desc *desc; 447 dma_addr_t mapping; 448 449 read = bcmasp_intf_tx_read(intf); 450 while (intf->tx_spb_dma_read != read) { 451 txcb = &intf->tx_cbs[intf->tx_spb_clean_index]; 452 mapping = dma_unmap_addr(txcb, dma_addr); 453 454 dma_unmap_single(kdev, mapping, 455 dma_unmap_len(txcb, dma_len), 456 DMA_TO_DEVICE); 457 458 if (txcb->last) { 459 dev_consume_skb_any(txcb->skb); 460 461 u64_stats_update_begin(&stats->syncp); 462 u64_stats_inc(&stats->tx_packets); 463 u64_stats_add(&stats->tx_bytes, txcb->bytes_sent); 464 u64_stats_update_end(&stats->syncp); 465 } 466 467 desc = &intf->tx_spb_cpu[intf->tx_spb_clean_index]; 468 469 netif_dbg(intf, tx_done, intf->ndev, 470 "%s dma_buf=%pad dma_len=0x%x flags=0x%x c_index=0x%x\n", 471 __func__, &mapping, desc->size, desc->flags, 472 intf->tx_spb_clean_index); 473 474 bcmasp_clean_txcb(intf, intf->tx_spb_clean_index); 475 released++; 476 477 intf->tx_spb_clean_index = incr_ring(intf->tx_spb_clean_index, 478 DESC_RING_COUNT); 479 intf->tx_spb_dma_read = incr_first_byte(intf->tx_spb_dma_read, 480 intf->tx_spb_dma_addr, 481 DESC_RING_COUNT); 482 } 483 484 return released; 485 } 486 487 static int bcmasp_tx_poll(struct napi_struct *napi, int budget) 488 { 489 struct bcmasp_intf *intf = 490 container_of(napi, struct bcmasp_intf, tx_napi); 491 int released = 0; 492 493 released = bcmasp_tx_reclaim(intf); 494 495 napi_complete(&intf->tx_napi); 496 497 bcmasp_enable_tx_irq(intf, 1); 498 499 if (released) 500 netif_wake_queue(intf->ndev); 501 502 return 0; 503 } 504 505 static int bcmasp_rx_poll(struct napi_struct *napi, int budget) 506 { 507 struct bcmasp_intf *intf = 508 container_of(napi, struct bcmasp_intf, rx_napi); 509 struct bcmasp_intf_stats64 *stats = &intf->stats64; 510 struct device *kdev = &intf->parent->pdev->dev; 511 unsigned long processed = 0; 512 struct bcmasp_desc *desc; 513 struct sk_buff *skb; 514 dma_addr_t valid; 515 void *data; 516 u64 flags; 517 u32 len; 518 519 valid = bcmasp_intf_rx_desc_read(intf) + 1; 520 if (valid == intf->rx_edpkt_dma_addr + DESC_RING_SIZE) 521 valid = intf->rx_edpkt_dma_addr; 522 523 while ((processed < budget) && (valid != intf->rx_edpkt_dma_read)) { 524 desc = &intf->rx_edpkt_cpu[intf->rx_edpkt_index]; 525 526 /* Ensure that descriptor has been fully written to DRAM by 527 * hardware before reading by the CPU 528 */ 529 rmb(); 530 531 /* Calculate virt addr by offsetting from physical addr */ 532 data = intf->rx_ring_cpu + 533 (DESC_ADDR(desc->buf) - intf->rx_ring_dma); 534 535 flags = DESC_FLAGS(desc->buf); 536 if (unlikely(flags & (DESC_CRC_ERR | DESC_RX_SYM_ERR))) { 537 if (net_ratelimit()) { 538 netif_err(intf, rx_status, intf->ndev, 539 "flags=0x%llx\n", flags); 540 } 541 542 u64_stats_update_begin(&stats->syncp); 543 if (flags & DESC_CRC_ERR) 544 u64_stats_inc(&stats->rx_crc_errs); 545 if (flags & DESC_RX_SYM_ERR) 546 u64_stats_inc(&stats->rx_sym_errs); 547 u64_stats_update_end(&stats->syncp); 548 549 goto next; 550 } 551 552 dma_sync_single_for_cpu(kdev, DESC_ADDR(desc->buf), desc->size, 553 DMA_FROM_DEVICE); 554 555 len = desc->size; 556 557 skb = napi_alloc_skb(napi, len); 558 if (!skb) { 559 u64_stats_update_begin(&stats->syncp); 560 u64_stats_inc(&stats->rx_dropped); 561 u64_stats_update_end(&stats->syncp); 562 intf->mib.alloc_rx_skb_failed++; 563 564 goto next; 565 } 566 567 skb_put(skb, len); 568 memcpy(skb->data, data, len); 569 570 skb_pull(skb, 2); 571 len -= 2; 572 if (likely(intf->crc_fwd)) { 573 skb_trim(skb, len - ETH_FCS_LEN); 574 len -= ETH_FCS_LEN; 575 } 576 577 if ((intf->ndev->features & NETIF_F_RXCSUM) && 578 (desc->buf & DESC_CHKSUM)) 579 skb->ip_summed = CHECKSUM_UNNECESSARY; 580 581 skb->protocol = eth_type_trans(skb, intf->ndev); 582 583 napi_gro_receive(napi, skb); 584 585 u64_stats_update_begin(&stats->syncp); 586 u64_stats_inc(&stats->rx_packets); 587 u64_stats_add(&stats->rx_bytes, len); 588 u64_stats_update_end(&stats->syncp); 589 590 next: 591 bcmasp_intf_rx_buffer_write(intf, (DESC_ADDR(desc->buf) + 592 desc->size)); 593 594 processed++; 595 intf->rx_edpkt_dma_read = 596 incr_first_byte(intf->rx_edpkt_dma_read, 597 intf->rx_edpkt_dma_addr, 598 DESC_RING_COUNT); 599 intf->rx_edpkt_index = incr_ring(intf->rx_edpkt_index, 600 DESC_RING_COUNT); 601 } 602 603 bcmasp_intf_rx_desc_write(intf, intf->rx_edpkt_dma_read); 604 605 if (processed < budget) { 606 napi_complete_done(&intf->rx_napi, processed); 607 bcmasp_enable_rx_irq(intf, 1); 608 } 609 610 return processed; 611 } 612 613 static void bcmasp_adj_link(struct net_device *dev) 614 { 615 struct bcmasp_intf *intf = netdev_priv(dev); 616 struct phy_device *phydev = dev->phydev; 617 u32 cmd_bits = 0, reg; 618 int changed = 0; 619 bool active; 620 621 if (intf->old_link != phydev->link) { 622 changed = 1; 623 intf->old_link = phydev->link; 624 } 625 626 if (intf->old_duplex != phydev->duplex) { 627 changed = 1; 628 intf->old_duplex = phydev->duplex; 629 } 630 631 switch (phydev->speed) { 632 case SPEED_2500: 633 cmd_bits = UMC_CMD_SPEED_2500; 634 break; 635 case SPEED_1000: 636 cmd_bits = UMC_CMD_SPEED_1000; 637 break; 638 case SPEED_100: 639 cmd_bits = UMC_CMD_SPEED_100; 640 break; 641 case SPEED_10: 642 cmd_bits = UMC_CMD_SPEED_10; 643 break; 644 default: 645 break; 646 } 647 cmd_bits <<= UMC_CMD_SPEED_SHIFT; 648 649 if (phydev->duplex == DUPLEX_HALF) 650 cmd_bits |= UMC_CMD_HD_EN; 651 652 if (intf->old_pause != phydev->pause) { 653 changed = 1; 654 intf->old_pause = phydev->pause; 655 } 656 657 if (!phydev->pause) 658 cmd_bits |= UMC_CMD_RX_PAUSE_IGNORE | UMC_CMD_TX_PAUSE_IGNORE; 659 660 if (!changed) 661 return; 662 663 if (phydev->link) { 664 reg = umac_rl(intf, UMC_CMD); 665 reg &= ~((UMC_CMD_SPEED_MASK << UMC_CMD_SPEED_SHIFT) | 666 UMC_CMD_HD_EN | UMC_CMD_RX_PAUSE_IGNORE | 667 UMC_CMD_TX_PAUSE_IGNORE); 668 reg |= cmd_bits; 669 if (reg & UMC_CMD_SW_RESET) { 670 reg &= ~UMC_CMD_SW_RESET; 671 umac_wl(intf, reg, UMC_CMD); 672 udelay(2); 673 reg |= UMC_CMD_TX_EN | UMC_CMD_RX_EN | UMC_CMD_PROMISC; 674 } 675 umac_wl(intf, reg, UMC_CMD); 676 677 active = phy_init_eee(phydev, 0) >= 0; 678 bcmasp_eee_enable_set(intf, active); 679 } 680 681 reg = rgmii_rl(intf, RGMII_OOB_CNTRL); 682 if (phydev->link) 683 reg |= RGMII_LINK; 684 else 685 reg &= ~RGMII_LINK; 686 rgmii_wl(intf, reg, RGMII_OOB_CNTRL); 687 688 if (changed) 689 phy_print_status(phydev); 690 } 691 692 static int bcmasp_alloc_buffers(struct bcmasp_intf *intf) 693 { 694 struct device *kdev = &intf->parent->pdev->dev; 695 struct page *buffer_pg; 696 697 /* Alloc RX */ 698 intf->rx_buf_order = get_order(RING_BUFFER_SIZE); 699 buffer_pg = alloc_pages(GFP_KERNEL, intf->rx_buf_order); 700 if (!buffer_pg) 701 return -ENOMEM; 702 703 intf->rx_ring_cpu = page_to_virt(buffer_pg); 704 intf->rx_ring_dma = dma_map_page(kdev, buffer_pg, 0, RING_BUFFER_SIZE, 705 DMA_FROM_DEVICE); 706 if (dma_mapping_error(kdev, intf->rx_ring_dma)) 707 goto free_rx_buffer; 708 709 intf->rx_edpkt_cpu = dma_alloc_coherent(kdev, DESC_RING_SIZE, 710 &intf->rx_edpkt_dma_addr, GFP_KERNEL); 711 if (!intf->rx_edpkt_cpu) 712 goto free_rx_buffer_dma; 713 714 /* Alloc TX */ 715 intf->tx_spb_cpu = dma_alloc_coherent(kdev, DESC_RING_SIZE, 716 &intf->tx_spb_dma_addr, GFP_KERNEL); 717 if (!intf->tx_spb_cpu) 718 goto free_rx_edpkt_dma; 719 720 intf->tx_cbs = kcalloc(DESC_RING_COUNT, sizeof(struct bcmasp_tx_cb), 721 GFP_KERNEL); 722 if (!intf->tx_cbs) 723 goto free_tx_spb_dma; 724 725 return 0; 726 727 free_tx_spb_dma: 728 dma_free_coherent(kdev, DESC_RING_SIZE, intf->tx_spb_cpu, 729 intf->tx_spb_dma_addr); 730 free_rx_edpkt_dma: 731 dma_free_coherent(kdev, DESC_RING_SIZE, intf->rx_edpkt_cpu, 732 intf->rx_edpkt_dma_addr); 733 free_rx_buffer_dma: 734 dma_unmap_page(kdev, intf->rx_ring_dma, RING_BUFFER_SIZE, 735 DMA_FROM_DEVICE); 736 free_rx_buffer: 737 __free_pages(buffer_pg, intf->rx_buf_order); 738 739 return -ENOMEM; 740 } 741 742 static void bcmasp_reclaim_free_buffers(struct bcmasp_intf *intf) 743 { 744 struct device *kdev = &intf->parent->pdev->dev; 745 746 /* RX buffers */ 747 dma_free_coherent(kdev, DESC_RING_SIZE, intf->rx_edpkt_cpu, 748 intf->rx_edpkt_dma_addr); 749 dma_unmap_page(kdev, intf->rx_ring_dma, RING_BUFFER_SIZE, 750 DMA_FROM_DEVICE); 751 __free_pages(virt_to_page(intf->rx_ring_cpu), intf->rx_buf_order); 752 753 /* TX buffers */ 754 dma_free_coherent(kdev, DESC_RING_SIZE, intf->tx_spb_cpu, 755 intf->tx_spb_dma_addr); 756 kfree(intf->tx_cbs); 757 } 758 759 static void bcmasp_init_rx(struct bcmasp_intf *intf) 760 { 761 /* Restart from index 0 */ 762 intf->rx_ring_dma_valid = intf->rx_ring_dma + RING_BUFFER_SIZE - 1; 763 intf->rx_edpkt_dma_valid = intf->rx_edpkt_dma_addr + (DESC_RING_SIZE - 1); 764 intf->rx_edpkt_dma_read = intf->rx_edpkt_dma_addr; 765 intf->rx_edpkt_index = 0; 766 767 /* Make sure channels are disabled */ 768 rx_edpkt_cfg_wl(intf, 0x0, RX_EDPKT_CFG_ENABLE); 769 770 /* Rx SPB */ 771 rx_edpkt_cfg_wq(intf, intf->rx_ring_dma, RX_EDPKT_RING_BUFFER_READ); 772 rx_edpkt_cfg_wq(intf, intf->rx_ring_dma, RX_EDPKT_RING_BUFFER_WRITE); 773 rx_edpkt_cfg_wq(intf, intf->rx_ring_dma, RX_EDPKT_RING_BUFFER_BASE); 774 rx_edpkt_cfg_wq(intf, intf->rx_ring_dma_valid, 775 RX_EDPKT_RING_BUFFER_END); 776 rx_edpkt_cfg_wq(intf, intf->rx_ring_dma_valid, 777 RX_EDPKT_RING_BUFFER_VALID); 778 779 /* EDPKT */ 780 rx_edpkt_cfg_wl(intf, (RX_EDPKT_CFG_CFG0_RBUF_4K << 781 RX_EDPKT_CFG_CFG0_DBUF_SHIFT) | 782 (RX_EDPKT_CFG_CFG0_64_ALN << 783 RX_EDPKT_CFG_CFG0_BALN_SHIFT) | 784 (RX_EDPKT_CFG_CFG0_EFRM_STUF), 785 RX_EDPKT_CFG_CFG0); 786 rx_edpkt_dma_wq(intf, intf->rx_edpkt_dma_addr, RX_EDPKT_DMA_WRITE); 787 rx_edpkt_dma_wq(intf, intf->rx_edpkt_dma_addr, RX_EDPKT_DMA_READ); 788 rx_edpkt_dma_wq(intf, intf->rx_edpkt_dma_addr, RX_EDPKT_DMA_BASE); 789 rx_edpkt_dma_wq(intf, intf->rx_edpkt_dma_valid, RX_EDPKT_DMA_END); 790 rx_edpkt_dma_wq(intf, intf->rx_edpkt_dma_valid, RX_EDPKT_DMA_VALID); 791 792 umac2fb_wl(intf, UMAC2FB_CFG_DEFAULT_EN | ((intf->channel + 11) << 793 UMAC2FB_CFG_CHID_SHIFT) | (0xd << UMAC2FB_CFG_OK_SEND_SHIFT), 794 UMAC2FB_CFG); 795 } 796 797 798 static void bcmasp_init_tx(struct bcmasp_intf *intf) 799 { 800 /* Restart from index 0 */ 801 intf->tx_spb_dma_valid = intf->tx_spb_dma_addr + DESC_RING_SIZE - 1; 802 intf->tx_spb_dma_read = intf->tx_spb_dma_addr; 803 intf->tx_spb_index = 0; 804 intf->tx_spb_clean_index = 0; 805 memset(intf->tx_cbs, 0, sizeof(struct bcmasp_tx_cb) * DESC_RING_COUNT); 806 807 /* Make sure channels are disabled */ 808 tx_spb_ctrl_wl(intf, 0x0, TX_SPB_CTRL_ENABLE); 809 tx_epkt_core_wl(intf, 0x0, TX_EPKT_C_CFG_MISC); 810 811 /* Tx SPB */ 812 tx_spb_ctrl_wl(intf, ((intf->channel + 8) << TX_SPB_CTRL_XF_BID_SHIFT), 813 TX_SPB_CTRL_XF_CTRL2); 814 tx_pause_ctrl_wl(intf, (1 << (intf->channel + 8)), TX_PAUSE_MAP_VECTOR); 815 tx_spb_top_wl(intf, 0x1e, TX_SPB_TOP_BLKOUT); 816 tx_spb_top_wl(intf, 0x0, TX_SPB_TOP_SPRE_BW_CTRL); 817 818 tx_spb_dma_wq(intf, intf->tx_spb_dma_addr, TX_SPB_DMA_READ); 819 tx_spb_dma_wq(intf, intf->tx_spb_dma_addr, TX_SPB_DMA_BASE); 820 tx_spb_dma_wq(intf, intf->tx_spb_dma_valid, TX_SPB_DMA_END); 821 tx_spb_dma_wq(intf, intf->tx_spb_dma_valid, TX_SPB_DMA_VALID); 822 } 823 824 static void bcmasp_ephy_enable_set(struct bcmasp_intf *intf, bool enable) 825 { 826 u32 mask = RGMII_EPHY_CFG_IDDQ_BIAS | RGMII_EPHY_CFG_EXT_PWRDOWN | 827 RGMII_EPHY_CFG_IDDQ_GLOBAL; 828 u32 reg; 829 830 reg = rgmii_rl(intf, RGMII_EPHY_CNTRL); 831 if (enable) { 832 reg &= ~RGMII_EPHY_CK25_DIS; 833 rgmii_wl(intf, reg, RGMII_EPHY_CNTRL); 834 mdelay(1); 835 836 reg &= ~mask; 837 reg |= RGMII_EPHY_RESET; 838 rgmii_wl(intf, reg, RGMII_EPHY_CNTRL); 839 mdelay(1); 840 841 reg &= ~RGMII_EPHY_RESET; 842 } else { 843 reg |= mask | RGMII_EPHY_RESET; 844 rgmii_wl(intf, reg, RGMII_EPHY_CNTRL); 845 mdelay(1); 846 reg |= RGMII_EPHY_CK25_DIS; 847 } 848 rgmii_wl(intf, reg, RGMII_EPHY_CNTRL); 849 mdelay(1); 850 851 /* Set or clear the LED control override to avoid lighting up LEDs 852 * while the EPHY is powered off and drawing unnecessary current. 853 */ 854 reg = rgmii_rl(intf, RGMII_SYS_LED_CNTRL); 855 if (enable) 856 reg &= ~RGMII_SYS_LED_CNTRL_LINK_OVRD; 857 else 858 reg |= RGMII_SYS_LED_CNTRL_LINK_OVRD; 859 rgmii_wl(intf, reg, RGMII_SYS_LED_CNTRL); 860 } 861 862 static void bcmasp_rgmii_mode_en_set(struct bcmasp_intf *intf, bool enable) 863 { 864 u32 reg; 865 866 reg = rgmii_rl(intf, RGMII_OOB_CNTRL); 867 reg &= ~RGMII_OOB_DIS; 868 if (enable) 869 reg |= RGMII_MODE_EN; 870 else 871 reg &= ~RGMII_MODE_EN; 872 rgmii_wl(intf, reg, RGMII_OOB_CNTRL); 873 } 874 875 static void bcmasp_netif_deinit(struct net_device *dev) 876 { 877 struct bcmasp_intf *intf = netdev_priv(dev); 878 u32 reg, timeout = 1000; 879 880 napi_disable(&intf->tx_napi); 881 882 bcmasp_enable_tx(intf, 0); 883 884 /* Flush any TX packets in the pipe */ 885 tx_spb_dma_wl(intf, TX_SPB_DMA_FIFO_FLUSH, TX_SPB_DMA_FIFO_CTRL); 886 do { 887 reg = tx_spb_dma_rl(intf, TX_SPB_DMA_FIFO_STATUS); 888 if (!(reg & TX_SPB_DMA_FIFO_FLUSH)) 889 break; 890 usleep_range(1000, 2000); 891 } while (timeout-- > 0); 892 tx_spb_dma_wl(intf, 0x0, TX_SPB_DMA_FIFO_CTRL); 893 894 bcmasp_tx_reclaim(intf); 895 896 umac_enable_set(intf, UMC_CMD_TX_EN, 0); 897 898 phy_stop(dev->phydev); 899 900 umac_enable_set(intf, UMC_CMD_RX_EN, 0); 901 902 bcmasp_flush_rx_port(intf); 903 usleep_range(1000, 2000); 904 bcmasp_enable_rx(intf, 0); 905 906 napi_disable(&intf->rx_napi); 907 908 /* Disable interrupts */ 909 bcmasp_enable_tx_irq(intf, 0); 910 bcmasp_enable_rx_irq(intf, 0); 911 bcmasp_enable_phy_irq(intf, 0); 912 913 netif_napi_del(&intf->tx_napi); 914 netif_napi_del(&intf->rx_napi); 915 } 916 917 static int bcmasp_stop(struct net_device *dev) 918 { 919 struct bcmasp_intf *intf = netdev_priv(dev); 920 921 netif_dbg(intf, ifdown, dev, "bcmasp stop\n"); 922 923 /* Stop tx from updating HW */ 924 netif_tx_disable(dev); 925 926 bcmasp_netif_deinit(dev); 927 928 bcmasp_reclaim_free_buffers(intf); 929 930 phy_disconnect(dev->phydev); 931 932 /* Disable internal EPHY or external PHY */ 933 if (intf->internal_phy) 934 bcmasp_ephy_enable_set(intf, false); 935 else 936 bcmasp_rgmii_mode_en_set(intf, false); 937 938 /* Disable the interface clocks */ 939 bcmasp_core_clock_set_intf(intf, false); 940 941 clk_disable_unprepare(intf->parent->clk); 942 943 return 0; 944 } 945 946 static void bcmasp_configure_port(struct bcmasp_intf *intf) 947 { 948 u32 reg, id_mode_dis = 0; 949 950 reg = rgmii_rl(intf, RGMII_PORT_CNTRL); 951 reg &= ~RGMII_PORT_MODE_MASK; 952 953 switch (intf->phy_interface) { 954 case PHY_INTERFACE_MODE_RGMII: 955 /* RGMII_NO_ID: TXC transitions at the same time as TXD 956 * (requires PCB or receiver-side delay) 957 * RGMII: Add 2ns delay on TXC (90 degree shift) 958 * 959 * ID is implicitly disabled for 100Mbps (RG)MII operation. 960 */ 961 id_mode_dis = RGMII_ID_MODE_DIS; 962 fallthrough; 963 case PHY_INTERFACE_MODE_RGMII_TXID: 964 reg |= RGMII_PORT_MODE_EXT_GPHY; 965 break; 966 case PHY_INTERFACE_MODE_MII: 967 reg |= RGMII_PORT_MODE_EXT_EPHY; 968 break; 969 default: 970 break; 971 } 972 973 if (intf->internal_phy) 974 reg |= RGMII_PORT_MODE_EPHY; 975 976 rgmii_wl(intf, reg, RGMII_PORT_CNTRL); 977 978 reg = rgmii_rl(intf, RGMII_OOB_CNTRL); 979 reg &= ~RGMII_ID_MODE_DIS; 980 reg |= id_mode_dis; 981 rgmii_wl(intf, reg, RGMII_OOB_CNTRL); 982 } 983 984 static int bcmasp_netif_init(struct net_device *dev, bool phy_connect) 985 { 986 struct bcmasp_intf *intf = netdev_priv(dev); 987 phy_interface_t phy_iface = intf->phy_interface; 988 u32 phy_flags = PHY_BRCM_AUTO_PWRDWN_ENABLE | 989 PHY_BRCM_DIS_TXCRXC_NOENRGY | 990 PHY_BRCM_IDDQ_SUSPEND; 991 struct phy_device *phydev = NULL; 992 int ret; 993 994 /* Always enable interface clocks */ 995 bcmasp_core_clock_set_intf(intf, true); 996 997 /* Enable internal PHY or external PHY before any MAC activity */ 998 if (intf->internal_phy) 999 bcmasp_ephy_enable_set(intf, true); 1000 else 1001 bcmasp_rgmii_mode_en_set(intf, true); 1002 bcmasp_configure_port(intf); 1003 1004 /* This is an ugly quirk but we have not been correctly 1005 * interpreting the phy_interface values and we have done that 1006 * across different drivers, so at least we are consistent in 1007 * our mistakes. 1008 * 1009 * When the Generic PHY driver is in use either the PHY has 1010 * been strapped or programmed correctly by the boot loader so 1011 * we should stick to our incorrect interpretation since we 1012 * have validated it. 1013 * 1014 * Now when a dedicated PHY driver is in use, we need to 1015 * reverse the meaning of the phy_interface_mode values to 1016 * something that the PHY driver will interpret and act on such 1017 * that we have two mistakes canceling themselves so to speak. 1018 * We only do this for the two modes that GENET driver 1019 * officially supports on Broadcom STB chips: 1020 * PHY_INTERFACE_MODE_RGMII and PHY_INTERFACE_MODE_RGMII_TXID. 1021 * Other modes are not *officially* supported with the boot 1022 * loader and the scripted environment generating Device Tree 1023 * blobs for those platforms. 1024 * 1025 * Note that internal PHY and fixed-link configurations are not 1026 * affected because they use different phy_interface_t values 1027 * or the Generic PHY driver. 1028 */ 1029 switch (phy_iface) { 1030 case PHY_INTERFACE_MODE_RGMII: 1031 phy_iface = PHY_INTERFACE_MODE_RGMII_ID; 1032 break; 1033 case PHY_INTERFACE_MODE_RGMII_TXID: 1034 phy_iface = PHY_INTERFACE_MODE_RGMII_RXID; 1035 break; 1036 default: 1037 break; 1038 } 1039 1040 if (phy_connect) { 1041 phydev = of_phy_connect(dev, intf->phy_dn, 1042 bcmasp_adj_link, phy_flags, 1043 phy_iface); 1044 if (!phydev) { 1045 ret = -ENODEV; 1046 netdev_err(dev, "could not attach to PHY\n"); 1047 goto err_phy_disable; 1048 } 1049 1050 if (intf->internal_phy) 1051 dev->phydev->irq = PHY_MAC_INTERRUPT; 1052 1053 /* Indicate that the MAC is responsible for PHY PM */ 1054 phydev->mac_managed_pm = true; 1055 } 1056 1057 umac_reset(intf); 1058 1059 umac_init(intf); 1060 1061 umac_set_hw_addr(intf, dev->dev_addr); 1062 1063 intf->old_duplex = -1; 1064 intf->old_link = -1; 1065 intf->old_pause = -1; 1066 1067 bcmasp_init_tx(intf); 1068 netif_napi_add_tx(intf->ndev, &intf->tx_napi, bcmasp_tx_poll); 1069 bcmasp_enable_tx(intf, 1); 1070 1071 bcmasp_init_rx(intf); 1072 netif_napi_add(intf->ndev, &intf->rx_napi, bcmasp_rx_poll); 1073 bcmasp_enable_rx(intf, 1); 1074 1075 intf->crc_fwd = !!(umac_rl(intf, UMC_CMD) & UMC_CMD_CRC_FWD); 1076 1077 bcmasp_netif_start(dev); 1078 1079 netif_start_queue(dev); 1080 1081 return 0; 1082 1083 err_phy_disable: 1084 if (intf->internal_phy) 1085 bcmasp_ephy_enable_set(intf, false); 1086 else 1087 bcmasp_rgmii_mode_en_set(intf, false); 1088 return ret; 1089 } 1090 1091 static int bcmasp_open(struct net_device *dev) 1092 { 1093 struct bcmasp_intf *intf = netdev_priv(dev); 1094 int ret; 1095 1096 netif_dbg(intf, ifup, dev, "bcmasp open\n"); 1097 1098 ret = bcmasp_alloc_buffers(intf); 1099 if (ret) 1100 return ret; 1101 1102 ret = clk_prepare_enable(intf->parent->clk); 1103 if (ret) 1104 goto err_free_mem; 1105 1106 ret = bcmasp_netif_init(dev, true); 1107 if (ret) { 1108 clk_disable_unprepare(intf->parent->clk); 1109 goto err_free_mem; 1110 } 1111 1112 return ret; 1113 1114 err_free_mem: 1115 bcmasp_reclaim_free_buffers(intf); 1116 1117 return ret; 1118 } 1119 1120 static void bcmasp_tx_timeout(struct net_device *dev, unsigned int txqueue) 1121 { 1122 struct bcmasp_intf *intf = netdev_priv(dev); 1123 1124 netif_dbg(intf, tx_err, dev, "transmit timeout!\n"); 1125 intf->mib.tx_timeout_cnt++; 1126 } 1127 1128 static int bcmasp_get_phys_port_name(struct net_device *dev, 1129 char *name, size_t len) 1130 { 1131 struct bcmasp_intf *intf = netdev_priv(dev); 1132 1133 if (snprintf(name, len, "p%d", intf->port) >= len) 1134 return -EINVAL; 1135 1136 return 0; 1137 } 1138 1139 static void bcmasp_get_stats64(struct net_device *dev, 1140 struct rtnl_link_stats64 *stats) 1141 { 1142 struct bcmasp_intf *intf = netdev_priv(dev); 1143 struct bcmasp_intf_stats64 *lstats; 1144 unsigned int start; 1145 1146 lstats = &intf->stats64; 1147 1148 do { 1149 start = u64_stats_fetch_begin(&lstats->syncp); 1150 stats->rx_packets = u64_stats_read(&lstats->rx_packets); 1151 stats->rx_bytes = u64_stats_read(&lstats->rx_bytes); 1152 stats->rx_dropped = u64_stats_read(&lstats->rx_dropped); 1153 stats->rx_crc_errors = u64_stats_read(&lstats->rx_crc_errs); 1154 stats->rx_frame_errors = u64_stats_read(&lstats->rx_sym_errs); 1155 stats->rx_errors = stats->rx_crc_errors + stats->rx_frame_errors; 1156 1157 stats->tx_packets = u64_stats_read(&lstats->tx_packets); 1158 stats->tx_bytes = u64_stats_read(&lstats->tx_bytes); 1159 } while (u64_stats_fetch_retry(&lstats->syncp, start)); 1160 } 1161 1162 static const struct net_device_ops bcmasp_netdev_ops = { 1163 .ndo_open = bcmasp_open, 1164 .ndo_stop = bcmasp_stop, 1165 .ndo_start_xmit = bcmasp_xmit, 1166 .ndo_tx_timeout = bcmasp_tx_timeout, 1167 .ndo_set_rx_mode = bcmasp_set_rx_mode, 1168 .ndo_get_phys_port_name = bcmasp_get_phys_port_name, 1169 .ndo_eth_ioctl = phy_do_ioctl_running, 1170 .ndo_set_mac_address = eth_mac_addr, 1171 .ndo_get_stats64 = bcmasp_get_stats64, 1172 }; 1173 1174 static void bcmasp_map_res(struct bcmasp_priv *priv, struct bcmasp_intf *intf) 1175 { 1176 /* Per port */ 1177 intf->res.umac = priv->base + UMC_OFFSET(intf); 1178 intf->res.umac2fb = priv->base + (priv->hw_info->umac2fb + 1179 (intf->port * 0x4)); 1180 intf->res.rgmii = priv->base + RGMII_OFFSET(intf); 1181 1182 /* Per ch */ 1183 intf->tx_spb_dma = priv->base + TX_SPB_DMA_OFFSET(intf); 1184 intf->res.tx_spb_ctrl = priv->base + TX_SPB_CTRL_OFFSET(intf); 1185 intf->res.tx_spb_top = priv->base + TX_SPB_TOP_OFFSET(intf); 1186 intf->res.tx_epkt_core = priv->base + TX_EPKT_C_OFFSET(intf); 1187 intf->res.tx_pause_ctrl = priv->base + TX_PAUSE_CTRL_OFFSET(intf); 1188 1189 intf->rx_edpkt_dma = priv->base + RX_EDPKT_DMA_OFFSET(intf); 1190 intf->rx_edpkt_cfg = priv->base + RX_EDPKT_CFG_OFFSET(intf); 1191 } 1192 1193 #define MAX_IRQ_STR_LEN 64 1194 struct bcmasp_intf *bcmasp_interface_create(struct bcmasp_priv *priv, 1195 struct device_node *ndev_dn, int i) 1196 { 1197 struct device *dev = &priv->pdev->dev; 1198 struct bcmasp_intf *intf; 1199 struct net_device *ndev; 1200 int ch, port, ret; 1201 1202 if (of_property_read_u32(ndev_dn, "reg", &port)) { 1203 dev_warn(dev, "%s: invalid port number\n", ndev_dn->name); 1204 goto err; 1205 } 1206 1207 if (of_property_read_u32(ndev_dn, "brcm,channel", &ch)) { 1208 dev_warn(dev, "%s: invalid ch number\n", ndev_dn->name); 1209 goto err; 1210 } 1211 1212 ndev = alloc_etherdev(sizeof(struct bcmasp_intf)); 1213 if (!ndev) { 1214 dev_warn(dev, "%s: unable to alloc ndev\n", ndev_dn->name); 1215 goto err; 1216 } 1217 intf = netdev_priv(ndev); 1218 1219 intf->parent = priv; 1220 intf->ndev = ndev; 1221 intf->channel = ch; 1222 intf->port = port; 1223 intf->ndev_dn = ndev_dn; 1224 intf->index = i; 1225 1226 ret = of_get_phy_mode(ndev_dn, &intf->phy_interface); 1227 if (ret < 0) { 1228 dev_err(dev, "invalid PHY mode property\n"); 1229 goto err_free_netdev; 1230 } 1231 1232 if (intf->phy_interface == PHY_INTERFACE_MODE_INTERNAL) 1233 intf->internal_phy = true; 1234 1235 intf->phy_dn = of_parse_phandle(ndev_dn, "phy-handle", 0); 1236 if (!intf->phy_dn && of_phy_is_fixed_link(ndev_dn)) { 1237 ret = of_phy_register_fixed_link(ndev_dn); 1238 if (ret) { 1239 dev_warn(dev, "%s: failed to register fixed PHY\n", 1240 ndev_dn->name); 1241 goto err_free_netdev; 1242 } 1243 intf->phy_dn = ndev_dn; 1244 } 1245 1246 /* Map resource */ 1247 bcmasp_map_res(priv, intf); 1248 1249 if ((!phy_interface_mode_is_rgmii(intf->phy_interface) && 1250 intf->phy_interface != PHY_INTERFACE_MODE_MII && 1251 intf->phy_interface != PHY_INTERFACE_MODE_INTERNAL) || 1252 (intf->port != 1 && intf->internal_phy)) { 1253 netdev_err(intf->ndev, "invalid PHY mode: %s for port %d\n", 1254 phy_modes(intf->phy_interface), intf->port); 1255 ret = -EINVAL; 1256 goto err_free_netdev; 1257 } 1258 1259 ret = of_get_ethdev_address(ndev_dn, ndev); 1260 if (ret) { 1261 netdev_warn(ndev, "using random Ethernet MAC\n"); 1262 eth_hw_addr_random(ndev); 1263 } 1264 1265 SET_NETDEV_DEV(ndev, dev); 1266 intf->ops = &bcmasp_intf_ops; 1267 ndev->netdev_ops = &bcmasp_netdev_ops; 1268 ndev->ethtool_ops = &bcmasp_ethtool_ops; 1269 intf->msg_enable = netif_msg_init(-1, NETIF_MSG_DRV | 1270 NETIF_MSG_PROBE | 1271 NETIF_MSG_LINK); 1272 ndev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | 1273 NETIF_F_RXCSUM; 1274 ndev->hw_features |= ndev->features; 1275 ndev->needed_headroom += sizeof(struct bcmasp_pkt_offload); 1276 1277 return intf; 1278 1279 err_free_netdev: 1280 free_netdev(ndev); 1281 err: 1282 return NULL; 1283 } 1284 1285 void bcmasp_interface_destroy(struct bcmasp_intf *intf) 1286 { 1287 if (intf->ndev->reg_state == NETREG_REGISTERED) 1288 unregister_netdev(intf->ndev); 1289 if (of_phy_is_fixed_link(intf->ndev_dn)) 1290 of_phy_deregister_fixed_link(intf->ndev_dn); 1291 free_netdev(intf->ndev); 1292 } 1293 1294 static void bcmasp_suspend_to_wol(struct bcmasp_intf *intf) 1295 { 1296 struct net_device *ndev = intf->ndev; 1297 u32 reg; 1298 1299 reg = umac_rl(intf, UMC_MPD_CTRL); 1300 if (intf->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE)) 1301 reg |= UMC_MPD_CTRL_MPD_EN; 1302 reg &= ~UMC_MPD_CTRL_PSW_EN; 1303 if (intf->wolopts & WAKE_MAGICSECURE) { 1304 /* Program the SecureOn password */ 1305 umac_wl(intf, get_unaligned_be16(&intf->sopass[0]), 1306 UMC_PSW_MS); 1307 umac_wl(intf, get_unaligned_be32(&intf->sopass[2]), 1308 UMC_PSW_LS); 1309 reg |= UMC_MPD_CTRL_PSW_EN; 1310 } 1311 umac_wl(intf, reg, UMC_MPD_CTRL); 1312 1313 if (intf->wolopts & WAKE_FILTER) 1314 bcmasp_netfilt_suspend(intf); 1315 1316 /* Bring UniMAC out of reset if needed and enable RX */ 1317 reg = umac_rl(intf, UMC_CMD); 1318 if (reg & UMC_CMD_SW_RESET) 1319 reg &= ~UMC_CMD_SW_RESET; 1320 1321 reg |= UMC_CMD_RX_EN | UMC_CMD_PROMISC; 1322 umac_wl(intf, reg, UMC_CMD); 1323 1324 umac_enable_set(intf, UMC_CMD_RX_EN, 1); 1325 1326 if (intf->parent->wol_irq > 0) { 1327 wakeup_intr2_core_wl(intf->parent, 0xffffffff, 1328 ASP_WAKEUP_INTR2_MASK_CLEAR); 1329 } 1330 1331 if (intf->eee.eee_enabled && intf->parent->eee_fixup) 1332 intf->parent->eee_fixup(intf, true); 1333 1334 netif_dbg(intf, wol, ndev, "entered WOL mode\n"); 1335 } 1336 1337 int bcmasp_interface_suspend(struct bcmasp_intf *intf) 1338 { 1339 struct device *kdev = &intf->parent->pdev->dev; 1340 struct net_device *dev = intf->ndev; 1341 1342 if (!netif_running(dev)) 1343 return 0; 1344 1345 netif_device_detach(dev); 1346 1347 bcmasp_netif_deinit(dev); 1348 1349 if (!intf->wolopts) { 1350 if (intf->internal_phy) 1351 bcmasp_ephy_enable_set(intf, false); 1352 else 1353 bcmasp_rgmii_mode_en_set(intf, false); 1354 1355 /* If Wake-on-LAN is disabled, we can safely 1356 * disable the network interface clocks. 1357 */ 1358 bcmasp_core_clock_set_intf(intf, false); 1359 } 1360 1361 if (device_may_wakeup(kdev) && intf->wolopts) 1362 bcmasp_suspend_to_wol(intf); 1363 1364 clk_disable_unprepare(intf->parent->clk); 1365 1366 return 0; 1367 } 1368 1369 static void bcmasp_resume_from_wol(struct bcmasp_intf *intf) 1370 { 1371 u32 reg; 1372 1373 if (intf->eee.eee_enabled && intf->parent->eee_fixup) 1374 intf->parent->eee_fixup(intf, false); 1375 1376 reg = umac_rl(intf, UMC_MPD_CTRL); 1377 reg &= ~UMC_MPD_CTRL_MPD_EN; 1378 umac_wl(intf, reg, UMC_MPD_CTRL); 1379 1380 if (intf->parent->wol_irq > 0) { 1381 wakeup_intr2_core_wl(intf->parent, 0xffffffff, 1382 ASP_WAKEUP_INTR2_MASK_SET); 1383 } 1384 } 1385 1386 int bcmasp_interface_resume(struct bcmasp_intf *intf) 1387 { 1388 struct net_device *dev = intf->ndev; 1389 int ret; 1390 1391 if (!netif_running(dev)) 1392 return 0; 1393 1394 ret = clk_prepare_enable(intf->parent->clk); 1395 if (ret) 1396 return ret; 1397 1398 ret = bcmasp_netif_init(dev, false); 1399 if (ret) 1400 goto out; 1401 1402 bcmasp_resume_from_wol(intf); 1403 1404 if (intf->eee.eee_enabled) 1405 bcmasp_eee_enable_set(intf, true); 1406 1407 netif_device_attach(dev); 1408 1409 return 0; 1410 1411 out: 1412 clk_disable_unprepare(intf->parent->clk); 1413 return ret; 1414 } 1415