1 // SPDX-License-Identifier: GPL-2.0 2 #define pr_fmt(fmt) "bcmasp_intf: " fmt 3 4 #include <asm/byteorder.h> 5 #include <linux/brcmphy.h> 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/etherdevice.h> 9 #include <linux/netdevice.h> 10 #include <linux/of_net.h> 11 #include <linux/of_mdio.h> 12 #include <linux/phy.h> 13 #include <linux/phy_fixed.h> 14 #include <linux/ptp_classify.h> 15 #include <linux/platform_device.h> 16 #include <net/ip.h> 17 #include <net/ipv6.h> 18 #include <net/page_pool/helpers.h> 19 20 #include "bcmasp.h" 21 #include "bcmasp_intf_defs.h" 22 23 static int incr_ring(int index, int ring_count) 24 { 25 index++; 26 if (index == ring_count) 27 return 0; 28 29 return index; 30 } 31 32 /* Points to last byte of descriptor */ 33 static dma_addr_t incr_last_byte(dma_addr_t addr, dma_addr_t beg, 34 int ring_count) 35 { 36 dma_addr_t end = beg + (ring_count * DESC_SIZE); 37 38 addr += DESC_SIZE; 39 if (addr > end) 40 return beg + DESC_SIZE - 1; 41 42 return addr; 43 } 44 45 /* Points to first byte of descriptor */ 46 static dma_addr_t incr_first_byte(dma_addr_t addr, dma_addr_t beg, 47 int ring_count) 48 { 49 dma_addr_t end = beg + (ring_count * DESC_SIZE); 50 51 addr += DESC_SIZE; 52 if (addr >= end) 53 return beg; 54 55 return addr; 56 } 57 58 static void bcmasp_enable_tx(struct bcmasp_intf *intf, int en) 59 { 60 if (en) { 61 tx_spb_ctrl_wl(intf, TX_SPB_CTRL_ENABLE_EN, TX_SPB_CTRL_ENABLE); 62 tx_epkt_core_wl(intf, (TX_EPKT_C_CFG_MISC_EN | 63 TX_EPKT_C_CFG_MISC_PT | 64 (intf->port << TX_EPKT_C_CFG_MISC_PS_SHIFT)), 65 TX_EPKT_C_CFG_MISC); 66 } else { 67 tx_spb_ctrl_wl(intf, 0x0, TX_SPB_CTRL_ENABLE); 68 tx_epkt_core_wl(intf, 0x0, TX_EPKT_C_CFG_MISC); 69 } 70 } 71 72 static void bcmasp_enable_rx(struct bcmasp_intf *intf, int en) 73 { 74 if (en) 75 rx_edpkt_cfg_wl(intf, RX_EDPKT_CFG_ENABLE_EN, 76 RX_EDPKT_CFG_ENABLE); 77 else 78 rx_edpkt_cfg_wl(intf, 0x0, RX_EDPKT_CFG_ENABLE); 79 } 80 81 static void bcmasp_set_rx_mode(struct net_device *dev) 82 { 83 unsigned char mask[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 84 struct bcmasp_intf *intf = netdev_priv(dev); 85 struct netdev_hw_addr *ha; 86 int ret; 87 88 spin_lock_bh(&intf->parent->mda_lock); 89 90 bcmasp_disable_all_filters(intf); 91 92 if (dev->flags & IFF_PROMISC) 93 goto set_promisc; 94 95 bcmasp_set_promisc(intf, 0); 96 97 bcmasp_set_broad(intf, 1); 98 99 bcmasp_set_oaddr(intf, dev->dev_addr, 1); 100 101 if (dev->flags & IFF_ALLMULTI) { 102 bcmasp_set_allmulti(intf, 1); 103 } else { 104 bcmasp_set_allmulti(intf, 0); 105 106 netdev_for_each_mc_addr(ha, dev) { 107 ret = bcmasp_set_en_mda_filter(intf, ha->addr, mask); 108 if (ret) { 109 intf->mib.mc_filters_full_cnt++; 110 goto set_promisc; 111 } 112 } 113 } 114 115 netdev_for_each_uc_addr(ha, dev) { 116 ret = bcmasp_set_en_mda_filter(intf, ha->addr, mask); 117 if (ret) { 118 intf->mib.uc_filters_full_cnt++; 119 goto set_promisc; 120 } 121 } 122 123 spin_unlock_bh(&intf->parent->mda_lock); 124 return; 125 126 set_promisc: 127 bcmasp_set_promisc(intf, 1); 128 intf->mib.promisc_filters_cnt++; 129 130 /* disable all filters used by this port */ 131 bcmasp_disable_all_filters(intf); 132 133 spin_unlock_bh(&intf->parent->mda_lock); 134 } 135 136 static void bcmasp_clean_txcb(struct bcmasp_intf *intf, int index) 137 { 138 struct bcmasp_tx_cb *txcb = &intf->tx_cbs[index]; 139 140 txcb->skb = NULL; 141 dma_unmap_addr_set(txcb, dma_addr, 0); 142 dma_unmap_len_set(txcb, dma_len, 0); 143 txcb->last = false; 144 } 145 146 static int tx_spb_ring_full(struct bcmasp_intf *intf, int cnt) 147 { 148 int next_index, i; 149 150 /* Check if we have enough room for cnt descriptors */ 151 for (i = 0; i < cnt; i++) { 152 next_index = incr_ring(intf->tx_spb_index, DESC_RING_COUNT); 153 if (next_index == intf->tx_spb_clean_index) 154 return 1; 155 } 156 157 return 0; 158 } 159 160 static struct sk_buff *bcmasp_csum_offload(struct net_device *dev, 161 struct sk_buff *skb, 162 bool *csum_hw) 163 { 164 struct bcmasp_intf *intf = netdev_priv(dev); 165 u32 header = 0, header2 = 0, epkt = 0; 166 struct bcmasp_pkt_offload *offload; 167 unsigned int header_cnt = 0; 168 u8 ip_proto; 169 int ret; 170 171 if (skb->ip_summed != CHECKSUM_PARTIAL) 172 return skb; 173 174 ret = skb_cow_head(skb, sizeof(*offload)); 175 if (ret < 0) { 176 intf->mib.tx_realloc_offload_failed++; 177 goto help; 178 } 179 180 switch (skb->protocol) { 181 case htons(ETH_P_IP): 182 header |= PKT_OFFLOAD_HDR_SIZE_2((ip_hdrlen(skb) >> 8) & 0xf); 183 header2 |= PKT_OFFLOAD_HDR2_SIZE_2(ip_hdrlen(skb) & 0xff); 184 epkt |= PKT_OFFLOAD_EPKT_IP(0); 185 ip_proto = ip_hdr(skb)->protocol; 186 header_cnt += 2; 187 break; 188 case htons(ETH_P_IPV6): 189 header |= PKT_OFFLOAD_HDR_SIZE_2((IP6_HLEN >> 8) & 0xf); 190 header2 |= PKT_OFFLOAD_HDR2_SIZE_2(IP6_HLEN & 0xff); 191 epkt |= PKT_OFFLOAD_EPKT_IP(1); 192 ip_proto = ipv6_hdr(skb)->nexthdr; 193 header_cnt += 2; 194 break; 195 default: 196 goto help; 197 } 198 199 switch (ip_proto) { 200 case IPPROTO_TCP: 201 header2 |= PKT_OFFLOAD_HDR2_SIZE_3(tcp_hdrlen(skb)); 202 epkt |= PKT_OFFLOAD_EPKT_TP(0) | PKT_OFFLOAD_EPKT_CSUM_L4; 203 header_cnt++; 204 break; 205 case IPPROTO_UDP: 206 header2 |= PKT_OFFLOAD_HDR2_SIZE_3(UDP_HLEN); 207 epkt |= PKT_OFFLOAD_EPKT_TP(1) | PKT_OFFLOAD_EPKT_CSUM_L4; 208 header_cnt++; 209 break; 210 default: 211 goto help; 212 } 213 214 offload = (struct bcmasp_pkt_offload *)skb_push(skb, sizeof(*offload)); 215 216 header |= PKT_OFFLOAD_HDR_OP | PKT_OFFLOAD_HDR_COUNT(header_cnt) | 217 PKT_OFFLOAD_HDR_SIZE_1(ETH_HLEN); 218 epkt |= PKT_OFFLOAD_EPKT_OP; 219 220 offload->nop = htonl(PKT_OFFLOAD_NOP); 221 offload->header = htonl(header); 222 offload->header2 = htonl(header2); 223 offload->epkt = htonl(epkt); 224 offload->end = htonl(PKT_OFFLOAD_END_OP); 225 *csum_hw = true; 226 227 return skb; 228 229 help: 230 skb_checksum_help(skb); 231 232 return skb; 233 } 234 235 static netdev_tx_t bcmasp_xmit(struct sk_buff *skb, struct net_device *dev) 236 { 237 struct bcmasp_intf *intf = netdev_priv(dev); 238 unsigned int total_bytes, size; 239 int spb_index, nr_frags, i, j; 240 struct bcmasp_tx_cb *txcb; 241 dma_addr_t mapping, valid; 242 struct bcmasp_desc *desc; 243 bool csum_hw = false; 244 struct device *kdev; 245 skb_frag_t *frag; 246 247 kdev = &intf->parent->pdev->dev; 248 249 nr_frags = skb_shinfo(skb)->nr_frags; 250 251 if (tx_spb_ring_full(intf, nr_frags + 1)) { 252 netif_stop_queue(dev); 253 if (net_ratelimit()) 254 netdev_err(dev, "Tx Ring Full!\n"); 255 return NETDEV_TX_BUSY; 256 } 257 258 /* Save skb len before adding csum offload header */ 259 total_bytes = skb->len; 260 skb = bcmasp_csum_offload(dev, skb, &csum_hw); 261 if (!skb) 262 return NETDEV_TX_OK; 263 264 spb_index = intf->tx_spb_index; 265 valid = intf->tx_spb_dma_valid; 266 for (i = 0; i <= nr_frags; i++) { 267 if (!i) { 268 size = skb_headlen(skb); 269 if (!nr_frags && size < (ETH_ZLEN + ETH_FCS_LEN)) { 270 if (skb_put_padto(skb, ETH_ZLEN + ETH_FCS_LEN)) 271 return NETDEV_TX_OK; 272 size = skb->len; 273 } 274 mapping = dma_map_single(kdev, skb->data, size, 275 DMA_TO_DEVICE); 276 } else { 277 frag = &skb_shinfo(skb)->frags[i - 1]; 278 size = skb_frag_size(frag); 279 mapping = skb_frag_dma_map(kdev, frag, 0, size, 280 DMA_TO_DEVICE); 281 } 282 283 if (dma_mapping_error(kdev, mapping)) { 284 intf->mib.tx_dma_failed++; 285 spb_index = intf->tx_spb_index; 286 for (j = 0; j < i; j++) { 287 bcmasp_clean_txcb(intf, spb_index); 288 spb_index = incr_ring(spb_index, 289 DESC_RING_COUNT); 290 } 291 /* Rewind so we do not have a hole */ 292 spb_index = intf->tx_spb_index; 293 dev_kfree_skb(skb); 294 return NETDEV_TX_OK; 295 } 296 297 txcb = &intf->tx_cbs[spb_index]; 298 desc = &intf->tx_spb_cpu[spb_index]; 299 memset(desc, 0, sizeof(*desc)); 300 txcb->skb = skb; 301 txcb->bytes_sent = total_bytes; 302 dma_unmap_addr_set(txcb, dma_addr, mapping); 303 dma_unmap_len_set(txcb, dma_len, size); 304 if (!i) { 305 desc->flags |= DESC_SOF; 306 if (csum_hw) 307 desc->flags |= DESC_EPKT_CMD; 308 } 309 310 if (i == nr_frags) { 311 desc->flags |= DESC_EOF; 312 txcb->last = true; 313 } 314 315 desc->buf = mapping; 316 desc->size = size; 317 desc->flags |= DESC_INT_EN; 318 319 netif_dbg(intf, tx_queued, dev, 320 "%s dma_buf=%pad dma_len=0x%x flags=0x%x index=0x%x\n", 321 __func__, &mapping, desc->size, desc->flags, 322 spb_index); 323 324 spb_index = incr_ring(spb_index, DESC_RING_COUNT); 325 valid = incr_last_byte(valid, intf->tx_spb_dma_addr, 326 DESC_RING_COUNT); 327 } 328 329 /* Ensure all descriptors have been written to DRAM for the 330 * hardware to see up-to-date contents. 331 */ 332 wmb(); 333 334 intf->tx_spb_index = spb_index; 335 intf->tx_spb_dma_valid = valid; 336 337 skb_tx_timestamp(skb); 338 339 tx_spb_dma_wq(intf, intf->tx_spb_dma_valid, TX_SPB_DMA_VALID); 340 341 if (tx_spb_ring_full(intf, MAX_SKB_FRAGS + 1)) 342 netif_stop_queue(dev); 343 344 return NETDEV_TX_OK; 345 } 346 347 static void umac_reset_and_init(struct bcmasp_intf *intf, 348 const unsigned char *addr) 349 { 350 struct phy_device *phydev = intf->ndev->phydev; 351 u32 mac0, mac1; 352 353 umac_wl(intf, 0x0, UMC_CMD); 354 umac_wl(intf, UMC_CMD_SW_RESET, UMC_CMD); 355 usleep_range(10, 100); 356 /* We hold the umac in reset and bring it out of 357 * reset when phy link is up. 358 */ 359 360 umac_wl(intf, 0x800, UMC_FRM_LEN); 361 umac_wl(intf, 0xffff, UMC_PAUSE_CNTRL); 362 umac_wl(intf, 0x800, UMC_RX_MAX_PKT_SZ); 363 364 mac0 = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | 365 addr[3]; 366 mac1 = (addr[4] << 8) | addr[5]; 367 368 umac_wl(intf, mac0, UMC_MAC0); 369 umac_wl(intf, mac1, UMC_MAC1); 370 371 /* Reset shadow values since we reset the umac */ 372 intf->old_duplex = -1; 373 intf->old_link = -1; 374 intf->old_pause = -1; 375 phydev->eee_cfg.tx_lpi_timer = umac_rl(intf, UMC_EEE_LPI_TIMER); 376 } 377 378 static void umac_enable_set(struct bcmasp_intf *intf, u32 mask, 379 unsigned int enable) 380 { 381 u32 reg; 382 383 reg = umac_rl(intf, UMC_CMD); 384 if (reg & UMC_CMD_SW_RESET) 385 return; 386 if (enable) 387 reg |= mask; 388 else 389 reg &= ~mask; 390 umac_wl(intf, reg, UMC_CMD); 391 392 /* UniMAC stops on a packet boundary, wait for a full-sized packet 393 * to be processed (1 msec). 394 */ 395 if (enable == 0) 396 usleep_range(1000, 2000); 397 } 398 399 static int bcmasp_tx_reclaim(struct bcmasp_intf *intf) 400 { 401 struct bcmasp_intf_stats64 *stats = &intf->stats64; 402 struct device *kdev = &intf->parent->pdev->dev; 403 unsigned long read, released = 0; 404 struct bcmasp_tx_cb *txcb; 405 struct bcmasp_desc *desc; 406 dma_addr_t mapping; 407 408 read = tx_spb_dma_rq(intf, TX_SPB_DMA_READ); 409 while (intf->tx_spb_dma_read != read) { 410 txcb = &intf->tx_cbs[intf->tx_spb_clean_index]; 411 mapping = dma_unmap_addr(txcb, dma_addr); 412 413 dma_unmap_single(kdev, mapping, 414 dma_unmap_len(txcb, dma_len), 415 DMA_TO_DEVICE); 416 417 if (txcb->last) { 418 dev_consume_skb_any(txcb->skb); 419 420 u64_stats_update_begin(&stats->syncp); 421 u64_stats_inc(&stats->tx_packets); 422 u64_stats_add(&stats->tx_bytes, txcb->bytes_sent); 423 u64_stats_update_end(&stats->syncp); 424 } 425 426 desc = &intf->tx_spb_cpu[intf->tx_spb_clean_index]; 427 428 netif_dbg(intf, tx_done, intf->ndev, 429 "%s dma_buf=%pad dma_len=0x%x flags=0x%x c_index=0x%x\n", 430 __func__, &mapping, desc->size, desc->flags, 431 intf->tx_spb_clean_index); 432 433 bcmasp_clean_txcb(intf, intf->tx_spb_clean_index); 434 released++; 435 436 intf->tx_spb_clean_index = incr_ring(intf->tx_spb_clean_index, 437 DESC_RING_COUNT); 438 intf->tx_spb_dma_read = incr_first_byte(intf->tx_spb_dma_read, 439 intf->tx_spb_dma_addr, 440 DESC_RING_COUNT); 441 } 442 443 return released; 444 } 445 446 static int bcmasp_tx_poll(struct napi_struct *napi, int budget) 447 { 448 struct bcmasp_intf *intf = 449 container_of(napi, struct bcmasp_intf, tx_napi); 450 int released = 0; 451 452 released = bcmasp_tx_reclaim(intf); 453 454 napi_complete(&intf->tx_napi); 455 456 bcmasp_enable_tx_irq(intf, 1); 457 458 if (released) 459 netif_wake_queue(intf->ndev); 460 461 return 0; 462 } 463 464 static int bcmasp_rx_poll(struct napi_struct *napi, int budget) 465 { 466 struct bcmasp_intf *intf = 467 container_of(napi, struct bcmasp_intf, rx_napi); 468 struct bcmasp_intf_stats64 *stats = &intf->stats64; 469 struct device *kdev = &intf->parent->pdev->dev; 470 unsigned long processed = 0; 471 struct bcmasp_desc *desc; 472 struct sk_buff *skb; 473 dma_addr_t valid; 474 struct page *page; 475 void *data; 476 u64 flags; 477 u32 len; 478 479 /* Hardware advances DMA_VALID as it writes each descriptor 480 * (RBUF_4K streaming mode); software chases with rx_edpkt_dma_read. 481 */ 482 valid = rx_edpkt_dma_rq(intf, RX_EDPKT_DMA_VALID) + 1; 483 if (valid == intf->rx_edpkt_dma_addr + DESC_RING_SIZE) 484 valid = intf->rx_edpkt_dma_addr; 485 486 while ((processed < budget) && (valid != intf->rx_edpkt_dma_read)) { 487 desc = &intf->rx_edpkt_cpu[intf->rx_edpkt_index]; 488 489 /* Ensure the descriptor has been fully written to DRAM by 490 * the hardware before the CPU reads it. 491 */ 492 rmb(); 493 494 /* Locate the packet data inside the streaming ring buffer. */ 495 data = intf->rx_ring_cpu + 496 (DESC_ADDR(desc->buf) - intf->rx_ring_dma); 497 498 flags = DESC_FLAGS(desc->buf); 499 if (unlikely(flags & (DESC_CRC_ERR | DESC_RX_SYM_ERR))) { 500 if (net_ratelimit()) { 501 netif_err(intf, rx_status, intf->ndev, 502 "flags=0x%llx\n", flags); 503 } 504 505 u64_stats_update_begin(&stats->syncp); 506 if (flags & DESC_CRC_ERR) 507 u64_stats_inc(&stats->rx_crc_errs); 508 if (flags & DESC_RX_SYM_ERR) 509 u64_stats_inc(&stats->rx_sym_errs); 510 u64_stats_update_end(&stats->syncp); 511 512 goto next; 513 } 514 515 dma_sync_single_for_cpu(kdev, DESC_ADDR(desc->buf), desc->size, 516 DMA_FROM_DEVICE); 517 518 len = desc->size; 519 520 /* Allocate a page pool page as the SKB data area so the 521 * kernel can recycle it efficiently after the packet is 522 * consumed, avoiding repeated slab allocations. 523 */ 524 page = page_pool_dev_alloc_pages(intf->rx_page_pool); 525 if (!page) { 526 u64_stats_update_begin(&stats->syncp); 527 u64_stats_inc(&stats->rx_dropped); 528 u64_stats_update_end(&stats->syncp); 529 intf->mib.alloc_rx_skb_failed++; 530 goto next; 531 } 532 533 skb = napi_build_skb(page_address(page), PAGE_SIZE); 534 if (!skb) { 535 u64_stats_update_begin(&stats->syncp); 536 u64_stats_inc(&stats->rx_dropped); 537 u64_stats_update_end(&stats->syncp); 538 intf->mib.alloc_rx_skb_failed++; 539 page_pool_recycle_direct(intf->rx_page_pool, page); 540 goto next; 541 } 542 543 /* Reserve headroom then copy the full descriptor payload 544 * (hardware prepends a 2-byte alignment pad at the start). 545 */ 546 skb_reserve(skb, NET_SKB_PAD); 547 skb_put(skb, len); 548 memcpy(skb->data, data, len); 549 skb_mark_for_recycle(skb); 550 551 /* Skip the 2-byte hardware alignment pad. */ 552 skb_pull(skb, 2); 553 len -= 2; 554 if (likely(intf->crc_fwd)) { 555 skb_trim(skb, len - ETH_FCS_LEN); 556 len -= ETH_FCS_LEN; 557 } 558 559 if ((intf->ndev->features & NETIF_F_RXCSUM) && 560 (desc->buf & DESC_CHKSUM)) 561 skb->ip_summed = CHECKSUM_UNNECESSARY; 562 563 skb->protocol = eth_type_trans(skb, intf->ndev); 564 565 napi_gro_receive(napi, skb); 566 567 u64_stats_update_begin(&stats->syncp); 568 u64_stats_inc(&stats->rx_packets); 569 u64_stats_add(&stats->rx_bytes, len); 570 u64_stats_update_end(&stats->syncp); 571 572 next: 573 /* Return this portion of the streaming ring buffer to HW. */ 574 rx_edpkt_cfg_wq(intf, (DESC_ADDR(desc->buf) + desc->size), 575 RX_EDPKT_RING_BUFFER_READ); 576 577 processed++; 578 intf->rx_edpkt_dma_read = 579 incr_first_byte(intf->rx_edpkt_dma_read, 580 intf->rx_edpkt_dma_addr, 581 DESC_RING_COUNT); 582 intf->rx_edpkt_index = incr_ring(intf->rx_edpkt_index, 583 DESC_RING_COUNT); 584 } 585 586 rx_edpkt_dma_wq(intf, intf->rx_edpkt_dma_read, RX_EDPKT_DMA_READ); 587 588 if (processed < budget && napi_complete_done(&intf->rx_napi, processed)) 589 bcmasp_enable_rx_irq(intf, 1); 590 591 return processed; 592 } 593 594 static void bcmasp_adj_link(struct net_device *dev) 595 { 596 struct bcmasp_intf *intf = netdev_priv(dev); 597 struct phy_device *phydev = dev->phydev; 598 u32 cmd_bits = 0, reg; 599 int changed = 0; 600 601 if (intf->old_link != phydev->link) { 602 changed = 1; 603 intf->old_link = phydev->link; 604 } 605 606 if (intf->old_duplex != phydev->duplex) { 607 changed = 1; 608 intf->old_duplex = phydev->duplex; 609 } 610 611 switch (phydev->speed) { 612 case SPEED_2500: 613 cmd_bits = UMC_CMD_SPEED_2500; 614 break; 615 case SPEED_1000: 616 cmd_bits = UMC_CMD_SPEED_1000; 617 break; 618 case SPEED_100: 619 cmd_bits = UMC_CMD_SPEED_100; 620 break; 621 case SPEED_10: 622 cmd_bits = UMC_CMD_SPEED_10; 623 break; 624 default: 625 break; 626 } 627 cmd_bits <<= UMC_CMD_SPEED_SHIFT; 628 629 if (phydev->duplex == DUPLEX_HALF) 630 cmd_bits |= UMC_CMD_HD_EN; 631 632 if (intf->old_pause != phydev->pause) { 633 changed = 1; 634 intf->old_pause = phydev->pause; 635 } 636 637 if (!phydev->pause) 638 cmd_bits |= UMC_CMD_RX_PAUSE_IGNORE | UMC_CMD_TX_PAUSE_IGNORE; 639 640 if (!changed) 641 return; 642 643 if (phydev->link) { 644 reg = umac_rl(intf, UMC_CMD); 645 reg &= ~((UMC_CMD_SPEED_MASK << UMC_CMD_SPEED_SHIFT) | 646 UMC_CMD_HD_EN | UMC_CMD_RX_PAUSE_IGNORE | 647 UMC_CMD_TX_PAUSE_IGNORE); 648 reg |= cmd_bits; 649 if (reg & UMC_CMD_SW_RESET) { 650 reg &= ~UMC_CMD_SW_RESET; 651 umac_wl(intf, reg, UMC_CMD); 652 udelay(2); 653 reg |= UMC_CMD_TX_EN | UMC_CMD_RX_EN | UMC_CMD_PROMISC; 654 } 655 umac_wl(intf, reg, UMC_CMD); 656 657 umac_wl(intf, phydev->eee_cfg.tx_lpi_timer, UMC_EEE_LPI_TIMER); 658 reg = umac_rl(intf, UMC_EEE_CTRL); 659 if (phydev->enable_tx_lpi) 660 reg |= EEE_EN; 661 else 662 reg &= ~EEE_EN; 663 umac_wl(intf, reg, UMC_EEE_CTRL); 664 } 665 666 reg = rgmii_rl(intf, RGMII_OOB_CNTRL); 667 if (phydev->link) 668 reg |= RGMII_LINK; 669 else 670 reg &= ~RGMII_LINK; 671 rgmii_wl(intf, reg, RGMII_OOB_CNTRL); 672 673 if (changed) 674 phy_print_status(phydev); 675 } 676 677 static struct page_pool * 678 bcmasp_rx_page_pool_create(struct bcmasp_intf *intf) 679 { 680 struct page_pool_params pp_params = { 681 .order = 0, 682 .flags = 0, 683 .pool_size = NUM_4K_BUFFERS, 684 .nid = NUMA_NO_NODE, 685 .dev = &intf->parent->pdev->dev, 686 .napi = &intf->rx_napi, 687 .netdev = intf->ndev, 688 .offset = 0, 689 .max_len = PAGE_SIZE, 690 }; 691 692 return page_pool_create(&pp_params); 693 } 694 695 static int bcmasp_alloc_rx_buffers(struct bcmasp_intf *intf) 696 { 697 struct device *kdev = &intf->parent->pdev->dev; 698 struct page *buffer_pg; 699 int ret; 700 701 /* Contiguous streaming ring that hardware writes packet data into. */ 702 intf->rx_buf_order = get_order(RING_BUFFER_SIZE); 703 buffer_pg = alloc_pages(GFP_KERNEL, intf->rx_buf_order); 704 if (!buffer_pg) 705 return -ENOMEM; 706 707 intf->rx_ring_cpu = page_to_virt(buffer_pg); 708 intf->rx_ring_dma = dma_map_page(kdev, buffer_pg, 0, RING_BUFFER_SIZE, 709 DMA_FROM_DEVICE); 710 if (dma_mapping_error(kdev, intf->rx_ring_dma)) { 711 ret = -ENOMEM; 712 goto free_ring_pages; 713 } 714 715 /* Page pool for SKB data areas (copy targets, not DMA buffers). */ 716 intf->rx_page_pool = bcmasp_rx_page_pool_create(intf); 717 if (IS_ERR(intf->rx_page_pool)) { 718 ret = PTR_ERR(intf->rx_page_pool); 719 intf->rx_page_pool = NULL; 720 goto free_ring_dma; 721 } 722 723 return 0; 724 725 free_ring_dma: 726 dma_unmap_page(kdev, intf->rx_ring_dma, RING_BUFFER_SIZE, 727 DMA_FROM_DEVICE); 728 free_ring_pages: 729 __free_pages(buffer_pg, intf->rx_buf_order); 730 return ret; 731 } 732 733 static void bcmasp_reclaim_rx_buffers(struct bcmasp_intf *intf) 734 { 735 struct device *kdev = &intf->parent->pdev->dev; 736 737 page_pool_destroy(intf->rx_page_pool); 738 intf->rx_page_pool = NULL; 739 dma_unmap_page(kdev, intf->rx_ring_dma, RING_BUFFER_SIZE, 740 DMA_FROM_DEVICE); 741 __free_pages(virt_to_page(intf->rx_ring_cpu), intf->rx_buf_order); 742 } 743 744 static int bcmasp_alloc_buffers(struct bcmasp_intf *intf) 745 { 746 struct device *kdev = &intf->parent->pdev->dev; 747 int ret; 748 749 /* Alloc RX */ 750 ret = bcmasp_alloc_rx_buffers(intf); 751 if (ret) 752 return ret; 753 754 intf->rx_edpkt_cpu = dma_alloc_coherent(kdev, DESC_RING_SIZE, 755 &intf->rx_edpkt_dma_addr, 756 GFP_KERNEL); 757 if (!intf->rx_edpkt_cpu) 758 goto free_rx_buffers; 759 760 /* Alloc TX */ 761 intf->tx_spb_cpu = dma_alloc_coherent(kdev, DESC_RING_SIZE, 762 &intf->tx_spb_dma_addr, GFP_KERNEL); 763 if (!intf->tx_spb_cpu) 764 goto free_rx_edpkt_dma; 765 766 intf->tx_cbs = kzalloc_objs(struct bcmasp_tx_cb, DESC_RING_COUNT); 767 if (!intf->tx_cbs) 768 goto free_tx_spb_dma; 769 770 return 0; 771 772 free_tx_spb_dma: 773 dma_free_coherent(kdev, DESC_RING_SIZE, intf->tx_spb_cpu, 774 intf->tx_spb_dma_addr); 775 free_rx_edpkt_dma: 776 dma_free_coherent(kdev, DESC_RING_SIZE, intf->rx_edpkt_cpu, 777 intf->rx_edpkt_dma_addr); 778 free_rx_buffers: 779 bcmasp_reclaim_rx_buffers(intf); 780 781 return -ENOMEM; 782 } 783 784 static void bcmasp_reclaim_free_buffers(struct bcmasp_intf *intf) 785 { 786 struct device *kdev = &intf->parent->pdev->dev; 787 788 /* RX buffers */ 789 dma_free_coherent(kdev, DESC_RING_SIZE, intf->rx_edpkt_cpu, 790 intf->rx_edpkt_dma_addr); 791 bcmasp_reclaim_rx_buffers(intf); 792 793 /* TX buffers */ 794 dma_free_coherent(kdev, DESC_RING_SIZE, intf->tx_spb_cpu, 795 intf->tx_spb_dma_addr); 796 kfree(intf->tx_cbs); 797 } 798 799 static void bcmasp_init_rx(struct bcmasp_intf *intf) 800 { 801 /* Restart from index 0 */ 802 intf->rx_ring_dma_valid = intf->rx_ring_dma + RING_BUFFER_SIZE - 1; 803 intf->rx_edpkt_dma_valid = intf->rx_edpkt_dma_addr + (DESC_RING_SIZE - 1); 804 intf->rx_edpkt_dma_read = intf->rx_edpkt_dma_addr; 805 intf->rx_edpkt_index = 0; 806 807 /* Make sure channels are disabled */ 808 rx_edpkt_cfg_wl(intf, 0x0, RX_EDPKT_CFG_ENABLE); 809 810 /* Streaming data ring: hardware writes raw packet bytes here. */ 811 rx_edpkt_cfg_wq(intf, intf->rx_ring_dma, RX_EDPKT_RING_BUFFER_READ); 812 rx_edpkt_cfg_wq(intf, intf->rx_ring_dma, RX_EDPKT_RING_BUFFER_WRITE); 813 rx_edpkt_cfg_wq(intf, intf->rx_ring_dma, RX_EDPKT_RING_BUFFER_BASE); 814 rx_edpkt_cfg_wq(intf, intf->rx_ring_dma_valid, 815 RX_EDPKT_RING_BUFFER_END); 816 rx_edpkt_cfg_wq(intf, intf->rx_ring_dma_valid, 817 RX_EDPKT_RING_BUFFER_VALID); 818 819 /* EDPKT descriptor ring: hardware fills descriptors pointing into 820 * the streaming ring buffer above (RBUF_4K mode). 821 */ 822 rx_edpkt_cfg_wl(intf, (RX_EDPKT_CFG_CFG0_RBUF_4K << 823 RX_EDPKT_CFG_CFG0_DBUF_SHIFT) | 824 (RX_EDPKT_CFG_CFG0_64_ALN << 825 RX_EDPKT_CFG_CFG0_BALN_SHIFT) | 826 (RX_EDPKT_CFG_CFG0_EFRM_STUF), 827 RX_EDPKT_CFG_CFG0); 828 rx_edpkt_dma_wq(intf, intf->rx_edpkt_dma_addr, RX_EDPKT_DMA_WRITE); 829 rx_edpkt_dma_wq(intf, intf->rx_edpkt_dma_addr, RX_EDPKT_DMA_READ); 830 rx_edpkt_dma_wq(intf, intf->rx_edpkt_dma_addr, RX_EDPKT_DMA_BASE); 831 rx_edpkt_dma_wq(intf, intf->rx_edpkt_dma_valid, RX_EDPKT_DMA_END); 832 rx_edpkt_dma_wq(intf, intf->rx_edpkt_dma_valid, RX_EDPKT_DMA_VALID); 833 834 umac2fb_wl(intf, UMAC2FB_CFG_DEFAULT_EN | ((intf->channel + 11) << 835 UMAC2FB_CFG_CHID_SHIFT) | (0xd << UMAC2FB_CFG_OK_SEND_SHIFT), 836 UMAC2FB_CFG); 837 } 838 839 840 static void bcmasp_init_tx(struct bcmasp_intf *intf) 841 { 842 /* Restart from index 0 */ 843 intf->tx_spb_dma_valid = intf->tx_spb_dma_addr + DESC_RING_SIZE - 1; 844 intf->tx_spb_dma_read = intf->tx_spb_dma_addr; 845 intf->tx_spb_index = 0; 846 intf->tx_spb_clean_index = 0; 847 memset(intf->tx_cbs, 0, sizeof(struct bcmasp_tx_cb) * DESC_RING_COUNT); 848 849 /* Make sure channels are disabled */ 850 tx_spb_ctrl_wl(intf, 0x0, TX_SPB_CTRL_ENABLE); 851 tx_epkt_core_wl(intf, 0x0, TX_EPKT_C_CFG_MISC); 852 853 /* Tx SPB */ 854 tx_spb_ctrl_wl(intf, ((intf->channel + 8) << TX_SPB_CTRL_XF_BID_SHIFT), 855 TX_SPB_CTRL_XF_CTRL2); 856 857 if (intf->parent->tx_chan_offset) 858 tx_pause_ctrl_wl(intf, (1 << (intf->channel + 8)), TX_PAUSE_MAP_VECTOR); 859 tx_spb_top_wl(intf, 0x1e, TX_SPB_TOP_BLKOUT); 860 861 tx_spb_dma_wq(intf, intf->tx_spb_dma_addr, TX_SPB_DMA_READ); 862 tx_spb_dma_wq(intf, intf->tx_spb_dma_addr, TX_SPB_DMA_BASE); 863 tx_spb_dma_wq(intf, intf->tx_spb_dma_valid, TX_SPB_DMA_END); 864 tx_spb_dma_wq(intf, intf->tx_spb_dma_valid, TX_SPB_DMA_VALID); 865 } 866 867 static void bcmasp_ephy_enable_set(struct bcmasp_intf *intf, bool enable) 868 { 869 u32 mask = RGMII_EPHY_CFG_IDDQ_BIAS | RGMII_EPHY_CFG_EXT_PWRDOWN | 870 RGMII_EPHY_CFG_IDDQ_GLOBAL; 871 u32 reg; 872 873 reg = rgmii_rl(intf, RGMII_EPHY_CNTRL); 874 if (enable) { 875 reg &= ~RGMII_EPHY_CK25_DIS; 876 rgmii_wl(intf, reg, RGMII_EPHY_CNTRL); 877 mdelay(1); 878 879 reg &= ~mask; 880 reg |= RGMII_EPHY_RESET; 881 rgmii_wl(intf, reg, RGMII_EPHY_CNTRL); 882 mdelay(1); 883 884 reg &= ~RGMII_EPHY_RESET; 885 } else { 886 reg |= mask | RGMII_EPHY_RESET; 887 rgmii_wl(intf, reg, RGMII_EPHY_CNTRL); 888 mdelay(1); 889 reg |= RGMII_EPHY_CK25_DIS; 890 } 891 rgmii_wl(intf, reg, RGMII_EPHY_CNTRL); 892 mdelay(1); 893 894 /* Set or clear the LED control override to avoid lighting up LEDs 895 * while the EPHY is powered off and drawing unnecessary current. 896 */ 897 reg = rgmii_rl(intf, RGMII_SYS_LED_CNTRL); 898 if (enable) 899 reg &= ~RGMII_SYS_LED_CNTRL_LINK_OVRD; 900 else 901 reg |= RGMII_SYS_LED_CNTRL_LINK_OVRD; 902 rgmii_wl(intf, reg, RGMII_SYS_LED_CNTRL); 903 } 904 905 static void bcmasp_rgmii_mode_en_set(struct bcmasp_intf *intf, bool enable) 906 { 907 u32 reg; 908 909 reg = rgmii_rl(intf, RGMII_OOB_CNTRL); 910 reg &= ~RGMII_OOB_DIS; 911 if (enable) 912 reg |= RGMII_MODE_EN; 913 else 914 reg &= ~RGMII_MODE_EN; 915 rgmii_wl(intf, reg, RGMII_OOB_CNTRL); 916 } 917 918 static void bcmasp_phy_hw_unprepare(struct bcmasp_intf *intf) 919 { 920 if (intf->internal_phy) 921 bcmasp_ephy_enable_set(intf, false); 922 else 923 bcmasp_rgmii_mode_en_set(intf, false); 924 } 925 926 static void bcmasp_netif_deinit(struct net_device *dev, bool stop_phy) 927 { 928 struct bcmasp_intf *intf = netdev_priv(dev); 929 u32 reg, timeout = 1000; 930 931 napi_disable(&intf->tx_napi); 932 933 bcmasp_enable_tx(intf, 0); 934 935 /* Flush any TX packets in the pipe */ 936 tx_spb_dma_wl(intf, TX_SPB_DMA_FIFO_FLUSH, TX_SPB_DMA_FIFO_CTRL); 937 do { 938 reg = tx_spb_dma_rl(intf, TX_SPB_DMA_FIFO_STATUS); 939 if (!(reg & TX_SPB_DMA_FIFO_FLUSH)) 940 break; 941 usleep_range(1000, 2000); 942 } while (timeout-- > 0); 943 tx_spb_dma_wl(intf, 0x0, TX_SPB_DMA_FIFO_CTRL); 944 945 bcmasp_tx_reclaim(intf); 946 947 umac_enable_set(intf, UMC_CMD_TX_EN, 0); 948 949 if (stop_phy) 950 phy_stop(dev->phydev); 951 952 umac_enable_set(intf, UMC_CMD_RX_EN, 0); 953 954 bcmasp_flush_rx_port(intf); 955 usleep_range(1000, 2000); 956 bcmasp_enable_rx(intf, 0); 957 958 napi_disable(&intf->rx_napi); 959 960 /* Disable interrupts */ 961 bcmasp_enable_tx_irq(intf, 0); 962 bcmasp_enable_rx_irq(intf, 0); 963 bcmasp_enable_phy_irq(intf, 0); 964 965 netif_napi_del(&intf->tx_napi); 966 netif_napi_del(&intf->rx_napi); 967 } 968 969 static int bcmasp_stop(struct net_device *dev) 970 { 971 struct bcmasp_intf *intf = netdev_priv(dev); 972 973 netif_dbg(intf, ifdown, dev, "bcmasp stop\n"); 974 975 /* Stop tx from updating HW */ 976 netif_tx_disable(dev); 977 978 bcmasp_netif_deinit(dev, true); 979 980 bcmasp_reclaim_free_buffers(intf); 981 982 phy_disconnect(dev->phydev); 983 984 bcmasp_phy_hw_unprepare(intf); 985 986 /* Disable the interface clocks */ 987 bcmasp_core_clock_set_intf(intf, false); 988 989 clk_disable_unprepare(intf->parent->clk); 990 991 return 0; 992 } 993 994 static void bcmasp_phy_hw_prepare(struct bcmasp_intf *intf) 995 { 996 u32 reg, id_mode_dis = 0; 997 998 if (intf->internal_phy) 999 bcmasp_ephy_enable_set(intf, true); 1000 else 1001 bcmasp_rgmii_mode_en_set(intf, true); 1002 1003 reg = rgmii_rl(intf, RGMII_PORT_CNTRL); 1004 reg &= ~RGMII_PORT_MODE_MASK; 1005 1006 switch (intf->phy_interface) { 1007 case PHY_INTERFACE_MODE_RGMII: 1008 /* RGMII_NO_ID: TXC transitions at the same time as TXD 1009 * (requires PCB or receiver-side delay) 1010 * RGMII: Add 2ns delay on TXC (90 degree shift) 1011 * 1012 * ID is implicitly disabled for 100Mbps (RG)MII operation. 1013 */ 1014 id_mode_dis = RGMII_ID_MODE_DIS; 1015 fallthrough; 1016 case PHY_INTERFACE_MODE_RGMII_TXID: 1017 reg |= RGMII_PORT_MODE_EXT_GPHY; 1018 break; 1019 case PHY_INTERFACE_MODE_MII: 1020 reg |= RGMII_PORT_MODE_EXT_EPHY; 1021 break; 1022 default: 1023 break; 1024 } 1025 1026 if (intf->internal_phy) 1027 reg |= RGMII_PORT_MODE_EPHY; 1028 1029 rgmii_wl(intf, reg, RGMII_PORT_CNTRL); 1030 1031 reg = rgmii_rl(intf, RGMII_OOB_CNTRL); 1032 reg &= ~RGMII_ID_MODE_DIS; 1033 reg |= id_mode_dis; 1034 rgmii_wl(intf, reg, RGMII_OOB_CNTRL); 1035 } 1036 1037 static phy_interface_t bcmasp_phy_iface_for_connect(phy_interface_t mode) 1038 { 1039 /* This is an ugly quirk but we have not been correctly 1040 * interpreting the phy_interface values and we have done that 1041 * across different drivers, so at least we are consistent in 1042 * our mistakes. 1043 * 1044 * When the Generic PHY driver is in use either the PHY has 1045 * been strapped or programmed correctly by the boot loader so 1046 * we should stick to our incorrect interpretation since we 1047 * have validated it. 1048 * 1049 * Now when a dedicated PHY driver is in use, we need to 1050 * reverse the meaning of the phy_interface_mode values to 1051 * something that the PHY driver will interpret and act on such 1052 * that we have two mistakes canceling themselves so to speak. 1053 * We only do this for the two modes that GENET driver 1054 * officially supports on Broadcom STB chips: 1055 * PHY_INTERFACE_MODE_RGMII and PHY_INTERFACE_MODE_RGMII_TXID. 1056 * Other modes are not *officially* supported with the boot 1057 * loader and the scripted environment generating Device Tree 1058 * blobs for those platforms. 1059 * 1060 * Note that internal PHY and fixed-link configurations are not 1061 * affected because they use different phy_interface_t values 1062 * or the Generic PHY driver. 1063 */ 1064 switch (mode) { 1065 case PHY_INTERFACE_MODE_RGMII: 1066 return PHY_INTERFACE_MODE_RGMII_ID; 1067 case PHY_INTERFACE_MODE_RGMII_TXID: 1068 return PHY_INTERFACE_MODE_RGMII_RXID; 1069 default: 1070 return mode; 1071 } 1072 } 1073 1074 static int bcmasp_phy_attach(struct bcmasp_intf *intf) 1075 { 1076 u32 phy_flags = PHY_BRCM_AUTO_PWRDWN_ENABLE | 1077 PHY_BRCM_DIS_TXCRXC_NOENRGY | 1078 PHY_BRCM_IDDQ_SUSPEND; 1079 struct phy_device *phydev; 1080 phy_interface_t phy_iface; 1081 1082 phy_iface = bcmasp_phy_iface_for_connect(intf->phy_interface); 1083 phydev = of_phy_connect(intf->ndev, intf->phy_dn, 1084 bcmasp_adj_link, phy_flags, 1085 phy_iface); 1086 if (!phydev) { 1087 netdev_err(intf->ndev, "could not attach to PHY\n"); 1088 return -ENODEV; 1089 } 1090 if (intf->internal_phy) 1091 intf->ndev->phydev->irq = PHY_MAC_INTERRUPT; 1092 1093 phydev->mac_managed_pm = true; 1094 1095 return 0; 1096 } 1097 1098 static void bcmasp_netif_init(struct net_device *dev) 1099 { 1100 struct bcmasp_intf *intf = netdev_priv(dev); 1101 1102 bcmasp_init_tx(intf); 1103 netif_napi_add_tx(intf->ndev, &intf->tx_napi, bcmasp_tx_poll); 1104 bcmasp_enable_tx(intf, 1); 1105 1106 bcmasp_init_rx(intf); 1107 netif_napi_add(intf->ndev, &intf->rx_napi, bcmasp_rx_poll); 1108 bcmasp_enable_rx(intf, 1); 1109 1110 intf->crc_fwd = !!(umac_rl(intf, UMC_CMD) & UMC_CMD_CRC_FWD); 1111 1112 bcmasp_set_rx_mode(dev); 1113 napi_enable(&intf->tx_napi); 1114 napi_enable(&intf->rx_napi); 1115 1116 bcmasp_enable_rx_irq(intf, 1); 1117 bcmasp_enable_tx_irq(intf, 1); 1118 bcmasp_enable_phy_irq(intf, 1); 1119 } 1120 1121 static int bcmasp_open(struct net_device *dev) 1122 { 1123 struct bcmasp_intf *intf = netdev_priv(dev); 1124 int ret; 1125 1126 netif_dbg(intf, ifup, dev, "bcmasp open\n"); 1127 1128 ret = bcmasp_alloc_buffers(intf); 1129 if (ret) 1130 return ret; 1131 1132 ret = clk_prepare_enable(intf->parent->clk); 1133 if (ret) 1134 goto err_free_mem; 1135 1136 bcmasp_core_clock_set_intf(intf, true); 1137 1138 bcmasp_phy_hw_prepare(intf); 1139 1140 ret = bcmasp_phy_attach(intf); 1141 if (ret) 1142 goto err_phy_attach; 1143 1144 umac_reset_and_init(intf, dev->dev_addr); 1145 1146 dev->phydev->eee_cfg.tx_lpi_timer = umac_rl(intf, UMC_EEE_LPI_TIMER); 1147 1148 bcmasp_netif_init(dev); 1149 1150 phy_start(dev->phydev); 1151 1152 netif_start_queue(dev); 1153 1154 return ret; 1155 1156 err_phy_attach: 1157 bcmasp_phy_hw_unprepare(intf); 1158 bcmasp_core_clock_set_intf(intf, false); 1159 clk_disable_unprepare(intf->parent->clk); 1160 err_free_mem: 1161 bcmasp_reclaim_free_buffers(intf); 1162 1163 return ret; 1164 } 1165 1166 static void bcmasp_tx_timeout(struct net_device *dev, unsigned int txqueue) 1167 { 1168 struct bcmasp_intf *intf = netdev_priv(dev); 1169 1170 netif_dbg(intf, tx_err, dev, "transmit timeout!\n"); 1171 intf->mib.tx_timeout_cnt++; 1172 } 1173 1174 static int bcmasp_get_phys_port_name(struct net_device *dev, 1175 char *name, size_t len) 1176 { 1177 struct bcmasp_intf *intf = netdev_priv(dev); 1178 1179 if (snprintf(name, len, "p%d", intf->port) >= len) 1180 return -EINVAL; 1181 1182 return 0; 1183 } 1184 1185 static void bcmasp_get_stats64(struct net_device *dev, 1186 struct rtnl_link_stats64 *stats) 1187 { 1188 struct bcmasp_intf *intf = netdev_priv(dev); 1189 struct bcmasp_intf_stats64 *lstats; 1190 unsigned int start; 1191 1192 lstats = &intf->stats64; 1193 1194 do { 1195 start = u64_stats_fetch_begin(&lstats->syncp); 1196 stats->rx_packets = u64_stats_read(&lstats->rx_packets); 1197 stats->rx_bytes = u64_stats_read(&lstats->rx_bytes); 1198 stats->rx_dropped = u64_stats_read(&lstats->rx_dropped); 1199 stats->rx_crc_errors = u64_stats_read(&lstats->rx_crc_errs); 1200 stats->rx_frame_errors = u64_stats_read(&lstats->rx_sym_errs); 1201 stats->rx_errors = stats->rx_crc_errors + stats->rx_frame_errors; 1202 1203 stats->tx_packets = u64_stats_read(&lstats->tx_packets); 1204 stats->tx_bytes = u64_stats_read(&lstats->tx_bytes); 1205 } while (u64_stats_fetch_retry(&lstats->syncp, start)); 1206 } 1207 1208 static const struct net_device_ops bcmasp_netdev_ops = { 1209 .ndo_open = bcmasp_open, 1210 .ndo_stop = bcmasp_stop, 1211 .ndo_start_xmit = bcmasp_xmit, 1212 .ndo_tx_timeout = bcmasp_tx_timeout, 1213 .ndo_set_rx_mode = bcmasp_set_rx_mode, 1214 .ndo_get_phys_port_name = bcmasp_get_phys_port_name, 1215 .ndo_eth_ioctl = phy_do_ioctl_running, 1216 .ndo_set_mac_address = eth_mac_addr, 1217 .ndo_get_stats64 = bcmasp_get_stats64, 1218 }; 1219 1220 static void bcmasp_map_res(struct bcmasp_priv *priv, struct bcmasp_intf *intf) 1221 { 1222 /* Per port */ 1223 intf->res.umac = priv->base + UMC_OFFSET(intf); 1224 intf->res.umac2fb = priv->base + (UMAC2FB_OFFSET + priv->rx_ctrl_offset + 1225 (intf->port * 0x4)); 1226 intf->res.rgmii = priv->base + RGMII_OFFSET(intf); 1227 1228 /* Per ch */ 1229 intf->tx_spb_dma = priv->base + TX_SPB_DMA_OFFSET(intf); 1230 intf->res.tx_spb_ctrl = priv->base + TX_SPB_CTRL_OFFSET(intf); 1231 intf->res.tx_spb_top = priv->base + TX_SPB_TOP_OFFSET(intf); 1232 intf->res.tx_epkt_core = priv->base + TX_EPKT_C_OFFSET(intf); 1233 intf->res.tx_pause_ctrl = priv->base + TX_PAUSE_CTRL_OFFSET(intf); 1234 1235 intf->rx_edpkt_dma = priv->base + RX_EDPKT_DMA_OFFSET(intf); 1236 intf->rx_edpkt_cfg = priv->base + RX_EDPKT_CFG_OFFSET(intf); 1237 } 1238 1239 struct bcmasp_intf *bcmasp_interface_create(struct bcmasp_priv *priv, 1240 struct device_node *ndev_dn, int i) 1241 { 1242 struct device *dev = &priv->pdev->dev; 1243 struct bcmasp_intf *intf; 1244 struct net_device *ndev; 1245 int ch, port, ret; 1246 1247 if (of_property_read_u32(ndev_dn, "reg", &port)) { 1248 dev_warn(dev, "%s: invalid port number\n", ndev_dn->name); 1249 goto err; 1250 } 1251 1252 if (of_property_read_u32(ndev_dn, "brcm,channel", &ch)) { 1253 dev_warn(dev, "%s: invalid ch number\n", ndev_dn->name); 1254 goto err; 1255 } 1256 1257 ndev = alloc_etherdev(sizeof(struct bcmasp_intf)); 1258 if (!ndev) { 1259 dev_warn(dev, "%s: unable to alloc ndev\n", ndev_dn->name); 1260 goto err; 1261 } 1262 intf = netdev_priv(ndev); 1263 1264 intf->parent = priv; 1265 intf->ndev = ndev; 1266 intf->channel = ch; 1267 intf->port = port; 1268 intf->ndev_dn = ndev_dn; 1269 intf->index = i; 1270 1271 ret = of_get_phy_mode(ndev_dn, &intf->phy_interface); 1272 if (ret < 0) { 1273 dev_err(dev, "invalid PHY mode property\n"); 1274 goto err_free_netdev; 1275 } 1276 1277 if (intf->phy_interface == PHY_INTERFACE_MODE_INTERNAL) 1278 intf->internal_phy = true; 1279 1280 intf->phy_dn = of_parse_phandle(ndev_dn, "phy-handle", 0); 1281 if (!intf->phy_dn && of_phy_is_fixed_link(ndev_dn)) { 1282 ret = of_phy_register_fixed_link(ndev_dn); 1283 if (ret) { 1284 dev_warn(dev, "%s: failed to register fixed PHY\n", 1285 ndev_dn->name); 1286 goto err_free_netdev; 1287 } 1288 intf->phy_dn = ndev_dn; 1289 } 1290 1291 /* Map resource */ 1292 bcmasp_map_res(priv, intf); 1293 1294 if ((!phy_interface_mode_is_rgmii(intf->phy_interface) && 1295 intf->phy_interface != PHY_INTERFACE_MODE_MII && 1296 intf->phy_interface != PHY_INTERFACE_MODE_INTERNAL) || 1297 (intf->port != 1 && intf->internal_phy)) { 1298 netdev_err(intf->ndev, "invalid PHY mode: %s for port %d\n", 1299 phy_modes(intf->phy_interface), intf->port); 1300 ret = -EINVAL; 1301 goto err_deregister_fixed_link; 1302 } 1303 1304 ret = of_get_ethdev_address(ndev_dn, ndev); 1305 if (ret) { 1306 netdev_warn(ndev, "using random Ethernet MAC\n"); 1307 eth_hw_addr_random(ndev); 1308 } 1309 1310 SET_NETDEV_DEV(ndev, dev); 1311 ndev->netdev_ops = &bcmasp_netdev_ops; 1312 ndev->ethtool_ops = &bcmasp_ethtool_ops; 1313 intf->msg_enable = netif_msg_init(-1, NETIF_MSG_DRV | 1314 NETIF_MSG_PROBE | 1315 NETIF_MSG_LINK); 1316 ndev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | 1317 NETIF_F_RXCSUM; 1318 ndev->hw_features |= ndev->features; 1319 ndev->needed_headroom += sizeof(struct bcmasp_pkt_offload); 1320 1321 netdev_sw_irq_coalesce_default_on(ndev); 1322 1323 return intf; 1324 1325 err_deregister_fixed_link: 1326 if (of_phy_is_fixed_link(ndev_dn)) 1327 of_phy_deregister_fixed_link(ndev_dn); 1328 err_free_netdev: 1329 free_netdev(ndev); 1330 err: 1331 return NULL; 1332 } 1333 1334 void bcmasp_interface_destroy(struct bcmasp_intf *intf) 1335 { 1336 if (intf->ndev->reg_state == NETREG_REGISTERED) 1337 unregister_netdev(intf->ndev); 1338 if (of_phy_is_fixed_link(intf->ndev_dn)) 1339 of_phy_deregister_fixed_link(intf->ndev_dn); 1340 free_netdev(intf->ndev); 1341 } 1342 1343 static void bcmasp_suspend_to_wol(struct bcmasp_intf *intf) 1344 { 1345 struct net_device *ndev = intf->ndev; 1346 u32 reg; 1347 1348 reg = umac_rl(intf, UMC_MPD_CTRL); 1349 if (intf->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE)) 1350 reg |= UMC_MPD_CTRL_MPD_EN; 1351 reg &= ~UMC_MPD_CTRL_PSW_EN; 1352 if (intf->wolopts & WAKE_MAGICSECURE) { 1353 /* Program the SecureOn password */ 1354 umac_wl(intf, get_unaligned_be16(&intf->sopass[0]), 1355 UMC_PSW_MS); 1356 umac_wl(intf, get_unaligned_be32(&intf->sopass[2]), 1357 UMC_PSW_LS); 1358 reg |= UMC_MPD_CTRL_PSW_EN; 1359 } 1360 umac_wl(intf, reg, UMC_MPD_CTRL); 1361 1362 if (intf->wolopts & WAKE_FILTER) 1363 bcmasp_netfilt_suspend(intf); 1364 1365 /* Bring UniMAC out of reset if needed and enable RX */ 1366 reg = umac_rl(intf, UMC_CMD); 1367 if (reg & UMC_CMD_SW_RESET) 1368 reg &= ~UMC_CMD_SW_RESET; 1369 1370 reg |= UMC_CMD_RX_EN | UMC_CMD_PROMISC; 1371 umac_wl(intf, reg, UMC_CMD); 1372 1373 umac_enable_set(intf, UMC_CMD_RX_EN, 1); 1374 1375 wakeup_intr2_core_wl(intf->parent, 0xffffffff, 1376 ASP_WAKEUP_INTR2_MASK_CLEAR); 1377 1378 if (ndev->phydev && ndev->phydev->eee_cfg.eee_enabled && 1379 intf->parent->eee_fixup) 1380 intf->parent->eee_fixup(intf, true); 1381 1382 netif_dbg(intf, wol, ndev, "entered WOL mode\n"); 1383 } 1384 1385 int bcmasp_interface_suspend(struct bcmasp_intf *intf) 1386 { 1387 struct device *kdev = &intf->parent->pdev->dev; 1388 struct net_device *dev = intf->ndev; 1389 bool wake; 1390 1391 if (!netif_running(dev)) 1392 return 0; 1393 1394 netif_device_detach(dev); 1395 1396 wake = device_may_wakeup(kdev) && intf->wolopts; 1397 1398 bcmasp_netif_deinit(dev, !wake); 1399 1400 if (wake) { 1401 /* Disable phy status updates while suspending */ 1402 mutex_lock(&dev->phydev->lock); 1403 dev->phydev->state = PHY_READY; 1404 mutex_unlock(&dev->phydev->lock); 1405 cancel_delayed_work_sync(&dev->phydev->state_queue); 1406 1407 bcmasp_suspend_to_wol(intf); 1408 } else { 1409 bcmasp_phy_hw_unprepare(intf); 1410 1411 /* If Wake-on-LAN is disabled, we can safely 1412 * disable the network interface clocks. 1413 */ 1414 bcmasp_core_clock_set_intf(intf, false); 1415 } 1416 1417 clk_disable_unprepare(intf->parent->clk); 1418 1419 return 0; 1420 } 1421 1422 static void bcmasp_resume_from_wol(struct bcmasp_intf *intf) 1423 { 1424 u32 reg; 1425 1426 if (intf->ndev->phydev && intf->ndev->phydev->eee_cfg.eee_enabled && 1427 intf->parent->eee_fixup) 1428 intf->parent->eee_fixup(intf, false); 1429 1430 reg = umac_rl(intf, UMC_MPD_CTRL); 1431 reg &= ~UMC_MPD_CTRL_MPD_EN; 1432 umac_wl(intf, reg, UMC_MPD_CTRL); 1433 1434 wakeup_intr2_core_wl(intf->parent, 0xffffffff, 1435 ASP_WAKEUP_INTR2_MASK_SET); 1436 } 1437 1438 int bcmasp_interface_resume(struct bcmasp_intf *intf) 1439 { 1440 struct device *kdev = &intf->parent->pdev->dev; 1441 struct net_device *dev = intf->ndev; 1442 bool wake; 1443 int ret; 1444 u32 reg; 1445 1446 if (!netif_running(dev)) 1447 return 0; 1448 1449 ret = clk_prepare_enable(intf->parent->clk); 1450 if (ret) 1451 return ret; 1452 1453 wake = device_may_wakeup(kdev) && intf->wolopts; 1454 1455 bcmasp_core_clock_set_intf(intf, true); 1456 1457 /* The interface might be HW reset in some suspend modes, so we may 1458 * need to restore the UNIMAC/PHY if that is the case. 1459 */ 1460 reg = umac_rl(intf, UMC_CMD); 1461 if (wake && (reg & UMC_CMD_RX_EN)) { 1462 umac_enable_set(intf, UMC_CMD_TX_EN, 1); 1463 bcmasp_resume_from_wol(intf); 1464 } else { 1465 bcmasp_phy_hw_prepare(intf); 1466 umac_reset_and_init(intf, dev->dev_addr); 1467 } 1468 1469 bcmasp_netif_init(dev); 1470 1471 if (wake) { 1472 /* If HW was reset, reprogram the unimac/PHY before resuming 1473 * link status tracking to avoid racing the state machine. 1474 */ 1475 if (!(reg & UMC_CMD_RX_EN)) 1476 bcmasp_adj_link(dev); 1477 1478 /* Resume link status tracking */ 1479 mutex_lock(&dev->phydev->lock); 1480 dev->phydev->state = dev->phydev->link ? PHY_RUNNING : PHY_NOLINK; 1481 mutex_unlock(&dev->phydev->lock); 1482 phy_trigger_machine(dev->phydev); 1483 } else { 1484 phy_start(dev->phydev); 1485 } 1486 1487 netif_device_attach(dev); 1488 1489 return 0; 1490 } 1491