1 // SPDX-License-Identifier: GPL-2.0 2 #define pr_fmt(fmt) "bcmasp_intf: " fmt 3 4 #include <asm/byteorder.h> 5 #include <linux/brcmphy.h> 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/etherdevice.h> 9 #include <linux/netdevice.h> 10 #include <linux/of_net.h> 11 #include <linux/of_mdio.h> 12 #include <linux/phy.h> 13 #include <linux/phy_fixed.h> 14 #include <linux/ptp_classify.h> 15 #include <linux/platform_device.h> 16 #include <net/ip.h> 17 #include <net/ipv6.h> 18 #include <net/page_pool/helpers.h> 19 20 #include "bcmasp.h" 21 #include "bcmasp_intf_defs.h" 22 23 static int incr_ring(int index, int ring_count) 24 { 25 index++; 26 if (index == ring_count) 27 return 0; 28 29 return index; 30 } 31 32 /* Points to last byte of descriptor */ 33 static dma_addr_t incr_last_byte(dma_addr_t addr, dma_addr_t beg, 34 int ring_count) 35 { 36 dma_addr_t end = beg + (ring_count * DESC_SIZE); 37 38 addr += DESC_SIZE; 39 if (addr > end) 40 return beg + DESC_SIZE - 1; 41 42 return addr; 43 } 44 45 /* Points to first byte of descriptor */ 46 static dma_addr_t incr_first_byte(dma_addr_t addr, dma_addr_t beg, 47 int ring_count) 48 { 49 dma_addr_t end = beg + (ring_count * DESC_SIZE); 50 51 addr += DESC_SIZE; 52 if (addr >= end) 53 return beg; 54 55 return addr; 56 } 57 58 static void bcmasp_enable_tx(struct bcmasp_intf *intf, int en) 59 { 60 if (en) { 61 tx_spb_ctrl_wl(intf, TX_SPB_CTRL_ENABLE_EN, TX_SPB_CTRL_ENABLE); 62 tx_epkt_core_wl(intf, (TX_EPKT_C_CFG_MISC_EN | 63 TX_EPKT_C_CFG_MISC_PT | 64 (intf->port << TX_EPKT_C_CFG_MISC_PS_SHIFT)), 65 TX_EPKT_C_CFG_MISC); 66 } else { 67 tx_spb_ctrl_wl(intf, 0x0, TX_SPB_CTRL_ENABLE); 68 tx_epkt_core_wl(intf, 0x0, TX_EPKT_C_CFG_MISC); 69 } 70 } 71 72 static void bcmasp_enable_rx(struct bcmasp_intf *intf, int en) 73 { 74 if (en) 75 rx_edpkt_cfg_wl(intf, RX_EDPKT_CFG_ENABLE_EN, 76 RX_EDPKT_CFG_ENABLE); 77 else 78 rx_edpkt_cfg_wl(intf, 0x0, RX_EDPKT_CFG_ENABLE); 79 } 80 81 static void bcmasp_set_rx_mode(struct net_device *dev) 82 { 83 unsigned char mask[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 84 struct bcmasp_intf *intf = netdev_priv(dev); 85 struct netdev_hw_addr *ha; 86 int ret; 87 88 spin_lock_bh(&intf->parent->mda_lock); 89 90 bcmasp_disable_all_filters(intf); 91 92 if (dev->flags & IFF_PROMISC) 93 goto set_promisc; 94 95 bcmasp_set_promisc(intf, 0); 96 97 bcmasp_set_broad(intf, 1); 98 99 bcmasp_set_oaddr(intf, dev->dev_addr, 1); 100 101 if (dev->flags & IFF_ALLMULTI) { 102 bcmasp_set_allmulti(intf, 1); 103 } else { 104 bcmasp_set_allmulti(intf, 0); 105 106 netdev_for_each_mc_addr(ha, dev) { 107 ret = bcmasp_set_en_mda_filter(intf, ha->addr, mask); 108 if (ret) { 109 intf->mib.mc_filters_full_cnt++; 110 goto set_promisc; 111 } 112 } 113 } 114 115 netdev_for_each_uc_addr(ha, dev) { 116 ret = bcmasp_set_en_mda_filter(intf, ha->addr, mask); 117 if (ret) { 118 intf->mib.uc_filters_full_cnt++; 119 goto set_promisc; 120 } 121 } 122 123 spin_unlock_bh(&intf->parent->mda_lock); 124 return; 125 126 set_promisc: 127 bcmasp_set_promisc(intf, 1); 128 intf->mib.promisc_filters_cnt++; 129 130 /* disable all filters used by this port */ 131 bcmasp_disable_all_filters(intf); 132 133 spin_unlock_bh(&intf->parent->mda_lock); 134 } 135 136 static void bcmasp_clean_txcb(struct bcmasp_intf *intf, int index) 137 { 138 struct bcmasp_tx_cb *txcb = &intf->tx_cbs[index]; 139 140 txcb->skb = NULL; 141 dma_unmap_addr_set(txcb, dma_addr, 0); 142 dma_unmap_len_set(txcb, dma_len, 0); 143 txcb->last = false; 144 } 145 146 static int tx_spb_ring_full(struct bcmasp_intf *intf, int cnt) 147 { 148 int next_index, i; 149 150 /* Check if we have enough room for cnt descriptors */ 151 for (i = 0; i < cnt; i++) { 152 next_index = incr_ring(intf->tx_spb_index, DESC_RING_COUNT); 153 if (next_index == intf->tx_spb_clean_index) 154 return 1; 155 } 156 157 return 0; 158 } 159 160 static struct sk_buff *bcmasp_csum_offload(struct net_device *dev, 161 struct sk_buff *skb, 162 bool *csum_hw) 163 { 164 struct bcmasp_intf *intf = netdev_priv(dev); 165 u32 header = 0, header2 = 0, epkt = 0; 166 struct bcmasp_pkt_offload *offload; 167 unsigned int header_cnt = 0; 168 u8 ip_proto; 169 int ret; 170 171 if (skb->ip_summed != CHECKSUM_PARTIAL) 172 return skb; 173 174 ret = skb_cow_head(skb, sizeof(*offload)); 175 if (ret < 0) { 176 intf->mib.tx_realloc_offload_failed++; 177 goto help; 178 } 179 180 switch (skb->protocol) { 181 case htons(ETH_P_IP): 182 header |= PKT_OFFLOAD_HDR_SIZE_2((ip_hdrlen(skb) >> 8) & 0xf); 183 header2 |= PKT_OFFLOAD_HDR2_SIZE_2(ip_hdrlen(skb) & 0xff); 184 epkt |= PKT_OFFLOAD_EPKT_IP(0); 185 ip_proto = ip_hdr(skb)->protocol; 186 header_cnt += 2; 187 break; 188 case htons(ETH_P_IPV6): 189 header |= PKT_OFFLOAD_HDR_SIZE_2((IP6_HLEN >> 8) & 0xf); 190 header2 |= PKT_OFFLOAD_HDR2_SIZE_2(IP6_HLEN & 0xff); 191 epkt |= PKT_OFFLOAD_EPKT_IP(1); 192 ip_proto = ipv6_hdr(skb)->nexthdr; 193 header_cnt += 2; 194 break; 195 default: 196 goto help; 197 } 198 199 switch (ip_proto) { 200 case IPPROTO_TCP: 201 header2 |= PKT_OFFLOAD_HDR2_SIZE_3(tcp_hdrlen(skb)); 202 epkt |= PKT_OFFLOAD_EPKT_TP(0) | PKT_OFFLOAD_EPKT_CSUM_L4; 203 header_cnt++; 204 break; 205 case IPPROTO_UDP: 206 header2 |= PKT_OFFLOAD_HDR2_SIZE_3(UDP_HLEN); 207 epkt |= PKT_OFFLOAD_EPKT_TP(1) | PKT_OFFLOAD_EPKT_CSUM_L4; 208 header_cnt++; 209 break; 210 default: 211 goto help; 212 } 213 214 offload = (struct bcmasp_pkt_offload *)skb_push(skb, sizeof(*offload)); 215 216 header |= PKT_OFFLOAD_HDR_OP | PKT_OFFLOAD_HDR_COUNT(header_cnt) | 217 PKT_OFFLOAD_HDR_SIZE_1(ETH_HLEN); 218 epkt |= PKT_OFFLOAD_EPKT_OP; 219 220 offload->nop = htonl(PKT_OFFLOAD_NOP); 221 offload->header = htonl(header); 222 offload->header2 = htonl(header2); 223 offload->epkt = htonl(epkt); 224 offload->end = htonl(PKT_OFFLOAD_END_OP); 225 *csum_hw = true; 226 227 return skb; 228 229 help: 230 skb_checksum_help(skb); 231 232 return skb; 233 } 234 235 static netdev_tx_t bcmasp_xmit(struct sk_buff *skb, struct net_device *dev) 236 { 237 struct bcmasp_intf *intf = netdev_priv(dev); 238 unsigned int total_bytes, size; 239 int spb_index, nr_frags, i, j; 240 struct bcmasp_tx_cb *txcb; 241 dma_addr_t mapping, valid; 242 struct bcmasp_desc *desc; 243 bool csum_hw = false; 244 struct device *kdev; 245 skb_frag_t *frag; 246 247 kdev = &intf->parent->pdev->dev; 248 249 nr_frags = skb_shinfo(skb)->nr_frags; 250 251 if (tx_spb_ring_full(intf, nr_frags + 1)) { 252 netif_stop_queue(dev); 253 if (net_ratelimit()) 254 netdev_err(dev, "Tx Ring Full!\n"); 255 return NETDEV_TX_BUSY; 256 } 257 258 /* Save skb len before adding csum offload header */ 259 total_bytes = skb->len; 260 skb = bcmasp_csum_offload(dev, skb, &csum_hw); 261 if (!skb) 262 return NETDEV_TX_OK; 263 264 spb_index = intf->tx_spb_index; 265 valid = intf->tx_spb_dma_valid; 266 for (i = 0; i <= nr_frags; i++) { 267 if (!i) { 268 size = skb_headlen(skb); 269 if (!nr_frags && size < (ETH_ZLEN + ETH_FCS_LEN)) { 270 if (skb_put_padto(skb, ETH_ZLEN + ETH_FCS_LEN)) 271 return NETDEV_TX_OK; 272 size = skb->len; 273 } 274 mapping = dma_map_single(kdev, skb->data, size, 275 DMA_TO_DEVICE); 276 } else { 277 frag = &skb_shinfo(skb)->frags[i - 1]; 278 size = skb_frag_size(frag); 279 mapping = skb_frag_dma_map(kdev, frag, 0, size, 280 DMA_TO_DEVICE); 281 } 282 283 if (dma_mapping_error(kdev, mapping)) { 284 intf->mib.tx_dma_failed++; 285 spb_index = intf->tx_spb_index; 286 for (j = 0; j < i; j++) { 287 bcmasp_clean_txcb(intf, spb_index); 288 spb_index = incr_ring(spb_index, 289 DESC_RING_COUNT); 290 } 291 /* Rewind so we do not have a hole */ 292 spb_index = intf->tx_spb_index; 293 dev_kfree_skb(skb); 294 return NETDEV_TX_OK; 295 } 296 297 txcb = &intf->tx_cbs[spb_index]; 298 desc = &intf->tx_spb_cpu[spb_index]; 299 memset(desc, 0, sizeof(*desc)); 300 txcb->skb = skb; 301 txcb->bytes_sent = total_bytes; 302 dma_unmap_addr_set(txcb, dma_addr, mapping); 303 dma_unmap_len_set(txcb, dma_len, size); 304 if (!i) { 305 desc->flags |= DESC_SOF; 306 if (csum_hw) 307 desc->flags |= DESC_EPKT_CMD; 308 } 309 310 if (i == nr_frags) { 311 desc->flags |= DESC_EOF; 312 txcb->last = true; 313 } 314 315 desc->buf = mapping; 316 desc->size = size; 317 desc->flags |= DESC_INT_EN; 318 319 netif_dbg(intf, tx_queued, dev, 320 "%s dma_buf=%pad dma_len=0x%x flags=0x%x index=0x%x\n", 321 __func__, &mapping, desc->size, desc->flags, 322 spb_index); 323 324 spb_index = incr_ring(spb_index, DESC_RING_COUNT); 325 valid = incr_last_byte(valid, intf->tx_spb_dma_addr, 326 DESC_RING_COUNT); 327 } 328 329 /* Ensure all descriptors have been written to DRAM for the 330 * hardware to see up-to-date contents. 331 */ 332 wmb(); 333 334 intf->tx_spb_index = spb_index; 335 intf->tx_spb_dma_valid = valid; 336 337 skb_tx_timestamp(skb); 338 339 tx_spb_dma_wq(intf, intf->tx_spb_dma_valid, TX_SPB_DMA_VALID); 340 341 if (tx_spb_ring_full(intf, MAX_SKB_FRAGS + 1)) 342 netif_stop_queue(dev); 343 344 return NETDEV_TX_OK; 345 } 346 347 static void bcmasp_netif_start(struct net_device *dev) 348 { 349 struct bcmasp_intf *intf = netdev_priv(dev); 350 351 bcmasp_set_rx_mode(dev); 352 napi_enable(&intf->tx_napi); 353 napi_enable(&intf->rx_napi); 354 355 bcmasp_enable_rx_irq(intf, 1); 356 bcmasp_enable_tx_irq(intf, 1); 357 bcmasp_enable_phy_irq(intf, 1); 358 359 phy_start(dev->phydev); 360 } 361 362 static void umac_reset(struct bcmasp_intf *intf) 363 { 364 umac_wl(intf, 0x0, UMC_CMD); 365 umac_wl(intf, UMC_CMD_SW_RESET, UMC_CMD); 366 usleep_range(10, 100); 367 /* We hold the umac in reset and bring it out of 368 * reset when phy link is up. 369 */ 370 } 371 372 static void umac_set_hw_addr(struct bcmasp_intf *intf, 373 const unsigned char *addr) 374 { 375 u32 mac0 = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | 376 addr[3]; 377 u32 mac1 = (addr[4] << 8) | addr[5]; 378 379 umac_wl(intf, mac0, UMC_MAC0); 380 umac_wl(intf, mac1, UMC_MAC1); 381 } 382 383 static void umac_enable_set(struct bcmasp_intf *intf, u32 mask, 384 unsigned int enable) 385 { 386 u32 reg; 387 388 reg = umac_rl(intf, UMC_CMD); 389 if (reg & UMC_CMD_SW_RESET) 390 return; 391 if (enable) 392 reg |= mask; 393 else 394 reg &= ~mask; 395 umac_wl(intf, reg, UMC_CMD); 396 397 /* UniMAC stops on a packet boundary, wait for a full-sized packet 398 * to be processed (1 msec). 399 */ 400 if (enable == 0) 401 usleep_range(1000, 2000); 402 } 403 404 static void umac_init(struct bcmasp_intf *intf) 405 { 406 umac_wl(intf, 0x800, UMC_FRM_LEN); 407 umac_wl(intf, 0xffff, UMC_PAUSE_CNTRL); 408 umac_wl(intf, 0x800, UMC_RX_MAX_PKT_SZ); 409 } 410 411 static int bcmasp_tx_reclaim(struct bcmasp_intf *intf) 412 { 413 struct bcmasp_intf_stats64 *stats = &intf->stats64; 414 struct device *kdev = &intf->parent->pdev->dev; 415 unsigned long read, released = 0; 416 struct bcmasp_tx_cb *txcb; 417 struct bcmasp_desc *desc; 418 dma_addr_t mapping; 419 420 read = tx_spb_dma_rq(intf, TX_SPB_DMA_READ); 421 while (intf->tx_spb_dma_read != read) { 422 txcb = &intf->tx_cbs[intf->tx_spb_clean_index]; 423 mapping = dma_unmap_addr(txcb, dma_addr); 424 425 dma_unmap_single(kdev, mapping, 426 dma_unmap_len(txcb, dma_len), 427 DMA_TO_DEVICE); 428 429 if (txcb->last) { 430 dev_consume_skb_any(txcb->skb); 431 432 u64_stats_update_begin(&stats->syncp); 433 u64_stats_inc(&stats->tx_packets); 434 u64_stats_add(&stats->tx_bytes, txcb->bytes_sent); 435 u64_stats_update_end(&stats->syncp); 436 } 437 438 desc = &intf->tx_spb_cpu[intf->tx_spb_clean_index]; 439 440 netif_dbg(intf, tx_done, intf->ndev, 441 "%s dma_buf=%pad dma_len=0x%x flags=0x%x c_index=0x%x\n", 442 __func__, &mapping, desc->size, desc->flags, 443 intf->tx_spb_clean_index); 444 445 bcmasp_clean_txcb(intf, intf->tx_spb_clean_index); 446 released++; 447 448 intf->tx_spb_clean_index = incr_ring(intf->tx_spb_clean_index, 449 DESC_RING_COUNT); 450 intf->tx_spb_dma_read = incr_first_byte(intf->tx_spb_dma_read, 451 intf->tx_spb_dma_addr, 452 DESC_RING_COUNT); 453 } 454 455 return released; 456 } 457 458 static int bcmasp_tx_poll(struct napi_struct *napi, int budget) 459 { 460 struct bcmasp_intf *intf = 461 container_of(napi, struct bcmasp_intf, tx_napi); 462 int released = 0; 463 464 released = bcmasp_tx_reclaim(intf); 465 466 napi_complete(&intf->tx_napi); 467 468 bcmasp_enable_tx_irq(intf, 1); 469 470 if (released) 471 netif_wake_queue(intf->ndev); 472 473 return 0; 474 } 475 476 static int bcmasp_rx_poll(struct napi_struct *napi, int budget) 477 { 478 struct bcmasp_intf *intf = 479 container_of(napi, struct bcmasp_intf, rx_napi); 480 struct bcmasp_intf_stats64 *stats = &intf->stats64; 481 struct device *kdev = &intf->parent->pdev->dev; 482 unsigned long processed = 0; 483 struct bcmasp_desc *desc; 484 struct sk_buff *skb; 485 dma_addr_t valid; 486 struct page *page; 487 void *data; 488 u64 flags; 489 u32 len; 490 491 /* Hardware advances DMA_VALID as it writes each descriptor 492 * (RBUF_4K streaming mode); software chases with rx_edpkt_dma_read. 493 */ 494 valid = rx_edpkt_dma_rq(intf, RX_EDPKT_DMA_VALID) + 1; 495 if (valid == intf->rx_edpkt_dma_addr + DESC_RING_SIZE) 496 valid = intf->rx_edpkt_dma_addr; 497 498 while ((processed < budget) && (valid != intf->rx_edpkt_dma_read)) { 499 desc = &intf->rx_edpkt_cpu[intf->rx_edpkt_index]; 500 501 /* Ensure the descriptor has been fully written to DRAM by 502 * the hardware before the CPU reads it. 503 */ 504 rmb(); 505 506 /* Locate the packet data inside the streaming ring buffer. */ 507 data = intf->rx_ring_cpu + 508 (DESC_ADDR(desc->buf) - intf->rx_ring_dma); 509 510 flags = DESC_FLAGS(desc->buf); 511 if (unlikely(flags & (DESC_CRC_ERR | DESC_RX_SYM_ERR))) { 512 if (net_ratelimit()) { 513 netif_err(intf, rx_status, intf->ndev, 514 "flags=0x%llx\n", flags); 515 } 516 517 u64_stats_update_begin(&stats->syncp); 518 if (flags & DESC_CRC_ERR) 519 u64_stats_inc(&stats->rx_crc_errs); 520 if (flags & DESC_RX_SYM_ERR) 521 u64_stats_inc(&stats->rx_sym_errs); 522 u64_stats_update_end(&stats->syncp); 523 524 goto next; 525 } 526 527 dma_sync_single_for_cpu(kdev, DESC_ADDR(desc->buf), desc->size, 528 DMA_FROM_DEVICE); 529 530 len = desc->size; 531 532 /* Allocate a page pool page as the SKB data area so the 533 * kernel can recycle it efficiently after the packet is 534 * consumed, avoiding repeated slab allocations. 535 */ 536 page = page_pool_dev_alloc_pages(intf->rx_page_pool); 537 if (!page) { 538 u64_stats_update_begin(&stats->syncp); 539 u64_stats_inc(&stats->rx_dropped); 540 u64_stats_update_end(&stats->syncp); 541 intf->mib.alloc_rx_skb_failed++; 542 goto next; 543 } 544 545 skb = napi_build_skb(page_address(page), PAGE_SIZE); 546 if (!skb) { 547 u64_stats_update_begin(&stats->syncp); 548 u64_stats_inc(&stats->rx_dropped); 549 u64_stats_update_end(&stats->syncp); 550 intf->mib.alloc_rx_skb_failed++; 551 page_pool_recycle_direct(intf->rx_page_pool, page); 552 goto next; 553 } 554 555 /* Reserve headroom then copy the full descriptor payload 556 * (hardware prepends a 2-byte alignment pad at the start). 557 */ 558 skb_reserve(skb, NET_SKB_PAD); 559 skb_put(skb, len); 560 memcpy(skb->data, data, len); 561 skb_mark_for_recycle(skb); 562 563 /* Skip the 2-byte hardware alignment pad. */ 564 skb_pull(skb, 2); 565 len -= 2; 566 if (likely(intf->crc_fwd)) { 567 skb_trim(skb, len - ETH_FCS_LEN); 568 len -= ETH_FCS_LEN; 569 } 570 571 if ((intf->ndev->features & NETIF_F_RXCSUM) && 572 (desc->buf & DESC_CHKSUM)) 573 skb->ip_summed = CHECKSUM_UNNECESSARY; 574 575 skb->protocol = eth_type_trans(skb, intf->ndev); 576 577 napi_gro_receive(napi, skb); 578 579 u64_stats_update_begin(&stats->syncp); 580 u64_stats_inc(&stats->rx_packets); 581 u64_stats_add(&stats->rx_bytes, len); 582 u64_stats_update_end(&stats->syncp); 583 584 next: 585 /* Return this portion of the streaming ring buffer to HW. */ 586 rx_edpkt_cfg_wq(intf, (DESC_ADDR(desc->buf) + desc->size), 587 RX_EDPKT_RING_BUFFER_READ); 588 589 processed++; 590 intf->rx_edpkt_dma_read = 591 incr_first_byte(intf->rx_edpkt_dma_read, 592 intf->rx_edpkt_dma_addr, 593 DESC_RING_COUNT); 594 intf->rx_edpkt_index = incr_ring(intf->rx_edpkt_index, 595 DESC_RING_COUNT); 596 } 597 598 rx_edpkt_dma_wq(intf, intf->rx_edpkt_dma_read, RX_EDPKT_DMA_READ); 599 600 if (processed < budget && napi_complete_done(&intf->rx_napi, processed)) 601 bcmasp_enable_rx_irq(intf, 1); 602 603 return processed; 604 } 605 606 static void bcmasp_adj_link(struct net_device *dev) 607 { 608 struct bcmasp_intf *intf = netdev_priv(dev); 609 struct phy_device *phydev = dev->phydev; 610 u32 cmd_bits = 0, reg; 611 int changed = 0; 612 613 if (intf->old_link != phydev->link) { 614 changed = 1; 615 intf->old_link = phydev->link; 616 } 617 618 if (intf->old_duplex != phydev->duplex) { 619 changed = 1; 620 intf->old_duplex = phydev->duplex; 621 } 622 623 switch (phydev->speed) { 624 case SPEED_2500: 625 cmd_bits = UMC_CMD_SPEED_2500; 626 break; 627 case SPEED_1000: 628 cmd_bits = UMC_CMD_SPEED_1000; 629 break; 630 case SPEED_100: 631 cmd_bits = UMC_CMD_SPEED_100; 632 break; 633 case SPEED_10: 634 cmd_bits = UMC_CMD_SPEED_10; 635 break; 636 default: 637 break; 638 } 639 cmd_bits <<= UMC_CMD_SPEED_SHIFT; 640 641 if (phydev->duplex == DUPLEX_HALF) 642 cmd_bits |= UMC_CMD_HD_EN; 643 644 if (intf->old_pause != phydev->pause) { 645 changed = 1; 646 intf->old_pause = phydev->pause; 647 } 648 649 if (!phydev->pause) 650 cmd_bits |= UMC_CMD_RX_PAUSE_IGNORE | UMC_CMD_TX_PAUSE_IGNORE; 651 652 if (!changed) 653 return; 654 655 if (phydev->link) { 656 reg = umac_rl(intf, UMC_CMD); 657 reg &= ~((UMC_CMD_SPEED_MASK << UMC_CMD_SPEED_SHIFT) | 658 UMC_CMD_HD_EN | UMC_CMD_RX_PAUSE_IGNORE | 659 UMC_CMD_TX_PAUSE_IGNORE); 660 reg |= cmd_bits; 661 if (reg & UMC_CMD_SW_RESET) { 662 reg &= ~UMC_CMD_SW_RESET; 663 umac_wl(intf, reg, UMC_CMD); 664 udelay(2); 665 reg |= UMC_CMD_TX_EN | UMC_CMD_RX_EN | UMC_CMD_PROMISC; 666 } 667 umac_wl(intf, reg, UMC_CMD); 668 669 umac_wl(intf, phydev->eee_cfg.tx_lpi_timer, UMC_EEE_LPI_TIMER); 670 reg = umac_rl(intf, UMC_EEE_CTRL); 671 if (phydev->enable_tx_lpi) 672 reg |= EEE_EN; 673 else 674 reg &= ~EEE_EN; 675 umac_wl(intf, reg, UMC_EEE_CTRL); 676 } 677 678 reg = rgmii_rl(intf, RGMII_OOB_CNTRL); 679 if (phydev->link) 680 reg |= RGMII_LINK; 681 else 682 reg &= ~RGMII_LINK; 683 rgmii_wl(intf, reg, RGMII_OOB_CNTRL); 684 685 if (changed) 686 phy_print_status(phydev); 687 } 688 689 static struct page_pool * 690 bcmasp_rx_page_pool_create(struct bcmasp_intf *intf) 691 { 692 struct page_pool_params pp_params = { 693 .order = 0, 694 .flags = 0, 695 .pool_size = NUM_4K_BUFFERS, 696 .nid = NUMA_NO_NODE, 697 .dev = &intf->parent->pdev->dev, 698 .napi = &intf->rx_napi, 699 .netdev = intf->ndev, 700 .offset = 0, 701 .max_len = PAGE_SIZE, 702 }; 703 704 return page_pool_create(&pp_params); 705 } 706 707 static int bcmasp_alloc_rx_buffers(struct bcmasp_intf *intf) 708 { 709 struct device *kdev = &intf->parent->pdev->dev; 710 struct page *buffer_pg; 711 int ret; 712 713 /* Contiguous streaming ring that hardware writes packet data into. */ 714 intf->rx_buf_order = get_order(RING_BUFFER_SIZE); 715 buffer_pg = alloc_pages(GFP_KERNEL, intf->rx_buf_order); 716 if (!buffer_pg) 717 return -ENOMEM; 718 719 intf->rx_ring_cpu = page_to_virt(buffer_pg); 720 intf->rx_ring_dma = dma_map_page(kdev, buffer_pg, 0, RING_BUFFER_SIZE, 721 DMA_FROM_DEVICE); 722 if (dma_mapping_error(kdev, intf->rx_ring_dma)) { 723 ret = -ENOMEM; 724 goto free_ring_pages; 725 } 726 727 /* Page pool for SKB data areas (copy targets, not DMA buffers). */ 728 intf->rx_page_pool = bcmasp_rx_page_pool_create(intf); 729 if (IS_ERR(intf->rx_page_pool)) { 730 ret = PTR_ERR(intf->rx_page_pool); 731 intf->rx_page_pool = NULL; 732 goto free_ring_dma; 733 } 734 735 return 0; 736 737 free_ring_dma: 738 dma_unmap_page(kdev, intf->rx_ring_dma, RING_BUFFER_SIZE, 739 DMA_FROM_DEVICE); 740 free_ring_pages: 741 __free_pages(buffer_pg, intf->rx_buf_order); 742 return ret; 743 } 744 745 static void bcmasp_reclaim_rx_buffers(struct bcmasp_intf *intf) 746 { 747 struct device *kdev = &intf->parent->pdev->dev; 748 749 page_pool_destroy(intf->rx_page_pool); 750 intf->rx_page_pool = NULL; 751 dma_unmap_page(kdev, intf->rx_ring_dma, RING_BUFFER_SIZE, 752 DMA_FROM_DEVICE); 753 __free_pages(virt_to_page(intf->rx_ring_cpu), intf->rx_buf_order); 754 } 755 756 static int bcmasp_alloc_buffers(struct bcmasp_intf *intf) 757 { 758 struct device *kdev = &intf->parent->pdev->dev; 759 int ret; 760 761 /* Alloc RX */ 762 ret = bcmasp_alloc_rx_buffers(intf); 763 if (ret) 764 return ret; 765 766 intf->rx_edpkt_cpu = dma_alloc_coherent(kdev, DESC_RING_SIZE, 767 &intf->rx_edpkt_dma_addr, 768 GFP_KERNEL); 769 if (!intf->rx_edpkt_cpu) 770 goto free_rx_buffers; 771 772 /* Alloc TX */ 773 intf->tx_spb_cpu = dma_alloc_coherent(kdev, DESC_RING_SIZE, 774 &intf->tx_spb_dma_addr, GFP_KERNEL); 775 if (!intf->tx_spb_cpu) 776 goto free_rx_edpkt_dma; 777 778 intf->tx_cbs = kzalloc_objs(struct bcmasp_tx_cb, DESC_RING_COUNT); 779 if (!intf->tx_cbs) 780 goto free_tx_spb_dma; 781 782 return 0; 783 784 free_tx_spb_dma: 785 dma_free_coherent(kdev, DESC_RING_SIZE, intf->tx_spb_cpu, 786 intf->tx_spb_dma_addr); 787 free_rx_edpkt_dma: 788 dma_free_coherent(kdev, DESC_RING_SIZE, intf->rx_edpkt_cpu, 789 intf->rx_edpkt_dma_addr); 790 free_rx_buffers: 791 bcmasp_reclaim_rx_buffers(intf); 792 793 return -ENOMEM; 794 } 795 796 static void bcmasp_reclaim_free_buffers(struct bcmasp_intf *intf) 797 { 798 struct device *kdev = &intf->parent->pdev->dev; 799 800 /* RX buffers */ 801 dma_free_coherent(kdev, DESC_RING_SIZE, intf->rx_edpkt_cpu, 802 intf->rx_edpkt_dma_addr); 803 bcmasp_reclaim_rx_buffers(intf); 804 805 /* TX buffers */ 806 dma_free_coherent(kdev, DESC_RING_SIZE, intf->tx_spb_cpu, 807 intf->tx_spb_dma_addr); 808 kfree(intf->tx_cbs); 809 } 810 811 static void bcmasp_init_rx(struct bcmasp_intf *intf) 812 { 813 /* Restart from index 0 */ 814 intf->rx_ring_dma_valid = intf->rx_ring_dma + RING_BUFFER_SIZE - 1; 815 intf->rx_edpkt_dma_valid = intf->rx_edpkt_dma_addr + (DESC_RING_SIZE - 1); 816 intf->rx_edpkt_dma_read = intf->rx_edpkt_dma_addr; 817 intf->rx_edpkt_index = 0; 818 819 /* Make sure channels are disabled */ 820 rx_edpkt_cfg_wl(intf, 0x0, RX_EDPKT_CFG_ENABLE); 821 822 /* Streaming data ring: hardware writes raw packet bytes here. */ 823 rx_edpkt_cfg_wq(intf, intf->rx_ring_dma, RX_EDPKT_RING_BUFFER_READ); 824 rx_edpkt_cfg_wq(intf, intf->rx_ring_dma, RX_EDPKT_RING_BUFFER_WRITE); 825 rx_edpkt_cfg_wq(intf, intf->rx_ring_dma, RX_EDPKT_RING_BUFFER_BASE); 826 rx_edpkt_cfg_wq(intf, intf->rx_ring_dma_valid, 827 RX_EDPKT_RING_BUFFER_END); 828 rx_edpkt_cfg_wq(intf, intf->rx_ring_dma_valid, 829 RX_EDPKT_RING_BUFFER_VALID); 830 831 /* EDPKT descriptor ring: hardware fills descriptors pointing into 832 * the streaming ring buffer above (RBUF_4K mode). 833 */ 834 rx_edpkt_cfg_wl(intf, (RX_EDPKT_CFG_CFG0_RBUF_4K << 835 RX_EDPKT_CFG_CFG0_DBUF_SHIFT) | 836 (RX_EDPKT_CFG_CFG0_64_ALN << 837 RX_EDPKT_CFG_CFG0_BALN_SHIFT) | 838 (RX_EDPKT_CFG_CFG0_EFRM_STUF), 839 RX_EDPKT_CFG_CFG0); 840 rx_edpkt_dma_wq(intf, intf->rx_edpkt_dma_addr, RX_EDPKT_DMA_WRITE); 841 rx_edpkt_dma_wq(intf, intf->rx_edpkt_dma_addr, RX_EDPKT_DMA_READ); 842 rx_edpkt_dma_wq(intf, intf->rx_edpkt_dma_addr, RX_EDPKT_DMA_BASE); 843 rx_edpkt_dma_wq(intf, intf->rx_edpkt_dma_valid, RX_EDPKT_DMA_END); 844 rx_edpkt_dma_wq(intf, intf->rx_edpkt_dma_valid, RX_EDPKT_DMA_VALID); 845 846 umac2fb_wl(intf, UMAC2FB_CFG_DEFAULT_EN | ((intf->channel + 11) << 847 UMAC2FB_CFG_CHID_SHIFT) | (0xd << UMAC2FB_CFG_OK_SEND_SHIFT), 848 UMAC2FB_CFG); 849 } 850 851 852 static void bcmasp_init_tx(struct bcmasp_intf *intf) 853 { 854 /* Restart from index 0 */ 855 intf->tx_spb_dma_valid = intf->tx_spb_dma_addr + DESC_RING_SIZE - 1; 856 intf->tx_spb_dma_read = intf->tx_spb_dma_addr; 857 intf->tx_spb_index = 0; 858 intf->tx_spb_clean_index = 0; 859 memset(intf->tx_cbs, 0, sizeof(struct bcmasp_tx_cb) * DESC_RING_COUNT); 860 861 /* Make sure channels are disabled */ 862 tx_spb_ctrl_wl(intf, 0x0, TX_SPB_CTRL_ENABLE); 863 tx_epkt_core_wl(intf, 0x0, TX_EPKT_C_CFG_MISC); 864 865 /* Tx SPB */ 866 tx_spb_ctrl_wl(intf, ((intf->channel + 8) << TX_SPB_CTRL_XF_BID_SHIFT), 867 TX_SPB_CTRL_XF_CTRL2); 868 869 if (intf->parent->tx_chan_offset) 870 tx_pause_ctrl_wl(intf, (1 << (intf->channel + 8)), TX_PAUSE_MAP_VECTOR); 871 tx_spb_top_wl(intf, 0x1e, TX_SPB_TOP_BLKOUT); 872 873 tx_spb_dma_wq(intf, intf->tx_spb_dma_addr, TX_SPB_DMA_READ); 874 tx_spb_dma_wq(intf, intf->tx_spb_dma_addr, TX_SPB_DMA_BASE); 875 tx_spb_dma_wq(intf, intf->tx_spb_dma_valid, TX_SPB_DMA_END); 876 tx_spb_dma_wq(intf, intf->tx_spb_dma_valid, TX_SPB_DMA_VALID); 877 } 878 879 static void bcmasp_ephy_enable_set(struct bcmasp_intf *intf, bool enable) 880 { 881 u32 mask = RGMII_EPHY_CFG_IDDQ_BIAS | RGMII_EPHY_CFG_EXT_PWRDOWN | 882 RGMII_EPHY_CFG_IDDQ_GLOBAL; 883 u32 reg; 884 885 reg = rgmii_rl(intf, RGMII_EPHY_CNTRL); 886 if (enable) { 887 reg &= ~RGMII_EPHY_CK25_DIS; 888 rgmii_wl(intf, reg, RGMII_EPHY_CNTRL); 889 mdelay(1); 890 891 reg &= ~mask; 892 reg |= RGMII_EPHY_RESET; 893 rgmii_wl(intf, reg, RGMII_EPHY_CNTRL); 894 mdelay(1); 895 896 reg &= ~RGMII_EPHY_RESET; 897 } else { 898 reg |= mask | RGMII_EPHY_RESET; 899 rgmii_wl(intf, reg, RGMII_EPHY_CNTRL); 900 mdelay(1); 901 reg |= RGMII_EPHY_CK25_DIS; 902 } 903 rgmii_wl(intf, reg, RGMII_EPHY_CNTRL); 904 mdelay(1); 905 906 /* Set or clear the LED control override to avoid lighting up LEDs 907 * while the EPHY is powered off and drawing unnecessary current. 908 */ 909 reg = rgmii_rl(intf, RGMII_SYS_LED_CNTRL); 910 if (enable) 911 reg &= ~RGMII_SYS_LED_CNTRL_LINK_OVRD; 912 else 913 reg |= RGMII_SYS_LED_CNTRL_LINK_OVRD; 914 rgmii_wl(intf, reg, RGMII_SYS_LED_CNTRL); 915 } 916 917 static void bcmasp_rgmii_mode_en_set(struct bcmasp_intf *intf, bool enable) 918 { 919 u32 reg; 920 921 reg = rgmii_rl(intf, RGMII_OOB_CNTRL); 922 reg &= ~RGMII_OOB_DIS; 923 if (enable) 924 reg |= RGMII_MODE_EN; 925 else 926 reg &= ~RGMII_MODE_EN; 927 rgmii_wl(intf, reg, RGMII_OOB_CNTRL); 928 } 929 930 static void bcmasp_netif_deinit(struct net_device *dev) 931 { 932 struct bcmasp_intf *intf = netdev_priv(dev); 933 u32 reg, timeout = 1000; 934 935 napi_disable(&intf->tx_napi); 936 937 bcmasp_enable_tx(intf, 0); 938 939 /* Flush any TX packets in the pipe */ 940 tx_spb_dma_wl(intf, TX_SPB_DMA_FIFO_FLUSH, TX_SPB_DMA_FIFO_CTRL); 941 do { 942 reg = tx_spb_dma_rl(intf, TX_SPB_DMA_FIFO_STATUS); 943 if (!(reg & TX_SPB_DMA_FIFO_FLUSH)) 944 break; 945 usleep_range(1000, 2000); 946 } while (timeout-- > 0); 947 tx_spb_dma_wl(intf, 0x0, TX_SPB_DMA_FIFO_CTRL); 948 949 bcmasp_tx_reclaim(intf); 950 951 umac_enable_set(intf, UMC_CMD_TX_EN, 0); 952 953 phy_stop(dev->phydev); 954 955 umac_enable_set(intf, UMC_CMD_RX_EN, 0); 956 957 bcmasp_flush_rx_port(intf); 958 usleep_range(1000, 2000); 959 bcmasp_enable_rx(intf, 0); 960 961 napi_disable(&intf->rx_napi); 962 963 /* Disable interrupts */ 964 bcmasp_enable_tx_irq(intf, 0); 965 bcmasp_enable_rx_irq(intf, 0); 966 bcmasp_enable_phy_irq(intf, 0); 967 968 netif_napi_del(&intf->tx_napi); 969 netif_napi_del(&intf->rx_napi); 970 } 971 972 static int bcmasp_stop(struct net_device *dev) 973 { 974 struct bcmasp_intf *intf = netdev_priv(dev); 975 976 netif_dbg(intf, ifdown, dev, "bcmasp stop\n"); 977 978 /* Stop tx from updating HW */ 979 netif_tx_disable(dev); 980 981 bcmasp_netif_deinit(dev); 982 983 bcmasp_reclaim_free_buffers(intf); 984 985 phy_disconnect(dev->phydev); 986 987 /* Disable internal EPHY or external PHY */ 988 if (intf->internal_phy) 989 bcmasp_ephy_enable_set(intf, false); 990 else 991 bcmasp_rgmii_mode_en_set(intf, false); 992 993 /* Disable the interface clocks */ 994 bcmasp_core_clock_set_intf(intf, false); 995 996 clk_disable_unprepare(intf->parent->clk); 997 998 return 0; 999 } 1000 1001 static void bcmasp_configure_port(struct bcmasp_intf *intf) 1002 { 1003 u32 reg, id_mode_dis = 0; 1004 1005 reg = rgmii_rl(intf, RGMII_PORT_CNTRL); 1006 reg &= ~RGMII_PORT_MODE_MASK; 1007 1008 switch (intf->phy_interface) { 1009 case PHY_INTERFACE_MODE_RGMII: 1010 /* RGMII_NO_ID: TXC transitions at the same time as TXD 1011 * (requires PCB or receiver-side delay) 1012 * RGMII: Add 2ns delay on TXC (90 degree shift) 1013 * 1014 * ID is implicitly disabled for 100Mbps (RG)MII operation. 1015 */ 1016 id_mode_dis = RGMII_ID_MODE_DIS; 1017 fallthrough; 1018 case PHY_INTERFACE_MODE_RGMII_TXID: 1019 reg |= RGMII_PORT_MODE_EXT_GPHY; 1020 break; 1021 case PHY_INTERFACE_MODE_MII: 1022 reg |= RGMII_PORT_MODE_EXT_EPHY; 1023 break; 1024 default: 1025 break; 1026 } 1027 1028 if (intf->internal_phy) 1029 reg |= RGMII_PORT_MODE_EPHY; 1030 1031 rgmii_wl(intf, reg, RGMII_PORT_CNTRL); 1032 1033 reg = rgmii_rl(intf, RGMII_OOB_CNTRL); 1034 reg &= ~RGMII_ID_MODE_DIS; 1035 reg |= id_mode_dis; 1036 rgmii_wl(intf, reg, RGMII_OOB_CNTRL); 1037 } 1038 1039 static int bcmasp_netif_init(struct net_device *dev, bool phy_connect) 1040 { 1041 struct bcmasp_intf *intf = netdev_priv(dev); 1042 phy_interface_t phy_iface = intf->phy_interface; 1043 u32 phy_flags = PHY_BRCM_AUTO_PWRDWN_ENABLE | 1044 PHY_BRCM_DIS_TXCRXC_NOENRGY | 1045 PHY_BRCM_IDDQ_SUSPEND; 1046 struct phy_device *phydev = NULL; 1047 int ret; 1048 1049 /* Always enable interface clocks */ 1050 bcmasp_core_clock_set_intf(intf, true); 1051 1052 /* Enable internal PHY or external PHY before any MAC activity */ 1053 if (intf->internal_phy) 1054 bcmasp_ephy_enable_set(intf, true); 1055 else 1056 bcmasp_rgmii_mode_en_set(intf, true); 1057 bcmasp_configure_port(intf); 1058 1059 /* This is an ugly quirk but we have not been correctly 1060 * interpreting the phy_interface values and we have done that 1061 * across different drivers, so at least we are consistent in 1062 * our mistakes. 1063 * 1064 * When the Generic PHY driver is in use either the PHY has 1065 * been strapped or programmed correctly by the boot loader so 1066 * we should stick to our incorrect interpretation since we 1067 * have validated it. 1068 * 1069 * Now when a dedicated PHY driver is in use, we need to 1070 * reverse the meaning of the phy_interface_mode values to 1071 * something that the PHY driver will interpret and act on such 1072 * that we have two mistakes canceling themselves so to speak. 1073 * We only do this for the two modes that GENET driver 1074 * officially supports on Broadcom STB chips: 1075 * PHY_INTERFACE_MODE_RGMII and PHY_INTERFACE_MODE_RGMII_TXID. 1076 * Other modes are not *officially* supported with the boot 1077 * loader and the scripted environment generating Device Tree 1078 * blobs for those platforms. 1079 * 1080 * Note that internal PHY and fixed-link configurations are not 1081 * affected because they use different phy_interface_t values 1082 * or the Generic PHY driver. 1083 */ 1084 switch (phy_iface) { 1085 case PHY_INTERFACE_MODE_RGMII: 1086 phy_iface = PHY_INTERFACE_MODE_RGMII_ID; 1087 break; 1088 case PHY_INTERFACE_MODE_RGMII_TXID: 1089 phy_iface = PHY_INTERFACE_MODE_RGMII_RXID; 1090 break; 1091 default: 1092 break; 1093 } 1094 1095 if (phy_connect) { 1096 phydev = of_phy_connect(dev, intf->phy_dn, 1097 bcmasp_adj_link, phy_flags, 1098 phy_iface); 1099 if (!phydev) { 1100 ret = -ENODEV; 1101 netdev_err(dev, "could not attach to PHY\n"); 1102 goto err_phy_disable; 1103 } 1104 1105 if (intf->internal_phy) 1106 dev->phydev->irq = PHY_MAC_INTERRUPT; 1107 1108 /* Indicate that the MAC is responsible for PHY PM */ 1109 phydev->mac_managed_pm = true; 1110 1111 /* Set phylib's copy of the LPI timer */ 1112 phydev->eee_cfg.tx_lpi_timer = umac_rl(intf, UMC_EEE_LPI_TIMER); 1113 } 1114 1115 umac_reset(intf); 1116 1117 umac_init(intf); 1118 1119 umac_set_hw_addr(intf, dev->dev_addr); 1120 1121 intf->old_duplex = -1; 1122 intf->old_link = -1; 1123 intf->old_pause = -1; 1124 1125 bcmasp_init_tx(intf); 1126 netif_napi_add_tx(intf->ndev, &intf->tx_napi, bcmasp_tx_poll); 1127 bcmasp_enable_tx(intf, 1); 1128 1129 bcmasp_init_rx(intf); 1130 netif_napi_add(intf->ndev, &intf->rx_napi, bcmasp_rx_poll); 1131 bcmasp_enable_rx(intf, 1); 1132 1133 intf->crc_fwd = !!(umac_rl(intf, UMC_CMD) & UMC_CMD_CRC_FWD); 1134 1135 bcmasp_netif_start(dev); 1136 1137 netif_start_queue(dev); 1138 1139 return 0; 1140 1141 err_phy_disable: 1142 if (intf->internal_phy) 1143 bcmasp_ephy_enable_set(intf, false); 1144 else 1145 bcmasp_rgmii_mode_en_set(intf, false); 1146 return ret; 1147 } 1148 1149 static int bcmasp_open(struct net_device *dev) 1150 { 1151 struct bcmasp_intf *intf = netdev_priv(dev); 1152 int ret; 1153 1154 netif_dbg(intf, ifup, dev, "bcmasp open\n"); 1155 1156 ret = bcmasp_alloc_buffers(intf); 1157 if (ret) 1158 return ret; 1159 1160 ret = clk_prepare_enable(intf->parent->clk); 1161 if (ret) 1162 goto err_free_mem; 1163 1164 ret = bcmasp_netif_init(dev, true); 1165 if (ret) { 1166 clk_disable_unprepare(intf->parent->clk); 1167 goto err_free_mem; 1168 } 1169 1170 return ret; 1171 1172 err_free_mem: 1173 bcmasp_reclaim_free_buffers(intf); 1174 1175 return ret; 1176 } 1177 1178 static void bcmasp_tx_timeout(struct net_device *dev, unsigned int txqueue) 1179 { 1180 struct bcmasp_intf *intf = netdev_priv(dev); 1181 1182 netif_dbg(intf, tx_err, dev, "transmit timeout!\n"); 1183 intf->mib.tx_timeout_cnt++; 1184 } 1185 1186 static int bcmasp_get_phys_port_name(struct net_device *dev, 1187 char *name, size_t len) 1188 { 1189 struct bcmasp_intf *intf = netdev_priv(dev); 1190 1191 if (snprintf(name, len, "p%d", intf->port) >= len) 1192 return -EINVAL; 1193 1194 return 0; 1195 } 1196 1197 static void bcmasp_get_stats64(struct net_device *dev, 1198 struct rtnl_link_stats64 *stats) 1199 { 1200 struct bcmasp_intf *intf = netdev_priv(dev); 1201 struct bcmasp_intf_stats64 *lstats; 1202 unsigned int start; 1203 1204 lstats = &intf->stats64; 1205 1206 do { 1207 start = u64_stats_fetch_begin(&lstats->syncp); 1208 stats->rx_packets = u64_stats_read(&lstats->rx_packets); 1209 stats->rx_bytes = u64_stats_read(&lstats->rx_bytes); 1210 stats->rx_dropped = u64_stats_read(&lstats->rx_dropped); 1211 stats->rx_crc_errors = u64_stats_read(&lstats->rx_crc_errs); 1212 stats->rx_frame_errors = u64_stats_read(&lstats->rx_sym_errs); 1213 stats->rx_errors = stats->rx_crc_errors + stats->rx_frame_errors; 1214 1215 stats->tx_packets = u64_stats_read(&lstats->tx_packets); 1216 stats->tx_bytes = u64_stats_read(&lstats->tx_bytes); 1217 } while (u64_stats_fetch_retry(&lstats->syncp, start)); 1218 } 1219 1220 static const struct net_device_ops bcmasp_netdev_ops = { 1221 .ndo_open = bcmasp_open, 1222 .ndo_stop = bcmasp_stop, 1223 .ndo_start_xmit = bcmasp_xmit, 1224 .ndo_tx_timeout = bcmasp_tx_timeout, 1225 .ndo_set_rx_mode = bcmasp_set_rx_mode, 1226 .ndo_get_phys_port_name = bcmasp_get_phys_port_name, 1227 .ndo_eth_ioctl = phy_do_ioctl_running, 1228 .ndo_set_mac_address = eth_mac_addr, 1229 .ndo_get_stats64 = bcmasp_get_stats64, 1230 }; 1231 1232 static void bcmasp_map_res(struct bcmasp_priv *priv, struct bcmasp_intf *intf) 1233 { 1234 /* Per port */ 1235 intf->res.umac = priv->base + UMC_OFFSET(intf); 1236 intf->res.umac2fb = priv->base + (UMAC2FB_OFFSET + priv->rx_ctrl_offset + 1237 (intf->port * 0x4)); 1238 intf->res.rgmii = priv->base + RGMII_OFFSET(intf); 1239 1240 /* Per ch */ 1241 intf->tx_spb_dma = priv->base + TX_SPB_DMA_OFFSET(intf); 1242 intf->res.tx_spb_ctrl = priv->base + TX_SPB_CTRL_OFFSET(intf); 1243 intf->res.tx_spb_top = priv->base + TX_SPB_TOP_OFFSET(intf); 1244 intf->res.tx_epkt_core = priv->base + TX_EPKT_C_OFFSET(intf); 1245 intf->res.tx_pause_ctrl = priv->base + TX_PAUSE_CTRL_OFFSET(intf); 1246 1247 intf->rx_edpkt_dma = priv->base + RX_EDPKT_DMA_OFFSET(intf); 1248 intf->rx_edpkt_cfg = priv->base + RX_EDPKT_CFG_OFFSET(intf); 1249 } 1250 1251 struct bcmasp_intf *bcmasp_interface_create(struct bcmasp_priv *priv, 1252 struct device_node *ndev_dn, int i) 1253 { 1254 struct device *dev = &priv->pdev->dev; 1255 struct bcmasp_intf *intf; 1256 struct net_device *ndev; 1257 int ch, port, ret; 1258 1259 if (of_property_read_u32(ndev_dn, "reg", &port)) { 1260 dev_warn(dev, "%s: invalid port number\n", ndev_dn->name); 1261 goto err; 1262 } 1263 1264 if (of_property_read_u32(ndev_dn, "brcm,channel", &ch)) { 1265 dev_warn(dev, "%s: invalid ch number\n", ndev_dn->name); 1266 goto err; 1267 } 1268 1269 ndev = alloc_etherdev(sizeof(struct bcmasp_intf)); 1270 if (!ndev) { 1271 dev_warn(dev, "%s: unable to alloc ndev\n", ndev_dn->name); 1272 goto err; 1273 } 1274 intf = netdev_priv(ndev); 1275 1276 intf->parent = priv; 1277 intf->ndev = ndev; 1278 intf->channel = ch; 1279 intf->port = port; 1280 intf->ndev_dn = ndev_dn; 1281 intf->index = i; 1282 1283 ret = of_get_phy_mode(ndev_dn, &intf->phy_interface); 1284 if (ret < 0) { 1285 dev_err(dev, "invalid PHY mode property\n"); 1286 goto err_free_netdev; 1287 } 1288 1289 if (intf->phy_interface == PHY_INTERFACE_MODE_INTERNAL) 1290 intf->internal_phy = true; 1291 1292 intf->phy_dn = of_parse_phandle(ndev_dn, "phy-handle", 0); 1293 if (!intf->phy_dn && of_phy_is_fixed_link(ndev_dn)) { 1294 ret = of_phy_register_fixed_link(ndev_dn); 1295 if (ret) { 1296 dev_warn(dev, "%s: failed to register fixed PHY\n", 1297 ndev_dn->name); 1298 goto err_free_netdev; 1299 } 1300 intf->phy_dn = ndev_dn; 1301 } 1302 1303 /* Map resource */ 1304 bcmasp_map_res(priv, intf); 1305 1306 if ((!phy_interface_mode_is_rgmii(intf->phy_interface) && 1307 intf->phy_interface != PHY_INTERFACE_MODE_MII && 1308 intf->phy_interface != PHY_INTERFACE_MODE_INTERNAL) || 1309 (intf->port != 1 && intf->internal_phy)) { 1310 netdev_err(intf->ndev, "invalid PHY mode: %s for port %d\n", 1311 phy_modes(intf->phy_interface), intf->port); 1312 ret = -EINVAL; 1313 goto err_deregister_fixed_link; 1314 } 1315 1316 ret = of_get_ethdev_address(ndev_dn, ndev); 1317 if (ret) { 1318 netdev_warn(ndev, "using random Ethernet MAC\n"); 1319 eth_hw_addr_random(ndev); 1320 } 1321 1322 SET_NETDEV_DEV(ndev, dev); 1323 ndev->netdev_ops = &bcmasp_netdev_ops; 1324 ndev->ethtool_ops = &bcmasp_ethtool_ops; 1325 intf->msg_enable = netif_msg_init(-1, NETIF_MSG_DRV | 1326 NETIF_MSG_PROBE | 1327 NETIF_MSG_LINK); 1328 ndev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | 1329 NETIF_F_RXCSUM; 1330 ndev->hw_features |= ndev->features; 1331 ndev->needed_headroom += sizeof(struct bcmasp_pkt_offload); 1332 1333 netdev_sw_irq_coalesce_default_on(ndev); 1334 1335 return intf; 1336 1337 err_deregister_fixed_link: 1338 if (of_phy_is_fixed_link(ndev_dn)) 1339 of_phy_deregister_fixed_link(ndev_dn); 1340 err_free_netdev: 1341 free_netdev(ndev); 1342 err: 1343 return NULL; 1344 } 1345 1346 void bcmasp_interface_destroy(struct bcmasp_intf *intf) 1347 { 1348 if (intf->ndev->reg_state == NETREG_REGISTERED) 1349 unregister_netdev(intf->ndev); 1350 if (of_phy_is_fixed_link(intf->ndev_dn)) 1351 of_phy_deregister_fixed_link(intf->ndev_dn); 1352 free_netdev(intf->ndev); 1353 } 1354 1355 static void bcmasp_suspend_to_wol(struct bcmasp_intf *intf) 1356 { 1357 struct net_device *ndev = intf->ndev; 1358 u32 reg; 1359 1360 reg = umac_rl(intf, UMC_MPD_CTRL); 1361 if (intf->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE)) 1362 reg |= UMC_MPD_CTRL_MPD_EN; 1363 reg &= ~UMC_MPD_CTRL_PSW_EN; 1364 if (intf->wolopts & WAKE_MAGICSECURE) { 1365 /* Program the SecureOn password */ 1366 umac_wl(intf, get_unaligned_be16(&intf->sopass[0]), 1367 UMC_PSW_MS); 1368 umac_wl(intf, get_unaligned_be32(&intf->sopass[2]), 1369 UMC_PSW_LS); 1370 reg |= UMC_MPD_CTRL_PSW_EN; 1371 } 1372 umac_wl(intf, reg, UMC_MPD_CTRL); 1373 1374 if (intf->wolopts & WAKE_FILTER) 1375 bcmasp_netfilt_suspend(intf); 1376 1377 /* Bring UniMAC out of reset if needed and enable RX */ 1378 reg = umac_rl(intf, UMC_CMD); 1379 if (reg & UMC_CMD_SW_RESET) 1380 reg &= ~UMC_CMD_SW_RESET; 1381 1382 reg |= UMC_CMD_RX_EN | UMC_CMD_PROMISC; 1383 umac_wl(intf, reg, UMC_CMD); 1384 1385 umac_enable_set(intf, UMC_CMD_RX_EN, 1); 1386 1387 wakeup_intr2_core_wl(intf->parent, 0xffffffff, 1388 ASP_WAKEUP_INTR2_MASK_CLEAR); 1389 1390 if (ndev->phydev && ndev->phydev->eee_cfg.eee_enabled && 1391 intf->parent->eee_fixup) 1392 intf->parent->eee_fixup(intf, true); 1393 1394 netif_dbg(intf, wol, ndev, "entered WOL mode\n"); 1395 } 1396 1397 int bcmasp_interface_suspend(struct bcmasp_intf *intf) 1398 { 1399 struct device *kdev = &intf->parent->pdev->dev; 1400 struct net_device *dev = intf->ndev; 1401 1402 if (!netif_running(dev)) 1403 return 0; 1404 1405 netif_device_detach(dev); 1406 1407 bcmasp_netif_deinit(dev); 1408 1409 if (!intf->wolopts) { 1410 if (intf->internal_phy) 1411 bcmasp_ephy_enable_set(intf, false); 1412 else 1413 bcmasp_rgmii_mode_en_set(intf, false); 1414 1415 /* If Wake-on-LAN is disabled, we can safely 1416 * disable the network interface clocks. 1417 */ 1418 bcmasp_core_clock_set_intf(intf, false); 1419 } 1420 1421 if (device_may_wakeup(kdev) && intf->wolopts) 1422 bcmasp_suspend_to_wol(intf); 1423 1424 clk_disable_unprepare(intf->parent->clk); 1425 1426 return 0; 1427 } 1428 1429 static void bcmasp_resume_from_wol(struct bcmasp_intf *intf) 1430 { 1431 u32 reg; 1432 1433 if (intf->ndev->phydev && intf->ndev->phydev->eee_cfg.eee_enabled && 1434 intf->parent->eee_fixup) 1435 intf->parent->eee_fixup(intf, false); 1436 1437 reg = umac_rl(intf, UMC_MPD_CTRL); 1438 reg &= ~UMC_MPD_CTRL_MPD_EN; 1439 umac_wl(intf, reg, UMC_MPD_CTRL); 1440 1441 wakeup_intr2_core_wl(intf->parent, 0xffffffff, 1442 ASP_WAKEUP_INTR2_MASK_SET); 1443 } 1444 1445 int bcmasp_interface_resume(struct bcmasp_intf *intf) 1446 { 1447 struct net_device *dev = intf->ndev; 1448 int ret; 1449 1450 if (!netif_running(dev)) 1451 return 0; 1452 1453 ret = clk_prepare_enable(intf->parent->clk); 1454 if (ret) 1455 return ret; 1456 1457 ret = bcmasp_netif_init(dev, false); 1458 if (ret) 1459 goto out; 1460 1461 bcmasp_resume_from_wol(intf); 1462 1463 netif_device_attach(dev); 1464 1465 return 0; 1466 1467 out: 1468 clk_disable_unprepare(intf->parent->clk); 1469 return ret; 1470 } 1471