1 // SPDX-License-Identifier: GPL-2.0 2 #define pr_fmt(fmt) "bcmasp_intf: " fmt 3 4 #include <asm/byteorder.h> 5 #include <linux/brcmphy.h> 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/etherdevice.h> 9 #include <linux/netdevice.h> 10 #include <linux/of_net.h> 11 #include <linux/of_mdio.h> 12 #include <linux/phy.h> 13 #include <linux/phy_fixed.h> 14 #include <linux/ptp_classify.h> 15 #include <linux/platform_device.h> 16 #include <net/ip.h> 17 #include <net/ipv6.h> 18 19 #include "bcmasp.h" 20 #include "bcmasp_intf_defs.h" 21 22 static int incr_ring(int index, int ring_count) 23 { 24 index++; 25 if (index == ring_count) 26 return 0; 27 28 return index; 29 } 30 31 /* Points to last byte of descriptor */ 32 static dma_addr_t incr_last_byte(dma_addr_t addr, dma_addr_t beg, 33 int ring_count) 34 { 35 dma_addr_t end = beg + (ring_count * DESC_SIZE); 36 37 addr += DESC_SIZE; 38 if (addr > end) 39 return beg + DESC_SIZE - 1; 40 41 return addr; 42 } 43 44 /* Points to first byte of descriptor */ 45 static dma_addr_t incr_first_byte(dma_addr_t addr, dma_addr_t beg, 46 int ring_count) 47 { 48 dma_addr_t end = beg + (ring_count * DESC_SIZE); 49 50 addr += DESC_SIZE; 51 if (addr >= end) 52 return beg; 53 54 return addr; 55 } 56 57 static void bcmasp_enable_tx(struct bcmasp_intf *intf, int en) 58 { 59 if (en) { 60 tx_spb_ctrl_wl(intf, TX_SPB_CTRL_ENABLE_EN, TX_SPB_CTRL_ENABLE); 61 tx_epkt_core_wl(intf, (TX_EPKT_C_CFG_MISC_EN | 62 TX_EPKT_C_CFG_MISC_PT | 63 (intf->port << TX_EPKT_C_CFG_MISC_PS_SHIFT)), 64 TX_EPKT_C_CFG_MISC); 65 } else { 66 tx_spb_ctrl_wl(intf, 0x0, TX_SPB_CTRL_ENABLE); 67 tx_epkt_core_wl(intf, 0x0, TX_EPKT_C_CFG_MISC); 68 } 69 } 70 71 static void bcmasp_enable_rx(struct bcmasp_intf *intf, int en) 72 { 73 if (en) 74 rx_edpkt_cfg_wl(intf, RX_EDPKT_CFG_ENABLE_EN, 75 RX_EDPKT_CFG_ENABLE); 76 else 77 rx_edpkt_cfg_wl(intf, 0x0, RX_EDPKT_CFG_ENABLE); 78 } 79 80 static void bcmasp_set_rx_mode(struct net_device *dev) 81 { 82 unsigned char mask[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 83 struct bcmasp_intf *intf = netdev_priv(dev); 84 struct netdev_hw_addr *ha; 85 int ret; 86 87 spin_lock_bh(&intf->parent->mda_lock); 88 89 bcmasp_disable_all_filters(intf); 90 91 if (dev->flags & IFF_PROMISC) 92 goto set_promisc; 93 94 bcmasp_set_promisc(intf, 0); 95 96 bcmasp_set_broad(intf, 1); 97 98 bcmasp_set_oaddr(intf, dev->dev_addr, 1); 99 100 if (dev->flags & IFF_ALLMULTI) { 101 bcmasp_set_allmulti(intf, 1); 102 } else { 103 bcmasp_set_allmulti(intf, 0); 104 105 netdev_for_each_mc_addr(ha, dev) { 106 ret = bcmasp_set_en_mda_filter(intf, ha->addr, mask); 107 if (ret) { 108 intf->mib.mc_filters_full_cnt++; 109 goto set_promisc; 110 } 111 } 112 } 113 114 netdev_for_each_uc_addr(ha, dev) { 115 ret = bcmasp_set_en_mda_filter(intf, ha->addr, mask); 116 if (ret) { 117 intf->mib.uc_filters_full_cnt++; 118 goto set_promisc; 119 } 120 } 121 122 spin_unlock_bh(&intf->parent->mda_lock); 123 return; 124 125 set_promisc: 126 bcmasp_set_promisc(intf, 1); 127 intf->mib.promisc_filters_cnt++; 128 129 /* disable all filters used by this port */ 130 bcmasp_disable_all_filters(intf); 131 132 spin_unlock_bh(&intf->parent->mda_lock); 133 } 134 135 static void bcmasp_clean_txcb(struct bcmasp_intf *intf, int index) 136 { 137 struct bcmasp_tx_cb *txcb = &intf->tx_cbs[index]; 138 139 txcb->skb = NULL; 140 dma_unmap_addr_set(txcb, dma_addr, 0); 141 dma_unmap_len_set(txcb, dma_len, 0); 142 txcb->last = false; 143 } 144 145 static int tx_spb_ring_full(struct bcmasp_intf *intf, int cnt) 146 { 147 int next_index, i; 148 149 /* Check if we have enough room for cnt descriptors */ 150 for (i = 0; i < cnt; i++) { 151 next_index = incr_ring(intf->tx_spb_index, DESC_RING_COUNT); 152 if (next_index == intf->tx_spb_clean_index) 153 return 1; 154 } 155 156 return 0; 157 } 158 159 static struct sk_buff *bcmasp_csum_offload(struct net_device *dev, 160 struct sk_buff *skb, 161 bool *csum_hw) 162 { 163 struct bcmasp_intf *intf = netdev_priv(dev); 164 u32 header = 0, header2 = 0, epkt = 0; 165 struct bcmasp_pkt_offload *offload; 166 unsigned int header_cnt = 0; 167 u8 ip_proto; 168 int ret; 169 170 if (skb->ip_summed != CHECKSUM_PARTIAL) 171 return skb; 172 173 ret = skb_cow_head(skb, sizeof(*offload)); 174 if (ret < 0) { 175 intf->mib.tx_realloc_offload_failed++; 176 goto help; 177 } 178 179 switch (skb->protocol) { 180 case htons(ETH_P_IP): 181 header |= PKT_OFFLOAD_HDR_SIZE_2((ip_hdrlen(skb) >> 8) & 0xf); 182 header2 |= PKT_OFFLOAD_HDR2_SIZE_2(ip_hdrlen(skb) & 0xff); 183 epkt |= PKT_OFFLOAD_EPKT_IP(0) | PKT_OFFLOAD_EPKT_CSUM_L2; 184 ip_proto = ip_hdr(skb)->protocol; 185 header_cnt += 2; 186 break; 187 case htons(ETH_P_IPV6): 188 header |= PKT_OFFLOAD_HDR_SIZE_2((IP6_HLEN >> 8) & 0xf); 189 header2 |= PKT_OFFLOAD_HDR2_SIZE_2(IP6_HLEN & 0xff); 190 epkt |= PKT_OFFLOAD_EPKT_IP(1) | PKT_OFFLOAD_EPKT_CSUM_L2; 191 ip_proto = ipv6_hdr(skb)->nexthdr; 192 header_cnt += 2; 193 break; 194 default: 195 goto help; 196 } 197 198 switch (ip_proto) { 199 case IPPROTO_TCP: 200 header2 |= PKT_OFFLOAD_HDR2_SIZE_3(tcp_hdrlen(skb)); 201 epkt |= PKT_OFFLOAD_EPKT_TP(0) | PKT_OFFLOAD_EPKT_CSUM_L3; 202 header_cnt++; 203 break; 204 case IPPROTO_UDP: 205 header2 |= PKT_OFFLOAD_HDR2_SIZE_3(UDP_HLEN); 206 epkt |= PKT_OFFLOAD_EPKT_TP(1) | PKT_OFFLOAD_EPKT_CSUM_L3; 207 header_cnt++; 208 break; 209 default: 210 goto help; 211 } 212 213 offload = (struct bcmasp_pkt_offload *)skb_push(skb, sizeof(*offload)); 214 215 header |= PKT_OFFLOAD_HDR_OP | PKT_OFFLOAD_HDR_COUNT(header_cnt) | 216 PKT_OFFLOAD_HDR_SIZE_1(ETH_HLEN); 217 epkt |= PKT_OFFLOAD_EPKT_OP; 218 219 offload->nop = htonl(PKT_OFFLOAD_NOP); 220 offload->header = htonl(header); 221 offload->header2 = htonl(header2); 222 offload->epkt = htonl(epkt); 223 offload->end = htonl(PKT_OFFLOAD_END_OP); 224 *csum_hw = true; 225 226 return skb; 227 228 help: 229 skb_checksum_help(skb); 230 231 return skb; 232 } 233 234 static unsigned long bcmasp_rx_edpkt_dma_rq(struct bcmasp_intf *intf) 235 { 236 return rx_edpkt_dma_rq(intf, RX_EDPKT_DMA_VALID); 237 } 238 239 static void bcmasp_rx_edpkt_cfg_wq(struct bcmasp_intf *intf, dma_addr_t addr) 240 { 241 rx_edpkt_cfg_wq(intf, addr, RX_EDPKT_RING_BUFFER_READ); 242 } 243 244 static void bcmasp_rx_edpkt_dma_wq(struct bcmasp_intf *intf, dma_addr_t addr) 245 { 246 rx_edpkt_dma_wq(intf, addr, RX_EDPKT_DMA_READ); 247 } 248 249 static unsigned long bcmasp_tx_spb_dma_rq(struct bcmasp_intf *intf) 250 { 251 return tx_spb_dma_rq(intf, TX_SPB_DMA_READ); 252 } 253 254 static void bcmasp_tx_spb_dma_wq(struct bcmasp_intf *intf, dma_addr_t addr) 255 { 256 tx_spb_dma_wq(intf, addr, TX_SPB_DMA_VALID); 257 } 258 259 static const struct bcmasp_intf_ops bcmasp_intf_ops = { 260 .rx_desc_read = bcmasp_rx_edpkt_dma_rq, 261 .rx_buffer_write = bcmasp_rx_edpkt_cfg_wq, 262 .rx_desc_write = bcmasp_rx_edpkt_dma_wq, 263 .tx_read = bcmasp_tx_spb_dma_rq, 264 .tx_write = bcmasp_tx_spb_dma_wq, 265 }; 266 267 static netdev_tx_t bcmasp_xmit(struct sk_buff *skb, struct net_device *dev) 268 { 269 struct bcmasp_intf *intf = netdev_priv(dev); 270 unsigned int total_bytes, size; 271 int spb_index, nr_frags, i, j; 272 struct bcmasp_tx_cb *txcb; 273 dma_addr_t mapping, valid; 274 struct bcmasp_desc *desc; 275 bool csum_hw = false; 276 struct device *kdev; 277 skb_frag_t *frag; 278 279 kdev = &intf->parent->pdev->dev; 280 281 nr_frags = skb_shinfo(skb)->nr_frags; 282 283 if (tx_spb_ring_full(intf, nr_frags + 1)) { 284 netif_stop_queue(dev); 285 if (net_ratelimit()) 286 netdev_err(dev, "Tx Ring Full!\n"); 287 return NETDEV_TX_BUSY; 288 } 289 290 /* Save skb len before adding csum offload header */ 291 total_bytes = skb->len; 292 skb = bcmasp_csum_offload(dev, skb, &csum_hw); 293 if (!skb) 294 return NETDEV_TX_OK; 295 296 spb_index = intf->tx_spb_index; 297 valid = intf->tx_spb_dma_valid; 298 for (i = 0; i <= nr_frags; i++) { 299 if (!i) { 300 size = skb_headlen(skb); 301 if (!nr_frags && size < (ETH_ZLEN + ETH_FCS_LEN)) { 302 if (skb_put_padto(skb, ETH_ZLEN + ETH_FCS_LEN)) 303 return NETDEV_TX_OK; 304 size = skb->len; 305 } 306 mapping = dma_map_single(kdev, skb->data, size, 307 DMA_TO_DEVICE); 308 } else { 309 frag = &skb_shinfo(skb)->frags[i - 1]; 310 size = skb_frag_size(frag); 311 mapping = skb_frag_dma_map(kdev, frag, 0, size, 312 DMA_TO_DEVICE); 313 } 314 315 if (dma_mapping_error(kdev, mapping)) { 316 intf->mib.tx_dma_failed++; 317 spb_index = intf->tx_spb_index; 318 for (j = 0; j < i; j++) { 319 bcmasp_clean_txcb(intf, spb_index); 320 spb_index = incr_ring(spb_index, 321 DESC_RING_COUNT); 322 } 323 /* Rewind so we do not have a hole */ 324 spb_index = intf->tx_spb_index; 325 return NETDEV_TX_OK; 326 } 327 328 txcb = &intf->tx_cbs[spb_index]; 329 desc = &intf->tx_spb_cpu[spb_index]; 330 memset(desc, 0, sizeof(*desc)); 331 txcb->skb = skb; 332 txcb->bytes_sent = total_bytes; 333 dma_unmap_addr_set(txcb, dma_addr, mapping); 334 dma_unmap_len_set(txcb, dma_len, size); 335 if (!i) { 336 desc->flags |= DESC_SOF; 337 if (csum_hw) 338 desc->flags |= DESC_EPKT_CMD; 339 } 340 341 if (i == nr_frags) { 342 desc->flags |= DESC_EOF; 343 txcb->last = true; 344 } 345 346 desc->buf = mapping; 347 desc->size = size; 348 desc->flags |= DESC_INT_EN; 349 350 netif_dbg(intf, tx_queued, dev, 351 "%s dma_buf=%pad dma_len=0x%x flags=0x%x index=0x%x\n", 352 __func__, &mapping, desc->size, desc->flags, 353 spb_index); 354 355 spb_index = incr_ring(spb_index, DESC_RING_COUNT); 356 valid = incr_last_byte(valid, intf->tx_spb_dma_addr, 357 DESC_RING_COUNT); 358 } 359 360 /* Ensure all descriptors have been written to DRAM for the 361 * hardware to see up-to-date contents. 362 */ 363 wmb(); 364 365 intf->tx_spb_index = spb_index; 366 intf->tx_spb_dma_valid = valid; 367 bcmasp_intf_tx_write(intf, intf->tx_spb_dma_valid); 368 369 if (tx_spb_ring_full(intf, MAX_SKB_FRAGS + 1)) 370 netif_stop_queue(dev); 371 372 return NETDEV_TX_OK; 373 } 374 375 static void bcmasp_netif_start(struct net_device *dev) 376 { 377 struct bcmasp_intf *intf = netdev_priv(dev); 378 379 bcmasp_set_rx_mode(dev); 380 napi_enable(&intf->tx_napi); 381 napi_enable(&intf->rx_napi); 382 383 bcmasp_enable_rx_irq(intf, 1); 384 bcmasp_enable_tx_irq(intf, 1); 385 bcmasp_enable_phy_irq(intf, 1); 386 387 phy_start(dev->phydev); 388 } 389 390 static void umac_reset(struct bcmasp_intf *intf) 391 { 392 umac_wl(intf, 0x0, UMC_CMD); 393 umac_wl(intf, UMC_CMD_SW_RESET, UMC_CMD); 394 usleep_range(10, 100); 395 umac_wl(intf, 0x0, UMC_CMD); 396 } 397 398 static void umac_set_hw_addr(struct bcmasp_intf *intf, 399 const unsigned char *addr) 400 { 401 u32 mac0 = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | 402 addr[3]; 403 u32 mac1 = (addr[4] << 8) | addr[5]; 404 405 umac_wl(intf, mac0, UMC_MAC0); 406 umac_wl(intf, mac1, UMC_MAC1); 407 } 408 409 static void umac_enable_set(struct bcmasp_intf *intf, u32 mask, 410 unsigned int enable) 411 { 412 u32 reg; 413 414 reg = umac_rl(intf, UMC_CMD); 415 if (enable) 416 reg |= mask; 417 else 418 reg &= ~mask; 419 umac_wl(intf, reg, UMC_CMD); 420 421 /* UniMAC stops on a packet boundary, wait for a full-sized packet 422 * to be processed (1 msec). 423 */ 424 if (enable == 0) 425 usleep_range(1000, 2000); 426 } 427 428 static void umac_init(struct bcmasp_intf *intf) 429 { 430 umac_wl(intf, 0x800, UMC_FRM_LEN); 431 umac_wl(intf, 0xffff, UMC_PAUSE_CNTRL); 432 umac_wl(intf, 0x800, UMC_RX_MAX_PKT_SZ); 433 umac_enable_set(intf, UMC_CMD_PROMISC, 1); 434 } 435 436 static int bcmasp_tx_poll(struct napi_struct *napi, int budget) 437 { 438 struct bcmasp_intf *intf = 439 container_of(napi, struct bcmasp_intf, tx_napi); 440 struct bcmasp_intf_stats64 *stats = &intf->stats64; 441 struct device *kdev = &intf->parent->pdev->dev; 442 unsigned long read, released = 0; 443 struct bcmasp_tx_cb *txcb; 444 struct bcmasp_desc *desc; 445 dma_addr_t mapping; 446 447 read = bcmasp_intf_tx_read(intf); 448 while (intf->tx_spb_dma_read != read) { 449 txcb = &intf->tx_cbs[intf->tx_spb_clean_index]; 450 mapping = dma_unmap_addr(txcb, dma_addr); 451 452 dma_unmap_single(kdev, mapping, 453 dma_unmap_len(txcb, dma_len), 454 DMA_TO_DEVICE); 455 456 if (txcb->last) { 457 dev_consume_skb_any(txcb->skb); 458 459 u64_stats_update_begin(&stats->syncp); 460 u64_stats_inc(&stats->tx_packets); 461 u64_stats_add(&stats->tx_bytes, txcb->bytes_sent); 462 u64_stats_update_end(&stats->syncp); 463 } 464 465 desc = &intf->tx_spb_cpu[intf->tx_spb_clean_index]; 466 467 netif_dbg(intf, tx_done, intf->ndev, 468 "%s dma_buf=%pad dma_len=0x%x flags=0x%x c_index=0x%x\n", 469 __func__, &mapping, desc->size, desc->flags, 470 intf->tx_spb_clean_index); 471 472 bcmasp_clean_txcb(intf, intf->tx_spb_clean_index); 473 released++; 474 475 intf->tx_spb_clean_index = incr_ring(intf->tx_spb_clean_index, 476 DESC_RING_COUNT); 477 intf->tx_spb_dma_read = incr_first_byte(intf->tx_spb_dma_read, 478 intf->tx_spb_dma_addr, 479 DESC_RING_COUNT); 480 } 481 482 /* Ensure all descriptors have been written to DRAM for the hardware 483 * to see updated contents. 484 */ 485 wmb(); 486 487 napi_complete(&intf->tx_napi); 488 489 bcmasp_enable_tx_irq(intf, 1); 490 491 if (released) 492 netif_wake_queue(intf->ndev); 493 494 return 0; 495 } 496 497 static int bcmasp_rx_poll(struct napi_struct *napi, int budget) 498 { 499 struct bcmasp_intf *intf = 500 container_of(napi, struct bcmasp_intf, rx_napi); 501 struct bcmasp_intf_stats64 *stats = &intf->stats64; 502 struct device *kdev = &intf->parent->pdev->dev; 503 unsigned long processed = 0; 504 struct bcmasp_desc *desc; 505 struct sk_buff *skb; 506 dma_addr_t valid; 507 void *data; 508 u64 flags; 509 u32 len; 510 511 valid = bcmasp_intf_rx_desc_read(intf) + 1; 512 if (valid == intf->rx_edpkt_dma_addr + DESC_RING_SIZE) 513 valid = intf->rx_edpkt_dma_addr; 514 515 while ((processed < budget) && (valid != intf->rx_edpkt_dma_read)) { 516 desc = &intf->rx_edpkt_cpu[intf->rx_edpkt_index]; 517 518 /* Ensure that descriptor has been fully written to DRAM by 519 * hardware before reading by the CPU 520 */ 521 rmb(); 522 523 /* Calculate virt addr by offsetting from physical addr */ 524 data = intf->rx_ring_cpu + 525 (DESC_ADDR(desc->buf) - intf->rx_ring_dma); 526 527 flags = DESC_FLAGS(desc->buf); 528 if (unlikely(flags & (DESC_CRC_ERR | DESC_RX_SYM_ERR))) { 529 if (net_ratelimit()) { 530 netif_err(intf, rx_status, intf->ndev, 531 "flags=0x%llx\n", flags); 532 } 533 534 u64_stats_update_begin(&stats->syncp); 535 if (flags & DESC_CRC_ERR) 536 u64_stats_inc(&stats->rx_crc_errs); 537 if (flags & DESC_RX_SYM_ERR) 538 u64_stats_inc(&stats->rx_sym_errs); 539 u64_stats_update_end(&stats->syncp); 540 541 goto next; 542 } 543 544 dma_sync_single_for_cpu(kdev, DESC_ADDR(desc->buf), desc->size, 545 DMA_FROM_DEVICE); 546 547 len = desc->size; 548 549 skb = napi_alloc_skb(napi, len); 550 if (!skb) { 551 u64_stats_update_begin(&stats->syncp); 552 u64_stats_inc(&stats->rx_dropped); 553 u64_stats_update_end(&stats->syncp); 554 intf->mib.alloc_rx_skb_failed++; 555 556 goto next; 557 } 558 559 skb_put(skb, len); 560 memcpy(skb->data, data, len); 561 562 skb_pull(skb, 2); 563 len -= 2; 564 if (likely(intf->crc_fwd)) { 565 skb_trim(skb, len - ETH_FCS_LEN); 566 len -= ETH_FCS_LEN; 567 } 568 569 if ((intf->ndev->features & NETIF_F_RXCSUM) && 570 (desc->buf & DESC_CHKSUM)) 571 skb->ip_summed = CHECKSUM_UNNECESSARY; 572 573 skb->protocol = eth_type_trans(skb, intf->ndev); 574 575 napi_gro_receive(napi, skb); 576 577 u64_stats_update_begin(&stats->syncp); 578 u64_stats_inc(&stats->rx_packets); 579 u64_stats_add(&stats->rx_bytes, len); 580 u64_stats_update_end(&stats->syncp); 581 582 next: 583 bcmasp_intf_rx_buffer_write(intf, (DESC_ADDR(desc->buf) + 584 desc->size)); 585 586 processed++; 587 intf->rx_edpkt_dma_read = 588 incr_first_byte(intf->rx_edpkt_dma_read, 589 intf->rx_edpkt_dma_addr, 590 DESC_RING_COUNT); 591 intf->rx_edpkt_index = incr_ring(intf->rx_edpkt_index, 592 DESC_RING_COUNT); 593 } 594 595 bcmasp_intf_rx_desc_write(intf, intf->rx_edpkt_dma_read); 596 597 if (processed < budget) { 598 napi_complete_done(&intf->rx_napi, processed); 599 bcmasp_enable_rx_irq(intf, 1); 600 } 601 602 return processed; 603 } 604 605 static void bcmasp_adj_link(struct net_device *dev) 606 { 607 struct bcmasp_intf *intf = netdev_priv(dev); 608 struct phy_device *phydev = dev->phydev; 609 u32 cmd_bits = 0, reg; 610 int changed = 0; 611 bool active; 612 613 if (intf->old_link != phydev->link) { 614 changed = 1; 615 intf->old_link = phydev->link; 616 } 617 618 if (intf->old_duplex != phydev->duplex) { 619 changed = 1; 620 intf->old_duplex = phydev->duplex; 621 } 622 623 switch (phydev->speed) { 624 case SPEED_2500: 625 cmd_bits = UMC_CMD_SPEED_2500; 626 break; 627 case SPEED_1000: 628 cmd_bits = UMC_CMD_SPEED_1000; 629 break; 630 case SPEED_100: 631 cmd_bits = UMC_CMD_SPEED_100; 632 break; 633 case SPEED_10: 634 cmd_bits = UMC_CMD_SPEED_10; 635 break; 636 default: 637 break; 638 } 639 cmd_bits <<= UMC_CMD_SPEED_SHIFT; 640 641 if (phydev->duplex == DUPLEX_HALF) 642 cmd_bits |= UMC_CMD_HD_EN; 643 644 if (intf->old_pause != phydev->pause) { 645 changed = 1; 646 intf->old_pause = phydev->pause; 647 } 648 649 if (!phydev->pause) 650 cmd_bits |= UMC_CMD_RX_PAUSE_IGNORE | UMC_CMD_TX_PAUSE_IGNORE; 651 652 if (!changed) 653 return; 654 655 if (phydev->link) { 656 reg = umac_rl(intf, UMC_CMD); 657 reg &= ~((UMC_CMD_SPEED_MASK << UMC_CMD_SPEED_SHIFT) | 658 UMC_CMD_HD_EN | UMC_CMD_RX_PAUSE_IGNORE | 659 UMC_CMD_TX_PAUSE_IGNORE); 660 reg |= cmd_bits; 661 umac_wl(intf, reg, UMC_CMD); 662 663 active = phy_init_eee(phydev, 0) >= 0; 664 bcmasp_eee_enable_set(intf, active); 665 } 666 667 reg = rgmii_rl(intf, RGMII_OOB_CNTRL); 668 if (phydev->link) 669 reg |= RGMII_LINK; 670 else 671 reg &= ~RGMII_LINK; 672 rgmii_wl(intf, reg, RGMII_OOB_CNTRL); 673 674 if (changed) 675 phy_print_status(phydev); 676 } 677 678 static int bcmasp_alloc_buffers(struct bcmasp_intf *intf) 679 { 680 struct device *kdev = &intf->parent->pdev->dev; 681 struct page *buffer_pg; 682 683 /* Alloc RX */ 684 intf->rx_buf_order = get_order(RING_BUFFER_SIZE); 685 buffer_pg = alloc_pages(GFP_KERNEL, intf->rx_buf_order); 686 if (!buffer_pg) 687 return -ENOMEM; 688 689 intf->rx_ring_cpu = page_to_virt(buffer_pg); 690 intf->rx_ring_dma = dma_map_page(kdev, buffer_pg, 0, RING_BUFFER_SIZE, 691 DMA_FROM_DEVICE); 692 if (dma_mapping_error(kdev, intf->rx_ring_dma)) 693 goto free_rx_buffer; 694 695 intf->rx_edpkt_cpu = dma_alloc_coherent(kdev, DESC_RING_SIZE, 696 &intf->rx_edpkt_dma_addr, GFP_KERNEL); 697 if (!intf->rx_edpkt_cpu) 698 goto free_rx_buffer_dma; 699 700 /* Alloc TX */ 701 intf->tx_spb_cpu = dma_alloc_coherent(kdev, DESC_RING_SIZE, 702 &intf->tx_spb_dma_addr, GFP_KERNEL); 703 if (!intf->tx_spb_cpu) 704 goto free_rx_edpkt_dma; 705 706 intf->tx_cbs = kcalloc(DESC_RING_COUNT, sizeof(struct bcmasp_tx_cb), 707 GFP_KERNEL); 708 if (!intf->tx_cbs) 709 goto free_tx_spb_dma; 710 711 return 0; 712 713 free_tx_spb_dma: 714 dma_free_coherent(kdev, DESC_RING_SIZE, intf->tx_spb_cpu, 715 intf->tx_spb_dma_addr); 716 free_rx_edpkt_dma: 717 dma_free_coherent(kdev, DESC_RING_SIZE, intf->rx_edpkt_cpu, 718 intf->rx_edpkt_dma_addr); 719 free_rx_buffer_dma: 720 dma_unmap_page(kdev, intf->rx_ring_dma, RING_BUFFER_SIZE, 721 DMA_FROM_DEVICE); 722 free_rx_buffer: 723 __free_pages(buffer_pg, intf->rx_buf_order); 724 725 return -ENOMEM; 726 } 727 728 static void bcmasp_reclaim_free_buffers(struct bcmasp_intf *intf) 729 { 730 struct device *kdev = &intf->parent->pdev->dev; 731 732 /* RX buffers */ 733 dma_free_coherent(kdev, DESC_RING_SIZE, intf->rx_edpkt_cpu, 734 intf->rx_edpkt_dma_addr); 735 dma_unmap_page(kdev, intf->rx_ring_dma, RING_BUFFER_SIZE, 736 DMA_FROM_DEVICE); 737 __free_pages(virt_to_page(intf->rx_ring_cpu), intf->rx_buf_order); 738 739 /* TX buffers */ 740 dma_free_coherent(kdev, DESC_RING_SIZE, intf->tx_spb_cpu, 741 intf->tx_spb_dma_addr); 742 kfree(intf->tx_cbs); 743 } 744 745 static void bcmasp_init_rx(struct bcmasp_intf *intf) 746 { 747 /* Restart from index 0 */ 748 intf->rx_ring_dma_valid = intf->rx_ring_dma + RING_BUFFER_SIZE - 1; 749 intf->rx_edpkt_dma_valid = intf->rx_edpkt_dma_addr + (DESC_RING_SIZE - 1); 750 intf->rx_edpkt_dma_read = intf->rx_edpkt_dma_addr; 751 intf->rx_edpkt_index = 0; 752 753 /* Make sure channels are disabled */ 754 rx_edpkt_cfg_wl(intf, 0x0, RX_EDPKT_CFG_ENABLE); 755 756 /* Rx SPB */ 757 rx_edpkt_cfg_wq(intf, intf->rx_ring_dma, RX_EDPKT_RING_BUFFER_READ); 758 rx_edpkt_cfg_wq(intf, intf->rx_ring_dma, RX_EDPKT_RING_BUFFER_WRITE); 759 rx_edpkt_cfg_wq(intf, intf->rx_ring_dma, RX_EDPKT_RING_BUFFER_BASE); 760 rx_edpkt_cfg_wq(intf, intf->rx_ring_dma_valid, 761 RX_EDPKT_RING_BUFFER_END); 762 rx_edpkt_cfg_wq(intf, intf->rx_ring_dma_valid, 763 RX_EDPKT_RING_BUFFER_VALID); 764 765 /* EDPKT */ 766 rx_edpkt_cfg_wl(intf, (RX_EDPKT_CFG_CFG0_RBUF_4K << 767 RX_EDPKT_CFG_CFG0_DBUF_SHIFT) | 768 (RX_EDPKT_CFG_CFG0_64_ALN << 769 RX_EDPKT_CFG_CFG0_BALN_SHIFT) | 770 (RX_EDPKT_CFG_CFG0_EFRM_STUF), 771 RX_EDPKT_CFG_CFG0); 772 rx_edpkt_dma_wq(intf, intf->rx_edpkt_dma_addr, RX_EDPKT_DMA_WRITE); 773 rx_edpkt_dma_wq(intf, intf->rx_edpkt_dma_addr, RX_EDPKT_DMA_READ); 774 rx_edpkt_dma_wq(intf, intf->rx_edpkt_dma_addr, RX_EDPKT_DMA_BASE); 775 rx_edpkt_dma_wq(intf, intf->rx_edpkt_dma_valid, RX_EDPKT_DMA_END); 776 rx_edpkt_dma_wq(intf, intf->rx_edpkt_dma_valid, RX_EDPKT_DMA_VALID); 777 778 umac2fb_wl(intf, UMAC2FB_CFG_DEFAULT_EN | ((intf->channel + 11) << 779 UMAC2FB_CFG_CHID_SHIFT) | (0xd << UMAC2FB_CFG_OK_SEND_SHIFT), 780 UMAC2FB_CFG); 781 } 782 783 784 static void bcmasp_init_tx(struct bcmasp_intf *intf) 785 { 786 /* Restart from index 0 */ 787 intf->tx_spb_dma_valid = intf->tx_spb_dma_addr + DESC_RING_SIZE - 1; 788 intf->tx_spb_dma_read = intf->tx_spb_dma_addr; 789 intf->tx_spb_index = 0; 790 intf->tx_spb_clean_index = 0; 791 792 /* Make sure channels are disabled */ 793 tx_spb_ctrl_wl(intf, 0x0, TX_SPB_CTRL_ENABLE); 794 tx_epkt_core_wl(intf, 0x0, TX_EPKT_C_CFG_MISC); 795 796 /* Tx SPB */ 797 tx_spb_ctrl_wl(intf, ((intf->channel + 8) << TX_SPB_CTRL_XF_BID_SHIFT), 798 TX_SPB_CTRL_XF_CTRL2); 799 tx_pause_ctrl_wl(intf, (1 << (intf->channel + 8)), TX_PAUSE_MAP_VECTOR); 800 tx_spb_top_wl(intf, 0x1e, TX_SPB_TOP_BLKOUT); 801 tx_spb_top_wl(intf, 0x0, TX_SPB_TOP_SPRE_BW_CTRL); 802 803 tx_spb_dma_wq(intf, intf->tx_spb_dma_addr, TX_SPB_DMA_READ); 804 tx_spb_dma_wq(intf, intf->tx_spb_dma_addr, TX_SPB_DMA_BASE); 805 tx_spb_dma_wq(intf, intf->tx_spb_dma_valid, TX_SPB_DMA_END); 806 tx_spb_dma_wq(intf, intf->tx_spb_dma_valid, TX_SPB_DMA_VALID); 807 } 808 809 static void bcmasp_ephy_enable_set(struct bcmasp_intf *intf, bool enable) 810 { 811 u32 mask = RGMII_EPHY_CFG_IDDQ_BIAS | RGMII_EPHY_CFG_EXT_PWRDOWN | 812 RGMII_EPHY_CFG_IDDQ_GLOBAL; 813 u32 reg; 814 815 reg = rgmii_rl(intf, RGMII_EPHY_CNTRL); 816 if (enable) { 817 reg &= ~RGMII_EPHY_CK25_DIS; 818 rgmii_wl(intf, reg, RGMII_EPHY_CNTRL); 819 mdelay(1); 820 821 reg &= ~mask; 822 reg |= RGMII_EPHY_RESET; 823 rgmii_wl(intf, reg, RGMII_EPHY_CNTRL); 824 mdelay(1); 825 826 reg &= ~RGMII_EPHY_RESET; 827 } else { 828 reg |= mask | RGMII_EPHY_RESET; 829 rgmii_wl(intf, reg, RGMII_EPHY_CNTRL); 830 mdelay(1); 831 reg |= RGMII_EPHY_CK25_DIS; 832 } 833 rgmii_wl(intf, reg, RGMII_EPHY_CNTRL); 834 mdelay(1); 835 836 /* Set or clear the LED control override to avoid lighting up LEDs 837 * while the EPHY is powered off and drawing unnecessary current. 838 */ 839 reg = rgmii_rl(intf, RGMII_SYS_LED_CNTRL); 840 if (enable) 841 reg &= ~RGMII_SYS_LED_CNTRL_LINK_OVRD; 842 else 843 reg |= RGMII_SYS_LED_CNTRL_LINK_OVRD; 844 rgmii_wl(intf, reg, RGMII_SYS_LED_CNTRL); 845 } 846 847 static void bcmasp_rgmii_mode_en_set(struct bcmasp_intf *intf, bool enable) 848 { 849 u32 reg; 850 851 reg = rgmii_rl(intf, RGMII_OOB_CNTRL); 852 reg &= ~RGMII_OOB_DIS; 853 if (enable) 854 reg |= RGMII_MODE_EN; 855 else 856 reg &= ~RGMII_MODE_EN; 857 rgmii_wl(intf, reg, RGMII_OOB_CNTRL); 858 } 859 860 static void bcmasp_netif_deinit(struct net_device *dev) 861 { 862 struct bcmasp_intf *intf = netdev_priv(dev); 863 u32 reg, timeout = 1000; 864 865 napi_disable(&intf->tx_napi); 866 867 bcmasp_enable_tx(intf, 0); 868 869 /* Flush any TX packets in the pipe */ 870 tx_spb_dma_wl(intf, TX_SPB_DMA_FIFO_FLUSH, TX_SPB_DMA_FIFO_CTRL); 871 do { 872 reg = tx_spb_dma_rl(intf, TX_SPB_DMA_FIFO_STATUS); 873 if (!(reg & TX_SPB_DMA_FIFO_FLUSH)) 874 break; 875 usleep_range(1000, 2000); 876 } while (timeout-- > 0); 877 tx_spb_dma_wl(intf, 0x0, TX_SPB_DMA_FIFO_CTRL); 878 879 umac_enable_set(intf, UMC_CMD_TX_EN, 0); 880 881 phy_stop(dev->phydev); 882 883 umac_enable_set(intf, UMC_CMD_RX_EN, 0); 884 885 bcmasp_flush_rx_port(intf); 886 usleep_range(1000, 2000); 887 bcmasp_enable_rx(intf, 0); 888 889 napi_disable(&intf->rx_napi); 890 891 /* Disable interrupts */ 892 bcmasp_enable_tx_irq(intf, 0); 893 bcmasp_enable_rx_irq(intf, 0); 894 bcmasp_enable_phy_irq(intf, 0); 895 896 netif_napi_del(&intf->tx_napi); 897 netif_napi_del(&intf->rx_napi); 898 } 899 900 static int bcmasp_stop(struct net_device *dev) 901 { 902 struct bcmasp_intf *intf = netdev_priv(dev); 903 904 netif_dbg(intf, ifdown, dev, "bcmasp stop\n"); 905 906 /* Stop tx from updating HW */ 907 netif_tx_disable(dev); 908 909 bcmasp_netif_deinit(dev); 910 911 bcmasp_reclaim_free_buffers(intf); 912 913 phy_disconnect(dev->phydev); 914 915 /* Disable internal EPHY or external PHY */ 916 if (intf->internal_phy) 917 bcmasp_ephy_enable_set(intf, false); 918 else 919 bcmasp_rgmii_mode_en_set(intf, false); 920 921 /* Disable the interface clocks */ 922 bcmasp_core_clock_set_intf(intf, false); 923 924 clk_disable_unprepare(intf->parent->clk); 925 926 return 0; 927 } 928 929 static void bcmasp_configure_port(struct bcmasp_intf *intf) 930 { 931 u32 reg, id_mode_dis = 0; 932 933 reg = rgmii_rl(intf, RGMII_PORT_CNTRL); 934 reg &= ~RGMII_PORT_MODE_MASK; 935 936 switch (intf->phy_interface) { 937 case PHY_INTERFACE_MODE_RGMII: 938 /* RGMII_NO_ID: TXC transitions at the same time as TXD 939 * (requires PCB or receiver-side delay) 940 * RGMII: Add 2ns delay on TXC (90 degree shift) 941 * 942 * ID is implicitly disabled for 100Mbps (RG)MII operation. 943 */ 944 id_mode_dis = RGMII_ID_MODE_DIS; 945 fallthrough; 946 case PHY_INTERFACE_MODE_RGMII_TXID: 947 reg |= RGMII_PORT_MODE_EXT_GPHY; 948 break; 949 case PHY_INTERFACE_MODE_MII: 950 reg |= RGMII_PORT_MODE_EXT_EPHY; 951 break; 952 default: 953 break; 954 } 955 956 if (intf->internal_phy) 957 reg |= RGMII_PORT_MODE_EPHY; 958 959 rgmii_wl(intf, reg, RGMII_PORT_CNTRL); 960 961 reg = rgmii_rl(intf, RGMII_OOB_CNTRL); 962 reg &= ~RGMII_ID_MODE_DIS; 963 reg |= id_mode_dis; 964 rgmii_wl(intf, reg, RGMII_OOB_CNTRL); 965 } 966 967 static int bcmasp_netif_init(struct net_device *dev, bool phy_connect) 968 { 969 struct bcmasp_intf *intf = netdev_priv(dev); 970 phy_interface_t phy_iface = intf->phy_interface; 971 u32 phy_flags = PHY_BRCM_AUTO_PWRDWN_ENABLE | 972 PHY_BRCM_DIS_TXCRXC_NOENRGY | 973 PHY_BRCM_IDDQ_SUSPEND; 974 struct phy_device *phydev = NULL; 975 int ret; 976 977 /* Always enable interface clocks */ 978 bcmasp_core_clock_set_intf(intf, true); 979 980 /* Enable internal PHY or external PHY before any MAC activity */ 981 if (intf->internal_phy) 982 bcmasp_ephy_enable_set(intf, true); 983 else 984 bcmasp_rgmii_mode_en_set(intf, true); 985 bcmasp_configure_port(intf); 986 987 /* This is an ugly quirk but we have not been correctly 988 * interpreting the phy_interface values and we have done that 989 * across different drivers, so at least we are consistent in 990 * our mistakes. 991 * 992 * When the Generic PHY driver is in use either the PHY has 993 * been strapped or programmed correctly by the boot loader so 994 * we should stick to our incorrect interpretation since we 995 * have validated it. 996 * 997 * Now when a dedicated PHY driver is in use, we need to 998 * reverse the meaning of the phy_interface_mode values to 999 * something that the PHY driver will interpret and act on such 1000 * that we have two mistakes canceling themselves so to speak. 1001 * We only do this for the two modes that GENET driver 1002 * officially supports on Broadcom STB chips: 1003 * PHY_INTERFACE_MODE_RGMII and PHY_INTERFACE_MODE_RGMII_TXID. 1004 * Other modes are not *officially* supported with the boot 1005 * loader and the scripted environment generating Device Tree 1006 * blobs for those platforms. 1007 * 1008 * Note that internal PHY and fixed-link configurations are not 1009 * affected because they use different phy_interface_t values 1010 * or the Generic PHY driver. 1011 */ 1012 switch (phy_iface) { 1013 case PHY_INTERFACE_MODE_RGMII: 1014 phy_iface = PHY_INTERFACE_MODE_RGMII_ID; 1015 break; 1016 case PHY_INTERFACE_MODE_RGMII_TXID: 1017 phy_iface = PHY_INTERFACE_MODE_RGMII_RXID; 1018 break; 1019 default: 1020 break; 1021 } 1022 1023 if (phy_connect) { 1024 phydev = of_phy_connect(dev, intf->phy_dn, 1025 bcmasp_adj_link, phy_flags, 1026 phy_iface); 1027 if (!phydev) { 1028 ret = -ENODEV; 1029 netdev_err(dev, "could not attach to PHY\n"); 1030 goto err_phy_disable; 1031 } 1032 1033 if (intf->internal_phy) 1034 dev->phydev->irq = PHY_MAC_INTERRUPT; 1035 1036 /* Indicate that the MAC is responsible for PHY PM */ 1037 phydev->mac_managed_pm = true; 1038 } else if (!intf->wolopts) { 1039 ret = phy_resume(dev->phydev); 1040 if (ret) 1041 goto err_phy_disable; 1042 } 1043 1044 umac_reset(intf); 1045 1046 umac_init(intf); 1047 1048 /* Disable the UniMAC RX/TX */ 1049 umac_enable_set(intf, (UMC_CMD_RX_EN | UMC_CMD_TX_EN), 0); 1050 1051 umac_set_hw_addr(intf, dev->dev_addr); 1052 1053 intf->old_duplex = -1; 1054 intf->old_link = -1; 1055 intf->old_pause = -1; 1056 1057 bcmasp_init_tx(intf); 1058 netif_napi_add_tx(intf->ndev, &intf->tx_napi, bcmasp_tx_poll); 1059 bcmasp_enable_tx(intf, 1); 1060 1061 bcmasp_init_rx(intf); 1062 netif_napi_add(intf->ndev, &intf->rx_napi, bcmasp_rx_poll); 1063 bcmasp_enable_rx(intf, 1); 1064 1065 /* Turn on UniMAC TX/RX */ 1066 umac_enable_set(intf, (UMC_CMD_RX_EN | UMC_CMD_TX_EN), 1); 1067 1068 intf->crc_fwd = !!(umac_rl(intf, UMC_CMD) & UMC_CMD_CRC_FWD); 1069 1070 bcmasp_netif_start(dev); 1071 1072 netif_start_queue(dev); 1073 1074 return 0; 1075 1076 err_phy_disable: 1077 if (intf->internal_phy) 1078 bcmasp_ephy_enable_set(intf, false); 1079 else 1080 bcmasp_rgmii_mode_en_set(intf, false); 1081 return ret; 1082 } 1083 1084 static int bcmasp_open(struct net_device *dev) 1085 { 1086 struct bcmasp_intf *intf = netdev_priv(dev); 1087 int ret; 1088 1089 netif_dbg(intf, ifup, dev, "bcmasp open\n"); 1090 1091 ret = bcmasp_alloc_buffers(intf); 1092 if (ret) 1093 return ret; 1094 1095 ret = clk_prepare_enable(intf->parent->clk); 1096 if (ret) 1097 goto err_free_mem; 1098 1099 ret = bcmasp_netif_init(dev, true); 1100 if (ret) { 1101 clk_disable_unprepare(intf->parent->clk); 1102 goto err_free_mem; 1103 } 1104 1105 return ret; 1106 1107 err_free_mem: 1108 bcmasp_reclaim_free_buffers(intf); 1109 1110 return ret; 1111 } 1112 1113 static void bcmasp_tx_timeout(struct net_device *dev, unsigned int txqueue) 1114 { 1115 struct bcmasp_intf *intf = netdev_priv(dev); 1116 1117 netif_dbg(intf, tx_err, dev, "transmit timeout!\n"); 1118 intf->mib.tx_timeout_cnt++; 1119 } 1120 1121 static int bcmasp_get_phys_port_name(struct net_device *dev, 1122 char *name, size_t len) 1123 { 1124 struct bcmasp_intf *intf = netdev_priv(dev); 1125 1126 if (snprintf(name, len, "p%d", intf->port) >= len) 1127 return -EINVAL; 1128 1129 return 0; 1130 } 1131 1132 static void bcmasp_get_stats64(struct net_device *dev, 1133 struct rtnl_link_stats64 *stats) 1134 { 1135 struct bcmasp_intf *intf = netdev_priv(dev); 1136 struct bcmasp_intf_stats64 *lstats; 1137 unsigned int start; 1138 1139 lstats = &intf->stats64; 1140 1141 do { 1142 start = u64_stats_fetch_begin(&lstats->syncp); 1143 stats->rx_packets = u64_stats_read(&lstats->rx_packets); 1144 stats->rx_bytes = u64_stats_read(&lstats->rx_bytes); 1145 stats->rx_dropped = u64_stats_read(&lstats->rx_dropped); 1146 stats->rx_crc_errors = u64_stats_read(&lstats->rx_crc_errs); 1147 stats->rx_frame_errors = u64_stats_read(&lstats->rx_sym_errs); 1148 stats->rx_errors = stats->rx_crc_errors + stats->rx_frame_errors; 1149 1150 stats->tx_packets = u64_stats_read(&lstats->tx_packets); 1151 stats->tx_bytes = u64_stats_read(&lstats->tx_bytes); 1152 } while (u64_stats_fetch_retry(&lstats->syncp, start)); 1153 } 1154 1155 static const struct net_device_ops bcmasp_netdev_ops = { 1156 .ndo_open = bcmasp_open, 1157 .ndo_stop = bcmasp_stop, 1158 .ndo_start_xmit = bcmasp_xmit, 1159 .ndo_tx_timeout = bcmasp_tx_timeout, 1160 .ndo_set_rx_mode = bcmasp_set_rx_mode, 1161 .ndo_get_phys_port_name = bcmasp_get_phys_port_name, 1162 .ndo_eth_ioctl = phy_do_ioctl_running, 1163 .ndo_set_mac_address = eth_mac_addr, 1164 .ndo_get_stats64 = bcmasp_get_stats64, 1165 }; 1166 1167 static void bcmasp_map_res(struct bcmasp_priv *priv, struct bcmasp_intf *intf) 1168 { 1169 /* Per port */ 1170 intf->res.umac = priv->base + UMC_OFFSET(intf); 1171 intf->res.umac2fb = priv->base + (priv->hw_info->umac2fb + 1172 (intf->port * 0x4)); 1173 intf->res.rgmii = priv->base + RGMII_OFFSET(intf); 1174 1175 /* Per ch */ 1176 intf->tx_spb_dma = priv->base + TX_SPB_DMA_OFFSET(intf); 1177 intf->res.tx_spb_ctrl = priv->base + TX_SPB_CTRL_OFFSET(intf); 1178 intf->res.tx_spb_top = priv->base + TX_SPB_TOP_OFFSET(intf); 1179 intf->res.tx_epkt_core = priv->base + TX_EPKT_C_OFFSET(intf); 1180 intf->res.tx_pause_ctrl = priv->base + TX_PAUSE_CTRL_OFFSET(intf); 1181 1182 intf->rx_edpkt_dma = priv->base + RX_EDPKT_DMA_OFFSET(intf); 1183 intf->rx_edpkt_cfg = priv->base + RX_EDPKT_CFG_OFFSET(intf); 1184 } 1185 1186 #define MAX_IRQ_STR_LEN 64 1187 struct bcmasp_intf *bcmasp_interface_create(struct bcmasp_priv *priv, 1188 struct device_node *ndev_dn, int i) 1189 { 1190 struct device *dev = &priv->pdev->dev; 1191 struct bcmasp_intf *intf; 1192 struct net_device *ndev; 1193 int ch, port, ret; 1194 1195 if (of_property_read_u32(ndev_dn, "reg", &port)) { 1196 dev_warn(dev, "%s: invalid port number\n", ndev_dn->name); 1197 goto err; 1198 } 1199 1200 if (of_property_read_u32(ndev_dn, "brcm,channel", &ch)) { 1201 dev_warn(dev, "%s: invalid ch number\n", ndev_dn->name); 1202 goto err; 1203 } 1204 1205 ndev = alloc_etherdev(sizeof(struct bcmasp_intf)); 1206 if (!ndev) { 1207 dev_warn(dev, "%s: unable to alloc ndev\n", ndev_dn->name); 1208 goto err; 1209 } 1210 intf = netdev_priv(ndev); 1211 1212 intf->parent = priv; 1213 intf->ndev = ndev; 1214 intf->channel = ch; 1215 intf->port = port; 1216 intf->ndev_dn = ndev_dn; 1217 intf->index = i; 1218 1219 ret = of_get_phy_mode(ndev_dn, &intf->phy_interface); 1220 if (ret < 0) { 1221 dev_err(dev, "invalid PHY mode property\n"); 1222 goto err_free_netdev; 1223 } 1224 1225 if (intf->phy_interface == PHY_INTERFACE_MODE_INTERNAL) 1226 intf->internal_phy = true; 1227 1228 intf->phy_dn = of_parse_phandle(ndev_dn, "phy-handle", 0); 1229 if (!intf->phy_dn && of_phy_is_fixed_link(ndev_dn)) { 1230 ret = of_phy_register_fixed_link(ndev_dn); 1231 if (ret) { 1232 dev_warn(dev, "%s: failed to register fixed PHY\n", 1233 ndev_dn->name); 1234 goto err_free_netdev; 1235 } 1236 intf->phy_dn = ndev_dn; 1237 } 1238 1239 /* Map resource */ 1240 bcmasp_map_res(priv, intf); 1241 1242 if ((!phy_interface_mode_is_rgmii(intf->phy_interface) && 1243 intf->phy_interface != PHY_INTERFACE_MODE_MII && 1244 intf->phy_interface != PHY_INTERFACE_MODE_INTERNAL) || 1245 (intf->port != 1 && intf->internal_phy)) { 1246 netdev_err(intf->ndev, "invalid PHY mode: %s for port %d\n", 1247 phy_modes(intf->phy_interface), intf->port); 1248 ret = -EINVAL; 1249 goto err_free_netdev; 1250 } 1251 1252 ret = of_get_ethdev_address(ndev_dn, ndev); 1253 if (ret) { 1254 netdev_warn(ndev, "using random Ethernet MAC\n"); 1255 eth_hw_addr_random(ndev); 1256 } 1257 1258 SET_NETDEV_DEV(ndev, dev); 1259 intf->ops = &bcmasp_intf_ops; 1260 ndev->netdev_ops = &bcmasp_netdev_ops; 1261 ndev->ethtool_ops = &bcmasp_ethtool_ops; 1262 intf->msg_enable = netif_msg_init(-1, NETIF_MSG_DRV | 1263 NETIF_MSG_PROBE | 1264 NETIF_MSG_LINK); 1265 ndev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | 1266 NETIF_F_RXCSUM; 1267 ndev->hw_features |= ndev->features; 1268 ndev->needed_headroom += sizeof(struct bcmasp_pkt_offload); 1269 1270 return intf; 1271 1272 err_free_netdev: 1273 free_netdev(ndev); 1274 err: 1275 return NULL; 1276 } 1277 1278 void bcmasp_interface_destroy(struct bcmasp_intf *intf) 1279 { 1280 if (intf->ndev->reg_state == NETREG_REGISTERED) 1281 unregister_netdev(intf->ndev); 1282 if (of_phy_is_fixed_link(intf->ndev_dn)) 1283 of_phy_deregister_fixed_link(intf->ndev_dn); 1284 free_netdev(intf->ndev); 1285 } 1286 1287 static void bcmasp_suspend_to_wol(struct bcmasp_intf *intf) 1288 { 1289 struct net_device *ndev = intf->ndev; 1290 u32 reg; 1291 1292 reg = umac_rl(intf, UMC_MPD_CTRL); 1293 if (intf->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE)) 1294 reg |= UMC_MPD_CTRL_MPD_EN; 1295 reg &= ~UMC_MPD_CTRL_PSW_EN; 1296 if (intf->wolopts & WAKE_MAGICSECURE) { 1297 /* Program the SecureOn password */ 1298 umac_wl(intf, get_unaligned_be16(&intf->sopass[0]), 1299 UMC_PSW_MS); 1300 umac_wl(intf, get_unaligned_be32(&intf->sopass[2]), 1301 UMC_PSW_LS); 1302 reg |= UMC_MPD_CTRL_PSW_EN; 1303 } 1304 umac_wl(intf, reg, UMC_MPD_CTRL); 1305 1306 if (intf->wolopts & WAKE_FILTER) 1307 bcmasp_netfilt_suspend(intf); 1308 1309 /* UniMAC receive needs to be turned on */ 1310 umac_enable_set(intf, UMC_CMD_RX_EN, 1); 1311 1312 if (intf->parent->wol_irq > 0) { 1313 wakeup_intr2_core_wl(intf->parent, 0xffffffff, 1314 ASP_WAKEUP_INTR2_MASK_CLEAR); 1315 } 1316 1317 if (intf->eee.eee_enabled && intf->parent->eee_fixup) 1318 intf->parent->eee_fixup(intf, true); 1319 1320 netif_dbg(intf, wol, ndev, "entered WOL mode\n"); 1321 } 1322 1323 int bcmasp_interface_suspend(struct bcmasp_intf *intf) 1324 { 1325 struct device *kdev = &intf->parent->pdev->dev; 1326 struct net_device *dev = intf->ndev; 1327 int ret = 0; 1328 1329 if (!netif_running(dev)) 1330 return 0; 1331 1332 netif_device_detach(dev); 1333 1334 bcmasp_netif_deinit(dev); 1335 1336 if (!intf->wolopts) { 1337 ret = phy_suspend(dev->phydev); 1338 if (ret) 1339 goto out; 1340 1341 if (intf->internal_phy) 1342 bcmasp_ephy_enable_set(intf, false); 1343 else 1344 bcmasp_rgmii_mode_en_set(intf, false); 1345 1346 /* If Wake-on-LAN is disabled, we can safely 1347 * disable the network interface clocks. 1348 */ 1349 bcmasp_core_clock_set_intf(intf, false); 1350 } 1351 1352 if (device_may_wakeup(kdev) && intf->wolopts) 1353 bcmasp_suspend_to_wol(intf); 1354 1355 clk_disable_unprepare(intf->parent->clk); 1356 1357 return ret; 1358 1359 out: 1360 bcmasp_netif_init(dev, false); 1361 return ret; 1362 } 1363 1364 static void bcmasp_resume_from_wol(struct bcmasp_intf *intf) 1365 { 1366 u32 reg; 1367 1368 if (intf->eee.eee_enabled && intf->parent->eee_fixup) 1369 intf->parent->eee_fixup(intf, false); 1370 1371 reg = umac_rl(intf, UMC_MPD_CTRL); 1372 reg &= ~UMC_MPD_CTRL_MPD_EN; 1373 umac_wl(intf, reg, UMC_MPD_CTRL); 1374 1375 if (intf->parent->wol_irq > 0) { 1376 wakeup_intr2_core_wl(intf->parent, 0xffffffff, 1377 ASP_WAKEUP_INTR2_MASK_SET); 1378 } 1379 } 1380 1381 int bcmasp_interface_resume(struct bcmasp_intf *intf) 1382 { 1383 struct net_device *dev = intf->ndev; 1384 int ret; 1385 1386 if (!netif_running(dev)) 1387 return 0; 1388 1389 ret = clk_prepare_enable(intf->parent->clk); 1390 if (ret) 1391 return ret; 1392 1393 ret = bcmasp_netif_init(dev, false); 1394 if (ret) 1395 goto out; 1396 1397 bcmasp_resume_from_wol(intf); 1398 1399 if (intf->eee.eee_enabled) 1400 bcmasp_eee_enable_set(intf, true); 1401 1402 netif_device_attach(dev); 1403 1404 return 0; 1405 1406 out: 1407 clk_disable_unprepare(intf->parent->clk); 1408 return ret; 1409 } 1410