1 /* 2 * Copyright(c) 2006 - 2007 Atheros Corporation. All rights reserved. 3 * Copyright(c) 2007 - 2008 Chris Snook <csnook@redhat.com> 4 * 5 * Derived from Intel e1000 driver 6 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the Free 10 * Software Foundation; either version 2 of the License, or (at your option) 11 * any later version. 12 * 13 * This program is distributed in the hope that it will be useful, but WITHOUT 14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 16 * more details. 17 * 18 * You should have received a copy of the GNU General Public License along with 19 * this program; if not, write to the Free Software Foundation, Inc., 59 20 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 21 */ 22 23 #include <linux/atomic.h> 24 #include <linux/crc32.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/etherdevice.h> 27 #include <linux/ethtool.h> 28 #include <linux/hardirq.h> 29 #include <linux/if_vlan.h> 30 #include <linux/in.h> 31 #include <linux/interrupt.h> 32 #include <linux/ip.h> 33 #include <linux/irqflags.h> 34 #include <linux/irqreturn.h> 35 #include <linux/mii.h> 36 #include <linux/net.h> 37 #include <linux/netdevice.h> 38 #include <linux/pci.h> 39 #include <linux/pci_ids.h> 40 #include <linux/pm.h> 41 #include <linux/skbuff.h> 42 #include <linux/slab.h> 43 #include <linux/spinlock.h> 44 #include <linux/string.h> 45 #include <linux/tcp.h> 46 #include <linux/timer.h> 47 #include <linux/types.h> 48 #include <linux/workqueue.h> 49 50 #include "atl2.h" 51 52 #define ATL2_DRV_VERSION "2.2.3" 53 54 static const char atl2_driver_name[] = "atl2"; 55 static const char atl2_driver_string[] = "Atheros(R) L2 Ethernet Driver"; 56 static const char atl2_copyright[] = "Copyright (c) 2007 Atheros Corporation."; 57 static const char atl2_driver_version[] = ATL2_DRV_VERSION; 58 59 MODULE_AUTHOR("Atheros Corporation <xiong.huang@atheros.com>, Chris Snook <csnook@redhat.com>"); 60 MODULE_DESCRIPTION("Atheros Fast Ethernet Network Driver"); 61 MODULE_LICENSE("GPL"); 62 MODULE_VERSION(ATL2_DRV_VERSION); 63 64 /* 65 * atl2_pci_tbl - PCI Device ID Table 66 */ 67 static DEFINE_PCI_DEVICE_TABLE(atl2_pci_tbl) = { 68 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L2)}, 69 /* required last entry */ 70 {0,} 71 }; 72 MODULE_DEVICE_TABLE(pci, atl2_pci_tbl); 73 74 static void atl2_set_ethtool_ops(struct net_device *netdev); 75 76 static void atl2_check_options(struct atl2_adapter *adapter); 77 78 /* 79 * atl2_sw_init - Initialize general software structures (struct atl2_adapter) 80 * @adapter: board private structure to initialize 81 * 82 * atl2_sw_init initializes the Adapter private data structure. 83 * Fields are initialized based on PCI device information and 84 * OS network device settings (MTU size). 85 */ 86 static int __devinit atl2_sw_init(struct atl2_adapter *adapter) 87 { 88 struct atl2_hw *hw = &adapter->hw; 89 struct pci_dev *pdev = adapter->pdev; 90 91 /* PCI config space info */ 92 hw->vendor_id = pdev->vendor; 93 hw->device_id = pdev->device; 94 hw->subsystem_vendor_id = pdev->subsystem_vendor; 95 hw->subsystem_id = pdev->subsystem_device; 96 hw->revision_id = pdev->revision; 97 98 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word); 99 100 adapter->wol = 0; 101 adapter->ict = 50000; /* ~100ms */ 102 adapter->link_speed = SPEED_0; /* hardware init */ 103 adapter->link_duplex = FULL_DUPLEX; 104 105 hw->phy_configured = false; 106 hw->preamble_len = 7; 107 hw->ipgt = 0x60; 108 hw->min_ifg = 0x50; 109 hw->ipgr1 = 0x40; 110 hw->ipgr2 = 0x60; 111 hw->retry_buf = 2; 112 hw->max_retry = 0xf; 113 hw->lcol = 0x37; 114 hw->jam_ipg = 7; 115 hw->fc_rxd_hi = 0; 116 hw->fc_rxd_lo = 0; 117 hw->max_frame_size = adapter->netdev->mtu; 118 119 spin_lock_init(&adapter->stats_lock); 120 121 set_bit(__ATL2_DOWN, &adapter->flags); 122 123 return 0; 124 } 125 126 /* 127 * atl2_set_multi - Multicast and Promiscuous mode set 128 * @netdev: network interface device structure 129 * 130 * The set_multi entry point is called whenever the multicast address 131 * list or the network interface flags are updated. This routine is 132 * responsible for configuring the hardware for proper multicast, 133 * promiscuous mode, and all-multi behavior. 134 */ 135 static void atl2_set_multi(struct net_device *netdev) 136 { 137 struct atl2_adapter *adapter = netdev_priv(netdev); 138 struct atl2_hw *hw = &adapter->hw; 139 struct netdev_hw_addr *ha; 140 u32 rctl; 141 u32 hash_value; 142 143 /* Check for Promiscuous and All Multicast modes */ 144 rctl = ATL2_READ_REG(hw, REG_MAC_CTRL); 145 146 if (netdev->flags & IFF_PROMISC) { 147 rctl |= MAC_CTRL_PROMIS_EN; 148 } else if (netdev->flags & IFF_ALLMULTI) { 149 rctl |= MAC_CTRL_MC_ALL_EN; 150 rctl &= ~MAC_CTRL_PROMIS_EN; 151 } else 152 rctl &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN); 153 154 ATL2_WRITE_REG(hw, REG_MAC_CTRL, rctl); 155 156 /* clear the old settings from the multicast hash table */ 157 ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0); 158 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0); 159 160 /* comoute mc addresses' hash value ,and put it into hash table */ 161 netdev_for_each_mc_addr(ha, netdev) { 162 hash_value = atl2_hash_mc_addr(hw, ha->addr); 163 atl2_hash_set(hw, hash_value); 164 } 165 } 166 167 static void init_ring_ptrs(struct atl2_adapter *adapter) 168 { 169 /* Read / Write Ptr Initialize: */ 170 adapter->txd_write_ptr = 0; 171 atomic_set(&adapter->txd_read_ptr, 0); 172 173 adapter->rxd_read_ptr = 0; 174 adapter->rxd_write_ptr = 0; 175 176 atomic_set(&adapter->txs_write_ptr, 0); 177 adapter->txs_next_clear = 0; 178 } 179 180 /* 181 * atl2_configure - Configure Transmit&Receive Unit after Reset 182 * @adapter: board private structure 183 * 184 * Configure the Tx /Rx unit of the MAC after a reset. 185 */ 186 static int atl2_configure(struct atl2_adapter *adapter) 187 { 188 struct atl2_hw *hw = &adapter->hw; 189 u32 value; 190 191 /* clear interrupt status */ 192 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0xffffffff); 193 194 /* set MAC Address */ 195 value = (((u32)hw->mac_addr[2]) << 24) | 196 (((u32)hw->mac_addr[3]) << 16) | 197 (((u32)hw->mac_addr[4]) << 8) | 198 (((u32)hw->mac_addr[5])); 199 ATL2_WRITE_REG(hw, REG_MAC_STA_ADDR, value); 200 value = (((u32)hw->mac_addr[0]) << 8) | 201 (((u32)hw->mac_addr[1])); 202 ATL2_WRITE_REG(hw, (REG_MAC_STA_ADDR+4), value); 203 204 /* HI base address */ 205 ATL2_WRITE_REG(hw, REG_DESC_BASE_ADDR_HI, 206 (u32)((adapter->ring_dma & 0xffffffff00000000ULL) >> 32)); 207 208 /* LO base address */ 209 ATL2_WRITE_REG(hw, REG_TXD_BASE_ADDR_LO, 210 (u32)(adapter->txd_dma & 0x00000000ffffffffULL)); 211 ATL2_WRITE_REG(hw, REG_TXS_BASE_ADDR_LO, 212 (u32)(adapter->txs_dma & 0x00000000ffffffffULL)); 213 ATL2_WRITE_REG(hw, REG_RXD_BASE_ADDR_LO, 214 (u32)(adapter->rxd_dma & 0x00000000ffffffffULL)); 215 216 /* element count */ 217 ATL2_WRITE_REGW(hw, REG_TXD_MEM_SIZE, (u16)(adapter->txd_ring_size/4)); 218 ATL2_WRITE_REGW(hw, REG_TXS_MEM_SIZE, (u16)adapter->txs_ring_size); 219 ATL2_WRITE_REGW(hw, REG_RXD_BUF_NUM, (u16)adapter->rxd_ring_size); 220 221 /* config Internal SRAM */ 222 /* 223 ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_tx_end); 224 ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_rx_end); 225 */ 226 227 /* config IPG/IFG */ 228 value = (((u32)hw->ipgt & MAC_IPG_IFG_IPGT_MASK) << 229 MAC_IPG_IFG_IPGT_SHIFT) | 230 (((u32)hw->min_ifg & MAC_IPG_IFG_MIFG_MASK) << 231 MAC_IPG_IFG_MIFG_SHIFT) | 232 (((u32)hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK) << 233 MAC_IPG_IFG_IPGR1_SHIFT)| 234 (((u32)hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK) << 235 MAC_IPG_IFG_IPGR2_SHIFT); 236 ATL2_WRITE_REG(hw, REG_MAC_IPG_IFG, value); 237 238 /* config Half-Duplex Control */ 239 value = ((u32)hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) | 240 (((u32)hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK) << 241 MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) | 242 MAC_HALF_DUPLX_CTRL_EXC_DEF_EN | 243 (0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) | 244 (((u32)hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK) << 245 MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT); 246 ATL2_WRITE_REG(hw, REG_MAC_HALF_DUPLX_CTRL, value); 247 248 /* set Interrupt Moderator Timer */ 249 ATL2_WRITE_REGW(hw, REG_IRQ_MODU_TIMER_INIT, adapter->imt); 250 ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_ITIMER_EN); 251 252 /* set Interrupt Clear Timer */ 253 ATL2_WRITE_REGW(hw, REG_CMBDISDMA_TIMER, adapter->ict); 254 255 /* set MTU */ 256 ATL2_WRITE_REG(hw, REG_MTU, adapter->netdev->mtu + 257 ENET_HEADER_SIZE + VLAN_SIZE + ETHERNET_FCS_SIZE); 258 259 /* 1590 */ 260 ATL2_WRITE_REG(hw, REG_TX_CUT_THRESH, 0x177); 261 262 /* flow control */ 263 ATL2_WRITE_REGW(hw, REG_PAUSE_ON_TH, hw->fc_rxd_hi); 264 ATL2_WRITE_REGW(hw, REG_PAUSE_OFF_TH, hw->fc_rxd_lo); 265 266 /* Init mailbox */ 267 ATL2_WRITE_REGW(hw, REG_MB_TXD_WR_IDX, (u16)adapter->txd_write_ptr); 268 ATL2_WRITE_REGW(hw, REG_MB_RXD_RD_IDX, (u16)adapter->rxd_read_ptr); 269 270 /* enable DMA read/write */ 271 ATL2_WRITE_REGB(hw, REG_DMAR, DMAR_EN); 272 ATL2_WRITE_REGB(hw, REG_DMAW, DMAW_EN); 273 274 value = ATL2_READ_REG(&adapter->hw, REG_ISR); 275 if ((value & ISR_PHY_LINKDOWN) != 0) 276 value = 1; /* config failed */ 277 else 278 value = 0; 279 280 /* clear all interrupt status */ 281 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0x3fffffff); 282 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0); 283 return value; 284 } 285 286 /* 287 * atl2_setup_ring_resources - allocate Tx / RX descriptor resources 288 * @adapter: board private structure 289 * 290 * Return 0 on success, negative on failure 291 */ 292 static s32 atl2_setup_ring_resources(struct atl2_adapter *adapter) 293 { 294 struct pci_dev *pdev = adapter->pdev; 295 int size; 296 u8 offset = 0; 297 298 /* real ring DMA buffer */ 299 adapter->ring_size = size = 300 adapter->txd_ring_size * 1 + 7 + /* dword align */ 301 adapter->txs_ring_size * 4 + 7 + /* dword align */ 302 adapter->rxd_ring_size * 1536 + 127; /* 128bytes align */ 303 304 adapter->ring_vir_addr = pci_alloc_consistent(pdev, size, 305 &adapter->ring_dma); 306 if (!adapter->ring_vir_addr) 307 return -ENOMEM; 308 memset(adapter->ring_vir_addr, 0, adapter->ring_size); 309 310 /* Init TXD Ring */ 311 adapter->txd_dma = adapter->ring_dma ; 312 offset = (adapter->txd_dma & 0x7) ? (8 - (adapter->txd_dma & 0x7)) : 0; 313 adapter->txd_dma += offset; 314 adapter->txd_ring = adapter->ring_vir_addr + offset; 315 316 /* Init TXS Ring */ 317 adapter->txs_dma = adapter->txd_dma + adapter->txd_ring_size; 318 offset = (adapter->txs_dma & 0x7) ? (8 - (adapter->txs_dma & 0x7)) : 0; 319 adapter->txs_dma += offset; 320 adapter->txs_ring = (struct tx_pkt_status *) 321 (((u8 *)adapter->txd_ring) + (adapter->txd_ring_size + offset)); 322 323 /* Init RXD Ring */ 324 adapter->rxd_dma = adapter->txs_dma + adapter->txs_ring_size * 4; 325 offset = (adapter->rxd_dma & 127) ? 326 (128 - (adapter->rxd_dma & 127)) : 0; 327 if (offset > 7) 328 offset -= 8; 329 else 330 offset += (128 - 8); 331 332 adapter->rxd_dma += offset; 333 adapter->rxd_ring = (struct rx_desc *) (((u8 *)adapter->txs_ring) + 334 (adapter->txs_ring_size * 4 + offset)); 335 336 /* 337 * Read / Write Ptr Initialize: 338 * init_ring_ptrs(adapter); 339 */ 340 return 0; 341 } 342 343 /* 344 * atl2_irq_enable - Enable default interrupt generation settings 345 * @adapter: board private structure 346 */ 347 static inline void atl2_irq_enable(struct atl2_adapter *adapter) 348 { 349 ATL2_WRITE_REG(&adapter->hw, REG_IMR, IMR_NORMAL_MASK); 350 ATL2_WRITE_FLUSH(&adapter->hw); 351 } 352 353 /* 354 * atl2_irq_disable - Mask off interrupt generation on the NIC 355 * @adapter: board private structure 356 */ 357 static inline void atl2_irq_disable(struct atl2_adapter *adapter) 358 { 359 ATL2_WRITE_REG(&adapter->hw, REG_IMR, 0); 360 ATL2_WRITE_FLUSH(&adapter->hw); 361 synchronize_irq(adapter->pdev->irq); 362 } 363 364 static void __atl2_vlan_mode(netdev_features_t features, u32 *ctrl) 365 { 366 if (features & NETIF_F_HW_VLAN_RX) { 367 /* enable VLAN tag insert/strip */ 368 *ctrl |= MAC_CTRL_RMV_VLAN; 369 } else { 370 /* disable VLAN tag insert/strip */ 371 *ctrl &= ~MAC_CTRL_RMV_VLAN; 372 } 373 } 374 375 static void atl2_vlan_mode(struct net_device *netdev, 376 netdev_features_t features) 377 { 378 struct atl2_adapter *adapter = netdev_priv(netdev); 379 u32 ctrl; 380 381 atl2_irq_disable(adapter); 382 383 ctrl = ATL2_READ_REG(&adapter->hw, REG_MAC_CTRL); 384 __atl2_vlan_mode(features, &ctrl); 385 ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl); 386 387 atl2_irq_enable(adapter); 388 } 389 390 static void atl2_restore_vlan(struct atl2_adapter *adapter) 391 { 392 atl2_vlan_mode(adapter->netdev, adapter->netdev->features); 393 } 394 395 static netdev_features_t atl2_fix_features(struct net_device *netdev, 396 netdev_features_t features) 397 { 398 /* 399 * Since there is no support for separate rx/tx vlan accel 400 * enable/disable make sure tx flag is always in same state as rx. 401 */ 402 if (features & NETIF_F_HW_VLAN_RX) 403 features |= NETIF_F_HW_VLAN_TX; 404 else 405 features &= ~NETIF_F_HW_VLAN_TX; 406 407 return features; 408 } 409 410 static int atl2_set_features(struct net_device *netdev, 411 netdev_features_t features) 412 { 413 netdev_features_t changed = netdev->features ^ features; 414 415 if (changed & NETIF_F_HW_VLAN_RX) 416 atl2_vlan_mode(netdev, features); 417 418 return 0; 419 } 420 421 static void atl2_intr_rx(struct atl2_adapter *adapter) 422 { 423 struct net_device *netdev = adapter->netdev; 424 struct rx_desc *rxd; 425 struct sk_buff *skb; 426 427 do { 428 rxd = adapter->rxd_ring+adapter->rxd_write_ptr; 429 if (!rxd->status.update) 430 break; /* end of tx */ 431 432 /* clear this flag at once */ 433 rxd->status.update = 0; 434 435 if (rxd->status.ok && rxd->status.pkt_size >= 60) { 436 int rx_size = (int)(rxd->status.pkt_size - 4); 437 /* alloc new buffer */ 438 skb = netdev_alloc_skb_ip_align(netdev, rx_size); 439 if (NULL == skb) { 440 printk(KERN_WARNING 441 "%s: Mem squeeze, deferring packet.\n", 442 netdev->name); 443 /* 444 * Check that some rx space is free. If not, 445 * free one and mark stats->rx_dropped++. 446 */ 447 netdev->stats.rx_dropped++; 448 break; 449 } 450 memcpy(skb->data, rxd->packet, rx_size); 451 skb_put(skb, rx_size); 452 skb->protocol = eth_type_trans(skb, netdev); 453 if (rxd->status.vlan) { 454 u16 vlan_tag = (rxd->status.vtag>>4) | 455 ((rxd->status.vtag&7) << 13) | 456 ((rxd->status.vtag&8) << 9); 457 458 __vlan_hwaccel_put_tag(skb, vlan_tag); 459 } 460 netif_rx(skb); 461 netdev->stats.rx_bytes += rx_size; 462 netdev->stats.rx_packets++; 463 } else { 464 netdev->stats.rx_errors++; 465 466 if (rxd->status.ok && rxd->status.pkt_size <= 60) 467 netdev->stats.rx_length_errors++; 468 if (rxd->status.mcast) 469 netdev->stats.multicast++; 470 if (rxd->status.crc) 471 netdev->stats.rx_crc_errors++; 472 if (rxd->status.align) 473 netdev->stats.rx_frame_errors++; 474 } 475 476 /* advance write ptr */ 477 if (++adapter->rxd_write_ptr == adapter->rxd_ring_size) 478 adapter->rxd_write_ptr = 0; 479 } while (1); 480 481 /* update mailbox? */ 482 adapter->rxd_read_ptr = adapter->rxd_write_ptr; 483 ATL2_WRITE_REGW(&adapter->hw, REG_MB_RXD_RD_IDX, adapter->rxd_read_ptr); 484 } 485 486 static void atl2_intr_tx(struct atl2_adapter *adapter) 487 { 488 struct net_device *netdev = adapter->netdev; 489 u32 txd_read_ptr; 490 u32 txs_write_ptr; 491 struct tx_pkt_status *txs; 492 struct tx_pkt_header *txph; 493 int free_hole = 0; 494 495 do { 496 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr); 497 txs = adapter->txs_ring + txs_write_ptr; 498 if (!txs->update) 499 break; /* tx stop here */ 500 501 free_hole = 1; 502 txs->update = 0; 503 504 if (++txs_write_ptr == adapter->txs_ring_size) 505 txs_write_ptr = 0; 506 atomic_set(&adapter->txs_write_ptr, (int)txs_write_ptr); 507 508 txd_read_ptr = (u32) atomic_read(&adapter->txd_read_ptr); 509 txph = (struct tx_pkt_header *) 510 (((u8 *)adapter->txd_ring) + txd_read_ptr); 511 512 if (txph->pkt_size != txs->pkt_size) { 513 struct tx_pkt_status *old_txs = txs; 514 printk(KERN_WARNING 515 "%s: txs packet size not consistent with txd" 516 " txd_:0x%08x, txs_:0x%08x!\n", 517 adapter->netdev->name, 518 *(u32 *)txph, *(u32 *)txs); 519 printk(KERN_WARNING 520 "txd read ptr: 0x%x\n", 521 txd_read_ptr); 522 txs = adapter->txs_ring + txs_write_ptr; 523 printk(KERN_WARNING 524 "txs-behind:0x%08x\n", 525 *(u32 *)txs); 526 if (txs_write_ptr < 2) { 527 txs = adapter->txs_ring + 528 (adapter->txs_ring_size + 529 txs_write_ptr - 2); 530 } else { 531 txs = adapter->txs_ring + (txs_write_ptr - 2); 532 } 533 printk(KERN_WARNING 534 "txs-before:0x%08x\n", 535 *(u32 *)txs); 536 txs = old_txs; 537 } 538 539 /* 4for TPH */ 540 txd_read_ptr += (((u32)(txph->pkt_size) + 7) & ~3); 541 if (txd_read_ptr >= adapter->txd_ring_size) 542 txd_read_ptr -= adapter->txd_ring_size; 543 544 atomic_set(&adapter->txd_read_ptr, (int)txd_read_ptr); 545 546 /* tx statistics: */ 547 if (txs->ok) { 548 netdev->stats.tx_bytes += txs->pkt_size; 549 netdev->stats.tx_packets++; 550 } 551 else 552 netdev->stats.tx_errors++; 553 554 if (txs->defer) 555 netdev->stats.collisions++; 556 if (txs->abort_col) 557 netdev->stats.tx_aborted_errors++; 558 if (txs->late_col) 559 netdev->stats.tx_window_errors++; 560 if (txs->underun) 561 netdev->stats.tx_fifo_errors++; 562 } while (1); 563 564 if (free_hole) { 565 if (netif_queue_stopped(adapter->netdev) && 566 netif_carrier_ok(adapter->netdev)) 567 netif_wake_queue(adapter->netdev); 568 } 569 } 570 571 static void atl2_check_for_link(struct atl2_adapter *adapter) 572 { 573 struct net_device *netdev = adapter->netdev; 574 u16 phy_data = 0; 575 576 spin_lock(&adapter->stats_lock); 577 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data); 578 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data); 579 spin_unlock(&adapter->stats_lock); 580 581 /* notify upper layer link down ASAP */ 582 if (!(phy_data & BMSR_LSTATUS)) { /* Link Down */ 583 if (netif_carrier_ok(netdev)) { /* old link state: Up */ 584 printk(KERN_INFO "%s: %s NIC Link is Down\n", 585 atl2_driver_name, netdev->name); 586 adapter->link_speed = SPEED_0; 587 netif_carrier_off(netdev); 588 netif_stop_queue(netdev); 589 } 590 } 591 schedule_work(&adapter->link_chg_task); 592 } 593 594 static inline void atl2_clear_phy_int(struct atl2_adapter *adapter) 595 { 596 u16 phy_data; 597 spin_lock(&adapter->stats_lock); 598 atl2_read_phy_reg(&adapter->hw, 19, &phy_data); 599 spin_unlock(&adapter->stats_lock); 600 } 601 602 /* 603 * atl2_intr - Interrupt Handler 604 * @irq: interrupt number 605 * @data: pointer to a network interface device structure 606 * @pt_regs: CPU registers structure 607 */ 608 static irqreturn_t atl2_intr(int irq, void *data) 609 { 610 struct atl2_adapter *adapter = netdev_priv(data); 611 struct atl2_hw *hw = &adapter->hw; 612 u32 status; 613 614 status = ATL2_READ_REG(hw, REG_ISR); 615 if (0 == status) 616 return IRQ_NONE; 617 618 /* link event */ 619 if (status & ISR_PHY) 620 atl2_clear_phy_int(adapter); 621 622 /* clear ISR status, and Enable CMB DMA/Disable Interrupt */ 623 ATL2_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT); 624 625 /* check if PCIE PHY Link down */ 626 if (status & ISR_PHY_LINKDOWN) { 627 if (netif_running(adapter->netdev)) { /* reset MAC */ 628 ATL2_WRITE_REG(hw, REG_ISR, 0); 629 ATL2_WRITE_REG(hw, REG_IMR, 0); 630 ATL2_WRITE_FLUSH(hw); 631 schedule_work(&adapter->reset_task); 632 return IRQ_HANDLED; 633 } 634 } 635 636 /* check if DMA read/write error? */ 637 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) { 638 ATL2_WRITE_REG(hw, REG_ISR, 0); 639 ATL2_WRITE_REG(hw, REG_IMR, 0); 640 ATL2_WRITE_FLUSH(hw); 641 schedule_work(&adapter->reset_task); 642 return IRQ_HANDLED; 643 } 644 645 /* link event */ 646 if (status & (ISR_PHY | ISR_MANUAL)) { 647 adapter->netdev->stats.tx_carrier_errors++; 648 atl2_check_for_link(adapter); 649 } 650 651 /* transmit event */ 652 if (status & ISR_TX_EVENT) 653 atl2_intr_tx(adapter); 654 655 /* rx exception */ 656 if (status & ISR_RX_EVENT) 657 atl2_intr_rx(adapter); 658 659 /* re-enable Interrupt */ 660 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0); 661 return IRQ_HANDLED; 662 } 663 664 static int atl2_request_irq(struct atl2_adapter *adapter) 665 { 666 struct net_device *netdev = adapter->netdev; 667 int flags, err = 0; 668 669 flags = IRQF_SHARED; 670 adapter->have_msi = true; 671 err = pci_enable_msi(adapter->pdev); 672 if (err) 673 adapter->have_msi = false; 674 675 if (adapter->have_msi) 676 flags &= ~IRQF_SHARED; 677 678 return request_irq(adapter->pdev->irq, atl2_intr, flags, netdev->name, 679 netdev); 680 } 681 682 /* 683 * atl2_free_ring_resources - Free Tx / RX descriptor Resources 684 * @adapter: board private structure 685 * 686 * Free all transmit software resources 687 */ 688 static void atl2_free_ring_resources(struct atl2_adapter *adapter) 689 { 690 struct pci_dev *pdev = adapter->pdev; 691 pci_free_consistent(pdev, adapter->ring_size, adapter->ring_vir_addr, 692 adapter->ring_dma); 693 } 694 695 /* 696 * atl2_open - Called when a network interface is made active 697 * @netdev: network interface device structure 698 * 699 * Returns 0 on success, negative value on failure 700 * 701 * The open entry point is called when a network interface is made 702 * active by the system (IFF_UP). At this point all resources needed 703 * for transmit and receive operations are allocated, the interrupt 704 * handler is registered with the OS, the watchdog timer is started, 705 * and the stack is notified that the interface is ready. 706 */ 707 static int atl2_open(struct net_device *netdev) 708 { 709 struct atl2_adapter *adapter = netdev_priv(netdev); 710 int err; 711 u32 val; 712 713 /* disallow open during test */ 714 if (test_bit(__ATL2_TESTING, &adapter->flags)) 715 return -EBUSY; 716 717 /* allocate transmit descriptors */ 718 err = atl2_setup_ring_resources(adapter); 719 if (err) 720 return err; 721 722 err = atl2_init_hw(&adapter->hw); 723 if (err) { 724 err = -EIO; 725 goto err_init_hw; 726 } 727 728 /* hardware has been reset, we need to reload some things */ 729 atl2_set_multi(netdev); 730 init_ring_ptrs(adapter); 731 732 atl2_restore_vlan(adapter); 733 734 if (atl2_configure(adapter)) { 735 err = -EIO; 736 goto err_config; 737 } 738 739 err = atl2_request_irq(adapter); 740 if (err) 741 goto err_req_irq; 742 743 clear_bit(__ATL2_DOWN, &adapter->flags); 744 745 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 4*HZ)); 746 747 val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL); 748 ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, 749 val | MASTER_CTRL_MANUAL_INT); 750 751 atl2_irq_enable(adapter); 752 753 return 0; 754 755 err_init_hw: 756 err_req_irq: 757 err_config: 758 atl2_free_ring_resources(adapter); 759 atl2_reset_hw(&adapter->hw); 760 761 return err; 762 } 763 764 static void atl2_down(struct atl2_adapter *adapter) 765 { 766 struct net_device *netdev = adapter->netdev; 767 768 /* signal that we're down so the interrupt handler does not 769 * reschedule our watchdog timer */ 770 set_bit(__ATL2_DOWN, &adapter->flags); 771 772 netif_tx_disable(netdev); 773 774 /* reset MAC to disable all RX/TX */ 775 atl2_reset_hw(&adapter->hw); 776 msleep(1); 777 778 atl2_irq_disable(adapter); 779 780 del_timer_sync(&adapter->watchdog_timer); 781 del_timer_sync(&adapter->phy_config_timer); 782 clear_bit(0, &adapter->cfg_phy); 783 784 netif_carrier_off(netdev); 785 adapter->link_speed = SPEED_0; 786 adapter->link_duplex = -1; 787 } 788 789 static void atl2_free_irq(struct atl2_adapter *adapter) 790 { 791 struct net_device *netdev = adapter->netdev; 792 793 free_irq(adapter->pdev->irq, netdev); 794 795 #ifdef CONFIG_PCI_MSI 796 if (adapter->have_msi) 797 pci_disable_msi(adapter->pdev); 798 #endif 799 } 800 801 /* 802 * atl2_close - Disables a network interface 803 * @netdev: network interface device structure 804 * 805 * Returns 0, this is not allowed to fail 806 * 807 * The close entry point is called when an interface is de-activated 808 * by the OS. The hardware is still under the drivers control, but 809 * needs to be disabled. A global MAC reset is issued to stop the 810 * hardware, and all transmit and receive resources are freed. 811 */ 812 static int atl2_close(struct net_device *netdev) 813 { 814 struct atl2_adapter *adapter = netdev_priv(netdev); 815 816 WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags)); 817 818 atl2_down(adapter); 819 atl2_free_irq(adapter); 820 atl2_free_ring_resources(adapter); 821 822 return 0; 823 } 824 825 static inline int TxsFreeUnit(struct atl2_adapter *adapter) 826 { 827 u32 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr); 828 829 return (adapter->txs_next_clear >= txs_write_ptr) ? 830 (int) (adapter->txs_ring_size - adapter->txs_next_clear + 831 txs_write_ptr - 1) : 832 (int) (txs_write_ptr - adapter->txs_next_clear - 1); 833 } 834 835 static inline int TxdFreeBytes(struct atl2_adapter *adapter) 836 { 837 u32 txd_read_ptr = (u32)atomic_read(&adapter->txd_read_ptr); 838 839 return (adapter->txd_write_ptr >= txd_read_ptr) ? 840 (int) (adapter->txd_ring_size - adapter->txd_write_ptr + 841 txd_read_ptr - 1) : 842 (int) (txd_read_ptr - adapter->txd_write_ptr - 1); 843 } 844 845 static netdev_tx_t atl2_xmit_frame(struct sk_buff *skb, 846 struct net_device *netdev) 847 { 848 struct atl2_adapter *adapter = netdev_priv(netdev); 849 struct tx_pkt_header *txph; 850 u32 offset, copy_len; 851 int txs_unused; 852 int txbuf_unused; 853 854 if (test_bit(__ATL2_DOWN, &adapter->flags)) { 855 dev_kfree_skb_any(skb); 856 return NETDEV_TX_OK; 857 } 858 859 if (unlikely(skb->len <= 0)) { 860 dev_kfree_skb_any(skb); 861 return NETDEV_TX_OK; 862 } 863 864 txs_unused = TxsFreeUnit(adapter); 865 txbuf_unused = TxdFreeBytes(adapter); 866 867 if (skb->len + sizeof(struct tx_pkt_header) + 4 > txbuf_unused || 868 txs_unused < 1) { 869 /* not enough resources */ 870 netif_stop_queue(netdev); 871 return NETDEV_TX_BUSY; 872 } 873 874 offset = adapter->txd_write_ptr; 875 876 txph = (struct tx_pkt_header *) (((u8 *)adapter->txd_ring) + offset); 877 878 *(u32 *)txph = 0; 879 txph->pkt_size = skb->len; 880 881 offset += 4; 882 if (offset >= adapter->txd_ring_size) 883 offset -= adapter->txd_ring_size; 884 copy_len = adapter->txd_ring_size - offset; 885 if (copy_len >= skb->len) { 886 memcpy(((u8 *)adapter->txd_ring) + offset, skb->data, skb->len); 887 offset += ((u32)(skb->len + 3) & ~3); 888 } else { 889 memcpy(((u8 *)adapter->txd_ring)+offset, skb->data, copy_len); 890 memcpy((u8 *)adapter->txd_ring, skb->data+copy_len, 891 skb->len-copy_len); 892 offset = ((u32)(skb->len-copy_len + 3) & ~3); 893 } 894 #ifdef NETIF_F_HW_VLAN_TX 895 if (vlan_tx_tag_present(skb)) { 896 u16 vlan_tag = vlan_tx_tag_get(skb); 897 vlan_tag = (vlan_tag << 4) | 898 (vlan_tag >> 13) | 899 ((vlan_tag >> 9) & 0x8); 900 txph->ins_vlan = 1; 901 txph->vlan = vlan_tag; 902 } 903 #endif 904 if (offset >= adapter->txd_ring_size) 905 offset -= adapter->txd_ring_size; 906 adapter->txd_write_ptr = offset; 907 908 /* clear txs before send */ 909 adapter->txs_ring[adapter->txs_next_clear].update = 0; 910 if (++adapter->txs_next_clear == adapter->txs_ring_size) 911 adapter->txs_next_clear = 0; 912 913 ATL2_WRITE_REGW(&adapter->hw, REG_MB_TXD_WR_IDX, 914 (adapter->txd_write_ptr >> 2)); 915 916 mmiowb(); 917 dev_kfree_skb_any(skb); 918 return NETDEV_TX_OK; 919 } 920 921 /* 922 * atl2_change_mtu - Change the Maximum Transfer Unit 923 * @netdev: network interface device structure 924 * @new_mtu: new value for maximum frame size 925 * 926 * Returns 0 on success, negative on failure 927 */ 928 static int atl2_change_mtu(struct net_device *netdev, int new_mtu) 929 { 930 struct atl2_adapter *adapter = netdev_priv(netdev); 931 struct atl2_hw *hw = &adapter->hw; 932 933 if ((new_mtu < 40) || (new_mtu > (ETH_DATA_LEN + VLAN_SIZE))) 934 return -EINVAL; 935 936 /* set MTU */ 937 if (hw->max_frame_size != new_mtu) { 938 netdev->mtu = new_mtu; 939 ATL2_WRITE_REG(hw, REG_MTU, new_mtu + ENET_HEADER_SIZE + 940 VLAN_SIZE + ETHERNET_FCS_SIZE); 941 } 942 943 return 0; 944 } 945 946 /* 947 * atl2_set_mac - Change the Ethernet Address of the NIC 948 * @netdev: network interface device structure 949 * @p: pointer to an address structure 950 * 951 * Returns 0 on success, negative on failure 952 */ 953 static int atl2_set_mac(struct net_device *netdev, void *p) 954 { 955 struct atl2_adapter *adapter = netdev_priv(netdev); 956 struct sockaddr *addr = p; 957 958 if (!is_valid_ether_addr(addr->sa_data)) 959 return -EADDRNOTAVAIL; 960 961 if (netif_running(netdev)) 962 return -EBUSY; 963 964 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 965 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len); 966 967 atl2_set_mac_addr(&adapter->hw); 968 969 return 0; 970 } 971 972 /* 973 * atl2_mii_ioctl - 974 * @netdev: 975 * @ifreq: 976 * @cmd: 977 */ 978 static int atl2_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 979 { 980 struct atl2_adapter *adapter = netdev_priv(netdev); 981 struct mii_ioctl_data *data = if_mii(ifr); 982 unsigned long flags; 983 984 switch (cmd) { 985 case SIOCGMIIPHY: 986 data->phy_id = 0; 987 break; 988 case SIOCGMIIREG: 989 spin_lock_irqsave(&adapter->stats_lock, flags); 990 if (atl2_read_phy_reg(&adapter->hw, 991 data->reg_num & 0x1F, &data->val_out)) { 992 spin_unlock_irqrestore(&adapter->stats_lock, flags); 993 return -EIO; 994 } 995 spin_unlock_irqrestore(&adapter->stats_lock, flags); 996 break; 997 case SIOCSMIIREG: 998 if (data->reg_num & ~(0x1F)) 999 return -EFAULT; 1000 spin_lock_irqsave(&adapter->stats_lock, flags); 1001 if (atl2_write_phy_reg(&adapter->hw, data->reg_num, 1002 data->val_in)) { 1003 spin_unlock_irqrestore(&adapter->stats_lock, flags); 1004 return -EIO; 1005 } 1006 spin_unlock_irqrestore(&adapter->stats_lock, flags); 1007 break; 1008 default: 1009 return -EOPNOTSUPP; 1010 } 1011 return 0; 1012 } 1013 1014 /* 1015 * atl2_ioctl - 1016 * @netdev: 1017 * @ifreq: 1018 * @cmd: 1019 */ 1020 static int atl2_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 1021 { 1022 switch (cmd) { 1023 case SIOCGMIIPHY: 1024 case SIOCGMIIREG: 1025 case SIOCSMIIREG: 1026 return atl2_mii_ioctl(netdev, ifr, cmd); 1027 #ifdef ETHTOOL_OPS_COMPAT 1028 case SIOCETHTOOL: 1029 return ethtool_ioctl(ifr); 1030 #endif 1031 default: 1032 return -EOPNOTSUPP; 1033 } 1034 } 1035 1036 /* 1037 * atl2_tx_timeout - Respond to a Tx Hang 1038 * @netdev: network interface device structure 1039 */ 1040 static void atl2_tx_timeout(struct net_device *netdev) 1041 { 1042 struct atl2_adapter *adapter = netdev_priv(netdev); 1043 1044 /* Do the reset outside of interrupt context */ 1045 schedule_work(&adapter->reset_task); 1046 } 1047 1048 /* 1049 * atl2_watchdog - Timer Call-back 1050 * @data: pointer to netdev cast into an unsigned long 1051 */ 1052 static void atl2_watchdog(unsigned long data) 1053 { 1054 struct atl2_adapter *adapter = (struct atl2_adapter *) data; 1055 1056 if (!test_bit(__ATL2_DOWN, &adapter->flags)) { 1057 u32 drop_rxd, drop_rxs; 1058 unsigned long flags; 1059 1060 spin_lock_irqsave(&adapter->stats_lock, flags); 1061 drop_rxd = ATL2_READ_REG(&adapter->hw, REG_STS_RXD_OV); 1062 drop_rxs = ATL2_READ_REG(&adapter->hw, REG_STS_RXS_OV); 1063 spin_unlock_irqrestore(&adapter->stats_lock, flags); 1064 1065 adapter->netdev->stats.rx_over_errors += drop_rxd + drop_rxs; 1066 1067 /* Reset the timer */ 1068 mod_timer(&adapter->watchdog_timer, 1069 round_jiffies(jiffies + 4 * HZ)); 1070 } 1071 } 1072 1073 /* 1074 * atl2_phy_config - Timer Call-back 1075 * @data: pointer to netdev cast into an unsigned long 1076 */ 1077 static void atl2_phy_config(unsigned long data) 1078 { 1079 struct atl2_adapter *adapter = (struct atl2_adapter *) data; 1080 struct atl2_hw *hw = &adapter->hw; 1081 unsigned long flags; 1082 1083 spin_lock_irqsave(&adapter->stats_lock, flags); 1084 atl2_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg); 1085 atl2_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN | 1086 MII_CR_RESTART_AUTO_NEG); 1087 spin_unlock_irqrestore(&adapter->stats_lock, flags); 1088 clear_bit(0, &adapter->cfg_phy); 1089 } 1090 1091 static int atl2_up(struct atl2_adapter *adapter) 1092 { 1093 struct net_device *netdev = adapter->netdev; 1094 int err = 0; 1095 u32 val; 1096 1097 /* hardware has been reset, we need to reload some things */ 1098 1099 err = atl2_init_hw(&adapter->hw); 1100 if (err) { 1101 err = -EIO; 1102 return err; 1103 } 1104 1105 atl2_set_multi(netdev); 1106 init_ring_ptrs(adapter); 1107 1108 atl2_restore_vlan(adapter); 1109 1110 if (atl2_configure(adapter)) { 1111 err = -EIO; 1112 goto err_up; 1113 } 1114 1115 clear_bit(__ATL2_DOWN, &adapter->flags); 1116 1117 val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL); 1118 ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, val | 1119 MASTER_CTRL_MANUAL_INT); 1120 1121 atl2_irq_enable(adapter); 1122 1123 err_up: 1124 return err; 1125 } 1126 1127 static void atl2_reinit_locked(struct atl2_adapter *adapter) 1128 { 1129 WARN_ON(in_interrupt()); 1130 while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags)) 1131 msleep(1); 1132 atl2_down(adapter); 1133 atl2_up(adapter); 1134 clear_bit(__ATL2_RESETTING, &adapter->flags); 1135 } 1136 1137 static void atl2_reset_task(struct work_struct *work) 1138 { 1139 struct atl2_adapter *adapter; 1140 adapter = container_of(work, struct atl2_adapter, reset_task); 1141 1142 atl2_reinit_locked(adapter); 1143 } 1144 1145 static void atl2_setup_mac_ctrl(struct atl2_adapter *adapter) 1146 { 1147 u32 value; 1148 struct atl2_hw *hw = &adapter->hw; 1149 struct net_device *netdev = adapter->netdev; 1150 1151 /* Config MAC CTRL Register */ 1152 value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY; 1153 1154 /* duplex */ 1155 if (FULL_DUPLEX == adapter->link_duplex) 1156 value |= MAC_CTRL_DUPLX; 1157 1158 /* flow control */ 1159 value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW); 1160 1161 /* PAD & CRC */ 1162 value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD); 1163 1164 /* preamble length */ 1165 value |= (((u32)adapter->hw.preamble_len & MAC_CTRL_PRMLEN_MASK) << 1166 MAC_CTRL_PRMLEN_SHIFT); 1167 1168 /* vlan */ 1169 __atl2_vlan_mode(netdev->features, &value); 1170 1171 /* filter mode */ 1172 value |= MAC_CTRL_BC_EN; 1173 if (netdev->flags & IFF_PROMISC) 1174 value |= MAC_CTRL_PROMIS_EN; 1175 else if (netdev->flags & IFF_ALLMULTI) 1176 value |= MAC_CTRL_MC_ALL_EN; 1177 1178 /* half retry buffer */ 1179 value |= (((u32)(adapter->hw.retry_buf & 1180 MAC_CTRL_HALF_LEFT_BUF_MASK)) << MAC_CTRL_HALF_LEFT_BUF_SHIFT); 1181 1182 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value); 1183 } 1184 1185 static int atl2_check_link(struct atl2_adapter *adapter) 1186 { 1187 struct atl2_hw *hw = &adapter->hw; 1188 struct net_device *netdev = adapter->netdev; 1189 int ret_val; 1190 u16 speed, duplex, phy_data; 1191 int reconfig = 0; 1192 1193 /* MII_BMSR must read twise */ 1194 atl2_read_phy_reg(hw, MII_BMSR, &phy_data); 1195 atl2_read_phy_reg(hw, MII_BMSR, &phy_data); 1196 if (!(phy_data&BMSR_LSTATUS)) { /* link down */ 1197 if (netif_carrier_ok(netdev)) { /* old link state: Up */ 1198 u32 value; 1199 /* disable rx */ 1200 value = ATL2_READ_REG(hw, REG_MAC_CTRL); 1201 value &= ~MAC_CTRL_RX_EN; 1202 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value); 1203 adapter->link_speed = SPEED_0; 1204 netif_carrier_off(netdev); 1205 netif_stop_queue(netdev); 1206 } 1207 return 0; 1208 } 1209 1210 /* Link Up */ 1211 ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex); 1212 if (ret_val) 1213 return ret_val; 1214 switch (hw->MediaType) { 1215 case MEDIA_TYPE_100M_FULL: 1216 if (speed != SPEED_100 || duplex != FULL_DUPLEX) 1217 reconfig = 1; 1218 break; 1219 case MEDIA_TYPE_100M_HALF: 1220 if (speed != SPEED_100 || duplex != HALF_DUPLEX) 1221 reconfig = 1; 1222 break; 1223 case MEDIA_TYPE_10M_FULL: 1224 if (speed != SPEED_10 || duplex != FULL_DUPLEX) 1225 reconfig = 1; 1226 break; 1227 case MEDIA_TYPE_10M_HALF: 1228 if (speed != SPEED_10 || duplex != HALF_DUPLEX) 1229 reconfig = 1; 1230 break; 1231 } 1232 /* link result is our setting */ 1233 if (reconfig == 0) { 1234 if (adapter->link_speed != speed || 1235 adapter->link_duplex != duplex) { 1236 adapter->link_speed = speed; 1237 adapter->link_duplex = duplex; 1238 atl2_setup_mac_ctrl(adapter); 1239 printk(KERN_INFO "%s: %s NIC Link is Up<%d Mbps %s>\n", 1240 atl2_driver_name, netdev->name, 1241 adapter->link_speed, 1242 adapter->link_duplex == FULL_DUPLEX ? 1243 "Full Duplex" : "Half Duplex"); 1244 } 1245 1246 if (!netif_carrier_ok(netdev)) { /* Link down -> Up */ 1247 netif_carrier_on(netdev); 1248 netif_wake_queue(netdev); 1249 } 1250 return 0; 1251 } 1252 1253 /* change original link status */ 1254 if (netif_carrier_ok(netdev)) { 1255 u32 value; 1256 /* disable rx */ 1257 value = ATL2_READ_REG(hw, REG_MAC_CTRL); 1258 value &= ~MAC_CTRL_RX_EN; 1259 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value); 1260 1261 adapter->link_speed = SPEED_0; 1262 netif_carrier_off(netdev); 1263 netif_stop_queue(netdev); 1264 } 1265 1266 /* auto-neg, insert timer to re-config phy 1267 * (if interval smaller than 5 seconds, something strange) */ 1268 if (!test_bit(__ATL2_DOWN, &adapter->flags)) { 1269 if (!test_and_set_bit(0, &adapter->cfg_phy)) 1270 mod_timer(&adapter->phy_config_timer, 1271 round_jiffies(jiffies + 5 * HZ)); 1272 } 1273 1274 return 0; 1275 } 1276 1277 /* 1278 * atl2_link_chg_task - deal with link change event Out of interrupt context 1279 * @netdev: network interface device structure 1280 */ 1281 static void atl2_link_chg_task(struct work_struct *work) 1282 { 1283 struct atl2_adapter *adapter; 1284 unsigned long flags; 1285 1286 adapter = container_of(work, struct atl2_adapter, link_chg_task); 1287 1288 spin_lock_irqsave(&adapter->stats_lock, flags); 1289 atl2_check_link(adapter); 1290 spin_unlock_irqrestore(&adapter->stats_lock, flags); 1291 } 1292 1293 static void atl2_setup_pcicmd(struct pci_dev *pdev) 1294 { 1295 u16 cmd; 1296 1297 pci_read_config_word(pdev, PCI_COMMAND, &cmd); 1298 1299 if (cmd & PCI_COMMAND_INTX_DISABLE) 1300 cmd &= ~PCI_COMMAND_INTX_DISABLE; 1301 if (cmd & PCI_COMMAND_IO) 1302 cmd &= ~PCI_COMMAND_IO; 1303 if (0 == (cmd & PCI_COMMAND_MEMORY)) 1304 cmd |= PCI_COMMAND_MEMORY; 1305 if (0 == (cmd & PCI_COMMAND_MASTER)) 1306 cmd |= PCI_COMMAND_MASTER; 1307 pci_write_config_word(pdev, PCI_COMMAND, cmd); 1308 1309 /* 1310 * some motherboards BIOS(PXE/EFI) driver may set PME 1311 * while they transfer control to OS (Windows/Linux) 1312 * so we should clear this bit before NIC work normally 1313 */ 1314 pci_write_config_dword(pdev, REG_PM_CTRLSTAT, 0); 1315 } 1316 1317 #ifdef CONFIG_NET_POLL_CONTROLLER 1318 static void atl2_poll_controller(struct net_device *netdev) 1319 { 1320 disable_irq(netdev->irq); 1321 atl2_intr(netdev->irq, netdev); 1322 enable_irq(netdev->irq); 1323 } 1324 #endif 1325 1326 1327 static const struct net_device_ops atl2_netdev_ops = { 1328 .ndo_open = atl2_open, 1329 .ndo_stop = atl2_close, 1330 .ndo_start_xmit = atl2_xmit_frame, 1331 .ndo_set_rx_mode = atl2_set_multi, 1332 .ndo_validate_addr = eth_validate_addr, 1333 .ndo_set_mac_address = atl2_set_mac, 1334 .ndo_change_mtu = atl2_change_mtu, 1335 .ndo_fix_features = atl2_fix_features, 1336 .ndo_set_features = atl2_set_features, 1337 .ndo_do_ioctl = atl2_ioctl, 1338 .ndo_tx_timeout = atl2_tx_timeout, 1339 #ifdef CONFIG_NET_POLL_CONTROLLER 1340 .ndo_poll_controller = atl2_poll_controller, 1341 #endif 1342 }; 1343 1344 /* 1345 * atl2_probe - Device Initialization Routine 1346 * @pdev: PCI device information struct 1347 * @ent: entry in atl2_pci_tbl 1348 * 1349 * Returns 0 on success, negative on failure 1350 * 1351 * atl2_probe initializes an adapter identified by a pci_dev structure. 1352 * The OS initialization, configuring of the adapter private structure, 1353 * and a hardware reset occur. 1354 */ 1355 static int __devinit atl2_probe(struct pci_dev *pdev, 1356 const struct pci_device_id *ent) 1357 { 1358 struct net_device *netdev; 1359 struct atl2_adapter *adapter; 1360 static int cards_found; 1361 unsigned long mmio_start; 1362 int mmio_len; 1363 int err; 1364 1365 cards_found = 0; 1366 1367 err = pci_enable_device(pdev); 1368 if (err) 1369 return err; 1370 1371 /* 1372 * atl2 is a shared-high-32-bit device, so we're stuck with 32-bit DMA 1373 * until the kernel has the proper infrastructure to support 64-bit DMA 1374 * on these devices. 1375 */ 1376 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) && 1377 pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) { 1378 printk(KERN_ERR "atl2: No usable DMA configuration, aborting\n"); 1379 goto err_dma; 1380 } 1381 1382 /* Mark all PCI regions associated with PCI device 1383 * pdev as being reserved by owner atl2_driver_name */ 1384 err = pci_request_regions(pdev, atl2_driver_name); 1385 if (err) 1386 goto err_pci_reg; 1387 1388 /* Enables bus-mastering on the device and calls 1389 * pcibios_set_master to do the needed arch specific settings */ 1390 pci_set_master(pdev); 1391 1392 err = -ENOMEM; 1393 netdev = alloc_etherdev(sizeof(struct atl2_adapter)); 1394 if (!netdev) 1395 goto err_alloc_etherdev; 1396 1397 SET_NETDEV_DEV(netdev, &pdev->dev); 1398 1399 pci_set_drvdata(pdev, netdev); 1400 adapter = netdev_priv(netdev); 1401 adapter->netdev = netdev; 1402 adapter->pdev = pdev; 1403 adapter->hw.back = adapter; 1404 1405 mmio_start = pci_resource_start(pdev, 0x0); 1406 mmio_len = pci_resource_len(pdev, 0x0); 1407 1408 adapter->hw.mem_rang = (u32)mmio_len; 1409 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len); 1410 if (!adapter->hw.hw_addr) { 1411 err = -EIO; 1412 goto err_ioremap; 1413 } 1414 1415 atl2_setup_pcicmd(pdev); 1416 1417 netdev->netdev_ops = &atl2_netdev_ops; 1418 atl2_set_ethtool_ops(netdev); 1419 netdev->watchdog_timeo = 5 * HZ; 1420 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); 1421 1422 netdev->mem_start = mmio_start; 1423 netdev->mem_end = mmio_start + mmio_len; 1424 adapter->bd_number = cards_found; 1425 adapter->pci_using_64 = false; 1426 1427 /* setup the private structure */ 1428 err = atl2_sw_init(adapter); 1429 if (err) 1430 goto err_sw_init; 1431 1432 err = -EIO; 1433 1434 netdev->hw_features = NETIF_F_SG | NETIF_F_HW_VLAN_RX; 1435 netdev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX); 1436 1437 /* Init PHY as early as possible due to power saving issue */ 1438 atl2_phy_init(&adapter->hw); 1439 1440 /* reset the controller to 1441 * put the device in a known good starting state */ 1442 1443 if (atl2_reset_hw(&adapter->hw)) { 1444 err = -EIO; 1445 goto err_reset; 1446 } 1447 1448 /* copy the MAC address out of the EEPROM */ 1449 atl2_read_mac_addr(&adapter->hw); 1450 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len); 1451 /* FIXME: do we still need this? */ 1452 #ifdef ETHTOOL_GPERMADDR 1453 memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len); 1454 1455 if (!is_valid_ether_addr(netdev->perm_addr)) { 1456 #else 1457 if (!is_valid_ether_addr(netdev->dev_addr)) { 1458 #endif 1459 err = -EIO; 1460 goto err_eeprom; 1461 } 1462 1463 atl2_check_options(adapter); 1464 1465 init_timer(&adapter->watchdog_timer); 1466 adapter->watchdog_timer.function = atl2_watchdog; 1467 adapter->watchdog_timer.data = (unsigned long) adapter; 1468 1469 init_timer(&adapter->phy_config_timer); 1470 adapter->phy_config_timer.function = atl2_phy_config; 1471 adapter->phy_config_timer.data = (unsigned long) adapter; 1472 1473 INIT_WORK(&adapter->reset_task, atl2_reset_task); 1474 INIT_WORK(&adapter->link_chg_task, atl2_link_chg_task); 1475 1476 strcpy(netdev->name, "eth%d"); /* ?? */ 1477 err = register_netdev(netdev); 1478 if (err) 1479 goto err_register; 1480 1481 /* assume we have no link for now */ 1482 netif_carrier_off(netdev); 1483 netif_stop_queue(netdev); 1484 1485 cards_found++; 1486 1487 return 0; 1488 1489 err_reset: 1490 err_register: 1491 err_sw_init: 1492 err_eeprom: 1493 iounmap(adapter->hw.hw_addr); 1494 err_ioremap: 1495 free_netdev(netdev); 1496 err_alloc_etherdev: 1497 pci_release_regions(pdev); 1498 err_pci_reg: 1499 err_dma: 1500 pci_disable_device(pdev); 1501 return err; 1502 } 1503 1504 /* 1505 * atl2_remove - Device Removal Routine 1506 * @pdev: PCI device information struct 1507 * 1508 * atl2_remove is called by the PCI subsystem to alert the driver 1509 * that it should release a PCI device. The could be caused by a 1510 * Hot-Plug event, or because the driver is going to be removed from 1511 * memory. 1512 */ 1513 /* FIXME: write the original MAC address back in case it was changed from a 1514 * BIOS-set value, as in atl1 -- CHS */ 1515 static void __devexit atl2_remove(struct pci_dev *pdev) 1516 { 1517 struct net_device *netdev = pci_get_drvdata(pdev); 1518 struct atl2_adapter *adapter = netdev_priv(netdev); 1519 1520 /* flush_scheduled work may reschedule our watchdog task, so 1521 * explicitly disable watchdog tasks from being rescheduled */ 1522 set_bit(__ATL2_DOWN, &adapter->flags); 1523 1524 del_timer_sync(&adapter->watchdog_timer); 1525 del_timer_sync(&adapter->phy_config_timer); 1526 cancel_work_sync(&adapter->reset_task); 1527 cancel_work_sync(&adapter->link_chg_task); 1528 1529 unregister_netdev(netdev); 1530 1531 atl2_force_ps(&adapter->hw); 1532 1533 iounmap(adapter->hw.hw_addr); 1534 pci_release_regions(pdev); 1535 1536 free_netdev(netdev); 1537 1538 pci_disable_device(pdev); 1539 } 1540 1541 static int atl2_suspend(struct pci_dev *pdev, pm_message_t state) 1542 { 1543 struct net_device *netdev = pci_get_drvdata(pdev); 1544 struct atl2_adapter *adapter = netdev_priv(netdev); 1545 struct atl2_hw *hw = &adapter->hw; 1546 u16 speed, duplex; 1547 u32 ctrl = 0; 1548 u32 wufc = adapter->wol; 1549 1550 #ifdef CONFIG_PM 1551 int retval = 0; 1552 #endif 1553 1554 netif_device_detach(netdev); 1555 1556 if (netif_running(netdev)) { 1557 WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags)); 1558 atl2_down(adapter); 1559 } 1560 1561 #ifdef CONFIG_PM 1562 retval = pci_save_state(pdev); 1563 if (retval) 1564 return retval; 1565 #endif 1566 1567 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl); 1568 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl); 1569 if (ctrl & BMSR_LSTATUS) 1570 wufc &= ~ATLX_WUFC_LNKC; 1571 1572 if (0 != (ctrl & BMSR_LSTATUS) && 0 != wufc) { 1573 u32 ret_val; 1574 /* get current link speed & duplex */ 1575 ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex); 1576 if (ret_val) { 1577 printk(KERN_DEBUG 1578 "%s: get speed&duplex error while suspend\n", 1579 atl2_driver_name); 1580 goto wol_dis; 1581 } 1582 1583 ctrl = 0; 1584 1585 /* turn on magic packet wol */ 1586 if (wufc & ATLX_WUFC_MAG) 1587 ctrl |= (WOL_MAGIC_EN | WOL_MAGIC_PME_EN); 1588 1589 /* ignore Link Chg event when Link is up */ 1590 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl); 1591 1592 /* Config MAC CTRL Register */ 1593 ctrl = MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY; 1594 if (FULL_DUPLEX == adapter->link_duplex) 1595 ctrl |= MAC_CTRL_DUPLX; 1596 ctrl |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD); 1597 ctrl |= (((u32)adapter->hw.preamble_len & 1598 MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT); 1599 ctrl |= (((u32)(adapter->hw.retry_buf & 1600 MAC_CTRL_HALF_LEFT_BUF_MASK)) << 1601 MAC_CTRL_HALF_LEFT_BUF_SHIFT); 1602 if (wufc & ATLX_WUFC_MAG) { 1603 /* magic packet maybe Broadcast&multicast&Unicast */ 1604 ctrl |= MAC_CTRL_BC_EN; 1605 } 1606 1607 ATL2_WRITE_REG(hw, REG_MAC_CTRL, ctrl); 1608 1609 /* pcie patch */ 1610 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC); 1611 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET; 1612 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl); 1613 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1); 1614 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK; 1615 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl); 1616 1617 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1); 1618 goto suspend_exit; 1619 } 1620 1621 if (0 == (ctrl&BMSR_LSTATUS) && 0 != (wufc&ATLX_WUFC_LNKC)) { 1622 /* link is down, so only LINK CHG WOL event enable */ 1623 ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN); 1624 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl); 1625 ATL2_WRITE_REG(hw, REG_MAC_CTRL, 0); 1626 1627 /* pcie patch */ 1628 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC); 1629 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET; 1630 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl); 1631 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1); 1632 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK; 1633 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl); 1634 1635 hw->phy_configured = false; /* re-init PHY when resume */ 1636 1637 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1); 1638 1639 goto suspend_exit; 1640 } 1641 1642 wol_dis: 1643 /* WOL disabled */ 1644 ATL2_WRITE_REG(hw, REG_WOL_CTRL, 0); 1645 1646 /* pcie patch */ 1647 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC); 1648 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET; 1649 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl); 1650 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1); 1651 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK; 1652 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl); 1653 1654 atl2_force_ps(hw); 1655 hw->phy_configured = false; /* re-init PHY when resume */ 1656 1657 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0); 1658 1659 suspend_exit: 1660 if (netif_running(netdev)) 1661 atl2_free_irq(adapter); 1662 1663 pci_disable_device(pdev); 1664 1665 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 1666 1667 return 0; 1668 } 1669 1670 #ifdef CONFIG_PM 1671 static int atl2_resume(struct pci_dev *pdev) 1672 { 1673 struct net_device *netdev = pci_get_drvdata(pdev); 1674 struct atl2_adapter *adapter = netdev_priv(netdev); 1675 u32 err; 1676 1677 pci_set_power_state(pdev, PCI_D0); 1678 pci_restore_state(pdev); 1679 1680 err = pci_enable_device(pdev); 1681 if (err) { 1682 printk(KERN_ERR 1683 "atl2: Cannot enable PCI device from suspend\n"); 1684 return err; 1685 } 1686 1687 pci_set_master(pdev); 1688 1689 ATL2_READ_REG(&adapter->hw, REG_WOL_CTRL); /* clear WOL status */ 1690 1691 pci_enable_wake(pdev, PCI_D3hot, 0); 1692 pci_enable_wake(pdev, PCI_D3cold, 0); 1693 1694 ATL2_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0); 1695 1696 if (netif_running(netdev)) { 1697 err = atl2_request_irq(adapter); 1698 if (err) 1699 return err; 1700 } 1701 1702 atl2_reset_hw(&adapter->hw); 1703 1704 if (netif_running(netdev)) 1705 atl2_up(adapter); 1706 1707 netif_device_attach(netdev); 1708 1709 return 0; 1710 } 1711 #endif 1712 1713 static void atl2_shutdown(struct pci_dev *pdev) 1714 { 1715 atl2_suspend(pdev, PMSG_SUSPEND); 1716 } 1717 1718 static struct pci_driver atl2_driver = { 1719 .name = atl2_driver_name, 1720 .id_table = atl2_pci_tbl, 1721 .probe = atl2_probe, 1722 .remove = __devexit_p(atl2_remove), 1723 /* Power Management Hooks */ 1724 .suspend = atl2_suspend, 1725 #ifdef CONFIG_PM 1726 .resume = atl2_resume, 1727 #endif 1728 .shutdown = atl2_shutdown, 1729 }; 1730 1731 /* 1732 * atl2_init_module - Driver Registration Routine 1733 * 1734 * atl2_init_module is the first routine called when the driver is 1735 * loaded. All it does is register with the PCI subsystem. 1736 */ 1737 static int __init atl2_init_module(void) 1738 { 1739 printk(KERN_INFO "%s - version %s\n", atl2_driver_string, 1740 atl2_driver_version); 1741 printk(KERN_INFO "%s\n", atl2_copyright); 1742 return pci_register_driver(&atl2_driver); 1743 } 1744 module_init(atl2_init_module); 1745 1746 /* 1747 * atl2_exit_module - Driver Exit Cleanup Routine 1748 * 1749 * atl2_exit_module is called just before the driver is removed 1750 * from memory. 1751 */ 1752 static void __exit atl2_exit_module(void) 1753 { 1754 pci_unregister_driver(&atl2_driver); 1755 } 1756 module_exit(atl2_exit_module); 1757 1758 static void atl2_read_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value) 1759 { 1760 struct atl2_adapter *adapter = hw->back; 1761 pci_read_config_word(adapter->pdev, reg, value); 1762 } 1763 1764 static void atl2_write_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value) 1765 { 1766 struct atl2_adapter *adapter = hw->back; 1767 pci_write_config_word(adapter->pdev, reg, *value); 1768 } 1769 1770 static int atl2_get_settings(struct net_device *netdev, 1771 struct ethtool_cmd *ecmd) 1772 { 1773 struct atl2_adapter *adapter = netdev_priv(netdev); 1774 struct atl2_hw *hw = &adapter->hw; 1775 1776 ecmd->supported = (SUPPORTED_10baseT_Half | 1777 SUPPORTED_10baseT_Full | 1778 SUPPORTED_100baseT_Half | 1779 SUPPORTED_100baseT_Full | 1780 SUPPORTED_Autoneg | 1781 SUPPORTED_TP); 1782 ecmd->advertising = ADVERTISED_TP; 1783 1784 ecmd->advertising |= ADVERTISED_Autoneg; 1785 ecmd->advertising |= hw->autoneg_advertised; 1786 1787 ecmd->port = PORT_TP; 1788 ecmd->phy_address = 0; 1789 ecmd->transceiver = XCVR_INTERNAL; 1790 1791 if (adapter->link_speed != SPEED_0) { 1792 ethtool_cmd_speed_set(ecmd, adapter->link_speed); 1793 if (adapter->link_duplex == FULL_DUPLEX) 1794 ecmd->duplex = DUPLEX_FULL; 1795 else 1796 ecmd->duplex = DUPLEX_HALF; 1797 } else { 1798 ethtool_cmd_speed_set(ecmd, -1); 1799 ecmd->duplex = -1; 1800 } 1801 1802 ecmd->autoneg = AUTONEG_ENABLE; 1803 return 0; 1804 } 1805 1806 static int atl2_set_settings(struct net_device *netdev, 1807 struct ethtool_cmd *ecmd) 1808 { 1809 struct atl2_adapter *adapter = netdev_priv(netdev); 1810 struct atl2_hw *hw = &adapter->hw; 1811 1812 while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags)) 1813 msleep(1); 1814 1815 if (ecmd->autoneg == AUTONEG_ENABLE) { 1816 #define MY_ADV_MASK (ADVERTISE_10_HALF | \ 1817 ADVERTISE_10_FULL | \ 1818 ADVERTISE_100_HALF| \ 1819 ADVERTISE_100_FULL) 1820 1821 if ((ecmd->advertising & MY_ADV_MASK) == MY_ADV_MASK) { 1822 hw->MediaType = MEDIA_TYPE_AUTO_SENSOR; 1823 hw->autoneg_advertised = MY_ADV_MASK; 1824 } else if ((ecmd->advertising & MY_ADV_MASK) == 1825 ADVERTISE_100_FULL) { 1826 hw->MediaType = MEDIA_TYPE_100M_FULL; 1827 hw->autoneg_advertised = ADVERTISE_100_FULL; 1828 } else if ((ecmd->advertising & MY_ADV_MASK) == 1829 ADVERTISE_100_HALF) { 1830 hw->MediaType = MEDIA_TYPE_100M_HALF; 1831 hw->autoneg_advertised = ADVERTISE_100_HALF; 1832 } else if ((ecmd->advertising & MY_ADV_MASK) == 1833 ADVERTISE_10_FULL) { 1834 hw->MediaType = MEDIA_TYPE_10M_FULL; 1835 hw->autoneg_advertised = ADVERTISE_10_FULL; 1836 } else if ((ecmd->advertising & MY_ADV_MASK) == 1837 ADVERTISE_10_HALF) { 1838 hw->MediaType = MEDIA_TYPE_10M_HALF; 1839 hw->autoneg_advertised = ADVERTISE_10_HALF; 1840 } else { 1841 clear_bit(__ATL2_RESETTING, &adapter->flags); 1842 return -EINVAL; 1843 } 1844 ecmd->advertising = hw->autoneg_advertised | 1845 ADVERTISED_TP | ADVERTISED_Autoneg; 1846 } else { 1847 clear_bit(__ATL2_RESETTING, &adapter->flags); 1848 return -EINVAL; 1849 } 1850 1851 /* reset the link */ 1852 if (netif_running(adapter->netdev)) { 1853 atl2_down(adapter); 1854 atl2_up(adapter); 1855 } else 1856 atl2_reset_hw(&adapter->hw); 1857 1858 clear_bit(__ATL2_RESETTING, &adapter->flags); 1859 return 0; 1860 } 1861 1862 static u32 atl2_get_msglevel(struct net_device *netdev) 1863 { 1864 return 0; 1865 } 1866 1867 /* 1868 * It's sane for this to be empty, but we might want to take advantage of this. 1869 */ 1870 static void atl2_set_msglevel(struct net_device *netdev, u32 data) 1871 { 1872 } 1873 1874 static int atl2_get_regs_len(struct net_device *netdev) 1875 { 1876 #define ATL2_REGS_LEN 42 1877 return sizeof(u32) * ATL2_REGS_LEN; 1878 } 1879 1880 static void atl2_get_regs(struct net_device *netdev, 1881 struct ethtool_regs *regs, void *p) 1882 { 1883 struct atl2_adapter *adapter = netdev_priv(netdev); 1884 struct atl2_hw *hw = &adapter->hw; 1885 u32 *regs_buff = p; 1886 u16 phy_data; 1887 1888 memset(p, 0, sizeof(u32) * ATL2_REGS_LEN); 1889 1890 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id; 1891 1892 regs_buff[0] = ATL2_READ_REG(hw, REG_VPD_CAP); 1893 regs_buff[1] = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL); 1894 regs_buff[2] = ATL2_READ_REG(hw, REG_SPI_FLASH_CONFIG); 1895 regs_buff[3] = ATL2_READ_REG(hw, REG_TWSI_CTRL); 1896 regs_buff[4] = ATL2_READ_REG(hw, REG_PCIE_DEV_MISC_CTRL); 1897 regs_buff[5] = ATL2_READ_REG(hw, REG_MASTER_CTRL); 1898 regs_buff[6] = ATL2_READ_REG(hw, REG_MANUAL_TIMER_INIT); 1899 regs_buff[7] = ATL2_READ_REG(hw, REG_IRQ_MODU_TIMER_INIT); 1900 regs_buff[8] = ATL2_READ_REG(hw, REG_PHY_ENABLE); 1901 regs_buff[9] = ATL2_READ_REG(hw, REG_CMBDISDMA_TIMER); 1902 regs_buff[10] = ATL2_READ_REG(hw, REG_IDLE_STATUS); 1903 regs_buff[11] = ATL2_READ_REG(hw, REG_MDIO_CTRL); 1904 regs_buff[12] = ATL2_READ_REG(hw, REG_SERDES_LOCK); 1905 regs_buff[13] = ATL2_READ_REG(hw, REG_MAC_CTRL); 1906 regs_buff[14] = ATL2_READ_REG(hw, REG_MAC_IPG_IFG); 1907 regs_buff[15] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR); 1908 regs_buff[16] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR+4); 1909 regs_buff[17] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE); 1910 regs_buff[18] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE+4); 1911 regs_buff[19] = ATL2_READ_REG(hw, REG_MAC_HALF_DUPLX_CTRL); 1912 regs_buff[20] = ATL2_READ_REG(hw, REG_MTU); 1913 regs_buff[21] = ATL2_READ_REG(hw, REG_WOL_CTRL); 1914 regs_buff[22] = ATL2_READ_REG(hw, REG_SRAM_TXRAM_END); 1915 regs_buff[23] = ATL2_READ_REG(hw, REG_DESC_BASE_ADDR_HI); 1916 regs_buff[24] = ATL2_READ_REG(hw, REG_TXD_BASE_ADDR_LO); 1917 regs_buff[25] = ATL2_READ_REG(hw, REG_TXD_MEM_SIZE); 1918 regs_buff[26] = ATL2_READ_REG(hw, REG_TXS_BASE_ADDR_LO); 1919 regs_buff[27] = ATL2_READ_REG(hw, REG_TXS_MEM_SIZE); 1920 regs_buff[28] = ATL2_READ_REG(hw, REG_RXD_BASE_ADDR_LO); 1921 regs_buff[29] = ATL2_READ_REG(hw, REG_RXD_BUF_NUM); 1922 regs_buff[30] = ATL2_READ_REG(hw, REG_DMAR); 1923 regs_buff[31] = ATL2_READ_REG(hw, REG_TX_CUT_THRESH); 1924 regs_buff[32] = ATL2_READ_REG(hw, REG_DMAW); 1925 regs_buff[33] = ATL2_READ_REG(hw, REG_PAUSE_ON_TH); 1926 regs_buff[34] = ATL2_READ_REG(hw, REG_PAUSE_OFF_TH); 1927 regs_buff[35] = ATL2_READ_REG(hw, REG_MB_TXD_WR_IDX); 1928 regs_buff[36] = ATL2_READ_REG(hw, REG_MB_RXD_RD_IDX); 1929 regs_buff[38] = ATL2_READ_REG(hw, REG_ISR); 1930 regs_buff[39] = ATL2_READ_REG(hw, REG_IMR); 1931 1932 atl2_read_phy_reg(hw, MII_BMCR, &phy_data); 1933 regs_buff[40] = (u32)phy_data; 1934 atl2_read_phy_reg(hw, MII_BMSR, &phy_data); 1935 regs_buff[41] = (u32)phy_data; 1936 } 1937 1938 static int atl2_get_eeprom_len(struct net_device *netdev) 1939 { 1940 struct atl2_adapter *adapter = netdev_priv(netdev); 1941 1942 if (!atl2_check_eeprom_exist(&adapter->hw)) 1943 return 512; 1944 else 1945 return 0; 1946 } 1947 1948 static int atl2_get_eeprom(struct net_device *netdev, 1949 struct ethtool_eeprom *eeprom, u8 *bytes) 1950 { 1951 struct atl2_adapter *adapter = netdev_priv(netdev); 1952 struct atl2_hw *hw = &adapter->hw; 1953 u32 *eeprom_buff; 1954 int first_dword, last_dword; 1955 int ret_val = 0; 1956 int i; 1957 1958 if (eeprom->len == 0) 1959 return -EINVAL; 1960 1961 if (atl2_check_eeprom_exist(hw)) 1962 return -EINVAL; 1963 1964 eeprom->magic = hw->vendor_id | (hw->device_id << 16); 1965 1966 first_dword = eeprom->offset >> 2; 1967 last_dword = (eeprom->offset + eeprom->len - 1) >> 2; 1968 1969 eeprom_buff = kmalloc(sizeof(u32) * (last_dword - first_dword + 1), 1970 GFP_KERNEL); 1971 if (!eeprom_buff) 1972 return -ENOMEM; 1973 1974 for (i = first_dword; i < last_dword; i++) { 1975 if (!atl2_read_eeprom(hw, i*4, &(eeprom_buff[i-first_dword]))) { 1976 ret_val = -EIO; 1977 goto free; 1978 } 1979 } 1980 1981 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 3), 1982 eeprom->len); 1983 free: 1984 kfree(eeprom_buff); 1985 1986 return ret_val; 1987 } 1988 1989 static int atl2_set_eeprom(struct net_device *netdev, 1990 struct ethtool_eeprom *eeprom, u8 *bytes) 1991 { 1992 struct atl2_adapter *adapter = netdev_priv(netdev); 1993 struct atl2_hw *hw = &adapter->hw; 1994 u32 *eeprom_buff; 1995 u32 *ptr; 1996 int max_len, first_dword, last_dword, ret_val = 0; 1997 int i; 1998 1999 if (eeprom->len == 0) 2000 return -EOPNOTSUPP; 2001 2002 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16))) 2003 return -EFAULT; 2004 2005 max_len = 512; 2006 2007 first_dword = eeprom->offset >> 2; 2008 last_dword = (eeprom->offset + eeprom->len - 1) >> 2; 2009 eeprom_buff = kmalloc(max_len, GFP_KERNEL); 2010 if (!eeprom_buff) 2011 return -ENOMEM; 2012 2013 ptr = eeprom_buff; 2014 2015 if (eeprom->offset & 3) { 2016 /* need read/modify/write of first changed EEPROM word */ 2017 /* only the second byte of the word is being modified */ 2018 if (!atl2_read_eeprom(hw, first_dword*4, &(eeprom_buff[0]))) { 2019 ret_val = -EIO; 2020 goto out; 2021 } 2022 ptr++; 2023 } 2024 if (((eeprom->offset + eeprom->len) & 3)) { 2025 /* 2026 * need read/modify/write of last changed EEPROM word 2027 * only the first byte of the word is being modified 2028 */ 2029 if (!atl2_read_eeprom(hw, last_dword * 4, 2030 &(eeprom_buff[last_dword - first_dword]))) { 2031 ret_val = -EIO; 2032 goto out; 2033 } 2034 } 2035 2036 /* Device's eeprom is always little-endian, word addressable */ 2037 memcpy(ptr, bytes, eeprom->len); 2038 2039 for (i = 0; i < last_dword - first_dword + 1; i++) { 2040 if (!atl2_write_eeprom(hw, ((first_dword+i)*4), eeprom_buff[i])) { 2041 ret_val = -EIO; 2042 goto out; 2043 } 2044 } 2045 out: 2046 kfree(eeprom_buff); 2047 return ret_val; 2048 } 2049 2050 static void atl2_get_drvinfo(struct net_device *netdev, 2051 struct ethtool_drvinfo *drvinfo) 2052 { 2053 struct atl2_adapter *adapter = netdev_priv(netdev); 2054 2055 strlcpy(drvinfo->driver, atl2_driver_name, sizeof(drvinfo->driver)); 2056 strlcpy(drvinfo->version, atl2_driver_version, 2057 sizeof(drvinfo->version)); 2058 strlcpy(drvinfo->fw_version, "L2", sizeof(drvinfo->fw_version)); 2059 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev), 2060 sizeof(drvinfo->bus_info)); 2061 drvinfo->n_stats = 0; 2062 drvinfo->testinfo_len = 0; 2063 drvinfo->regdump_len = atl2_get_regs_len(netdev); 2064 drvinfo->eedump_len = atl2_get_eeprom_len(netdev); 2065 } 2066 2067 static void atl2_get_wol(struct net_device *netdev, 2068 struct ethtool_wolinfo *wol) 2069 { 2070 struct atl2_adapter *adapter = netdev_priv(netdev); 2071 2072 wol->supported = WAKE_MAGIC; 2073 wol->wolopts = 0; 2074 2075 if (adapter->wol & ATLX_WUFC_EX) 2076 wol->wolopts |= WAKE_UCAST; 2077 if (adapter->wol & ATLX_WUFC_MC) 2078 wol->wolopts |= WAKE_MCAST; 2079 if (adapter->wol & ATLX_WUFC_BC) 2080 wol->wolopts |= WAKE_BCAST; 2081 if (adapter->wol & ATLX_WUFC_MAG) 2082 wol->wolopts |= WAKE_MAGIC; 2083 if (adapter->wol & ATLX_WUFC_LNKC) 2084 wol->wolopts |= WAKE_PHY; 2085 } 2086 2087 static int atl2_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 2088 { 2089 struct atl2_adapter *adapter = netdev_priv(netdev); 2090 2091 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE)) 2092 return -EOPNOTSUPP; 2093 2094 if (wol->wolopts & (WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)) 2095 return -EOPNOTSUPP; 2096 2097 /* these settings will always override what we currently have */ 2098 adapter->wol = 0; 2099 2100 if (wol->wolopts & WAKE_MAGIC) 2101 adapter->wol |= ATLX_WUFC_MAG; 2102 if (wol->wolopts & WAKE_PHY) 2103 adapter->wol |= ATLX_WUFC_LNKC; 2104 2105 return 0; 2106 } 2107 2108 static int atl2_nway_reset(struct net_device *netdev) 2109 { 2110 struct atl2_adapter *adapter = netdev_priv(netdev); 2111 if (netif_running(netdev)) 2112 atl2_reinit_locked(adapter); 2113 return 0; 2114 } 2115 2116 static const struct ethtool_ops atl2_ethtool_ops = { 2117 .get_settings = atl2_get_settings, 2118 .set_settings = atl2_set_settings, 2119 .get_drvinfo = atl2_get_drvinfo, 2120 .get_regs_len = atl2_get_regs_len, 2121 .get_regs = atl2_get_regs, 2122 .get_wol = atl2_get_wol, 2123 .set_wol = atl2_set_wol, 2124 .get_msglevel = atl2_get_msglevel, 2125 .set_msglevel = atl2_set_msglevel, 2126 .nway_reset = atl2_nway_reset, 2127 .get_link = ethtool_op_get_link, 2128 .get_eeprom_len = atl2_get_eeprom_len, 2129 .get_eeprom = atl2_get_eeprom, 2130 .set_eeprom = atl2_set_eeprom, 2131 }; 2132 2133 static void atl2_set_ethtool_ops(struct net_device *netdev) 2134 { 2135 SET_ETHTOOL_OPS(netdev, &atl2_ethtool_ops); 2136 } 2137 2138 #define LBYTESWAP(a) ((((a) & 0x00ff00ff) << 8) | \ 2139 (((a) & 0xff00ff00) >> 8)) 2140 #define LONGSWAP(a) ((LBYTESWAP(a) << 16) | (LBYTESWAP(a) >> 16)) 2141 #define SHORTSWAP(a) (((a) << 8) | ((a) >> 8)) 2142 2143 /* 2144 * Reset the transmit and receive units; mask and clear all interrupts. 2145 * 2146 * hw - Struct containing variables accessed by shared code 2147 * return : 0 or idle status (if error) 2148 */ 2149 static s32 atl2_reset_hw(struct atl2_hw *hw) 2150 { 2151 u32 icr; 2152 u16 pci_cfg_cmd_word; 2153 int i; 2154 2155 /* Workaround for PCI problem when BIOS sets MMRBC incorrectly. */ 2156 atl2_read_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word); 2157 if ((pci_cfg_cmd_word & 2158 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) != 2159 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) { 2160 pci_cfg_cmd_word |= 2161 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER); 2162 atl2_write_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word); 2163 } 2164 2165 /* Clear Interrupt mask to stop board from generating 2166 * interrupts & Clear any pending interrupt events 2167 */ 2168 /* FIXME */ 2169 /* ATL2_WRITE_REG(hw, REG_IMR, 0); */ 2170 /* ATL2_WRITE_REG(hw, REG_ISR, 0xffffffff); */ 2171 2172 /* Issue Soft Reset to the MAC. This will reset the chip's 2173 * transmit, receive, DMA. It will not effect 2174 * the current PCI configuration. The global reset bit is self- 2175 * clearing, and should clear within a microsecond. 2176 */ 2177 ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_SOFT_RST); 2178 wmb(); 2179 msleep(1); /* delay about 1ms */ 2180 2181 /* Wait at least 10ms for All module to be Idle */ 2182 for (i = 0; i < 10; i++) { 2183 icr = ATL2_READ_REG(hw, REG_IDLE_STATUS); 2184 if (!icr) 2185 break; 2186 msleep(1); /* delay 1 ms */ 2187 cpu_relax(); 2188 } 2189 2190 if (icr) 2191 return icr; 2192 2193 return 0; 2194 } 2195 2196 #define CUSTOM_SPI_CS_SETUP 2 2197 #define CUSTOM_SPI_CLK_HI 2 2198 #define CUSTOM_SPI_CLK_LO 2 2199 #define CUSTOM_SPI_CS_HOLD 2 2200 #define CUSTOM_SPI_CS_HI 3 2201 2202 static struct atl2_spi_flash_dev flash_table[] = 2203 { 2204 /* MFR WRSR READ PROGRAM WREN WRDI RDSR RDID SECTOR_ERASE CHIP_ERASE */ 2205 {"Atmel", 0x0, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62 }, 2206 {"SST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60 }, 2207 {"ST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xAB, 0xD8, 0xC7 }, 2208 }; 2209 2210 static bool atl2_spi_read(struct atl2_hw *hw, u32 addr, u32 *buf) 2211 { 2212 int i; 2213 u32 value; 2214 2215 ATL2_WRITE_REG(hw, REG_SPI_DATA, 0); 2216 ATL2_WRITE_REG(hw, REG_SPI_ADDR, addr); 2217 2218 value = SPI_FLASH_CTRL_WAIT_READY | 2219 (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) << 2220 SPI_FLASH_CTRL_CS_SETUP_SHIFT | 2221 (CUSTOM_SPI_CLK_HI & SPI_FLASH_CTRL_CLK_HI_MASK) << 2222 SPI_FLASH_CTRL_CLK_HI_SHIFT | 2223 (CUSTOM_SPI_CLK_LO & SPI_FLASH_CTRL_CLK_LO_MASK) << 2224 SPI_FLASH_CTRL_CLK_LO_SHIFT | 2225 (CUSTOM_SPI_CS_HOLD & SPI_FLASH_CTRL_CS_HOLD_MASK) << 2226 SPI_FLASH_CTRL_CS_HOLD_SHIFT | 2227 (CUSTOM_SPI_CS_HI & SPI_FLASH_CTRL_CS_HI_MASK) << 2228 SPI_FLASH_CTRL_CS_HI_SHIFT | 2229 (0x1 & SPI_FLASH_CTRL_INS_MASK) << SPI_FLASH_CTRL_INS_SHIFT; 2230 2231 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value); 2232 2233 value |= SPI_FLASH_CTRL_START; 2234 2235 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value); 2236 2237 for (i = 0; i < 10; i++) { 2238 msleep(1); 2239 value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL); 2240 if (!(value & SPI_FLASH_CTRL_START)) 2241 break; 2242 } 2243 2244 if (value & SPI_FLASH_CTRL_START) 2245 return false; 2246 2247 *buf = ATL2_READ_REG(hw, REG_SPI_DATA); 2248 2249 return true; 2250 } 2251 2252 /* 2253 * get_permanent_address 2254 * return 0 if get valid mac address, 2255 */ 2256 static int get_permanent_address(struct atl2_hw *hw) 2257 { 2258 u32 Addr[2]; 2259 u32 i, Control; 2260 u16 Register; 2261 u8 EthAddr[NODE_ADDRESS_SIZE]; 2262 bool KeyValid; 2263 2264 if (is_valid_ether_addr(hw->perm_mac_addr)) 2265 return 0; 2266 2267 Addr[0] = 0; 2268 Addr[1] = 0; 2269 2270 if (!atl2_check_eeprom_exist(hw)) { /* eeprom exists */ 2271 Register = 0; 2272 KeyValid = false; 2273 2274 /* Read out all EEPROM content */ 2275 i = 0; 2276 while (1) { 2277 if (atl2_read_eeprom(hw, i + 0x100, &Control)) { 2278 if (KeyValid) { 2279 if (Register == REG_MAC_STA_ADDR) 2280 Addr[0] = Control; 2281 else if (Register == 2282 (REG_MAC_STA_ADDR + 4)) 2283 Addr[1] = Control; 2284 KeyValid = false; 2285 } else if ((Control & 0xff) == 0x5A) { 2286 KeyValid = true; 2287 Register = (u16) (Control >> 16); 2288 } else { 2289 /* assume data end while encount an invalid KEYWORD */ 2290 break; 2291 } 2292 } else { 2293 break; /* read error */ 2294 } 2295 i += 4; 2296 } 2297 2298 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]); 2299 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]); 2300 2301 if (is_valid_ether_addr(EthAddr)) { 2302 memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE); 2303 return 0; 2304 } 2305 return 1; 2306 } 2307 2308 /* see if SPI flash exists? */ 2309 Addr[0] = 0; 2310 Addr[1] = 0; 2311 Register = 0; 2312 KeyValid = false; 2313 i = 0; 2314 while (1) { 2315 if (atl2_spi_read(hw, i + 0x1f000, &Control)) { 2316 if (KeyValid) { 2317 if (Register == REG_MAC_STA_ADDR) 2318 Addr[0] = Control; 2319 else if (Register == (REG_MAC_STA_ADDR + 4)) 2320 Addr[1] = Control; 2321 KeyValid = false; 2322 } else if ((Control & 0xff) == 0x5A) { 2323 KeyValid = true; 2324 Register = (u16) (Control >> 16); 2325 } else { 2326 break; /* data end */ 2327 } 2328 } else { 2329 break; /* read error */ 2330 } 2331 i += 4; 2332 } 2333 2334 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]); 2335 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *)&Addr[1]); 2336 if (is_valid_ether_addr(EthAddr)) { 2337 memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE); 2338 return 0; 2339 } 2340 /* maybe MAC-address is from BIOS */ 2341 Addr[0] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR); 2342 Addr[1] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR + 4); 2343 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]); 2344 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]); 2345 2346 if (is_valid_ether_addr(EthAddr)) { 2347 memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE); 2348 return 0; 2349 } 2350 2351 return 1; 2352 } 2353 2354 /* 2355 * Reads the adapter's MAC address from the EEPROM 2356 * 2357 * hw - Struct containing variables accessed by shared code 2358 */ 2359 static s32 atl2_read_mac_addr(struct atl2_hw *hw) 2360 { 2361 u16 i; 2362 2363 if (get_permanent_address(hw)) { 2364 /* for test */ 2365 /* FIXME: shouldn't we use random_ether_addr() here? */ 2366 hw->perm_mac_addr[0] = 0x00; 2367 hw->perm_mac_addr[1] = 0x13; 2368 hw->perm_mac_addr[2] = 0x74; 2369 hw->perm_mac_addr[3] = 0x00; 2370 hw->perm_mac_addr[4] = 0x5c; 2371 hw->perm_mac_addr[5] = 0x38; 2372 } 2373 2374 for (i = 0; i < NODE_ADDRESS_SIZE; i++) 2375 hw->mac_addr[i] = hw->perm_mac_addr[i]; 2376 2377 return 0; 2378 } 2379 2380 /* 2381 * Hashes an address to determine its location in the multicast table 2382 * 2383 * hw - Struct containing variables accessed by shared code 2384 * mc_addr - the multicast address to hash 2385 * 2386 * atl2_hash_mc_addr 2387 * purpose 2388 * set hash value for a multicast address 2389 * hash calcu processing : 2390 * 1. calcu 32bit CRC for multicast address 2391 * 2. reverse crc with MSB to LSB 2392 */ 2393 static u32 atl2_hash_mc_addr(struct atl2_hw *hw, u8 *mc_addr) 2394 { 2395 u32 crc32, value; 2396 int i; 2397 2398 value = 0; 2399 crc32 = ether_crc_le(6, mc_addr); 2400 2401 for (i = 0; i < 32; i++) 2402 value |= (((crc32 >> i) & 1) << (31 - i)); 2403 2404 return value; 2405 } 2406 2407 /* 2408 * Sets the bit in the multicast table corresponding to the hash value. 2409 * 2410 * hw - Struct containing variables accessed by shared code 2411 * hash_value - Multicast address hash value 2412 */ 2413 static void atl2_hash_set(struct atl2_hw *hw, u32 hash_value) 2414 { 2415 u32 hash_bit, hash_reg; 2416 u32 mta; 2417 2418 /* The HASH Table is a register array of 2 32-bit registers. 2419 * It is treated like an array of 64 bits. We want to set 2420 * bit BitArray[hash_value]. So we figure out what register 2421 * the bit is in, read it, OR in the new bit, then write 2422 * back the new value. The register is determined by the 2423 * upper 7 bits of the hash value and the bit within that 2424 * register are determined by the lower 5 bits of the value. 2425 */ 2426 hash_reg = (hash_value >> 31) & 0x1; 2427 hash_bit = (hash_value >> 26) & 0x1F; 2428 2429 mta = ATL2_READ_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg); 2430 2431 mta |= (1 << hash_bit); 2432 2433 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg, mta); 2434 } 2435 2436 /* 2437 * atl2_init_pcie - init PCIE module 2438 */ 2439 static void atl2_init_pcie(struct atl2_hw *hw) 2440 { 2441 u32 value; 2442 value = LTSSM_TEST_MODE_DEF; 2443 ATL2_WRITE_REG(hw, REG_LTSSM_TEST_MODE, value); 2444 2445 value = PCIE_DLL_TX_CTRL1_DEF; 2446 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, value); 2447 } 2448 2449 static void atl2_init_flash_opcode(struct atl2_hw *hw) 2450 { 2451 if (hw->flash_vendor >= ARRAY_SIZE(flash_table)) 2452 hw->flash_vendor = 0; /* ATMEL */ 2453 2454 /* Init OP table */ 2455 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_PROGRAM, 2456 flash_table[hw->flash_vendor].cmdPROGRAM); 2457 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_SC_ERASE, 2458 flash_table[hw->flash_vendor].cmdSECTOR_ERASE); 2459 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_CHIP_ERASE, 2460 flash_table[hw->flash_vendor].cmdCHIP_ERASE); 2461 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDID, 2462 flash_table[hw->flash_vendor].cmdRDID); 2463 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WREN, 2464 flash_table[hw->flash_vendor].cmdWREN); 2465 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDSR, 2466 flash_table[hw->flash_vendor].cmdRDSR); 2467 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WRSR, 2468 flash_table[hw->flash_vendor].cmdWRSR); 2469 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_READ, 2470 flash_table[hw->flash_vendor].cmdREAD); 2471 } 2472 2473 /******************************************************************** 2474 * Performs basic configuration of the adapter. 2475 * 2476 * hw - Struct containing variables accessed by shared code 2477 * Assumes that the controller has previously been reset and is in a 2478 * post-reset uninitialized state. Initializes multicast table, 2479 * and Calls routines to setup link 2480 * Leaves the transmit and receive units disabled and uninitialized. 2481 ********************************************************************/ 2482 static s32 atl2_init_hw(struct atl2_hw *hw) 2483 { 2484 u32 ret_val = 0; 2485 2486 atl2_init_pcie(hw); 2487 2488 /* Zero out the Multicast HASH table */ 2489 /* clear the old settings from the multicast hash table */ 2490 ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0); 2491 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0); 2492 2493 atl2_init_flash_opcode(hw); 2494 2495 ret_val = atl2_phy_init(hw); 2496 2497 return ret_val; 2498 } 2499 2500 /* 2501 * Detects the current speed and duplex settings of the hardware. 2502 * 2503 * hw - Struct containing variables accessed by shared code 2504 * speed - Speed of the connection 2505 * duplex - Duplex setting of the connection 2506 */ 2507 static s32 atl2_get_speed_and_duplex(struct atl2_hw *hw, u16 *speed, 2508 u16 *duplex) 2509 { 2510 s32 ret_val; 2511 u16 phy_data; 2512 2513 /* Read PHY Specific Status Register (17) */ 2514 ret_val = atl2_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data); 2515 if (ret_val) 2516 return ret_val; 2517 2518 if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED)) 2519 return ATLX_ERR_PHY_RES; 2520 2521 switch (phy_data & MII_ATLX_PSSR_SPEED) { 2522 case MII_ATLX_PSSR_100MBS: 2523 *speed = SPEED_100; 2524 break; 2525 case MII_ATLX_PSSR_10MBS: 2526 *speed = SPEED_10; 2527 break; 2528 default: 2529 return ATLX_ERR_PHY_SPEED; 2530 break; 2531 } 2532 2533 if (phy_data & MII_ATLX_PSSR_DPLX) 2534 *duplex = FULL_DUPLEX; 2535 else 2536 *duplex = HALF_DUPLEX; 2537 2538 return 0; 2539 } 2540 2541 /* 2542 * Reads the value from a PHY register 2543 * hw - Struct containing variables accessed by shared code 2544 * reg_addr - address of the PHY register to read 2545 */ 2546 static s32 atl2_read_phy_reg(struct atl2_hw *hw, u16 reg_addr, u16 *phy_data) 2547 { 2548 u32 val; 2549 int i; 2550 2551 val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT | 2552 MDIO_START | 2553 MDIO_SUP_PREAMBLE | 2554 MDIO_RW | 2555 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT; 2556 ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val); 2557 2558 wmb(); 2559 2560 for (i = 0; i < MDIO_WAIT_TIMES; i++) { 2561 udelay(2); 2562 val = ATL2_READ_REG(hw, REG_MDIO_CTRL); 2563 if (!(val & (MDIO_START | MDIO_BUSY))) 2564 break; 2565 wmb(); 2566 } 2567 if (!(val & (MDIO_START | MDIO_BUSY))) { 2568 *phy_data = (u16)val; 2569 return 0; 2570 } 2571 2572 return ATLX_ERR_PHY; 2573 } 2574 2575 /* 2576 * Writes a value to a PHY register 2577 * hw - Struct containing variables accessed by shared code 2578 * reg_addr - address of the PHY register to write 2579 * data - data to write to the PHY 2580 */ 2581 static s32 atl2_write_phy_reg(struct atl2_hw *hw, u32 reg_addr, u16 phy_data) 2582 { 2583 int i; 2584 u32 val; 2585 2586 val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT | 2587 (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT | 2588 MDIO_SUP_PREAMBLE | 2589 MDIO_START | 2590 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT; 2591 ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val); 2592 2593 wmb(); 2594 2595 for (i = 0; i < MDIO_WAIT_TIMES; i++) { 2596 udelay(2); 2597 val = ATL2_READ_REG(hw, REG_MDIO_CTRL); 2598 if (!(val & (MDIO_START | MDIO_BUSY))) 2599 break; 2600 2601 wmb(); 2602 } 2603 2604 if (!(val & (MDIO_START | MDIO_BUSY))) 2605 return 0; 2606 2607 return ATLX_ERR_PHY; 2608 } 2609 2610 /* 2611 * Configures PHY autoneg and flow control advertisement settings 2612 * 2613 * hw - Struct containing variables accessed by shared code 2614 */ 2615 static s32 atl2_phy_setup_autoneg_adv(struct atl2_hw *hw) 2616 { 2617 s32 ret_val; 2618 s16 mii_autoneg_adv_reg; 2619 2620 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 2621 mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK; 2622 2623 /* Need to parse autoneg_advertised and set up 2624 * the appropriate PHY registers. First we will parse for 2625 * autoneg_advertised software override. Since we can advertise 2626 * a plethora of combinations, we need to check each bit 2627 * individually. 2628 */ 2629 2630 /* First we clear all the 10/100 mb speed bits in the Auto-Neg 2631 * Advertisement Register (Address 4) and the 1000 mb speed bits in 2632 * the 1000Base-T Control Register (Address 9). */ 2633 mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK; 2634 2635 /* Need to parse MediaType and setup the 2636 * appropriate PHY registers. */ 2637 switch (hw->MediaType) { 2638 case MEDIA_TYPE_AUTO_SENSOR: 2639 mii_autoneg_adv_reg |= 2640 (MII_AR_10T_HD_CAPS | 2641 MII_AR_10T_FD_CAPS | 2642 MII_AR_100TX_HD_CAPS| 2643 MII_AR_100TX_FD_CAPS); 2644 hw->autoneg_advertised = 2645 ADVERTISE_10_HALF | 2646 ADVERTISE_10_FULL | 2647 ADVERTISE_100_HALF| 2648 ADVERTISE_100_FULL; 2649 break; 2650 case MEDIA_TYPE_100M_FULL: 2651 mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS; 2652 hw->autoneg_advertised = ADVERTISE_100_FULL; 2653 break; 2654 case MEDIA_TYPE_100M_HALF: 2655 mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS; 2656 hw->autoneg_advertised = ADVERTISE_100_HALF; 2657 break; 2658 case MEDIA_TYPE_10M_FULL: 2659 mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS; 2660 hw->autoneg_advertised = ADVERTISE_10_FULL; 2661 break; 2662 default: 2663 mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS; 2664 hw->autoneg_advertised = ADVERTISE_10_HALF; 2665 break; 2666 } 2667 2668 /* flow control fixed to enable all */ 2669 mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE); 2670 2671 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg; 2672 2673 ret_val = atl2_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg); 2674 2675 if (ret_val) 2676 return ret_val; 2677 2678 return 0; 2679 } 2680 2681 /* 2682 * Resets the PHY and make all config validate 2683 * 2684 * hw - Struct containing variables accessed by shared code 2685 * 2686 * Sets bit 15 and 12 of the MII Control regiser (for F001 bug) 2687 */ 2688 static s32 atl2_phy_commit(struct atl2_hw *hw) 2689 { 2690 s32 ret_val; 2691 u16 phy_data; 2692 2693 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG; 2694 ret_val = atl2_write_phy_reg(hw, MII_BMCR, phy_data); 2695 if (ret_val) { 2696 u32 val; 2697 int i; 2698 /* pcie serdes link may be down ! */ 2699 for (i = 0; i < 25; i++) { 2700 msleep(1); 2701 val = ATL2_READ_REG(hw, REG_MDIO_CTRL); 2702 if (!(val & (MDIO_START | MDIO_BUSY))) 2703 break; 2704 } 2705 2706 if (0 != (val & (MDIO_START | MDIO_BUSY))) { 2707 printk(KERN_ERR "atl2: PCIe link down for at least 25ms !\n"); 2708 return ret_val; 2709 } 2710 } 2711 return 0; 2712 } 2713 2714 static s32 atl2_phy_init(struct atl2_hw *hw) 2715 { 2716 s32 ret_val; 2717 u16 phy_val; 2718 2719 if (hw->phy_configured) 2720 return 0; 2721 2722 /* Enable PHY */ 2723 ATL2_WRITE_REGW(hw, REG_PHY_ENABLE, 1); 2724 ATL2_WRITE_FLUSH(hw); 2725 msleep(1); 2726 2727 /* check if the PHY is in powersaving mode */ 2728 atl2_write_phy_reg(hw, MII_DBG_ADDR, 0); 2729 atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val); 2730 2731 /* 024E / 124E 0r 0274 / 1274 ? */ 2732 if (phy_val & 0x1000) { 2733 phy_val &= ~0x1000; 2734 atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val); 2735 } 2736 2737 msleep(1); 2738 2739 /*Enable PHY LinkChange Interrupt */ 2740 ret_val = atl2_write_phy_reg(hw, 18, 0xC00); 2741 if (ret_val) 2742 return ret_val; 2743 2744 /* setup AutoNeg parameters */ 2745 ret_val = atl2_phy_setup_autoneg_adv(hw); 2746 if (ret_val) 2747 return ret_val; 2748 2749 /* SW.Reset & En-Auto-Neg to restart Auto-Neg */ 2750 ret_val = atl2_phy_commit(hw); 2751 if (ret_val) 2752 return ret_val; 2753 2754 hw->phy_configured = true; 2755 2756 return ret_val; 2757 } 2758 2759 static void atl2_set_mac_addr(struct atl2_hw *hw) 2760 { 2761 u32 value; 2762 /* 00-0B-6A-F6-00-DC 2763 * 0: 6AF600DC 1: 000B 2764 * low dword */ 2765 value = (((u32)hw->mac_addr[2]) << 24) | 2766 (((u32)hw->mac_addr[3]) << 16) | 2767 (((u32)hw->mac_addr[4]) << 8) | 2768 (((u32)hw->mac_addr[5])); 2769 ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value); 2770 /* hight dword */ 2771 value = (((u32)hw->mac_addr[0]) << 8) | 2772 (((u32)hw->mac_addr[1])); 2773 ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value); 2774 } 2775 2776 /* 2777 * check_eeprom_exist 2778 * return 0 if eeprom exist 2779 */ 2780 static int atl2_check_eeprom_exist(struct atl2_hw *hw) 2781 { 2782 u32 value; 2783 2784 value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL); 2785 if (value & SPI_FLASH_CTRL_EN_VPD) { 2786 value &= ~SPI_FLASH_CTRL_EN_VPD; 2787 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value); 2788 } 2789 value = ATL2_READ_REGW(hw, REG_PCIE_CAP_LIST); 2790 return ((value & 0xFF00) == 0x6C00) ? 0 : 1; 2791 } 2792 2793 /* FIXME: This doesn't look right. -- CHS */ 2794 static bool atl2_write_eeprom(struct atl2_hw *hw, u32 offset, u32 value) 2795 { 2796 return true; 2797 } 2798 2799 static bool atl2_read_eeprom(struct atl2_hw *hw, u32 Offset, u32 *pValue) 2800 { 2801 int i; 2802 u32 Control; 2803 2804 if (Offset & 0x3) 2805 return false; /* address do not align */ 2806 2807 ATL2_WRITE_REG(hw, REG_VPD_DATA, 0); 2808 Control = (Offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT; 2809 ATL2_WRITE_REG(hw, REG_VPD_CAP, Control); 2810 2811 for (i = 0; i < 10; i++) { 2812 msleep(2); 2813 Control = ATL2_READ_REG(hw, REG_VPD_CAP); 2814 if (Control & VPD_CAP_VPD_FLAG) 2815 break; 2816 } 2817 2818 if (Control & VPD_CAP_VPD_FLAG) { 2819 *pValue = ATL2_READ_REG(hw, REG_VPD_DATA); 2820 return true; 2821 } 2822 return false; /* timeout */ 2823 } 2824 2825 static void atl2_force_ps(struct atl2_hw *hw) 2826 { 2827 u16 phy_val; 2828 2829 atl2_write_phy_reg(hw, MII_DBG_ADDR, 0); 2830 atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val); 2831 atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val | 0x1000); 2832 2833 atl2_write_phy_reg(hw, MII_DBG_ADDR, 2); 2834 atl2_write_phy_reg(hw, MII_DBG_DATA, 0x3000); 2835 atl2_write_phy_reg(hw, MII_DBG_ADDR, 3); 2836 atl2_write_phy_reg(hw, MII_DBG_DATA, 0); 2837 } 2838 2839 /* This is the only thing that needs to be changed to adjust the 2840 * maximum number of ports that the driver can manage. 2841 */ 2842 #define ATL2_MAX_NIC 4 2843 2844 #define OPTION_UNSET -1 2845 #define OPTION_DISABLED 0 2846 #define OPTION_ENABLED 1 2847 2848 /* All parameters are treated the same, as an integer array of values. 2849 * This macro just reduces the need to repeat the same declaration code 2850 * over and over (plus this helps to avoid typo bugs). 2851 */ 2852 #define ATL2_PARAM_INIT {[0 ... ATL2_MAX_NIC] = OPTION_UNSET} 2853 #ifndef module_param_array 2854 /* Module Parameters are always initialized to -1, so that the driver 2855 * can tell the difference between no user specified value or the 2856 * user asking for the default value. 2857 * The true default values are loaded in when atl2_check_options is called. 2858 * 2859 * This is a GCC extension to ANSI C. 2860 * See the item "Labeled Elements in Initializers" in the section 2861 * "Extensions to the C Language Family" of the GCC documentation. 2862 */ 2863 2864 #define ATL2_PARAM(X, desc) \ 2865 static const int __devinitdata X[ATL2_MAX_NIC + 1] = ATL2_PARAM_INIT; \ 2866 MODULE_PARM(X, "1-" __MODULE_STRING(ATL2_MAX_NIC) "i"); \ 2867 MODULE_PARM_DESC(X, desc); 2868 #else 2869 #define ATL2_PARAM(X, desc) \ 2870 static int __devinitdata X[ATL2_MAX_NIC+1] = ATL2_PARAM_INIT; \ 2871 static unsigned int num_##X; \ 2872 module_param_array_named(X, X, int, &num_##X, 0); \ 2873 MODULE_PARM_DESC(X, desc); 2874 #endif 2875 2876 /* 2877 * Transmit Memory Size 2878 * Valid Range: 64-2048 2879 * Default Value: 128 2880 */ 2881 #define ATL2_MIN_TX_MEMSIZE 4 /* 4KB */ 2882 #define ATL2_MAX_TX_MEMSIZE 64 /* 64KB */ 2883 #define ATL2_DEFAULT_TX_MEMSIZE 8 /* 8KB */ 2884 ATL2_PARAM(TxMemSize, "Bytes of Transmit Memory"); 2885 2886 /* 2887 * Receive Memory Block Count 2888 * Valid Range: 16-512 2889 * Default Value: 128 2890 */ 2891 #define ATL2_MIN_RXD_COUNT 16 2892 #define ATL2_MAX_RXD_COUNT 512 2893 #define ATL2_DEFAULT_RXD_COUNT 64 2894 ATL2_PARAM(RxMemBlock, "Number of receive memory block"); 2895 2896 /* 2897 * User Specified MediaType Override 2898 * 2899 * Valid Range: 0-5 2900 * - 0 - auto-negotiate at all supported speeds 2901 * - 1 - only link at 1000Mbps Full Duplex 2902 * - 2 - only link at 100Mbps Full Duplex 2903 * - 3 - only link at 100Mbps Half Duplex 2904 * - 4 - only link at 10Mbps Full Duplex 2905 * - 5 - only link at 10Mbps Half Duplex 2906 * Default Value: 0 2907 */ 2908 ATL2_PARAM(MediaType, "MediaType Select"); 2909 2910 /* 2911 * Interrupt Moderate Timer in units of 2048 ns (~2 us) 2912 * Valid Range: 10-65535 2913 * Default Value: 45000(90ms) 2914 */ 2915 #define INT_MOD_DEFAULT_CNT 100 /* 200us */ 2916 #define INT_MOD_MAX_CNT 65000 2917 #define INT_MOD_MIN_CNT 50 2918 ATL2_PARAM(IntModTimer, "Interrupt Moderator Timer"); 2919 2920 /* 2921 * FlashVendor 2922 * Valid Range: 0-2 2923 * 0 - Atmel 2924 * 1 - SST 2925 * 2 - ST 2926 */ 2927 ATL2_PARAM(FlashVendor, "SPI Flash Vendor"); 2928 2929 #define AUTONEG_ADV_DEFAULT 0x2F 2930 #define AUTONEG_ADV_MASK 0x2F 2931 #define FLOW_CONTROL_DEFAULT FLOW_CONTROL_FULL 2932 2933 #define FLASH_VENDOR_DEFAULT 0 2934 #define FLASH_VENDOR_MIN 0 2935 #define FLASH_VENDOR_MAX 2 2936 2937 struct atl2_option { 2938 enum { enable_option, range_option, list_option } type; 2939 char *name; 2940 char *err; 2941 int def; 2942 union { 2943 struct { /* range_option info */ 2944 int min; 2945 int max; 2946 } r; 2947 struct { /* list_option info */ 2948 int nr; 2949 struct atl2_opt_list { int i; char *str; } *p; 2950 } l; 2951 } arg; 2952 }; 2953 2954 static int __devinit atl2_validate_option(int *value, struct atl2_option *opt) 2955 { 2956 int i; 2957 struct atl2_opt_list *ent; 2958 2959 if (*value == OPTION_UNSET) { 2960 *value = opt->def; 2961 return 0; 2962 } 2963 2964 switch (opt->type) { 2965 case enable_option: 2966 switch (*value) { 2967 case OPTION_ENABLED: 2968 printk(KERN_INFO "%s Enabled\n", opt->name); 2969 return 0; 2970 break; 2971 case OPTION_DISABLED: 2972 printk(KERN_INFO "%s Disabled\n", opt->name); 2973 return 0; 2974 break; 2975 } 2976 break; 2977 case range_option: 2978 if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) { 2979 printk(KERN_INFO "%s set to %i\n", opt->name, *value); 2980 return 0; 2981 } 2982 break; 2983 case list_option: 2984 for (i = 0; i < opt->arg.l.nr; i++) { 2985 ent = &opt->arg.l.p[i]; 2986 if (*value == ent->i) { 2987 if (ent->str[0] != '\0') 2988 printk(KERN_INFO "%s\n", ent->str); 2989 return 0; 2990 } 2991 } 2992 break; 2993 default: 2994 BUG(); 2995 } 2996 2997 printk(KERN_INFO "Invalid %s specified (%i) %s\n", 2998 opt->name, *value, opt->err); 2999 *value = opt->def; 3000 return -1; 3001 } 3002 3003 /* 3004 * atl2_check_options - Range Checking for Command Line Parameters 3005 * @adapter: board private structure 3006 * 3007 * This routine checks all command line parameters for valid user 3008 * input. If an invalid value is given, or if no user specified 3009 * value exists, a default value is used. The final value is stored 3010 * in a variable in the adapter structure. 3011 */ 3012 static void __devinit atl2_check_options(struct atl2_adapter *adapter) 3013 { 3014 int val; 3015 struct atl2_option opt; 3016 int bd = adapter->bd_number; 3017 if (bd >= ATL2_MAX_NIC) { 3018 printk(KERN_NOTICE "Warning: no configuration for board #%i\n", 3019 bd); 3020 printk(KERN_NOTICE "Using defaults for all values\n"); 3021 #ifndef module_param_array 3022 bd = ATL2_MAX_NIC; 3023 #endif 3024 } 3025 3026 /* Bytes of Transmit Memory */ 3027 opt.type = range_option; 3028 opt.name = "Bytes of Transmit Memory"; 3029 opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_TX_MEMSIZE); 3030 opt.def = ATL2_DEFAULT_TX_MEMSIZE; 3031 opt.arg.r.min = ATL2_MIN_TX_MEMSIZE; 3032 opt.arg.r.max = ATL2_MAX_TX_MEMSIZE; 3033 #ifdef module_param_array 3034 if (num_TxMemSize > bd) { 3035 #endif 3036 val = TxMemSize[bd]; 3037 atl2_validate_option(&val, &opt); 3038 adapter->txd_ring_size = ((u32) val) * 1024; 3039 #ifdef module_param_array 3040 } else 3041 adapter->txd_ring_size = ((u32)opt.def) * 1024; 3042 #endif 3043 /* txs ring size: */ 3044 adapter->txs_ring_size = adapter->txd_ring_size / 128; 3045 if (adapter->txs_ring_size > 160) 3046 adapter->txs_ring_size = 160; 3047 3048 /* Receive Memory Block Count */ 3049 opt.type = range_option; 3050 opt.name = "Number of receive memory block"; 3051 opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_RXD_COUNT); 3052 opt.def = ATL2_DEFAULT_RXD_COUNT; 3053 opt.arg.r.min = ATL2_MIN_RXD_COUNT; 3054 opt.arg.r.max = ATL2_MAX_RXD_COUNT; 3055 #ifdef module_param_array 3056 if (num_RxMemBlock > bd) { 3057 #endif 3058 val = RxMemBlock[bd]; 3059 atl2_validate_option(&val, &opt); 3060 adapter->rxd_ring_size = (u32)val; 3061 /* FIXME */ 3062 /* ((u16)val)&~1; */ /* even number */ 3063 #ifdef module_param_array 3064 } else 3065 adapter->rxd_ring_size = (u32)opt.def; 3066 #endif 3067 /* init RXD Flow control value */ 3068 adapter->hw.fc_rxd_hi = (adapter->rxd_ring_size / 8) * 7; 3069 adapter->hw.fc_rxd_lo = (ATL2_MIN_RXD_COUNT / 8) > 3070 (adapter->rxd_ring_size / 12) ? (ATL2_MIN_RXD_COUNT / 8) : 3071 (adapter->rxd_ring_size / 12); 3072 3073 /* Interrupt Moderate Timer */ 3074 opt.type = range_option; 3075 opt.name = "Interrupt Moderate Timer"; 3076 opt.err = "using default of " __MODULE_STRING(INT_MOD_DEFAULT_CNT); 3077 opt.def = INT_MOD_DEFAULT_CNT; 3078 opt.arg.r.min = INT_MOD_MIN_CNT; 3079 opt.arg.r.max = INT_MOD_MAX_CNT; 3080 #ifdef module_param_array 3081 if (num_IntModTimer > bd) { 3082 #endif 3083 val = IntModTimer[bd]; 3084 atl2_validate_option(&val, &opt); 3085 adapter->imt = (u16) val; 3086 #ifdef module_param_array 3087 } else 3088 adapter->imt = (u16)(opt.def); 3089 #endif 3090 /* Flash Vendor */ 3091 opt.type = range_option; 3092 opt.name = "SPI Flash Vendor"; 3093 opt.err = "using default of " __MODULE_STRING(FLASH_VENDOR_DEFAULT); 3094 opt.def = FLASH_VENDOR_DEFAULT; 3095 opt.arg.r.min = FLASH_VENDOR_MIN; 3096 opt.arg.r.max = FLASH_VENDOR_MAX; 3097 #ifdef module_param_array 3098 if (num_FlashVendor > bd) { 3099 #endif 3100 val = FlashVendor[bd]; 3101 atl2_validate_option(&val, &opt); 3102 adapter->hw.flash_vendor = (u8) val; 3103 #ifdef module_param_array 3104 } else 3105 adapter->hw.flash_vendor = (u8)(opt.def); 3106 #endif 3107 /* MediaType */ 3108 opt.type = range_option; 3109 opt.name = "Speed/Duplex Selection"; 3110 opt.err = "using default of " __MODULE_STRING(MEDIA_TYPE_AUTO_SENSOR); 3111 opt.def = MEDIA_TYPE_AUTO_SENSOR; 3112 opt.arg.r.min = MEDIA_TYPE_AUTO_SENSOR; 3113 opt.arg.r.max = MEDIA_TYPE_10M_HALF; 3114 #ifdef module_param_array 3115 if (num_MediaType > bd) { 3116 #endif 3117 val = MediaType[bd]; 3118 atl2_validate_option(&val, &opt); 3119 adapter->hw.MediaType = (u16) val; 3120 #ifdef module_param_array 3121 } else 3122 adapter->hw.MediaType = (u16)(opt.def); 3123 #endif 3124 } 3125