1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright(c) 2006 - 2007 Atheros Corporation. All rights reserved. 4 * Copyright(c) 2007 - 2008 Chris Snook <csnook@redhat.com> 5 * 6 * Derived from Intel e1000 driver 7 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. 8 */ 9 10 #include <linux/atomic.h> 11 #include <linux/crc32.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/etherdevice.h> 14 #include <linux/ethtool.h> 15 #include <linux/hardirq.h> 16 #include <linux/if_vlan.h> 17 #include <linux/in.h> 18 #include <linux/interrupt.h> 19 #include <linux/ip.h> 20 #include <linux/irqflags.h> 21 #include <linux/irqreturn.h> 22 #include <linux/mii.h> 23 #include <linux/net.h> 24 #include <linux/netdevice.h> 25 #include <linux/pci.h> 26 #include <linux/pci_ids.h> 27 #include <linux/pm.h> 28 #include <linux/skbuff.h> 29 #include <linux/slab.h> 30 #include <linux/spinlock.h> 31 #include <linux/string.h> 32 #include <linux/tcp.h> 33 #include <linux/timer.h> 34 #include <linux/types.h> 35 #include <linux/workqueue.h> 36 37 #include "atl2.h" 38 39 static const char atl2_driver_name[] = "atl2"; 40 static const struct ethtool_ops atl2_ethtool_ops; 41 42 MODULE_AUTHOR("Atheros Corporation <xiong.huang@atheros.com>, Chris Snook <csnook@redhat.com>"); 43 MODULE_DESCRIPTION("Atheros Fast Ethernet Network Driver"); 44 MODULE_LICENSE("GPL"); 45 46 /* 47 * atl2_pci_tbl - PCI Device ID Table 48 */ 49 static const struct pci_device_id atl2_pci_tbl[] = { 50 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L2)}, 51 /* required last entry */ 52 {0,} 53 }; 54 MODULE_DEVICE_TABLE(pci, atl2_pci_tbl); 55 56 static void atl2_check_options(struct atl2_adapter *adapter); 57 58 /** 59 * atl2_sw_init - Initialize general software structures (struct atl2_adapter) 60 * @adapter: board private structure to initialize 61 * 62 * atl2_sw_init initializes the Adapter private data structure. 63 * Fields are initialized based on PCI device information and 64 * OS network device settings (MTU size). 65 */ 66 static int atl2_sw_init(struct atl2_adapter *adapter) 67 { 68 struct atl2_hw *hw = &adapter->hw; 69 struct pci_dev *pdev = adapter->pdev; 70 71 /* PCI config space info */ 72 hw->vendor_id = pdev->vendor; 73 hw->device_id = pdev->device; 74 hw->subsystem_vendor_id = pdev->subsystem_vendor; 75 hw->subsystem_id = pdev->subsystem_device; 76 hw->revision_id = pdev->revision; 77 78 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word); 79 80 adapter->wol = 0; 81 adapter->ict = 50000; /* ~100ms */ 82 adapter->link_speed = SPEED_0; /* hardware init */ 83 adapter->link_duplex = FULL_DUPLEX; 84 85 hw->phy_configured = false; 86 hw->preamble_len = 7; 87 hw->ipgt = 0x60; 88 hw->min_ifg = 0x50; 89 hw->ipgr1 = 0x40; 90 hw->ipgr2 = 0x60; 91 hw->retry_buf = 2; 92 hw->max_retry = 0xf; 93 hw->lcol = 0x37; 94 hw->jam_ipg = 7; 95 hw->fc_rxd_hi = 0; 96 hw->fc_rxd_lo = 0; 97 hw->max_frame_size = adapter->netdev->mtu; 98 99 spin_lock_init(&adapter->stats_lock); 100 101 set_bit(__ATL2_DOWN, &adapter->flags); 102 103 return 0; 104 } 105 106 /** 107 * atl2_set_multi - Multicast and Promiscuous mode set 108 * @netdev: network interface device structure 109 * 110 * The set_multi entry point is called whenever the multicast address 111 * list or the network interface flags are updated. This routine is 112 * responsible for configuring the hardware for proper multicast, 113 * promiscuous mode, and all-multi behavior. 114 */ 115 static void atl2_set_multi(struct net_device *netdev) 116 { 117 struct atl2_adapter *adapter = netdev_priv(netdev); 118 struct atl2_hw *hw = &adapter->hw; 119 struct netdev_hw_addr *ha; 120 u32 rctl; 121 u32 hash_value; 122 123 /* Check for Promiscuous and All Multicast modes */ 124 rctl = ATL2_READ_REG(hw, REG_MAC_CTRL); 125 126 if (netdev->flags & IFF_PROMISC) { 127 rctl |= MAC_CTRL_PROMIS_EN; 128 } else if (netdev->flags & IFF_ALLMULTI) { 129 rctl |= MAC_CTRL_MC_ALL_EN; 130 rctl &= ~MAC_CTRL_PROMIS_EN; 131 } else 132 rctl &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN); 133 134 ATL2_WRITE_REG(hw, REG_MAC_CTRL, rctl); 135 136 /* clear the old settings from the multicast hash table */ 137 ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0); 138 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0); 139 140 /* comoute mc addresses' hash value ,and put it into hash table */ 141 netdev_for_each_mc_addr(ha, netdev) { 142 hash_value = atl2_hash_mc_addr(hw, ha->addr); 143 atl2_hash_set(hw, hash_value); 144 } 145 } 146 147 static void init_ring_ptrs(struct atl2_adapter *adapter) 148 { 149 /* Read / Write Ptr Initialize: */ 150 adapter->txd_write_ptr = 0; 151 atomic_set(&adapter->txd_read_ptr, 0); 152 153 adapter->rxd_read_ptr = 0; 154 adapter->rxd_write_ptr = 0; 155 156 atomic_set(&adapter->txs_write_ptr, 0); 157 adapter->txs_next_clear = 0; 158 } 159 160 /** 161 * atl2_configure - Configure Transmit&Receive Unit after Reset 162 * @adapter: board private structure 163 * 164 * Configure the Tx /Rx unit of the MAC after a reset. 165 */ 166 static int atl2_configure(struct atl2_adapter *adapter) 167 { 168 struct atl2_hw *hw = &adapter->hw; 169 u32 value; 170 171 /* clear interrupt status */ 172 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0xffffffff); 173 174 /* set MAC Address */ 175 value = (((u32)hw->mac_addr[2]) << 24) | 176 (((u32)hw->mac_addr[3]) << 16) | 177 (((u32)hw->mac_addr[4]) << 8) | 178 (((u32)hw->mac_addr[5])); 179 ATL2_WRITE_REG(hw, REG_MAC_STA_ADDR, value); 180 value = (((u32)hw->mac_addr[0]) << 8) | 181 (((u32)hw->mac_addr[1])); 182 ATL2_WRITE_REG(hw, (REG_MAC_STA_ADDR+4), value); 183 184 /* HI base address */ 185 ATL2_WRITE_REG(hw, REG_DESC_BASE_ADDR_HI, 186 (u32)((adapter->ring_dma & 0xffffffff00000000ULL) >> 32)); 187 188 /* LO base address */ 189 ATL2_WRITE_REG(hw, REG_TXD_BASE_ADDR_LO, 190 (u32)(adapter->txd_dma & 0x00000000ffffffffULL)); 191 ATL2_WRITE_REG(hw, REG_TXS_BASE_ADDR_LO, 192 (u32)(adapter->txs_dma & 0x00000000ffffffffULL)); 193 ATL2_WRITE_REG(hw, REG_RXD_BASE_ADDR_LO, 194 (u32)(adapter->rxd_dma & 0x00000000ffffffffULL)); 195 196 /* element count */ 197 ATL2_WRITE_REGW(hw, REG_TXD_MEM_SIZE, (u16)(adapter->txd_ring_size/4)); 198 ATL2_WRITE_REGW(hw, REG_TXS_MEM_SIZE, (u16)adapter->txs_ring_size); 199 ATL2_WRITE_REGW(hw, REG_RXD_BUF_NUM, (u16)adapter->rxd_ring_size); 200 201 /* config Internal SRAM */ 202 /* 203 ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_tx_end); 204 ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_rx_end); 205 */ 206 207 /* config IPG/IFG */ 208 value = (((u32)hw->ipgt & MAC_IPG_IFG_IPGT_MASK) << 209 MAC_IPG_IFG_IPGT_SHIFT) | 210 (((u32)hw->min_ifg & MAC_IPG_IFG_MIFG_MASK) << 211 MAC_IPG_IFG_MIFG_SHIFT) | 212 (((u32)hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK) << 213 MAC_IPG_IFG_IPGR1_SHIFT)| 214 (((u32)hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK) << 215 MAC_IPG_IFG_IPGR2_SHIFT); 216 ATL2_WRITE_REG(hw, REG_MAC_IPG_IFG, value); 217 218 /* config Half-Duplex Control */ 219 value = ((u32)hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) | 220 (((u32)hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK) << 221 MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) | 222 MAC_HALF_DUPLX_CTRL_EXC_DEF_EN | 223 (0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) | 224 (((u32)hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK) << 225 MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT); 226 ATL2_WRITE_REG(hw, REG_MAC_HALF_DUPLX_CTRL, value); 227 228 /* set Interrupt Moderator Timer */ 229 ATL2_WRITE_REGW(hw, REG_IRQ_MODU_TIMER_INIT, adapter->imt); 230 ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_ITIMER_EN); 231 232 /* set Interrupt Clear Timer */ 233 ATL2_WRITE_REGW(hw, REG_CMBDISDMA_TIMER, adapter->ict); 234 235 /* set MTU */ 236 ATL2_WRITE_REG(hw, REG_MTU, adapter->netdev->mtu + 237 ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); 238 239 /* 1590 */ 240 ATL2_WRITE_REG(hw, REG_TX_CUT_THRESH, 0x177); 241 242 /* flow control */ 243 ATL2_WRITE_REGW(hw, REG_PAUSE_ON_TH, hw->fc_rxd_hi); 244 ATL2_WRITE_REGW(hw, REG_PAUSE_OFF_TH, hw->fc_rxd_lo); 245 246 /* Init mailbox */ 247 ATL2_WRITE_REGW(hw, REG_MB_TXD_WR_IDX, (u16)adapter->txd_write_ptr); 248 ATL2_WRITE_REGW(hw, REG_MB_RXD_RD_IDX, (u16)adapter->rxd_read_ptr); 249 250 /* enable DMA read/write */ 251 ATL2_WRITE_REGB(hw, REG_DMAR, DMAR_EN); 252 ATL2_WRITE_REGB(hw, REG_DMAW, DMAW_EN); 253 254 value = ATL2_READ_REG(&adapter->hw, REG_ISR); 255 if ((value & ISR_PHY_LINKDOWN) != 0) 256 value = 1; /* config failed */ 257 else 258 value = 0; 259 260 /* clear all interrupt status */ 261 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0x3fffffff); 262 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0); 263 return value; 264 } 265 266 /** 267 * atl2_setup_ring_resources - allocate Tx / RX descriptor resources 268 * @adapter: board private structure 269 * 270 * Return 0 on success, negative on failure 271 */ 272 static s32 atl2_setup_ring_resources(struct atl2_adapter *adapter) 273 { 274 struct pci_dev *pdev = adapter->pdev; 275 int size; 276 u8 offset = 0; 277 278 /* real ring DMA buffer */ 279 adapter->ring_size = size = 280 adapter->txd_ring_size * 1 + 7 + /* dword align */ 281 adapter->txs_ring_size * 4 + 7 + /* dword align */ 282 adapter->rxd_ring_size * 1536 + 127; /* 128bytes align */ 283 284 adapter->ring_vir_addr = pci_alloc_consistent(pdev, size, 285 &adapter->ring_dma); 286 if (!adapter->ring_vir_addr) 287 return -ENOMEM; 288 289 /* Init TXD Ring */ 290 adapter->txd_dma = adapter->ring_dma ; 291 offset = (adapter->txd_dma & 0x7) ? (8 - (adapter->txd_dma & 0x7)) : 0; 292 adapter->txd_dma += offset; 293 adapter->txd_ring = adapter->ring_vir_addr + offset; 294 295 /* Init TXS Ring */ 296 adapter->txs_dma = adapter->txd_dma + adapter->txd_ring_size; 297 offset = (adapter->txs_dma & 0x7) ? (8 - (adapter->txs_dma & 0x7)) : 0; 298 adapter->txs_dma += offset; 299 adapter->txs_ring = (struct tx_pkt_status *) 300 (((u8 *)adapter->txd_ring) + (adapter->txd_ring_size + offset)); 301 302 /* Init RXD Ring */ 303 adapter->rxd_dma = adapter->txs_dma + adapter->txs_ring_size * 4; 304 offset = (adapter->rxd_dma & 127) ? 305 (128 - (adapter->rxd_dma & 127)) : 0; 306 if (offset > 7) 307 offset -= 8; 308 else 309 offset += (128 - 8); 310 311 adapter->rxd_dma += offset; 312 adapter->rxd_ring = (struct rx_desc *) (((u8 *)adapter->txs_ring) + 313 (adapter->txs_ring_size * 4 + offset)); 314 315 /* 316 * Read / Write Ptr Initialize: 317 * init_ring_ptrs(adapter); 318 */ 319 return 0; 320 } 321 322 /** 323 * atl2_irq_enable - Enable default interrupt generation settings 324 * @adapter: board private structure 325 */ 326 static inline void atl2_irq_enable(struct atl2_adapter *adapter) 327 { 328 ATL2_WRITE_REG(&adapter->hw, REG_IMR, IMR_NORMAL_MASK); 329 ATL2_WRITE_FLUSH(&adapter->hw); 330 } 331 332 /** 333 * atl2_irq_disable - Mask off interrupt generation on the NIC 334 * @adapter: board private structure 335 */ 336 static inline void atl2_irq_disable(struct atl2_adapter *adapter) 337 { 338 ATL2_WRITE_REG(&adapter->hw, REG_IMR, 0); 339 ATL2_WRITE_FLUSH(&adapter->hw); 340 synchronize_irq(adapter->pdev->irq); 341 } 342 343 static void __atl2_vlan_mode(netdev_features_t features, u32 *ctrl) 344 { 345 if (features & NETIF_F_HW_VLAN_CTAG_RX) { 346 /* enable VLAN tag insert/strip */ 347 *ctrl |= MAC_CTRL_RMV_VLAN; 348 } else { 349 /* disable VLAN tag insert/strip */ 350 *ctrl &= ~MAC_CTRL_RMV_VLAN; 351 } 352 } 353 354 static void atl2_vlan_mode(struct net_device *netdev, 355 netdev_features_t features) 356 { 357 struct atl2_adapter *adapter = netdev_priv(netdev); 358 u32 ctrl; 359 360 atl2_irq_disable(adapter); 361 362 ctrl = ATL2_READ_REG(&adapter->hw, REG_MAC_CTRL); 363 __atl2_vlan_mode(features, &ctrl); 364 ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl); 365 366 atl2_irq_enable(adapter); 367 } 368 369 static void atl2_restore_vlan(struct atl2_adapter *adapter) 370 { 371 atl2_vlan_mode(adapter->netdev, adapter->netdev->features); 372 } 373 374 static netdev_features_t atl2_fix_features(struct net_device *netdev, 375 netdev_features_t features) 376 { 377 /* 378 * Since there is no support for separate rx/tx vlan accel 379 * enable/disable make sure tx flag is always in same state as rx. 380 */ 381 if (features & NETIF_F_HW_VLAN_CTAG_RX) 382 features |= NETIF_F_HW_VLAN_CTAG_TX; 383 else 384 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 385 386 return features; 387 } 388 389 static int atl2_set_features(struct net_device *netdev, 390 netdev_features_t features) 391 { 392 netdev_features_t changed = netdev->features ^ features; 393 394 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 395 atl2_vlan_mode(netdev, features); 396 397 return 0; 398 } 399 400 static void atl2_intr_rx(struct atl2_adapter *adapter) 401 { 402 struct net_device *netdev = adapter->netdev; 403 struct rx_desc *rxd; 404 struct sk_buff *skb; 405 406 do { 407 rxd = adapter->rxd_ring+adapter->rxd_write_ptr; 408 if (!rxd->status.update) 409 break; /* end of tx */ 410 411 /* clear this flag at once */ 412 rxd->status.update = 0; 413 414 if (rxd->status.ok && rxd->status.pkt_size >= 60) { 415 int rx_size = (int)(rxd->status.pkt_size - 4); 416 /* alloc new buffer */ 417 skb = netdev_alloc_skb_ip_align(netdev, rx_size); 418 if (NULL == skb) { 419 /* 420 * Check that some rx space is free. If not, 421 * free one and mark stats->rx_dropped++. 422 */ 423 netdev->stats.rx_dropped++; 424 break; 425 } 426 memcpy(skb->data, rxd->packet, rx_size); 427 skb_put(skb, rx_size); 428 skb->protocol = eth_type_trans(skb, netdev); 429 if (rxd->status.vlan) { 430 u16 vlan_tag = (rxd->status.vtag>>4) | 431 ((rxd->status.vtag&7) << 13) | 432 ((rxd->status.vtag&8) << 9); 433 434 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag); 435 } 436 netif_rx(skb); 437 netdev->stats.rx_bytes += rx_size; 438 netdev->stats.rx_packets++; 439 } else { 440 netdev->stats.rx_errors++; 441 442 if (rxd->status.ok && rxd->status.pkt_size <= 60) 443 netdev->stats.rx_length_errors++; 444 if (rxd->status.mcast) 445 netdev->stats.multicast++; 446 if (rxd->status.crc) 447 netdev->stats.rx_crc_errors++; 448 if (rxd->status.align) 449 netdev->stats.rx_frame_errors++; 450 } 451 452 /* advance write ptr */ 453 if (++adapter->rxd_write_ptr == adapter->rxd_ring_size) 454 adapter->rxd_write_ptr = 0; 455 } while (1); 456 457 /* update mailbox? */ 458 adapter->rxd_read_ptr = adapter->rxd_write_ptr; 459 ATL2_WRITE_REGW(&adapter->hw, REG_MB_RXD_RD_IDX, adapter->rxd_read_ptr); 460 } 461 462 static void atl2_intr_tx(struct atl2_adapter *adapter) 463 { 464 struct net_device *netdev = adapter->netdev; 465 u32 txd_read_ptr; 466 u32 txs_write_ptr; 467 struct tx_pkt_status *txs; 468 struct tx_pkt_header *txph; 469 int free_hole = 0; 470 471 do { 472 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr); 473 txs = adapter->txs_ring + txs_write_ptr; 474 if (!txs->update) 475 break; /* tx stop here */ 476 477 free_hole = 1; 478 txs->update = 0; 479 480 if (++txs_write_ptr == adapter->txs_ring_size) 481 txs_write_ptr = 0; 482 atomic_set(&adapter->txs_write_ptr, (int)txs_write_ptr); 483 484 txd_read_ptr = (u32) atomic_read(&adapter->txd_read_ptr); 485 txph = (struct tx_pkt_header *) 486 (((u8 *)adapter->txd_ring) + txd_read_ptr); 487 488 if (txph->pkt_size != txs->pkt_size) { 489 struct tx_pkt_status *old_txs = txs; 490 printk(KERN_WARNING 491 "%s: txs packet size not consistent with txd" 492 " txd_:0x%08x, txs_:0x%08x!\n", 493 adapter->netdev->name, 494 *(u32 *)txph, *(u32 *)txs); 495 printk(KERN_WARNING 496 "txd read ptr: 0x%x\n", 497 txd_read_ptr); 498 txs = adapter->txs_ring + txs_write_ptr; 499 printk(KERN_WARNING 500 "txs-behind:0x%08x\n", 501 *(u32 *)txs); 502 if (txs_write_ptr < 2) { 503 txs = adapter->txs_ring + 504 (adapter->txs_ring_size + 505 txs_write_ptr - 2); 506 } else { 507 txs = adapter->txs_ring + (txs_write_ptr - 2); 508 } 509 printk(KERN_WARNING 510 "txs-before:0x%08x\n", 511 *(u32 *)txs); 512 txs = old_txs; 513 } 514 515 /* 4for TPH */ 516 txd_read_ptr += (((u32)(txph->pkt_size) + 7) & ~3); 517 if (txd_read_ptr >= adapter->txd_ring_size) 518 txd_read_ptr -= adapter->txd_ring_size; 519 520 atomic_set(&adapter->txd_read_ptr, (int)txd_read_ptr); 521 522 /* tx statistics: */ 523 if (txs->ok) { 524 netdev->stats.tx_bytes += txs->pkt_size; 525 netdev->stats.tx_packets++; 526 } 527 else 528 netdev->stats.tx_errors++; 529 530 if (txs->defer) 531 netdev->stats.collisions++; 532 if (txs->abort_col) 533 netdev->stats.tx_aborted_errors++; 534 if (txs->late_col) 535 netdev->stats.tx_window_errors++; 536 if (txs->underrun) 537 netdev->stats.tx_fifo_errors++; 538 } while (1); 539 540 if (free_hole) { 541 if (netif_queue_stopped(adapter->netdev) && 542 netif_carrier_ok(adapter->netdev)) 543 netif_wake_queue(adapter->netdev); 544 } 545 } 546 547 static void atl2_check_for_link(struct atl2_adapter *adapter) 548 { 549 struct net_device *netdev = adapter->netdev; 550 u16 phy_data = 0; 551 552 spin_lock(&adapter->stats_lock); 553 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data); 554 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data); 555 spin_unlock(&adapter->stats_lock); 556 557 /* notify upper layer link down ASAP */ 558 if (!(phy_data & BMSR_LSTATUS)) { /* Link Down */ 559 if (netif_carrier_ok(netdev)) { /* old link state: Up */ 560 printk(KERN_INFO "%s: %s NIC Link is Down\n", 561 atl2_driver_name, netdev->name); 562 adapter->link_speed = SPEED_0; 563 netif_carrier_off(netdev); 564 netif_stop_queue(netdev); 565 } 566 } 567 schedule_work(&adapter->link_chg_task); 568 } 569 570 static inline void atl2_clear_phy_int(struct atl2_adapter *adapter) 571 { 572 u16 phy_data; 573 spin_lock(&adapter->stats_lock); 574 atl2_read_phy_reg(&adapter->hw, 19, &phy_data); 575 spin_unlock(&adapter->stats_lock); 576 } 577 578 /** 579 * atl2_intr - Interrupt Handler 580 * @irq: interrupt number 581 * @data: pointer to a network interface device structure 582 */ 583 static irqreturn_t atl2_intr(int irq, void *data) 584 { 585 struct atl2_adapter *adapter = netdev_priv(data); 586 struct atl2_hw *hw = &adapter->hw; 587 u32 status; 588 589 status = ATL2_READ_REG(hw, REG_ISR); 590 if (0 == status) 591 return IRQ_NONE; 592 593 /* link event */ 594 if (status & ISR_PHY) 595 atl2_clear_phy_int(adapter); 596 597 /* clear ISR status, and Enable CMB DMA/Disable Interrupt */ 598 ATL2_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT); 599 600 /* check if PCIE PHY Link down */ 601 if (status & ISR_PHY_LINKDOWN) { 602 if (netif_running(adapter->netdev)) { /* reset MAC */ 603 ATL2_WRITE_REG(hw, REG_ISR, 0); 604 ATL2_WRITE_REG(hw, REG_IMR, 0); 605 ATL2_WRITE_FLUSH(hw); 606 schedule_work(&adapter->reset_task); 607 return IRQ_HANDLED; 608 } 609 } 610 611 /* check if DMA read/write error? */ 612 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) { 613 ATL2_WRITE_REG(hw, REG_ISR, 0); 614 ATL2_WRITE_REG(hw, REG_IMR, 0); 615 ATL2_WRITE_FLUSH(hw); 616 schedule_work(&adapter->reset_task); 617 return IRQ_HANDLED; 618 } 619 620 /* link event */ 621 if (status & (ISR_PHY | ISR_MANUAL)) { 622 adapter->netdev->stats.tx_carrier_errors++; 623 atl2_check_for_link(adapter); 624 } 625 626 /* transmit event */ 627 if (status & ISR_TX_EVENT) 628 atl2_intr_tx(adapter); 629 630 /* rx exception */ 631 if (status & ISR_RX_EVENT) 632 atl2_intr_rx(adapter); 633 634 /* re-enable Interrupt */ 635 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0); 636 return IRQ_HANDLED; 637 } 638 639 static int atl2_request_irq(struct atl2_adapter *adapter) 640 { 641 struct net_device *netdev = adapter->netdev; 642 int flags, err = 0; 643 644 flags = IRQF_SHARED; 645 adapter->have_msi = true; 646 err = pci_enable_msi(adapter->pdev); 647 if (err) 648 adapter->have_msi = false; 649 650 if (adapter->have_msi) 651 flags &= ~IRQF_SHARED; 652 653 return request_irq(adapter->pdev->irq, atl2_intr, flags, netdev->name, 654 netdev); 655 } 656 657 /** 658 * atl2_free_ring_resources - Free Tx / RX descriptor Resources 659 * @adapter: board private structure 660 * 661 * Free all transmit software resources 662 */ 663 static void atl2_free_ring_resources(struct atl2_adapter *adapter) 664 { 665 struct pci_dev *pdev = adapter->pdev; 666 pci_free_consistent(pdev, adapter->ring_size, adapter->ring_vir_addr, 667 adapter->ring_dma); 668 } 669 670 /** 671 * atl2_open - Called when a network interface is made active 672 * @netdev: network interface device structure 673 * 674 * Returns 0 on success, negative value on failure 675 * 676 * The open entry point is called when a network interface is made 677 * active by the system (IFF_UP). At this point all resources needed 678 * for transmit and receive operations are allocated, the interrupt 679 * handler is registered with the OS, the watchdog timer is started, 680 * and the stack is notified that the interface is ready. 681 */ 682 static int atl2_open(struct net_device *netdev) 683 { 684 struct atl2_adapter *adapter = netdev_priv(netdev); 685 int err; 686 u32 val; 687 688 /* disallow open during test */ 689 if (test_bit(__ATL2_TESTING, &adapter->flags)) 690 return -EBUSY; 691 692 /* allocate transmit descriptors */ 693 err = atl2_setup_ring_resources(adapter); 694 if (err) 695 return err; 696 697 err = atl2_init_hw(&adapter->hw); 698 if (err) { 699 err = -EIO; 700 goto err_init_hw; 701 } 702 703 /* hardware has been reset, we need to reload some things */ 704 atl2_set_multi(netdev); 705 init_ring_ptrs(adapter); 706 707 atl2_restore_vlan(adapter); 708 709 if (atl2_configure(adapter)) { 710 err = -EIO; 711 goto err_config; 712 } 713 714 err = atl2_request_irq(adapter); 715 if (err) 716 goto err_req_irq; 717 718 clear_bit(__ATL2_DOWN, &adapter->flags); 719 720 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 4*HZ)); 721 722 val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL); 723 ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, 724 val | MASTER_CTRL_MANUAL_INT); 725 726 atl2_irq_enable(adapter); 727 728 return 0; 729 730 err_init_hw: 731 err_req_irq: 732 err_config: 733 atl2_free_ring_resources(adapter); 734 atl2_reset_hw(&adapter->hw); 735 736 return err; 737 } 738 739 static void atl2_down(struct atl2_adapter *adapter) 740 { 741 struct net_device *netdev = adapter->netdev; 742 743 /* signal that we're down so the interrupt handler does not 744 * reschedule our watchdog timer */ 745 set_bit(__ATL2_DOWN, &adapter->flags); 746 747 netif_tx_disable(netdev); 748 749 /* reset MAC to disable all RX/TX */ 750 atl2_reset_hw(&adapter->hw); 751 msleep(1); 752 753 atl2_irq_disable(adapter); 754 755 del_timer_sync(&adapter->watchdog_timer); 756 del_timer_sync(&adapter->phy_config_timer); 757 clear_bit(0, &adapter->cfg_phy); 758 759 netif_carrier_off(netdev); 760 adapter->link_speed = SPEED_0; 761 adapter->link_duplex = -1; 762 } 763 764 static void atl2_free_irq(struct atl2_adapter *adapter) 765 { 766 struct net_device *netdev = adapter->netdev; 767 768 free_irq(adapter->pdev->irq, netdev); 769 770 #ifdef CONFIG_PCI_MSI 771 if (adapter->have_msi) 772 pci_disable_msi(adapter->pdev); 773 #endif 774 } 775 776 /** 777 * atl2_close - Disables a network interface 778 * @netdev: network interface device structure 779 * 780 * Returns 0, this is not allowed to fail 781 * 782 * The close entry point is called when an interface is de-activated 783 * by the OS. The hardware is still under the drivers control, but 784 * needs to be disabled. A global MAC reset is issued to stop the 785 * hardware, and all transmit and receive resources are freed. 786 */ 787 static int atl2_close(struct net_device *netdev) 788 { 789 struct atl2_adapter *adapter = netdev_priv(netdev); 790 791 WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags)); 792 793 atl2_down(adapter); 794 atl2_free_irq(adapter); 795 atl2_free_ring_resources(adapter); 796 797 return 0; 798 } 799 800 static inline int TxsFreeUnit(struct atl2_adapter *adapter) 801 { 802 u32 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr); 803 804 return (adapter->txs_next_clear >= txs_write_ptr) ? 805 (int) (adapter->txs_ring_size - adapter->txs_next_clear + 806 txs_write_ptr - 1) : 807 (int) (txs_write_ptr - adapter->txs_next_clear - 1); 808 } 809 810 static inline int TxdFreeBytes(struct atl2_adapter *adapter) 811 { 812 u32 txd_read_ptr = (u32)atomic_read(&adapter->txd_read_ptr); 813 814 return (adapter->txd_write_ptr >= txd_read_ptr) ? 815 (int) (adapter->txd_ring_size - adapter->txd_write_ptr + 816 txd_read_ptr - 1) : 817 (int) (txd_read_ptr - adapter->txd_write_ptr - 1); 818 } 819 820 static netdev_tx_t atl2_xmit_frame(struct sk_buff *skb, 821 struct net_device *netdev) 822 { 823 struct atl2_adapter *adapter = netdev_priv(netdev); 824 struct tx_pkt_header *txph; 825 u32 offset, copy_len; 826 int txs_unused; 827 int txbuf_unused; 828 829 if (test_bit(__ATL2_DOWN, &adapter->flags)) { 830 dev_kfree_skb_any(skb); 831 return NETDEV_TX_OK; 832 } 833 834 if (unlikely(skb->len <= 0)) { 835 dev_kfree_skb_any(skb); 836 return NETDEV_TX_OK; 837 } 838 839 txs_unused = TxsFreeUnit(adapter); 840 txbuf_unused = TxdFreeBytes(adapter); 841 842 if (skb->len + sizeof(struct tx_pkt_header) + 4 > txbuf_unused || 843 txs_unused < 1) { 844 /* not enough resources */ 845 netif_stop_queue(netdev); 846 return NETDEV_TX_BUSY; 847 } 848 849 offset = adapter->txd_write_ptr; 850 851 txph = (struct tx_pkt_header *) (((u8 *)adapter->txd_ring) + offset); 852 853 *(u32 *)txph = 0; 854 txph->pkt_size = skb->len; 855 856 offset += 4; 857 if (offset >= adapter->txd_ring_size) 858 offset -= adapter->txd_ring_size; 859 copy_len = adapter->txd_ring_size - offset; 860 if (copy_len >= skb->len) { 861 memcpy(((u8 *)adapter->txd_ring) + offset, skb->data, skb->len); 862 offset += ((u32)(skb->len + 3) & ~3); 863 } else { 864 memcpy(((u8 *)adapter->txd_ring)+offset, skb->data, copy_len); 865 memcpy((u8 *)adapter->txd_ring, skb->data+copy_len, 866 skb->len-copy_len); 867 offset = ((u32)(skb->len-copy_len + 3) & ~3); 868 } 869 #ifdef NETIF_F_HW_VLAN_CTAG_TX 870 if (skb_vlan_tag_present(skb)) { 871 u16 vlan_tag = skb_vlan_tag_get(skb); 872 vlan_tag = (vlan_tag << 4) | 873 (vlan_tag >> 13) | 874 ((vlan_tag >> 9) & 0x8); 875 txph->ins_vlan = 1; 876 txph->vlan = vlan_tag; 877 } 878 #endif 879 if (offset >= adapter->txd_ring_size) 880 offset -= adapter->txd_ring_size; 881 adapter->txd_write_ptr = offset; 882 883 /* clear txs before send */ 884 adapter->txs_ring[adapter->txs_next_clear].update = 0; 885 if (++adapter->txs_next_clear == adapter->txs_ring_size) 886 adapter->txs_next_clear = 0; 887 888 ATL2_WRITE_REGW(&adapter->hw, REG_MB_TXD_WR_IDX, 889 (adapter->txd_write_ptr >> 2)); 890 891 dev_consume_skb_any(skb); 892 return NETDEV_TX_OK; 893 } 894 895 /** 896 * atl2_change_mtu - Change the Maximum Transfer Unit 897 * @netdev: network interface device structure 898 * @new_mtu: new value for maximum frame size 899 * 900 * Returns 0 on success, negative on failure 901 */ 902 static int atl2_change_mtu(struct net_device *netdev, int new_mtu) 903 { 904 struct atl2_adapter *adapter = netdev_priv(netdev); 905 struct atl2_hw *hw = &adapter->hw; 906 907 /* set MTU */ 908 netdev->mtu = new_mtu; 909 hw->max_frame_size = new_mtu; 910 ATL2_WRITE_REG(hw, REG_MTU, new_mtu + ETH_HLEN + 911 VLAN_HLEN + ETH_FCS_LEN); 912 913 return 0; 914 } 915 916 /** 917 * atl2_set_mac - Change the Ethernet Address of the NIC 918 * @netdev: network interface device structure 919 * @p: pointer to an address structure 920 * 921 * Returns 0 on success, negative on failure 922 */ 923 static int atl2_set_mac(struct net_device *netdev, void *p) 924 { 925 struct atl2_adapter *adapter = netdev_priv(netdev); 926 struct sockaddr *addr = p; 927 928 if (!is_valid_ether_addr(addr->sa_data)) 929 return -EADDRNOTAVAIL; 930 931 if (netif_running(netdev)) 932 return -EBUSY; 933 934 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 935 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len); 936 937 atl2_set_mac_addr(&adapter->hw); 938 939 return 0; 940 } 941 942 static int atl2_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 943 { 944 struct atl2_adapter *adapter = netdev_priv(netdev); 945 struct mii_ioctl_data *data = if_mii(ifr); 946 unsigned long flags; 947 948 switch (cmd) { 949 case SIOCGMIIPHY: 950 data->phy_id = 0; 951 break; 952 case SIOCGMIIREG: 953 spin_lock_irqsave(&adapter->stats_lock, flags); 954 if (atl2_read_phy_reg(&adapter->hw, 955 data->reg_num & 0x1F, &data->val_out)) { 956 spin_unlock_irqrestore(&adapter->stats_lock, flags); 957 return -EIO; 958 } 959 spin_unlock_irqrestore(&adapter->stats_lock, flags); 960 break; 961 case SIOCSMIIREG: 962 if (data->reg_num & ~(0x1F)) 963 return -EFAULT; 964 spin_lock_irqsave(&adapter->stats_lock, flags); 965 if (atl2_write_phy_reg(&adapter->hw, data->reg_num, 966 data->val_in)) { 967 spin_unlock_irqrestore(&adapter->stats_lock, flags); 968 return -EIO; 969 } 970 spin_unlock_irqrestore(&adapter->stats_lock, flags); 971 break; 972 default: 973 return -EOPNOTSUPP; 974 } 975 return 0; 976 } 977 978 static int atl2_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 979 { 980 switch (cmd) { 981 case SIOCGMIIPHY: 982 case SIOCGMIIREG: 983 case SIOCSMIIREG: 984 return atl2_mii_ioctl(netdev, ifr, cmd); 985 #ifdef ETHTOOL_OPS_COMPAT 986 case SIOCETHTOOL: 987 return ethtool_ioctl(ifr); 988 #endif 989 default: 990 return -EOPNOTSUPP; 991 } 992 } 993 994 /** 995 * atl2_tx_timeout - Respond to a Tx Hang 996 * @netdev: network interface device structure 997 */ 998 static void atl2_tx_timeout(struct net_device *netdev, unsigned int txqueue) 999 { 1000 struct atl2_adapter *adapter = netdev_priv(netdev); 1001 1002 /* Do the reset outside of interrupt context */ 1003 schedule_work(&adapter->reset_task); 1004 } 1005 1006 /** 1007 * atl2_watchdog - Timer Call-back 1008 * @data: pointer to netdev cast into an unsigned long 1009 */ 1010 static void atl2_watchdog(struct timer_list *t) 1011 { 1012 struct atl2_adapter *adapter = from_timer(adapter, t, watchdog_timer); 1013 1014 if (!test_bit(__ATL2_DOWN, &adapter->flags)) { 1015 u32 drop_rxd, drop_rxs; 1016 unsigned long flags; 1017 1018 spin_lock_irqsave(&adapter->stats_lock, flags); 1019 drop_rxd = ATL2_READ_REG(&adapter->hw, REG_STS_RXD_OV); 1020 drop_rxs = ATL2_READ_REG(&adapter->hw, REG_STS_RXS_OV); 1021 spin_unlock_irqrestore(&adapter->stats_lock, flags); 1022 1023 adapter->netdev->stats.rx_over_errors += drop_rxd + drop_rxs; 1024 1025 /* Reset the timer */ 1026 mod_timer(&adapter->watchdog_timer, 1027 round_jiffies(jiffies + 4 * HZ)); 1028 } 1029 } 1030 1031 /** 1032 * atl2_phy_config - Timer Call-back 1033 * @data: pointer to netdev cast into an unsigned long 1034 */ 1035 static void atl2_phy_config(struct timer_list *t) 1036 { 1037 struct atl2_adapter *adapter = from_timer(adapter, t, 1038 phy_config_timer); 1039 struct atl2_hw *hw = &adapter->hw; 1040 unsigned long flags; 1041 1042 spin_lock_irqsave(&adapter->stats_lock, flags); 1043 atl2_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg); 1044 atl2_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN | 1045 MII_CR_RESTART_AUTO_NEG); 1046 spin_unlock_irqrestore(&adapter->stats_lock, flags); 1047 clear_bit(0, &adapter->cfg_phy); 1048 } 1049 1050 static int atl2_up(struct atl2_adapter *adapter) 1051 { 1052 struct net_device *netdev = adapter->netdev; 1053 int err = 0; 1054 u32 val; 1055 1056 /* hardware has been reset, we need to reload some things */ 1057 1058 err = atl2_init_hw(&adapter->hw); 1059 if (err) { 1060 err = -EIO; 1061 return err; 1062 } 1063 1064 atl2_set_multi(netdev); 1065 init_ring_ptrs(adapter); 1066 1067 atl2_restore_vlan(adapter); 1068 1069 if (atl2_configure(adapter)) { 1070 err = -EIO; 1071 goto err_up; 1072 } 1073 1074 clear_bit(__ATL2_DOWN, &adapter->flags); 1075 1076 val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL); 1077 ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, val | 1078 MASTER_CTRL_MANUAL_INT); 1079 1080 atl2_irq_enable(adapter); 1081 1082 err_up: 1083 return err; 1084 } 1085 1086 static void atl2_reinit_locked(struct atl2_adapter *adapter) 1087 { 1088 WARN_ON(in_interrupt()); 1089 while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags)) 1090 msleep(1); 1091 atl2_down(adapter); 1092 atl2_up(adapter); 1093 clear_bit(__ATL2_RESETTING, &adapter->flags); 1094 } 1095 1096 static void atl2_reset_task(struct work_struct *work) 1097 { 1098 struct atl2_adapter *adapter; 1099 adapter = container_of(work, struct atl2_adapter, reset_task); 1100 1101 atl2_reinit_locked(adapter); 1102 } 1103 1104 static void atl2_setup_mac_ctrl(struct atl2_adapter *adapter) 1105 { 1106 u32 value; 1107 struct atl2_hw *hw = &adapter->hw; 1108 struct net_device *netdev = adapter->netdev; 1109 1110 /* Config MAC CTRL Register */ 1111 value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY; 1112 1113 /* duplex */ 1114 if (FULL_DUPLEX == adapter->link_duplex) 1115 value |= MAC_CTRL_DUPLX; 1116 1117 /* flow control */ 1118 value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW); 1119 1120 /* PAD & CRC */ 1121 value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD); 1122 1123 /* preamble length */ 1124 value |= (((u32)adapter->hw.preamble_len & MAC_CTRL_PRMLEN_MASK) << 1125 MAC_CTRL_PRMLEN_SHIFT); 1126 1127 /* vlan */ 1128 __atl2_vlan_mode(netdev->features, &value); 1129 1130 /* filter mode */ 1131 value |= MAC_CTRL_BC_EN; 1132 if (netdev->flags & IFF_PROMISC) 1133 value |= MAC_CTRL_PROMIS_EN; 1134 else if (netdev->flags & IFF_ALLMULTI) 1135 value |= MAC_CTRL_MC_ALL_EN; 1136 1137 /* half retry buffer */ 1138 value |= (((u32)(adapter->hw.retry_buf & 1139 MAC_CTRL_HALF_LEFT_BUF_MASK)) << MAC_CTRL_HALF_LEFT_BUF_SHIFT); 1140 1141 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value); 1142 } 1143 1144 static int atl2_check_link(struct atl2_adapter *adapter) 1145 { 1146 struct atl2_hw *hw = &adapter->hw; 1147 struct net_device *netdev = adapter->netdev; 1148 int ret_val; 1149 u16 speed, duplex, phy_data; 1150 int reconfig = 0; 1151 1152 /* MII_BMSR must read twise */ 1153 atl2_read_phy_reg(hw, MII_BMSR, &phy_data); 1154 atl2_read_phy_reg(hw, MII_BMSR, &phy_data); 1155 if (!(phy_data&BMSR_LSTATUS)) { /* link down */ 1156 if (netif_carrier_ok(netdev)) { /* old link state: Up */ 1157 u32 value; 1158 /* disable rx */ 1159 value = ATL2_READ_REG(hw, REG_MAC_CTRL); 1160 value &= ~MAC_CTRL_RX_EN; 1161 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value); 1162 adapter->link_speed = SPEED_0; 1163 netif_carrier_off(netdev); 1164 netif_stop_queue(netdev); 1165 } 1166 return 0; 1167 } 1168 1169 /* Link Up */ 1170 ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex); 1171 if (ret_val) 1172 return ret_val; 1173 switch (hw->MediaType) { 1174 case MEDIA_TYPE_100M_FULL: 1175 if (speed != SPEED_100 || duplex != FULL_DUPLEX) 1176 reconfig = 1; 1177 break; 1178 case MEDIA_TYPE_100M_HALF: 1179 if (speed != SPEED_100 || duplex != HALF_DUPLEX) 1180 reconfig = 1; 1181 break; 1182 case MEDIA_TYPE_10M_FULL: 1183 if (speed != SPEED_10 || duplex != FULL_DUPLEX) 1184 reconfig = 1; 1185 break; 1186 case MEDIA_TYPE_10M_HALF: 1187 if (speed != SPEED_10 || duplex != HALF_DUPLEX) 1188 reconfig = 1; 1189 break; 1190 } 1191 /* link result is our setting */ 1192 if (reconfig == 0) { 1193 if (adapter->link_speed != speed || 1194 adapter->link_duplex != duplex) { 1195 adapter->link_speed = speed; 1196 adapter->link_duplex = duplex; 1197 atl2_setup_mac_ctrl(adapter); 1198 printk(KERN_INFO "%s: %s NIC Link is Up<%d Mbps %s>\n", 1199 atl2_driver_name, netdev->name, 1200 adapter->link_speed, 1201 adapter->link_duplex == FULL_DUPLEX ? 1202 "Full Duplex" : "Half Duplex"); 1203 } 1204 1205 if (!netif_carrier_ok(netdev)) { /* Link down -> Up */ 1206 netif_carrier_on(netdev); 1207 netif_wake_queue(netdev); 1208 } 1209 return 0; 1210 } 1211 1212 /* change original link status */ 1213 if (netif_carrier_ok(netdev)) { 1214 u32 value; 1215 /* disable rx */ 1216 value = ATL2_READ_REG(hw, REG_MAC_CTRL); 1217 value &= ~MAC_CTRL_RX_EN; 1218 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value); 1219 1220 adapter->link_speed = SPEED_0; 1221 netif_carrier_off(netdev); 1222 netif_stop_queue(netdev); 1223 } 1224 1225 /* auto-neg, insert timer to re-config phy 1226 * (if interval smaller than 5 seconds, something strange) */ 1227 if (!test_bit(__ATL2_DOWN, &adapter->flags)) { 1228 if (!test_and_set_bit(0, &adapter->cfg_phy)) 1229 mod_timer(&adapter->phy_config_timer, 1230 round_jiffies(jiffies + 5 * HZ)); 1231 } 1232 1233 return 0; 1234 } 1235 1236 /** 1237 * atl2_link_chg_task - deal with link change event Out of interrupt context 1238 */ 1239 static void atl2_link_chg_task(struct work_struct *work) 1240 { 1241 struct atl2_adapter *adapter; 1242 unsigned long flags; 1243 1244 adapter = container_of(work, struct atl2_adapter, link_chg_task); 1245 1246 spin_lock_irqsave(&adapter->stats_lock, flags); 1247 atl2_check_link(adapter); 1248 spin_unlock_irqrestore(&adapter->stats_lock, flags); 1249 } 1250 1251 static void atl2_setup_pcicmd(struct pci_dev *pdev) 1252 { 1253 u16 cmd; 1254 1255 pci_read_config_word(pdev, PCI_COMMAND, &cmd); 1256 1257 if (cmd & PCI_COMMAND_INTX_DISABLE) 1258 cmd &= ~PCI_COMMAND_INTX_DISABLE; 1259 if (cmd & PCI_COMMAND_IO) 1260 cmd &= ~PCI_COMMAND_IO; 1261 if (0 == (cmd & PCI_COMMAND_MEMORY)) 1262 cmd |= PCI_COMMAND_MEMORY; 1263 if (0 == (cmd & PCI_COMMAND_MASTER)) 1264 cmd |= PCI_COMMAND_MASTER; 1265 pci_write_config_word(pdev, PCI_COMMAND, cmd); 1266 1267 /* 1268 * some motherboards BIOS(PXE/EFI) driver may set PME 1269 * while they transfer control to OS (Windows/Linux) 1270 * so we should clear this bit before NIC work normally 1271 */ 1272 pci_write_config_dword(pdev, REG_PM_CTRLSTAT, 0); 1273 } 1274 1275 #ifdef CONFIG_NET_POLL_CONTROLLER 1276 static void atl2_poll_controller(struct net_device *netdev) 1277 { 1278 disable_irq(netdev->irq); 1279 atl2_intr(netdev->irq, netdev); 1280 enable_irq(netdev->irq); 1281 } 1282 #endif 1283 1284 1285 static const struct net_device_ops atl2_netdev_ops = { 1286 .ndo_open = atl2_open, 1287 .ndo_stop = atl2_close, 1288 .ndo_start_xmit = atl2_xmit_frame, 1289 .ndo_set_rx_mode = atl2_set_multi, 1290 .ndo_validate_addr = eth_validate_addr, 1291 .ndo_set_mac_address = atl2_set_mac, 1292 .ndo_change_mtu = atl2_change_mtu, 1293 .ndo_fix_features = atl2_fix_features, 1294 .ndo_set_features = atl2_set_features, 1295 .ndo_do_ioctl = atl2_ioctl, 1296 .ndo_tx_timeout = atl2_tx_timeout, 1297 #ifdef CONFIG_NET_POLL_CONTROLLER 1298 .ndo_poll_controller = atl2_poll_controller, 1299 #endif 1300 }; 1301 1302 /** 1303 * atl2_probe - Device Initialization Routine 1304 * @pdev: PCI device information struct 1305 * @ent: entry in atl2_pci_tbl 1306 * 1307 * Returns 0 on success, negative on failure 1308 * 1309 * atl2_probe initializes an adapter identified by a pci_dev structure. 1310 * The OS initialization, configuring of the adapter private structure, 1311 * and a hardware reset occur. 1312 */ 1313 static int atl2_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1314 { 1315 struct net_device *netdev; 1316 struct atl2_adapter *adapter; 1317 static int cards_found = 0; 1318 unsigned long mmio_start; 1319 int mmio_len; 1320 int err; 1321 1322 err = pci_enable_device(pdev); 1323 if (err) 1324 return err; 1325 1326 /* 1327 * atl2 is a shared-high-32-bit device, so we're stuck with 32-bit DMA 1328 * until the kernel has the proper infrastructure to support 64-bit DMA 1329 * on these devices. 1330 */ 1331 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) && 1332 pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) { 1333 printk(KERN_ERR "atl2: No usable DMA configuration, aborting\n"); 1334 err = -EIO; 1335 goto err_dma; 1336 } 1337 1338 /* Mark all PCI regions associated with PCI device 1339 * pdev as being reserved by owner atl2_driver_name */ 1340 err = pci_request_regions(pdev, atl2_driver_name); 1341 if (err) 1342 goto err_pci_reg; 1343 1344 /* Enables bus-mastering on the device and calls 1345 * pcibios_set_master to do the needed arch specific settings */ 1346 pci_set_master(pdev); 1347 1348 netdev = alloc_etherdev(sizeof(struct atl2_adapter)); 1349 if (!netdev) { 1350 err = -ENOMEM; 1351 goto err_alloc_etherdev; 1352 } 1353 1354 SET_NETDEV_DEV(netdev, &pdev->dev); 1355 1356 pci_set_drvdata(pdev, netdev); 1357 adapter = netdev_priv(netdev); 1358 adapter->netdev = netdev; 1359 adapter->pdev = pdev; 1360 adapter->hw.back = adapter; 1361 1362 mmio_start = pci_resource_start(pdev, 0x0); 1363 mmio_len = pci_resource_len(pdev, 0x0); 1364 1365 adapter->hw.mem_rang = (u32)mmio_len; 1366 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len); 1367 if (!adapter->hw.hw_addr) { 1368 err = -EIO; 1369 goto err_ioremap; 1370 } 1371 1372 atl2_setup_pcicmd(pdev); 1373 1374 netdev->netdev_ops = &atl2_netdev_ops; 1375 netdev->ethtool_ops = &atl2_ethtool_ops; 1376 netdev->watchdog_timeo = 5 * HZ; 1377 netdev->min_mtu = 40; 1378 netdev->max_mtu = ETH_DATA_LEN + VLAN_HLEN; 1379 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); 1380 1381 netdev->mem_start = mmio_start; 1382 netdev->mem_end = mmio_start + mmio_len; 1383 adapter->bd_number = cards_found; 1384 adapter->pci_using_64 = false; 1385 1386 /* setup the private structure */ 1387 err = atl2_sw_init(adapter); 1388 if (err) 1389 goto err_sw_init; 1390 1391 netdev->hw_features = NETIF_F_HW_VLAN_CTAG_RX; 1392 netdev->features |= (NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX); 1393 1394 /* Init PHY as early as possible due to power saving issue */ 1395 atl2_phy_init(&adapter->hw); 1396 1397 /* reset the controller to 1398 * put the device in a known good starting state */ 1399 1400 if (atl2_reset_hw(&adapter->hw)) { 1401 err = -EIO; 1402 goto err_reset; 1403 } 1404 1405 /* copy the MAC address out of the EEPROM */ 1406 atl2_read_mac_addr(&adapter->hw); 1407 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len); 1408 if (!is_valid_ether_addr(netdev->dev_addr)) { 1409 err = -EIO; 1410 goto err_eeprom; 1411 } 1412 1413 atl2_check_options(adapter); 1414 1415 timer_setup(&adapter->watchdog_timer, atl2_watchdog, 0); 1416 1417 timer_setup(&adapter->phy_config_timer, atl2_phy_config, 0); 1418 1419 INIT_WORK(&adapter->reset_task, atl2_reset_task); 1420 INIT_WORK(&adapter->link_chg_task, atl2_link_chg_task); 1421 1422 strcpy(netdev->name, "eth%d"); /* ?? */ 1423 err = register_netdev(netdev); 1424 if (err) 1425 goto err_register; 1426 1427 /* assume we have no link for now */ 1428 netif_carrier_off(netdev); 1429 netif_stop_queue(netdev); 1430 1431 cards_found++; 1432 1433 return 0; 1434 1435 err_reset: 1436 err_register: 1437 err_sw_init: 1438 err_eeprom: 1439 iounmap(adapter->hw.hw_addr); 1440 err_ioremap: 1441 free_netdev(netdev); 1442 err_alloc_etherdev: 1443 pci_release_regions(pdev); 1444 err_pci_reg: 1445 err_dma: 1446 pci_disable_device(pdev); 1447 return err; 1448 } 1449 1450 /** 1451 * atl2_remove - Device Removal Routine 1452 * @pdev: PCI device information struct 1453 * 1454 * atl2_remove is called by the PCI subsystem to alert the driver 1455 * that it should release a PCI device. The could be caused by a 1456 * Hot-Plug event, or because the driver is going to be removed from 1457 * memory. 1458 */ 1459 /* FIXME: write the original MAC address back in case it was changed from a 1460 * BIOS-set value, as in atl1 -- CHS */ 1461 static void atl2_remove(struct pci_dev *pdev) 1462 { 1463 struct net_device *netdev = pci_get_drvdata(pdev); 1464 struct atl2_adapter *adapter = netdev_priv(netdev); 1465 1466 /* flush_scheduled work may reschedule our watchdog task, so 1467 * explicitly disable watchdog tasks from being rescheduled */ 1468 set_bit(__ATL2_DOWN, &adapter->flags); 1469 1470 del_timer_sync(&adapter->watchdog_timer); 1471 del_timer_sync(&adapter->phy_config_timer); 1472 cancel_work_sync(&adapter->reset_task); 1473 cancel_work_sync(&adapter->link_chg_task); 1474 1475 unregister_netdev(netdev); 1476 1477 atl2_force_ps(&adapter->hw); 1478 1479 iounmap(adapter->hw.hw_addr); 1480 pci_release_regions(pdev); 1481 1482 free_netdev(netdev); 1483 1484 pci_disable_device(pdev); 1485 } 1486 1487 static int atl2_suspend(struct pci_dev *pdev, pm_message_t state) 1488 { 1489 struct net_device *netdev = pci_get_drvdata(pdev); 1490 struct atl2_adapter *adapter = netdev_priv(netdev); 1491 struct atl2_hw *hw = &adapter->hw; 1492 u16 speed, duplex; 1493 u32 ctrl = 0; 1494 u32 wufc = adapter->wol; 1495 1496 #ifdef CONFIG_PM 1497 int retval = 0; 1498 #endif 1499 1500 netif_device_detach(netdev); 1501 1502 if (netif_running(netdev)) { 1503 WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags)); 1504 atl2_down(adapter); 1505 } 1506 1507 #ifdef CONFIG_PM 1508 retval = pci_save_state(pdev); 1509 if (retval) 1510 return retval; 1511 #endif 1512 1513 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl); 1514 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl); 1515 if (ctrl & BMSR_LSTATUS) 1516 wufc &= ~ATLX_WUFC_LNKC; 1517 1518 if (0 != (ctrl & BMSR_LSTATUS) && 0 != wufc) { 1519 u32 ret_val; 1520 /* get current link speed & duplex */ 1521 ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex); 1522 if (ret_val) { 1523 printk(KERN_DEBUG 1524 "%s: get speed&duplex error while suspend\n", 1525 atl2_driver_name); 1526 goto wol_dis; 1527 } 1528 1529 ctrl = 0; 1530 1531 /* turn on magic packet wol */ 1532 if (wufc & ATLX_WUFC_MAG) 1533 ctrl |= (WOL_MAGIC_EN | WOL_MAGIC_PME_EN); 1534 1535 /* ignore Link Chg event when Link is up */ 1536 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl); 1537 1538 /* Config MAC CTRL Register */ 1539 ctrl = MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY; 1540 if (FULL_DUPLEX == adapter->link_duplex) 1541 ctrl |= MAC_CTRL_DUPLX; 1542 ctrl |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD); 1543 ctrl |= (((u32)adapter->hw.preamble_len & 1544 MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT); 1545 ctrl |= (((u32)(adapter->hw.retry_buf & 1546 MAC_CTRL_HALF_LEFT_BUF_MASK)) << 1547 MAC_CTRL_HALF_LEFT_BUF_SHIFT); 1548 if (wufc & ATLX_WUFC_MAG) { 1549 /* magic packet maybe Broadcast&multicast&Unicast */ 1550 ctrl |= MAC_CTRL_BC_EN; 1551 } 1552 1553 ATL2_WRITE_REG(hw, REG_MAC_CTRL, ctrl); 1554 1555 /* pcie patch */ 1556 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC); 1557 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET; 1558 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl); 1559 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1); 1560 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK; 1561 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl); 1562 1563 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1); 1564 goto suspend_exit; 1565 } 1566 1567 if (0 == (ctrl&BMSR_LSTATUS) && 0 != (wufc&ATLX_WUFC_LNKC)) { 1568 /* link is down, so only LINK CHG WOL event enable */ 1569 ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN); 1570 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl); 1571 ATL2_WRITE_REG(hw, REG_MAC_CTRL, 0); 1572 1573 /* pcie patch */ 1574 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC); 1575 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET; 1576 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl); 1577 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1); 1578 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK; 1579 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl); 1580 1581 hw->phy_configured = false; /* re-init PHY when resume */ 1582 1583 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1); 1584 1585 goto suspend_exit; 1586 } 1587 1588 wol_dis: 1589 /* WOL disabled */ 1590 ATL2_WRITE_REG(hw, REG_WOL_CTRL, 0); 1591 1592 /* pcie patch */ 1593 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC); 1594 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET; 1595 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl); 1596 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1); 1597 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK; 1598 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl); 1599 1600 atl2_force_ps(hw); 1601 hw->phy_configured = false; /* re-init PHY when resume */ 1602 1603 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0); 1604 1605 suspend_exit: 1606 if (netif_running(netdev)) 1607 atl2_free_irq(adapter); 1608 1609 pci_disable_device(pdev); 1610 1611 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 1612 1613 return 0; 1614 } 1615 1616 #ifdef CONFIG_PM 1617 static int atl2_resume(struct pci_dev *pdev) 1618 { 1619 struct net_device *netdev = pci_get_drvdata(pdev); 1620 struct atl2_adapter *adapter = netdev_priv(netdev); 1621 u32 err; 1622 1623 pci_set_power_state(pdev, PCI_D0); 1624 pci_restore_state(pdev); 1625 1626 err = pci_enable_device(pdev); 1627 if (err) { 1628 printk(KERN_ERR 1629 "atl2: Cannot enable PCI device from suspend\n"); 1630 return err; 1631 } 1632 1633 pci_set_master(pdev); 1634 1635 ATL2_READ_REG(&adapter->hw, REG_WOL_CTRL); /* clear WOL status */ 1636 1637 pci_enable_wake(pdev, PCI_D3hot, 0); 1638 pci_enable_wake(pdev, PCI_D3cold, 0); 1639 1640 ATL2_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0); 1641 1642 if (netif_running(netdev)) { 1643 err = atl2_request_irq(adapter); 1644 if (err) 1645 return err; 1646 } 1647 1648 atl2_reset_hw(&adapter->hw); 1649 1650 if (netif_running(netdev)) 1651 atl2_up(adapter); 1652 1653 netif_device_attach(netdev); 1654 1655 return 0; 1656 } 1657 #endif 1658 1659 static void atl2_shutdown(struct pci_dev *pdev) 1660 { 1661 atl2_suspend(pdev, PMSG_SUSPEND); 1662 } 1663 1664 static struct pci_driver atl2_driver = { 1665 .name = atl2_driver_name, 1666 .id_table = atl2_pci_tbl, 1667 .probe = atl2_probe, 1668 .remove = atl2_remove, 1669 /* Power Management Hooks */ 1670 .suspend = atl2_suspend, 1671 #ifdef CONFIG_PM 1672 .resume = atl2_resume, 1673 #endif 1674 .shutdown = atl2_shutdown, 1675 }; 1676 1677 /** 1678 * atl2_init_module - Driver Registration Routine 1679 * 1680 * atl2_init_module is the first routine called when the driver is 1681 * loaded. All it does is register with the PCI subsystem. 1682 */ 1683 static int __init atl2_init_module(void) 1684 { 1685 return pci_register_driver(&atl2_driver); 1686 } 1687 module_init(atl2_init_module); 1688 1689 /** 1690 * atl2_exit_module - Driver Exit Cleanup Routine 1691 * 1692 * atl2_exit_module is called just before the driver is removed 1693 * from memory. 1694 */ 1695 static void __exit atl2_exit_module(void) 1696 { 1697 pci_unregister_driver(&atl2_driver); 1698 } 1699 module_exit(atl2_exit_module); 1700 1701 static void atl2_read_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value) 1702 { 1703 struct atl2_adapter *adapter = hw->back; 1704 pci_read_config_word(adapter->pdev, reg, value); 1705 } 1706 1707 static void atl2_write_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value) 1708 { 1709 struct atl2_adapter *adapter = hw->back; 1710 pci_write_config_word(adapter->pdev, reg, *value); 1711 } 1712 1713 static int atl2_get_link_ksettings(struct net_device *netdev, 1714 struct ethtool_link_ksettings *cmd) 1715 { 1716 struct atl2_adapter *adapter = netdev_priv(netdev); 1717 struct atl2_hw *hw = &adapter->hw; 1718 u32 supported, advertising; 1719 1720 supported = (SUPPORTED_10baseT_Half | 1721 SUPPORTED_10baseT_Full | 1722 SUPPORTED_100baseT_Half | 1723 SUPPORTED_100baseT_Full | 1724 SUPPORTED_Autoneg | 1725 SUPPORTED_TP); 1726 advertising = ADVERTISED_TP; 1727 1728 advertising |= ADVERTISED_Autoneg; 1729 advertising |= hw->autoneg_advertised; 1730 1731 cmd->base.port = PORT_TP; 1732 cmd->base.phy_address = 0; 1733 1734 if (adapter->link_speed != SPEED_0) { 1735 cmd->base.speed = adapter->link_speed; 1736 if (adapter->link_duplex == FULL_DUPLEX) 1737 cmd->base.duplex = DUPLEX_FULL; 1738 else 1739 cmd->base.duplex = DUPLEX_HALF; 1740 } else { 1741 cmd->base.speed = SPEED_UNKNOWN; 1742 cmd->base.duplex = DUPLEX_UNKNOWN; 1743 } 1744 1745 cmd->base.autoneg = AUTONEG_ENABLE; 1746 1747 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 1748 supported); 1749 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 1750 advertising); 1751 1752 return 0; 1753 } 1754 1755 static int atl2_set_link_ksettings(struct net_device *netdev, 1756 const struct ethtool_link_ksettings *cmd) 1757 { 1758 struct atl2_adapter *adapter = netdev_priv(netdev); 1759 struct atl2_hw *hw = &adapter->hw; 1760 u32 advertising; 1761 1762 ethtool_convert_link_mode_to_legacy_u32(&advertising, 1763 cmd->link_modes.advertising); 1764 1765 while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags)) 1766 msleep(1); 1767 1768 if (cmd->base.autoneg == AUTONEG_ENABLE) { 1769 #define MY_ADV_MASK (ADVERTISE_10_HALF | \ 1770 ADVERTISE_10_FULL | \ 1771 ADVERTISE_100_HALF| \ 1772 ADVERTISE_100_FULL) 1773 1774 if ((advertising & MY_ADV_MASK) == MY_ADV_MASK) { 1775 hw->MediaType = MEDIA_TYPE_AUTO_SENSOR; 1776 hw->autoneg_advertised = MY_ADV_MASK; 1777 } else if ((advertising & MY_ADV_MASK) == ADVERTISE_100_FULL) { 1778 hw->MediaType = MEDIA_TYPE_100M_FULL; 1779 hw->autoneg_advertised = ADVERTISE_100_FULL; 1780 } else if ((advertising & MY_ADV_MASK) == ADVERTISE_100_HALF) { 1781 hw->MediaType = MEDIA_TYPE_100M_HALF; 1782 hw->autoneg_advertised = ADVERTISE_100_HALF; 1783 } else if ((advertising & MY_ADV_MASK) == ADVERTISE_10_FULL) { 1784 hw->MediaType = MEDIA_TYPE_10M_FULL; 1785 hw->autoneg_advertised = ADVERTISE_10_FULL; 1786 } else if ((advertising & MY_ADV_MASK) == ADVERTISE_10_HALF) { 1787 hw->MediaType = MEDIA_TYPE_10M_HALF; 1788 hw->autoneg_advertised = ADVERTISE_10_HALF; 1789 } else { 1790 clear_bit(__ATL2_RESETTING, &adapter->flags); 1791 return -EINVAL; 1792 } 1793 advertising = hw->autoneg_advertised | 1794 ADVERTISED_TP | ADVERTISED_Autoneg; 1795 } else { 1796 clear_bit(__ATL2_RESETTING, &adapter->flags); 1797 return -EINVAL; 1798 } 1799 1800 /* reset the link */ 1801 if (netif_running(adapter->netdev)) { 1802 atl2_down(adapter); 1803 atl2_up(adapter); 1804 } else 1805 atl2_reset_hw(&adapter->hw); 1806 1807 clear_bit(__ATL2_RESETTING, &adapter->flags); 1808 return 0; 1809 } 1810 1811 static u32 atl2_get_msglevel(struct net_device *netdev) 1812 { 1813 return 0; 1814 } 1815 1816 /* 1817 * It's sane for this to be empty, but we might want to take advantage of this. 1818 */ 1819 static void atl2_set_msglevel(struct net_device *netdev, u32 data) 1820 { 1821 } 1822 1823 static int atl2_get_regs_len(struct net_device *netdev) 1824 { 1825 #define ATL2_REGS_LEN 42 1826 return sizeof(u32) * ATL2_REGS_LEN; 1827 } 1828 1829 static void atl2_get_regs(struct net_device *netdev, 1830 struct ethtool_regs *regs, void *p) 1831 { 1832 struct atl2_adapter *adapter = netdev_priv(netdev); 1833 struct atl2_hw *hw = &adapter->hw; 1834 u32 *regs_buff = p; 1835 u16 phy_data; 1836 1837 memset(p, 0, sizeof(u32) * ATL2_REGS_LEN); 1838 1839 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id; 1840 1841 regs_buff[0] = ATL2_READ_REG(hw, REG_VPD_CAP); 1842 regs_buff[1] = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL); 1843 regs_buff[2] = ATL2_READ_REG(hw, REG_SPI_FLASH_CONFIG); 1844 regs_buff[3] = ATL2_READ_REG(hw, REG_TWSI_CTRL); 1845 regs_buff[4] = ATL2_READ_REG(hw, REG_PCIE_DEV_MISC_CTRL); 1846 regs_buff[5] = ATL2_READ_REG(hw, REG_MASTER_CTRL); 1847 regs_buff[6] = ATL2_READ_REG(hw, REG_MANUAL_TIMER_INIT); 1848 regs_buff[7] = ATL2_READ_REG(hw, REG_IRQ_MODU_TIMER_INIT); 1849 regs_buff[8] = ATL2_READ_REG(hw, REG_PHY_ENABLE); 1850 regs_buff[9] = ATL2_READ_REG(hw, REG_CMBDISDMA_TIMER); 1851 regs_buff[10] = ATL2_READ_REG(hw, REG_IDLE_STATUS); 1852 regs_buff[11] = ATL2_READ_REG(hw, REG_MDIO_CTRL); 1853 regs_buff[12] = ATL2_READ_REG(hw, REG_SERDES_LOCK); 1854 regs_buff[13] = ATL2_READ_REG(hw, REG_MAC_CTRL); 1855 regs_buff[14] = ATL2_READ_REG(hw, REG_MAC_IPG_IFG); 1856 regs_buff[15] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR); 1857 regs_buff[16] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR+4); 1858 regs_buff[17] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE); 1859 regs_buff[18] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE+4); 1860 regs_buff[19] = ATL2_READ_REG(hw, REG_MAC_HALF_DUPLX_CTRL); 1861 regs_buff[20] = ATL2_READ_REG(hw, REG_MTU); 1862 regs_buff[21] = ATL2_READ_REG(hw, REG_WOL_CTRL); 1863 regs_buff[22] = ATL2_READ_REG(hw, REG_SRAM_TXRAM_END); 1864 regs_buff[23] = ATL2_READ_REG(hw, REG_DESC_BASE_ADDR_HI); 1865 regs_buff[24] = ATL2_READ_REG(hw, REG_TXD_BASE_ADDR_LO); 1866 regs_buff[25] = ATL2_READ_REG(hw, REG_TXD_MEM_SIZE); 1867 regs_buff[26] = ATL2_READ_REG(hw, REG_TXS_BASE_ADDR_LO); 1868 regs_buff[27] = ATL2_READ_REG(hw, REG_TXS_MEM_SIZE); 1869 regs_buff[28] = ATL2_READ_REG(hw, REG_RXD_BASE_ADDR_LO); 1870 regs_buff[29] = ATL2_READ_REG(hw, REG_RXD_BUF_NUM); 1871 regs_buff[30] = ATL2_READ_REG(hw, REG_DMAR); 1872 regs_buff[31] = ATL2_READ_REG(hw, REG_TX_CUT_THRESH); 1873 regs_buff[32] = ATL2_READ_REG(hw, REG_DMAW); 1874 regs_buff[33] = ATL2_READ_REG(hw, REG_PAUSE_ON_TH); 1875 regs_buff[34] = ATL2_READ_REG(hw, REG_PAUSE_OFF_TH); 1876 regs_buff[35] = ATL2_READ_REG(hw, REG_MB_TXD_WR_IDX); 1877 regs_buff[36] = ATL2_READ_REG(hw, REG_MB_RXD_RD_IDX); 1878 regs_buff[38] = ATL2_READ_REG(hw, REG_ISR); 1879 regs_buff[39] = ATL2_READ_REG(hw, REG_IMR); 1880 1881 atl2_read_phy_reg(hw, MII_BMCR, &phy_data); 1882 regs_buff[40] = (u32)phy_data; 1883 atl2_read_phy_reg(hw, MII_BMSR, &phy_data); 1884 regs_buff[41] = (u32)phy_data; 1885 } 1886 1887 static int atl2_get_eeprom_len(struct net_device *netdev) 1888 { 1889 struct atl2_adapter *adapter = netdev_priv(netdev); 1890 1891 if (!atl2_check_eeprom_exist(&adapter->hw)) 1892 return 512; 1893 else 1894 return 0; 1895 } 1896 1897 static int atl2_get_eeprom(struct net_device *netdev, 1898 struct ethtool_eeprom *eeprom, u8 *bytes) 1899 { 1900 struct atl2_adapter *adapter = netdev_priv(netdev); 1901 struct atl2_hw *hw = &adapter->hw; 1902 u32 *eeprom_buff; 1903 int first_dword, last_dword; 1904 int ret_val = 0; 1905 int i; 1906 1907 if (eeprom->len == 0) 1908 return -EINVAL; 1909 1910 if (atl2_check_eeprom_exist(hw)) 1911 return -EINVAL; 1912 1913 eeprom->magic = hw->vendor_id | (hw->device_id << 16); 1914 1915 first_dword = eeprom->offset >> 2; 1916 last_dword = (eeprom->offset + eeprom->len - 1) >> 2; 1917 1918 eeprom_buff = kmalloc_array(last_dword - first_dword + 1, sizeof(u32), 1919 GFP_KERNEL); 1920 if (!eeprom_buff) 1921 return -ENOMEM; 1922 1923 for (i = first_dword; i < last_dword; i++) { 1924 if (!atl2_read_eeprom(hw, i*4, &(eeprom_buff[i-first_dword]))) { 1925 ret_val = -EIO; 1926 goto free; 1927 } 1928 } 1929 1930 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 3), 1931 eeprom->len); 1932 free: 1933 kfree(eeprom_buff); 1934 1935 return ret_val; 1936 } 1937 1938 static int atl2_set_eeprom(struct net_device *netdev, 1939 struct ethtool_eeprom *eeprom, u8 *bytes) 1940 { 1941 struct atl2_adapter *adapter = netdev_priv(netdev); 1942 struct atl2_hw *hw = &adapter->hw; 1943 u32 *eeprom_buff; 1944 u32 *ptr; 1945 int max_len, first_dword, last_dword, ret_val = 0; 1946 int i; 1947 1948 if (eeprom->len == 0) 1949 return -EOPNOTSUPP; 1950 1951 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16))) 1952 return -EFAULT; 1953 1954 max_len = 512; 1955 1956 first_dword = eeprom->offset >> 2; 1957 last_dword = (eeprom->offset + eeprom->len - 1) >> 2; 1958 eeprom_buff = kmalloc(max_len, GFP_KERNEL); 1959 if (!eeprom_buff) 1960 return -ENOMEM; 1961 1962 ptr = eeprom_buff; 1963 1964 if (eeprom->offset & 3) { 1965 /* need read/modify/write of first changed EEPROM word */ 1966 /* only the second byte of the word is being modified */ 1967 if (!atl2_read_eeprom(hw, first_dword*4, &(eeprom_buff[0]))) { 1968 ret_val = -EIO; 1969 goto out; 1970 } 1971 ptr++; 1972 } 1973 if (((eeprom->offset + eeprom->len) & 3)) { 1974 /* 1975 * need read/modify/write of last changed EEPROM word 1976 * only the first byte of the word is being modified 1977 */ 1978 if (!atl2_read_eeprom(hw, last_dword * 4, 1979 &(eeprom_buff[last_dword - first_dword]))) { 1980 ret_val = -EIO; 1981 goto out; 1982 } 1983 } 1984 1985 /* Device's eeprom is always little-endian, word addressable */ 1986 memcpy(ptr, bytes, eeprom->len); 1987 1988 for (i = 0; i < last_dword - first_dword + 1; i++) { 1989 if (!atl2_write_eeprom(hw, ((first_dword+i)*4), eeprom_buff[i])) { 1990 ret_val = -EIO; 1991 goto out; 1992 } 1993 } 1994 out: 1995 kfree(eeprom_buff); 1996 return ret_val; 1997 } 1998 1999 static void atl2_get_drvinfo(struct net_device *netdev, 2000 struct ethtool_drvinfo *drvinfo) 2001 { 2002 struct atl2_adapter *adapter = netdev_priv(netdev); 2003 2004 strlcpy(drvinfo->driver, atl2_driver_name, sizeof(drvinfo->driver)); 2005 strlcpy(drvinfo->fw_version, "L2", sizeof(drvinfo->fw_version)); 2006 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev), 2007 sizeof(drvinfo->bus_info)); 2008 } 2009 2010 static void atl2_get_wol(struct net_device *netdev, 2011 struct ethtool_wolinfo *wol) 2012 { 2013 struct atl2_adapter *adapter = netdev_priv(netdev); 2014 2015 wol->supported = WAKE_MAGIC; 2016 wol->wolopts = 0; 2017 2018 if (adapter->wol & ATLX_WUFC_EX) 2019 wol->wolopts |= WAKE_UCAST; 2020 if (adapter->wol & ATLX_WUFC_MC) 2021 wol->wolopts |= WAKE_MCAST; 2022 if (adapter->wol & ATLX_WUFC_BC) 2023 wol->wolopts |= WAKE_BCAST; 2024 if (adapter->wol & ATLX_WUFC_MAG) 2025 wol->wolopts |= WAKE_MAGIC; 2026 if (adapter->wol & ATLX_WUFC_LNKC) 2027 wol->wolopts |= WAKE_PHY; 2028 } 2029 2030 static int atl2_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 2031 { 2032 struct atl2_adapter *adapter = netdev_priv(netdev); 2033 2034 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE)) 2035 return -EOPNOTSUPP; 2036 2037 if (wol->wolopts & (WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)) 2038 return -EOPNOTSUPP; 2039 2040 /* these settings will always override what we currently have */ 2041 adapter->wol = 0; 2042 2043 if (wol->wolopts & WAKE_MAGIC) 2044 adapter->wol |= ATLX_WUFC_MAG; 2045 if (wol->wolopts & WAKE_PHY) 2046 adapter->wol |= ATLX_WUFC_LNKC; 2047 2048 return 0; 2049 } 2050 2051 static int atl2_nway_reset(struct net_device *netdev) 2052 { 2053 struct atl2_adapter *adapter = netdev_priv(netdev); 2054 if (netif_running(netdev)) 2055 atl2_reinit_locked(adapter); 2056 return 0; 2057 } 2058 2059 static const struct ethtool_ops atl2_ethtool_ops = { 2060 .get_drvinfo = atl2_get_drvinfo, 2061 .get_regs_len = atl2_get_regs_len, 2062 .get_regs = atl2_get_regs, 2063 .get_wol = atl2_get_wol, 2064 .set_wol = atl2_set_wol, 2065 .get_msglevel = atl2_get_msglevel, 2066 .set_msglevel = atl2_set_msglevel, 2067 .nway_reset = atl2_nway_reset, 2068 .get_link = ethtool_op_get_link, 2069 .get_eeprom_len = atl2_get_eeprom_len, 2070 .get_eeprom = atl2_get_eeprom, 2071 .set_eeprom = atl2_set_eeprom, 2072 .get_link_ksettings = atl2_get_link_ksettings, 2073 .set_link_ksettings = atl2_set_link_ksettings, 2074 }; 2075 2076 #define LBYTESWAP(a) ((((a) & 0x00ff00ff) << 8) | \ 2077 (((a) & 0xff00ff00) >> 8)) 2078 #define LONGSWAP(a) ((LBYTESWAP(a) << 16) | (LBYTESWAP(a) >> 16)) 2079 #define SHORTSWAP(a) (((a) << 8) | ((a) >> 8)) 2080 2081 /* 2082 * Reset the transmit and receive units; mask and clear all interrupts. 2083 * 2084 * hw - Struct containing variables accessed by shared code 2085 * return : 0 or idle status (if error) 2086 */ 2087 static s32 atl2_reset_hw(struct atl2_hw *hw) 2088 { 2089 u32 icr; 2090 u16 pci_cfg_cmd_word; 2091 int i; 2092 2093 /* Workaround for PCI problem when BIOS sets MMRBC incorrectly. */ 2094 atl2_read_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word); 2095 if ((pci_cfg_cmd_word & 2096 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) != 2097 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) { 2098 pci_cfg_cmd_word |= 2099 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER); 2100 atl2_write_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word); 2101 } 2102 2103 /* Clear Interrupt mask to stop board from generating 2104 * interrupts & Clear any pending interrupt events 2105 */ 2106 /* FIXME */ 2107 /* ATL2_WRITE_REG(hw, REG_IMR, 0); */ 2108 /* ATL2_WRITE_REG(hw, REG_ISR, 0xffffffff); */ 2109 2110 /* Issue Soft Reset to the MAC. This will reset the chip's 2111 * transmit, receive, DMA. It will not effect 2112 * the current PCI configuration. The global reset bit is self- 2113 * clearing, and should clear within a microsecond. 2114 */ 2115 ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_SOFT_RST); 2116 wmb(); 2117 msleep(1); /* delay about 1ms */ 2118 2119 /* Wait at least 10ms for All module to be Idle */ 2120 for (i = 0; i < 10; i++) { 2121 icr = ATL2_READ_REG(hw, REG_IDLE_STATUS); 2122 if (!icr) 2123 break; 2124 msleep(1); /* delay 1 ms */ 2125 cpu_relax(); 2126 } 2127 2128 if (icr) 2129 return icr; 2130 2131 return 0; 2132 } 2133 2134 #define CUSTOM_SPI_CS_SETUP 2 2135 #define CUSTOM_SPI_CLK_HI 2 2136 #define CUSTOM_SPI_CLK_LO 2 2137 #define CUSTOM_SPI_CS_HOLD 2 2138 #define CUSTOM_SPI_CS_HI 3 2139 2140 static struct atl2_spi_flash_dev flash_table[] = 2141 { 2142 /* MFR WRSR READ PROGRAM WREN WRDI RDSR RDID SECTOR_ERASE CHIP_ERASE */ 2143 {"Atmel", 0x0, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62 }, 2144 {"SST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60 }, 2145 {"ST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xAB, 0xD8, 0xC7 }, 2146 }; 2147 2148 static bool atl2_spi_read(struct atl2_hw *hw, u32 addr, u32 *buf) 2149 { 2150 int i; 2151 u32 value; 2152 2153 ATL2_WRITE_REG(hw, REG_SPI_DATA, 0); 2154 ATL2_WRITE_REG(hw, REG_SPI_ADDR, addr); 2155 2156 value = SPI_FLASH_CTRL_WAIT_READY | 2157 (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) << 2158 SPI_FLASH_CTRL_CS_SETUP_SHIFT | 2159 (CUSTOM_SPI_CLK_HI & SPI_FLASH_CTRL_CLK_HI_MASK) << 2160 SPI_FLASH_CTRL_CLK_HI_SHIFT | 2161 (CUSTOM_SPI_CLK_LO & SPI_FLASH_CTRL_CLK_LO_MASK) << 2162 SPI_FLASH_CTRL_CLK_LO_SHIFT | 2163 (CUSTOM_SPI_CS_HOLD & SPI_FLASH_CTRL_CS_HOLD_MASK) << 2164 SPI_FLASH_CTRL_CS_HOLD_SHIFT | 2165 (CUSTOM_SPI_CS_HI & SPI_FLASH_CTRL_CS_HI_MASK) << 2166 SPI_FLASH_CTRL_CS_HI_SHIFT | 2167 (0x1 & SPI_FLASH_CTRL_INS_MASK) << SPI_FLASH_CTRL_INS_SHIFT; 2168 2169 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value); 2170 2171 value |= SPI_FLASH_CTRL_START; 2172 2173 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value); 2174 2175 for (i = 0; i < 10; i++) { 2176 msleep(1); 2177 value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL); 2178 if (!(value & SPI_FLASH_CTRL_START)) 2179 break; 2180 } 2181 2182 if (value & SPI_FLASH_CTRL_START) 2183 return false; 2184 2185 *buf = ATL2_READ_REG(hw, REG_SPI_DATA); 2186 2187 return true; 2188 } 2189 2190 /* 2191 * get_permanent_address 2192 * return 0 if get valid mac address, 2193 */ 2194 static int get_permanent_address(struct atl2_hw *hw) 2195 { 2196 u32 Addr[2]; 2197 u32 i, Control; 2198 u16 Register; 2199 u8 EthAddr[ETH_ALEN]; 2200 bool KeyValid; 2201 2202 if (is_valid_ether_addr(hw->perm_mac_addr)) 2203 return 0; 2204 2205 Addr[0] = 0; 2206 Addr[1] = 0; 2207 2208 if (!atl2_check_eeprom_exist(hw)) { /* eeprom exists */ 2209 Register = 0; 2210 KeyValid = false; 2211 2212 /* Read out all EEPROM content */ 2213 i = 0; 2214 while (1) { 2215 if (atl2_read_eeprom(hw, i + 0x100, &Control)) { 2216 if (KeyValid) { 2217 if (Register == REG_MAC_STA_ADDR) 2218 Addr[0] = Control; 2219 else if (Register == 2220 (REG_MAC_STA_ADDR + 4)) 2221 Addr[1] = Control; 2222 KeyValid = false; 2223 } else if ((Control & 0xff) == 0x5A) { 2224 KeyValid = true; 2225 Register = (u16) (Control >> 16); 2226 } else { 2227 /* assume data end while encount an invalid KEYWORD */ 2228 break; 2229 } 2230 } else { 2231 break; /* read error */ 2232 } 2233 i += 4; 2234 } 2235 2236 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]); 2237 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]); 2238 2239 if (is_valid_ether_addr(EthAddr)) { 2240 memcpy(hw->perm_mac_addr, EthAddr, ETH_ALEN); 2241 return 0; 2242 } 2243 return 1; 2244 } 2245 2246 /* see if SPI flash exists? */ 2247 Addr[0] = 0; 2248 Addr[1] = 0; 2249 Register = 0; 2250 KeyValid = false; 2251 i = 0; 2252 while (1) { 2253 if (atl2_spi_read(hw, i + 0x1f000, &Control)) { 2254 if (KeyValid) { 2255 if (Register == REG_MAC_STA_ADDR) 2256 Addr[0] = Control; 2257 else if (Register == (REG_MAC_STA_ADDR + 4)) 2258 Addr[1] = Control; 2259 KeyValid = false; 2260 } else if ((Control & 0xff) == 0x5A) { 2261 KeyValid = true; 2262 Register = (u16) (Control >> 16); 2263 } else { 2264 break; /* data end */ 2265 } 2266 } else { 2267 break; /* read error */ 2268 } 2269 i += 4; 2270 } 2271 2272 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]); 2273 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *)&Addr[1]); 2274 if (is_valid_ether_addr(EthAddr)) { 2275 memcpy(hw->perm_mac_addr, EthAddr, ETH_ALEN); 2276 return 0; 2277 } 2278 /* maybe MAC-address is from BIOS */ 2279 Addr[0] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR); 2280 Addr[1] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR + 4); 2281 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]); 2282 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]); 2283 2284 if (is_valid_ether_addr(EthAddr)) { 2285 memcpy(hw->perm_mac_addr, EthAddr, ETH_ALEN); 2286 return 0; 2287 } 2288 2289 return 1; 2290 } 2291 2292 /* 2293 * Reads the adapter's MAC address from the EEPROM 2294 * 2295 * hw - Struct containing variables accessed by shared code 2296 */ 2297 static s32 atl2_read_mac_addr(struct atl2_hw *hw) 2298 { 2299 if (get_permanent_address(hw)) { 2300 /* for test */ 2301 /* FIXME: shouldn't we use eth_random_addr() here? */ 2302 hw->perm_mac_addr[0] = 0x00; 2303 hw->perm_mac_addr[1] = 0x13; 2304 hw->perm_mac_addr[2] = 0x74; 2305 hw->perm_mac_addr[3] = 0x00; 2306 hw->perm_mac_addr[4] = 0x5c; 2307 hw->perm_mac_addr[5] = 0x38; 2308 } 2309 2310 memcpy(hw->mac_addr, hw->perm_mac_addr, ETH_ALEN); 2311 2312 return 0; 2313 } 2314 2315 /* 2316 * Hashes an address to determine its location in the multicast table 2317 * 2318 * hw - Struct containing variables accessed by shared code 2319 * mc_addr - the multicast address to hash 2320 * 2321 * atl2_hash_mc_addr 2322 * purpose 2323 * set hash value for a multicast address 2324 * hash calcu processing : 2325 * 1. calcu 32bit CRC for multicast address 2326 * 2. reverse crc with MSB to LSB 2327 */ 2328 static u32 atl2_hash_mc_addr(struct atl2_hw *hw, u8 *mc_addr) 2329 { 2330 u32 crc32, value; 2331 int i; 2332 2333 value = 0; 2334 crc32 = ether_crc_le(6, mc_addr); 2335 2336 for (i = 0; i < 32; i++) 2337 value |= (((crc32 >> i) & 1) << (31 - i)); 2338 2339 return value; 2340 } 2341 2342 /* 2343 * Sets the bit in the multicast table corresponding to the hash value. 2344 * 2345 * hw - Struct containing variables accessed by shared code 2346 * hash_value - Multicast address hash value 2347 */ 2348 static void atl2_hash_set(struct atl2_hw *hw, u32 hash_value) 2349 { 2350 u32 hash_bit, hash_reg; 2351 u32 mta; 2352 2353 /* The HASH Table is a register array of 2 32-bit registers. 2354 * It is treated like an array of 64 bits. We want to set 2355 * bit BitArray[hash_value]. So we figure out what register 2356 * the bit is in, read it, OR in the new bit, then write 2357 * back the new value. The register is determined by the 2358 * upper 7 bits of the hash value and the bit within that 2359 * register are determined by the lower 5 bits of the value. 2360 */ 2361 hash_reg = (hash_value >> 31) & 0x1; 2362 hash_bit = (hash_value >> 26) & 0x1F; 2363 2364 mta = ATL2_READ_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg); 2365 2366 mta |= (1 << hash_bit); 2367 2368 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg, mta); 2369 } 2370 2371 /* 2372 * atl2_init_pcie - init PCIE module 2373 */ 2374 static void atl2_init_pcie(struct atl2_hw *hw) 2375 { 2376 u32 value; 2377 value = LTSSM_TEST_MODE_DEF; 2378 ATL2_WRITE_REG(hw, REG_LTSSM_TEST_MODE, value); 2379 2380 value = PCIE_DLL_TX_CTRL1_DEF; 2381 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, value); 2382 } 2383 2384 static void atl2_init_flash_opcode(struct atl2_hw *hw) 2385 { 2386 if (hw->flash_vendor >= ARRAY_SIZE(flash_table)) 2387 hw->flash_vendor = 0; /* ATMEL */ 2388 2389 /* Init OP table */ 2390 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_PROGRAM, 2391 flash_table[hw->flash_vendor].cmdPROGRAM); 2392 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_SC_ERASE, 2393 flash_table[hw->flash_vendor].cmdSECTOR_ERASE); 2394 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_CHIP_ERASE, 2395 flash_table[hw->flash_vendor].cmdCHIP_ERASE); 2396 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDID, 2397 flash_table[hw->flash_vendor].cmdRDID); 2398 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WREN, 2399 flash_table[hw->flash_vendor].cmdWREN); 2400 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDSR, 2401 flash_table[hw->flash_vendor].cmdRDSR); 2402 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WRSR, 2403 flash_table[hw->flash_vendor].cmdWRSR); 2404 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_READ, 2405 flash_table[hw->flash_vendor].cmdREAD); 2406 } 2407 2408 /******************************************************************** 2409 * Performs basic configuration of the adapter. 2410 * 2411 * hw - Struct containing variables accessed by shared code 2412 * Assumes that the controller has previously been reset and is in a 2413 * post-reset uninitialized state. Initializes multicast table, 2414 * and Calls routines to setup link 2415 * Leaves the transmit and receive units disabled and uninitialized. 2416 ********************************************************************/ 2417 static s32 atl2_init_hw(struct atl2_hw *hw) 2418 { 2419 u32 ret_val = 0; 2420 2421 atl2_init_pcie(hw); 2422 2423 /* Zero out the Multicast HASH table */ 2424 /* clear the old settings from the multicast hash table */ 2425 ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0); 2426 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0); 2427 2428 atl2_init_flash_opcode(hw); 2429 2430 ret_val = atl2_phy_init(hw); 2431 2432 return ret_val; 2433 } 2434 2435 /* 2436 * Detects the current speed and duplex settings of the hardware. 2437 * 2438 * hw - Struct containing variables accessed by shared code 2439 * speed - Speed of the connection 2440 * duplex - Duplex setting of the connection 2441 */ 2442 static s32 atl2_get_speed_and_duplex(struct atl2_hw *hw, u16 *speed, 2443 u16 *duplex) 2444 { 2445 s32 ret_val; 2446 u16 phy_data; 2447 2448 /* Read PHY Specific Status Register (17) */ 2449 ret_val = atl2_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data); 2450 if (ret_val) 2451 return ret_val; 2452 2453 if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED)) 2454 return ATLX_ERR_PHY_RES; 2455 2456 switch (phy_data & MII_ATLX_PSSR_SPEED) { 2457 case MII_ATLX_PSSR_100MBS: 2458 *speed = SPEED_100; 2459 break; 2460 case MII_ATLX_PSSR_10MBS: 2461 *speed = SPEED_10; 2462 break; 2463 default: 2464 return ATLX_ERR_PHY_SPEED; 2465 } 2466 2467 if (phy_data & MII_ATLX_PSSR_DPLX) 2468 *duplex = FULL_DUPLEX; 2469 else 2470 *duplex = HALF_DUPLEX; 2471 2472 return 0; 2473 } 2474 2475 /* 2476 * Reads the value from a PHY register 2477 * hw - Struct containing variables accessed by shared code 2478 * reg_addr - address of the PHY register to read 2479 */ 2480 static s32 atl2_read_phy_reg(struct atl2_hw *hw, u16 reg_addr, u16 *phy_data) 2481 { 2482 u32 val; 2483 int i; 2484 2485 val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT | 2486 MDIO_START | 2487 MDIO_SUP_PREAMBLE | 2488 MDIO_RW | 2489 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT; 2490 ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val); 2491 2492 wmb(); 2493 2494 for (i = 0; i < MDIO_WAIT_TIMES; i++) { 2495 udelay(2); 2496 val = ATL2_READ_REG(hw, REG_MDIO_CTRL); 2497 if (!(val & (MDIO_START | MDIO_BUSY))) 2498 break; 2499 wmb(); 2500 } 2501 if (!(val & (MDIO_START | MDIO_BUSY))) { 2502 *phy_data = (u16)val; 2503 return 0; 2504 } 2505 2506 return ATLX_ERR_PHY; 2507 } 2508 2509 /* 2510 * Writes a value to a PHY register 2511 * hw - Struct containing variables accessed by shared code 2512 * reg_addr - address of the PHY register to write 2513 * data - data to write to the PHY 2514 */ 2515 static s32 atl2_write_phy_reg(struct atl2_hw *hw, u32 reg_addr, u16 phy_data) 2516 { 2517 int i; 2518 u32 val; 2519 2520 val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT | 2521 (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT | 2522 MDIO_SUP_PREAMBLE | 2523 MDIO_START | 2524 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT; 2525 ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val); 2526 2527 wmb(); 2528 2529 for (i = 0; i < MDIO_WAIT_TIMES; i++) { 2530 udelay(2); 2531 val = ATL2_READ_REG(hw, REG_MDIO_CTRL); 2532 if (!(val & (MDIO_START | MDIO_BUSY))) 2533 break; 2534 2535 wmb(); 2536 } 2537 2538 if (!(val & (MDIO_START | MDIO_BUSY))) 2539 return 0; 2540 2541 return ATLX_ERR_PHY; 2542 } 2543 2544 /* 2545 * Configures PHY autoneg and flow control advertisement settings 2546 * 2547 * hw - Struct containing variables accessed by shared code 2548 */ 2549 static s32 atl2_phy_setup_autoneg_adv(struct atl2_hw *hw) 2550 { 2551 s32 ret_val; 2552 s16 mii_autoneg_adv_reg; 2553 2554 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 2555 mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK; 2556 2557 /* Need to parse autoneg_advertised and set up 2558 * the appropriate PHY registers. First we will parse for 2559 * autoneg_advertised software override. Since we can advertise 2560 * a plethora of combinations, we need to check each bit 2561 * individually. 2562 */ 2563 2564 /* First we clear all the 10/100 mb speed bits in the Auto-Neg 2565 * Advertisement Register (Address 4) and the 1000 mb speed bits in 2566 * the 1000Base-T Control Register (Address 9). */ 2567 mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK; 2568 2569 /* Need to parse MediaType and setup the 2570 * appropriate PHY registers. */ 2571 switch (hw->MediaType) { 2572 case MEDIA_TYPE_AUTO_SENSOR: 2573 mii_autoneg_adv_reg |= 2574 (MII_AR_10T_HD_CAPS | 2575 MII_AR_10T_FD_CAPS | 2576 MII_AR_100TX_HD_CAPS| 2577 MII_AR_100TX_FD_CAPS); 2578 hw->autoneg_advertised = 2579 ADVERTISE_10_HALF | 2580 ADVERTISE_10_FULL | 2581 ADVERTISE_100_HALF| 2582 ADVERTISE_100_FULL; 2583 break; 2584 case MEDIA_TYPE_100M_FULL: 2585 mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS; 2586 hw->autoneg_advertised = ADVERTISE_100_FULL; 2587 break; 2588 case MEDIA_TYPE_100M_HALF: 2589 mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS; 2590 hw->autoneg_advertised = ADVERTISE_100_HALF; 2591 break; 2592 case MEDIA_TYPE_10M_FULL: 2593 mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS; 2594 hw->autoneg_advertised = ADVERTISE_10_FULL; 2595 break; 2596 default: 2597 mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS; 2598 hw->autoneg_advertised = ADVERTISE_10_HALF; 2599 break; 2600 } 2601 2602 /* flow control fixed to enable all */ 2603 mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE); 2604 2605 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg; 2606 2607 ret_val = atl2_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg); 2608 2609 if (ret_val) 2610 return ret_val; 2611 2612 return 0; 2613 } 2614 2615 /* 2616 * Resets the PHY and make all config validate 2617 * 2618 * hw - Struct containing variables accessed by shared code 2619 * 2620 * Sets bit 15 and 12 of the MII Control regiser (for F001 bug) 2621 */ 2622 static s32 atl2_phy_commit(struct atl2_hw *hw) 2623 { 2624 s32 ret_val; 2625 u16 phy_data; 2626 2627 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG; 2628 ret_val = atl2_write_phy_reg(hw, MII_BMCR, phy_data); 2629 if (ret_val) { 2630 u32 val; 2631 int i; 2632 /* pcie serdes link may be down ! */ 2633 for (i = 0; i < 25; i++) { 2634 msleep(1); 2635 val = ATL2_READ_REG(hw, REG_MDIO_CTRL); 2636 if (!(val & (MDIO_START | MDIO_BUSY))) 2637 break; 2638 } 2639 2640 if (0 != (val & (MDIO_START | MDIO_BUSY))) { 2641 printk(KERN_ERR "atl2: PCIe link down for at least 25ms !\n"); 2642 return ret_val; 2643 } 2644 } 2645 return 0; 2646 } 2647 2648 static s32 atl2_phy_init(struct atl2_hw *hw) 2649 { 2650 s32 ret_val; 2651 u16 phy_val; 2652 2653 if (hw->phy_configured) 2654 return 0; 2655 2656 /* Enable PHY */ 2657 ATL2_WRITE_REGW(hw, REG_PHY_ENABLE, 1); 2658 ATL2_WRITE_FLUSH(hw); 2659 msleep(1); 2660 2661 /* check if the PHY is in powersaving mode */ 2662 atl2_write_phy_reg(hw, MII_DBG_ADDR, 0); 2663 atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val); 2664 2665 /* 024E / 124E 0r 0274 / 1274 ? */ 2666 if (phy_val & 0x1000) { 2667 phy_val &= ~0x1000; 2668 atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val); 2669 } 2670 2671 msleep(1); 2672 2673 /*Enable PHY LinkChange Interrupt */ 2674 ret_val = atl2_write_phy_reg(hw, 18, 0xC00); 2675 if (ret_val) 2676 return ret_val; 2677 2678 /* setup AutoNeg parameters */ 2679 ret_val = atl2_phy_setup_autoneg_adv(hw); 2680 if (ret_val) 2681 return ret_val; 2682 2683 /* SW.Reset & En-Auto-Neg to restart Auto-Neg */ 2684 ret_val = atl2_phy_commit(hw); 2685 if (ret_val) 2686 return ret_val; 2687 2688 hw->phy_configured = true; 2689 2690 return ret_val; 2691 } 2692 2693 static void atl2_set_mac_addr(struct atl2_hw *hw) 2694 { 2695 u32 value; 2696 /* 00-0B-6A-F6-00-DC 2697 * 0: 6AF600DC 1: 000B 2698 * low dword */ 2699 value = (((u32)hw->mac_addr[2]) << 24) | 2700 (((u32)hw->mac_addr[3]) << 16) | 2701 (((u32)hw->mac_addr[4]) << 8) | 2702 (((u32)hw->mac_addr[5])); 2703 ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value); 2704 /* hight dword */ 2705 value = (((u32)hw->mac_addr[0]) << 8) | 2706 (((u32)hw->mac_addr[1])); 2707 ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value); 2708 } 2709 2710 /* 2711 * check_eeprom_exist 2712 * return 0 if eeprom exist 2713 */ 2714 static int atl2_check_eeprom_exist(struct atl2_hw *hw) 2715 { 2716 u32 value; 2717 2718 value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL); 2719 if (value & SPI_FLASH_CTRL_EN_VPD) { 2720 value &= ~SPI_FLASH_CTRL_EN_VPD; 2721 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value); 2722 } 2723 value = ATL2_READ_REGW(hw, REG_PCIE_CAP_LIST); 2724 return ((value & 0xFF00) == 0x6C00) ? 0 : 1; 2725 } 2726 2727 /* FIXME: This doesn't look right. -- CHS */ 2728 static bool atl2_write_eeprom(struct atl2_hw *hw, u32 offset, u32 value) 2729 { 2730 return true; 2731 } 2732 2733 static bool atl2_read_eeprom(struct atl2_hw *hw, u32 Offset, u32 *pValue) 2734 { 2735 int i; 2736 u32 Control; 2737 2738 if (Offset & 0x3) 2739 return false; /* address do not align */ 2740 2741 ATL2_WRITE_REG(hw, REG_VPD_DATA, 0); 2742 Control = (Offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT; 2743 ATL2_WRITE_REG(hw, REG_VPD_CAP, Control); 2744 2745 for (i = 0; i < 10; i++) { 2746 msleep(2); 2747 Control = ATL2_READ_REG(hw, REG_VPD_CAP); 2748 if (Control & VPD_CAP_VPD_FLAG) 2749 break; 2750 } 2751 2752 if (Control & VPD_CAP_VPD_FLAG) { 2753 *pValue = ATL2_READ_REG(hw, REG_VPD_DATA); 2754 return true; 2755 } 2756 return false; /* timeout */ 2757 } 2758 2759 static void atl2_force_ps(struct atl2_hw *hw) 2760 { 2761 u16 phy_val; 2762 2763 atl2_write_phy_reg(hw, MII_DBG_ADDR, 0); 2764 atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val); 2765 atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val | 0x1000); 2766 2767 atl2_write_phy_reg(hw, MII_DBG_ADDR, 2); 2768 atl2_write_phy_reg(hw, MII_DBG_DATA, 0x3000); 2769 atl2_write_phy_reg(hw, MII_DBG_ADDR, 3); 2770 atl2_write_phy_reg(hw, MII_DBG_DATA, 0); 2771 } 2772 2773 /* This is the only thing that needs to be changed to adjust the 2774 * maximum number of ports that the driver can manage. 2775 */ 2776 #define ATL2_MAX_NIC 4 2777 2778 #define OPTION_UNSET -1 2779 #define OPTION_DISABLED 0 2780 #define OPTION_ENABLED 1 2781 2782 /* All parameters are treated the same, as an integer array of values. 2783 * This macro just reduces the need to repeat the same declaration code 2784 * over and over (plus this helps to avoid typo bugs). 2785 */ 2786 #define ATL2_PARAM_INIT {[0 ... ATL2_MAX_NIC] = OPTION_UNSET} 2787 #ifndef module_param_array 2788 /* Module Parameters are always initialized to -1, so that the driver 2789 * can tell the difference between no user specified value or the 2790 * user asking for the default value. 2791 * The true default values are loaded in when atl2_check_options is called. 2792 * 2793 * This is a GCC extension to ANSI C. 2794 * See the item "Labeled Elements in Initializers" in the section 2795 * "Extensions to the C Language Family" of the GCC documentation. 2796 */ 2797 2798 #define ATL2_PARAM(X, desc) \ 2799 static const int X[ATL2_MAX_NIC + 1] = ATL2_PARAM_INIT; \ 2800 MODULE_PARM(X, "1-" __MODULE_STRING(ATL2_MAX_NIC) "i"); \ 2801 MODULE_PARM_DESC(X, desc); 2802 #else 2803 #define ATL2_PARAM(X, desc) \ 2804 static int X[ATL2_MAX_NIC+1] = ATL2_PARAM_INIT; \ 2805 static unsigned int num_##X; \ 2806 module_param_array_named(X, X, int, &num_##X, 0); \ 2807 MODULE_PARM_DESC(X, desc); 2808 #endif 2809 2810 /* 2811 * Transmit Memory Size 2812 * Valid Range: 64-2048 2813 * Default Value: 128 2814 */ 2815 #define ATL2_MIN_TX_MEMSIZE 4 /* 4KB */ 2816 #define ATL2_MAX_TX_MEMSIZE 64 /* 64KB */ 2817 #define ATL2_DEFAULT_TX_MEMSIZE 8 /* 8KB */ 2818 ATL2_PARAM(TxMemSize, "Bytes of Transmit Memory"); 2819 2820 /* 2821 * Receive Memory Block Count 2822 * Valid Range: 16-512 2823 * Default Value: 128 2824 */ 2825 #define ATL2_MIN_RXD_COUNT 16 2826 #define ATL2_MAX_RXD_COUNT 512 2827 #define ATL2_DEFAULT_RXD_COUNT 64 2828 ATL2_PARAM(RxMemBlock, "Number of receive memory block"); 2829 2830 /* 2831 * User Specified MediaType Override 2832 * 2833 * Valid Range: 0-5 2834 * - 0 - auto-negotiate at all supported speeds 2835 * - 1 - only link at 1000Mbps Full Duplex 2836 * - 2 - only link at 100Mbps Full Duplex 2837 * - 3 - only link at 100Mbps Half Duplex 2838 * - 4 - only link at 10Mbps Full Duplex 2839 * - 5 - only link at 10Mbps Half Duplex 2840 * Default Value: 0 2841 */ 2842 ATL2_PARAM(MediaType, "MediaType Select"); 2843 2844 /* 2845 * Interrupt Moderate Timer in units of 2048 ns (~2 us) 2846 * Valid Range: 10-65535 2847 * Default Value: 45000(90ms) 2848 */ 2849 #define INT_MOD_DEFAULT_CNT 100 /* 200us */ 2850 #define INT_MOD_MAX_CNT 65000 2851 #define INT_MOD_MIN_CNT 50 2852 ATL2_PARAM(IntModTimer, "Interrupt Moderator Timer"); 2853 2854 /* 2855 * FlashVendor 2856 * Valid Range: 0-2 2857 * 0 - Atmel 2858 * 1 - SST 2859 * 2 - ST 2860 */ 2861 ATL2_PARAM(FlashVendor, "SPI Flash Vendor"); 2862 2863 #define AUTONEG_ADV_DEFAULT 0x2F 2864 #define AUTONEG_ADV_MASK 0x2F 2865 #define FLOW_CONTROL_DEFAULT FLOW_CONTROL_FULL 2866 2867 #define FLASH_VENDOR_DEFAULT 0 2868 #define FLASH_VENDOR_MIN 0 2869 #define FLASH_VENDOR_MAX 2 2870 2871 struct atl2_option { 2872 enum { enable_option, range_option, list_option } type; 2873 char *name; 2874 char *err; 2875 int def; 2876 union { 2877 struct { /* range_option info */ 2878 int min; 2879 int max; 2880 } r; 2881 struct { /* list_option info */ 2882 int nr; 2883 struct atl2_opt_list { int i; char *str; } *p; 2884 } l; 2885 } arg; 2886 }; 2887 2888 static int atl2_validate_option(int *value, struct atl2_option *opt) 2889 { 2890 int i; 2891 struct atl2_opt_list *ent; 2892 2893 if (*value == OPTION_UNSET) { 2894 *value = opt->def; 2895 return 0; 2896 } 2897 2898 switch (opt->type) { 2899 case enable_option: 2900 switch (*value) { 2901 case OPTION_ENABLED: 2902 printk(KERN_INFO "%s Enabled\n", opt->name); 2903 return 0; 2904 case OPTION_DISABLED: 2905 printk(KERN_INFO "%s Disabled\n", opt->name); 2906 return 0; 2907 } 2908 break; 2909 case range_option: 2910 if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) { 2911 printk(KERN_INFO "%s set to %i\n", opt->name, *value); 2912 return 0; 2913 } 2914 break; 2915 case list_option: 2916 for (i = 0; i < opt->arg.l.nr; i++) { 2917 ent = &opt->arg.l.p[i]; 2918 if (*value == ent->i) { 2919 if (ent->str[0] != '\0') 2920 printk(KERN_INFO "%s\n", ent->str); 2921 return 0; 2922 } 2923 } 2924 break; 2925 default: 2926 BUG(); 2927 } 2928 2929 printk(KERN_INFO "Invalid %s specified (%i) %s\n", 2930 opt->name, *value, opt->err); 2931 *value = opt->def; 2932 return -1; 2933 } 2934 2935 /** 2936 * atl2_check_options - Range Checking for Command Line Parameters 2937 * @adapter: board private structure 2938 * 2939 * This routine checks all command line parameters for valid user 2940 * input. If an invalid value is given, or if no user specified 2941 * value exists, a default value is used. The final value is stored 2942 * in a variable in the adapter structure. 2943 */ 2944 static void atl2_check_options(struct atl2_adapter *adapter) 2945 { 2946 int val; 2947 struct atl2_option opt; 2948 int bd = adapter->bd_number; 2949 if (bd >= ATL2_MAX_NIC) { 2950 printk(KERN_NOTICE "Warning: no configuration for board #%i\n", 2951 bd); 2952 printk(KERN_NOTICE "Using defaults for all values\n"); 2953 #ifndef module_param_array 2954 bd = ATL2_MAX_NIC; 2955 #endif 2956 } 2957 2958 /* Bytes of Transmit Memory */ 2959 opt.type = range_option; 2960 opt.name = "Bytes of Transmit Memory"; 2961 opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_TX_MEMSIZE); 2962 opt.def = ATL2_DEFAULT_TX_MEMSIZE; 2963 opt.arg.r.min = ATL2_MIN_TX_MEMSIZE; 2964 opt.arg.r.max = ATL2_MAX_TX_MEMSIZE; 2965 #ifdef module_param_array 2966 if (num_TxMemSize > bd) { 2967 #endif 2968 val = TxMemSize[bd]; 2969 atl2_validate_option(&val, &opt); 2970 adapter->txd_ring_size = ((u32) val) * 1024; 2971 #ifdef module_param_array 2972 } else 2973 adapter->txd_ring_size = ((u32)opt.def) * 1024; 2974 #endif 2975 /* txs ring size: */ 2976 adapter->txs_ring_size = adapter->txd_ring_size / 128; 2977 if (adapter->txs_ring_size > 160) 2978 adapter->txs_ring_size = 160; 2979 2980 /* Receive Memory Block Count */ 2981 opt.type = range_option; 2982 opt.name = "Number of receive memory block"; 2983 opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_RXD_COUNT); 2984 opt.def = ATL2_DEFAULT_RXD_COUNT; 2985 opt.arg.r.min = ATL2_MIN_RXD_COUNT; 2986 opt.arg.r.max = ATL2_MAX_RXD_COUNT; 2987 #ifdef module_param_array 2988 if (num_RxMemBlock > bd) { 2989 #endif 2990 val = RxMemBlock[bd]; 2991 atl2_validate_option(&val, &opt); 2992 adapter->rxd_ring_size = (u32)val; 2993 /* FIXME */ 2994 /* ((u16)val)&~1; */ /* even number */ 2995 #ifdef module_param_array 2996 } else 2997 adapter->rxd_ring_size = (u32)opt.def; 2998 #endif 2999 /* init RXD Flow control value */ 3000 adapter->hw.fc_rxd_hi = (adapter->rxd_ring_size / 8) * 7; 3001 adapter->hw.fc_rxd_lo = (ATL2_MIN_RXD_COUNT / 8) > 3002 (adapter->rxd_ring_size / 12) ? (ATL2_MIN_RXD_COUNT / 8) : 3003 (adapter->rxd_ring_size / 12); 3004 3005 /* Interrupt Moderate Timer */ 3006 opt.type = range_option; 3007 opt.name = "Interrupt Moderate Timer"; 3008 opt.err = "using default of " __MODULE_STRING(INT_MOD_DEFAULT_CNT); 3009 opt.def = INT_MOD_DEFAULT_CNT; 3010 opt.arg.r.min = INT_MOD_MIN_CNT; 3011 opt.arg.r.max = INT_MOD_MAX_CNT; 3012 #ifdef module_param_array 3013 if (num_IntModTimer > bd) { 3014 #endif 3015 val = IntModTimer[bd]; 3016 atl2_validate_option(&val, &opt); 3017 adapter->imt = (u16) val; 3018 #ifdef module_param_array 3019 } else 3020 adapter->imt = (u16)(opt.def); 3021 #endif 3022 /* Flash Vendor */ 3023 opt.type = range_option; 3024 opt.name = "SPI Flash Vendor"; 3025 opt.err = "using default of " __MODULE_STRING(FLASH_VENDOR_DEFAULT); 3026 opt.def = FLASH_VENDOR_DEFAULT; 3027 opt.arg.r.min = FLASH_VENDOR_MIN; 3028 opt.arg.r.max = FLASH_VENDOR_MAX; 3029 #ifdef module_param_array 3030 if (num_FlashVendor > bd) { 3031 #endif 3032 val = FlashVendor[bd]; 3033 atl2_validate_option(&val, &opt); 3034 adapter->hw.flash_vendor = (u8) val; 3035 #ifdef module_param_array 3036 } else 3037 adapter->hw.flash_vendor = (u8)(opt.def); 3038 #endif 3039 /* MediaType */ 3040 opt.type = range_option; 3041 opt.name = "Speed/Duplex Selection"; 3042 opt.err = "using default of " __MODULE_STRING(MEDIA_TYPE_AUTO_SENSOR); 3043 opt.def = MEDIA_TYPE_AUTO_SENSOR; 3044 opt.arg.r.min = MEDIA_TYPE_AUTO_SENSOR; 3045 opt.arg.r.max = MEDIA_TYPE_10M_HALF; 3046 #ifdef module_param_array 3047 if (num_MediaType > bd) { 3048 #endif 3049 val = MediaType[bd]; 3050 atl2_validate_option(&val, &opt); 3051 adapter->hw.MediaType = (u16) val; 3052 #ifdef module_param_array 3053 } else 3054 adapter->hw.MediaType = (u16)(opt.def); 3055 #endif 3056 } 3057