1 /* 2 * Copyright(c) 2007 Atheros Corporation. All rights reserved. 3 * 4 * Derived from Intel e1000 driver 5 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the Free 9 * Software Foundation; either version 2 of the License, or (at your option) 10 * any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program; if not, write to the Free Software Foundation, Inc., 59 19 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 20 */ 21 #include <linux/pci.h> 22 #include <linux/delay.h> 23 #include <linux/mii.h> 24 #include <linux/crc32.h> 25 26 #include "atl1e.h" 27 28 /* 29 * check_eeprom_exist 30 * return 0 if eeprom exist 31 */ 32 int atl1e_check_eeprom_exist(struct atl1e_hw *hw) 33 { 34 u32 value; 35 36 value = AT_READ_REG(hw, REG_SPI_FLASH_CTRL); 37 if (value & SPI_FLASH_CTRL_EN_VPD) { 38 value &= ~SPI_FLASH_CTRL_EN_VPD; 39 AT_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value); 40 } 41 value = AT_READ_REGW(hw, REG_PCIE_CAP_LIST); 42 return ((value & 0xFF00) == 0x6C00) ? 0 : 1; 43 } 44 45 void atl1e_hw_set_mac_addr(struct atl1e_hw *hw) 46 { 47 u32 value; 48 /* 49 * 00-0B-6A-F6-00-DC 50 * 0: 6AF600DC 1: 000B 51 * low dword 52 */ 53 value = (((u32)hw->mac_addr[2]) << 24) | 54 (((u32)hw->mac_addr[3]) << 16) | 55 (((u32)hw->mac_addr[4]) << 8) | 56 (((u32)hw->mac_addr[5])) ; 57 AT_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value); 58 /* hight dword */ 59 value = (((u32)hw->mac_addr[0]) << 8) | 60 (((u32)hw->mac_addr[1])) ; 61 AT_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value); 62 } 63 64 /* 65 * atl1e_get_permanent_address 66 * return 0 if get valid mac address, 67 */ 68 static int atl1e_get_permanent_address(struct atl1e_hw *hw) 69 { 70 u32 addr[2]; 71 u32 i; 72 u32 twsi_ctrl_data; 73 u8 eth_addr[ETH_ALEN]; 74 75 if (is_valid_ether_addr(hw->perm_mac_addr)) 76 return 0; 77 78 /* init */ 79 addr[0] = addr[1] = 0; 80 81 if (!atl1e_check_eeprom_exist(hw)) { 82 /* eeprom exist */ 83 twsi_ctrl_data = AT_READ_REG(hw, REG_TWSI_CTRL); 84 twsi_ctrl_data |= TWSI_CTRL_SW_LDSTART; 85 AT_WRITE_REG(hw, REG_TWSI_CTRL, twsi_ctrl_data); 86 for (i = 0; i < AT_TWSI_EEPROM_TIMEOUT; i++) { 87 msleep(10); 88 twsi_ctrl_data = AT_READ_REG(hw, REG_TWSI_CTRL); 89 if ((twsi_ctrl_data & TWSI_CTRL_SW_LDSTART) == 0) 90 break; 91 } 92 if (i >= AT_TWSI_EEPROM_TIMEOUT) 93 return AT_ERR_TIMEOUT; 94 } 95 96 /* maybe MAC-address is from BIOS */ 97 addr[0] = AT_READ_REG(hw, REG_MAC_STA_ADDR); 98 addr[1] = AT_READ_REG(hw, REG_MAC_STA_ADDR + 4); 99 *(u32 *) ð_addr[2] = swab32(addr[0]); 100 *(u16 *) ð_addr[0] = swab16(*(u16 *)&addr[1]); 101 102 if (is_valid_ether_addr(eth_addr)) { 103 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN); 104 return 0; 105 } 106 107 return AT_ERR_EEPROM; 108 } 109 110 bool atl1e_write_eeprom(struct atl1e_hw *hw, u32 offset, u32 value) 111 { 112 return true; 113 } 114 115 bool atl1e_read_eeprom(struct atl1e_hw *hw, u32 offset, u32 *p_value) 116 { 117 int i; 118 u32 control; 119 120 if (offset & 3) 121 return false; /* address do not align */ 122 123 AT_WRITE_REG(hw, REG_VPD_DATA, 0); 124 control = (offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT; 125 AT_WRITE_REG(hw, REG_VPD_CAP, control); 126 127 for (i = 0; i < 10; i++) { 128 msleep(2); 129 control = AT_READ_REG(hw, REG_VPD_CAP); 130 if (control & VPD_CAP_VPD_FLAG) 131 break; 132 } 133 if (control & VPD_CAP_VPD_FLAG) { 134 *p_value = AT_READ_REG(hw, REG_VPD_DATA); 135 return true; 136 } 137 return false; /* timeout */ 138 } 139 140 void atl1e_force_ps(struct atl1e_hw *hw) 141 { 142 AT_WRITE_REGW(hw, REG_GPHY_CTRL, 143 GPHY_CTRL_PW_WOL_DIS | GPHY_CTRL_EXT_RESET); 144 } 145 146 /* 147 * Reads the adapter's MAC address from the EEPROM 148 * 149 * hw - Struct containing variables accessed by shared code 150 */ 151 int atl1e_read_mac_addr(struct atl1e_hw *hw) 152 { 153 int err = 0; 154 155 err = atl1e_get_permanent_address(hw); 156 if (err) 157 return AT_ERR_EEPROM; 158 memcpy(hw->mac_addr, hw->perm_mac_addr, sizeof(hw->perm_mac_addr)); 159 return 0; 160 } 161 162 /* 163 * atl1e_hash_mc_addr 164 * purpose 165 * set hash value for a multicast address 166 */ 167 u32 atl1e_hash_mc_addr(struct atl1e_hw *hw, u8 *mc_addr) 168 { 169 u32 crc32; 170 u32 value = 0; 171 int i; 172 173 crc32 = ether_crc_le(6, mc_addr); 174 for (i = 0; i < 32; i++) 175 value |= (((crc32 >> i) & 1) << (31 - i)); 176 177 return value; 178 } 179 180 /* 181 * Sets the bit in the multicast table corresponding to the hash value. 182 * hw - Struct containing variables accessed by shared code 183 * hash_value - Multicast address hash value 184 */ 185 void atl1e_hash_set(struct atl1e_hw *hw, u32 hash_value) 186 { 187 u32 hash_bit, hash_reg; 188 u32 mta; 189 190 /* 191 * The HASH Table is a register array of 2 32-bit registers. 192 * It is treated like an array of 64 bits. We want to set 193 * bit BitArray[hash_value]. So we figure out what register 194 * the bit is in, read it, OR in the new bit, then write 195 * back the new value. The register is determined by the 196 * upper 7 bits of the hash value and the bit within that 197 * register are determined by the lower 5 bits of the value. 198 */ 199 hash_reg = (hash_value >> 31) & 0x1; 200 hash_bit = (hash_value >> 26) & 0x1F; 201 202 mta = AT_READ_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg); 203 204 mta |= (1 << hash_bit); 205 206 AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg, mta); 207 } 208 /* 209 * Reads the value from a PHY register 210 * hw - Struct containing variables accessed by shared code 211 * reg_addr - address of the PHY register to read 212 */ 213 int atl1e_read_phy_reg(struct atl1e_hw *hw, u16 reg_addr, u16 *phy_data) 214 { 215 u32 val; 216 int i; 217 218 val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT | 219 MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW | 220 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT; 221 222 AT_WRITE_REG(hw, REG_MDIO_CTRL, val); 223 224 wmb(); 225 226 for (i = 0; i < MDIO_WAIT_TIMES; i++) { 227 udelay(2); 228 val = AT_READ_REG(hw, REG_MDIO_CTRL); 229 if (!(val & (MDIO_START | MDIO_BUSY))) 230 break; 231 wmb(); 232 } 233 if (!(val & (MDIO_START | MDIO_BUSY))) { 234 *phy_data = (u16)val; 235 return 0; 236 } 237 238 return AT_ERR_PHY; 239 } 240 241 /* 242 * Writes a value to a PHY register 243 * hw - Struct containing variables accessed by shared code 244 * reg_addr - address of the PHY register to write 245 * data - data to write to the PHY 246 */ 247 int atl1e_write_phy_reg(struct atl1e_hw *hw, u32 reg_addr, u16 phy_data) 248 { 249 int i; 250 u32 val; 251 252 val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT | 253 (reg_addr&MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT | 254 MDIO_SUP_PREAMBLE | 255 MDIO_START | 256 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT; 257 258 AT_WRITE_REG(hw, REG_MDIO_CTRL, val); 259 wmb(); 260 261 for (i = 0; i < MDIO_WAIT_TIMES; i++) { 262 udelay(2); 263 val = AT_READ_REG(hw, REG_MDIO_CTRL); 264 if (!(val & (MDIO_START | MDIO_BUSY))) 265 break; 266 wmb(); 267 } 268 269 if (!(val & (MDIO_START | MDIO_BUSY))) 270 return 0; 271 272 return AT_ERR_PHY; 273 } 274 275 /* 276 * atl1e_init_pcie - init PCIE module 277 */ 278 static void atl1e_init_pcie(struct atl1e_hw *hw) 279 { 280 u32 value; 281 /* comment 2lines below to save more power when sususpend 282 value = LTSSM_TEST_MODE_DEF; 283 AT_WRITE_REG(hw, REG_LTSSM_TEST_MODE, value); 284 */ 285 286 /* pcie flow control mode change */ 287 value = AT_READ_REG(hw, 0x1008); 288 value |= 0x8000; 289 AT_WRITE_REG(hw, 0x1008, value); 290 } 291 /* 292 * Configures PHY autoneg and flow control advertisement settings 293 * 294 * hw - Struct containing variables accessed by shared code 295 */ 296 static int atl1e_phy_setup_autoneg_adv(struct atl1e_hw *hw) 297 { 298 s32 ret_val; 299 u16 mii_autoneg_adv_reg; 300 u16 mii_1000t_ctrl_reg; 301 302 if (0 != hw->mii_autoneg_adv_reg) 303 return 0; 304 /* Read the MII Auto-Neg Advertisement Register (Address 4/9). */ 305 mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK; 306 mii_1000t_ctrl_reg = MII_AT001_CR_1000T_DEFAULT_CAP_MASK; 307 308 /* 309 * Need to parse autoneg_advertised and set up 310 * the appropriate PHY registers. First we will parse for 311 * autoneg_advertised software override. Since we can advertise 312 * a plethora of combinations, we need to check each bit 313 * individually. 314 */ 315 316 /* 317 * First we clear all the 10/100 mb speed bits in the Auto-Neg 318 * Advertisement Register (Address 4) and the 1000 mb speed bits in 319 * the 1000Base-T control Register (Address 9). 320 */ 321 mii_autoneg_adv_reg &= ~ADVERTISE_ALL; 322 mii_1000t_ctrl_reg &= ~MII_AT001_CR_1000T_SPEED_MASK; 323 324 /* 325 * Need to parse MediaType and setup the 326 * appropriate PHY registers. 327 */ 328 switch (hw->media_type) { 329 case MEDIA_TYPE_AUTO_SENSOR: 330 mii_autoneg_adv_reg |= ADVERTISE_ALL; 331 hw->autoneg_advertised = ADVERTISE_ALL; 332 if (hw->nic_type == athr_l1e) { 333 mii_1000t_ctrl_reg |= ADVERTISE_1000FULL; 334 hw->autoneg_advertised |= ADVERTISE_1000_FULL; 335 } 336 break; 337 338 case MEDIA_TYPE_100M_FULL: 339 mii_autoneg_adv_reg |= ADVERTISE_100FULL; 340 hw->autoneg_advertised = ADVERTISE_100_FULL; 341 break; 342 343 case MEDIA_TYPE_100M_HALF: 344 mii_autoneg_adv_reg |= ADVERTISE_100_HALF; 345 hw->autoneg_advertised = ADVERTISE_100_HALF; 346 break; 347 348 case MEDIA_TYPE_10M_FULL: 349 mii_autoneg_adv_reg |= ADVERTISE_10_FULL; 350 hw->autoneg_advertised = ADVERTISE_10_FULL; 351 break; 352 353 default: 354 mii_autoneg_adv_reg |= ADVERTISE_10_HALF; 355 hw->autoneg_advertised = ADVERTISE_10_HALF; 356 break; 357 } 358 359 /* flow control fixed to enable all */ 360 mii_autoneg_adv_reg |= (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP); 361 362 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg; 363 hw->mii_1000t_ctrl_reg = mii_1000t_ctrl_reg; 364 365 ret_val = atl1e_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg); 366 if (ret_val) 367 return ret_val; 368 369 if (hw->nic_type == athr_l1e || hw->nic_type == athr_l2e_revA) { 370 ret_val = atl1e_write_phy_reg(hw, MII_CTRL1000, 371 mii_1000t_ctrl_reg); 372 if (ret_val) 373 return ret_val; 374 } 375 376 return 0; 377 } 378 379 380 /* 381 * Resets the PHY and make all config validate 382 * 383 * hw - Struct containing variables accessed by shared code 384 * 385 * Sets bit 15 and 12 of the MII control regiser (for F001 bug) 386 */ 387 int atl1e_phy_commit(struct atl1e_hw *hw) 388 { 389 struct atl1e_adapter *adapter = hw->adapter; 390 int ret_val; 391 u16 phy_data; 392 393 phy_data = BMCR_RESET | BMCR_ANENABLE | BMCR_ANRESTART; 394 395 ret_val = atl1e_write_phy_reg(hw, MII_BMCR, phy_data); 396 if (ret_val) { 397 u32 val; 398 int i; 399 /************************************** 400 * pcie serdes link may be down ! 401 **************************************/ 402 for (i = 0; i < 25; i++) { 403 msleep(1); 404 val = AT_READ_REG(hw, REG_MDIO_CTRL); 405 if (!(val & (MDIO_START | MDIO_BUSY))) 406 break; 407 } 408 409 if (0 != (val & (MDIO_START | MDIO_BUSY))) { 410 netdev_err(adapter->netdev, 411 "pcie linkdown at least for 25ms\n"); 412 return ret_val; 413 } 414 415 netdev_err(adapter->netdev, "pcie linkup after %d ms\n", i); 416 } 417 return 0; 418 } 419 420 int atl1e_phy_init(struct atl1e_hw *hw) 421 { 422 struct atl1e_adapter *adapter = hw->adapter; 423 s32 ret_val; 424 u16 phy_val; 425 426 if (hw->phy_configured) { 427 if (hw->re_autoneg) { 428 hw->re_autoneg = false; 429 return atl1e_restart_autoneg(hw); 430 } 431 return 0; 432 } 433 434 /* RESET GPHY Core */ 435 AT_WRITE_REGW(hw, REG_GPHY_CTRL, GPHY_CTRL_DEFAULT); 436 msleep(2); 437 AT_WRITE_REGW(hw, REG_GPHY_CTRL, GPHY_CTRL_DEFAULT | 438 GPHY_CTRL_EXT_RESET); 439 msleep(2); 440 441 /* patches */ 442 /* p1. eable hibernation mode */ 443 ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0xB); 444 if (ret_val) 445 return ret_val; 446 ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0xBC00); 447 if (ret_val) 448 return ret_val; 449 /* p2. set Class A/B for all modes */ 450 ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0); 451 if (ret_val) 452 return ret_val; 453 phy_val = 0x02ef; 454 /* remove Class AB */ 455 /* phy_val = hw->emi_ca ? 0x02ef : 0x02df; */ 456 ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, phy_val); 457 if (ret_val) 458 return ret_val; 459 /* p3. 10B ??? */ 460 ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0x12); 461 if (ret_val) 462 return ret_val; 463 ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0x4C04); 464 if (ret_val) 465 return ret_val; 466 /* p4. 1000T power */ 467 ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0x4); 468 if (ret_val) 469 return ret_val; 470 ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0x8BBB); 471 if (ret_val) 472 return ret_val; 473 474 ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0x5); 475 if (ret_val) 476 return ret_val; 477 ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0x2C46); 478 if (ret_val) 479 return ret_val; 480 481 msleep(1); 482 483 /*Enable PHY LinkChange Interrupt */ 484 ret_val = atl1e_write_phy_reg(hw, MII_INT_CTRL, 0xC00); 485 if (ret_val) { 486 netdev_err(adapter->netdev, 487 "Error enable PHY linkChange Interrupt\n"); 488 return ret_val; 489 } 490 /* setup AutoNeg parameters */ 491 ret_val = atl1e_phy_setup_autoneg_adv(hw); 492 if (ret_val) { 493 netdev_err(adapter->netdev, 494 "Error Setting up Auto-Negotiation\n"); 495 return ret_val; 496 } 497 /* SW.Reset & En-Auto-Neg to restart Auto-Neg*/ 498 netdev_dbg(adapter->netdev, "Restarting Auto-Negotiation\n"); 499 ret_val = atl1e_phy_commit(hw); 500 if (ret_val) { 501 netdev_err(adapter->netdev, "Error resetting the phy\n"); 502 return ret_val; 503 } 504 505 hw->phy_configured = true; 506 507 return 0; 508 } 509 510 /* 511 * Reset the transmit and receive units; mask and clear all interrupts. 512 * hw - Struct containing variables accessed by shared code 513 * return : 0 or idle status (if error) 514 */ 515 int atl1e_reset_hw(struct atl1e_hw *hw) 516 { 517 struct atl1e_adapter *adapter = hw->adapter; 518 struct pci_dev *pdev = adapter->pdev; 519 520 u32 idle_status_data = 0; 521 u16 pci_cfg_cmd_word = 0; 522 int timeout = 0; 523 524 /* Workaround for PCI problem when BIOS sets MMRBC incorrectly. */ 525 pci_read_config_word(pdev, PCI_REG_COMMAND, &pci_cfg_cmd_word); 526 if ((pci_cfg_cmd_word & (CMD_IO_SPACE | 527 CMD_MEMORY_SPACE | CMD_BUS_MASTER)) 528 != (CMD_IO_SPACE | CMD_MEMORY_SPACE | CMD_BUS_MASTER)) { 529 pci_cfg_cmd_word |= (CMD_IO_SPACE | 530 CMD_MEMORY_SPACE | CMD_BUS_MASTER); 531 pci_write_config_word(pdev, PCI_REG_COMMAND, pci_cfg_cmd_word); 532 } 533 534 /* 535 * Issue Soft Reset to the MAC. This will reset the chip's 536 * transmit, receive, DMA. It will not effect 537 * the current PCI configuration. The global reset bit is self- 538 * clearing, and should clear within a microsecond. 539 */ 540 AT_WRITE_REG(hw, REG_MASTER_CTRL, 541 MASTER_CTRL_LED_MODE | MASTER_CTRL_SOFT_RST); 542 wmb(); 543 msleep(1); 544 545 /* Wait at least 10ms for All module to be Idle */ 546 for (timeout = 0; timeout < AT_HW_MAX_IDLE_DELAY; timeout++) { 547 idle_status_data = AT_READ_REG(hw, REG_IDLE_STATUS); 548 if (idle_status_data == 0) 549 break; 550 msleep(1); 551 cpu_relax(); 552 } 553 554 if (timeout >= AT_HW_MAX_IDLE_DELAY) { 555 netdev_err(adapter->netdev, 556 "MAC state machine can't be idle since disabled for 10ms second\n"); 557 return AT_ERR_TIMEOUT; 558 } 559 560 return 0; 561 } 562 563 564 /* 565 * Performs basic configuration of the adapter. 566 * 567 * hw - Struct containing variables accessed by shared code 568 * Assumes that the controller has previously been reset and is in a 569 * post-reset uninitialized state. Initializes multicast table, 570 * and Calls routines to setup link 571 * Leaves the transmit and receive units disabled and uninitialized. 572 */ 573 int atl1e_init_hw(struct atl1e_hw *hw) 574 { 575 s32 ret_val = 0; 576 577 atl1e_init_pcie(hw); 578 579 /* Zero out the Multicast HASH table */ 580 /* clear the old settings from the multicast hash table */ 581 AT_WRITE_REG(hw, REG_RX_HASH_TABLE, 0); 582 AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0); 583 584 ret_val = atl1e_phy_init(hw); 585 586 return ret_val; 587 } 588 589 /* 590 * Detects the current speed and duplex settings of the hardware. 591 * 592 * hw - Struct containing variables accessed by shared code 593 * speed - Speed of the connection 594 * duplex - Duplex setting of the connection 595 */ 596 int atl1e_get_speed_and_duplex(struct atl1e_hw *hw, u16 *speed, u16 *duplex) 597 { 598 int err; 599 u16 phy_data; 600 601 /* Read PHY Specific Status Register (17) */ 602 err = atl1e_read_phy_reg(hw, MII_AT001_PSSR, &phy_data); 603 if (err) 604 return err; 605 606 if (!(phy_data & MII_AT001_PSSR_SPD_DPLX_RESOLVED)) 607 return AT_ERR_PHY_RES; 608 609 switch (phy_data & MII_AT001_PSSR_SPEED) { 610 case MII_AT001_PSSR_1000MBS: 611 *speed = SPEED_1000; 612 break; 613 case MII_AT001_PSSR_100MBS: 614 *speed = SPEED_100; 615 break; 616 case MII_AT001_PSSR_10MBS: 617 *speed = SPEED_10; 618 break; 619 default: 620 return AT_ERR_PHY_SPEED; 621 } 622 623 if (phy_data & MII_AT001_PSSR_DPLX) 624 *duplex = FULL_DUPLEX; 625 else 626 *duplex = HALF_DUPLEX; 627 628 return 0; 629 } 630 631 int atl1e_restart_autoneg(struct atl1e_hw *hw) 632 { 633 int err = 0; 634 635 err = atl1e_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg); 636 if (err) 637 return err; 638 639 if (hw->nic_type == athr_l1e || hw->nic_type == athr_l2e_revA) { 640 err = atl1e_write_phy_reg(hw, MII_CTRL1000, 641 hw->mii_1000t_ctrl_reg); 642 if (err) 643 return err; 644 } 645 646 err = atl1e_write_phy_reg(hw, MII_BMCR, 647 BMCR_RESET | BMCR_ANENABLE | BMCR_ANRESTART); 648 return err; 649 } 650 651