1 // SPDX-License-Identifier: GPL-2.0 2 /* Atheros AR71xx built-in ethernet mac driver 3 * 4 * Copyright (C) 2019 Oleksij Rempel <o.rempel@pengutronix.de> 5 * 6 * List of authors contributed to this driver before mainlining: 7 * Alexander Couzens <lynxis@fe80.eu> 8 * Christian Lamparter <chunkeey@gmail.com> 9 * Chuanhong Guo <gch981213@gmail.com> 10 * Daniel F. Dickinson <cshored@thecshore.com> 11 * David Bauer <mail@david-bauer.net> 12 * Felix Fietkau <nbd@nbd.name> 13 * Gabor Juhos <juhosg@freemail.hu> 14 * Hauke Mehrtens <hauke@hauke-m.de> 15 * Johann Neuhauser <johann@it-neuhauser.de> 16 * John Crispin <john@phrozen.org> 17 * Jo-Philipp Wich <jo@mein.io> 18 * Koen Vandeputte <koen.vandeputte@ncentric.com> 19 * Lucian Cristian <lucian.cristian@gmail.com> 20 * Matt Merhar <mattmerhar@protonmail.com> 21 * Milan Krstic <milan.krstic@gmail.com> 22 * Petr Štetiar <ynezz@true.cz> 23 * Rosen Penev <rosenp@gmail.com> 24 * Stephen Walker <stephendwalker+github@gmail.com> 25 * Vittorio Gambaletta <openwrt@vittgam.net> 26 * Weijie Gao <hackpascal@gmail.com> 27 * Imre Kaloz <kaloz@openwrt.org> 28 */ 29 30 #include <linux/if_vlan.h> 31 #include <linux/mfd/syscon.h> 32 #include <linux/of.h> 33 #include <linux/of_mdio.h> 34 #include <linux/of_net.h> 35 #include <linux/platform_device.h> 36 #include <linux/phylink.h> 37 #include <linux/regmap.h> 38 #include <linux/reset.h> 39 #include <linux/clk.h> 40 #include <linux/io.h> 41 #include <net/selftests.h> 42 43 /* For our NAPI weight bigger does *NOT* mean better - it means more 44 * D-cache misses and lots more wasted cycles than we'll ever 45 * possibly gain from saving instructions. 46 */ 47 #define AG71XX_NAPI_WEIGHT 32 48 #define AG71XX_OOM_REFILL (1 + HZ / 10) 49 50 #define AG71XX_INT_ERR (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE) 51 #define AG71XX_INT_TX (AG71XX_INT_TX_PS) 52 #define AG71XX_INT_RX (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF) 53 54 #define AG71XX_INT_POLL (AG71XX_INT_RX | AG71XX_INT_TX) 55 #define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL) 56 57 #define AG71XX_TX_MTU_LEN 1540 58 59 #define AG71XX_TX_RING_SPLIT 512 60 #define AG71XX_TX_RING_DS_PER_PKT DIV_ROUND_UP(AG71XX_TX_MTU_LEN, \ 61 AG71XX_TX_RING_SPLIT) 62 #define AG71XX_TX_RING_SIZE_DEFAULT 128 63 #define AG71XX_RX_RING_SIZE_DEFAULT 256 64 65 #define AG71XX_MDIO_RETRY 1000 66 #define AG71XX_MDIO_DELAY 5 67 #define AG71XX_MDIO_MAX_CLK 5000000 68 69 /* Register offsets */ 70 #define AG71XX_REG_MAC_CFG1 0x0000 71 #define MAC_CFG1_TXE BIT(0) /* Tx Enable */ 72 #define MAC_CFG1_STX BIT(1) /* Synchronize Tx Enable */ 73 #define MAC_CFG1_RXE BIT(2) /* Rx Enable */ 74 #define MAC_CFG1_SRX BIT(3) /* Synchronize Rx Enable */ 75 #define MAC_CFG1_TFC BIT(4) /* Tx Flow Control Enable */ 76 #define MAC_CFG1_RFC BIT(5) /* Rx Flow Control Enable */ 77 #define MAC_CFG1_SR BIT(31) /* Soft Reset */ 78 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \ 79 MAC_CFG1_SRX | MAC_CFG1_STX) 80 81 #define AG71XX_REG_MAC_CFG2 0x0004 82 #define MAC_CFG2_FDX BIT(0) 83 #define MAC_CFG2_PAD_CRC_EN BIT(2) 84 #define MAC_CFG2_LEN_CHECK BIT(4) 85 #define MAC_CFG2_IF_1000 BIT(9) 86 #define MAC_CFG2_IF_10_100 BIT(8) 87 88 #define AG71XX_REG_MAC_MFL 0x0010 89 90 #define AG71XX_REG_MII_CFG 0x0020 91 #define MII_CFG_CLK_DIV_4 0 92 #define MII_CFG_CLK_DIV_6 2 93 #define MII_CFG_CLK_DIV_8 3 94 #define MII_CFG_CLK_DIV_10 4 95 #define MII_CFG_CLK_DIV_14 5 96 #define MII_CFG_CLK_DIV_20 6 97 #define MII_CFG_CLK_DIV_28 7 98 #define MII_CFG_CLK_DIV_34 8 99 #define MII_CFG_CLK_DIV_42 9 100 #define MII_CFG_CLK_DIV_50 10 101 #define MII_CFG_CLK_DIV_58 11 102 #define MII_CFG_CLK_DIV_66 12 103 #define MII_CFG_CLK_DIV_74 13 104 #define MII_CFG_CLK_DIV_82 14 105 #define MII_CFG_CLK_DIV_98 15 106 #define MII_CFG_RESET BIT(31) 107 108 #define AG71XX_REG_MII_CMD 0x0024 109 #define MII_CMD_READ BIT(0) 110 111 #define AG71XX_REG_MII_ADDR 0x0028 112 #define MII_ADDR_SHIFT 8 113 114 #define AG71XX_REG_MII_CTRL 0x002c 115 #define AG71XX_REG_MII_STATUS 0x0030 116 #define AG71XX_REG_MII_IND 0x0034 117 #define MII_IND_BUSY BIT(0) 118 #define MII_IND_INVALID BIT(2) 119 120 #define AG71XX_REG_MAC_IFCTL 0x0038 121 #define MAC_IFCTL_SPEED BIT(16) 122 123 #define AG71XX_REG_MAC_ADDR1 0x0040 124 #define AG71XX_REG_MAC_ADDR2 0x0044 125 #define AG71XX_REG_FIFO_CFG0 0x0048 126 #define FIFO_CFG0_WTM BIT(0) /* Watermark Module */ 127 #define FIFO_CFG0_RXS BIT(1) /* Rx System Module */ 128 #define FIFO_CFG0_RXF BIT(2) /* Rx Fabric Module */ 129 #define FIFO_CFG0_TXS BIT(3) /* Tx System Module */ 130 #define FIFO_CFG0_TXF BIT(4) /* Tx Fabric Module */ 131 #define FIFO_CFG0_ALL (FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \ 132 | FIFO_CFG0_TXS | FIFO_CFG0_TXF) 133 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT) 134 135 #define FIFO_CFG0_ENABLE_SHIFT 8 136 137 #define AG71XX_REG_FIFO_CFG1 0x004c 138 #define AG71XX_REG_FIFO_CFG2 0x0050 139 #define AG71XX_REG_FIFO_CFG3 0x0054 140 #define AG71XX_REG_FIFO_CFG4 0x0058 141 #define FIFO_CFG4_DE BIT(0) /* Drop Event */ 142 #define FIFO_CFG4_DV BIT(1) /* RX_DV Event */ 143 #define FIFO_CFG4_FC BIT(2) /* False Carrier */ 144 #define FIFO_CFG4_CE BIT(3) /* Code Error */ 145 #define FIFO_CFG4_CR BIT(4) /* CRC error */ 146 #define FIFO_CFG4_LM BIT(5) /* Length Mismatch */ 147 #define FIFO_CFG4_LO BIT(6) /* Length out of range */ 148 #define FIFO_CFG4_OK BIT(7) /* Packet is OK */ 149 #define FIFO_CFG4_MC BIT(8) /* Multicast Packet */ 150 #define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */ 151 #define FIFO_CFG4_DR BIT(10) /* Dribble */ 152 #define FIFO_CFG4_LE BIT(11) /* Long Event */ 153 #define FIFO_CFG4_CF BIT(12) /* Control Frame */ 154 #define FIFO_CFG4_PF BIT(13) /* Pause Frame */ 155 #define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */ 156 #define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */ 157 #define FIFO_CFG4_FT BIT(16) /* Frame Truncated */ 158 #define FIFO_CFG4_UC BIT(17) /* Unicast Packet */ 159 #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \ 160 FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \ 161 FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \ 162 FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \ 163 FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \ 164 FIFO_CFG4_VT) 165 166 #define AG71XX_REG_FIFO_CFG5 0x005c 167 #define FIFO_CFG5_DE BIT(0) /* Drop Event */ 168 #define FIFO_CFG5_DV BIT(1) /* RX_DV Event */ 169 #define FIFO_CFG5_FC BIT(2) /* False Carrier */ 170 #define FIFO_CFG5_CE BIT(3) /* Code Error */ 171 #define FIFO_CFG5_LM BIT(4) /* Length Mismatch */ 172 #define FIFO_CFG5_LO BIT(5) /* Length Out of Range */ 173 #define FIFO_CFG5_OK BIT(6) /* Packet is OK */ 174 #define FIFO_CFG5_MC BIT(7) /* Multicast Packet */ 175 #define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */ 176 #define FIFO_CFG5_DR BIT(9) /* Dribble */ 177 #define FIFO_CFG5_CF BIT(10) /* Control Frame */ 178 #define FIFO_CFG5_PF BIT(11) /* Pause Frame */ 179 #define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */ 180 #define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */ 181 #define FIFO_CFG5_LE BIT(14) /* Long Event */ 182 #define FIFO_CFG5_FT BIT(15) /* Frame Truncated */ 183 #define FIFO_CFG5_16 BIT(16) /* unknown */ 184 #define FIFO_CFG5_17 BIT(17) /* unknown */ 185 #define FIFO_CFG5_SF BIT(18) /* Short Frame */ 186 #define FIFO_CFG5_BM BIT(19) /* Byte Mode */ 187 #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \ 188 FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \ 189 FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \ 190 FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \ 191 FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \ 192 FIFO_CFG5_17 | FIFO_CFG5_SF) 193 194 #define AG71XX_REG_TX_CTRL 0x0180 195 #define TX_CTRL_TXE BIT(0) /* Tx Enable */ 196 197 #define AG71XX_REG_TX_DESC 0x0184 198 #define AG71XX_REG_TX_STATUS 0x0188 199 #define TX_STATUS_PS BIT(0) /* Packet Sent */ 200 #define TX_STATUS_UR BIT(1) /* Tx Underrun */ 201 #define TX_STATUS_BE BIT(3) /* Bus Error */ 202 203 #define AG71XX_REG_RX_CTRL 0x018c 204 #define RX_CTRL_RXE BIT(0) /* Rx Enable */ 205 206 #define AG71XX_DMA_RETRY 10 207 #define AG71XX_DMA_DELAY 1 208 209 #define AG71XX_REG_RX_DESC 0x0190 210 #define AG71XX_REG_RX_STATUS 0x0194 211 #define RX_STATUS_PR BIT(0) /* Packet Received */ 212 #define RX_STATUS_OF BIT(2) /* Rx Overflow */ 213 #define RX_STATUS_BE BIT(3) /* Bus Error */ 214 215 #define AG71XX_REG_INT_ENABLE 0x0198 216 #define AG71XX_REG_INT_STATUS 0x019c 217 #define AG71XX_INT_TX_PS BIT(0) 218 #define AG71XX_INT_TX_UR BIT(1) 219 #define AG71XX_INT_TX_BE BIT(3) 220 #define AG71XX_INT_RX_PR BIT(4) 221 #define AG71XX_INT_RX_OF BIT(6) 222 #define AG71XX_INT_RX_BE BIT(7) 223 224 #define AG71XX_REG_FIFO_DEPTH 0x01a8 225 #define AG71XX_REG_RX_SM 0x01b0 226 #define AG71XX_REG_TX_SM 0x01b4 227 228 #define AG71XX_DEFAULT_MSG_ENABLE \ 229 (NETIF_MSG_DRV \ 230 | NETIF_MSG_PROBE \ 231 | NETIF_MSG_LINK \ 232 | NETIF_MSG_TIMER \ 233 | NETIF_MSG_IFDOWN \ 234 | NETIF_MSG_IFUP \ 235 | NETIF_MSG_RX_ERR \ 236 | NETIF_MSG_TX_ERR) 237 238 struct ag71xx_statistic { 239 unsigned short offset; 240 u32 mask; 241 const char name[ETH_GSTRING_LEN]; 242 }; 243 244 static const struct ag71xx_statistic ag71xx_statistics[] = { 245 { 0x0080, GENMASK(17, 0), "Tx/Rx 64 Byte", }, 246 { 0x0084, GENMASK(17, 0), "Tx/Rx 65-127 Byte", }, 247 { 0x0088, GENMASK(17, 0), "Tx/Rx 128-255 Byte", }, 248 { 0x008C, GENMASK(17, 0), "Tx/Rx 256-511 Byte", }, 249 { 0x0090, GENMASK(17, 0), "Tx/Rx 512-1023 Byte", }, 250 { 0x0094, GENMASK(17, 0), "Tx/Rx 1024-1518 Byte", }, 251 { 0x0098, GENMASK(17, 0), "Tx/Rx 1519-1522 Byte VLAN", }, 252 { 0x009C, GENMASK(23, 0), "Rx Byte", }, 253 { 0x00A0, GENMASK(17, 0), "Rx Packet", }, 254 { 0x00A4, GENMASK(11, 0), "Rx FCS Error", }, 255 { 0x00A8, GENMASK(17, 0), "Rx Multicast Packet", }, 256 { 0x00AC, GENMASK(21, 0), "Rx Broadcast Packet", }, 257 { 0x00B0, GENMASK(17, 0), "Rx Control Frame Packet", }, 258 { 0x00B4, GENMASK(11, 0), "Rx Pause Frame Packet", }, 259 { 0x00B8, GENMASK(11, 0), "Rx Unknown OPCode Packet", }, 260 { 0x00BC, GENMASK(11, 0), "Rx Alignment Error", }, 261 { 0x00C0, GENMASK(15, 0), "Rx Frame Length Error", }, 262 { 0x00C4, GENMASK(11, 0), "Rx Code Error", }, 263 { 0x00C8, GENMASK(11, 0), "Rx Carrier Sense Error", }, 264 { 0x00CC, GENMASK(11, 0), "Rx Undersize Packet", }, 265 { 0x00D0, GENMASK(11, 0), "Rx Oversize Packet", }, 266 { 0x00D4, GENMASK(11, 0), "Rx Fragments", }, 267 { 0x00D8, GENMASK(11, 0), "Rx Jabber", }, 268 { 0x00DC, GENMASK(11, 0), "Rx Dropped Packet", }, 269 { 0x00E0, GENMASK(23, 0), "Tx Byte", }, 270 { 0x00E4, GENMASK(17, 0), "Tx Packet", }, 271 { 0x00E8, GENMASK(17, 0), "Tx Multicast Packet", }, 272 { 0x00EC, GENMASK(17, 0), "Tx Broadcast Packet", }, 273 { 0x00F0, GENMASK(11, 0), "Tx Pause Control Frame", }, 274 { 0x00F4, GENMASK(11, 0), "Tx Deferral Packet", }, 275 { 0x00F8, GENMASK(11, 0), "Tx Excessive Deferral Packet", }, 276 { 0x00FC, GENMASK(11, 0), "Tx Single Collision Packet", }, 277 { 0x0100, GENMASK(11, 0), "Tx Multiple Collision", }, 278 { 0x0104, GENMASK(11, 0), "Tx Late Collision Packet", }, 279 { 0x0108, GENMASK(11, 0), "Tx Excessive Collision Packet", }, 280 { 0x010C, GENMASK(12, 0), "Tx Total Collision", }, 281 { 0x0110, GENMASK(11, 0), "Tx Pause Frames Honored", }, 282 { 0x0114, GENMASK(11, 0), "Tx Drop Frame", }, 283 { 0x0118, GENMASK(11, 0), "Tx Jabber Frame", }, 284 { 0x011C, GENMASK(11, 0), "Tx FCS Error", }, 285 { 0x0120, GENMASK(11, 0), "Tx Control Frame", }, 286 { 0x0124, GENMASK(11, 0), "Tx Oversize Frame", }, 287 { 0x0128, GENMASK(11, 0), "Tx Undersize Frame", }, 288 { 0x012C, GENMASK(11, 0), "Tx Fragment", }, 289 }; 290 291 #define DESC_EMPTY BIT(31) 292 #define DESC_MORE BIT(24) 293 #define DESC_PKTLEN_M 0xfff 294 struct ag71xx_desc { 295 u32 data; 296 u32 ctrl; 297 u32 next; 298 u32 pad; 299 } __aligned(4); 300 301 #define AG71XX_DESC_SIZE roundup(sizeof(struct ag71xx_desc), \ 302 L1_CACHE_BYTES) 303 304 struct ag71xx_buf { 305 union { 306 struct { 307 struct sk_buff *skb; 308 unsigned int len; 309 } tx; 310 struct { 311 dma_addr_t dma_addr; 312 void *rx_buf; 313 } rx; 314 }; 315 }; 316 317 struct ag71xx_ring { 318 /* "Hot" fields in the data path. */ 319 unsigned int curr; 320 unsigned int dirty; 321 322 /* "Cold" fields - not used in the data path. */ 323 struct ag71xx_buf *buf; 324 u16 order; 325 u16 desc_split; 326 dma_addr_t descs_dma; 327 u8 *descs_cpu; 328 }; 329 330 enum ag71xx_type { 331 AR7100, 332 AR7240, 333 AR9130, 334 AR9330, 335 AR9340, 336 QCA9530, 337 QCA9550, 338 }; 339 340 struct ag71xx_dcfg { 341 u32 max_frame_len; 342 const u32 *fifodata; 343 u16 desc_pktlen_mask; 344 bool tx_hang_workaround; 345 enum ag71xx_type type; 346 }; 347 348 struct ag71xx { 349 /* Critical data related to the per-packet data path are clustered 350 * early in this structure to help improve the D-cache footprint. 351 */ 352 struct ag71xx_ring rx_ring ____cacheline_aligned; 353 struct ag71xx_ring tx_ring ____cacheline_aligned; 354 355 u16 rx_buf_size; 356 u8 rx_buf_offset; 357 358 struct net_device *ndev; 359 struct platform_device *pdev; 360 struct napi_struct napi; 361 u32 msg_enable; 362 const struct ag71xx_dcfg *dcfg; 363 364 /* From this point onwards we're not looking at per-packet fields. */ 365 void __iomem *mac_base; 366 367 struct ag71xx_desc *stop_desc; 368 dma_addr_t stop_desc_dma; 369 370 phy_interface_t phy_if_mode; 371 struct phylink *phylink; 372 struct phylink_config phylink_config; 373 374 struct delayed_work restart_work; 375 struct timer_list oom_timer; 376 377 struct reset_control *mac_reset; 378 379 u32 fifodata[3]; 380 int mac_idx; 381 382 struct reset_control *mdio_reset; 383 struct mii_bus *mii_bus; 384 struct clk *clk_mdio; 385 struct clk *clk_eth; 386 }; 387 388 static int ag71xx_desc_empty(struct ag71xx_desc *desc) 389 { 390 return (desc->ctrl & DESC_EMPTY) != 0; 391 } 392 393 static struct ag71xx_desc *ag71xx_ring_desc(struct ag71xx_ring *ring, int idx) 394 { 395 return (struct ag71xx_desc *)&ring->descs_cpu[idx * AG71XX_DESC_SIZE]; 396 } 397 398 static int ag71xx_ring_size_order(int size) 399 { 400 return fls(size - 1); 401 } 402 403 static bool ag71xx_is(struct ag71xx *ag, enum ag71xx_type type) 404 { 405 return ag->dcfg->type == type; 406 } 407 408 static void ag71xx_wr(struct ag71xx *ag, unsigned int reg, u32 value) 409 { 410 iowrite32(value, ag->mac_base + reg); 411 /* flush write */ 412 (void)ioread32(ag->mac_base + reg); 413 } 414 415 static u32 ag71xx_rr(struct ag71xx *ag, unsigned int reg) 416 { 417 return ioread32(ag->mac_base + reg); 418 } 419 420 static void ag71xx_sb(struct ag71xx *ag, unsigned int reg, u32 mask) 421 { 422 void __iomem *r; 423 424 r = ag->mac_base + reg; 425 iowrite32(ioread32(r) | mask, r); 426 /* flush write */ 427 (void)ioread32(r); 428 } 429 430 static void ag71xx_cb(struct ag71xx *ag, unsigned int reg, u32 mask) 431 { 432 void __iomem *r; 433 434 r = ag->mac_base + reg; 435 iowrite32(ioread32(r) & ~mask, r); 436 /* flush write */ 437 (void)ioread32(r); 438 } 439 440 static void ag71xx_int_enable(struct ag71xx *ag, u32 ints) 441 { 442 ag71xx_sb(ag, AG71XX_REG_INT_ENABLE, ints); 443 } 444 445 static void ag71xx_int_disable(struct ag71xx *ag, u32 ints) 446 { 447 ag71xx_cb(ag, AG71XX_REG_INT_ENABLE, ints); 448 } 449 450 static int ag71xx_do_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd) 451 { 452 struct ag71xx *ag = netdev_priv(ndev); 453 454 return phylink_mii_ioctl(ag->phylink, ifr, cmd); 455 } 456 457 static void ag71xx_get_drvinfo(struct net_device *ndev, 458 struct ethtool_drvinfo *info) 459 { 460 struct ag71xx *ag = netdev_priv(ndev); 461 462 strscpy(info->driver, "ag71xx", sizeof(info->driver)); 463 strscpy(info->bus_info, of_node_full_name(ag->pdev->dev.of_node), 464 sizeof(info->bus_info)); 465 } 466 467 static int ag71xx_get_link_ksettings(struct net_device *ndev, 468 struct ethtool_link_ksettings *kset) 469 { 470 struct ag71xx *ag = netdev_priv(ndev); 471 472 return phylink_ethtool_ksettings_get(ag->phylink, kset); 473 } 474 475 static int ag71xx_set_link_ksettings(struct net_device *ndev, 476 const struct ethtool_link_ksettings *kset) 477 { 478 struct ag71xx *ag = netdev_priv(ndev); 479 480 return phylink_ethtool_ksettings_set(ag->phylink, kset); 481 } 482 483 static int ag71xx_ethtool_nway_reset(struct net_device *ndev) 484 { 485 struct ag71xx *ag = netdev_priv(ndev); 486 487 return phylink_ethtool_nway_reset(ag->phylink); 488 } 489 490 static void ag71xx_ethtool_get_pauseparam(struct net_device *ndev, 491 struct ethtool_pauseparam *pause) 492 { 493 struct ag71xx *ag = netdev_priv(ndev); 494 495 phylink_ethtool_get_pauseparam(ag->phylink, pause); 496 } 497 498 static int ag71xx_ethtool_set_pauseparam(struct net_device *ndev, 499 struct ethtool_pauseparam *pause) 500 { 501 struct ag71xx *ag = netdev_priv(ndev); 502 503 return phylink_ethtool_set_pauseparam(ag->phylink, pause); 504 } 505 506 static void ag71xx_ethtool_get_strings(struct net_device *netdev, u32 sset, 507 u8 *data) 508 { 509 int i; 510 511 switch (sset) { 512 case ETH_SS_STATS: 513 for (i = 0; i < ARRAY_SIZE(ag71xx_statistics); i++) 514 memcpy(data + i * ETH_GSTRING_LEN, 515 ag71xx_statistics[i].name, ETH_GSTRING_LEN); 516 break; 517 case ETH_SS_TEST: 518 net_selftest_get_strings(data); 519 break; 520 } 521 } 522 523 static void ag71xx_ethtool_get_stats(struct net_device *ndev, 524 struct ethtool_stats *stats, u64 *data) 525 { 526 struct ag71xx *ag = netdev_priv(ndev); 527 int i; 528 529 for (i = 0; i < ARRAY_SIZE(ag71xx_statistics); i++) 530 *data++ = ag71xx_rr(ag, ag71xx_statistics[i].offset) 531 & ag71xx_statistics[i].mask; 532 } 533 534 static int ag71xx_ethtool_get_sset_count(struct net_device *ndev, int sset) 535 { 536 switch (sset) { 537 case ETH_SS_STATS: 538 return ARRAY_SIZE(ag71xx_statistics); 539 case ETH_SS_TEST: 540 return net_selftest_get_count(); 541 default: 542 return -EOPNOTSUPP; 543 } 544 } 545 546 static const struct ethtool_ops ag71xx_ethtool_ops = { 547 .get_drvinfo = ag71xx_get_drvinfo, 548 .get_link = ethtool_op_get_link, 549 .get_ts_info = ethtool_op_get_ts_info, 550 .get_link_ksettings = ag71xx_get_link_ksettings, 551 .set_link_ksettings = ag71xx_set_link_ksettings, 552 .nway_reset = ag71xx_ethtool_nway_reset, 553 .get_pauseparam = ag71xx_ethtool_get_pauseparam, 554 .set_pauseparam = ag71xx_ethtool_set_pauseparam, 555 .get_strings = ag71xx_ethtool_get_strings, 556 .get_ethtool_stats = ag71xx_ethtool_get_stats, 557 .get_sset_count = ag71xx_ethtool_get_sset_count, 558 .self_test = net_selftest, 559 }; 560 561 static int ag71xx_mdio_wait_busy(struct ag71xx *ag) 562 { 563 struct net_device *ndev = ag->ndev; 564 int i; 565 566 for (i = 0; i < AG71XX_MDIO_RETRY; i++) { 567 u32 busy; 568 569 udelay(AG71XX_MDIO_DELAY); 570 571 busy = ag71xx_rr(ag, AG71XX_REG_MII_IND); 572 if (!busy) 573 return 0; 574 575 udelay(AG71XX_MDIO_DELAY); 576 } 577 578 netif_err(ag, link, ndev, "MDIO operation timed out\n"); 579 580 return -ETIMEDOUT; 581 } 582 583 static int ag71xx_mdio_mii_read(struct mii_bus *bus, int addr, int reg) 584 { 585 struct ag71xx *ag = bus->priv; 586 int err, val; 587 588 err = ag71xx_mdio_wait_busy(ag); 589 if (err) 590 return err; 591 592 ag71xx_wr(ag, AG71XX_REG_MII_ADDR, 593 ((addr & 0x1f) << MII_ADDR_SHIFT) | (reg & 0xff)); 594 /* enable read mode */ 595 ag71xx_wr(ag, AG71XX_REG_MII_CMD, MII_CMD_READ); 596 597 err = ag71xx_mdio_wait_busy(ag); 598 if (err) 599 return err; 600 601 val = ag71xx_rr(ag, AG71XX_REG_MII_STATUS); 602 /* disable read mode */ 603 ag71xx_wr(ag, AG71XX_REG_MII_CMD, 0); 604 605 netif_dbg(ag, link, ag->ndev, "mii_read: addr=%04x, reg=%04x, value=%04x\n", 606 addr, reg, val); 607 608 return val; 609 } 610 611 static int ag71xx_mdio_mii_write(struct mii_bus *bus, int addr, int reg, 612 u16 val) 613 { 614 struct ag71xx *ag = bus->priv; 615 616 netif_dbg(ag, link, ag->ndev, "mii_write: addr=%04x, reg=%04x, value=%04x\n", 617 addr, reg, val); 618 619 ag71xx_wr(ag, AG71XX_REG_MII_ADDR, 620 ((addr & 0x1f) << MII_ADDR_SHIFT) | (reg & 0xff)); 621 ag71xx_wr(ag, AG71XX_REG_MII_CTRL, val); 622 623 return ag71xx_mdio_wait_busy(ag); 624 } 625 626 static const u32 ar71xx_mdio_div_table[] = { 627 4, 4, 6, 8, 10, 14, 20, 28, 628 }; 629 630 static const u32 ar7240_mdio_div_table[] = { 631 2, 2, 4, 6, 8, 12, 18, 26, 32, 40, 48, 56, 62, 70, 78, 96, 632 }; 633 634 static const u32 ar933x_mdio_div_table[] = { 635 4, 4, 6, 8, 10, 14, 20, 28, 34, 42, 50, 58, 66, 74, 82, 98, 636 }; 637 638 static int ag71xx_mdio_get_divider(struct ag71xx *ag, u32 *div) 639 { 640 unsigned long ref_clock; 641 const u32 *table; 642 int ndivs, i; 643 644 ref_clock = clk_get_rate(ag->clk_mdio); 645 if (!ref_clock) 646 return -EINVAL; 647 648 if (ag71xx_is(ag, AR9330) || ag71xx_is(ag, AR9340)) { 649 table = ar933x_mdio_div_table; 650 ndivs = ARRAY_SIZE(ar933x_mdio_div_table); 651 } else if (ag71xx_is(ag, AR7240)) { 652 table = ar7240_mdio_div_table; 653 ndivs = ARRAY_SIZE(ar7240_mdio_div_table); 654 } else { 655 table = ar71xx_mdio_div_table; 656 ndivs = ARRAY_SIZE(ar71xx_mdio_div_table); 657 } 658 659 for (i = 0; i < ndivs; i++) { 660 unsigned long t; 661 662 t = ref_clock / table[i]; 663 if (t <= AG71XX_MDIO_MAX_CLK) { 664 *div = i; 665 return 0; 666 } 667 } 668 669 return -ENOENT; 670 } 671 672 static int ag71xx_mdio_reset(struct mii_bus *bus) 673 { 674 struct ag71xx *ag = bus->priv; 675 int err; 676 u32 t; 677 678 err = ag71xx_mdio_get_divider(ag, &t); 679 if (err) 680 return err; 681 682 ag71xx_wr(ag, AG71XX_REG_MII_CFG, t | MII_CFG_RESET); 683 usleep_range(100, 200); 684 685 ag71xx_wr(ag, AG71XX_REG_MII_CFG, t); 686 usleep_range(100, 200); 687 688 return 0; 689 } 690 691 static int ag71xx_mdio_probe(struct ag71xx *ag) 692 { 693 struct device *dev = &ag->pdev->dev; 694 struct net_device *ndev = ag->ndev; 695 static struct mii_bus *mii_bus; 696 struct device_node *np, *mnp; 697 int err; 698 699 np = dev->of_node; 700 ag->mii_bus = NULL; 701 702 ag->clk_mdio = devm_clk_get(dev, "mdio"); 703 if (IS_ERR(ag->clk_mdio)) { 704 netif_err(ag, probe, ndev, "Failed to get mdio clk.\n"); 705 return PTR_ERR(ag->clk_mdio); 706 } 707 708 err = clk_prepare_enable(ag->clk_mdio); 709 if (err) { 710 netif_err(ag, probe, ndev, "Failed to enable mdio clk.\n"); 711 return err; 712 } 713 714 mii_bus = devm_mdiobus_alloc(dev); 715 if (!mii_bus) { 716 err = -ENOMEM; 717 goto mdio_err_put_clk; 718 } 719 720 ag->mdio_reset = of_reset_control_get_exclusive(np, "mdio"); 721 if (IS_ERR(ag->mdio_reset)) { 722 netif_err(ag, probe, ndev, "Failed to get reset mdio.\n"); 723 err = PTR_ERR(ag->mdio_reset); 724 goto mdio_err_put_clk; 725 } 726 727 mii_bus->name = "ag71xx_mdio"; 728 mii_bus->read = ag71xx_mdio_mii_read; 729 mii_bus->write = ag71xx_mdio_mii_write; 730 mii_bus->reset = ag71xx_mdio_reset; 731 mii_bus->priv = ag; 732 mii_bus->parent = dev; 733 snprintf(mii_bus->id, MII_BUS_ID_SIZE, "%s.%d", np->name, ag->mac_idx); 734 735 if (!IS_ERR(ag->mdio_reset)) { 736 reset_control_assert(ag->mdio_reset); 737 msleep(100); 738 reset_control_deassert(ag->mdio_reset); 739 msleep(200); 740 } 741 742 mnp = of_get_child_by_name(np, "mdio"); 743 err = of_mdiobus_register(mii_bus, mnp); 744 of_node_put(mnp); 745 if (err) 746 goto mdio_err_put_clk; 747 748 ag->mii_bus = mii_bus; 749 750 return 0; 751 752 mdio_err_put_clk: 753 clk_disable_unprepare(ag->clk_mdio); 754 return err; 755 } 756 757 static void ag71xx_mdio_remove(struct ag71xx *ag) 758 { 759 if (ag->mii_bus) 760 mdiobus_unregister(ag->mii_bus); 761 clk_disable_unprepare(ag->clk_mdio); 762 } 763 764 static void ag71xx_hw_stop(struct ag71xx *ag) 765 { 766 /* disable all interrupts and stop the rx/tx engine */ 767 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0); 768 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0); 769 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0); 770 } 771 772 static bool ag71xx_check_dma_stuck(struct ag71xx *ag) 773 { 774 unsigned long timestamp; 775 u32 rx_sm, tx_sm, rx_fd; 776 777 timestamp = READ_ONCE(netdev_get_tx_queue(ag->ndev, 0)->trans_start); 778 if (likely(time_before(jiffies, timestamp + HZ / 10))) 779 return false; 780 781 if (!netif_carrier_ok(ag->ndev)) 782 return false; 783 784 rx_sm = ag71xx_rr(ag, AG71XX_REG_RX_SM); 785 if ((rx_sm & 0x7) == 0x3 && ((rx_sm >> 4) & 0x7) == 0x6) 786 return true; 787 788 tx_sm = ag71xx_rr(ag, AG71XX_REG_TX_SM); 789 rx_fd = ag71xx_rr(ag, AG71XX_REG_FIFO_DEPTH); 790 if (((tx_sm >> 4) & 0x7) == 0 && ((rx_sm & 0x7) == 0) && 791 ((rx_sm >> 4) & 0x7) == 0 && rx_fd == 0) 792 return true; 793 794 return false; 795 } 796 797 static int ag71xx_tx_packets(struct ag71xx *ag, bool flush, int budget) 798 { 799 struct ag71xx_ring *ring = &ag->tx_ring; 800 int sent = 0, bytes_compl = 0, n = 0; 801 struct net_device *ndev = ag->ndev; 802 int ring_mask, ring_size; 803 bool dma_stuck = false; 804 805 ring_mask = BIT(ring->order) - 1; 806 ring_size = BIT(ring->order); 807 808 netif_dbg(ag, tx_queued, ndev, "processing TX ring\n"); 809 810 while (ring->dirty + n != ring->curr) { 811 struct ag71xx_desc *desc; 812 struct sk_buff *skb; 813 unsigned int i; 814 815 i = (ring->dirty + n) & ring_mask; 816 desc = ag71xx_ring_desc(ring, i); 817 skb = ring->buf[i].tx.skb; 818 819 if (!flush && !ag71xx_desc_empty(desc)) { 820 if (ag->dcfg->tx_hang_workaround && 821 ag71xx_check_dma_stuck(ag)) { 822 schedule_delayed_work(&ag->restart_work, 823 HZ / 2); 824 dma_stuck = true; 825 } 826 break; 827 } 828 829 if (flush) 830 desc->ctrl |= DESC_EMPTY; 831 832 n++; 833 if (!skb) 834 continue; 835 836 napi_consume_skb(skb, budget); 837 ring->buf[i].tx.skb = NULL; 838 839 bytes_compl += ring->buf[i].tx.len; 840 841 sent++; 842 ring->dirty += n; 843 844 while (n > 0) { 845 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS); 846 n--; 847 } 848 } 849 850 netif_dbg(ag, tx_done, ndev, "%d packets sent out\n", sent); 851 852 if (!sent) 853 return 0; 854 855 ag->ndev->stats.tx_bytes += bytes_compl; 856 ag->ndev->stats.tx_packets += sent; 857 858 netdev_completed_queue(ag->ndev, sent, bytes_compl); 859 if ((ring->curr - ring->dirty) < (ring_size * 3) / 4) 860 netif_wake_queue(ag->ndev); 861 862 if (!dma_stuck) 863 cancel_delayed_work(&ag->restart_work); 864 865 return sent; 866 } 867 868 static void ag71xx_dma_wait_stop(struct ag71xx *ag) 869 { 870 struct net_device *ndev = ag->ndev; 871 int i; 872 873 for (i = 0; i < AG71XX_DMA_RETRY; i++) { 874 u32 rx, tx; 875 876 mdelay(AG71XX_DMA_DELAY); 877 878 rx = ag71xx_rr(ag, AG71XX_REG_RX_CTRL) & RX_CTRL_RXE; 879 tx = ag71xx_rr(ag, AG71XX_REG_TX_CTRL) & TX_CTRL_TXE; 880 if (!rx && !tx) 881 return; 882 } 883 884 netif_err(ag, hw, ndev, "DMA stop operation timed out\n"); 885 } 886 887 static void ag71xx_dma_reset(struct ag71xx *ag) 888 { 889 struct net_device *ndev = ag->ndev; 890 u32 val; 891 int i; 892 893 /* stop RX and TX */ 894 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0); 895 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0); 896 897 /* give the hardware some time to really stop all rx/tx activity 898 * clearing the descriptors too early causes random memory corruption 899 */ 900 ag71xx_dma_wait_stop(ag); 901 902 /* clear descriptor addresses */ 903 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma); 904 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma); 905 906 /* clear pending RX/TX interrupts */ 907 for (i = 0; i < 256; i++) { 908 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR); 909 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS); 910 } 911 912 /* clear pending errors */ 913 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF); 914 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR); 915 916 val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS); 917 if (val) 918 netif_err(ag, hw, ndev, "unable to clear DMA Rx status: %08x\n", 919 val); 920 921 val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS); 922 923 /* mask out reserved bits */ 924 val &= ~0xff000000; 925 926 if (val) 927 netif_err(ag, hw, ndev, "unable to clear DMA Tx status: %08x\n", 928 val); 929 } 930 931 static void ag71xx_hw_setup(struct ag71xx *ag) 932 { 933 u32 init = MAC_CFG1_INIT; 934 935 /* setup MAC configuration registers */ 936 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, init); 937 938 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2, 939 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK); 940 941 /* setup max frame length to zero */ 942 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, 0); 943 944 /* setup FIFO configuration registers */ 945 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT); 946 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, ag->fifodata[0]); 947 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, ag->fifodata[1]); 948 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT); 949 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT); 950 } 951 952 static unsigned int ag71xx_max_frame_len(unsigned int mtu) 953 { 954 return ETH_HLEN + VLAN_HLEN + mtu + ETH_FCS_LEN; 955 } 956 957 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, const unsigned char *mac) 958 { 959 u32 t; 960 961 t = (((u32)mac[5]) << 24) | (((u32)mac[4]) << 16) 962 | (((u32)mac[3]) << 8) | ((u32)mac[2]); 963 964 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t); 965 966 t = (((u32)mac[1]) << 24) | (((u32)mac[0]) << 16); 967 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t); 968 } 969 970 static void ag71xx_fast_reset(struct ag71xx *ag) 971 { 972 struct net_device *dev = ag->ndev; 973 u32 rx_ds; 974 u32 mii_reg; 975 976 ag71xx_hw_stop(ag); 977 978 mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG); 979 rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC); 980 981 ag71xx_tx_packets(ag, true, 0); 982 983 reset_control_assert(ag->mac_reset); 984 usleep_range(10, 20); 985 reset_control_deassert(ag->mac_reset); 986 usleep_range(10, 20); 987 988 ag71xx_dma_reset(ag); 989 ag71xx_hw_setup(ag); 990 ag->tx_ring.curr = 0; 991 ag->tx_ring.dirty = 0; 992 netdev_reset_queue(ag->ndev); 993 994 /* setup max frame length */ 995 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, 996 ag71xx_max_frame_len(ag->ndev->mtu)); 997 998 ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds); 999 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma); 1000 ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg); 1001 1002 ag71xx_hw_set_macaddr(ag, dev->dev_addr); 1003 } 1004 1005 static void ag71xx_hw_start(struct ag71xx *ag) 1006 { 1007 /* start RX engine */ 1008 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE); 1009 1010 /* enable interrupts */ 1011 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT); 1012 1013 netif_wake_queue(ag->ndev); 1014 } 1015 1016 static void ag71xx_mac_config(struct phylink_config *config, unsigned int mode, 1017 const struct phylink_link_state *state) 1018 { 1019 struct ag71xx *ag = netdev_priv(to_net_dev(config->dev)); 1020 1021 if (phylink_autoneg_inband(mode)) 1022 return; 1023 1024 if (!ag71xx_is(ag, AR7100) && !ag71xx_is(ag, AR9130)) 1025 ag71xx_fast_reset(ag); 1026 1027 if (ag->tx_ring.desc_split) { 1028 ag->fifodata[2] &= 0xffff; 1029 ag->fifodata[2] |= ((2048 - ag->tx_ring.desc_split) / 4) << 16; 1030 } 1031 1032 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, ag->fifodata[2]); 1033 } 1034 1035 static void ag71xx_mac_link_down(struct phylink_config *config, 1036 unsigned int mode, phy_interface_t interface) 1037 { 1038 struct ag71xx *ag = netdev_priv(to_net_dev(config->dev)); 1039 1040 ag71xx_hw_stop(ag); 1041 } 1042 1043 static void ag71xx_mac_link_up(struct phylink_config *config, 1044 struct phy_device *phy, 1045 unsigned int mode, phy_interface_t interface, 1046 int speed, int duplex, 1047 bool tx_pause, bool rx_pause) 1048 { 1049 struct ag71xx *ag = netdev_priv(to_net_dev(config->dev)); 1050 u32 cfg1, cfg2; 1051 u32 ifctl; 1052 u32 fifo5; 1053 1054 cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2); 1055 cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX); 1056 cfg2 |= duplex ? MAC_CFG2_FDX : 0; 1057 1058 ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL); 1059 ifctl &= ~(MAC_IFCTL_SPEED); 1060 1061 fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5); 1062 fifo5 &= ~FIFO_CFG5_BM; 1063 1064 switch (speed) { 1065 case SPEED_1000: 1066 cfg2 |= MAC_CFG2_IF_1000; 1067 fifo5 |= FIFO_CFG5_BM; 1068 break; 1069 case SPEED_100: 1070 cfg2 |= MAC_CFG2_IF_10_100; 1071 ifctl |= MAC_IFCTL_SPEED; 1072 break; 1073 case SPEED_10: 1074 cfg2 |= MAC_CFG2_IF_10_100; 1075 break; 1076 default: 1077 return; 1078 } 1079 1080 ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2); 1081 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5); 1082 ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl); 1083 1084 cfg1 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG1); 1085 cfg1 &= ~(MAC_CFG1_TFC | MAC_CFG1_RFC); 1086 if (tx_pause) 1087 cfg1 |= MAC_CFG1_TFC; 1088 1089 if (rx_pause) 1090 cfg1 |= MAC_CFG1_RFC; 1091 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, cfg1); 1092 1093 ag71xx_hw_start(ag); 1094 } 1095 1096 static const struct phylink_mac_ops ag71xx_phylink_mac_ops = { 1097 .mac_config = ag71xx_mac_config, 1098 .mac_link_down = ag71xx_mac_link_down, 1099 .mac_link_up = ag71xx_mac_link_up, 1100 }; 1101 1102 static int ag71xx_phylink_setup(struct ag71xx *ag) 1103 { 1104 struct phylink *phylink; 1105 1106 ag->phylink_config.dev = &ag->ndev->dev; 1107 ag->phylink_config.type = PHYLINK_NETDEV; 1108 ag->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE | 1109 MAC_10 | MAC_100 | MAC_1000FD; 1110 1111 if ((ag71xx_is(ag, AR9330) && ag->mac_idx == 0) || 1112 ag71xx_is(ag, AR9340) || 1113 ag71xx_is(ag, QCA9530) || 1114 (ag71xx_is(ag, QCA9550) && ag->mac_idx == 1)) 1115 __set_bit(PHY_INTERFACE_MODE_MII, 1116 ag->phylink_config.supported_interfaces); 1117 1118 if ((ag71xx_is(ag, AR9330) && ag->mac_idx == 1) || 1119 (ag71xx_is(ag, AR9340) && ag->mac_idx == 1) || 1120 (ag71xx_is(ag, QCA9530) && ag->mac_idx == 1)) 1121 __set_bit(PHY_INTERFACE_MODE_GMII, 1122 ag->phylink_config.supported_interfaces); 1123 1124 if (ag71xx_is(ag, QCA9550) && ag->mac_idx == 0) 1125 __set_bit(PHY_INTERFACE_MODE_SGMII, 1126 ag->phylink_config.supported_interfaces); 1127 1128 if (ag71xx_is(ag, AR9340) && ag->mac_idx == 0) 1129 __set_bit(PHY_INTERFACE_MODE_RMII, 1130 ag->phylink_config.supported_interfaces); 1131 1132 if ((ag71xx_is(ag, AR9340) && ag->mac_idx == 0) || 1133 (ag71xx_is(ag, QCA9550) && ag->mac_idx == 1)) 1134 __set_bit(PHY_INTERFACE_MODE_RGMII, 1135 ag->phylink_config.supported_interfaces); 1136 1137 phylink = phylink_create(&ag->phylink_config, ag->pdev->dev.fwnode, 1138 ag->phy_if_mode, &ag71xx_phylink_mac_ops); 1139 if (IS_ERR(phylink)) 1140 return PTR_ERR(phylink); 1141 1142 ag->phylink = phylink; 1143 return 0; 1144 } 1145 1146 static void ag71xx_ring_tx_clean(struct ag71xx *ag) 1147 { 1148 struct ag71xx_ring *ring = &ag->tx_ring; 1149 int ring_mask = BIT(ring->order) - 1; 1150 u32 bytes_compl = 0, pkts_compl = 0; 1151 struct net_device *ndev = ag->ndev; 1152 1153 while (ring->curr != ring->dirty) { 1154 struct ag71xx_desc *desc; 1155 u32 i = ring->dirty & ring_mask; 1156 1157 desc = ag71xx_ring_desc(ring, i); 1158 if (!ag71xx_desc_empty(desc)) { 1159 desc->ctrl = 0; 1160 ndev->stats.tx_errors++; 1161 } 1162 1163 if (ring->buf[i].tx.skb) { 1164 bytes_compl += ring->buf[i].tx.len; 1165 pkts_compl++; 1166 dev_kfree_skb_any(ring->buf[i].tx.skb); 1167 } 1168 ring->buf[i].tx.skb = NULL; 1169 ring->dirty++; 1170 } 1171 1172 /* flush descriptors */ 1173 wmb(); 1174 1175 netdev_completed_queue(ndev, pkts_compl, bytes_compl); 1176 } 1177 1178 static void ag71xx_ring_tx_init(struct ag71xx *ag) 1179 { 1180 struct ag71xx_ring *ring = &ag->tx_ring; 1181 int ring_size = BIT(ring->order); 1182 int ring_mask = ring_size - 1; 1183 int i; 1184 1185 for (i = 0; i < ring_size; i++) { 1186 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i); 1187 1188 desc->next = (u32)(ring->descs_dma + 1189 AG71XX_DESC_SIZE * ((i + 1) & ring_mask)); 1190 1191 desc->ctrl = DESC_EMPTY; 1192 ring->buf[i].tx.skb = NULL; 1193 } 1194 1195 /* flush descriptors */ 1196 wmb(); 1197 1198 ring->curr = 0; 1199 ring->dirty = 0; 1200 netdev_reset_queue(ag->ndev); 1201 } 1202 1203 static void ag71xx_ring_rx_clean(struct ag71xx *ag) 1204 { 1205 struct ag71xx_ring *ring = &ag->rx_ring; 1206 int ring_size = BIT(ring->order); 1207 int i; 1208 1209 if (!ring->buf) 1210 return; 1211 1212 for (i = 0; i < ring_size; i++) 1213 if (ring->buf[i].rx.rx_buf) { 1214 dma_unmap_single(&ag->pdev->dev, 1215 ring->buf[i].rx.dma_addr, 1216 ag->rx_buf_size, DMA_FROM_DEVICE); 1217 skb_free_frag(ring->buf[i].rx.rx_buf); 1218 } 1219 } 1220 1221 static int ag71xx_buffer_size(struct ag71xx *ag) 1222 { 1223 return ag->rx_buf_size + 1224 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 1225 } 1226 1227 static bool ag71xx_fill_rx_buf(struct ag71xx *ag, struct ag71xx_buf *buf, 1228 int offset, 1229 void *(*alloc)(unsigned int size)) 1230 { 1231 struct ag71xx_ring *ring = &ag->rx_ring; 1232 struct ag71xx_desc *desc; 1233 void *data; 1234 1235 desc = ag71xx_ring_desc(ring, buf - &ring->buf[0]); 1236 1237 data = alloc(ag71xx_buffer_size(ag)); 1238 if (!data) 1239 return false; 1240 1241 buf->rx.rx_buf = data; 1242 buf->rx.dma_addr = dma_map_single(&ag->pdev->dev, data, ag->rx_buf_size, 1243 DMA_FROM_DEVICE); 1244 desc->data = (u32)buf->rx.dma_addr + offset; 1245 return true; 1246 } 1247 1248 static int ag71xx_ring_rx_init(struct ag71xx *ag) 1249 { 1250 struct ag71xx_ring *ring = &ag->rx_ring; 1251 struct net_device *ndev = ag->ndev; 1252 int ring_mask = BIT(ring->order) - 1; 1253 int ring_size = BIT(ring->order); 1254 unsigned int i; 1255 int ret; 1256 1257 ret = 0; 1258 for (i = 0; i < ring_size; i++) { 1259 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i); 1260 1261 desc->next = (u32)(ring->descs_dma + 1262 AG71XX_DESC_SIZE * ((i + 1) & ring_mask)); 1263 1264 netif_dbg(ag, rx_status, ndev, "RX desc at %p, next is %08x\n", 1265 desc, desc->next); 1266 } 1267 1268 for (i = 0; i < ring_size; i++) { 1269 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i); 1270 1271 if (!ag71xx_fill_rx_buf(ag, &ring->buf[i], ag->rx_buf_offset, 1272 netdev_alloc_frag)) { 1273 ret = -ENOMEM; 1274 break; 1275 } 1276 1277 desc->ctrl = DESC_EMPTY; 1278 } 1279 1280 /* flush descriptors */ 1281 wmb(); 1282 1283 ring->curr = 0; 1284 ring->dirty = 0; 1285 1286 return ret; 1287 } 1288 1289 static int ag71xx_ring_rx_refill(struct ag71xx *ag) 1290 { 1291 struct ag71xx_ring *ring = &ag->rx_ring; 1292 int ring_mask = BIT(ring->order) - 1; 1293 int offset = ag->rx_buf_offset; 1294 unsigned int count; 1295 1296 count = 0; 1297 for (; ring->curr - ring->dirty > 0; ring->dirty++) { 1298 struct ag71xx_desc *desc; 1299 unsigned int i; 1300 1301 i = ring->dirty & ring_mask; 1302 desc = ag71xx_ring_desc(ring, i); 1303 1304 if (!ring->buf[i].rx.rx_buf && 1305 !ag71xx_fill_rx_buf(ag, &ring->buf[i], offset, 1306 napi_alloc_frag)) 1307 break; 1308 1309 desc->ctrl = DESC_EMPTY; 1310 count++; 1311 } 1312 1313 /* flush descriptors */ 1314 wmb(); 1315 1316 netif_dbg(ag, rx_status, ag->ndev, "%u rx descriptors refilled\n", 1317 count); 1318 1319 return count; 1320 } 1321 1322 static int ag71xx_rings_init(struct ag71xx *ag) 1323 { 1324 struct ag71xx_ring *tx = &ag->tx_ring; 1325 struct ag71xx_ring *rx = &ag->rx_ring; 1326 int ring_size, tx_size; 1327 1328 ring_size = BIT(tx->order) + BIT(rx->order); 1329 tx_size = BIT(tx->order); 1330 1331 tx->buf = kcalloc(ring_size, sizeof(*tx->buf), GFP_KERNEL); 1332 if (!tx->buf) 1333 return -ENOMEM; 1334 1335 tx->descs_cpu = dma_alloc_coherent(&ag->pdev->dev, 1336 ring_size * AG71XX_DESC_SIZE, 1337 &tx->descs_dma, GFP_KERNEL); 1338 if (!tx->descs_cpu) { 1339 kfree(tx->buf); 1340 tx->buf = NULL; 1341 return -ENOMEM; 1342 } 1343 1344 rx->buf = &tx->buf[tx_size]; 1345 rx->descs_cpu = ((void *)tx->descs_cpu) + tx_size * AG71XX_DESC_SIZE; 1346 rx->descs_dma = tx->descs_dma + tx_size * AG71XX_DESC_SIZE; 1347 1348 ag71xx_ring_tx_init(ag); 1349 return ag71xx_ring_rx_init(ag); 1350 } 1351 1352 static void ag71xx_rings_free(struct ag71xx *ag) 1353 { 1354 struct ag71xx_ring *tx = &ag->tx_ring; 1355 struct ag71xx_ring *rx = &ag->rx_ring; 1356 int ring_size; 1357 1358 ring_size = BIT(tx->order) + BIT(rx->order); 1359 1360 if (tx->descs_cpu) 1361 dma_free_coherent(&ag->pdev->dev, ring_size * AG71XX_DESC_SIZE, 1362 tx->descs_cpu, tx->descs_dma); 1363 1364 kfree(tx->buf); 1365 1366 tx->descs_cpu = NULL; 1367 rx->descs_cpu = NULL; 1368 tx->buf = NULL; 1369 rx->buf = NULL; 1370 } 1371 1372 static void ag71xx_rings_cleanup(struct ag71xx *ag) 1373 { 1374 ag71xx_ring_rx_clean(ag); 1375 ag71xx_ring_tx_clean(ag); 1376 ag71xx_rings_free(ag); 1377 1378 netdev_reset_queue(ag->ndev); 1379 } 1380 1381 static void ag71xx_hw_init(struct ag71xx *ag) 1382 { 1383 ag71xx_hw_stop(ag); 1384 1385 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR); 1386 usleep_range(20, 30); 1387 1388 reset_control_assert(ag->mac_reset); 1389 msleep(100); 1390 reset_control_deassert(ag->mac_reset); 1391 msleep(200); 1392 1393 ag71xx_hw_setup(ag); 1394 1395 ag71xx_dma_reset(ag); 1396 } 1397 1398 static int ag71xx_hw_enable(struct ag71xx *ag) 1399 { 1400 int ret; 1401 1402 ret = ag71xx_rings_init(ag); 1403 if (ret) 1404 return ret; 1405 1406 napi_enable(&ag->napi); 1407 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma); 1408 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma); 1409 netif_start_queue(ag->ndev); 1410 1411 return 0; 1412 } 1413 1414 static void ag71xx_hw_disable(struct ag71xx *ag) 1415 { 1416 netif_stop_queue(ag->ndev); 1417 1418 ag71xx_hw_stop(ag); 1419 ag71xx_dma_reset(ag); 1420 1421 napi_disable(&ag->napi); 1422 del_timer_sync(&ag->oom_timer); 1423 1424 ag71xx_rings_cleanup(ag); 1425 } 1426 1427 static int ag71xx_open(struct net_device *ndev) 1428 { 1429 struct ag71xx *ag = netdev_priv(ndev); 1430 unsigned int max_frame_len; 1431 int ret; 1432 1433 ret = phylink_of_phy_connect(ag->phylink, ag->pdev->dev.of_node, 0); 1434 if (ret) { 1435 netif_err(ag, link, ndev, "phylink_of_phy_connect filed with err: %i\n", 1436 ret); 1437 return ret; 1438 } 1439 1440 max_frame_len = ag71xx_max_frame_len(ndev->mtu); 1441 ag->rx_buf_size = 1442 SKB_DATA_ALIGN(max_frame_len + NET_SKB_PAD + NET_IP_ALIGN); 1443 1444 /* setup max frame length */ 1445 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, max_frame_len); 1446 ag71xx_hw_set_macaddr(ag, ndev->dev_addr); 1447 1448 ret = ag71xx_hw_enable(ag); 1449 if (ret) 1450 goto err; 1451 1452 phylink_start(ag->phylink); 1453 1454 return 0; 1455 1456 err: 1457 ag71xx_rings_cleanup(ag); 1458 phylink_disconnect_phy(ag->phylink); 1459 return ret; 1460 } 1461 1462 static int ag71xx_stop(struct net_device *ndev) 1463 { 1464 struct ag71xx *ag = netdev_priv(ndev); 1465 1466 phylink_stop(ag->phylink); 1467 phylink_disconnect_phy(ag->phylink); 1468 ag71xx_hw_disable(ag); 1469 1470 return 0; 1471 } 1472 1473 static int ag71xx_fill_dma_desc(struct ag71xx_ring *ring, u32 addr, int len) 1474 { 1475 int i, ring_mask, ndesc, split; 1476 struct ag71xx_desc *desc; 1477 1478 ring_mask = BIT(ring->order) - 1; 1479 ndesc = 0; 1480 split = ring->desc_split; 1481 1482 if (!split) 1483 split = len; 1484 1485 while (len > 0) { 1486 unsigned int cur_len = len; 1487 1488 i = (ring->curr + ndesc) & ring_mask; 1489 desc = ag71xx_ring_desc(ring, i); 1490 1491 if (!ag71xx_desc_empty(desc)) 1492 return -1; 1493 1494 if (cur_len > split) { 1495 cur_len = split; 1496 1497 /* TX will hang if DMA transfers <= 4 bytes, 1498 * make sure next segment is more than 4 bytes long. 1499 */ 1500 if (len <= split + 4) 1501 cur_len -= 4; 1502 } 1503 1504 desc->data = addr; 1505 addr += cur_len; 1506 len -= cur_len; 1507 1508 if (len > 0) 1509 cur_len |= DESC_MORE; 1510 1511 /* prevent early tx attempt of this descriptor */ 1512 if (!ndesc) 1513 cur_len |= DESC_EMPTY; 1514 1515 desc->ctrl = cur_len; 1516 ndesc++; 1517 } 1518 1519 return ndesc; 1520 } 1521 1522 static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb, 1523 struct net_device *ndev) 1524 { 1525 int i, n, ring_min, ring_mask, ring_size; 1526 struct ag71xx *ag = netdev_priv(ndev); 1527 struct ag71xx_ring *ring; 1528 struct ag71xx_desc *desc; 1529 dma_addr_t dma_addr; 1530 1531 ring = &ag->tx_ring; 1532 ring_mask = BIT(ring->order) - 1; 1533 ring_size = BIT(ring->order); 1534 1535 if (skb->len <= 4) { 1536 netif_dbg(ag, tx_err, ndev, "packet len is too small\n"); 1537 goto err_drop; 1538 } 1539 1540 dma_addr = dma_map_single(&ag->pdev->dev, skb->data, skb->len, 1541 DMA_TO_DEVICE); 1542 1543 i = ring->curr & ring_mask; 1544 desc = ag71xx_ring_desc(ring, i); 1545 1546 /* setup descriptor fields */ 1547 n = ag71xx_fill_dma_desc(ring, (u32)dma_addr, 1548 skb->len & ag->dcfg->desc_pktlen_mask); 1549 if (n < 0) 1550 goto err_drop_unmap; 1551 1552 i = (ring->curr + n - 1) & ring_mask; 1553 ring->buf[i].tx.len = skb->len; 1554 ring->buf[i].tx.skb = skb; 1555 1556 netdev_sent_queue(ndev, skb->len); 1557 1558 skb_tx_timestamp(skb); 1559 1560 desc->ctrl &= ~DESC_EMPTY; 1561 ring->curr += n; 1562 1563 /* flush descriptor */ 1564 wmb(); 1565 1566 ring_min = 2; 1567 if (ring->desc_split) 1568 ring_min *= AG71XX_TX_RING_DS_PER_PKT; 1569 1570 if (ring->curr - ring->dirty >= ring_size - ring_min) { 1571 netif_dbg(ag, tx_err, ndev, "tx queue full\n"); 1572 netif_stop_queue(ndev); 1573 } 1574 1575 netif_dbg(ag, tx_queued, ndev, "packet injected into TX queue\n"); 1576 1577 /* enable TX engine */ 1578 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE); 1579 1580 return NETDEV_TX_OK; 1581 1582 err_drop_unmap: 1583 dma_unmap_single(&ag->pdev->dev, dma_addr, skb->len, DMA_TO_DEVICE); 1584 1585 err_drop: 1586 ndev->stats.tx_dropped++; 1587 1588 dev_kfree_skb(skb); 1589 return NETDEV_TX_OK; 1590 } 1591 1592 static void ag71xx_oom_timer_handler(struct timer_list *t) 1593 { 1594 struct ag71xx *ag = from_timer(ag, t, oom_timer); 1595 1596 napi_schedule(&ag->napi); 1597 } 1598 1599 static void ag71xx_tx_timeout(struct net_device *ndev, unsigned int txqueue) 1600 { 1601 struct ag71xx *ag = netdev_priv(ndev); 1602 1603 netif_err(ag, tx_err, ndev, "tx timeout\n"); 1604 1605 schedule_delayed_work(&ag->restart_work, 1); 1606 } 1607 1608 static void ag71xx_restart_work_func(struct work_struct *work) 1609 { 1610 struct ag71xx *ag = container_of(work, struct ag71xx, 1611 restart_work.work); 1612 1613 rtnl_lock(); 1614 ag71xx_hw_disable(ag); 1615 ag71xx_hw_enable(ag); 1616 1617 phylink_stop(ag->phylink); 1618 phylink_start(ag->phylink); 1619 1620 rtnl_unlock(); 1621 } 1622 1623 static int ag71xx_rx_packets(struct ag71xx *ag, int limit) 1624 { 1625 struct net_device *ndev = ag->ndev; 1626 int ring_mask, ring_size, done = 0; 1627 unsigned int pktlen_mask, offset; 1628 struct ag71xx_ring *ring; 1629 struct list_head rx_list; 1630 struct sk_buff *skb; 1631 1632 ring = &ag->rx_ring; 1633 pktlen_mask = ag->dcfg->desc_pktlen_mask; 1634 offset = ag->rx_buf_offset; 1635 ring_mask = BIT(ring->order) - 1; 1636 ring_size = BIT(ring->order); 1637 1638 netif_dbg(ag, rx_status, ndev, "rx packets, limit=%d, curr=%u, dirty=%u\n", 1639 limit, ring->curr, ring->dirty); 1640 1641 INIT_LIST_HEAD(&rx_list); 1642 1643 while (done < limit) { 1644 unsigned int i = ring->curr & ring_mask; 1645 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i); 1646 int pktlen; 1647 int err = 0; 1648 1649 if (ag71xx_desc_empty(desc)) 1650 break; 1651 1652 if ((ring->dirty + ring_size) == ring->curr) { 1653 WARN_ONCE(1, "RX out of ring"); 1654 break; 1655 } 1656 1657 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR); 1658 1659 pktlen = desc->ctrl & pktlen_mask; 1660 pktlen -= ETH_FCS_LEN; 1661 1662 dma_unmap_single(&ag->pdev->dev, ring->buf[i].rx.dma_addr, 1663 ag->rx_buf_size, DMA_FROM_DEVICE); 1664 1665 ndev->stats.rx_packets++; 1666 ndev->stats.rx_bytes += pktlen; 1667 1668 skb = napi_build_skb(ring->buf[i].rx.rx_buf, ag71xx_buffer_size(ag)); 1669 if (!skb) { 1670 skb_free_frag(ring->buf[i].rx.rx_buf); 1671 goto next; 1672 } 1673 1674 skb_reserve(skb, offset); 1675 skb_put(skb, pktlen); 1676 1677 if (err) { 1678 ndev->stats.rx_dropped++; 1679 kfree_skb(skb); 1680 } else { 1681 skb->dev = ndev; 1682 skb->ip_summed = CHECKSUM_NONE; 1683 list_add_tail(&skb->list, &rx_list); 1684 } 1685 1686 next: 1687 ring->buf[i].rx.rx_buf = NULL; 1688 done++; 1689 1690 ring->curr++; 1691 } 1692 1693 ag71xx_ring_rx_refill(ag); 1694 1695 list_for_each_entry(skb, &rx_list, list) 1696 skb->protocol = eth_type_trans(skb, ndev); 1697 netif_receive_skb_list(&rx_list); 1698 1699 netif_dbg(ag, rx_status, ndev, "rx finish, curr=%u, dirty=%u, done=%d\n", 1700 ring->curr, ring->dirty, done); 1701 1702 return done; 1703 } 1704 1705 static int ag71xx_poll(struct napi_struct *napi, int limit) 1706 { 1707 struct ag71xx *ag = container_of(napi, struct ag71xx, napi); 1708 struct ag71xx_ring *rx_ring = &ag->rx_ring; 1709 int rx_ring_size = BIT(rx_ring->order); 1710 struct net_device *ndev = ag->ndev; 1711 int tx_done, rx_done; 1712 u32 status; 1713 1714 tx_done = ag71xx_tx_packets(ag, false, limit); 1715 1716 netif_dbg(ag, rx_status, ndev, "processing RX ring\n"); 1717 rx_done = ag71xx_rx_packets(ag, limit); 1718 1719 if (!rx_ring->buf[rx_ring->dirty % rx_ring_size].rx.rx_buf) 1720 goto oom; 1721 1722 status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS); 1723 if (unlikely(status & RX_STATUS_OF)) { 1724 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF); 1725 ndev->stats.rx_fifo_errors++; 1726 1727 /* restart RX */ 1728 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE); 1729 } 1730 1731 if (rx_done < limit) { 1732 if (status & RX_STATUS_PR) 1733 goto more; 1734 1735 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS); 1736 if (status & TX_STATUS_PS) 1737 goto more; 1738 1739 netif_dbg(ag, rx_status, ndev, "disable polling mode, rx=%d, tx=%d,limit=%d\n", 1740 rx_done, tx_done, limit); 1741 1742 napi_complete(napi); 1743 1744 /* enable interrupts */ 1745 ag71xx_int_enable(ag, AG71XX_INT_POLL); 1746 return rx_done; 1747 } 1748 1749 more: 1750 netif_dbg(ag, rx_status, ndev, "stay in polling mode, rx=%d, tx=%d, limit=%d\n", 1751 rx_done, tx_done, limit); 1752 return limit; 1753 1754 oom: 1755 netif_err(ag, rx_err, ndev, "out of memory\n"); 1756 1757 mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL); 1758 napi_complete(napi); 1759 return 0; 1760 } 1761 1762 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id) 1763 { 1764 struct net_device *ndev = dev_id; 1765 struct ag71xx *ag; 1766 u32 status; 1767 1768 ag = netdev_priv(ndev); 1769 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS); 1770 1771 if (unlikely(!status)) 1772 return IRQ_NONE; 1773 1774 if (unlikely(status & AG71XX_INT_ERR)) { 1775 if (status & AG71XX_INT_TX_BE) { 1776 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE); 1777 netif_err(ag, intr, ndev, "TX BUS error\n"); 1778 } 1779 if (status & AG71XX_INT_RX_BE) { 1780 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE); 1781 netif_err(ag, intr, ndev, "RX BUS error\n"); 1782 } 1783 } 1784 1785 if (likely(status & AG71XX_INT_POLL)) { 1786 ag71xx_int_disable(ag, AG71XX_INT_POLL); 1787 netif_dbg(ag, intr, ndev, "enable polling mode\n"); 1788 napi_schedule(&ag->napi); 1789 } 1790 1791 return IRQ_HANDLED; 1792 } 1793 1794 static int ag71xx_change_mtu(struct net_device *ndev, int new_mtu) 1795 { 1796 struct ag71xx *ag = netdev_priv(ndev); 1797 1798 WRITE_ONCE(ndev->mtu, new_mtu); 1799 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, 1800 ag71xx_max_frame_len(ndev->mtu)); 1801 1802 return 0; 1803 } 1804 1805 static const struct net_device_ops ag71xx_netdev_ops = { 1806 .ndo_open = ag71xx_open, 1807 .ndo_stop = ag71xx_stop, 1808 .ndo_start_xmit = ag71xx_hard_start_xmit, 1809 .ndo_eth_ioctl = ag71xx_do_ioctl, 1810 .ndo_tx_timeout = ag71xx_tx_timeout, 1811 .ndo_change_mtu = ag71xx_change_mtu, 1812 .ndo_set_mac_address = eth_mac_addr, 1813 .ndo_validate_addr = eth_validate_addr, 1814 }; 1815 1816 static const u32 ar71xx_addr_ar7100[] = { 1817 0x19000000, 0x1a000000, 1818 }; 1819 1820 static int ag71xx_probe(struct platform_device *pdev) 1821 { 1822 struct device_node *np = pdev->dev.of_node; 1823 const struct ag71xx_dcfg *dcfg; 1824 struct net_device *ndev; 1825 struct resource *res; 1826 int tx_size, err, i; 1827 struct ag71xx *ag; 1828 1829 if (!np) 1830 return -ENODEV; 1831 1832 ndev = devm_alloc_etherdev(&pdev->dev, sizeof(*ag)); 1833 if (!ndev) 1834 return -ENOMEM; 1835 1836 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1837 if (!res) 1838 return -EINVAL; 1839 1840 dcfg = of_device_get_match_data(&pdev->dev); 1841 if (!dcfg) 1842 return -EINVAL; 1843 1844 ag = netdev_priv(ndev); 1845 ag->mac_idx = -1; 1846 for (i = 0; i < ARRAY_SIZE(ar71xx_addr_ar7100); i++) { 1847 if (ar71xx_addr_ar7100[i] == res->start) 1848 ag->mac_idx = i; 1849 } 1850 1851 if (ag->mac_idx < 0) { 1852 netif_err(ag, probe, ndev, "unknown mac idx\n"); 1853 return -EINVAL; 1854 } 1855 1856 ag->clk_eth = devm_clk_get(&pdev->dev, "eth"); 1857 if (IS_ERR(ag->clk_eth)) { 1858 netif_err(ag, probe, ndev, "Failed to get eth clk.\n"); 1859 return PTR_ERR(ag->clk_eth); 1860 } 1861 1862 SET_NETDEV_DEV(ndev, &pdev->dev); 1863 1864 ag->pdev = pdev; 1865 ag->ndev = ndev; 1866 ag->dcfg = dcfg; 1867 ag->msg_enable = netif_msg_init(-1, AG71XX_DEFAULT_MSG_ENABLE); 1868 memcpy(ag->fifodata, dcfg->fifodata, sizeof(ag->fifodata)); 1869 1870 ag->mac_reset = devm_reset_control_get(&pdev->dev, "mac"); 1871 if (IS_ERR(ag->mac_reset)) { 1872 netif_err(ag, probe, ndev, "missing mac reset\n"); 1873 return PTR_ERR(ag->mac_reset); 1874 } 1875 1876 ag->mac_base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); 1877 if (!ag->mac_base) 1878 return -ENOMEM; 1879 1880 ndev->irq = platform_get_irq(pdev, 0); 1881 err = devm_request_irq(&pdev->dev, ndev->irq, ag71xx_interrupt, 1882 0x0, dev_name(&pdev->dev), ndev); 1883 if (err) { 1884 netif_err(ag, probe, ndev, "unable to request IRQ %d\n", 1885 ndev->irq); 1886 return err; 1887 } 1888 1889 ndev->netdev_ops = &ag71xx_netdev_ops; 1890 ndev->ethtool_ops = &ag71xx_ethtool_ops; 1891 1892 INIT_DELAYED_WORK(&ag->restart_work, ag71xx_restart_work_func); 1893 timer_setup(&ag->oom_timer, ag71xx_oom_timer_handler, 0); 1894 1895 tx_size = AG71XX_TX_RING_SIZE_DEFAULT; 1896 ag->rx_ring.order = ag71xx_ring_size_order(AG71XX_RX_RING_SIZE_DEFAULT); 1897 1898 ndev->min_mtu = 68; 1899 ndev->max_mtu = dcfg->max_frame_len - ag71xx_max_frame_len(0); 1900 1901 ag->rx_buf_offset = NET_SKB_PAD; 1902 if (!ag71xx_is(ag, AR7100) && !ag71xx_is(ag, AR9130)) 1903 ag->rx_buf_offset += NET_IP_ALIGN; 1904 1905 if (ag71xx_is(ag, AR7100)) { 1906 ag->tx_ring.desc_split = AG71XX_TX_RING_SPLIT; 1907 tx_size *= AG71XX_TX_RING_DS_PER_PKT; 1908 } 1909 ag->tx_ring.order = ag71xx_ring_size_order(tx_size); 1910 1911 ag->stop_desc = dmam_alloc_coherent(&pdev->dev, 1912 sizeof(struct ag71xx_desc), 1913 &ag->stop_desc_dma, GFP_KERNEL); 1914 if (!ag->stop_desc) 1915 return -ENOMEM; 1916 1917 ag->stop_desc->data = 0; 1918 ag->stop_desc->ctrl = 0; 1919 ag->stop_desc->next = (u32)ag->stop_desc_dma; 1920 1921 err = of_get_ethdev_address(np, ndev); 1922 if (err) { 1923 netif_err(ag, probe, ndev, "invalid MAC address, using random address\n"); 1924 eth_hw_addr_random(ndev); 1925 } 1926 1927 err = of_get_phy_mode(np, &ag->phy_if_mode); 1928 if (err) { 1929 netif_err(ag, probe, ndev, "missing phy-mode property in DT\n"); 1930 return err; 1931 } 1932 1933 netif_napi_add_weight(ndev, &ag->napi, ag71xx_poll, 1934 AG71XX_NAPI_WEIGHT); 1935 1936 err = clk_prepare_enable(ag->clk_eth); 1937 if (err) { 1938 netif_err(ag, probe, ndev, "Failed to enable eth clk.\n"); 1939 return err; 1940 } 1941 1942 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, 0); 1943 1944 ag71xx_hw_init(ag); 1945 1946 err = ag71xx_mdio_probe(ag); 1947 if (err) 1948 goto err_put_clk; 1949 1950 platform_set_drvdata(pdev, ndev); 1951 1952 err = ag71xx_phylink_setup(ag); 1953 if (err) { 1954 netif_err(ag, probe, ndev, "failed to setup phylink (%d)\n", err); 1955 goto err_mdio_remove; 1956 } 1957 1958 err = register_netdev(ndev); 1959 if (err) { 1960 netif_err(ag, probe, ndev, "unable to register net device\n"); 1961 platform_set_drvdata(pdev, NULL); 1962 goto err_mdio_remove; 1963 } 1964 1965 netif_info(ag, probe, ndev, "Atheros AG71xx at 0x%08lx, irq %d, mode:%s\n", 1966 (unsigned long)ag->mac_base, ndev->irq, 1967 phy_modes(ag->phy_if_mode)); 1968 1969 return 0; 1970 1971 err_mdio_remove: 1972 ag71xx_mdio_remove(ag); 1973 err_put_clk: 1974 clk_disable_unprepare(ag->clk_eth); 1975 return err; 1976 } 1977 1978 static void ag71xx_remove(struct platform_device *pdev) 1979 { 1980 struct net_device *ndev = platform_get_drvdata(pdev); 1981 struct ag71xx *ag; 1982 1983 if (!ndev) 1984 return; 1985 1986 ag = netdev_priv(ndev); 1987 unregister_netdev(ndev); 1988 ag71xx_mdio_remove(ag); 1989 clk_disable_unprepare(ag->clk_eth); 1990 platform_set_drvdata(pdev, NULL); 1991 } 1992 1993 static const u32 ar71xx_fifo_ar7100[] = { 1994 0x0fff0000, 0x00001fff, 0x00780fff, 1995 }; 1996 1997 static const u32 ar71xx_fifo_ar9130[] = { 1998 0x0fff0000, 0x00001fff, 0x008001ff, 1999 }; 2000 2001 static const u32 ar71xx_fifo_ar9330[] = { 2002 0x0010ffff, 0x015500aa, 0x01f00140, 2003 }; 2004 2005 static const struct ag71xx_dcfg ag71xx_dcfg_ar7100 = { 2006 .type = AR7100, 2007 .fifodata = ar71xx_fifo_ar7100, 2008 .max_frame_len = 1540, 2009 .desc_pktlen_mask = SZ_4K - 1, 2010 .tx_hang_workaround = false, 2011 }; 2012 2013 static const struct ag71xx_dcfg ag71xx_dcfg_ar7240 = { 2014 .type = AR7240, 2015 .fifodata = ar71xx_fifo_ar7100, 2016 .max_frame_len = 1540, 2017 .desc_pktlen_mask = SZ_4K - 1, 2018 .tx_hang_workaround = true, 2019 }; 2020 2021 static const struct ag71xx_dcfg ag71xx_dcfg_ar9130 = { 2022 .type = AR9130, 2023 .fifodata = ar71xx_fifo_ar9130, 2024 .max_frame_len = 1540, 2025 .desc_pktlen_mask = SZ_4K - 1, 2026 .tx_hang_workaround = false, 2027 }; 2028 2029 static const struct ag71xx_dcfg ag71xx_dcfg_ar9330 = { 2030 .type = AR9330, 2031 .fifodata = ar71xx_fifo_ar9330, 2032 .max_frame_len = 1540, 2033 .desc_pktlen_mask = SZ_4K - 1, 2034 .tx_hang_workaround = true, 2035 }; 2036 2037 static const struct ag71xx_dcfg ag71xx_dcfg_ar9340 = { 2038 .type = AR9340, 2039 .fifodata = ar71xx_fifo_ar9330, 2040 .max_frame_len = SZ_16K - 1, 2041 .desc_pktlen_mask = SZ_16K - 1, 2042 .tx_hang_workaround = true, 2043 }; 2044 2045 static const struct ag71xx_dcfg ag71xx_dcfg_qca9530 = { 2046 .type = QCA9530, 2047 .fifodata = ar71xx_fifo_ar9330, 2048 .max_frame_len = SZ_16K - 1, 2049 .desc_pktlen_mask = SZ_16K - 1, 2050 .tx_hang_workaround = true, 2051 }; 2052 2053 static const struct ag71xx_dcfg ag71xx_dcfg_qca9550 = { 2054 .type = QCA9550, 2055 .fifodata = ar71xx_fifo_ar9330, 2056 .max_frame_len = 1540, 2057 .desc_pktlen_mask = SZ_16K - 1, 2058 .tx_hang_workaround = true, 2059 }; 2060 2061 static const struct of_device_id ag71xx_match[] = { 2062 { .compatible = "qca,ar7100-eth", .data = &ag71xx_dcfg_ar7100 }, 2063 { .compatible = "qca,ar7240-eth", .data = &ag71xx_dcfg_ar7240 }, 2064 { .compatible = "qca,ar7241-eth", .data = &ag71xx_dcfg_ar7240 }, 2065 { .compatible = "qca,ar7242-eth", .data = &ag71xx_dcfg_ar7240 }, 2066 { .compatible = "qca,ar9130-eth", .data = &ag71xx_dcfg_ar9130 }, 2067 { .compatible = "qca,ar9330-eth", .data = &ag71xx_dcfg_ar9330 }, 2068 { .compatible = "qca,ar9340-eth", .data = &ag71xx_dcfg_ar9340 }, 2069 { .compatible = "qca,qca9530-eth", .data = &ag71xx_dcfg_qca9530 }, 2070 { .compatible = "qca,qca9550-eth", .data = &ag71xx_dcfg_qca9550 }, 2071 { .compatible = "qca,qca9560-eth", .data = &ag71xx_dcfg_qca9550 }, 2072 {} 2073 }; 2074 2075 static struct platform_driver ag71xx_driver = { 2076 .probe = ag71xx_probe, 2077 .remove_new = ag71xx_remove, 2078 .driver = { 2079 .name = "ag71xx", 2080 .of_match_table = ag71xx_match, 2081 } 2082 }; 2083 2084 module_platform_driver(ag71xx_driver); 2085 MODULE_LICENSE("GPL v2"); 2086