1 // SPDX-License-Identifier: GPL-2.0 2 /* Atheros AR71xx built-in ethernet mac driver 3 * 4 * Copyright (C) 2019 Oleksij Rempel <o.rempel@pengutronix.de> 5 * 6 * List of authors contributed to this driver before mainlining: 7 * Alexander Couzens <lynxis@fe80.eu> 8 * Christian Lamparter <chunkeey@gmail.com> 9 * Chuanhong Guo <gch981213@gmail.com> 10 * Daniel F. Dickinson <cshored@thecshore.com> 11 * David Bauer <mail@david-bauer.net> 12 * Felix Fietkau <nbd@nbd.name> 13 * Gabor Juhos <juhosg@freemail.hu> 14 * Hauke Mehrtens <hauke@hauke-m.de> 15 * Johann Neuhauser <johann@it-neuhauser.de> 16 * John Crispin <john@phrozen.org> 17 * Jo-Philipp Wich <jo@mein.io> 18 * Koen Vandeputte <koen.vandeputte@ncentric.com> 19 * Lucian Cristian <lucian.cristian@gmail.com> 20 * Matt Merhar <mattmerhar@protonmail.com> 21 * Milan Krstic <milan.krstic@gmail.com> 22 * Petr Štetiar <ynezz@true.cz> 23 * Rosen Penev <rosenp@gmail.com> 24 * Stephen Walker <stephendwalker+github@gmail.com> 25 * Vittorio Gambaletta <openwrt@vittgam.net> 26 * Weijie Gao <hackpascal@gmail.com> 27 * Imre Kaloz <kaloz@openwrt.org> 28 */ 29 30 #include <linux/if_vlan.h> 31 #include <linux/mfd/syscon.h> 32 #include <linux/of.h> 33 #include <linux/of_mdio.h> 34 #include <linux/of_net.h> 35 #include <linux/platform_device.h> 36 #include <linux/phylink.h> 37 #include <linux/regmap.h> 38 #include <linux/reset.h> 39 #include <linux/clk.h> 40 #include <linux/io.h> 41 #include <net/selftests.h> 42 43 /* For our NAPI weight bigger does *NOT* mean better - it means more 44 * D-cache misses and lots more wasted cycles than we'll ever 45 * possibly gain from saving instructions. 46 */ 47 #define AG71XX_NAPI_WEIGHT 32 48 #define AG71XX_OOM_REFILL (1 + HZ / 10) 49 50 #define AG71XX_INT_ERR (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE) 51 #define AG71XX_INT_TX (AG71XX_INT_TX_PS) 52 #define AG71XX_INT_RX (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF) 53 54 #define AG71XX_INT_POLL (AG71XX_INT_RX | AG71XX_INT_TX) 55 #define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL) 56 57 #define AG71XX_TX_MTU_LEN 1540 58 59 #define AG71XX_TX_RING_SPLIT 512 60 #define AG71XX_TX_RING_DS_PER_PKT DIV_ROUND_UP(AG71XX_TX_MTU_LEN, \ 61 AG71XX_TX_RING_SPLIT) 62 #define AG71XX_TX_RING_SIZE_DEFAULT 128 63 #define AG71XX_RX_RING_SIZE_DEFAULT 256 64 65 #define AG71XX_MDIO_RETRY 1000 66 #define AG71XX_MDIO_DELAY 5 67 #define AG71XX_MDIO_MAX_CLK 5000000 68 69 /* Register offsets */ 70 #define AG71XX_REG_MAC_CFG1 0x0000 71 #define MAC_CFG1_TXE BIT(0) /* Tx Enable */ 72 #define MAC_CFG1_STX BIT(1) /* Synchronize Tx Enable */ 73 #define MAC_CFG1_RXE BIT(2) /* Rx Enable */ 74 #define MAC_CFG1_SRX BIT(3) /* Synchronize Rx Enable */ 75 #define MAC_CFG1_TFC BIT(4) /* Tx Flow Control Enable */ 76 #define MAC_CFG1_RFC BIT(5) /* Rx Flow Control Enable */ 77 #define MAC_CFG1_SR BIT(31) /* Soft Reset */ 78 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \ 79 MAC_CFG1_SRX | MAC_CFG1_STX) 80 81 #define AG71XX_REG_MAC_CFG2 0x0004 82 #define MAC_CFG2_FDX BIT(0) 83 #define MAC_CFG2_PAD_CRC_EN BIT(2) 84 #define MAC_CFG2_LEN_CHECK BIT(4) 85 #define MAC_CFG2_IF_1000 BIT(9) 86 #define MAC_CFG2_IF_10_100 BIT(8) 87 88 #define AG71XX_REG_MAC_MFL 0x0010 89 90 #define AG71XX_REG_MII_CFG 0x0020 91 #define MII_CFG_CLK_DIV_4 0 92 #define MII_CFG_CLK_DIV_6 2 93 #define MII_CFG_CLK_DIV_8 3 94 #define MII_CFG_CLK_DIV_10 4 95 #define MII_CFG_CLK_DIV_14 5 96 #define MII_CFG_CLK_DIV_20 6 97 #define MII_CFG_CLK_DIV_28 7 98 #define MII_CFG_CLK_DIV_34 8 99 #define MII_CFG_CLK_DIV_42 9 100 #define MII_CFG_CLK_DIV_50 10 101 #define MII_CFG_CLK_DIV_58 11 102 #define MII_CFG_CLK_DIV_66 12 103 #define MII_CFG_CLK_DIV_74 13 104 #define MII_CFG_CLK_DIV_82 14 105 #define MII_CFG_CLK_DIV_98 15 106 #define MII_CFG_RESET BIT(31) 107 108 #define AG71XX_REG_MII_CMD 0x0024 109 #define MII_CMD_READ BIT(0) 110 111 #define AG71XX_REG_MII_ADDR 0x0028 112 #define MII_ADDR_SHIFT 8 113 114 #define AG71XX_REG_MII_CTRL 0x002c 115 #define AG71XX_REG_MII_STATUS 0x0030 116 #define AG71XX_REG_MII_IND 0x0034 117 #define MII_IND_BUSY BIT(0) 118 #define MII_IND_INVALID BIT(2) 119 120 #define AG71XX_REG_MAC_IFCTL 0x0038 121 #define MAC_IFCTL_SPEED BIT(16) 122 123 #define AG71XX_REG_MAC_ADDR1 0x0040 124 #define AG71XX_REG_MAC_ADDR2 0x0044 125 #define AG71XX_REG_FIFO_CFG0 0x0048 126 #define FIFO_CFG0_WTM BIT(0) /* Watermark Module */ 127 #define FIFO_CFG0_RXS BIT(1) /* Rx System Module */ 128 #define FIFO_CFG0_RXF BIT(2) /* Rx Fabric Module */ 129 #define FIFO_CFG0_TXS BIT(3) /* Tx System Module */ 130 #define FIFO_CFG0_TXF BIT(4) /* Tx Fabric Module */ 131 #define FIFO_CFG0_ALL (FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \ 132 | FIFO_CFG0_TXS | FIFO_CFG0_TXF) 133 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT) 134 135 #define FIFO_CFG0_ENABLE_SHIFT 8 136 137 #define AG71XX_REG_FIFO_CFG1 0x004c 138 #define AG71XX_REG_FIFO_CFG2 0x0050 139 #define AG71XX_REG_FIFO_CFG3 0x0054 140 #define AG71XX_REG_FIFO_CFG4 0x0058 141 #define FIFO_CFG4_DE BIT(0) /* Drop Event */ 142 #define FIFO_CFG4_DV BIT(1) /* RX_DV Event */ 143 #define FIFO_CFG4_FC BIT(2) /* False Carrier */ 144 #define FIFO_CFG4_CE BIT(3) /* Code Error */ 145 #define FIFO_CFG4_CR BIT(4) /* CRC error */ 146 #define FIFO_CFG4_LM BIT(5) /* Length Mismatch */ 147 #define FIFO_CFG4_LO BIT(6) /* Length out of range */ 148 #define FIFO_CFG4_OK BIT(7) /* Packet is OK */ 149 #define FIFO_CFG4_MC BIT(8) /* Multicast Packet */ 150 #define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */ 151 #define FIFO_CFG4_DR BIT(10) /* Dribble */ 152 #define FIFO_CFG4_LE BIT(11) /* Long Event */ 153 #define FIFO_CFG4_CF BIT(12) /* Control Frame */ 154 #define FIFO_CFG4_PF BIT(13) /* Pause Frame */ 155 #define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */ 156 #define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */ 157 #define FIFO_CFG4_FT BIT(16) /* Frame Truncated */ 158 #define FIFO_CFG4_UC BIT(17) /* Unicast Packet */ 159 #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \ 160 FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \ 161 FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \ 162 FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \ 163 FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \ 164 FIFO_CFG4_VT) 165 166 #define AG71XX_REG_FIFO_CFG5 0x005c 167 #define FIFO_CFG5_DE BIT(0) /* Drop Event */ 168 #define FIFO_CFG5_DV BIT(1) /* RX_DV Event */ 169 #define FIFO_CFG5_FC BIT(2) /* False Carrier */ 170 #define FIFO_CFG5_CE BIT(3) /* Code Error */ 171 #define FIFO_CFG5_LM BIT(4) /* Length Mismatch */ 172 #define FIFO_CFG5_LO BIT(5) /* Length Out of Range */ 173 #define FIFO_CFG5_OK BIT(6) /* Packet is OK */ 174 #define FIFO_CFG5_MC BIT(7) /* Multicast Packet */ 175 #define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */ 176 #define FIFO_CFG5_DR BIT(9) /* Dribble */ 177 #define FIFO_CFG5_CF BIT(10) /* Control Frame */ 178 #define FIFO_CFG5_PF BIT(11) /* Pause Frame */ 179 #define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */ 180 #define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */ 181 #define FIFO_CFG5_LE BIT(14) /* Long Event */ 182 #define FIFO_CFG5_FT BIT(15) /* Frame Truncated */ 183 #define FIFO_CFG5_16 BIT(16) /* unknown */ 184 #define FIFO_CFG5_17 BIT(17) /* unknown */ 185 #define FIFO_CFG5_SF BIT(18) /* Short Frame */ 186 #define FIFO_CFG5_BM BIT(19) /* Byte Mode */ 187 #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \ 188 FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \ 189 FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \ 190 FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \ 191 FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \ 192 FIFO_CFG5_17 | FIFO_CFG5_SF) 193 194 #define AG71XX_REG_TX_CTRL 0x0180 195 #define TX_CTRL_TXE BIT(0) /* Tx Enable */ 196 197 #define AG71XX_REG_TX_DESC 0x0184 198 #define AG71XX_REG_TX_STATUS 0x0188 199 #define TX_STATUS_PS BIT(0) /* Packet Sent */ 200 #define TX_STATUS_UR BIT(1) /* Tx Underrun */ 201 #define TX_STATUS_BE BIT(3) /* Bus Error */ 202 203 #define AG71XX_REG_RX_CTRL 0x018c 204 #define RX_CTRL_RXE BIT(0) /* Rx Enable */ 205 206 #define AG71XX_DMA_RETRY 10 207 #define AG71XX_DMA_DELAY 1 208 209 #define AG71XX_REG_RX_DESC 0x0190 210 #define AG71XX_REG_RX_STATUS 0x0194 211 #define RX_STATUS_PR BIT(0) /* Packet Received */ 212 #define RX_STATUS_OF BIT(2) /* Rx Overflow */ 213 #define RX_STATUS_BE BIT(3) /* Bus Error */ 214 215 #define AG71XX_REG_INT_ENABLE 0x0198 216 #define AG71XX_REG_INT_STATUS 0x019c 217 #define AG71XX_INT_TX_PS BIT(0) 218 #define AG71XX_INT_TX_UR BIT(1) 219 #define AG71XX_INT_TX_BE BIT(3) 220 #define AG71XX_INT_RX_PR BIT(4) 221 #define AG71XX_INT_RX_OF BIT(6) 222 #define AG71XX_INT_RX_BE BIT(7) 223 224 #define AG71XX_REG_FIFO_DEPTH 0x01a8 225 #define AG71XX_REG_RX_SM 0x01b0 226 #define AG71XX_REG_TX_SM 0x01b4 227 228 #define AG71XX_DEFAULT_MSG_ENABLE \ 229 (NETIF_MSG_DRV \ 230 | NETIF_MSG_PROBE \ 231 | NETIF_MSG_LINK \ 232 | NETIF_MSG_TIMER \ 233 | NETIF_MSG_IFDOWN \ 234 | NETIF_MSG_IFUP \ 235 | NETIF_MSG_RX_ERR \ 236 | NETIF_MSG_TX_ERR) 237 238 struct ag71xx_statistic { 239 unsigned short offset; 240 u32 mask; 241 const char name[ETH_GSTRING_LEN]; 242 }; 243 244 static const struct ag71xx_statistic ag71xx_statistics[] = { 245 { 0x0080, GENMASK(17, 0), "Tx/Rx 64 Byte", }, 246 { 0x0084, GENMASK(17, 0), "Tx/Rx 65-127 Byte", }, 247 { 0x0088, GENMASK(17, 0), "Tx/Rx 128-255 Byte", }, 248 { 0x008C, GENMASK(17, 0), "Tx/Rx 256-511 Byte", }, 249 { 0x0090, GENMASK(17, 0), "Tx/Rx 512-1023 Byte", }, 250 { 0x0094, GENMASK(17, 0), "Tx/Rx 1024-1518 Byte", }, 251 { 0x0098, GENMASK(17, 0), "Tx/Rx 1519-1522 Byte VLAN", }, 252 { 0x009C, GENMASK(23, 0), "Rx Byte", }, 253 { 0x00A0, GENMASK(17, 0), "Rx Packet", }, 254 { 0x00A4, GENMASK(11, 0), "Rx FCS Error", }, 255 { 0x00A8, GENMASK(17, 0), "Rx Multicast Packet", }, 256 { 0x00AC, GENMASK(21, 0), "Rx Broadcast Packet", }, 257 { 0x00B0, GENMASK(17, 0), "Rx Control Frame Packet", }, 258 { 0x00B4, GENMASK(11, 0), "Rx Pause Frame Packet", }, 259 { 0x00B8, GENMASK(11, 0), "Rx Unknown OPCode Packet", }, 260 { 0x00BC, GENMASK(11, 0), "Rx Alignment Error", }, 261 { 0x00C0, GENMASK(15, 0), "Rx Frame Length Error", }, 262 { 0x00C4, GENMASK(11, 0), "Rx Code Error", }, 263 { 0x00C8, GENMASK(11, 0), "Rx Carrier Sense Error", }, 264 { 0x00CC, GENMASK(11, 0), "Rx Undersize Packet", }, 265 { 0x00D0, GENMASK(11, 0), "Rx Oversize Packet", }, 266 { 0x00D4, GENMASK(11, 0), "Rx Fragments", }, 267 { 0x00D8, GENMASK(11, 0), "Rx Jabber", }, 268 { 0x00DC, GENMASK(11, 0), "Rx Dropped Packet", }, 269 { 0x00E0, GENMASK(23, 0), "Tx Byte", }, 270 { 0x00E4, GENMASK(17, 0), "Tx Packet", }, 271 { 0x00E8, GENMASK(17, 0), "Tx Multicast Packet", }, 272 { 0x00EC, GENMASK(17, 0), "Tx Broadcast Packet", }, 273 { 0x00F0, GENMASK(11, 0), "Tx Pause Control Frame", }, 274 { 0x00F4, GENMASK(11, 0), "Tx Deferral Packet", }, 275 { 0x00F8, GENMASK(11, 0), "Tx Excessive Deferral Packet", }, 276 { 0x00FC, GENMASK(11, 0), "Tx Single Collision Packet", }, 277 { 0x0100, GENMASK(11, 0), "Tx Multiple Collision", }, 278 { 0x0104, GENMASK(11, 0), "Tx Late Collision Packet", }, 279 { 0x0108, GENMASK(11, 0), "Tx Excessive Collision Packet", }, 280 { 0x010C, GENMASK(12, 0), "Tx Total Collision", }, 281 { 0x0110, GENMASK(11, 0), "Tx Pause Frames Honored", }, 282 { 0x0114, GENMASK(11, 0), "Tx Drop Frame", }, 283 { 0x0118, GENMASK(11, 0), "Tx Jabber Frame", }, 284 { 0x011C, GENMASK(11, 0), "Tx FCS Error", }, 285 { 0x0120, GENMASK(11, 0), "Tx Control Frame", }, 286 { 0x0124, GENMASK(11, 0), "Tx Oversize Frame", }, 287 { 0x0128, GENMASK(11, 0), "Tx Undersize Frame", }, 288 { 0x012C, GENMASK(11, 0), "Tx Fragment", }, 289 }; 290 291 #define DESC_EMPTY BIT(31) 292 #define DESC_MORE BIT(24) 293 #define DESC_PKTLEN_M 0xfff 294 struct ag71xx_desc { 295 u32 data; 296 u32 ctrl; 297 u32 next; 298 u32 pad; 299 } __aligned(4); 300 301 #define AG71XX_DESC_SIZE roundup(sizeof(struct ag71xx_desc), \ 302 L1_CACHE_BYTES) 303 304 struct ag71xx_buf { 305 union { 306 struct { 307 struct sk_buff *skb; 308 unsigned int len; 309 } tx; 310 struct { 311 dma_addr_t dma_addr; 312 void *rx_buf; 313 } rx; 314 }; 315 }; 316 317 struct ag71xx_ring { 318 /* "Hot" fields in the data path. */ 319 unsigned int curr; 320 unsigned int dirty; 321 322 /* "Cold" fields - not used in the data path. */ 323 struct ag71xx_buf *buf; 324 u16 order; 325 u16 desc_split; 326 dma_addr_t descs_dma; 327 u8 *descs_cpu; 328 }; 329 330 enum ag71xx_type { 331 AR7100, 332 AR7240, 333 AR9130, 334 AR9330, 335 AR9340, 336 QCA9530, 337 QCA9550, 338 }; 339 340 struct ag71xx_dcfg { 341 u32 max_frame_len; 342 const u32 *fifodata; 343 u16 desc_pktlen_mask; 344 bool tx_hang_workaround; 345 enum ag71xx_type type; 346 }; 347 348 struct ag71xx { 349 /* Critical data related to the per-packet data path are clustered 350 * early in this structure to help improve the D-cache footprint. 351 */ 352 struct ag71xx_ring rx_ring ____cacheline_aligned; 353 struct ag71xx_ring tx_ring ____cacheline_aligned; 354 355 u16 rx_buf_size; 356 u8 rx_buf_offset; 357 358 struct net_device *ndev; 359 struct platform_device *pdev; 360 struct napi_struct napi; 361 u32 msg_enable; 362 const struct ag71xx_dcfg *dcfg; 363 364 /* From this point onwards we're not looking at per-packet fields. */ 365 void __iomem *mac_base; 366 367 struct ag71xx_desc *stop_desc; 368 dma_addr_t stop_desc_dma; 369 370 phy_interface_t phy_if_mode; 371 struct phylink *phylink; 372 struct phylink_config phylink_config; 373 374 struct delayed_work restart_work; 375 struct timer_list oom_timer; 376 377 struct reset_control *mac_reset; 378 379 u32 fifodata[3]; 380 int mac_idx; 381 382 struct reset_control *mdio_reset; 383 struct clk *clk_mdio; 384 struct clk *clk_eth; 385 }; 386 387 static int ag71xx_desc_empty(struct ag71xx_desc *desc) 388 { 389 return (desc->ctrl & DESC_EMPTY) != 0; 390 } 391 392 static struct ag71xx_desc *ag71xx_ring_desc(struct ag71xx_ring *ring, int idx) 393 { 394 return (struct ag71xx_desc *)&ring->descs_cpu[idx * AG71XX_DESC_SIZE]; 395 } 396 397 static int ag71xx_ring_size_order(int size) 398 { 399 return fls(size - 1); 400 } 401 402 static bool ag71xx_is(struct ag71xx *ag, enum ag71xx_type type) 403 { 404 return ag->dcfg->type == type; 405 } 406 407 static void ag71xx_wr(struct ag71xx *ag, unsigned int reg, u32 value) 408 { 409 iowrite32(value, ag->mac_base + reg); 410 /* flush write */ 411 (void)ioread32(ag->mac_base + reg); 412 } 413 414 static u32 ag71xx_rr(struct ag71xx *ag, unsigned int reg) 415 { 416 return ioread32(ag->mac_base + reg); 417 } 418 419 static void ag71xx_sb(struct ag71xx *ag, unsigned int reg, u32 mask) 420 { 421 void __iomem *r; 422 423 r = ag->mac_base + reg; 424 iowrite32(ioread32(r) | mask, r); 425 /* flush write */ 426 (void)ioread32(r); 427 } 428 429 static void ag71xx_cb(struct ag71xx *ag, unsigned int reg, u32 mask) 430 { 431 void __iomem *r; 432 433 r = ag->mac_base + reg; 434 iowrite32(ioread32(r) & ~mask, r); 435 /* flush write */ 436 (void)ioread32(r); 437 } 438 439 static void ag71xx_int_enable(struct ag71xx *ag, u32 ints) 440 { 441 ag71xx_sb(ag, AG71XX_REG_INT_ENABLE, ints); 442 } 443 444 static void ag71xx_int_disable(struct ag71xx *ag, u32 ints) 445 { 446 ag71xx_cb(ag, AG71XX_REG_INT_ENABLE, ints); 447 } 448 449 static int ag71xx_do_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd) 450 { 451 struct ag71xx *ag = netdev_priv(ndev); 452 453 return phylink_mii_ioctl(ag->phylink, ifr, cmd); 454 } 455 456 static void ag71xx_get_drvinfo(struct net_device *ndev, 457 struct ethtool_drvinfo *info) 458 { 459 struct ag71xx *ag = netdev_priv(ndev); 460 461 strscpy(info->driver, "ag71xx", sizeof(info->driver)); 462 strscpy(info->bus_info, of_node_full_name(ag->pdev->dev.of_node), 463 sizeof(info->bus_info)); 464 } 465 466 static int ag71xx_get_link_ksettings(struct net_device *ndev, 467 struct ethtool_link_ksettings *kset) 468 { 469 struct ag71xx *ag = netdev_priv(ndev); 470 471 return phylink_ethtool_ksettings_get(ag->phylink, kset); 472 } 473 474 static int ag71xx_set_link_ksettings(struct net_device *ndev, 475 const struct ethtool_link_ksettings *kset) 476 { 477 struct ag71xx *ag = netdev_priv(ndev); 478 479 return phylink_ethtool_ksettings_set(ag->phylink, kset); 480 } 481 482 static int ag71xx_ethtool_nway_reset(struct net_device *ndev) 483 { 484 struct ag71xx *ag = netdev_priv(ndev); 485 486 return phylink_ethtool_nway_reset(ag->phylink); 487 } 488 489 static void ag71xx_ethtool_get_pauseparam(struct net_device *ndev, 490 struct ethtool_pauseparam *pause) 491 { 492 struct ag71xx *ag = netdev_priv(ndev); 493 494 phylink_ethtool_get_pauseparam(ag->phylink, pause); 495 } 496 497 static int ag71xx_ethtool_set_pauseparam(struct net_device *ndev, 498 struct ethtool_pauseparam *pause) 499 { 500 struct ag71xx *ag = netdev_priv(ndev); 501 502 return phylink_ethtool_set_pauseparam(ag->phylink, pause); 503 } 504 505 static void ag71xx_ethtool_get_strings(struct net_device *netdev, u32 sset, 506 u8 *data) 507 { 508 int i; 509 510 switch (sset) { 511 case ETH_SS_STATS: 512 for (i = 0; i < ARRAY_SIZE(ag71xx_statistics); i++) 513 memcpy(data + i * ETH_GSTRING_LEN, 514 ag71xx_statistics[i].name, ETH_GSTRING_LEN); 515 break; 516 case ETH_SS_TEST: 517 net_selftest_get_strings(data); 518 break; 519 } 520 } 521 522 static void ag71xx_ethtool_get_stats(struct net_device *ndev, 523 struct ethtool_stats *stats, u64 *data) 524 { 525 struct ag71xx *ag = netdev_priv(ndev); 526 int i; 527 528 for (i = 0; i < ARRAY_SIZE(ag71xx_statistics); i++) 529 *data++ = ag71xx_rr(ag, ag71xx_statistics[i].offset) 530 & ag71xx_statistics[i].mask; 531 } 532 533 static int ag71xx_ethtool_get_sset_count(struct net_device *ndev, int sset) 534 { 535 switch (sset) { 536 case ETH_SS_STATS: 537 return ARRAY_SIZE(ag71xx_statistics); 538 case ETH_SS_TEST: 539 return net_selftest_get_count(); 540 default: 541 return -EOPNOTSUPP; 542 } 543 } 544 545 static const struct ethtool_ops ag71xx_ethtool_ops = { 546 .get_drvinfo = ag71xx_get_drvinfo, 547 .get_link = ethtool_op_get_link, 548 .get_ts_info = ethtool_op_get_ts_info, 549 .get_link_ksettings = ag71xx_get_link_ksettings, 550 .set_link_ksettings = ag71xx_set_link_ksettings, 551 .nway_reset = ag71xx_ethtool_nway_reset, 552 .get_pauseparam = ag71xx_ethtool_get_pauseparam, 553 .set_pauseparam = ag71xx_ethtool_set_pauseparam, 554 .get_strings = ag71xx_ethtool_get_strings, 555 .get_ethtool_stats = ag71xx_ethtool_get_stats, 556 .get_sset_count = ag71xx_ethtool_get_sset_count, 557 .self_test = net_selftest, 558 }; 559 560 static int ag71xx_mdio_wait_busy(struct ag71xx *ag) 561 { 562 struct net_device *ndev = ag->ndev; 563 int i; 564 565 for (i = 0; i < AG71XX_MDIO_RETRY; i++) { 566 u32 busy; 567 568 udelay(AG71XX_MDIO_DELAY); 569 570 busy = ag71xx_rr(ag, AG71XX_REG_MII_IND); 571 if (!busy) 572 return 0; 573 574 udelay(AG71XX_MDIO_DELAY); 575 } 576 577 netif_err(ag, link, ndev, "MDIO operation timed out\n"); 578 579 return -ETIMEDOUT; 580 } 581 582 static int ag71xx_mdio_mii_read(struct mii_bus *bus, int addr, int reg) 583 { 584 struct ag71xx *ag = bus->priv; 585 int err, val; 586 587 err = ag71xx_mdio_wait_busy(ag); 588 if (err) 589 return err; 590 591 ag71xx_wr(ag, AG71XX_REG_MII_ADDR, 592 ((addr & 0x1f) << MII_ADDR_SHIFT) | (reg & 0xff)); 593 /* enable read mode */ 594 ag71xx_wr(ag, AG71XX_REG_MII_CMD, MII_CMD_READ); 595 596 err = ag71xx_mdio_wait_busy(ag); 597 if (err) 598 return err; 599 600 val = ag71xx_rr(ag, AG71XX_REG_MII_STATUS); 601 /* disable read mode */ 602 ag71xx_wr(ag, AG71XX_REG_MII_CMD, 0); 603 604 netif_dbg(ag, link, ag->ndev, "mii_read: addr=%04x, reg=%04x, value=%04x\n", 605 addr, reg, val); 606 607 return val; 608 } 609 610 static int ag71xx_mdio_mii_write(struct mii_bus *bus, int addr, int reg, 611 u16 val) 612 { 613 struct ag71xx *ag = bus->priv; 614 615 netif_dbg(ag, link, ag->ndev, "mii_write: addr=%04x, reg=%04x, value=%04x\n", 616 addr, reg, val); 617 618 ag71xx_wr(ag, AG71XX_REG_MII_ADDR, 619 ((addr & 0x1f) << MII_ADDR_SHIFT) | (reg & 0xff)); 620 ag71xx_wr(ag, AG71XX_REG_MII_CTRL, val); 621 622 return ag71xx_mdio_wait_busy(ag); 623 } 624 625 static const u32 ar71xx_mdio_div_table[] = { 626 4, 4, 6, 8, 10, 14, 20, 28, 627 }; 628 629 static const u32 ar7240_mdio_div_table[] = { 630 2, 2, 4, 6, 8, 12, 18, 26, 32, 40, 48, 56, 62, 70, 78, 96, 631 }; 632 633 static const u32 ar933x_mdio_div_table[] = { 634 4, 4, 6, 8, 10, 14, 20, 28, 34, 42, 50, 58, 66, 74, 82, 98, 635 }; 636 637 static int ag71xx_mdio_get_divider(struct ag71xx *ag, u32 *div) 638 { 639 unsigned long ref_clock; 640 const u32 *table; 641 int ndivs, i; 642 643 ref_clock = clk_get_rate(ag->clk_mdio); 644 if (!ref_clock) 645 return -EINVAL; 646 647 if (ag71xx_is(ag, AR9330) || ag71xx_is(ag, AR9340)) { 648 table = ar933x_mdio_div_table; 649 ndivs = ARRAY_SIZE(ar933x_mdio_div_table); 650 } else if (ag71xx_is(ag, AR7240)) { 651 table = ar7240_mdio_div_table; 652 ndivs = ARRAY_SIZE(ar7240_mdio_div_table); 653 } else { 654 table = ar71xx_mdio_div_table; 655 ndivs = ARRAY_SIZE(ar71xx_mdio_div_table); 656 } 657 658 for (i = 0; i < ndivs; i++) { 659 unsigned long t; 660 661 t = ref_clock / table[i]; 662 if (t <= AG71XX_MDIO_MAX_CLK) { 663 *div = i; 664 return 0; 665 } 666 } 667 668 return -ENOENT; 669 } 670 671 static int ag71xx_mdio_reset(struct mii_bus *bus) 672 { 673 struct ag71xx *ag = bus->priv; 674 int err; 675 u32 t; 676 677 err = ag71xx_mdio_get_divider(ag, &t); 678 if (err) 679 return err; 680 681 ag71xx_wr(ag, AG71XX_REG_MII_CFG, t | MII_CFG_RESET); 682 usleep_range(100, 200); 683 684 ag71xx_wr(ag, AG71XX_REG_MII_CFG, t); 685 usleep_range(100, 200); 686 687 return 0; 688 } 689 690 static int ag71xx_mdio_probe(struct ag71xx *ag) 691 { 692 struct device *dev = &ag->pdev->dev; 693 struct net_device *ndev = ag->ndev; 694 static struct mii_bus *mii_bus; 695 struct device_node *np, *mnp; 696 int err; 697 698 np = dev->of_node; 699 700 ag->clk_mdio = devm_clk_get_enabled(dev, "mdio"); 701 if (IS_ERR(ag->clk_mdio)) { 702 netif_err(ag, probe, ndev, "Failed to get mdio clk.\n"); 703 return PTR_ERR(ag->clk_mdio); 704 } 705 706 mii_bus = devm_mdiobus_alloc(dev); 707 if (!mii_bus) 708 return -ENOMEM; 709 710 ag->mdio_reset = of_reset_control_get_exclusive(np, "mdio"); 711 if (IS_ERR(ag->mdio_reset)) { 712 netif_err(ag, probe, ndev, "Failed to get reset mdio.\n"); 713 return PTR_ERR(ag->mdio_reset); 714 } 715 716 mii_bus->name = "ag71xx_mdio"; 717 mii_bus->read = ag71xx_mdio_mii_read; 718 mii_bus->write = ag71xx_mdio_mii_write; 719 mii_bus->reset = ag71xx_mdio_reset; 720 mii_bus->priv = ag; 721 mii_bus->parent = dev; 722 snprintf(mii_bus->id, MII_BUS_ID_SIZE, "%s.%d", np->name, ag->mac_idx); 723 724 if (!IS_ERR(ag->mdio_reset)) { 725 reset_control_assert(ag->mdio_reset); 726 msleep(100); 727 reset_control_deassert(ag->mdio_reset); 728 msleep(200); 729 } 730 731 mnp = of_get_child_by_name(np, "mdio"); 732 err = devm_of_mdiobus_register(dev, mii_bus, mnp); 733 of_node_put(mnp); 734 if (err) 735 return err; 736 737 return 0; 738 } 739 740 static void ag71xx_hw_stop(struct ag71xx *ag) 741 { 742 /* disable all interrupts and stop the rx/tx engine */ 743 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0); 744 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0); 745 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0); 746 } 747 748 static bool ag71xx_check_dma_stuck(struct ag71xx *ag) 749 { 750 unsigned long timestamp; 751 u32 rx_sm, tx_sm, rx_fd; 752 753 timestamp = READ_ONCE(netdev_get_tx_queue(ag->ndev, 0)->trans_start); 754 if (likely(time_before(jiffies, timestamp + HZ / 10))) 755 return false; 756 757 if (!netif_carrier_ok(ag->ndev)) 758 return false; 759 760 rx_sm = ag71xx_rr(ag, AG71XX_REG_RX_SM); 761 if ((rx_sm & 0x7) == 0x3 && ((rx_sm >> 4) & 0x7) == 0x6) 762 return true; 763 764 tx_sm = ag71xx_rr(ag, AG71XX_REG_TX_SM); 765 rx_fd = ag71xx_rr(ag, AG71XX_REG_FIFO_DEPTH); 766 if (((tx_sm >> 4) & 0x7) == 0 && ((rx_sm & 0x7) == 0) && 767 ((rx_sm >> 4) & 0x7) == 0 && rx_fd == 0) 768 return true; 769 770 return false; 771 } 772 773 static int ag71xx_tx_packets(struct ag71xx *ag, bool flush, int budget) 774 { 775 struct ag71xx_ring *ring = &ag->tx_ring; 776 int sent = 0, bytes_compl = 0, n = 0; 777 struct net_device *ndev = ag->ndev; 778 int ring_mask, ring_size; 779 bool dma_stuck = false; 780 781 ring_mask = BIT(ring->order) - 1; 782 ring_size = BIT(ring->order); 783 784 netif_dbg(ag, tx_queued, ndev, "processing TX ring\n"); 785 786 while (ring->dirty + n != ring->curr) { 787 struct ag71xx_desc *desc; 788 struct sk_buff *skb; 789 unsigned int i; 790 791 i = (ring->dirty + n) & ring_mask; 792 desc = ag71xx_ring_desc(ring, i); 793 skb = ring->buf[i].tx.skb; 794 795 if (!flush && !ag71xx_desc_empty(desc)) { 796 if (ag->dcfg->tx_hang_workaround && 797 ag71xx_check_dma_stuck(ag)) { 798 schedule_delayed_work(&ag->restart_work, 799 HZ / 2); 800 dma_stuck = true; 801 } 802 break; 803 } 804 805 if (flush) 806 desc->ctrl |= DESC_EMPTY; 807 808 n++; 809 if (!skb) 810 continue; 811 812 napi_consume_skb(skb, budget); 813 ring->buf[i].tx.skb = NULL; 814 815 bytes_compl += ring->buf[i].tx.len; 816 817 sent++; 818 ring->dirty += n; 819 820 while (n > 0) { 821 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS); 822 n--; 823 } 824 } 825 826 netif_dbg(ag, tx_done, ndev, "%d packets sent out\n", sent); 827 828 if (!sent) 829 return 0; 830 831 ag->ndev->stats.tx_bytes += bytes_compl; 832 ag->ndev->stats.tx_packets += sent; 833 834 netdev_completed_queue(ag->ndev, sent, bytes_compl); 835 if ((ring->curr - ring->dirty) < (ring_size * 3) / 4) 836 netif_wake_queue(ag->ndev); 837 838 if (!dma_stuck) 839 cancel_delayed_work(&ag->restart_work); 840 841 return sent; 842 } 843 844 static void ag71xx_dma_wait_stop(struct ag71xx *ag) 845 { 846 struct net_device *ndev = ag->ndev; 847 int i; 848 849 for (i = 0; i < AG71XX_DMA_RETRY; i++) { 850 u32 rx, tx; 851 852 mdelay(AG71XX_DMA_DELAY); 853 854 rx = ag71xx_rr(ag, AG71XX_REG_RX_CTRL) & RX_CTRL_RXE; 855 tx = ag71xx_rr(ag, AG71XX_REG_TX_CTRL) & TX_CTRL_TXE; 856 if (!rx && !tx) 857 return; 858 } 859 860 netif_err(ag, hw, ndev, "DMA stop operation timed out\n"); 861 } 862 863 static void ag71xx_dma_reset(struct ag71xx *ag) 864 { 865 struct net_device *ndev = ag->ndev; 866 u32 val; 867 int i; 868 869 /* stop RX and TX */ 870 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0); 871 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0); 872 873 /* give the hardware some time to really stop all rx/tx activity 874 * clearing the descriptors too early causes random memory corruption 875 */ 876 ag71xx_dma_wait_stop(ag); 877 878 /* clear descriptor addresses */ 879 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma); 880 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma); 881 882 /* clear pending RX/TX interrupts */ 883 for (i = 0; i < 256; i++) { 884 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR); 885 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS); 886 } 887 888 /* clear pending errors */ 889 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF); 890 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR); 891 892 val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS); 893 if (val) 894 netif_err(ag, hw, ndev, "unable to clear DMA Rx status: %08x\n", 895 val); 896 897 val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS); 898 899 /* mask out reserved bits */ 900 val &= ~0xff000000; 901 902 if (val) 903 netif_err(ag, hw, ndev, "unable to clear DMA Tx status: %08x\n", 904 val); 905 } 906 907 static void ag71xx_hw_setup(struct ag71xx *ag) 908 { 909 u32 init = MAC_CFG1_INIT; 910 911 /* setup MAC configuration registers */ 912 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, init); 913 914 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2, 915 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK); 916 917 /* setup max frame length to zero */ 918 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, 0); 919 920 /* setup FIFO configuration registers */ 921 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT); 922 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, ag->fifodata[0]); 923 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, ag->fifodata[1]); 924 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT); 925 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT); 926 } 927 928 static unsigned int ag71xx_max_frame_len(unsigned int mtu) 929 { 930 return ETH_HLEN + VLAN_HLEN + mtu + ETH_FCS_LEN; 931 } 932 933 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, const unsigned char *mac) 934 { 935 u32 t; 936 937 t = (((u32)mac[5]) << 24) | (((u32)mac[4]) << 16) 938 | (((u32)mac[3]) << 8) | ((u32)mac[2]); 939 940 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t); 941 942 t = (((u32)mac[1]) << 24) | (((u32)mac[0]) << 16); 943 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t); 944 } 945 946 static void ag71xx_fast_reset(struct ag71xx *ag) 947 { 948 struct net_device *dev = ag->ndev; 949 u32 rx_ds; 950 u32 mii_reg; 951 952 ag71xx_hw_stop(ag); 953 954 mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG); 955 rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC); 956 957 ag71xx_tx_packets(ag, true, 0); 958 959 reset_control_assert(ag->mac_reset); 960 usleep_range(10, 20); 961 reset_control_deassert(ag->mac_reset); 962 usleep_range(10, 20); 963 964 ag71xx_dma_reset(ag); 965 ag71xx_hw_setup(ag); 966 ag->tx_ring.curr = 0; 967 ag->tx_ring.dirty = 0; 968 netdev_reset_queue(ag->ndev); 969 970 /* setup max frame length */ 971 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, 972 ag71xx_max_frame_len(ag->ndev->mtu)); 973 974 ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds); 975 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma); 976 ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg); 977 978 ag71xx_hw_set_macaddr(ag, dev->dev_addr); 979 } 980 981 static void ag71xx_hw_start(struct ag71xx *ag) 982 { 983 /* start RX engine */ 984 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE); 985 986 /* enable interrupts */ 987 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT); 988 989 netif_wake_queue(ag->ndev); 990 } 991 992 static void ag71xx_mac_config(struct phylink_config *config, unsigned int mode, 993 const struct phylink_link_state *state) 994 { 995 struct ag71xx *ag = netdev_priv(to_net_dev(config->dev)); 996 997 if (phylink_autoneg_inband(mode)) 998 return; 999 1000 if (!ag71xx_is(ag, AR7100) && !ag71xx_is(ag, AR9130)) 1001 ag71xx_fast_reset(ag); 1002 1003 if (ag->tx_ring.desc_split) { 1004 ag->fifodata[2] &= 0xffff; 1005 ag->fifodata[2] |= ((2048 - ag->tx_ring.desc_split) / 4) << 16; 1006 } 1007 1008 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, ag->fifodata[2]); 1009 } 1010 1011 static void ag71xx_mac_link_down(struct phylink_config *config, 1012 unsigned int mode, phy_interface_t interface) 1013 { 1014 struct ag71xx *ag = netdev_priv(to_net_dev(config->dev)); 1015 1016 ag71xx_hw_stop(ag); 1017 } 1018 1019 static void ag71xx_mac_link_up(struct phylink_config *config, 1020 struct phy_device *phy, 1021 unsigned int mode, phy_interface_t interface, 1022 int speed, int duplex, 1023 bool tx_pause, bool rx_pause) 1024 { 1025 struct ag71xx *ag = netdev_priv(to_net_dev(config->dev)); 1026 u32 cfg1, cfg2; 1027 u32 ifctl; 1028 u32 fifo5; 1029 1030 cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2); 1031 cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX); 1032 cfg2 |= duplex ? MAC_CFG2_FDX : 0; 1033 1034 ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL); 1035 ifctl &= ~(MAC_IFCTL_SPEED); 1036 1037 fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5); 1038 fifo5 &= ~FIFO_CFG5_BM; 1039 1040 switch (speed) { 1041 case SPEED_1000: 1042 cfg2 |= MAC_CFG2_IF_1000; 1043 fifo5 |= FIFO_CFG5_BM; 1044 break; 1045 case SPEED_100: 1046 cfg2 |= MAC_CFG2_IF_10_100; 1047 ifctl |= MAC_IFCTL_SPEED; 1048 break; 1049 case SPEED_10: 1050 cfg2 |= MAC_CFG2_IF_10_100; 1051 break; 1052 default: 1053 return; 1054 } 1055 1056 ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2); 1057 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5); 1058 ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl); 1059 1060 cfg1 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG1); 1061 cfg1 &= ~(MAC_CFG1_TFC | MAC_CFG1_RFC); 1062 if (tx_pause) 1063 cfg1 |= MAC_CFG1_TFC; 1064 1065 if (rx_pause) 1066 cfg1 |= MAC_CFG1_RFC; 1067 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, cfg1); 1068 1069 ag71xx_hw_start(ag); 1070 } 1071 1072 static const struct phylink_mac_ops ag71xx_phylink_mac_ops = { 1073 .mac_config = ag71xx_mac_config, 1074 .mac_link_down = ag71xx_mac_link_down, 1075 .mac_link_up = ag71xx_mac_link_up, 1076 }; 1077 1078 static int ag71xx_phylink_setup(struct ag71xx *ag) 1079 { 1080 struct phylink *phylink; 1081 1082 ag->phylink_config.dev = &ag->ndev->dev; 1083 ag->phylink_config.type = PHYLINK_NETDEV; 1084 ag->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE | 1085 MAC_10 | MAC_100 | MAC_1000FD; 1086 1087 if ((ag71xx_is(ag, AR9330) && ag->mac_idx == 0) || 1088 ag71xx_is(ag, AR9340) || 1089 ag71xx_is(ag, QCA9530) || 1090 (ag71xx_is(ag, QCA9550) && ag->mac_idx == 1)) 1091 __set_bit(PHY_INTERFACE_MODE_MII, 1092 ag->phylink_config.supported_interfaces); 1093 1094 if ((ag71xx_is(ag, AR9330) && ag->mac_idx == 1) || 1095 (ag71xx_is(ag, AR9340) && ag->mac_idx == 1) || 1096 (ag71xx_is(ag, QCA9530) && ag->mac_idx == 1)) 1097 __set_bit(PHY_INTERFACE_MODE_GMII, 1098 ag->phylink_config.supported_interfaces); 1099 1100 if (ag71xx_is(ag, QCA9550) && ag->mac_idx == 0) 1101 __set_bit(PHY_INTERFACE_MODE_SGMII, 1102 ag->phylink_config.supported_interfaces); 1103 1104 if (ag71xx_is(ag, AR9340) && ag->mac_idx == 0) 1105 __set_bit(PHY_INTERFACE_MODE_RMII, 1106 ag->phylink_config.supported_interfaces); 1107 1108 if ((ag71xx_is(ag, AR9340) && ag->mac_idx == 0) || 1109 (ag71xx_is(ag, QCA9550) && ag->mac_idx == 1)) 1110 __set_bit(PHY_INTERFACE_MODE_RGMII, 1111 ag->phylink_config.supported_interfaces); 1112 1113 phylink = phylink_create(&ag->phylink_config, ag->pdev->dev.fwnode, 1114 ag->phy_if_mode, &ag71xx_phylink_mac_ops); 1115 if (IS_ERR(phylink)) 1116 return PTR_ERR(phylink); 1117 1118 ag->phylink = phylink; 1119 return 0; 1120 } 1121 1122 static void ag71xx_ring_tx_clean(struct ag71xx *ag) 1123 { 1124 struct ag71xx_ring *ring = &ag->tx_ring; 1125 int ring_mask = BIT(ring->order) - 1; 1126 u32 bytes_compl = 0, pkts_compl = 0; 1127 struct net_device *ndev = ag->ndev; 1128 1129 while (ring->curr != ring->dirty) { 1130 struct ag71xx_desc *desc; 1131 u32 i = ring->dirty & ring_mask; 1132 1133 desc = ag71xx_ring_desc(ring, i); 1134 if (!ag71xx_desc_empty(desc)) { 1135 desc->ctrl = 0; 1136 ndev->stats.tx_errors++; 1137 } 1138 1139 if (ring->buf[i].tx.skb) { 1140 bytes_compl += ring->buf[i].tx.len; 1141 pkts_compl++; 1142 dev_kfree_skb_any(ring->buf[i].tx.skb); 1143 } 1144 ring->buf[i].tx.skb = NULL; 1145 ring->dirty++; 1146 } 1147 1148 /* flush descriptors */ 1149 wmb(); 1150 1151 netdev_completed_queue(ndev, pkts_compl, bytes_compl); 1152 } 1153 1154 static void ag71xx_ring_tx_init(struct ag71xx *ag) 1155 { 1156 struct ag71xx_ring *ring = &ag->tx_ring; 1157 int ring_size = BIT(ring->order); 1158 int ring_mask = ring_size - 1; 1159 int i; 1160 1161 for (i = 0; i < ring_size; i++) { 1162 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i); 1163 1164 desc->next = (u32)(ring->descs_dma + 1165 AG71XX_DESC_SIZE * ((i + 1) & ring_mask)); 1166 1167 desc->ctrl = DESC_EMPTY; 1168 ring->buf[i].tx.skb = NULL; 1169 } 1170 1171 /* flush descriptors */ 1172 wmb(); 1173 1174 ring->curr = 0; 1175 ring->dirty = 0; 1176 netdev_reset_queue(ag->ndev); 1177 } 1178 1179 static void ag71xx_ring_rx_clean(struct ag71xx *ag) 1180 { 1181 struct ag71xx_ring *ring = &ag->rx_ring; 1182 int ring_size = BIT(ring->order); 1183 int i; 1184 1185 if (!ring->buf) 1186 return; 1187 1188 for (i = 0; i < ring_size; i++) 1189 if (ring->buf[i].rx.rx_buf) { 1190 dma_unmap_single(&ag->pdev->dev, 1191 ring->buf[i].rx.dma_addr, 1192 ag->rx_buf_size, DMA_FROM_DEVICE); 1193 skb_free_frag(ring->buf[i].rx.rx_buf); 1194 } 1195 } 1196 1197 static int ag71xx_buffer_size(struct ag71xx *ag) 1198 { 1199 return ag->rx_buf_size + 1200 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 1201 } 1202 1203 static bool ag71xx_fill_rx_buf(struct ag71xx *ag, struct ag71xx_buf *buf, 1204 int offset, 1205 void *(*alloc)(unsigned int size)) 1206 { 1207 struct ag71xx_ring *ring = &ag->rx_ring; 1208 struct ag71xx_desc *desc; 1209 void *data; 1210 1211 desc = ag71xx_ring_desc(ring, buf - &ring->buf[0]); 1212 1213 data = alloc(ag71xx_buffer_size(ag)); 1214 if (!data) 1215 return false; 1216 1217 buf->rx.rx_buf = data; 1218 buf->rx.dma_addr = dma_map_single(&ag->pdev->dev, data, ag->rx_buf_size, 1219 DMA_FROM_DEVICE); 1220 desc->data = (u32)buf->rx.dma_addr + offset; 1221 return true; 1222 } 1223 1224 static int ag71xx_ring_rx_init(struct ag71xx *ag) 1225 { 1226 struct ag71xx_ring *ring = &ag->rx_ring; 1227 struct net_device *ndev = ag->ndev; 1228 int ring_mask = BIT(ring->order) - 1; 1229 int ring_size = BIT(ring->order); 1230 unsigned int i; 1231 int ret; 1232 1233 ret = 0; 1234 for (i = 0; i < ring_size; i++) { 1235 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i); 1236 1237 desc->next = (u32)(ring->descs_dma + 1238 AG71XX_DESC_SIZE * ((i + 1) & ring_mask)); 1239 1240 netif_dbg(ag, rx_status, ndev, "RX desc at %p, next is %08x\n", 1241 desc, desc->next); 1242 } 1243 1244 for (i = 0; i < ring_size; i++) { 1245 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i); 1246 1247 if (!ag71xx_fill_rx_buf(ag, &ring->buf[i], ag->rx_buf_offset, 1248 netdev_alloc_frag)) { 1249 ret = -ENOMEM; 1250 break; 1251 } 1252 1253 desc->ctrl = DESC_EMPTY; 1254 } 1255 1256 /* flush descriptors */ 1257 wmb(); 1258 1259 ring->curr = 0; 1260 ring->dirty = 0; 1261 1262 return ret; 1263 } 1264 1265 static int ag71xx_ring_rx_refill(struct ag71xx *ag) 1266 { 1267 struct ag71xx_ring *ring = &ag->rx_ring; 1268 int ring_mask = BIT(ring->order) - 1; 1269 int offset = ag->rx_buf_offset; 1270 unsigned int count; 1271 1272 count = 0; 1273 for (; ring->curr - ring->dirty > 0; ring->dirty++) { 1274 struct ag71xx_desc *desc; 1275 unsigned int i; 1276 1277 i = ring->dirty & ring_mask; 1278 desc = ag71xx_ring_desc(ring, i); 1279 1280 if (!ring->buf[i].rx.rx_buf && 1281 !ag71xx_fill_rx_buf(ag, &ring->buf[i], offset, 1282 napi_alloc_frag)) 1283 break; 1284 1285 desc->ctrl = DESC_EMPTY; 1286 count++; 1287 } 1288 1289 /* flush descriptors */ 1290 wmb(); 1291 1292 netif_dbg(ag, rx_status, ag->ndev, "%u rx descriptors refilled\n", 1293 count); 1294 1295 return count; 1296 } 1297 1298 static int ag71xx_rings_init(struct ag71xx *ag) 1299 { 1300 struct ag71xx_ring *tx = &ag->tx_ring; 1301 struct ag71xx_ring *rx = &ag->rx_ring; 1302 int ring_size, tx_size; 1303 1304 ring_size = BIT(tx->order) + BIT(rx->order); 1305 tx_size = BIT(tx->order); 1306 1307 tx->buf = kcalloc(ring_size, sizeof(*tx->buf), GFP_KERNEL); 1308 if (!tx->buf) 1309 return -ENOMEM; 1310 1311 tx->descs_cpu = dma_alloc_coherent(&ag->pdev->dev, 1312 ring_size * AG71XX_DESC_SIZE, 1313 &tx->descs_dma, GFP_KERNEL); 1314 if (!tx->descs_cpu) { 1315 kfree(tx->buf); 1316 tx->buf = NULL; 1317 return -ENOMEM; 1318 } 1319 1320 rx->buf = &tx->buf[tx_size]; 1321 rx->descs_cpu = ((void *)tx->descs_cpu) + tx_size * AG71XX_DESC_SIZE; 1322 rx->descs_dma = tx->descs_dma + tx_size * AG71XX_DESC_SIZE; 1323 1324 ag71xx_ring_tx_init(ag); 1325 return ag71xx_ring_rx_init(ag); 1326 } 1327 1328 static void ag71xx_rings_free(struct ag71xx *ag) 1329 { 1330 struct ag71xx_ring *tx = &ag->tx_ring; 1331 struct ag71xx_ring *rx = &ag->rx_ring; 1332 int ring_size; 1333 1334 ring_size = BIT(tx->order) + BIT(rx->order); 1335 1336 if (tx->descs_cpu) 1337 dma_free_coherent(&ag->pdev->dev, ring_size * AG71XX_DESC_SIZE, 1338 tx->descs_cpu, tx->descs_dma); 1339 1340 kfree(tx->buf); 1341 1342 tx->descs_cpu = NULL; 1343 rx->descs_cpu = NULL; 1344 tx->buf = NULL; 1345 rx->buf = NULL; 1346 } 1347 1348 static void ag71xx_rings_cleanup(struct ag71xx *ag) 1349 { 1350 ag71xx_ring_rx_clean(ag); 1351 ag71xx_ring_tx_clean(ag); 1352 ag71xx_rings_free(ag); 1353 1354 netdev_reset_queue(ag->ndev); 1355 } 1356 1357 static void ag71xx_hw_init(struct ag71xx *ag) 1358 { 1359 ag71xx_hw_stop(ag); 1360 1361 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR); 1362 usleep_range(20, 30); 1363 1364 reset_control_assert(ag->mac_reset); 1365 msleep(100); 1366 reset_control_deassert(ag->mac_reset); 1367 msleep(200); 1368 1369 ag71xx_hw_setup(ag); 1370 1371 ag71xx_dma_reset(ag); 1372 } 1373 1374 static int ag71xx_hw_enable(struct ag71xx *ag) 1375 { 1376 int ret; 1377 1378 ret = ag71xx_rings_init(ag); 1379 if (ret) 1380 return ret; 1381 1382 napi_enable(&ag->napi); 1383 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma); 1384 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma); 1385 netif_start_queue(ag->ndev); 1386 1387 return 0; 1388 } 1389 1390 static void ag71xx_hw_disable(struct ag71xx *ag) 1391 { 1392 netif_stop_queue(ag->ndev); 1393 1394 ag71xx_hw_stop(ag); 1395 ag71xx_dma_reset(ag); 1396 1397 napi_disable(&ag->napi); 1398 del_timer_sync(&ag->oom_timer); 1399 1400 ag71xx_rings_cleanup(ag); 1401 } 1402 1403 static int ag71xx_open(struct net_device *ndev) 1404 { 1405 struct ag71xx *ag = netdev_priv(ndev); 1406 unsigned int max_frame_len; 1407 int ret; 1408 1409 ret = phylink_of_phy_connect(ag->phylink, ag->pdev->dev.of_node, 0); 1410 if (ret) { 1411 netif_err(ag, link, ndev, "phylink_of_phy_connect filed with err: %i\n", 1412 ret); 1413 return ret; 1414 } 1415 1416 max_frame_len = ag71xx_max_frame_len(ndev->mtu); 1417 ag->rx_buf_size = 1418 SKB_DATA_ALIGN(max_frame_len + NET_SKB_PAD + NET_IP_ALIGN); 1419 1420 /* setup max frame length */ 1421 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, max_frame_len); 1422 ag71xx_hw_set_macaddr(ag, ndev->dev_addr); 1423 1424 ret = ag71xx_hw_enable(ag); 1425 if (ret) 1426 goto err; 1427 1428 phylink_start(ag->phylink); 1429 1430 return 0; 1431 1432 err: 1433 ag71xx_rings_cleanup(ag); 1434 phylink_disconnect_phy(ag->phylink); 1435 return ret; 1436 } 1437 1438 static int ag71xx_stop(struct net_device *ndev) 1439 { 1440 struct ag71xx *ag = netdev_priv(ndev); 1441 1442 phylink_stop(ag->phylink); 1443 phylink_disconnect_phy(ag->phylink); 1444 ag71xx_hw_disable(ag); 1445 1446 return 0; 1447 } 1448 1449 static int ag71xx_fill_dma_desc(struct ag71xx_ring *ring, u32 addr, int len) 1450 { 1451 int i, ring_mask, ndesc, split; 1452 struct ag71xx_desc *desc; 1453 1454 ring_mask = BIT(ring->order) - 1; 1455 ndesc = 0; 1456 split = ring->desc_split; 1457 1458 if (!split) 1459 split = len; 1460 1461 while (len > 0) { 1462 unsigned int cur_len = len; 1463 1464 i = (ring->curr + ndesc) & ring_mask; 1465 desc = ag71xx_ring_desc(ring, i); 1466 1467 if (!ag71xx_desc_empty(desc)) 1468 return -1; 1469 1470 if (cur_len > split) { 1471 cur_len = split; 1472 1473 /* TX will hang if DMA transfers <= 4 bytes, 1474 * make sure next segment is more than 4 bytes long. 1475 */ 1476 if (len <= split + 4) 1477 cur_len -= 4; 1478 } 1479 1480 desc->data = addr; 1481 addr += cur_len; 1482 len -= cur_len; 1483 1484 if (len > 0) 1485 cur_len |= DESC_MORE; 1486 1487 /* prevent early tx attempt of this descriptor */ 1488 if (!ndesc) 1489 cur_len |= DESC_EMPTY; 1490 1491 desc->ctrl = cur_len; 1492 ndesc++; 1493 } 1494 1495 return ndesc; 1496 } 1497 1498 static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb, 1499 struct net_device *ndev) 1500 { 1501 int i, n, ring_min, ring_mask, ring_size; 1502 struct ag71xx *ag = netdev_priv(ndev); 1503 struct ag71xx_ring *ring; 1504 struct ag71xx_desc *desc; 1505 dma_addr_t dma_addr; 1506 1507 ring = &ag->tx_ring; 1508 ring_mask = BIT(ring->order) - 1; 1509 ring_size = BIT(ring->order); 1510 1511 if (skb->len <= 4) { 1512 netif_dbg(ag, tx_err, ndev, "packet len is too small\n"); 1513 goto err_drop; 1514 } 1515 1516 dma_addr = dma_map_single(&ag->pdev->dev, skb->data, skb->len, 1517 DMA_TO_DEVICE); 1518 1519 i = ring->curr & ring_mask; 1520 desc = ag71xx_ring_desc(ring, i); 1521 1522 /* setup descriptor fields */ 1523 n = ag71xx_fill_dma_desc(ring, (u32)dma_addr, 1524 skb->len & ag->dcfg->desc_pktlen_mask); 1525 if (n < 0) 1526 goto err_drop_unmap; 1527 1528 i = (ring->curr + n - 1) & ring_mask; 1529 ring->buf[i].tx.len = skb->len; 1530 ring->buf[i].tx.skb = skb; 1531 1532 netdev_sent_queue(ndev, skb->len); 1533 1534 skb_tx_timestamp(skb); 1535 1536 desc->ctrl &= ~DESC_EMPTY; 1537 ring->curr += n; 1538 1539 /* flush descriptor */ 1540 wmb(); 1541 1542 ring_min = 2; 1543 if (ring->desc_split) 1544 ring_min *= AG71XX_TX_RING_DS_PER_PKT; 1545 1546 if (ring->curr - ring->dirty >= ring_size - ring_min) { 1547 netif_dbg(ag, tx_err, ndev, "tx queue full\n"); 1548 netif_stop_queue(ndev); 1549 } 1550 1551 netif_dbg(ag, tx_queued, ndev, "packet injected into TX queue\n"); 1552 1553 /* enable TX engine */ 1554 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE); 1555 1556 return NETDEV_TX_OK; 1557 1558 err_drop_unmap: 1559 dma_unmap_single(&ag->pdev->dev, dma_addr, skb->len, DMA_TO_DEVICE); 1560 1561 err_drop: 1562 ndev->stats.tx_dropped++; 1563 1564 dev_kfree_skb(skb); 1565 return NETDEV_TX_OK; 1566 } 1567 1568 static void ag71xx_oom_timer_handler(struct timer_list *t) 1569 { 1570 struct ag71xx *ag = from_timer(ag, t, oom_timer); 1571 1572 napi_schedule(&ag->napi); 1573 } 1574 1575 static void ag71xx_tx_timeout(struct net_device *ndev, unsigned int txqueue) 1576 { 1577 struct ag71xx *ag = netdev_priv(ndev); 1578 1579 netif_err(ag, tx_err, ndev, "tx timeout\n"); 1580 1581 schedule_delayed_work(&ag->restart_work, 1); 1582 } 1583 1584 static void ag71xx_restart_work_func(struct work_struct *work) 1585 { 1586 struct ag71xx *ag = container_of(work, struct ag71xx, 1587 restart_work.work); 1588 1589 rtnl_lock(); 1590 ag71xx_hw_disable(ag); 1591 ag71xx_hw_enable(ag); 1592 1593 phylink_stop(ag->phylink); 1594 phylink_start(ag->phylink); 1595 1596 rtnl_unlock(); 1597 } 1598 1599 static int ag71xx_rx_packets(struct ag71xx *ag, int limit) 1600 { 1601 struct net_device *ndev = ag->ndev; 1602 int ring_mask, ring_size, done = 0; 1603 unsigned int pktlen_mask, offset; 1604 struct ag71xx_ring *ring; 1605 struct list_head rx_list; 1606 struct sk_buff *skb; 1607 1608 ring = &ag->rx_ring; 1609 pktlen_mask = ag->dcfg->desc_pktlen_mask; 1610 offset = ag->rx_buf_offset; 1611 ring_mask = BIT(ring->order) - 1; 1612 ring_size = BIT(ring->order); 1613 1614 netif_dbg(ag, rx_status, ndev, "rx packets, limit=%d, curr=%u, dirty=%u\n", 1615 limit, ring->curr, ring->dirty); 1616 1617 INIT_LIST_HEAD(&rx_list); 1618 1619 while (done < limit) { 1620 unsigned int i = ring->curr & ring_mask; 1621 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i); 1622 int pktlen; 1623 int err = 0; 1624 1625 if (ag71xx_desc_empty(desc)) 1626 break; 1627 1628 if ((ring->dirty + ring_size) == ring->curr) { 1629 WARN_ONCE(1, "RX out of ring"); 1630 break; 1631 } 1632 1633 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR); 1634 1635 pktlen = desc->ctrl & pktlen_mask; 1636 pktlen -= ETH_FCS_LEN; 1637 1638 dma_unmap_single(&ag->pdev->dev, ring->buf[i].rx.dma_addr, 1639 ag->rx_buf_size, DMA_FROM_DEVICE); 1640 1641 ndev->stats.rx_packets++; 1642 ndev->stats.rx_bytes += pktlen; 1643 1644 skb = napi_build_skb(ring->buf[i].rx.rx_buf, ag71xx_buffer_size(ag)); 1645 if (!skb) { 1646 skb_free_frag(ring->buf[i].rx.rx_buf); 1647 goto next; 1648 } 1649 1650 skb_reserve(skb, offset); 1651 skb_put(skb, pktlen); 1652 1653 if (err) { 1654 ndev->stats.rx_dropped++; 1655 kfree_skb(skb); 1656 } else { 1657 skb->dev = ndev; 1658 skb->ip_summed = CHECKSUM_NONE; 1659 list_add_tail(&skb->list, &rx_list); 1660 } 1661 1662 next: 1663 ring->buf[i].rx.rx_buf = NULL; 1664 done++; 1665 1666 ring->curr++; 1667 } 1668 1669 ag71xx_ring_rx_refill(ag); 1670 1671 list_for_each_entry(skb, &rx_list, list) 1672 skb->protocol = eth_type_trans(skb, ndev); 1673 netif_receive_skb_list(&rx_list); 1674 1675 netif_dbg(ag, rx_status, ndev, "rx finish, curr=%u, dirty=%u, done=%d\n", 1676 ring->curr, ring->dirty, done); 1677 1678 return done; 1679 } 1680 1681 static int ag71xx_poll(struct napi_struct *napi, int limit) 1682 { 1683 struct ag71xx *ag = container_of(napi, struct ag71xx, napi); 1684 struct ag71xx_ring *rx_ring = &ag->rx_ring; 1685 int rx_ring_size = BIT(rx_ring->order); 1686 struct net_device *ndev = ag->ndev; 1687 int tx_done, rx_done; 1688 u32 status; 1689 1690 tx_done = ag71xx_tx_packets(ag, false, limit); 1691 1692 netif_dbg(ag, rx_status, ndev, "processing RX ring\n"); 1693 rx_done = ag71xx_rx_packets(ag, limit); 1694 1695 if (!rx_ring->buf[rx_ring->dirty % rx_ring_size].rx.rx_buf) 1696 goto oom; 1697 1698 status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS); 1699 if (unlikely(status & RX_STATUS_OF)) { 1700 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF); 1701 ndev->stats.rx_fifo_errors++; 1702 1703 /* restart RX */ 1704 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE); 1705 } 1706 1707 if (rx_done < limit) { 1708 if (status & RX_STATUS_PR) 1709 goto more; 1710 1711 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS); 1712 if (status & TX_STATUS_PS) 1713 goto more; 1714 1715 netif_dbg(ag, rx_status, ndev, "disable polling mode, rx=%d, tx=%d,limit=%d\n", 1716 rx_done, tx_done, limit); 1717 1718 napi_complete(napi); 1719 1720 /* enable interrupts */ 1721 ag71xx_int_enable(ag, AG71XX_INT_POLL); 1722 return rx_done; 1723 } 1724 1725 more: 1726 netif_dbg(ag, rx_status, ndev, "stay in polling mode, rx=%d, tx=%d, limit=%d\n", 1727 rx_done, tx_done, limit); 1728 return limit; 1729 1730 oom: 1731 netif_err(ag, rx_err, ndev, "out of memory\n"); 1732 1733 mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL); 1734 napi_complete(napi); 1735 return 0; 1736 } 1737 1738 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id) 1739 { 1740 struct net_device *ndev = dev_id; 1741 struct ag71xx *ag; 1742 u32 status; 1743 1744 ag = netdev_priv(ndev); 1745 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS); 1746 1747 if (unlikely(!status)) 1748 return IRQ_NONE; 1749 1750 if (unlikely(status & AG71XX_INT_ERR)) { 1751 if (status & AG71XX_INT_TX_BE) { 1752 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE); 1753 netif_err(ag, intr, ndev, "TX BUS error\n"); 1754 } 1755 if (status & AG71XX_INT_RX_BE) { 1756 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE); 1757 netif_err(ag, intr, ndev, "RX BUS error\n"); 1758 } 1759 } 1760 1761 if (likely(status & AG71XX_INT_POLL)) { 1762 ag71xx_int_disable(ag, AG71XX_INT_POLL); 1763 netif_dbg(ag, intr, ndev, "enable polling mode\n"); 1764 napi_schedule(&ag->napi); 1765 } 1766 1767 return IRQ_HANDLED; 1768 } 1769 1770 static int ag71xx_change_mtu(struct net_device *ndev, int new_mtu) 1771 { 1772 struct ag71xx *ag = netdev_priv(ndev); 1773 1774 WRITE_ONCE(ndev->mtu, new_mtu); 1775 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, 1776 ag71xx_max_frame_len(ndev->mtu)); 1777 1778 return 0; 1779 } 1780 1781 static const struct net_device_ops ag71xx_netdev_ops = { 1782 .ndo_open = ag71xx_open, 1783 .ndo_stop = ag71xx_stop, 1784 .ndo_start_xmit = ag71xx_hard_start_xmit, 1785 .ndo_eth_ioctl = ag71xx_do_ioctl, 1786 .ndo_tx_timeout = ag71xx_tx_timeout, 1787 .ndo_change_mtu = ag71xx_change_mtu, 1788 .ndo_set_mac_address = eth_mac_addr, 1789 .ndo_validate_addr = eth_validate_addr, 1790 }; 1791 1792 static const u32 ar71xx_addr_ar7100[] = { 1793 0x19000000, 0x1a000000, 1794 }; 1795 1796 static int ag71xx_probe(struct platform_device *pdev) 1797 { 1798 struct device_node *np = pdev->dev.of_node; 1799 const struct ag71xx_dcfg *dcfg; 1800 struct net_device *ndev; 1801 struct resource *res; 1802 int tx_size, err, i; 1803 struct ag71xx *ag; 1804 1805 if (!np) 1806 return -ENODEV; 1807 1808 ndev = devm_alloc_etherdev(&pdev->dev, sizeof(*ag)); 1809 if (!ndev) 1810 return -ENOMEM; 1811 1812 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1813 if (!res) 1814 return -EINVAL; 1815 1816 dcfg = of_device_get_match_data(&pdev->dev); 1817 if (!dcfg) 1818 return -EINVAL; 1819 1820 ag = netdev_priv(ndev); 1821 ag->mac_idx = -1; 1822 for (i = 0; i < ARRAY_SIZE(ar71xx_addr_ar7100); i++) { 1823 if (ar71xx_addr_ar7100[i] == res->start) 1824 ag->mac_idx = i; 1825 } 1826 1827 if (ag->mac_idx < 0) { 1828 netif_err(ag, probe, ndev, "unknown mac idx\n"); 1829 return -EINVAL; 1830 } 1831 1832 ag->clk_eth = devm_clk_get_enabled(&pdev->dev, "eth"); 1833 if (IS_ERR(ag->clk_eth)) { 1834 netif_err(ag, probe, ndev, "Failed to get eth clk.\n"); 1835 return PTR_ERR(ag->clk_eth); 1836 } 1837 1838 SET_NETDEV_DEV(ndev, &pdev->dev); 1839 1840 ag->pdev = pdev; 1841 ag->ndev = ndev; 1842 ag->dcfg = dcfg; 1843 ag->msg_enable = netif_msg_init(-1, AG71XX_DEFAULT_MSG_ENABLE); 1844 memcpy(ag->fifodata, dcfg->fifodata, sizeof(ag->fifodata)); 1845 1846 ag->mac_reset = devm_reset_control_get(&pdev->dev, "mac"); 1847 if (IS_ERR(ag->mac_reset)) { 1848 netif_err(ag, probe, ndev, "missing mac reset\n"); 1849 return PTR_ERR(ag->mac_reset); 1850 } 1851 1852 ag->mac_base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); 1853 if (!ag->mac_base) 1854 return -ENOMEM; 1855 1856 ndev->irq = platform_get_irq(pdev, 0); 1857 err = devm_request_irq(&pdev->dev, ndev->irq, ag71xx_interrupt, 1858 0x0, dev_name(&pdev->dev), ndev); 1859 if (err) { 1860 netif_err(ag, probe, ndev, "unable to request IRQ %d\n", 1861 ndev->irq); 1862 return err; 1863 } 1864 1865 ndev->netdev_ops = &ag71xx_netdev_ops; 1866 ndev->ethtool_ops = &ag71xx_ethtool_ops; 1867 1868 INIT_DELAYED_WORK(&ag->restart_work, ag71xx_restart_work_func); 1869 timer_setup(&ag->oom_timer, ag71xx_oom_timer_handler, 0); 1870 1871 tx_size = AG71XX_TX_RING_SIZE_DEFAULT; 1872 ag->rx_ring.order = ag71xx_ring_size_order(AG71XX_RX_RING_SIZE_DEFAULT); 1873 1874 ndev->min_mtu = 68; 1875 ndev->max_mtu = dcfg->max_frame_len - ag71xx_max_frame_len(0); 1876 1877 ag->rx_buf_offset = NET_SKB_PAD; 1878 if (!ag71xx_is(ag, AR7100) && !ag71xx_is(ag, AR9130)) 1879 ag->rx_buf_offset += NET_IP_ALIGN; 1880 1881 if (ag71xx_is(ag, AR7100)) { 1882 ag->tx_ring.desc_split = AG71XX_TX_RING_SPLIT; 1883 tx_size *= AG71XX_TX_RING_DS_PER_PKT; 1884 } 1885 ag->tx_ring.order = ag71xx_ring_size_order(tx_size); 1886 1887 ag->stop_desc = dmam_alloc_coherent(&pdev->dev, 1888 sizeof(struct ag71xx_desc), 1889 &ag->stop_desc_dma, GFP_KERNEL); 1890 if (!ag->stop_desc) 1891 return -ENOMEM; 1892 1893 ag->stop_desc->data = 0; 1894 ag->stop_desc->ctrl = 0; 1895 ag->stop_desc->next = (u32)ag->stop_desc_dma; 1896 1897 err = of_get_ethdev_address(np, ndev); 1898 if (err) { 1899 netif_err(ag, probe, ndev, "invalid MAC address, using random address\n"); 1900 eth_hw_addr_random(ndev); 1901 } 1902 1903 err = of_get_phy_mode(np, &ag->phy_if_mode); 1904 if (err) { 1905 netif_err(ag, probe, ndev, "missing phy-mode property in DT\n"); 1906 return err; 1907 } 1908 1909 netif_napi_add_weight(ndev, &ag->napi, ag71xx_poll, 1910 AG71XX_NAPI_WEIGHT); 1911 1912 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, 0); 1913 1914 ag71xx_hw_init(ag); 1915 1916 err = ag71xx_mdio_probe(ag); 1917 if (err) 1918 return err; 1919 1920 platform_set_drvdata(pdev, ndev); 1921 1922 err = ag71xx_phylink_setup(ag); 1923 if (err) { 1924 netif_err(ag, probe, ndev, "failed to setup phylink (%d)\n", err); 1925 return err; 1926 } 1927 1928 err = devm_register_netdev(&pdev->dev, ndev); 1929 if (err) { 1930 netif_err(ag, probe, ndev, "unable to register net device\n"); 1931 platform_set_drvdata(pdev, NULL); 1932 return err; 1933 } 1934 1935 netif_info(ag, probe, ndev, "Atheros AG71xx at 0x%08lx, irq %d, mode:%s\n", 1936 (unsigned long)ag->mac_base, ndev->irq, 1937 phy_modes(ag->phy_if_mode)); 1938 1939 return 0; 1940 } 1941 1942 static const u32 ar71xx_fifo_ar7100[] = { 1943 0x0fff0000, 0x00001fff, 0x00780fff, 1944 }; 1945 1946 static const u32 ar71xx_fifo_ar9130[] = { 1947 0x0fff0000, 0x00001fff, 0x008001ff, 1948 }; 1949 1950 static const u32 ar71xx_fifo_ar9330[] = { 1951 0x0010ffff, 0x015500aa, 0x01f00140, 1952 }; 1953 1954 static const struct ag71xx_dcfg ag71xx_dcfg_ar7100 = { 1955 .type = AR7100, 1956 .fifodata = ar71xx_fifo_ar7100, 1957 .max_frame_len = 1540, 1958 .desc_pktlen_mask = SZ_4K - 1, 1959 .tx_hang_workaround = false, 1960 }; 1961 1962 static const struct ag71xx_dcfg ag71xx_dcfg_ar7240 = { 1963 .type = AR7240, 1964 .fifodata = ar71xx_fifo_ar7100, 1965 .max_frame_len = 1540, 1966 .desc_pktlen_mask = SZ_4K - 1, 1967 .tx_hang_workaround = true, 1968 }; 1969 1970 static const struct ag71xx_dcfg ag71xx_dcfg_ar9130 = { 1971 .type = AR9130, 1972 .fifodata = ar71xx_fifo_ar9130, 1973 .max_frame_len = 1540, 1974 .desc_pktlen_mask = SZ_4K - 1, 1975 .tx_hang_workaround = false, 1976 }; 1977 1978 static const struct ag71xx_dcfg ag71xx_dcfg_ar9330 = { 1979 .type = AR9330, 1980 .fifodata = ar71xx_fifo_ar9330, 1981 .max_frame_len = 1540, 1982 .desc_pktlen_mask = SZ_4K - 1, 1983 .tx_hang_workaround = true, 1984 }; 1985 1986 static const struct ag71xx_dcfg ag71xx_dcfg_ar9340 = { 1987 .type = AR9340, 1988 .fifodata = ar71xx_fifo_ar9330, 1989 .max_frame_len = SZ_16K - 1, 1990 .desc_pktlen_mask = SZ_16K - 1, 1991 .tx_hang_workaround = true, 1992 }; 1993 1994 static const struct ag71xx_dcfg ag71xx_dcfg_qca9530 = { 1995 .type = QCA9530, 1996 .fifodata = ar71xx_fifo_ar9330, 1997 .max_frame_len = SZ_16K - 1, 1998 .desc_pktlen_mask = SZ_16K - 1, 1999 .tx_hang_workaround = true, 2000 }; 2001 2002 static const struct ag71xx_dcfg ag71xx_dcfg_qca9550 = { 2003 .type = QCA9550, 2004 .fifodata = ar71xx_fifo_ar9330, 2005 .max_frame_len = 1540, 2006 .desc_pktlen_mask = SZ_16K - 1, 2007 .tx_hang_workaround = true, 2008 }; 2009 2010 static const struct of_device_id ag71xx_match[] = { 2011 { .compatible = "qca,ar7100-eth", .data = &ag71xx_dcfg_ar7100 }, 2012 { .compatible = "qca,ar7240-eth", .data = &ag71xx_dcfg_ar7240 }, 2013 { .compatible = "qca,ar7241-eth", .data = &ag71xx_dcfg_ar7240 }, 2014 { .compatible = "qca,ar7242-eth", .data = &ag71xx_dcfg_ar7240 }, 2015 { .compatible = "qca,ar9130-eth", .data = &ag71xx_dcfg_ar9130 }, 2016 { .compatible = "qca,ar9330-eth", .data = &ag71xx_dcfg_ar9330 }, 2017 { .compatible = "qca,ar9340-eth", .data = &ag71xx_dcfg_ar9340 }, 2018 { .compatible = "qca,qca9530-eth", .data = &ag71xx_dcfg_qca9530 }, 2019 { .compatible = "qca,qca9550-eth", .data = &ag71xx_dcfg_qca9550 }, 2020 { .compatible = "qca,qca9560-eth", .data = &ag71xx_dcfg_qca9550 }, 2021 {} 2022 }; 2023 2024 static struct platform_driver ag71xx_driver = { 2025 .probe = ag71xx_probe, 2026 .driver = { 2027 .name = "ag71xx", 2028 .of_match_table = ag71xx_match, 2029 } 2030 }; 2031 2032 module_platform_driver(ag71xx_driver); 2033 MODULE_LICENSE("GPL v2"); 2034