1 /* 2 * aQuantia Corporation Network Driver 3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 */ 9 10 /* File aq_hw.h: Declaration of abstract interface for NIC hardware specific 11 * functions. 12 */ 13 14 #ifndef AQ_HW_H 15 #define AQ_HW_H 16 17 #include "aq_common.h" 18 #include "aq_rss.h" 19 #include "hw_atl/hw_atl_utils.h" 20 21 #define AQ_RX_FIRST_LOC_FVLANID 0U 22 #define AQ_RX_LAST_LOC_FVLANID 15U 23 #define AQ_RX_FIRST_LOC_FETHERT 16U 24 #define AQ_RX_LAST_LOC_FETHERT 31U 25 #define AQ_RX_FIRST_LOC_FL3L4 32U 26 #define AQ_RX_LAST_LOC_FL3L4 39U 27 #define AQ_RX_MAX_RXNFC_LOC AQ_RX_LAST_LOC_FL3L4 28 #define AQ_VLAN_MAX_FILTERS \ 29 (AQ_RX_LAST_LOC_FVLANID - AQ_RX_FIRST_LOC_FVLANID + 1U) 30 #define AQ_RX_QUEUE_NOT_ASSIGNED 0xFFU 31 32 /* NIC H/W capabilities */ 33 struct aq_hw_caps_s { 34 u64 hw_features; 35 u64 link_speed_msk; 36 unsigned int hw_priv_flags; 37 u32 media_type; 38 u32 rxds_max; 39 u32 txds_max; 40 u32 rxds_min; 41 u32 txds_min; 42 u32 txhwb_alignment; 43 u32 irq_mask; 44 u32 vecs; 45 u32 mtu; 46 u32 mac_regs_count; 47 u32 hw_alive_check_addr; 48 u8 msix_irqs; 49 u8 tcs; 50 u8 rxd_alignment; 51 u8 rxd_size; 52 u8 txd_alignment; 53 u8 txd_size; 54 u8 tx_rings; 55 u8 rx_rings; 56 bool flow_control; 57 bool is_64_dma; 58 }; 59 60 struct aq_hw_link_status_s { 61 unsigned int mbps; 62 }; 63 64 struct aq_stats_s { 65 u64 uprc; 66 u64 mprc; 67 u64 bprc; 68 u64 erpt; 69 u64 uptc; 70 u64 mptc; 71 u64 bptc; 72 u64 erpr; 73 u64 mbtc; 74 u64 bbtc; 75 u64 mbrc; 76 u64 bbrc; 77 u64 ubrc; 78 u64 ubtc; 79 u64 dpc; 80 u64 dma_pkt_rc; 81 u64 dma_pkt_tc; 82 u64 dma_oct_rc; 83 u64 dma_oct_tc; 84 }; 85 86 #define AQ_HW_IRQ_INVALID 0U 87 #define AQ_HW_IRQ_LEGACY 1U 88 #define AQ_HW_IRQ_MSI 2U 89 #define AQ_HW_IRQ_MSIX 3U 90 91 #define AQ_HW_POWER_STATE_D0 0U 92 #define AQ_HW_POWER_STATE_D3 3U 93 94 #define AQ_HW_FLAG_STARTED 0x00000004U 95 #define AQ_HW_FLAG_STOPPING 0x00000008U 96 #define AQ_HW_FLAG_RESETTING 0x00000010U 97 #define AQ_HW_FLAG_CLOSING 0x00000020U 98 #define AQ_HW_LINK_DOWN 0x04000000U 99 #define AQ_HW_FLAG_ERR_UNPLUG 0x40000000U 100 #define AQ_HW_FLAG_ERR_HW 0x80000000U 101 102 #define AQ_HW_FLAG_ERRORS (AQ_HW_FLAG_ERR_HW | AQ_HW_FLAG_ERR_UNPLUG) 103 104 #define AQ_NIC_FLAGS_IS_NOT_READY (AQ_NIC_FLAG_STOPPING | \ 105 AQ_NIC_FLAG_RESETTING | AQ_NIC_FLAG_CLOSING | \ 106 AQ_NIC_FLAG_ERR_UNPLUG | AQ_NIC_FLAG_ERR_HW) 107 108 #define AQ_NIC_FLAGS_IS_NOT_TX_READY (AQ_NIC_FLAGS_IS_NOT_READY | \ 109 AQ_NIC_LINK_DOWN) 110 111 #define AQ_HW_MEDIA_TYPE_TP 1U 112 #define AQ_HW_MEDIA_TYPE_FIBRE 2U 113 114 #define AQ_HW_TXD_MULTIPLE 8U 115 #define AQ_HW_RXD_MULTIPLE 8U 116 117 #define AQ_HW_MULTICAST_ADDRESS_MAX 32U 118 119 struct aq_hw_s { 120 atomic_t flags; 121 u8 rbl_enabled:1; 122 struct aq_nic_cfg_s *aq_nic_cfg; 123 const struct aq_fw_ops *aq_fw_ops; 124 void __iomem *mmio; 125 struct aq_hw_link_status_s aq_link_status; 126 struct hw_atl_utils_mbox mbox; 127 struct hw_atl_stats_s last_stats; 128 struct aq_stats_s curr_stats; 129 u64 speed; 130 u32 itr_tx; 131 u32 itr_rx; 132 unsigned int chip_features; 133 u32 fw_ver_actual; 134 atomic_t dpc; 135 u32 mbox_addr; 136 u32 rpc_addr; 137 u32 rpc_tid; 138 struct hw_atl_utils_fw_rpc rpc; 139 }; 140 141 struct aq_ring_s; 142 struct aq_ring_param_s; 143 struct sk_buff; 144 struct aq_rx_filter_l3l4; 145 146 struct aq_hw_ops { 147 148 int (*hw_ring_tx_xmit)(struct aq_hw_s *self, struct aq_ring_s *aq_ring, 149 unsigned int frags); 150 151 int (*hw_ring_rx_receive)(struct aq_hw_s *self, 152 struct aq_ring_s *aq_ring); 153 154 int (*hw_ring_rx_fill)(struct aq_hw_s *self, struct aq_ring_s *aq_ring, 155 unsigned int sw_tail_old); 156 157 int (*hw_ring_tx_head_update)(struct aq_hw_s *self, 158 struct aq_ring_s *aq_ring); 159 160 int (*hw_set_mac_address)(struct aq_hw_s *self, u8 *mac_addr); 161 162 int (*hw_reset)(struct aq_hw_s *self); 163 164 int (*hw_init)(struct aq_hw_s *self, u8 *mac_addr); 165 166 int (*hw_start)(struct aq_hw_s *self); 167 168 int (*hw_stop)(struct aq_hw_s *self); 169 170 int (*hw_ring_tx_init)(struct aq_hw_s *self, struct aq_ring_s *aq_ring, 171 struct aq_ring_param_s *aq_ring_param); 172 173 int (*hw_ring_tx_start)(struct aq_hw_s *self, 174 struct aq_ring_s *aq_ring); 175 176 int (*hw_ring_tx_stop)(struct aq_hw_s *self, 177 struct aq_ring_s *aq_ring); 178 179 int (*hw_ring_rx_init)(struct aq_hw_s *self, 180 struct aq_ring_s *aq_ring, 181 struct aq_ring_param_s *aq_ring_param); 182 183 int (*hw_ring_rx_start)(struct aq_hw_s *self, 184 struct aq_ring_s *aq_ring); 185 186 int (*hw_ring_rx_stop)(struct aq_hw_s *self, 187 struct aq_ring_s *aq_ring); 188 189 int (*hw_irq_enable)(struct aq_hw_s *self, u64 mask); 190 191 int (*hw_irq_disable)(struct aq_hw_s *self, u64 mask); 192 193 int (*hw_irq_read)(struct aq_hw_s *self, u64 *mask); 194 195 int (*hw_packet_filter_set)(struct aq_hw_s *self, 196 unsigned int packet_filter); 197 198 int (*hw_filter_l3l4_set)(struct aq_hw_s *self, 199 struct aq_rx_filter_l3l4 *data); 200 201 int (*hw_filter_l3l4_clear)(struct aq_hw_s *self, 202 struct aq_rx_filter_l3l4 *data); 203 204 int (*hw_filter_l2_set)(struct aq_hw_s *self, 205 struct aq_rx_filter_l2 *data); 206 207 int (*hw_filter_l2_clear)(struct aq_hw_s *self, 208 struct aq_rx_filter_l2 *data); 209 210 int (*hw_filter_vlan_set)(struct aq_hw_s *self, 211 struct aq_rx_filter_vlan *aq_vlans); 212 213 int (*hw_filter_vlan_ctrl)(struct aq_hw_s *self, bool enable); 214 215 int (*hw_multicast_list_set)(struct aq_hw_s *self, 216 u8 ar_mac[AQ_HW_MULTICAST_ADDRESS_MAX] 217 [ETH_ALEN], 218 u32 count); 219 220 int (*hw_interrupt_moderation_set)(struct aq_hw_s *self); 221 222 int (*hw_rss_set)(struct aq_hw_s *self, 223 struct aq_rss_parameters *rss_params); 224 225 int (*hw_rss_hash_set)(struct aq_hw_s *self, 226 struct aq_rss_parameters *rss_params); 227 228 int (*hw_get_regs)(struct aq_hw_s *self, 229 const struct aq_hw_caps_s *aq_hw_caps, 230 u32 *regs_buff); 231 232 struct aq_stats_s *(*hw_get_hw_stats)(struct aq_hw_s *self); 233 234 int (*hw_get_fw_version)(struct aq_hw_s *self, u32 *fw_version); 235 236 int (*hw_set_offload)(struct aq_hw_s *self, 237 struct aq_nic_cfg_s *aq_nic_cfg); 238 239 int (*hw_set_fc)(struct aq_hw_s *self, u32 fc, u32 tc); 240 }; 241 242 struct aq_fw_ops { 243 int (*init)(struct aq_hw_s *self); 244 245 int (*deinit)(struct aq_hw_s *self); 246 247 int (*reset)(struct aq_hw_s *self); 248 249 int (*renegotiate)(struct aq_hw_s *self); 250 251 int (*get_mac_permanent)(struct aq_hw_s *self, u8 *mac); 252 253 int (*set_link_speed)(struct aq_hw_s *self, u32 speed); 254 255 int (*set_state)(struct aq_hw_s *self, 256 enum hal_atl_utils_fw_state_e state); 257 258 int (*update_link_status)(struct aq_hw_s *self); 259 260 int (*update_stats)(struct aq_hw_s *self); 261 262 u32 (*get_flow_control)(struct aq_hw_s *self, u32 *fcmode); 263 264 int (*set_flow_control)(struct aq_hw_s *self); 265 266 int (*set_power)(struct aq_hw_s *self, unsigned int power_state, 267 u8 *mac); 268 269 int (*set_eee_rate)(struct aq_hw_s *self, u32 speed); 270 271 int (*get_eee_rate)(struct aq_hw_s *self, u32 *rate, 272 u32 *supported_rates); 273 }; 274 275 #endif /* AQ_HW_H */ 276