1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Atlantic Network Driver 3 * 4 * Copyright (C) 2014-2019 aQuantia Corporation 5 * Copyright (C) 2019-2020 Marvell International Ltd. 6 */ 7 8 /* File aq_hw.h: Declaration of abstract interface for NIC hardware specific 9 * functions. 10 */ 11 12 #ifndef AQ_HW_H 13 #define AQ_HW_H 14 15 #include "aq_common.h" 16 #include "aq_rss.h" 17 #include "hw_atl/hw_atl_utils.h" 18 19 #define AQ_HW_MAC_COUNTER_HZ 312500000ll 20 #define AQ_HW_PHY_COUNTER_HZ 160000000ll 21 22 enum aq_tc_mode { 23 AQ_TC_MODE_INVALID = -1, 24 AQ_TC_MODE_8TCS, 25 AQ_TC_MODE_4TCS, 26 }; 27 28 #define AQ_RX_FIRST_LOC_FVLANID 0U 29 #define AQ_RX_LAST_LOC_FVLANID 15U 30 #define AQ_RX_FIRST_LOC_FETHERT 16U 31 #define AQ_RX_LAST_LOC_FETHERT 31U 32 #define AQ_RX_FIRST_LOC_FL3L4 32U 33 #define AQ_RX_LAST_LOC_FL3L4 39U 34 #define AQ_RX_MAX_RXNFC_LOC AQ_RX_LAST_LOC_FL3L4 35 #define AQ_VLAN_MAX_FILTERS \ 36 (AQ_RX_LAST_LOC_FVLANID - AQ_RX_FIRST_LOC_FVLANID + 1U) 37 #define AQ_RX_QUEUE_NOT_ASSIGNED 0xFFU 38 39 /* Used for rate to Mbps conversion */ 40 #define AQ_MBPS_DIVISOR 125000 /* 1000000 / 8 */ 41 42 /* NIC H/W capabilities */ 43 struct aq_hw_caps_s { 44 u64 hw_features; 45 u64 link_speed_msk; 46 unsigned int hw_priv_flags; 47 u32 media_type; 48 u32 rxds_max; 49 u32 txds_max; 50 u32 rxds_min; 51 u32 txds_min; 52 u32 txhwb_alignment; 53 u32 irq_mask; 54 u32 vecs; 55 u32 mtu; 56 u32 mac_regs_count; 57 u32 hw_alive_check_addr; 58 u8 msix_irqs; 59 u8 tcs_max; 60 u8 rxd_alignment; 61 u8 rxd_size; 62 u8 txd_alignment; 63 u8 txd_size; 64 u8 tx_rings; 65 u8 rx_rings; 66 bool flow_control; 67 bool is_64_dma; 68 u32 priv_data_len; 69 }; 70 71 struct aq_hw_link_status_s { 72 unsigned int mbps; 73 bool full_duplex; 74 u32 lp_link_speed_msk; 75 u32 lp_flow_control; 76 }; 77 78 struct aq_stats_s { 79 u64 uprc; 80 u64 mprc; 81 u64 bprc; 82 u64 erpt; 83 u64 uptc; 84 u64 mptc; 85 u64 bptc; 86 u64 erpr; 87 u64 mbtc; 88 u64 bbtc; 89 u64 mbrc; 90 u64 bbrc; 91 u64 ubrc; 92 u64 ubtc; 93 u64 dpc; 94 u64 dma_pkt_rc; 95 u64 dma_pkt_tc; 96 u64 dma_oct_rc; 97 u64 dma_oct_tc; 98 }; 99 100 #define AQ_HW_IRQ_INVALID 0U 101 #define AQ_HW_IRQ_LEGACY 1U 102 #define AQ_HW_IRQ_MSI 2U 103 #define AQ_HW_IRQ_MSIX 3U 104 105 #define AQ_HW_SERVICE_IRQS 1U 106 107 #define AQ_HW_POWER_STATE_D0 0U 108 #define AQ_HW_POWER_STATE_D3 3U 109 110 #define AQ_HW_FLAG_STARTED 0x00000004U 111 #define AQ_HW_FLAG_STOPPING 0x00000008U 112 #define AQ_HW_FLAG_RESETTING 0x00000010U 113 #define AQ_HW_FLAG_CLOSING 0x00000020U 114 #define AQ_HW_PTP_AVAILABLE 0x01000000U 115 #define AQ_HW_LINK_DOWN 0x04000000U 116 #define AQ_HW_FLAG_ERR_UNPLUG 0x40000000U 117 #define AQ_HW_FLAG_ERR_HW 0x80000000U 118 119 #define AQ_HW_FLAG_ERRORS (AQ_HW_FLAG_ERR_HW | AQ_HW_FLAG_ERR_UNPLUG) 120 121 #define AQ_NIC_FLAGS_IS_NOT_READY (AQ_NIC_FLAG_STOPPING | \ 122 AQ_NIC_FLAG_RESETTING | AQ_NIC_FLAG_CLOSING | \ 123 AQ_NIC_FLAG_ERR_UNPLUG | AQ_NIC_FLAG_ERR_HW) 124 125 #define AQ_NIC_FLAGS_IS_NOT_TX_READY (AQ_NIC_FLAGS_IS_NOT_READY | \ 126 AQ_NIC_LINK_DOWN) 127 128 #define AQ_HW_MEDIA_TYPE_TP 1U 129 #define AQ_HW_MEDIA_TYPE_FIBRE 2U 130 131 #define AQ_HW_TXD_MULTIPLE 8U 132 #define AQ_HW_RXD_MULTIPLE 8U 133 134 #define AQ_HW_QUEUES_MAX 32U 135 #define AQ_HW_MULTICAST_ADDRESS_MAX 32U 136 137 #define AQ_HW_PTP_TC 2U 138 139 #define AQ_HW_LED_BLINK 0x2U 140 #define AQ_HW_LED_DEFAULT 0x0U 141 142 enum aq_priv_flags { 143 AQ_HW_LOOPBACK_DMA_SYS, 144 AQ_HW_LOOPBACK_PKT_SYS, 145 AQ_HW_LOOPBACK_DMA_NET, 146 AQ_HW_LOOPBACK_PHYINT_SYS, 147 AQ_HW_LOOPBACK_PHYEXT_SYS, 148 }; 149 150 #define AQ_HW_LOOPBACK_MASK (BIT(AQ_HW_LOOPBACK_DMA_SYS) |\ 151 BIT(AQ_HW_LOOPBACK_PKT_SYS) |\ 152 BIT(AQ_HW_LOOPBACK_DMA_NET) |\ 153 BIT(AQ_HW_LOOPBACK_PHYINT_SYS) |\ 154 BIT(AQ_HW_LOOPBACK_PHYEXT_SYS)) 155 156 #define ATL_HW_CHIP_MIPS 0x00000001U 157 #define ATL_HW_CHIP_TPO2 0x00000002U 158 #define ATL_HW_CHIP_RPF2 0x00000004U 159 #define ATL_HW_CHIP_MPI_AQ 0x00000010U 160 #define ATL_HW_CHIP_ATLANTIC 0x00800000U 161 #define ATL_HW_CHIP_REVISION_A0 0x01000000U 162 #define ATL_HW_CHIP_REVISION_B0 0x02000000U 163 #define ATL_HW_CHIP_REVISION_B1 0x04000000U 164 #define ATL_HW_CHIP_ANTIGUA 0x08000000U 165 166 #define ATL_HW_IS_CHIP_FEATURE(_HW_, _F_) (!!(ATL_HW_CHIP_##_F_ & \ 167 (_HW_)->chip_features)) 168 169 struct aq_hw_s { 170 atomic_t flags; 171 u8 rbl_enabled:1; 172 struct aq_nic_cfg_s *aq_nic_cfg; 173 const struct aq_fw_ops *aq_fw_ops; 174 void __iomem *mmio; 175 struct aq_hw_link_status_s aq_link_status; 176 struct hw_atl_utils_mbox mbox; 177 struct hw_atl_stats_s last_stats; 178 struct aq_stats_s curr_stats; 179 u64 speed; 180 u32 itr_tx; 181 u32 itr_rx; 182 unsigned int chip_features; 183 u32 fw_ver_actual; 184 atomic_t dpc; 185 u32 mbox_addr; 186 u32 rpc_addr; 187 u32 settings_addr; 188 u32 rpc_tid; 189 struct hw_atl_utils_fw_rpc rpc; 190 s64 ptp_clk_offset; 191 u16 phy_id; 192 void *priv; 193 }; 194 195 struct aq_ring_s; 196 struct aq_ring_param_s; 197 struct sk_buff; 198 struct aq_rx_filter_l3l4; 199 200 struct aq_hw_ops { 201 202 int (*hw_ring_tx_xmit)(struct aq_hw_s *self, struct aq_ring_s *aq_ring, 203 unsigned int frags); 204 205 int (*hw_ring_rx_receive)(struct aq_hw_s *self, 206 struct aq_ring_s *aq_ring); 207 208 int (*hw_ring_rx_fill)(struct aq_hw_s *self, struct aq_ring_s *aq_ring, 209 unsigned int sw_tail_old); 210 211 int (*hw_ring_tx_head_update)(struct aq_hw_s *self, 212 struct aq_ring_s *aq_ring); 213 214 int (*hw_set_mac_address)(struct aq_hw_s *self, u8 *mac_addr); 215 216 int (*hw_soft_reset)(struct aq_hw_s *self); 217 218 int (*hw_prepare)(struct aq_hw_s *self, 219 const struct aq_fw_ops **fw_ops); 220 221 int (*hw_reset)(struct aq_hw_s *self); 222 223 int (*hw_init)(struct aq_hw_s *self, u8 *mac_addr); 224 225 int (*hw_start)(struct aq_hw_s *self); 226 227 int (*hw_stop)(struct aq_hw_s *self); 228 229 int (*hw_ring_tx_init)(struct aq_hw_s *self, struct aq_ring_s *aq_ring, 230 struct aq_ring_param_s *aq_ring_param); 231 232 int (*hw_ring_tx_start)(struct aq_hw_s *self, 233 struct aq_ring_s *aq_ring); 234 235 int (*hw_ring_tx_stop)(struct aq_hw_s *self, 236 struct aq_ring_s *aq_ring); 237 238 int (*hw_ring_rx_init)(struct aq_hw_s *self, 239 struct aq_ring_s *aq_ring, 240 struct aq_ring_param_s *aq_ring_param); 241 242 int (*hw_ring_rx_start)(struct aq_hw_s *self, 243 struct aq_ring_s *aq_ring); 244 245 int (*hw_ring_rx_stop)(struct aq_hw_s *self, 246 struct aq_ring_s *aq_ring); 247 248 int (*hw_irq_enable)(struct aq_hw_s *self, u64 mask); 249 250 int (*hw_irq_disable)(struct aq_hw_s *self, u64 mask); 251 252 int (*hw_irq_read)(struct aq_hw_s *self, u64 *mask); 253 254 int (*hw_packet_filter_set)(struct aq_hw_s *self, 255 unsigned int packet_filter); 256 257 int (*hw_filter_l3l4_set)(struct aq_hw_s *self, 258 struct aq_rx_filter_l3l4 *data); 259 260 int (*hw_filter_l3l4_clear)(struct aq_hw_s *self, 261 struct aq_rx_filter_l3l4 *data); 262 263 int (*hw_filter_l2_set)(struct aq_hw_s *self, 264 struct aq_rx_filter_l2 *data); 265 266 int (*hw_filter_l2_clear)(struct aq_hw_s *self, 267 struct aq_rx_filter_l2 *data); 268 269 int (*hw_filter_vlan_set)(struct aq_hw_s *self, 270 struct aq_rx_filter_vlan *aq_vlans); 271 272 int (*hw_filter_vlan_ctrl)(struct aq_hw_s *self, bool enable); 273 274 int (*hw_multicast_list_set)(struct aq_hw_s *self, 275 u8 ar_mac[AQ_HW_MULTICAST_ADDRESS_MAX] 276 [ETH_ALEN], 277 u32 count); 278 279 int (*hw_interrupt_moderation_set)(struct aq_hw_s *self); 280 281 int (*hw_rss_set)(struct aq_hw_s *self, 282 struct aq_rss_parameters *rss_params); 283 284 int (*hw_rss_hash_set)(struct aq_hw_s *self, 285 struct aq_rss_parameters *rss_params); 286 287 int (*hw_tc_rate_limit_set)(struct aq_hw_s *self); 288 289 int (*hw_get_regs)(struct aq_hw_s *self, 290 const struct aq_hw_caps_s *aq_hw_caps, 291 u32 *regs_buff); 292 293 struct aq_stats_s *(*hw_get_hw_stats)(struct aq_hw_s *self); 294 295 u32 (*hw_get_fw_version)(struct aq_hw_s *self); 296 297 int (*hw_set_offload)(struct aq_hw_s *self, 298 struct aq_nic_cfg_s *aq_nic_cfg); 299 300 int (*hw_ring_hwts_rx_fill)(struct aq_hw_s *self, 301 struct aq_ring_s *aq_ring); 302 303 int (*hw_ring_hwts_rx_receive)(struct aq_hw_s *self, 304 struct aq_ring_s *ring); 305 306 void (*hw_get_ptp_ts)(struct aq_hw_s *self, u64 *stamp); 307 308 int (*hw_adj_clock_freq)(struct aq_hw_s *self, s32 delta); 309 310 int (*hw_adj_sys_clock)(struct aq_hw_s *self, s64 delta); 311 312 int (*hw_set_sys_clock)(struct aq_hw_s *self, u64 time, u64 ts); 313 314 int (*hw_ts_to_sys_clock)(struct aq_hw_s *self, u64 ts, u64 *time); 315 316 int (*hw_gpio_pulse)(struct aq_hw_s *self, u32 index, u64 start, 317 u32 period); 318 319 int (*hw_extts_gpio_enable)(struct aq_hw_s *self, u32 index, 320 u32 enable); 321 322 int (*hw_get_sync_ts)(struct aq_hw_s *self, u64 *ts); 323 324 u16 (*rx_extract_ts)(struct aq_hw_s *self, u8 *p, unsigned int len, 325 u64 *timestamp); 326 327 int (*extract_hwts)(struct aq_hw_s *self, u8 *p, unsigned int len, 328 u64 *timestamp); 329 330 int (*hw_set_fc)(struct aq_hw_s *self, u32 fc, u32 tc); 331 332 int (*hw_set_loopback)(struct aq_hw_s *self, u32 mode, bool enable); 333 }; 334 335 struct aq_fw_ops { 336 int (*init)(struct aq_hw_s *self); 337 338 int (*deinit)(struct aq_hw_s *self); 339 340 int (*reset)(struct aq_hw_s *self); 341 342 int (*renegotiate)(struct aq_hw_s *self); 343 344 int (*get_mac_permanent)(struct aq_hw_s *self, u8 *mac); 345 346 int (*set_link_speed)(struct aq_hw_s *self, u32 speed); 347 348 int (*set_state)(struct aq_hw_s *self, 349 enum hal_atl_utils_fw_state_e state); 350 351 int (*update_link_status)(struct aq_hw_s *self); 352 353 int (*update_stats)(struct aq_hw_s *self); 354 355 int (*get_phy_temp)(struct aq_hw_s *self, int *temp); 356 357 u32 (*get_flow_control)(struct aq_hw_s *self, u32 *fcmode); 358 359 int (*set_flow_control)(struct aq_hw_s *self); 360 361 int (*led_control)(struct aq_hw_s *self, u32 mode); 362 363 int (*set_phyloopback)(struct aq_hw_s *self, u32 mode, bool enable); 364 365 int (*set_power)(struct aq_hw_s *self, unsigned int power_state, 366 u8 *mac); 367 368 int (*send_fw_request)(struct aq_hw_s *self, 369 const struct hw_fw_request_iface *fw_req, 370 size_t size); 371 372 void (*enable_ptp)(struct aq_hw_s *self, int enable); 373 374 void (*adjust_ptp)(struct aq_hw_s *self, uint64_t adj); 375 376 int (*set_eee_rate)(struct aq_hw_s *self, u32 speed); 377 378 int (*get_eee_rate)(struct aq_hw_s *self, u32 *rate, 379 u32 *supported_rates); 380 381 u32 (*get_link_capabilities)(struct aq_hw_s *self); 382 383 int (*send_macsec_req)(struct aq_hw_s *self, 384 struct macsec_msg_fw_request *msg, 385 struct macsec_msg_fw_response *resp); 386 }; 387 388 #endif /* AQ_HW_H */ 389