1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * aQuantia Corporation Network Driver 4 * Copyright (C) 2014-2019 aQuantia Corporation. All rights reserved 5 */ 6 7 /* File aq_hw.h: Declaration of abstract interface for NIC hardware specific 8 * functions. 9 */ 10 11 #ifndef AQ_HW_H 12 #define AQ_HW_H 13 14 #include "aq_common.h" 15 #include "aq_rss.h" 16 #include "hw_atl/hw_atl_utils.h" 17 18 #define AQ_HW_MAC_COUNTER_HZ 312500000ll 19 #define AQ_HW_PHY_COUNTER_HZ 160000000ll 20 21 #define AQ_RX_FIRST_LOC_FVLANID 0U 22 #define AQ_RX_LAST_LOC_FVLANID 15U 23 #define AQ_RX_FIRST_LOC_FETHERT 16U 24 #define AQ_RX_LAST_LOC_FETHERT 31U 25 #define AQ_RX_FIRST_LOC_FL3L4 32U 26 #define AQ_RX_LAST_LOC_FL3L4 39U 27 #define AQ_RX_MAX_RXNFC_LOC AQ_RX_LAST_LOC_FL3L4 28 #define AQ_VLAN_MAX_FILTERS \ 29 (AQ_RX_LAST_LOC_FVLANID - AQ_RX_FIRST_LOC_FVLANID + 1U) 30 #define AQ_RX_QUEUE_NOT_ASSIGNED 0xFFU 31 32 /* NIC H/W capabilities */ 33 struct aq_hw_caps_s { 34 u64 hw_features; 35 u64 link_speed_msk; 36 unsigned int hw_priv_flags; 37 u32 media_type; 38 u32 rxds_max; 39 u32 txds_max; 40 u32 rxds_min; 41 u32 txds_min; 42 u32 txhwb_alignment; 43 u32 irq_mask; 44 u32 vecs; 45 u32 mtu; 46 u32 mac_regs_count; 47 u32 hw_alive_check_addr; 48 u8 msix_irqs; 49 u8 tcs; 50 u8 rxd_alignment; 51 u8 rxd_size; 52 u8 txd_alignment; 53 u8 txd_size; 54 u8 tx_rings; 55 u8 rx_rings; 56 bool flow_control; 57 bool is_64_dma; 58 u32 priv_data_len; 59 }; 60 61 struct aq_hw_link_status_s { 62 unsigned int mbps; 63 }; 64 65 struct aq_stats_s { 66 u64 uprc; 67 u64 mprc; 68 u64 bprc; 69 u64 erpt; 70 u64 uptc; 71 u64 mptc; 72 u64 bptc; 73 u64 erpr; 74 u64 mbtc; 75 u64 bbtc; 76 u64 mbrc; 77 u64 bbrc; 78 u64 ubrc; 79 u64 ubtc; 80 u64 dpc; 81 u64 dma_pkt_rc; 82 u64 dma_pkt_tc; 83 u64 dma_oct_rc; 84 u64 dma_oct_tc; 85 }; 86 87 #define AQ_HW_IRQ_INVALID 0U 88 #define AQ_HW_IRQ_LEGACY 1U 89 #define AQ_HW_IRQ_MSI 2U 90 #define AQ_HW_IRQ_MSIX 3U 91 92 #define AQ_HW_SERVICE_IRQS 1U 93 94 #define AQ_HW_POWER_STATE_D0 0U 95 #define AQ_HW_POWER_STATE_D3 3U 96 97 #define AQ_HW_FLAG_STARTED 0x00000004U 98 #define AQ_HW_FLAG_STOPPING 0x00000008U 99 #define AQ_HW_FLAG_RESETTING 0x00000010U 100 #define AQ_HW_FLAG_CLOSING 0x00000020U 101 #define AQ_HW_PTP_AVAILABLE 0x01000000U 102 #define AQ_HW_LINK_DOWN 0x04000000U 103 #define AQ_HW_FLAG_ERR_UNPLUG 0x40000000U 104 #define AQ_HW_FLAG_ERR_HW 0x80000000U 105 106 #define AQ_HW_FLAG_ERRORS (AQ_HW_FLAG_ERR_HW | AQ_HW_FLAG_ERR_UNPLUG) 107 108 #define AQ_NIC_FLAGS_IS_NOT_READY (AQ_NIC_FLAG_STOPPING | \ 109 AQ_NIC_FLAG_RESETTING | AQ_NIC_FLAG_CLOSING | \ 110 AQ_NIC_FLAG_ERR_UNPLUG | AQ_NIC_FLAG_ERR_HW) 111 112 #define AQ_NIC_FLAGS_IS_NOT_TX_READY (AQ_NIC_FLAGS_IS_NOT_READY | \ 113 AQ_NIC_LINK_DOWN) 114 115 #define AQ_HW_MEDIA_TYPE_TP 1U 116 #define AQ_HW_MEDIA_TYPE_FIBRE 2U 117 118 #define AQ_HW_TXD_MULTIPLE 8U 119 #define AQ_HW_RXD_MULTIPLE 8U 120 121 #define AQ_HW_MULTICAST_ADDRESS_MAX 32U 122 123 #define AQ_HW_LED_BLINK 0x2U 124 #define AQ_HW_LED_DEFAULT 0x0U 125 126 enum aq_priv_flags { 127 AQ_HW_LOOPBACK_DMA_SYS, 128 AQ_HW_LOOPBACK_PKT_SYS, 129 AQ_HW_LOOPBACK_DMA_NET, 130 AQ_HW_LOOPBACK_PHYINT_SYS, 131 AQ_HW_LOOPBACK_PHYEXT_SYS, 132 }; 133 134 #define AQ_HW_LOOPBACK_MASK (BIT(AQ_HW_LOOPBACK_DMA_SYS) |\ 135 BIT(AQ_HW_LOOPBACK_PKT_SYS) |\ 136 BIT(AQ_HW_LOOPBACK_DMA_NET) |\ 137 BIT(AQ_HW_LOOPBACK_PHYINT_SYS) |\ 138 BIT(AQ_HW_LOOPBACK_PHYEXT_SYS)) 139 140 #define ATL_HW_CHIP_MIPS 0x00000001U 141 #define ATL_HW_CHIP_TPO2 0x00000002U 142 #define ATL_HW_CHIP_RPF2 0x00000004U 143 #define ATL_HW_CHIP_MPI_AQ 0x00000010U 144 #define ATL_HW_CHIP_ATLANTIC 0x00800000U 145 #define ATL_HW_CHIP_REVISION_A0 0x01000000U 146 #define ATL_HW_CHIP_REVISION_B0 0x02000000U 147 #define ATL_HW_CHIP_REVISION_B1 0x04000000U 148 #define ATL_HW_CHIP_ANTIGUA 0x08000000U 149 150 #define ATL_HW_IS_CHIP_FEATURE(_HW_, _F_) (!!(ATL_HW_CHIP_##_F_ & \ 151 (_HW_)->chip_features)) 152 153 struct aq_hw_s { 154 atomic_t flags; 155 u8 rbl_enabled:1; 156 struct aq_nic_cfg_s *aq_nic_cfg; 157 const struct aq_fw_ops *aq_fw_ops; 158 void __iomem *mmio; 159 struct aq_hw_link_status_s aq_link_status; 160 struct hw_atl_utils_mbox mbox; 161 struct hw_atl_stats_s last_stats; 162 struct aq_stats_s curr_stats; 163 u64 speed; 164 u32 itr_tx; 165 u32 itr_rx; 166 unsigned int chip_features; 167 u32 fw_ver_actual; 168 atomic_t dpc; 169 u32 mbox_addr; 170 u32 rpc_addr; 171 u32 settings_addr; 172 u32 rpc_tid; 173 struct hw_atl_utils_fw_rpc rpc; 174 s64 ptp_clk_offset; 175 u16 phy_id; 176 void *priv; 177 }; 178 179 struct aq_ring_s; 180 struct aq_ring_param_s; 181 struct sk_buff; 182 struct aq_rx_filter_l3l4; 183 184 struct aq_hw_ops { 185 186 int (*hw_ring_tx_xmit)(struct aq_hw_s *self, struct aq_ring_s *aq_ring, 187 unsigned int frags); 188 189 int (*hw_ring_rx_receive)(struct aq_hw_s *self, 190 struct aq_ring_s *aq_ring); 191 192 int (*hw_ring_rx_fill)(struct aq_hw_s *self, struct aq_ring_s *aq_ring, 193 unsigned int sw_tail_old); 194 195 int (*hw_ring_tx_head_update)(struct aq_hw_s *self, 196 struct aq_ring_s *aq_ring); 197 198 int (*hw_set_mac_address)(struct aq_hw_s *self, u8 *mac_addr); 199 200 int (*hw_soft_reset)(struct aq_hw_s *self); 201 202 int (*hw_prepare)(struct aq_hw_s *self, 203 const struct aq_fw_ops **fw_ops); 204 205 int (*hw_reset)(struct aq_hw_s *self); 206 207 int (*hw_init)(struct aq_hw_s *self, u8 *mac_addr); 208 209 int (*hw_start)(struct aq_hw_s *self); 210 211 int (*hw_stop)(struct aq_hw_s *self); 212 213 int (*hw_ring_tx_init)(struct aq_hw_s *self, struct aq_ring_s *aq_ring, 214 struct aq_ring_param_s *aq_ring_param); 215 216 int (*hw_ring_tx_start)(struct aq_hw_s *self, 217 struct aq_ring_s *aq_ring); 218 219 int (*hw_ring_tx_stop)(struct aq_hw_s *self, 220 struct aq_ring_s *aq_ring); 221 222 int (*hw_ring_rx_init)(struct aq_hw_s *self, 223 struct aq_ring_s *aq_ring, 224 struct aq_ring_param_s *aq_ring_param); 225 226 int (*hw_ring_rx_start)(struct aq_hw_s *self, 227 struct aq_ring_s *aq_ring); 228 229 int (*hw_ring_rx_stop)(struct aq_hw_s *self, 230 struct aq_ring_s *aq_ring); 231 232 int (*hw_irq_enable)(struct aq_hw_s *self, u64 mask); 233 234 int (*hw_irq_disable)(struct aq_hw_s *self, u64 mask); 235 236 int (*hw_irq_read)(struct aq_hw_s *self, u64 *mask); 237 238 int (*hw_packet_filter_set)(struct aq_hw_s *self, 239 unsigned int packet_filter); 240 241 int (*hw_filter_l3l4_set)(struct aq_hw_s *self, 242 struct aq_rx_filter_l3l4 *data); 243 244 int (*hw_filter_l3l4_clear)(struct aq_hw_s *self, 245 struct aq_rx_filter_l3l4 *data); 246 247 int (*hw_filter_l2_set)(struct aq_hw_s *self, 248 struct aq_rx_filter_l2 *data); 249 250 int (*hw_filter_l2_clear)(struct aq_hw_s *self, 251 struct aq_rx_filter_l2 *data); 252 253 int (*hw_filter_vlan_set)(struct aq_hw_s *self, 254 struct aq_rx_filter_vlan *aq_vlans); 255 256 int (*hw_filter_vlan_ctrl)(struct aq_hw_s *self, bool enable); 257 258 int (*hw_multicast_list_set)(struct aq_hw_s *self, 259 u8 ar_mac[AQ_HW_MULTICAST_ADDRESS_MAX] 260 [ETH_ALEN], 261 u32 count); 262 263 int (*hw_interrupt_moderation_set)(struct aq_hw_s *self); 264 265 int (*hw_rss_set)(struct aq_hw_s *self, 266 struct aq_rss_parameters *rss_params); 267 268 int (*hw_rss_hash_set)(struct aq_hw_s *self, 269 struct aq_rss_parameters *rss_params); 270 271 int (*hw_get_regs)(struct aq_hw_s *self, 272 const struct aq_hw_caps_s *aq_hw_caps, 273 u32 *regs_buff); 274 275 struct aq_stats_s *(*hw_get_hw_stats)(struct aq_hw_s *self); 276 277 u32 (*hw_get_fw_version)(struct aq_hw_s *self); 278 279 int (*hw_set_offload)(struct aq_hw_s *self, 280 struct aq_nic_cfg_s *aq_nic_cfg); 281 282 int (*hw_tx_tc_mode_get)(struct aq_hw_s *self, u32 *tc_mode); 283 284 int (*hw_rx_tc_mode_get)(struct aq_hw_s *self, u32 *tc_mode); 285 286 int (*hw_ring_hwts_rx_fill)(struct aq_hw_s *self, 287 struct aq_ring_s *aq_ring); 288 289 int (*hw_ring_hwts_rx_receive)(struct aq_hw_s *self, 290 struct aq_ring_s *ring); 291 292 void (*hw_get_ptp_ts)(struct aq_hw_s *self, u64 *stamp); 293 294 int (*hw_adj_clock_freq)(struct aq_hw_s *self, s32 delta); 295 296 int (*hw_adj_sys_clock)(struct aq_hw_s *self, s64 delta); 297 298 int (*hw_set_sys_clock)(struct aq_hw_s *self, u64 time, u64 ts); 299 300 int (*hw_ts_to_sys_clock)(struct aq_hw_s *self, u64 ts, u64 *time); 301 302 int (*hw_gpio_pulse)(struct aq_hw_s *self, u32 index, u64 start, 303 u32 period); 304 305 int (*hw_extts_gpio_enable)(struct aq_hw_s *self, u32 index, 306 u32 enable); 307 308 int (*hw_get_sync_ts)(struct aq_hw_s *self, u64 *ts); 309 310 u16 (*rx_extract_ts)(struct aq_hw_s *self, u8 *p, unsigned int len, 311 u64 *timestamp); 312 313 int (*extract_hwts)(struct aq_hw_s *self, u8 *p, unsigned int len, 314 u64 *timestamp); 315 316 int (*hw_set_fc)(struct aq_hw_s *self, u32 fc, u32 tc); 317 318 int (*hw_set_loopback)(struct aq_hw_s *self, u32 mode, bool enable); 319 }; 320 321 struct aq_fw_ops { 322 int (*init)(struct aq_hw_s *self); 323 324 int (*deinit)(struct aq_hw_s *self); 325 326 int (*reset)(struct aq_hw_s *self); 327 328 int (*renegotiate)(struct aq_hw_s *self); 329 330 int (*get_mac_permanent)(struct aq_hw_s *self, u8 *mac); 331 332 int (*set_link_speed)(struct aq_hw_s *self, u32 speed); 333 334 int (*set_state)(struct aq_hw_s *self, 335 enum hal_atl_utils_fw_state_e state); 336 337 int (*update_link_status)(struct aq_hw_s *self); 338 339 int (*update_stats)(struct aq_hw_s *self); 340 341 int (*get_phy_temp)(struct aq_hw_s *self, int *temp); 342 343 u32 (*get_flow_control)(struct aq_hw_s *self, u32 *fcmode); 344 345 int (*set_flow_control)(struct aq_hw_s *self); 346 347 int (*led_control)(struct aq_hw_s *self, u32 mode); 348 349 int (*set_phyloopback)(struct aq_hw_s *self, u32 mode, bool enable); 350 351 int (*set_power)(struct aq_hw_s *self, unsigned int power_state, 352 u8 *mac); 353 354 int (*send_fw_request)(struct aq_hw_s *self, 355 const struct hw_fw_request_iface *fw_req, 356 size_t size); 357 358 void (*enable_ptp)(struct aq_hw_s *self, int enable); 359 360 void (*adjust_ptp)(struct aq_hw_s *self, uint64_t adj); 361 362 int (*set_eee_rate)(struct aq_hw_s *self, u32 speed); 363 364 int (*get_eee_rate)(struct aq_hw_s *self, u32 *rate, 365 u32 *supported_rates); 366 367 u32 (*get_link_capabilities)(struct aq_hw_s *self); 368 369 int (*send_macsec_req)(struct aq_hw_s *self, 370 struct macsec_msg_fw_request *msg, 371 struct macsec_msg_fw_response *resp); 372 }; 373 374 #endif /* AQ_HW_H */ 375