1 /* Applied Micro X-Gene SoC Ethernet Driver 2 * 3 * Copyright (c) 2014, Applied Micro Circuits Corporation 4 * Authors: Iyappan Subramanian <isubramanian@apm.com> 5 * Keyur Chudgar <kchudgar@apm.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "xgene_enet_main.h" 22 #include "xgene_enet_hw.h" 23 #include "xgene_enet_xgmac.h" 24 25 static void xgene_enet_wr_csr(struct xgene_enet_pdata *pdata, 26 u32 offset, u32 val) 27 { 28 void __iomem *addr = pdata->eth_csr_addr + offset; 29 30 iowrite32(val, addr); 31 } 32 33 static void xgene_enet_wr_ring_if(struct xgene_enet_pdata *pdata, 34 u32 offset, u32 val) 35 { 36 void __iomem *addr = pdata->eth_ring_if_addr + offset; 37 38 iowrite32(val, addr); 39 } 40 41 static void xgene_enet_wr_diag_csr(struct xgene_enet_pdata *pdata, 42 u32 offset, u32 val) 43 { 44 void __iomem *addr = pdata->eth_diag_csr_addr + offset; 45 46 iowrite32(val, addr); 47 } 48 49 static bool xgene_enet_wr_indirect(void __iomem *addr, void __iomem *wr, 50 void __iomem *cmd, void __iomem *cmd_done, 51 u32 wr_addr, u32 wr_data) 52 { 53 u32 done; 54 u8 wait = 10; 55 56 iowrite32(wr_addr, addr); 57 iowrite32(wr_data, wr); 58 iowrite32(XGENE_ENET_WR_CMD, cmd); 59 60 /* wait for write command to complete */ 61 while (!(done = ioread32(cmd_done)) && wait--) 62 udelay(1); 63 64 if (!done) 65 return false; 66 67 iowrite32(0, cmd); 68 69 return true; 70 } 71 72 static void xgene_enet_wr_mac(struct xgene_enet_pdata *pdata, 73 u32 wr_addr, u32 wr_data) 74 { 75 void __iomem *addr, *wr, *cmd, *cmd_done; 76 77 addr = pdata->mcx_mac_addr + MAC_ADDR_REG_OFFSET; 78 wr = pdata->mcx_mac_addr + MAC_WRITE_REG_OFFSET; 79 cmd = pdata->mcx_mac_addr + MAC_COMMAND_REG_OFFSET; 80 cmd_done = pdata->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET; 81 82 if (!xgene_enet_wr_indirect(addr, wr, cmd, cmd_done, wr_addr, wr_data)) 83 netdev_err(pdata->ndev, "MCX mac write failed, addr: %04x\n", 84 wr_addr); 85 } 86 87 static void xgene_enet_rd_csr(struct xgene_enet_pdata *pdata, 88 u32 offset, u32 *val) 89 { 90 void __iomem *addr = pdata->eth_csr_addr + offset; 91 92 *val = ioread32(addr); 93 } 94 95 static void xgene_enet_rd_diag_csr(struct xgene_enet_pdata *pdata, 96 u32 offset, u32 *val) 97 { 98 void __iomem *addr = pdata->eth_diag_csr_addr + offset; 99 100 *val = ioread32(addr); 101 } 102 103 static bool xgene_enet_rd_indirect(void __iomem *addr, void __iomem *rd, 104 void __iomem *cmd, void __iomem *cmd_done, 105 u32 rd_addr, u32 *rd_data) 106 { 107 u32 done; 108 u8 wait = 10; 109 110 iowrite32(rd_addr, addr); 111 iowrite32(XGENE_ENET_RD_CMD, cmd); 112 113 /* wait for read command to complete */ 114 while (!(done = ioread32(cmd_done)) && wait--) 115 udelay(1); 116 117 if (!done) 118 return false; 119 120 *rd_data = ioread32(rd); 121 iowrite32(0, cmd); 122 123 return true; 124 } 125 static void xgene_enet_rd_mac(struct xgene_enet_pdata *pdata, 126 u32 rd_addr, u32 *rd_data) 127 { 128 void __iomem *addr, *rd, *cmd, *cmd_done; 129 130 addr = pdata->mcx_mac_addr + MAC_ADDR_REG_OFFSET; 131 rd = pdata->mcx_mac_addr + MAC_READ_REG_OFFSET; 132 cmd = pdata->mcx_mac_addr + MAC_COMMAND_REG_OFFSET; 133 cmd_done = pdata->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET; 134 135 if (!xgene_enet_rd_indirect(addr, rd, cmd, cmd_done, rd_addr, rd_data)) 136 netdev_err(pdata->ndev, "MCX mac read failed, addr: %04x\n", 137 rd_addr); 138 } 139 140 static int xgene_enet_ecc_init(struct xgene_enet_pdata *pdata) 141 { 142 struct net_device *ndev = pdata->ndev; 143 u32 data; 144 u8 wait = 10; 145 146 xgene_enet_wr_diag_csr(pdata, ENET_CFG_MEM_RAM_SHUTDOWN_ADDR, 0x0); 147 do { 148 usleep_range(100, 110); 149 xgene_enet_rd_diag_csr(pdata, ENET_BLOCK_MEM_RDY_ADDR, &data); 150 } while ((data != 0xffffffff) && wait--); 151 152 if (data != 0xffffffff) { 153 netdev_err(ndev, "Failed to release memory from shutdown\n"); 154 return -ENODEV; 155 } 156 157 return 0; 158 } 159 160 static void xgene_enet_config_ring_if_assoc(struct xgene_enet_pdata *pdata) 161 { 162 xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIWQASSOC_ADDR, 0); 163 xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIFPQASSOC_ADDR, 0); 164 xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIQMLITEWQASSOC_ADDR, 0); 165 xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIQMLITEFPQASSOC_ADDR, 0); 166 } 167 168 static void xgene_xgmac_reset(struct xgene_enet_pdata *pdata) 169 { 170 xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_0, HSTMACRST); 171 xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_0, 0); 172 } 173 174 static void xgene_xgmac_set_mac_addr(struct xgene_enet_pdata *pdata) 175 { 176 u32 addr0, addr1; 177 u8 *dev_addr = pdata->ndev->dev_addr; 178 179 addr0 = (dev_addr[3] << 24) | (dev_addr[2] << 16) | 180 (dev_addr[1] << 8) | dev_addr[0]; 181 addr1 = (dev_addr[5] << 24) | (dev_addr[4] << 16); 182 183 xgene_enet_wr_mac(pdata, HSTMACADR_LSW_ADDR, addr0); 184 xgene_enet_wr_mac(pdata, HSTMACADR_MSW_ADDR, addr1); 185 } 186 187 static u32 xgene_enet_link_status(struct xgene_enet_pdata *pdata) 188 { 189 u32 data; 190 191 xgene_enet_rd_csr(pdata, XG_LINK_STATUS_ADDR, &data); 192 193 return data; 194 } 195 196 static void xgene_xgmac_init(struct xgene_enet_pdata *pdata) 197 { 198 u32 data; 199 200 xgene_xgmac_reset(pdata); 201 202 xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1, &data); 203 data |= HSTPPEN; 204 data &= ~HSTLENCHK; 205 xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data); 206 207 xgene_enet_wr_mac(pdata, HSTMAXFRAME_LENGTH_ADDR, 0x06000600); 208 xgene_xgmac_set_mac_addr(pdata); 209 210 xgene_enet_rd_csr(pdata, XG_RSIF_CONFIG_REG_ADDR, &data); 211 data |= CFG_RSIF_FPBUFF_TIMEOUT_EN; 212 xgene_enet_wr_csr(pdata, XG_RSIF_CONFIG_REG_ADDR, data); 213 214 xgene_enet_wr_csr(pdata, XG_CFG_BYPASS_ADDR, RESUME_TX); 215 xgene_enet_wr_csr(pdata, XGENET_RX_DV_GATE_REG_0_ADDR, 0); 216 xgene_enet_rd_csr(pdata, XG_ENET_SPARE_CFG_REG_ADDR, &data); 217 data |= BIT(12); 218 xgene_enet_wr_csr(pdata, XG_ENET_SPARE_CFG_REG_ADDR, data); 219 xgene_enet_wr_csr(pdata, XG_ENET_SPARE_CFG_REG_1_ADDR, 0x82); 220 } 221 222 static void xgene_xgmac_rx_enable(struct xgene_enet_pdata *pdata) 223 { 224 u32 data; 225 226 xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1, &data); 227 xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data | HSTRFEN); 228 } 229 230 static void xgene_xgmac_tx_enable(struct xgene_enet_pdata *pdata) 231 { 232 u32 data; 233 234 xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1, &data); 235 xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data | HSTTFEN); 236 } 237 238 static void xgene_xgmac_rx_disable(struct xgene_enet_pdata *pdata) 239 { 240 u32 data; 241 242 xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1, &data); 243 xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data & ~HSTRFEN); 244 } 245 246 static void xgene_xgmac_tx_disable(struct xgene_enet_pdata *pdata) 247 { 248 u32 data; 249 250 xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1, &data); 251 xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data & ~HSTTFEN); 252 } 253 254 static int xgene_enet_reset(struct xgene_enet_pdata *pdata) 255 { 256 if (!xgene_ring_mgr_init(pdata)) 257 return -ENODEV; 258 259 if (!IS_ERR(pdata->clk)) { 260 clk_prepare_enable(pdata->clk); 261 clk_disable_unprepare(pdata->clk); 262 clk_prepare_enable(pdata->clk); 263 } 264 265 xgene_enet_ecc_init(pdata); 266 xgene_enet_config_ring_if_assoc(pdata); 267 268 return 0; 269 } 270 271 static void xgene_enet_xgcle_bypass(struct xgene_enet_pdata *pdata, 272 u32 dst_ring_num, u16 bufpool_id) 273 { 274 u32 cb, fpsel; 275 276 xgene_enet_rd_csr(pdata, XCLE_BYPASS_REG0_ADDR, &cb); 277 cb |= CFG_CLE_BYPASS_EN0; 278 CFG_CLE_IP_PROTOCOL0_SET(&cb, 3); 279 xgene_enet_wr_csr(pdata, XCLE_BYPASS_REG0_ADDR, cb); 280 281 fpsel = xgene_enet_ring_bufnum(bufpool_id) - 0x20; 282 xgene_enet_rd_csr(pdata, XCLE_BYPASS_REG1_ADDR, &cb); 283 CFG_CLE_DSTQID0_SET(&cb, dst_ring_num); 284 CFG_CLE_FPSEL0_SET(&cb, fpsel); 285 xgene_enet_wr_csr(pdata, XCLE_BYPASS_REG1_ADDR, cb); 286 } 287 288 static void xgene_enet_shutdown(struct xgene_enet_pdata *pdata) 289 { 290 if (!IS_ERR(pdata->clk)) 291 clk_disable_unprepare(pdata->clk); 292 } 293 294 static void xgene_enet_link_state(struct work_struct *work) 295 { 296 struct xgene_enet_pdata *pdata = container_of(to_delayed_work(work), 297 struct xgene_enet_pdata, link_work); 298 struct net_device *ndev = pdata->ndev; 299 u32 link_status, poll_interval; 300 301 link_status = xgene_enet_link_status(pdata); 302 if (link_status) { 303 if (!netif_carrier_ok(ndev)) { 304 netif_carrier_on(ndev); 305 xgene_xgmac_init(pdata); 306 xgene_xgmac_rx_enable(pdata); 307 xgene_xgmac_tx_enable(pdata); 308 netdev_info(ndev, "Link is Up - 10Gbps\n"); 309 } 310 poll_interval = PHY_POLL_LINK_ON; 311 } else { 312 if (netif_carrier_ok(ndev)) { 313 xgene_xgmac_rx_disable(pdata); 314 xgene_xgmac_tx_disable(pdata); 315 netif_carrier_off(ndev); 316 netdev_info(ndev, "Link is Down\n"); 317 } 318 poll_interval = PHY_POLL_LINK_OFF; 319 } 320 321 schedule_delayed_work(&pdata->link_work, poll_interval); 322 } 323 324 struct xgene_mac_ops xgene_xgmac_ops = { 325 .init = xgene_xgmac_init, 326 .reset = xgene_xgmac_reset, 327 .rx_enable = xgene_xgmac_rx_enable, 328 .tx_enable = xgene_xgmac_tx_enable, 329 .rx_disable = xgene_xgmac_rx_disable, 330 .tx_disable = xgene_xgmac_tx_disable, 331 .set_mac_addr = xgene_xgmac_set_mac_addr, 332 .link_state = xgene_enet_link_state 333 }; 334 335 struct xgene_port_ops xgene_xgport_ops = { 336 .reset = xgene_enet_reset, 337 .cle_bypass = xgene_enet_xgcle_bypass, 338 .shutdown = xgene_enet_shutdown, 339 }; 340