1 /* Applied Micro X-Gene SoC Ethernet Driver 2 * 3 * Copyright (c) 2014, Applied Micro Circuits Corporation 4 * Authors: Iyappan Subramanian <isubramanian@apm.com> 5 * Keyur Chudgar <kchudgar@apm.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "xgene_enet_main.h" 22 #include "xgene_enet_hw.h" 23 #include "xgene_enet_sgmac.h" 24 #include "xgene_enet_xgmac.h" 25 26 static void xgene_enet_wr_csr(struct xgene_enet_pdata *p, u32 offset, u32 val) 27 { 28 iowrite32(val, p->eth_csr_addr + offset); 29 } 30 31 static void xgene_enet_wr_ring_if(struct xgene_enet_pdata *p, 32 u32 offset, u32 val) 33 { 34 iowrite32(val, p->eth_ring_if_addr + offset); 35 } 36 37 static void xgene_enet_wr_diag_csr(struct xgene_enet_pdata *p, 38 u32 offset, u32 val) 39 { 40 iowrite32(val, p->eth_diag_csr_addr + offset); 41 } 42 43 static void xgene_enet_wr_mcx_csr(struct xgene_enet_pdata *pdata, 44 u32 offset, u32 val) 45 { 46 void __iomem *addr = pdata->mcx_mac_csr_addr + offset; 47 48 iowrite32(val, addr); 49 } 50 51 static bool xgene_enet_wr_indirect(struct xgene_indirect_ctl *ctl, 52 u32 wr_addr, u32 wr_data) 53 { 54 int i; 55 56 iowrite32(wr_addr, ctl->addr); 57 iowrite32(wr_data, ctl->ctl); 58 iowrite32(XGENE_ENET_WR_CMD, ctl->cmd); 59 60 /* wait for write command to complete */ 61 for (i = 0; i < 10; i++) { 62 if (ioread32(ctl->cmd_done)) { 63 iowrite32(0, ctl->cmd); 64 return true; 65 } 66 udelay(1); 67 } 68 69 return false; 70 } 71 72 static void xgene_enet_wr_mac(struct xgene_enet_pdata *p, 73 u32 wr_addr, u32 wr_data) 74 { 75 struct xgene_indirect_ctl ctl = { 76 .addr = p->mcx_mac_addr + MAC_ADDR_REG_OFFSET, 77 .ctl = p->mcx_mac_addr + MAC_WRITE_REG_OFFSET, 78 .cmd = p->mcx_mac_addr + MAC_COMMAND_REG_OFFSET, 79 .cmd_done = p->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET 80 }; 81 82 if (!xgene_enet_wr_indirect(&ctl, wr_addr, wr_data)) 83 netdev_err(p->ndev, "mac write failed, addr: %04x\n", wr_addr); 84 } 85 86 static u32 xgene_enet_rd_csr(struct xgene_enet_pdata *p, u32 offset) 87 { 88 return ioread32(p->eth_csr_addr + offset); 89 } 90 91 static u32 xgene_enet_rd_diag_csr(struct xgene_enet_pdata *p, u32 offset) 92 { 93 return ioread32(p->eth_diag_csr_addr + offset); 94 } 95 96 static u32 xgene_enet_rd_indirect(struct xgene_indirect_ctl *ctl, u32 rd_addr) 97 { 98 u32 rd_data; 99 int i; 100 101 iowrite32(rd_addr, ctl->addr); 102 iowrite32(XGENE_ENET_RD_CMD, ctl->cmd); 103 104 /* wait for read command to complete */ 105 for (i = 0; i < 10; i++) { 106 if (ioread32(ctl->cmd_done)) { 107 rd_data = ioread32(ctl->ctl); 108 iowrite32(0, ctl->cmd); 109 110 return rd_data; 111 } 112 udelay(1); 113 } 114 115 pr_err("%s: mac read failed, addr: %04x\n", __func__, rd_addr); 116 117 return 0; 118 } 119 120 static u32 xgene_enet_rd_mac(struct xgene_enet_pdata *p, u32 rd_addr) 121 { 122 struct xgene_indirect_ctl ctl = { 123 .addr = p->mcx_mac_addr + MAC_ADDR_REG_OFFSET, 124 .ctl = p->mcx_mac_addr + MAC_READ_REG_OFFSET, 125 .cmd = p->mcx_mac_addr + MAC_COMMAND_REG_OFFSET, 126 .cmd_done = p->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET 127 }; 128 129 return xgene_enet_rd_indirect(&ctl, rd_addr); 130 } 131 132 static int xgene_enet_ecc_init(struct xgene_enet_pdata *p) 133 { 134 struct net_device *ndev = p->ndev; 135 u32 data; 136 int i = 0; 137 138 xgene_enet_wr_diag_csr(p, ENET_CFG_MEM_RAM_SHUTDOWN_ADDR, 0); 139 do { 140 usleep_range(100, 110); 141 data = xgene_enet_rd_diag_csr(p, ENET_BLOCK_MEM_RDY_ADDR); 142 if (data == ~0U) 143 return 0; 144 } while (++i < 10); 145 146 netdev_err(ndev, "Failed to release memory from shutdown\n"); 147 return -ENODEV; 148 } 149 150 static void xgene_enet_config_ring_if_assoc(struct xgene_enet_pdata *p) 151 { 152 u32 val; 153 154 val = (p->enet_id == XGENE_ENET1) ? 0xffffffff : 0; 155 xgene_enet_wr_ring_if(p, ENET_CFGSSQMIWQASSOC_ADDR, val); 156 xgene_enet_wr_ring_if(p, ENET_CFGSSQMIFPQASSOC_ADDR, val); 157 } 158 159 static void xgene_mii_phy_write(struct xgene_enet_pdata *p, u8 phy_id, 160 u32 reg, u16 data) 161 { 162 u32 addr, wr_data, done; 163 int i; 164 165 addr = PHY_ADDR(phy_id) | REG_ADDR(reg); 166 xgene_enet_wr_mac(p, MII_MGMT_ADDRESS_ADDR, addr); 167 168 wr_data = PHY_CONTROL(data); 169 xgene_enet_wr_mac(p, MII_MGMT_CONTROL_ADDR, wr_data); 170 171 for (i = 0; i < 10; i++) { 172 done = xgene_enet_rd_mac(p, MII_MGMT_INDICATORS_ADDR); 173 if (!(done & BUSY_MASK)) 174 return; 175 usleep_range(10, 20); 176 } 177 178 netdev_err(p->ndev, "MII_MGMT write failed\n"); 179 } 180 181 static u32 xgene_mii_phy_read(struct xgene_enet_pdata *p, u8 phy_id, u32 reg) 182 { 183 u32 addr, data, done; 184 int i; 185 186 addr = PHY_ADDR(phy_id) | REG_ADDR(reg); 187 xgene_enet_wr_mac(p, MII_MGMT_ADDRESS_ADDR, addr); 188 xgene_enet_wr_mac(p, MII_MGMT_COMMAND_ADDR, READ_CYCLE_MASK); 189 190 for (i = 0; i < 10; i++) { 191 done = xgene_enet_rd_mac(p, MII_MGMT_INDICATORS_ADDR); 192 if (!(done & BUSY_MASK)) { 193 data = xgene_enet_rd_mac(p, MII_MGMT_STATUS_ADDR); 194 xgene_enet_wr_mac(p, MII_MGMT_COMMAND_ADDR, 0); 195 196 return data; 197 } 198 usleep_range(10, 20); 199 } 200 201 netdev_err(p->ndev, "MII_MGMT read failed\n"); 202 203 return 0; 204 } 205 206 static void xgene_sgmac_reset(struct xgene_enet_pdata *p) 207 { 208 xgene_enet_wr_mac(p, MAC_CONFIG_1_ADDR, SOFT_RESET1); 209 xgene_enet_wr_mac(p, MAC_CONFIG_1_ADDR, 0); 210 } 211 212 static void xgene_sgmac_set_mac_addr(struct xgene_enet_pdata *p) 213 { 214 u32 addr0, addr1; 215 u8 *dev_addr = p->ndev->dev_addr; 216 217 addr0 = (dev_addr[3] << 24) | (dev_addr[2] << 16) | 218 (dev_addr[1] << 8) | dev_addr[0]; 219 xgene_enet_wr_mac(p, STATION_ADDR0_ADDR, addr0); 220 221 addr1 = xgene_enet_rd_mac(p, STATION_ADDR1_ADDR); 222 addr1 |= (dev_addr[5] << 24) | (dev_addr[4] << 16); 223 xgene_enet_wr_mac(p, STATION_ADDR1_ADDR, addr1); 224 } 225 226 static u32 xgene_enet_link_status(struct xgene_enet_pdata *p) 227 { 228 u32 data; 229 230 data = xgene_mii_phy_read(p, INT_PHY_ADDR, 231 SGMII_BASE_PAGE_ABILITY_ADDR >> 2); 232 233 return data & LINK_UP; 234 } 235 236 static void xgene_sgmac_init(struct xgene_enet_pdata *p) 237 { 238 u32 data, loop = 10; 239 u32 offset = p->port_id * 4; 240 u32 enet_spare_cfg_reg, rsif_config_reg; 241 u32 cfg_bypass_reg, rx_dv_gate_reg; 242 243 xgene_sgmac_reset(p); 244 245 /* Enable auto-negotiation */ 246 xgene_mii_phy_write(p, INT_PHY_ADDR, SGMII_CONTROL_ADDR >> 2, 0x1000); 247 xgene_mii_phy_write(p, INT_PHY_ADDR, SGMII_TBI_CONTROL_ADDR >> 2, 0); 248 249 while (loop--) { 250 data = xgene_mii_phy_read(p, INT_PHY_ADDR, 251 SGMII_STATUS_ADDR >> 2); 252 if ((data & AUTO_NEG_COMPLETE) && (data & LINK_STATUS)) 253 break; 254 usleep_range(1000, 2000); 255 } 256 if (!(data & AUTO_NEG_COMPLETE) || !(data & LINK_STATUS)) 257 netdev_err(p->ndev, "Auto-negotiation failed\n"); 258 259 data = xgene_enet_rd_mac(p, MAC_CONFIG_2_ADDR); 260 ENET_INTERFACE_MODE2_SET(&data, 2); 261 xgene_enet_wr_mac(p, MAC_CONFIG_2_ADDR, data | FULL_DUPLEX2); 262 xgene_enet_wr_mac(p, INTERFACE_CONTROL_ADDR, ENET_GHD_MODE); 263 264 if (p->enet_id == XGENE_ENET1) { 265 enet_spare_cfg_reg = ENET_SPARE_CFG_REG_ADDR; 266 rsif_config_reg = RSIF_CONFIG_REG_ADDR; 267 cfg_bypass_reg = CFG_BYPASS_ADDR; 268 rx_dv_gate_reg = SG_RX_DV_GATE_REG_0_ADDR; 269 } else { 270 enet_spare_cfg_reg = XG_ENET_SPARE_CFG_REG_ADDR; 271 rsif_config_reg = XG_RSIF_CONFIG_REG_ADDR; 272 cfg_bypass_reg = XG_CFG_BYPASS_ADDR; 273 rx_dv_gate_reg = XG_MCX_RX_DV_GATE_REG_0_ADDR; 274 } 275 276 data = xgene_enet_rd_csr(p, enet_spare_cfg_reg); 277 data |= MPA_IDLE_WITH_QMI_EMPTY; 278 xgene_enet_wr_csr(p, enet_spare_cfg_reg, data); 279 280 xgene_sgmac_set_mac_addr(p); 281 282 /* Adjust MDC clock frequency */ 283 data = xgene_enet_rd_mac(p, MII_MGMT_CONFIG_ADDR); 284 MGMT_CLOCK_SEL_SET(&data, 7); 285 xgene_enet_wr_mac(p, MII_MGMT_CONFIG_ADDR, data); 286 287 /* Enable drop if bufpool not available */ 288 data = xgene_enet_rd_csr(p, rsif_config_reg); 289 data |= CFG_RSIF_FPBUFF_TIMEOUT_EN; 290 xgene_enet_wr_csr(p, rsif_config_reg, data); 291 292 /* Bypass traffic gating */ 293 xgene_enet_wr_csr(p, XG_ENET_SPARE_CFG_REG_1_ADDR, 0x84); 294 xgene_enet_wr_csr(p, cfg_bypass_reg, RESUME_TX); 295 xgene_enet_wr_mcx_csr(p, rx_dv_gate_reg + offset, RESUME_RX0); 296 } 297 298 static void xgene_sgmac_rxtx(struct xgene_enet_pdata *p, u32 bits, bool set) 299 { 300 u32 data; 301 302 data = xgene_enet_rd_mac(p, MAC_CONFIG_1_ADDR); 303 304 if (set) 305 data |= bits; 306 else 307 data &= ~bits; 308 309 xgene_enet_wr_mac(p, MAC_CONFIG_1_ADDR, data); 310 } 311 312 static void xgene_sgmac_rx_enable(struct xgene_enet_pdata *p) 313 { 314 xgene_sgmac_rxtx(p, RX_EN, true); 315 } 316 317 static void xgene_sgmac_tx_enable(struct xgene_enet_pdata *p) 318 { 319 xgene_sgmac_rxtx(p, TX_EN, true); 320 } 321 322 static void xgene_sgmac_rx_disable(struct xgene_enet_pdata *p) 323 { 324 xgene_sgmac_rxtx(p, RX_EN, false); 325 } 326 327 static void xgene_sgmac_tx_disable(struct xgene_enet_pdata *p) 328 { 329 xgene_sgmac_rxtx(p, TX_EN, false); 330 } 331 332 static int xgene_enet_reset(struct xgene_enet_pdata *p) 333 { 334 if (!xgene_ring_mgr_init(p)) 335 return -ENODEV; 336 337 if (!IS_ERR(p->clk)) { 338 clk_prepare_enable(p->clk); 339 clk_disable_unprepare(p->clk); 340 clk_prepare_enable(p->clk); 341 } 342 343 xgene_enet_ecc_init(p); 344 xgene_enet_config_ring_if_assoc(p); 345 346 return 0; 347 } 348 349 static void xgene_enet_cle_bypass(struct xgene_enet_pdata *p, 350 u32 dst_ring_num, u16 bufpool_id) 351 { 352 u32 data, fpsel; 353 u32 cle_bypass_reg0, cle_bypass_reg1; 354 u32 offset = p->port_id * MAC_OFFSET; 355 356 if (p->enet_id == XGENE_ENET1) { 357 cle_bypass_reg0 = CLE_BYPASS_REG0_0_ADDR; 358 cle_bypass_reg1 = CLE_BYPASS_REG1_0_ADDR; 359 } else { 360 cle_bypass_reg0 = XCLE_BYPASS_REG0_ADDR; 361 cle_bypass_reg1 = XCLE_BYPASS_REG1_ADDR; 362 } 363 364 data = CFG_CLE_BYPASS_EN0; 365 xgene_enet_wr_csr(p, cle_bypass_reg0 + offset, data); 366 367 fpsel = xgene_enet_ring_bufnum(bufpool_id) - 0x20; 368 data = CFG_CLE_DSTQID0(dst_ring_num) | CFG_CLE_FPSEL0(fpsel); 369 xgene_enet_wr_csr(p, cle_bypass_reg1 + offset, data); 370 } 371 372 static void xgene_enet_shutdown(struct xgene_enet_pdata *p) 373 { 374 if (!IS_ERR(p->clk)) 375 clk_disable_unprepare(p->clk); 376 } 377 378 static void xgene_enet_link_state(struct work_struct *work) 379 { 380 struct xgene_enet_pdata *p = container_of(to_delayed_work(work), 381 struct xgene_enet_pdata, link_work); 382 struct net_device *ndev = p->ndev; 383 u32 link, poll_interval; 384 385 link = xgene_enet_link_status(p); 386 if (link) { 387 if (!netif_carrier_ok(ndev)) { 388 netif_carrier_on(ndev); 389 xgene_sgmac_init(p); 390 xgene_sgmac_rx_enable(p); 391 xgene_sgmac_tx_enable(p); 392 netdev_info(ndev, "Link is Up - 1Gbps\n"); 393 } 394 poll_interval = PHY_POLL_LINK_ON; 395 } else { 396 if (netif_carrier_ok(ndev)) { 397 xgene_sgmac_rx_disable(p); 398 xgene_sgmac_tx_disable(p); 399 netif_carrier_off(ndev); 400 netdev_info(ndev, "Link is Down\n"); 401 } 402 poll_interval = PHY_POLL_LINK_OFF; 403 } 404 405 schedule_delayed_work(&p->link_work, poll_interval); 406 } 407 408 struct xgene_mac_ops xgene_sgmac_ops = { 409 .init = xgene_sgmac_init, 410 .reset = xgene_sgmac_reset, 411 .rx_enable = xgene_sgmac_rx_enable, 412 .tx_enable = xgene_sgmac_tx_enable, 413 .rx_disable = xgene_sgmac_rx_disable, 414 .tx_disable = xgene_sgmac_tx_disable, 415 .set_mac_addr = xgene_sgmac_set_mac_addr, 416 .link_state = xgene_enet_link_state 417 }; 418 419 struct xgene_port_ops xgene_sgport_ops = { 420 .reset = xgene_enet_reset, 421 .cle_bypass = xgene_enet_cle_bypass, 422 .shutdown = xgene_enet_shutdown 423 }; 424