1*1ccea77eSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 2ed9b7da0SIyappan Subramanian /* Applied Micro X-Gene SoC Ethernet Driver 3ed9b7da0SIyappan Subramanian * 4ed9b7da0SIyappan Subramanian * Copyright (c) 2015, Applied Micro Circuits Corporation 5ed9b7da0SIyappan Subramanian * Author: Iyappan Subramanian <isubramanian@apm.com> 6ed9b7da0SIyappan Subramanian */ 7ed9b7da0SIyappan Subramanian 8ed9b7da0SIyappan Subramanian #ifndef __XGENE_ENET_RING2_H__ 9ed9b7da0SIyappan Subramanian #define __XGENE_ENET_RING2_H__ 10ed9b7da0SIyappan Subramanian 11ed9b7da0SIyappan Subramanian #include "xgene_enet_main.h" 12ed9b7da0SIyappan Subramanian 13ed9b7da0SIyappan Subramanian #define X2_NUM_RING_CONFIG 6 14ed9b7da0SIyappan Subramanian 15ed9b7da0SIyappan Subramanian #define INTR_MBOX_SIZE 1024 16ed9b7da0SIyappan Subramanian #define CSR_VMID0_INTR_MBOX 0x0270 17ed9b7da0SIyappan Subramanian #define INTR_CLEAR BIT(23) 18ed9b7da0SIyappan Subramanian 19ed9b7da0SIyappan Subramanian #define X2_MSG_AM_POS 10 20ed9b7da0SIyappan Subramanian #define X2_QBASE_AM_POS 11 21ed9b7da0SIyappan Subramanian #define X2_INTLINE_POS 24 22ed9b7da0SIyappan Subramanian #define X2_INTLINE_LEN 5 23ed9b7da0SIyappan Subramanian #define X2_CFGCRID_POS 29 24ed9b7da0SIyappan Subramanian #define X2_CFGCRID_LEN 3 25ed9b7da0SIyappan Subramanian #define X2_SELTHRSH_POS 7 26ed9b7da0SIyappan Subramanian #define X2_SELTHRSH_LEN 3 27ed9b7da0SIyappan Subramanian #define X2_RINGTYPE_POS 23 28ed9b7da0SIyappan Subramanian #define X2_RINGTYPE_LEN 2 29ed9b7da0SIyappan Subramanian #define X2_DEQINTEN_POS 29 30ed9b7da0SIyappan Subramanian #define X2_RECOMTIMEOUT_POS 0 31ed9b7da0SIyappan Subramanian #define X2_RECOMTIMEOUT_LEN 7 32ed9b7da0SIyappan Subramanian #define X2_NUMMSGSINQ_POS 0 33ed9b7da0SIyappan Subramanian #define X2_NUMMSGSINQ_LEN 17 34ed9b7da0SIyappan Subramanian 35ed9b7da0SIyappan Subramanian extern struct xgene_ring_ops xgene_ring2_ops; 36ed9b7da0SIyappan Subramanian 37ed9b7da0SIyappan Subramanian #endif /* __XGENE_ENET_RING2_H__ */ 38