1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) 2 /* 3 * Copyright (c) 2014-2025, Advanced Micro Devices, Inc. 4 * Copyright (c) 2014, Synopsys, Inc. 5 * All rights reserved 6 */ 7 8 #ifndef __XGBE_H__ 9 #define __XGBE_H__ 10 11 #include <linux/dma-mapping.h> 12 #include <linux/netdevice.h> 13 #include <linux/workqueue.h> 14 #include <linux/phy.h> 15 #include <linux/if_vlan.h> 16 #include <linux/bitops.h> 17 #include <linux/ptp_clock_kernel.h> 18 #include <linux/timecounter.h> 19 #include <linux/net_tstamp.h> 20 #include <net/dcbnl.h> 21 #include <linux/completion.h> 22 #include <linux/cpumask.h> 23 #include <linux/interrupt.h> 24 #include <linux/dcache.h> 25 #include <linux/ethtool.h> 26 #include <linux/list.h> 27 28 #define XGBE_DRV_NAME "amd-xgbe" 29 #define XGBE_DRV_DESC "AMD 10 Gigabit Ethernet Driver" 30 31 /* Descriptor related defines */ 32 #define XGBE_TX_DESC_CNT 512 33 #define XGBE_TX_DESC_MIN_FREE (XGBE_TX_DESC_CNT >> 3) 34 #define XGBE_TX_DESC_MAX_PROC (XGBE_TX_DESC_CNT >> 1) 35 #define XGBE_RX_DESC_CNT 512 36 37 #define XGBE_TX_DESC_CNT_MIN 64 38 #define XGBE_TX_DESC_CNT_MAX 4096 39 #define XGBE_RX_DESC_CNT_MIN 64 40 #define XGBE_RX_DESC_CNT_MAX 4096 41 42 #define XGBE_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1)) 43 44 /* Descriptors required for maximum contiguous TSO/GSO packet */ 45 #define XGBE_TX_MAX_SPLIT \ 46 ((GSO_LEGACY_MAX_SIZE / XGBE_TX_MAX_BUF_SIZE) + 1) 47 48 /* Maximum possible descriptors needed for an SKB: 49 * - Maximum number of SKB frags 50 * - Maximum descriptors for contiguous TSO/GSO packet 51 * - Possible context descriptor 52 * - Possible TSO header descriptor 53 */ 54 #define XGBE_TX_MAX_DESCS (MAX_SKB_FRAGS + XGBE_TX_MAX_SPLIT + 2) 55 56 #define XGBE_RX_MIN_BUF_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN) 57 #define XGBE_RX_BUF_ALIGN 64 58 #define XGBE_SKB_ALLOC_SIZE 256 59 #define XGBE_SPH_HDSMS_SIZE 2 /* Keep in sync with SKB_ALLOC_SIZE */ 60 61 #define XGBE_MAX_DMA_CHANNELS 16 62 #define XGBE_MAX_QUEUES 16 63 #define XGBE_PRIORITY_QUEUES 8 64 #define XGBE_DMA_STOP_TIMEOUT 1 65 66 /* DMA cache settings - Outer sharable, write-back, write-allocate */ 67 #define XGBE_DMA_OS_ARCR 0x002b2b2b 68 #define XGBE_DMA_OS_AWCR 0x2f2f2f2f 69 70 /* DMA cache settings - System, no caches used */ 71 #define XGBE_DMA_SYS_ARCR 0x00303030 72 #define XGBE_DMA_SYS_AWCR 0x30303030 73 74 /* DMA cache settings - PCI device */ 75 #define XGBE_DMA_PCI_ARCR 0x000f0f0f 76 #define XGBE_DMA_PCI_AWCR 0x0f0f0f0f 77 #define XGBE_DMA_PCI_AWARCR 0x00000f0f 78 79 /* DMA channel interrupt modes */ 80 #define XGBE_IRQ_MODE_EDGE 0 81 #define XGBE_IRQ_MODE_LEVEL 1 82 83 #define XGBE_ETH_FRAME_HDR (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN) 84 #define XGMAC_MIN_PACKET 60 85 #define XGMAC_STD_PACKET_MTU 1500 86 #define XGMAC_MAX_STD_PACKET 1518 87 #define XGMAC_JUMBO_PACKET_MTU 9000 88 #define XGMAC_MAX_JUMBO_PACKET 9018 89 #define XGMAC_GIANT_PACKET_MTU 16368 90 #define XGMAC_ETH_PREAMBLE (12 + 8) /* Inter-frame gap + preamble */ 91 92 #define XGMAC_PFC_DATA_LEN 46 93 #define XGMAC_PFC_DELAYS 14000 94 95 #define XGMAC_PRIO_QUEUES(_cnt) \ 96 min_t(unsigned int, IEEE_8021QAZ_MAX_TCS, (_cnt)) 97 98 /* Common property names */ 99 #define XGBE_MAC_ADDR_PROPERTY "mac-address" 100 #define XGBE_PHY_MODE_PROPERTY "phy-mode" 101 #define XGBE_DMA_IRQS_PROPERTY "amd,per-channel-interrupt" 102 #define XGBE_SPEEDSET_PROPERTY "amd,speed-set" 103 104 /* Device-tree clock names */ 105 #define XGBE_DMA_CLOCK "dma_clk" 106 #define XGBE_PTP_CLOCK "ptp_clk" 107 108 /* ACPI property names */ 109 #define XGBE_ACPI_DMA_FREQ "amd,dma-freq" 110 #define XGBE_ACPI_PTP_FREQ "amd,ptp-freq" 111 112 /* PCI BAR mapping */ 113 #define XGBE_XGMAC_BAR 0 114 #define XGBE_XPCS_BAR 1 115 #define XGBE_MAC_PROP_OFFSET 0x1d000 116 #define XGBE_I2C_CTRL_OFFSET 0x1e000 117 118 /* PCI MSI/MSIx support */ 119 #define XGBE_MSI_BASE_COUNT 4 120 #define XGBE_MSI_MIN_COUNT (XGBE_MSI_BASE_COUNT + 1) 121 122 /* PCI clock frequencies */ 123 #define XGBE_V2_DMA_CLOCK_FREQ 500000000 /* 500 MHz */ 124 #define XGBE_V2_PTP_CLOCK_FREQ 125000000 /* 125 MHz */ 125 126 /* Timestamp support - values based on 50MHz PTP clock 127 * 50MHz => 20 nsec 128 */ 129 #define XGBE_TSTAMP_SSINC 20 130 #define XGBE_TSTAMP_SNSINC 0 131 132 /* Driver PMT macros */ 133 #define XGMAC_DRIVER_CONTEXT 1 134 #define XGMAC_IOCTL_CONTEXT 2 135 136 #define XGMAC_FIFO_MIN_ALLOC 2048 137 #define XGMAC_FIFO_UNIT 256 138 #define XGMAC_FIFO_ALIGN(_x) \ 139 (((_x) + XGMAC_FIFO_UNIT - 1) & ~(XGMAC_FIFO_UNIT - 1)) 140 #define XGMAC_FIFO_FC_OFF 2048 141 #define XGMAC_FIFO_FC_MIN 4096 142 143 #define XGBE_TC_MIN_QUANTUM 10 144 145 /* Helper macro for descriptor handling 146 * Always use XGBE_GET_DESC_DATA to access the descriptor data 147 * since the index is free-running and needs to be and-ed 148 * with the descriptor count value of the ring to index to 149 * the proper descriptor data. 150 */ 151 #define XGBE_GET_DESC_DATA(_ring, _idx) \ 152 ((_ring)->rdata + \ 153 ((_idx) & ((_ring)->rdesc_count - 1))) 154 155 /* Default coalescing parameters */ 156 #define XGMAC_INIT_DMA_TX_USECS 1000 157 #define XGMAC_INIT_DMA_TX_FRAMES 25 158 159 #define XGMAC_MAX_DMA_RIWT 0xff 160 #define XGMAC_INIT_DMA_RX_USECS 30 161 #define XGMAC_INIT_DMA_RX_FRAMES 25 162 163 /* Flow control queue count */ 164 #define XGMAC_MAX_FLOW_CONTROL_QUEUES 8 165 166 /* Flow control threshold units */ 167 #define XGMAC_FLOW_CONTROL_UNIT 512 168 #define XGMAC_FLOW_CONTROL_ALIGN(_x) \ 169 (((_x) + XGMAC_FLOW_CONTROL_UNIT - 1) & ~(XGMAC_FLOW_CONTROL_UNIT - 1)) 170 #define XGMAC_FLOW_CONTROL_VALUE(_x) \ 171 (((_x) < 1024) ? 0 : ((_x) / XGMAC_FLOW_CONTROL_UNIT) - 2) 172 #define XGMAC_FLOW_CONTROL_MAX 33280 173 174 /* Maximum MAC address hash table size (256 bits = 8 bytes) */ 175 #define XGBE_MAC_HASH_TABLE_SIZE 8 176 177 /* Receive Side Scaling */ 178 #define XGBE_RSS_HASH_KEY_SIZE 40 179 #define XGBE_RSS_MAX_TABLE_SIZE 256 180 #define XGBE_RSS_LOOKUP_TABLE_TYPE 0 181 #define XGBE_RSS_HASH_KEY_TYPE 1 182 183 /* Auto-negotiation */ 184 #define XGBE_AN_MS_TIMEOUT 500 185 #define XGBE_LINK_TIMEOUT 5 186 #define XGBE_KR_TRAINING_WAIT_ITER 50 187 188 #define XGBE_SGMII_AN_LINK_DUPLEX BIT(1) 189 #define XGBE_SGMII_AN_LINK_SPEED (BIT(2) | BIT(3)) 190 #define XGBE_SGMII_AN_LINK_SPEED_10 0x00 191 #define XGBE_SGMII_AN_LINK_SPEED_100 0x04 192 #define XGBE_SGMII_AN_LINK_SPEED_1000 0x08 193 #define XGBE_SGMII_AN_LINK_STATUS BIT(4) 194 195 /* ECC correctable error notification window (seconds) */ 196 #define XGBE_ECC_LIMIT 60 197 198 /* MDIO port types */ 199 #define XGMAC_MAX_C22_PORT 3 200 201 /* Link mode bit operations */ 202 #define XGBE_ZERO_SUP(_ls) \ 203 ethtool_link_ksettings_zero_link_mode((_ls), supported) 204 205 #define XGBE_SET_SUP(_ls, _mode) \ 206 ethtool_link_ksettings_add_link_mode((_ls), supported, _mode) 207 208 #define XGBE_CLR_SUP(_ls, _mode) \ 209 ethtool_link_ksettings_del_link_mode((_ls), supported, _mode) 210 211 #define XGBE_IS_SUP(_ls, _mode) \ 212 ethtool_link_ksettings_test_link_mode((_ls), supported, _mode) 213 214 #define XGBE_ZERO_ADV(_ls) \ 215 ethtool_link_ksettings_zero_link_mode((_ls), advertising) 216 217 #define XGBE_SET_ADV(_ls, _mode) \ 218 ethtool_link_ksettings_add_link_mode((_ls), advertising, _mode) 219 220 #define XGBE_CLR_ADV(_ls, _mode) \ 221 ethtool_link_ksettings_del_link_mode((_ls), advertising, _mode) 222 223 #define XGBE_ADV(_ls, _mode) \ 224 ethtool_link_ksettings_test_link_mode((_ls), advertising, _mode) 225 226 #define XGBE_ZERO_LP_ADV(_ls) \ 227 ethtool_link_ksettings_zero_link_mode((_ls), lp_advertising) 228 229 #define XGBE_SET_LP_ADV(_ls, _mode) \ 230 ethtool_link_ksettings_add_link_mode((_ls), lp_advertising, _mode) 231 232 #define XGBE_CLR_LP_ADV(_ls, _mode) \ 233 ethtool_link_ksettings_del_link_mode((_ls), lp_advertising, _mode) 234 235 #define XGBE_LP_ADV(_ls, _mode) \ 236 ethtool_link_ksettings_test_link_mode((_ls), lp_advertising, _mode) 237 238 #define XGBE_LM_COPY(_dst, _dname, _src, _sname) \ 239 bitmap_copy((_dst)->link_modes._dname, \ 240 (_src)->link_modes._sname, \ 241 __ETHTOOL_LINK_MODE_MASK_NBITS) 242 243 /* XGBE PCI device id */ 244 #define XGBE_RV_PCI_DEVICE_ID 0x15d0 245 #define XGBE_YC_PCI_DEVICE_ID 0x14b5 246 #define XGBE_RN_PCI_DEVICE_ID 0x1630 247 248 /* Generic low and high masks */ 249 #define XGBE_GEN_HI_MASK GENMASK(31, 16) 250 #define XGBE_GEN_LO_MASK GENMASK(15, 0) 251 252 struct xgbe_prv_data; 253 254 struct xgbe_packet_data { 255 struct sk_buff *skb; 256 257 unsigned int attributes; 258 259 unsigned int errors; 260 261 unsigned int rdesc_count; 262 unsigned int length; 263 264 unsigned int header_len; 265 unsigned int tcp_header_len; 266 unsigned int tcp_payload_len; 267 unsigned short mss; 268 269 unsigned short vlan_ctag; 270 271 u64 rx_tstamp; 272 273 u32 rss_hash; 274 enum pkt_hash_types rss_hash_type; 275 276 unsigned int tx_packets; 277 unsigned int tx_bytes; 278 }; 279 280 /* Common Rx and Tx descriptor mapping */ 281 struct xgbe_ring_desc { 282 __le32 desc0; 283 __le32 desc1; 284 __le32 desc2; 285 __le32 desc3; 286 }; 287 288 /* Page allocation related values */ 289 struct xgbe_page_alloc { 290 struct page *pages; 291 unsigned int pages_len; 292 unsigned int pages_offset; 293 294 dma_addr_t pages_dma; 295 }; 296 297 /* Ring entry buffer data */ 298 struct xgbe_buffer_data { 299 struct xgbe_page_alloc pa; 300 struct xgbe_page_alloc pa_unmap; 301 302 dma_addr_t dma_base; 303 unsigned long dma_off; 304 unsigned int dma_len; 305 }; 306 307 /* Tx-related ring data */ 308 struct xgbe_tx_ring_data { 309 unsigned int packets; /* BQL packet count */ 310 unsigned int bytes; /* BQL byte count */ 311 }; 312 313 /* Rx-related ring data */ 314 struct xgbe_rx_ring_data { 315 struct xgbe_buffer_data hdr; /* Header locations */ 316 struct xgbe_buffer_data buf; /* Payload locations */ 317 318 unsigned short hdr_len; /* Length of received header */ 319 unsigned short len; /* Length of received packet */ 320 }; 321 322 /* Structure used to hold information related to the descriptor 323 * and the packet associated with the descriptor (always use 324 * the XGBE_GET_DESC_DATA macro to access this data from the ring) 325 */ 326 struct xgbe_ring_data { 327 struct xgbe_ring_desc *rdesc; /* Virtual address of descriptor */ 328 dma_addr_t rdesc_dma; /* DMA address of descriptor */ 329 330 struct sk_buff *skb; /* Virtual address of SKB */ 331 dma_addr_t skb_dma; /* DMA address of SKB data */ 332 unsigned int skb_dma_len; /* Length of SKB DMA area */ 333 334 struct xgbe_tx_ring_data tx; /* Tx-related data */ 335 struct xgbe_rx_ring_data rx; /* Rx-related data */ 336 337 unsigned int mapped_as_page; 338 339 /* Incomplete receive save location. If the budget is exhausted 340 * or the last descriptor (last normal descriptor or a following 341 * context descriptor) has not been DMA'd yet the current state 342 * of the receive processing needs to be saved. 343 */ 344 unsigned int state_saved; 345 struct { 346 struct sk_buff *skb; 347 unsigned int len; 348 unsigned int error; 349 } state; 350 }; 351 352 struct xgbe_ring { 353 /* Ring lock - used just for TX rings at the moment */ 354 spinlock_t lock; 355 356 /* Per packet related information */ 357 struct xgbe_packet_data packet_data; 358 359 /* Virtual/DMA addresses and count of allocated descriptor memory */ 360 struct xgbe_ring_desc *rdesc; 361 dma_addr_t rdesc_dma; 362 unsigned int rdesc_count; 363 364 /* Array of descriptor data corresponding the descriptor memory 365 * (always use the XGBE_GET_DESC_DATA macro to access this data) 366 */ 367 struct xgbe_ring_data *rdata; 368 369 /* Page allocation for RX buffers */ 370 struct xgbe_page_alloc rx_hdr_pa; 371 struct xgbe_page_alloc rx_buf_pa; 372 int node; 373 374 /* Ring index values 375 * cur - Tx: index of descriptor to be used for current transfer 376 * Rx: index of descriptor to check for packet availability 377 * dirty - Tx: index of descriptor to check for transfer complete 378 * Rx: index of descriptor to check for buffer reallocation 379 */ 380 unsigned int cur; 381 unsigned int dirty; 382 383 /* Coalesce frame count used for interrupt bit setting */ 384 unsigned int coalesce_count; 385 386 union { 387 struct { 388 unsigned int queue_stopped; 389 unsigned int xmit_more; 390 unsigned short cur_mss; 391 unsigned short cur_vlan_ctag; 392 } tx; 393 }; 394 } ____cacheline_aligned; 395 396 /* Structure used to describe the descriptor rings associated with 397 * a DMA channel. 398 */ 399 struct xgbe_channel { 400 char name[20]; 401 402 /* Address of private data area for device */ 403 struct xgbe_prv_data *pdata; 404 405 /* Queue index and base address of queue's DMA registers */ 406 unsigned int queue_index; 407 void __iomem *dma_regs; 408 409 /* Per channel interrupt irq number */ 410 int dma_irq; 411 char dma_irq_name[IFNAMSIZ + 32]; 412 413 /* Netdev related settings */ 414 struct napi_struct napi; 415 416 /* Per channel interrupt enablement tracker */ 417 unsigned int curr_ier; 418 unsigned int saved_ier; 419 420 unsigned int tx_timer_active; 421 struct timer_list tx_timer; 422 423 struct xgbe_ring *tx_ring; 424 struct xgbe_ring *rx_ring; 425 426 int node; 427 cpumask_t affinity_mask; 428 } ____cacheline_aligned; 429 430 enum xgbe_state { 431 XGBE_DOWN, 432 XGBE_LINK_INIT, 433 XGBE_LINK_ERR, 434 XGBE_STOPPED, 435 }; 436 437 enum xgbe_int { 438 XGMAC_INT_DMA_CH_SR_TI, 439 XGMAC_INT_DMA_CH_SR_TPS, 440 XGMAC_INT_DMA_CH_SR_TBU, 441 XGMAC_INT_DMA_CH_SR_RI, 442 XGMAC_INT_DMA_CH_SR_RBU, 443 XGMAC_INT_DMA_CH_SR_RPS, 444 XGMAC_INT_DMA_CH_SR_TI_RI, 445 XGMAC_INT_DMA_CH_SR_FBE, 446 XGMAC_INT_DMA_ALL, 447 }; 448 449 enum xgbe_int_state { 450 XGMAC_INT_STATE_SAVE, 451 XGMAC_INT_STATE_RESTORE, 452 }; 453 454 enum xgbe_ecc_sec { 455 XGBE_ECC_SEC_TX, 456 XGBE_ECC_SEC_RX, 457 XGBE_ECC_SEC_DESC, 458 }; 459 460 enum xgbe_speed { 461 XGBE_SPEED_1000 = 0, 462 XGBE_SPEED_2500, 463 XGBE_SPEED_10000, 464 XGBE_SPEEDS, 465 }; 466 467 enum xgbe_xpcs_access { 468 XGBE_XPCS_ACCESS_V1 = 0, 469 XGBE_XPCS_ACCESS_V2, 470 XGBE_XPCS_ACCESS_V3, 471 }; 472 473 enum xgbe_an_mode { 474 XGBE_AN_MODE_CL73 = 0, 475 XGBE_AN_MODE_CL73_REDRV, 476 XGBE_AN_MODE_CL37, 477 XGBE_AN_MODE_CL37_SGMII, 478 XGBE_AN_MODE_NONE, 479 }; 480 481 enum xgbe_an { 482 XGBE_AN_READY = 0, 483 XGBE_AN_PAGE_RECEIVED, 484 XGBE_AN_INCOMPAT_LINK, 485 XGBE_AN_COMPLETE, 486 XGBE_AN_NO_LINK, 487 XGBE_AN_ERROR, 488 }; 489 490 enum xgbe_rx { 491 XGBE_RX_BPA = 0, 492 XGBE_RX_XNP, 493 XGBE_RX_COMPLETE, 494 XGBE_RX_ERROR, 495 }; 496 497 enum xgbe_mode { 498 XGBE_MODE_KX_1000 = 0, 499 XGBE_MODE_KX_2500, 500 XGBE_MODE_KR, 501 XGBE_MODE_X, 502 XGBE_MODE_SGMII_10, 503 XGBE_MODE_SGMII_100, 504 XGBE_MODE_SGMII_1000, 505 XGBE_MODE_SFI, 506 XGBE_MODE_UNKNOWN, 507 }; 508 509 enum xgbe_speedset { 510 XGBE_SPEEDSET_1000_10000 = 0, 511 XGBE_SPEEDSET_2500_10000, 512 }; 513 514 enum xgbe_mdio_mode { 515 XGBE_MDIO_MODE_NONE = 0, 516 XGBE_MDIO_MODE_CL22, 517 XGBE_MDIO_MODE_CL45, 518 }; 519 520 enum xgbe_mb_cmd { 521 XGBE_MB_CMD_POWER_OFF = 0, 522 XGBE_MB_CMD_SET_1G, 523 XGBE_MB_CMD_SET_2_5G, 524 XGBE_MB_CMD_SET_10G_SFI, 525 XGBE_MB_CMD_SET_10G_KR, 526 XGBE_MB_CMD_RRC 527 }; 528 529 enum xgbe_mb_subcmd { 530 XGBE_MB_SUBCMD_NONE = 0, 531 XGBE_MB_SUBCMD_RX_ADAP, 532 533 /* 10GbE SFP subcommands */ 534 XGBE_MB_SUBCMD_ACTIVE = 0, 535 XGBE_MB_SUBCMD_PASSIVE_1M, 536 XGBE_MB_SUBCMD_PASSIVE_3M, 537 XGBE_MB_SUBCMD_PASSIVE_OTHER, 538 539 /* 1GbE Mode subcommands */ 540 XGBE_MB_SUBCMD_10MBITS = 0, 541 XGBE_MB_SUBCMD_100MBITS, 542 XGBE_MB_SUBCMD_1G_SGMII, 543 XGBE_MB_SUBCMD_1G_KX 544 }; 545 546 struct xgbe_phy { 547 struct ethtool_link_ksettings lks; 548 549 int address; 550 551 int autoneg; 552 int speed; 553 int duplex; 554 555 int link; 556 557 int pause_autoneg; 558 int tx_pause; 559 int rx_pause; 560 }; 561 562 enum xgbe_i2c_cmd { 563 XGBE_I2C_CMD_READ = 0, 564 XGBE_I2C_CMD_WRITE, 565 }; 566 567 struct xgbe_i2c_op { 568 enum xgbe_i2c_cmd cmd; 569 570 unsigned int target; 571 572 void *buf; 573 unsigned int len; 574 }; 575 576 struct xgbe_i2c_op_state { 577 struct xgbe_i2c_op *op; 578 579 unsigned int tx_len; 580 unsigned char *tx_buf; 581 582 unsigned int rx_len; 583 unsigned char *rx_buf; 584 585 unsigned int tx_abort_source; 586 587 int ret; 588 }; 589 590 struct xgbe_i2c { 591 unsigned int started; 592 unsigned int max_speed_mode; 593 unsigned int rx_fifo_size; 594 unsigned int tx_fifo_size; 595 596 struct xgbe_i2c_op_state op_state; 597 }; 598 599 struct xgbe_mmc_stats { 600 /* Tx Stats */ 601 u64 txoctetcount_gb; 602 u64 txframecount_gb; 603 u64 txbroadcastframes_g; 604 u64 txmulticastframes_g; 605 u64 tx64octets_gb; 606 u64 tx65to127octets_gb; 607 u64 tx128to255octets_gb; 608 u64 tx256to511octets_gb; 609 u64 tx512to1023octets_gb; 610 u64 tx1024tomaxoctets_gb; 611 u64 txunicastframes_gb; 612 u64 txmulticastframes_gb; 613 u64 txbroadcastframes_gb; 614 u64 txunderflowerror; 615 u64 txoctetcount_g; 616 u64 txframecount_g; 617 u64 txpauseframes; 618 u64 txvlanframes_g; 619 620 /* Rx Stats */ 621 u64 rxframecount_gb; 622 u64 rxoctetcount_gb; 623 u64 rxoctetcount_g; 624 u64 rxbroadcastframes_g; 625 u64 rxmulticastframes_g; 626 u64 rxcrcerror; 627 u64 rxrunterror; 628 u64 rxjabbererror; 629 u64 rxundersize_g; 630 u64 rxoversize_g; 631 u64 rx64octets_gb; 632 u64 rx65to127octets_gb; 633 u64 rx128to255octets_gb; 634 u64 rx256to511octets_gb; 635 u64 rx512to1023octets_gb; 636 u64 rx1024tomaxoctets_gb; 637 u64 rxunicastframes_g; 638 u64 rxlengtherror; 639 u64 rxoutofrangetype; 640 u64 rxpauseframes; 641 u64 rxfifooverflow; 642 u64 rxvlanframes_gb; 643 u64 rxwatchdogerror; 644 }; 645 646 struct xgbe_ext_stats { 647 u64 tx_tso_packets; 648 u64 rx_split_header_packets; 649 u64 rx_buffer_unavailable; 650 651 u64 txq_packets[XGBE_MAX_DMA_CHANNELS]; 652 u64 txq_bytes[XGBE_MAX_DMA_CHANNELS]; 653 u64 rxq_packets[XGBE_MAX_DMA_CHANNELS]; 654 u64 rxq_bytes[XGBE_MAX_DMA_CHANNELS]; 655 656 u64 tx_vxlan_packets; 657 u64 rx_vxlan_packets; 658 u64 rx_csum_errors; 659 u64 rx_vxlan_csum_errors; 660 }; 661 662 struct xgbe_hw_if { 663 int (*tx_complete)(struct xgbe_ring_desc *); 664 665 int (*set_mac_address)(struct xgbe_prv_data *, const u8 *addr); 666 int (*config_rx_mode)(struct xgbe_prv_data *); 667 668 int (*enable_rx_csum)(struct xgbe_prv_data *); 669 int (*disable_rx_csum)(struct xgbe_prv_data *); 670 671 int (*enable_rx_vlan_stripping)(struct xgbe_prv_data *); 672 int (*disable_rx_vlan_stripping)(struct xgbe_prv_data *); 673 int (*enable_rx_vlan_filtering)(struct xgbe_prv_data *); 674 int (*disable_rx_vlan_filtering)(struct xgbe_prv_data *); 675 int (*update_vlan_hash_table)(struct xgbe_prv_data *); 676 677 int (*read_mmd_regs)(struct xgbe_prv_data *, int, int); 678 void (*write_mmd_regs)(struct xgbe_prv_data *, int, int, int); 679 int (*set_speed)(struct xgbe_prv_data *, int); 680 681 int (*set_ext_mii_mode)(struct xgbe_prv_data *, unsigned int, 682 enum xgbe_mdio_mode); 683 int (*read_ext_mii_regs_c22)(struct xgbe_prv_data *, int, int); 684 int (*write_ext_mii_regs_c22)(struct xgbe_prv_data *, int, int, u16); 685 int (*read_ext_mii_regs_c45)(struct xgbe_prv_data *, int, int, int); 686 int (*write_ext_mii_regs_c45)(struct xgbe_prv_data *, int, int, int, 687 u16); 688 689 int (*set_gpio)(struct xgbe_prv_data *, unsigned int); 690 int (*clr_gpio)(struct xgbe_prv_data *, unsigned int); 691 692 void (*enable_tx)(struct xgbe_prv_data *); 693 void (*disable_tx)(struct xgbe_prv_data *); 694 void (*enable_rx)(struct xgbe_prv_data *); 695 void (*disable_rx)(struct xgbe_prv_data *); 696 697 void (*powerup_tx)(struct xgbe_prv_data *); 698 void (*powerdown_tx)(struct xgbe_prv_data *); 699 void (*powerup_rx)(struct xgbe_prv_data *); 700 void (*powerdown_rx)(struct xgbe_prv_data *); 701 702 int (*init)(struct xgbe_prv_data *); 703 int (*exit)(struct xgbe_prv_data *); 704 705 int (*enable_int)(struct xgbe_channel *, enum xgbe_int); 706 int (*disable_int)(struct xgbe_channel *, enum xgbe_int); 707 void (*dev_xmit)(struct xgbe_channel *); 708 int (*dev_read)(struct xgbe_channel *); 709 void (*tx_desc_init)(struct xgbe_channel *); 710 void (*rx_desc_init)(struct xgbe_channel *); 711 void (*tx_desc_reset)(struct xgbe_ring_data *); 712 void (*rx_desc_reset)(struct xgbe_prv_data *, struct xgbe_ring_data *, 713 unsigned int); 714 int (*is_last_desc)(struct xgbe_ring_desc *); 715 int (*is_context_desc)(struct xgbe_ring_desc *); 716 void (*tx_start_xmit)(struct xgbe_channel *, struct xgbe_ring *); 717 718 /* For FLOW ctrl */ 719 int (*config_tx_flow_control)(struct xgbe_prv_data *); 720 int (*config_rx_flow_control)(struct xgbe_prv_data *); 721 722 /* For RX coalescing */ 723 int (*config_rx_coalesce)(struct xgbe_prv_data *); 724 int (*config_tx_coalesce)(struct xgbe_prv_data *); 725 unsigned int (*usec_to_riwt)(struct xgbe_prv_data *, unsigned int); 726 unsigned int (*riwt_to_usec)(struct xgbe_prv_data *, unsigned int); 727 728 /* For RX and TX threshold config */ 729 int (*config_rx_threshold)(struct xgbe_prv_data *, unsigned int); 730 int (*config_tx_threshold)(struct xgbe_prv_data *, unsigned int); 731 732 /* For RX and TX Store and Forward Mode config */ 733 int (*config_rsf_mode)(struct xgbe_prv_data *, unsigned int); 734 int (*config_tsf_mode)(struct xgbe_prv_data *, unsigned int); 735 736 /* For TX DMA Operate on Second Frame config */ 737 int (*config_osp_mode)(struct xgbe_prv_data *); 738 739 /* For MMC statistics */ 740 void (*rx_mmc_int)(struct xgbe_prv_data *); 741 void (*tx_mmc_int)(struct xgbe_prv_data *); 742 void (*read_mmc_stats)(struct xgbe_prv_data *); 743 744 /* For Timestamp config */ 745 int (*config_tstamp)(struct xgbe_prv_data *, unsigned int); 746 void (*update_tstamp_addend)(struct xgbe_prv_data *, unsigned int); 747 void (*set_tstamp_time)(struct xgbe_prv_data *, unsigned int sec, 748 unsigned int nsec); 749 u64 (*get_tstamp_time)(struct xgbe_prv_data *); 750 u64 (*get_tx_tstamp)(struct xgbe_prv_data *); 751 752 /* For Data Center Bridging config */ 753 void (*config_tc)(struct xgbe_prv_data *); 754 void (*config_dcb_tc)(struct xgbe_prv_data *); 755 void (*config_dcb_pfc)(struct xgbe_prv_data *); 756 757 /* For Receive Side Scaling */ 758 int (*enable_rss)(struct xgbe_prv_data *); 759 int (*disable_rss)(struct xgbe_prv_data *); 760 int (*set_rss_hash_key)(struct xgbe_prv_data *, const u8 *); 761 int (*set_rss_lookup_table)(struct xgbe_prv_data *, const u32 *); 762 763 /* For ECC */ 764 void (*disable_ecc_ded)(struct xgbe_prv_data *); 765 void (*disable_ecc_sec)(struct xgbe_prv_data *, enum xgbe_ecc_sec); 766 767 /* For VXLAN */ 768 void (*enable_vxlan)(struct xgbe_prv_data *); 769 void (*disable_vxlan)(struct xgbe_prv_data *); 770 void (*set_vxlan_id)(struct xgbe_prv_data *); 771 772 /* For Split Header */ 773 void (*enable_sph)(struct xgbe_prv_data *pdata); 774 void (*disable_sph)(struct xgbe_prv_data *pdata); 775 }; 776 777 /* This structure represents implementation specific routines for an 778 * implementation of a PHY. All routines are required unless noted below. 779 * Optional routines: 780 * an_pre, an_post 781 * kr_training_pre, kr_training_post 782 * module_info, module_eeprom 783 */ 784 struct xgbe_phy_impl_if { 785 /* Perform Setup/teardown actions */ 786 int (*init)(struct xgbe_prv_data *); 787 void (*exit)(struct xgbe_prv_data *); 788 789 /* Perform start/stop specific actions */ 790 int (*reset)(struct xgbe_prv_data *); 791 int (*start)(struct xgbe_prv_data *); 792 void (*stop)(struct xgbe_prv_data *); 793 794 /* Return the link status */ 795 int (*link_status)(struct xgbe_prv_data *, int *); 796 797 /* Indicate if a particular speed is valid */ 798 bool (*valid_speed)(struct xgbe_prv_data *, int); 799 800 /* Check if the specified mode can/should be used */ 801 bool (*use_mode)(struct xgbe_prv_data *, enum xgbe_mode); 802 /* Switch the PHY into various modes */ 803 void (*set_mode)(struct xgbe_prv_data *, enum xgbe_mode); 804 /* Retrieve mode needed for a specific speed */ 805 enum xgbe_mode (*get_mode)(struct xgbe_prv_data *, int); 806 /* Retrieve new/next mode when trying to auto-negotiate */ 807 enum xgbe_mode (*switch_mode)(struct xgbe_prv_data *); 808 /* Retrieve current mode */ 809 enum xgbe_mode (*cur_mode)(struct xgbe_prv_data *); 810 811 /* Retrieve current auto-negotiation mode */ 812 enum xgbe_an_mode (*an_mode)(struct xgbe_prv_data *); 813 814 /* Configure auto-negotiation settings */ 815 int (*an_config)(struct xgbe_prv_data *); 816 817 /* Set/override auto-negotiation advertisement settings */ 818 void (*an_advertising)(struct xgbe_prv_data *, 819 struct ethtool_link_ksettings *); 820 821 /* Process results of auto-negotiation */ 822 enum xgbe_mode (*an_outcome)(struct xgbe_prv_data *); 823 824 /* Pre/Post auto-negotiation support */ 825 void (*an_pre)(struct xgbe_prv_data *); 826 void (*an_post)(struct xgbe_prv_data *); 827 828 /* Pre/Post KR training enablement support */ 829 void (*kr_training_pre)(struct xgbe_prv_data *); 830 void (*kr_training_post)(struct xgbe_prv_data *); 831 832 /* SFP module related info */ 833 int (*module_info)(struct xgbe_prv_data *pdata, 834 struct ethtool_modinfo *modinfo); 835 int (*module_eeprom)(struct xgbe_prv_data *pdata, 836 struct ethtool_eeprom *eeprom, u8 *data); 837 }; 838 839 struct xgbe_phy_if { 840 /* For PHY setup/teardown */ 841 int (*phy_init)(struct xgbe_prv_data *); 842 void (*phy_exit)(struct xgbe_prv_data *); 843 844 /* For PHY support when setting device up/down */ 845 int (*phy_reset)(struct xgbe_prv_data *); 846 int (*phy_start)(struct xgbe_prv_data *); 847 void (*phy_stop)(struct xgbe_prv_data *); 848 849 /* For PHY support while device is up */ 850 void (*phy_status)(struct xgbe_prv_data *); 851 int (*phy_config_aneg)(struct xgbe_prv_data *); 852 853 /* For PHY settings validation */ 854 bool (*phy_valid_speed)(struct xgbe_prv_data *, int); 855 856 /* For single interrupt support */ 857 irqreturn_t (*an_isr)(struct xgbe_prv_data *); 858 859 /* For ethtool PHY support */ 860 int (*module_info)(struct xgbe_prv_data *pdata, 861 struct ethtool_modinfo *modinfo); 862 int (*module_eeprom)(struct xgbe_prv_data *pdata, 863 struct ethtool_eeprom *eeprom, u8 *data); 864 865 /* PHY implementation specific services */ 866 struct xgbe_phy_impl_if phy_impl; 867 }; 868 869 struct xgbe_i2c_if { 870 /* For initial I2C setup */ 871 int (*i2c_init)(struct xgbe_prv_data *); 872 873 /* For I2C support when setting device up/down */ 874 int (*i2c_start)(struct xgbe_prv_data *); 875 void (*i2c_stop)(struct xgbe_prv_data *); 876 877 /* For performing I2C operations */ 878 int (*i2c_xfer)(struct xgbe_prv_data *, struct xgbe_i2c_op *); 879 880 /* For single interrupt support */ 881 irqreturn_t (*i2c_isr)(struct xgbe_prv_data *); 882 }; 883 884 struct xgbe_desc_if { 885 int (*alloc_ring_resources)(struct xgbe_prv_data *); 886 void (*free_ring_resources)(struct xgbe_prv_data *); 887 int (*map_tx_skb)(struct xgbe_channel *, struct sk_buff *); 888 int (*map_rx_buffer)(struct xgbe_prv_data *, struct xgbe_ring *, 889 struct xgbe_ring_data *); 890 void (*unmap_rdata)(struct xgbe_prv_data *, struct xgbe_ring_data *); 891 void (*wrapper_tx_desc_init)(struct xgbe_prv_data *); 892 void (*wrapper_rx_desc_init)(struct xgbe_prv_data *); 893 }; 894 895 /* This structure contains flags that indicate what hardware features 896 * or configurations are present in the device. 897 */ 898 struct xgbe_hw_features { 899 /* HW Version */ 900 unsigned int version; 901 902 /* HW Feature Register0 */ 903 unsigned int gmii; /* 1000 Mbps support */ 904 unsigned int vlhash; /* VLAN Hash Filter */ 905 unsigned int sma; /* SMA(MDIO) Interface */ 906 unsigned int rwk; /* PMT remote wake-up packet */ 907 unsigned int mgk; /* PMT magic packet */ 908 unsigned int mmc; /* RMON module */ 909 unsigned int aoe; /* ARP Offload */ 910 unsigned int ts; /* IEEE 1588-2008 Advanced Timestamp */ 911 unsigned int eee; /* Energy Efficient Ethernet */ 912 unsigned int tx_coe; /* Tx Checksum Offload */ 913 unsigned int rx_coe; /* Rx Checksum Offload */ 914 unsigned int addn_mac; /* Additional MAC Addresses */ 915 unsigned int ts_src; /* Timestamp Source */ 916 unsigned int sa_vlan_ins; /* Source Address or VLAN Insertion */ 917 unsigned int vxn; /* VXLAN/NVGRE */ 918 919 /* HW Feature Register1 */ 920 unsigned int rx_fifo_size; /* MTL Receive FIFO Size */ 921 unsigned int tx_fifo_size; /* MTL Transmit FIFO Size */ 922 unsigned int adv_ts_hi; /* Advance Timestamping High Word */ 923 unsigned int dma_width; /* DMA width */ 924 unsigned int dcb; /* DCB Feature */ 925 unsigned int sph; /* Split Header Feature */ 926 unsigned int tso; /* TCP Segmentation Offload */ 927 unsigned int dma_debug; /* DMA Debug Registers */ 928 unsigned int rss; /* Receive Side Scaling */ 929 unsigned int tc_cnt; /* Number of Traffic Classes */ 930 unsigned int hash_table_size; /* Hash Table Size */ 931 unsigned int l3l4_filter_num; /* Number of L3-L4 Filters */ 932 933 /* HW Feature Register2 */ 934 unsigned int rx_q_cnt; /* Number of MTL Receive Queues */ 935 unsigned int tx_q_cnt; /* Number of MTL Transmit Queues */ 936 unsigned int rx_ch_cnt; /* Number of DMA Receive Channels */ 937 unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */ 938 unsigned int pps_out_num; /* Number of PPS outputs */ 939 unsigned int aux_snap_num; /* Number of Aux snapshot inputs */ 940 }; 941 942 struct xgbe_version_data { 943 void (*init_function_ptrs_phy_impl)(struct xgbe_phy_if *); 944 enum xgbe_xpcs_access xpcs_access; 945 unsigned int mmc_64bit; 946 unsigned int tx_max_fifo_size; 947 unsigned int rx_max_fifo_size; 948 unsigned int tx_tstamp_workaround; 949 unsigned int ecc_support; 950 unsigned int i2c_support; 951 unsigned int irq_reissue_support; 952 unsigned int tx_desc_prefetch; 953 unsigned int rx_desc_prefetch; 954 unsigned int an_cdr_workaround; 955 unsigned int enable_rrc; 956 }; 957 958 struct xgbe_prv_data { 959 struct net_device *netdev; 960 struct pci_dev *pcidev; 961 struct platform_device *platdev; 962 struct acpi_device *adev; 963 struct device *dev; 964 struct platform_device *phy_platdev; 965 struct device *phy_dev; 966 unsigned int smn_base; 967 968 /* Version related data */ 969 struct xgbe_version_data *vdata; 970 971 /* ACPI or DT flag */ 972 unsigned int use_acpi; 973 974 /* XGMAC/XPCS related mmio registers */ 975 void __iomem *xgmac_regs; /* XGMAC CSRs */ 976 void __iomem *xpcs_regs; /* XPCS MMD registers */ 977 void __iomem *rxtx_regs; /* SerDes Rx/Tx CSRs */ 978 void __iomem *sir0_regs; /* SerDes integration registers (1/2) */ 979 void __iomem *sir1_regs; /* SerDes integration registers (2/2) */ 980 void __iomem *xprop_regs; /* XGBE property registers */ 981 void __iomem *xi2c_regs; /* XGBE I2C CSRs */ 982 983 /* Port property registers */ 984 unsigned int pp0; 985 unsigned int pp1; 986 unsigned int pp2; 987 unsigned int pp3; 988 unsigned int pp4; 989 990 /* Overall device lock */ 991 spinlock_t lock; 992 993 /* XPCS indirect addressing lock */ 994 spinlock_t xpcs_lock; 995 unsigned int xpcs_window_def_reg; 996 unsigned int xpcs_window_sel_reg; 997 unsigned int xpcs_window; 998 unsigned int xpcs_window_size; 999 unsigned int xpcs_window_mask; 1000 1001 /* RSS addressing mutex */ 1002 struct mutex rss_mutex; 1003 1004 /* Flags representing xgbe_state */ 1005 unsigned long dev_state; 1006 1007 /* ECC support */ 1008 unsigned long tx_sec_period; 1009 unsigned long tx_ded_period; 1010 unsigned long rx_sec_period; 1011 unsigned long rx_ded_period; 1012 unsigned long desc_sec_period; 1013 unsigned long desc_ded_period; 1014 1015 unsigned int tx_sec_count; 1016 unsigned int tx_ded_count; 1017 unsigned int rx_sec_count; 1018 unsigned int rx_ded_count; 1019 unsigned int desc_ded_count; 1020 unsigned int desc_sec_count; 1021 1022 int dev_irq; 1023 int ecc_irq; 1024 int i2c_irq; 1025 int channel_irq[XGBE_MAX_DMA_CHANNELS]; 1026 1027 unsigned int per_channel_irq; 1028 unsigned int irq_count; 1029 unsigned int channel_irq_count; 1030 unsigned int channel_irq_mode; 1031 1032 char ecc_name[IFNAMSIZ + 32]; 1033 1034 struct xgbe_hw_if hw_if; 1035 struct xgbe_phy_if phy_if; 1036 struct xgbe_desc_if desc_if; 1037 struct xgbe_i2c_if i2c_if; 1038 1039 /* AXI DMA settings */ 1040 unsigned int coherent; 1041 unsigned int arcr; 1042 unsigned int awcr; 1043 unsigned int awarcr; 1044 1045 /* Service routine support */ 1046 struct workqueue_struct *dev_workqueue; 1047 struct work_struct service_work; 1048 struct timer_list service_timer; 1049 1050 /* Rings for Tx/Rx on a DMA channel */ 1051 struct xgbe_channel *channel[XGBE_MAX_DMA_CHANNELS]; 1052 unsigned int tx_max_channel_count; 1053 unsigned int rx_max_channel_count; 1054 unsigned int channel_count; 1055 unsigned int tx_ring_count; 1056 unsigned int tx_desc_count; 1057 unsigned int rx_ring_count; 1058 unsigned int rx_desc_count; 1059 1060 unsigned int new_tx_ring_count; 1061 unsigned int new_rx_ring_count; 1062 1063 unsigned int tx_max_q_count; 1064 unsigned int rx_max_q_count; 1065 unsigned int tx_q_count; 1066 unsigned int rx_q_count; 1067 1068 /* Tx/Rx common settings */ 1069 unsigned int blen; 1070 unsigned int pbl; 1071 unsigned int aal; 1072 unsigned int rd_osr_limit; 1073 unsigned int wr_osr_limit; 1074 1075 /* Tx settings */ 1076 unsigned int tx_sf_mode; 1077 unsigned int tx_threshold; 1078 unsigned int tx_osp_mode; 1079 unsigned int tx_max_fifo_size; 1080 1081 /* Rx settings */ 1082 unsigned int rx_sf_mode; 1083 unsigned int rx_threshold; 1084 unsigned int rx_max_fifo_size; 1085 1086 /* Tx coalescing settings */ 1087 unsigned int tx_usecs; 1088 unsigned int tx_frames; 1089 1090 /* Rx coalescing settings */ 1091 unsigned int rx_riwt; 1092 unsigned int rx_usecs; 1093 unsigned int rx_frames; 1094 1095 /* Current Rx buffer size */ 1096 unsigned int rx_buf_size; 1097 1098 /* Flow control settings */ 1099 unsigned int pause_autoneg; 1100 unsigned int tx_pause; 1101 unsigned int rx_pause; 1102 unsigned int rx_rfa[XGBE_MAX_QUEUES]; 1103 unsigned int rx_rfd[XGBE_MAX_QUEUES]; 1104 1105 /* Receive Side Scaling settings */ 1106 u8 rss_key[XGBE_RSS_HASH_KEY_SIZE]; 1107 u32 rss_table[XGBE_RSS_MAX_TABLE_SIZE]; 1108 u32 rss_options; 1109 1110 /* VXLAN settings */ 1111 u16 vxlan_port; 1112 1113 /* Netdev related settings */ 1114 unsigned char mac_addr[ETH_ALEN]; 1115 netdev_features_t netdev_features; 1116 struct napi_struct napi; 1117 struct xgbe_mmc_stats mmc_stats; 1118 struct xgbe_ext_stats ext_stats; 1119 1120 /* Filtering support */ 1121 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 1122 1123 /* Device clocks */ 1124 struct clk *sysclk; 1125 unsigned long sysclk_rate; 1126 struct clk *ptpclk; 1127 unsigned long ptpclk_rate; 1128 1129 /* Timestamp support */ 1130 spinlock_t tstamp_lock; 1131 struct ptp_clock_info ptp_clock_info; 1132 struct ptp_clock *ptp_clock; 1133 struct hwtstamp_config tstamp_config; 1134 struct cyclecounter tstamp_cc; 1135 struct timecounter tstamp_tc; 1136 unsigned int tstamp_addend; 1137 struct work_struct tx_tstamp_work; 1138 struct sk_buff *tx_tstamp_skb; 1139 u64 tx_tstamp; 1140 1141 /* DCB support */ 1142 struct ieee_ets *ets; 1143 struct ieee_pfc *pfc; 1144 unsigned int q2tc_map[XGBE_MAX_QUEUES]; 1145 unsigned int prio2q_map[IEEE_8021QAZ_MAX_TCS]; 1146 unsigned int pfcq[XGBE_MAX_QUEUES]; 1147 unsigned int pfc_rfa; 1148 u8 num_tcs; 1149 1150 /* Hardware features of the device */ 1151 struct xgbe_hw_features hw_feat; 1152 1153 /* Device work structures */ 1154 struct work_struct restart_work; 1155 struct work_struct stopdev_work; 1156 1157 /* Keeps track of power mode */ 1158 unsigned int power_down; 1159 1160 /* Network interface message level setting */ 1161 u32 msg_enable; 1162 1163 /* Current PHY settings */ 1164 phy_interface_t phy_mode; 1165 int phy_link; 1166 int phy_speed; 1167 1168 /* MDIO/PHY related settings */ 1169 unsigned int phy_started; 1170 void *phy_data; 1171 struct xgbe_phy phy; 1172 int mdio_mmd; 1173 unsigned long link_check; 1174 struct completion mdio_complete; 1175 1176 unsigned int kr_redrv; 1177 1178 char an_name[IFNAMSIZ + 32]; 1179 struct workqueue_struct *an_workqueue; 1180 1181 int an_irq; 1182 struct work_struct an_irq_work; 1183 1184 /* Auto-negotiation state machine support */ 1185 unsigned int an_int; 1186 unsigned int an_status; 1187 struct mutex an_mutex; 1188 enum xgbe_an an_result; 1189 enum xgbe_an an_state; 1190 enum xgbe_rx kr_state; 1191 enum xgbe_rx kx_state; 1192 struct work_struct an_work; 1193 unsigned int an_again; 1194 unsigned int an_supported; 1195 unsigned int parallel_detect; 1196 unsigned int fec_ability; 1197 unsigned long an_start; 1198 unsigned long kr_start_time; 1199 enum xgbe_an_mode an_mode; 1200 1201 /* I2C support */ 1202 struct xgbe_i2c i2c; 1203 struct mutex i2c_mutex; 1204 struct completion i2c_complete; 1205 char i2c_name[IFNAMSIZ + 32]; 1206 1207 unsigned int lpm_ctrl; /* CTRL1 for resume */ 1208 1209 unsigned int isr_as_bh_work; 1210 struct work_struct dev_bh_work; 1211 struct work_struct ecc_bh_work; 1212 struct work_struct i2c_bh_work; 1213 struct work_struct an_bh_work; 1214 1215 struct dentry *xgbe_debugfs; 1216 1217 unsigned int debugfs_xgmac_reg; 1218 1219 unsigned int debugfs_xpcs_mmd; 1220 unsigned int debugfs_xpcs_reg; 1221 1222 unsigned int debugfs_xprop_reg; 1223 1224 unsigned int debugfs_xi2c_reg; 1225 1226 bool debugfs_an_cdr_workaround; 1227 bool debugfs_an_cdr_track_early; 1228 bool en_rx_adap; 1229 int rx_adapt_retries; 1230 bool rx_adapt_done; 1231 bool mode_set; 1232 }; 1233 1234 /* Function prototypes*/ 1235 struct xgbe_prv_data *xgbe_alloc_pdata(struct device *); 1236 void xgbe_free_pdata(struct xgbe_prv_data *); 1237 void xgbe_set_counts(struct xgbe_prv_data *); 1238 int xgbe_config_netdev(struct xgbe_prv_data *); 1239 void xgbe_deconfig_netdev(struct xgbe_prv_data *); 1240 1241 int xgbe_platform_init(void); 1242 void xgbe_platform_exit(void); 1243 #ifdef CONFIG_PCI 1244 int xgbe_pci_init(void); 1245 void xgbe_pci_exit(void); 1246 #else 1247 static inline int xgbe_pci_init(void) { return 0; } 1248 static inline void xgbe_pci_exit(void) { } 1249 #endif 1250 1251 void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *); 1252 void xgbe_init_function_ptrs_phy(struct xgbe_phy_if *); 1253 void xgbe_init_function_ptrs_phy_v1(struct xgbe_phy_if *); 1254 void xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *); 1255 void xgbe_init_function_ptrs_desc(struct xgbe_desc_if *); 1256 void xgbe_init_function_ptrs_i2c(struct xgbe_i2c_if *); 1257 const struct net_device_ops *xgbe_get_netdev_ops(void); 1258 const struct ethtool_ops *xgbe_get_ethtool_ops(void); 1259 const struct udp_tunnel_nic_info *xgbe_get_udp_tunnel_info(void); 1260 1261 #ifdef CONFIG_AMD_XGBE_DCB 1262 const struct dcbnl_rtnl_ops *xgbe_get_dcbnl_ops(void); 1263 #endif 1264 1265 void xgbe_ptp_register(struct xgbe_prv_data *); 1266 void xgbe_ptp_unregister(struct xgbe_prv_data *); 1267 void xgbe_dump_tx_desc(struct xgbe_prv_data *, struct xgbe_ring *, 1268 unsigned int, unsigned int, unsigned int); 1269 void xgbe_dump_rx_desc(struct xgbe_prv_data *, struct xgbe_ring *, 1270 unsigned int); 1271 void xgbe_print_pkt(struct net_device *, struct sk_buff *, bool); 1272 void xgbe_get_all_hw_features(struct xgbe_prv_data *); 1273 int xgbe_powerup(struct net_device *, unsigned int); 1274 int xgbe_powerdown(struct net_device *, unsigned int); 1275 void xgbe_init_rx_coalesce(struct xgbe_prv_data *); 1276 void xgbe_init_tx_coalesce(struct xgbe_prv_data *); 1277 void xgbe_restart_dev(struct xgbe_prv_data *pdata); 1278 void xgbe_full_restart_dev(struct xgbe_prv_data *pdata); 1279 1280 #ifdef CONFIG_DEBUG_FS 1281 void xgbe_debugfs_init(struct xgbe_prv_data *); 1282 void xgbe_debugfs_exit(struct xgbe_prv_data *); 1283 void xgbe_debugfs_rename(struct xgbe_prv_data *pdata); 1284 #else 1285 static inline void xgbe_debugfs_init(struct xgbe_prv_data *pdata) {} 1286 static inline void xgbe_debugfs_exit(struct xgbe_prv_data *pdata) {} 1287 static inline void xgbe_debugfs_rename(struct xgbe_prv_data *pdata) {} 1288 #endif /* CONFIG_DEBUG_FS */ 1289 1290 /* NOTE: Uncomment for function trace log messages in KERNEL LOG */ 1291 #if 0 1292 #define YDEBUG 1293 #define YDEBUG_MDIO 1294 #endif 1295 1296 /* For debug prints */ 1297 #ifdef YDEBUG 1298 #define DBGPR(x...) pr_alert(x) 1299 #else 1300 #define DBGPR(x...) do { } while (0) 1301 #endif 1302 1303 #ifdef YDEBUG_MDIO 1304 #define DBGPR_MDIO(x...) pr_alert(x) 1305 #else 1306 #define DBGPR_MDIO(x...) do { } while (0) 1307 #endif 1308 1309 #endif 1310