1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) 2 /* 3 * Copyright (c) 2014-2025, Advanced Micro Devices, Inc. 4 * Copyright (c) 2014, Synopsys, Inc. 5 * All rights reserved 6 */ 7 8 #ifndef __XGBE_H__ 9 #define __XGBE_H__ 10 11 #include <linux/dma-mapping.h> 12 #include <linux/netdevice.h> 13 #include <linux/workqueue.h> 14 #include <linux/phy.h> 15 #include <linux/if_vlan.h> 16 #include <linux/bitops.h> 17 #include <linux/ptp_clock_kernel.h> 18 #include <linux/timecounter.h> 19 #include <linux/net_tstamp.h> 20 #include <net/dcbnl.h> 21 #include <linux/completion.h> 22 #include <linux/cpumask.h> 23 #include <linux/interrupt.h> 24 #include <linux/dcache.h> 25 #include <linux/ethtool.h> 26 #include <linux/list.h> 27 28 #define XGBE_DRV_NAME "amd-xgbe" 29 #define XGBE_DRV_DESC "AMD 10 Gigabit Ethernet Driver" 30 31 /* Descriptor related defines */ 32 #define XGBE_TX_DESC_CNT 512 33 #define XGBE_TX_DESC_MIN_FREE (XGBE_TX_DESC_CNT >> 3) 34 #define XGBE_TX_DESC_MAX_PROC (XGBE_TX_DESC_CNT >> 1) 35 #define XGBE_RX_DESC_CNT 512 36 37 #define XGBE_TX_DESC_CNT_MIN 64 38 #define XGBE_TX_DESC_CNT_MAX 4096 39 #define XGBE_RX_DESC_CNT_MIN 64 40 #define XGBE_RX_DESC_CNT_MAX 4096 41 42 #define XGBE_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1)) 43 44 /* Descriptors required for maximum contiguous TSO/GSO packet */ 45 #define XGBE_TX_MAX_SPLIT \ 46 ((GSO_LEGACY_MAX_SIZE / XGBE_TX_MAX_BUF_SIZE) + 1) 47 48 /* Maximum possible descriptors needed for an SKB: 49 * - Maximum number of SKB frags 50 * - Maximum descriptors for contiguous TSO/GSO packet 51 * - Possible context descriptor 52 * - Possible TSO header descriptor 53 */ 54 #define XGBE_TX_MAX_DESCS (MAX_SKB_FRAGS + XGBE_TX_MAX_SPLIT + 2) 55 56 #define XGBE_RX_MIN_BUF_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN) 57 #define XGBE_RX_BUF_ALIGN 64 58 #define XGBE_SKB_ALLOC_SIZE 256 59 #define XGBE_SPH_HDSMS_SIZE 2 /* Keep in sync with SKB_ALLOC_SIZE */ 60 61 #define XGBE_MAX_DMA_CHANNELS 16 62 #define XGBE_MAX_QUEUES 16 63 #define XGBE_PRIORITY_QUEUES 8 64 #define XGBE_DMA_STOP_TIMEOUT 1 65 66 /* DMA cache settings - Outer sharable, write-back, write-allocate */ 67 #define XGBE_DMA_OS_ARCR 0x002b2b2b 68 #define XGBE_DMA_OS_AWCR 0x2f2f2f2f 69 70 /* DMA cache settings - System, no caches used */ 71 #define XGBE_DMA_SYS_ARCR 0x00303030 72 #define XGBE_DMA_SYS_AWCR 0x30303030 73 74 /* DMA cache settings - PCI device */ 75 #define XGBE_DMA_PCI_ARCR 0x000f0f0f 76 #define XGBE_DMA_PCI_AWCR 0x0f0f0f0f 77 #define XGBE_DMA_PCI_AWARCR 0x00000f0f 78 79 /* DMA channel interrupt modes */ 80 #define XGBE_IRQ_MODE_EDGE 0 81 #define XGBE_IRQ_MODE_LEVEL 1 82 83 #define XGMAC_MIN_PACKET 60 84 #define XGMAC_STD_PACKET_MTU 1500 85 #define XGMAC_MAX_STD_PACKET 1518 86 #define XGMAC_JUMBO_PACKET_MTU 9000 87 #define XGMAC_MAX_JUMBO_PACKET 9018 88 #define XGMAC_ETH_PREAMBLE (12 + 8) /* Inter-frame gap + preamble */ 89 90 #define XGMAC_PFC_DATA_LEN 46 91 #define XGMAC_PFC_DELAYS 14000 92 93 #define XGMAC_PRIO_QUEUES(_cnt) \ 94 min_t(unsigned int, IEEE_8021QAZ_MAX_TCS, (_cnt)) 95 96 /* Common property names */ 97 #define XGBE_MAC_ADDR_PROPERTY "mac-address" 98 #define XGBE_PHY_MODE_PROPERTY "phy-mode" 99 #define XGBE_DMA_IRQS_PROPERTY "amd,per-channel-interrupt" 100 #define XGBE_SPEEDSET_PROPERTY "amd,speed-set" 101 102 /* Device-tree clock names */ 103 #define XGBE_DMA_CLOCK "dma_clk" 104 #define XGBE_PTP_CLOCK "ptp_clk" 105 106 /* ACPI property names */ 107 #define XGBE_ACPI_DMA_FREQ "amd,dma-freq" 108 #define XGBE_ACPI_PTP_FREQ "amd,ptp-freq" 109 110 /* PCI BAR mapping */ 111 #define XGBE_XGMAC_BAR 0 112 #define XGBE_XPCS_BAR 1 113 #define XGBE_MAC_PROP_OFFSET 0x1d000 114 #define XGBE_I2C_CTRL_OFFSET 0x1e000 115 116 /* PCI MSI/MSIx support */ 117 #define XGBE_MSI_BASE_COUNT 4 118 #define XGBE_MSI_MIN_COUNT (XGBE_MSI_BASE_COUNT + 1) 119 120 /* PCI clock frequencies */ 121 #define XGBE_V2_DMA_CLOCK_FREQ 500000000 /* 500 MHz */ 122 #define XGBE_V2_PTP_CLOCK_FREQ 125000000 /* 125 MHz */ 123 124 /* Timestamp support - values based on 50MHz PTP clock 125 * 50MHz => 20 nsec 126 */ 127 #define XGBE_TSTAMP_SSINC 20 128 #define XGBE_TSTAMP_SNSINC 0 129 130 /* Driver PMT macros */ 131 #define XGMAC_DRIVER_CONTEXT 1 132 #define XGMAC_IOCTL_CONTEXT 2 133 134 #define XGMAC_FIFO_MIN_ALLOC 2048 135 #define XGMAC_FIFO_UNIT 256 136 #define XGMAC_FIFO_ALIGN(_x) \ 137 (((_x) + XGMAC_FIFO_UNIT - 1) & ~(XGMAC_FIFO_UNIT - 1)) 138 #define XGMAC_FIFO_FC_OFF 2048 139 #define XGMAC_FIFO_FC_MIN 4096 140 141 #define XGBE_TC_MIN_QUANTUM 10 142 143 /* Helper macro for descriptor handling 144 * Always use XGBE_GET_DESC_DATA to access the descriptor data 145 * since the index is free-running and needs to be and-ed 146 * with the descriptor count value of the ring to index to 147 * the proper descriptor data. 148 */ 149 #define XGBE_GET_DESC_DATA(_ring, _idx) \ 150 ((_ring)->rdata + \ 151 ((_idx) & ((_ring)->rdesc_count - 1))) 152 153 /* Default coalescing parameters */ 154 #define XGMAC_INIT_DMA_TX_USECS 1000 155 #define XGMAC_INIT_DMA_TX_FRAMES 25 156 157 #define XGMAC_MAX_DMA_RIWT 0xff 158 #define XGMAC_INIT_DMA_RX_USECS 30 159 #define XGMAC_INIT_DMA_RX_FRAMES 25 160 161 /* Flow control queue count */ 162 #define XGMAC_MAX_FLOW_CONTROL_QUEUES 8 163 164 /* Flow control threshold units */ 165 #define XGMAC_FLOW_CONTROL_UNIT 512 166 #define XGMAC_FLOW_CONTROL_ALIGN(_x) \ 167 (((_x) + XGMAC_FLOW_CONTROL_UNIT - 1) & ~(XGMAC_FLOW_CONTROL_UNIT - 1)) 168 #define XGMAC_FLOW_CONTROL_VALUE(_x) \ 169 (((_x) < 1024) ? 0 : ((_x) / XGMAC_FLOW_CONTROL_UNIT) - 2) 170 #define XGMAC_FLOW_CONTROL_MAX 33280 171 172 /* Maximum MAC address hash table size (256 bits = 8 bytes) */ 173 #define XGBE_MAC_HASH_TABLE_SIZE 8 174 175 /* Receive Side Scaling */ 176 #define XGBE_RSS_HASH_KEY_SIZE 40 177 #define XGBE_RSS_MAX_TABLE_SIZE 256 178 #define XGBE_RSS_LOOKUP_TABLE_TYPE 0 179 #define XGBE_RSS_HASH_KEY_TYPE 1 180 181 /* Auto-negotiation */ 182 #define XGBE_AN_MS_TIMEOUT 500 183 #define XGBE_LINK_TIMEOUT 5 184 #define XGBE_KR_TRAINING_WAIT_ITER 50 185 186 #define XGBE_SGMII_AN_LINK_STATUS BIT(1) 187 #define XGBE_SGMII_AN_LINK_SPEED (BIT(2) | BIT(3)) 188 #define XGBE_SGMII_AN_LINK_SPEED_10 0x00 189 #define XGBE_SGMII_AN_LINK_SPEED_100 0x04 190 #define XGBE_SGMII_AN_LINK_SPEED_1000 0x08 191 #define XGBE_SGMII_AN_LINK_DUPLEX BIT(4) 192 193 /* ECC correctable error notification window (seconds) */ 194 #define XGBE_ECC_LIMIT 60 195 196 /* MDIO port types */ 197 #define XGMAC_MAX_C22_PORT 3 198 199 /* Link mode bit operations */ 200 #define XGBE_ZERO_SUP(_ls) \ 201 ethtool_link_ksettings_zero_link_mode((_ls), supported) 202 203 #define XGBE_SET_SUP(_ls, _mode) \ 204 ethtool_link_ksettings_add_link_mode((_ls), supported, _mode) 205 206 #define XGBE_CLR_SUP(_ls, _mode) \ 207 ethtool_link_ksettings_del_link_mode((_ls), supported, _mode) 208 209 #define XGBE_IS_SUP(_ls, _mode) \ 210 ethtool_link_ksettings_test_link_mode((_ls), supported, _mode) 211 212 #define XGBE_ZERO_ADV(_ls) \ 213 ethtool_link_ksettings_zero_link_mode((_ls), advertising) 214 215 #define XGBE_SET_ADV(_ls, _mode) \ 216 ethtool_link_ksettings_add_link_mode((_ls), advertising, _mode) 217 218 #define XGBE_CLR_ADV(_ls, _mode) \ 219 ethtool_link_ksettings_del_link_mode((_ls), advertising, _mode) 220 221 #define XGBE_ADV(_ls, _mode) \ 222 ethtool_link_ksettings_test_link_mode((_ls), advertising, _mode) 223 224 #define XGBE_ZERO_LP_ADV(_ls) \ 225 ethtool_link_ksettings_zero_link_mode((_ls), lp_advertising) 226 227 #define XGBE_SET_LP_ADV(_ls, _mode) \ 228 ethtool_link_ksettings_add_link_mode((_ls), lp_advertising, _mode) 229 230 #define XGBE_CLR_LP_ADV(_ls, _mode) \ 231 ethtool_link_ksettings_del_link_mode((_ls), lp_advertising, _mode) 232 233 #define XGBE_LP_ADV(_ls, _mode) \ 234 ethtool_link_ksettings_test_link_mode((_ls), lp_advertising, _mode) 235 236 #define XGBE_LM_COPY(_dst, _dname, _src, _sname) \ 237 bitmap_copy((_dst)->link_modes._dname, \ 238 (_src)->link_modes._sname, \ 239 __ETHTOOL_LINK_MODE_MASK_NBITS) 240 241 struct xgbe_prv_data; 242 243 struct xgbe_packet_data { 244 struct sk_buff *skb; 245 246 unsigned int attributes; 247 248 unsigned int errors; 249 250 unsigned int rdesc_count; 251 unsigned int length; 252 253 unsigned int header_len; 254 unsigned int tcp_header_len; 255 unsigned int tcp_payload_len; 256 unsigned short mss; 257 258 unsigned short vlan_ctag; 259 260 u64 rx_tstamp; 261 262 u32 rss_hash; 263 enum pkt_hash_types rss_hash_type; 264 265 unsigned int tx_packets; 266 unsigned int tx_bytes; 267 }; 268 269 /* Common Rx and Tx descriptor mapping */ 270 struct xgbe_ring_desc { 271 __le32 desc0; 272 __le32 desc1; 273 __le32 desc2; 274 __le32 desc3; 275 }; 276 277 /* Page allocation related values */ 278 struct xgbe_page_alloc { 279 struct page *pages; 280 unsigned int pages_len; 281 unsigned int pages_offset; 282 283 dma_addr_t pages_dma; 284 }; 285 286 /* Ring entry buffer data */ 287 struct xgbe_buffer_data { 288 struct xgbe_page_alloc pa; 289 struct xgbe_page_alloc pa_unmap; 290 291 dma_addr_t dma_base; 292 unsigned long dma_off; 293 unsigned int dma_len; 294 }; 295 296 /* Tx-related ring data */ 297 struct xgbe_tx_ring_data { 298 unsigned int packets; /* BQL packet count */ 299 unsigned int bytes; /* BQL byte count */ 300 }; 301 302 /* Rx-related ring data */ 303 struct xgbe_rx_ring_data { 304 struct xgbe_buffer_data hdr; /* Header locations */ 305 struct xgbe_buffer_data buf; /* Payload locations */ 306 307 unsigned short hdr_len; /* Length of received header */ 308 unsigned short len; /* Length of received packet */ 309 }; 310 311 /* Structure used to hold information related to the descriptor 312 * and the packet associated with the descriptor (always use 313 * the XGBE_GET_DESC_DATA macro to access this data from the ring) 314 */ 315 struct xgbe_ring_data { 316 struct xgbe_ring_desc *rdesc; /* Virtual address of descriptor */ 317 dma_addr_t rdesc_dma; /* DMA address of descriptor */ 318 319 struct sk_buff *skb; /* Virtual address of SKB */ 320 dma_addr_t skb_dma; /* DMA address of SKB data */ 321 unsigned int skb_dma_len; /* Length of SKB DMA area */ 322 323 struct xgbe_tx_ring_data tx; /* Tx-related data */ 324 struct xgbe_rx_ring_data rx; /* Rx-related data */ 325 326 unsigned int mapped_as_page; 327 328 /* Incomplete receive save location. If the budget is exhausted 329 * or the last descriptor (last normal descriptor or a following 330 * context descriptor) has not been DMA'd yet the current state 331 * of the receive processing needs to be saved. 332 */ 333 unsigned int state_saved; 334 struct { 335 struct sk_buff *skb; 336 unsigned int len; 337 unsigned int error; 338 } state; 339 }; 340 341 struct xgbe_ring { 342 /* Ring lock - used just for TX rings at the moment */ 343 spinlock_t lock; 344 345 /* Per packet related information */ 346 struct xgbe_packet_data packet_data; 347 348 /* Virtual/DMA addresses and count of allocated descriptor memory */ 349 struct xgbe_ring_desc *rdesc; 350 dma_addr_t rdesc_dma; 351 unsigned int rdesc_count; 352 353 /* Array of descriptor data corresponding the descriptor memory 354 * (always use the XGBE_GET_DESC_DATA macro to access this data) 355 */ 356 struct xgbe_ring_data *rdata; 357 358 /* Page allocation for RX buffers */ 359 struct xgbe_page_alloc rx_hdr_pa; 360 struct xgbe_page_alloc rx_buf_pa; 361 int node; 362 363 /* Ring index values 364 * cur - Tx: index of descriptor to be used for current transfer 365 * Rx: index of descriptor to check for packet availability 366 * dirty - Tx: index of descriptor to check for transfer complete 367 * Rx: index of descriptor to check for buffer reallocation 368 */ 369 unsigned int cur; 370 unsigned int dirty; 371 372 /* Coalesce frame count used for interrupt bit setting */ 373 unsigned int coalesce_count; 374 375 union { 376 struct { 377 unsigned int queue_stopped; 378 unsigned int xmit_more; 379 unsigned short cur_mss; 380 unsigned short cur_vlan_ctag; 381 } tx; 382 }; 383 } ____cacheline_aligned; 384 385 /* Structure used to describe the descriptor rings associated with 386 * a DMA channel. 387 */ 388 struct xgbe_channel { 389 char name[20]; 390 391 /* Address of private data area for device */ 392 struct xgbe_prv_data *pdata; 393 394 /* Queue index and base address of queue's DMA registers */ 395 unsigned int queue_index; 396 void __iomem *dma_regs; 397 398 /* Per channel interrupt irq number */ 399 int dma_irq; 400 char dma_irq_name[IFNAMSIZ + 32]; 401 402 /* Netdev related settings */ 403 struct napi_struct napi; 404 405 /* Per channel interrupt enablement tracker */ 406 unsigned int curr_ier; 407 unsigned int saved_ier; 408 409 unsigned int tx_timer_active; 410 struct timer_list tx_timer; 411 412 struct xgbe_ring *tx_ring; 413 struct xgbe_ring *rx_ring; 414 415 int node; 416 cpumask_t affinity_mask; 417 } ____cacheline_aligned; 418 419 enum xgbe_state { 420 XGBE_DOWN, 421 XGBE_LINK_INIT, 422 XGBE_LINK_ERR, 423 XGBE_STOPPED, 424 }; 425 426 enum xgbe_int { 427 XGMAC_INT_DMA_CH_SR_TI, 428 XGMAC_INT_DMA_CH_SR_TPS, 429 XGMAC_INT_DMA_CH_SR_TBU, 430 XGMAC_INT_DMA_CH_SR_RI, 431 XGMAC_INT_DMA_CH_SR_RBU, 432 XGMAC_INT_DMA_CH_SR_RPS, 433 XGMAC_INT_DMA_CH_SR_TI_RI, 434 XGMAC_INT_DMA_CH_SR_FBE, 435 XGMAC_INT_DMA_ALL, 436 }; 437 438 enum xgbe_int_state { 439 XGMAC_INT_STATE_SAVE, 440 XGMAC_INT_STATE_RESTORE, 441 }; 442 443 enum xgbe_ecc_sec { 444 XGBE_ECC_SEC_TX, 445 XGBE_ECC_SEC_RX, 446 XGBE_ECC_SEC_DESC, 447 }; 448 449 enum xgbe_speed { 450 XGBE_SPEED_1000 = 0, 451 XGBE_SPEED_2500, 452 XGBE_SPEED_10000, 453 XGBE_SPEEDS, 454 }; 455 456 enum xgbe_xpcs_access { 457 XGBE_XPCS_ACCESS_V1 = 0, 458 XGBE_XPCS_ACCESS_V2, 459 }; 460 461 enum xgbe_an_mode { 462 XGBE_AN_MODE_CL73 = 0, 463 XGBE_AN_MODE_CL73_REDRV, 464 XGBE_AN_MODE_CL37, 465 XGBE_AN_MODE_CL37_SGMII, 466 XGBE_AN_MODE_NONE, 467 }; 468 469 enum xgbe_an { 470 XGBE_AN_READY = 0, 471 XGBE_AN_PAGE_RECEIVED, 472 XGBE_AN_INCOMPAT_LINK, 473 XGBE_AN_COMPLETE, 474 XGBE_AN_NO_LINK, 475 XGBE_AN_ERROR, 476 }; 477 478 enum xgbe_rx { 479 XGBE_RX_BPA = 0, 480 XGBE_RX_XNP, 481 XGBE_RX_COMPLETE, 482 XGBE_RX_ERROR, 483 }; 484 485 enum xgbe_mode { 486 XGBE_MODE_KX_1000 = 0, 487 XGBE_MODE_KX_2500, 488 XGBE_MODE_KR, 489 XGBE_MODE_X, 490 XGBE_MODE_SGMII_10, 491 XGBE_MODE_SGMII_100, 492 XGBE_MODE_SGMII_1000, 493 XGBE_MODE_SFI, 494 XGBE_MODE_UNKNOWN, 495 }; 496 497 enum xgbe_speedset { 498 XGBE_SPEEDSET_1000_10000 = 0, 499 XGBE_SPEEDSET_2500_10000, 500 }; 501 502 enum xgbe_mdio_mode { 503 XGBE_MDIO_MODE_NONE = 0, 504 XGBE_MDIO_MODE_CL22, 505 XGBE_MDIO_MODE_CL45, 506 }; 507 508 enum xgbe_mb_cmd { 509 XGBE_MB_CMD_POWER_OFF = 0, 510 XGBE_MB_CMD_SET_1G, 511 XGBE_MB_CMD_SET_2_5G, 512 XGBE_MB_CMD_SET_10G_SFI, 513 XGBE_MB_CMD_SET_10G_KR, 514 XGBE_MB_CMD_RRC 515 }; 516 517 enum xgbe_mb_subcmd { 518 XGBE_MB_SUBCMD_NONE = 0, 519 XGBE_MB_SUBCMD_RX_ADAP, 520 521 /* 10GbE SFP subcommands */ 522 XGBE_MB_SUBCMD_ACTIVE = 0, 523 XGBE_MB_SUBCMD_PASSIVE_1M, 524 XGBE_MB_SUBCMD_PASSIVE_3M, 525 XGBE_MB_SUBCMD_PASSIVE_OTHER, 526 527 /* 1GbE Mode subcommands */ 528 XGBE_MB_SUBCMD_10MBITS = 0, 529 XGBE_MB_SUBCMD_100MBITS, 530 XGBE_MB_SUBCMD_1G_SGMII, 531 XGBE_MB_SUBCMD_1G_KX 532 }; 533 534 struct xgbe_phy { 535 struct ethtool_link_ksettings lks; 536 537 int address; 538 539 int autoneg; 540 int speed; 541 int duplex; 542 543 int link; 544 545 int pause_autoneg; 546 int tx_pause; 547 int rx_pause; 548 }; 549 550 enum xgbe_i2c_cmd { 551 XGBE_I2C_CMD_READ = 0, 552 XGBE_I2C_CMD_WRITE, 553 }; 554 555 struct xgbe_i2c_op { 556 enum xgbe_i2c_cmd cmd; 557 558 unsigned int target; 559 560 void *buf; 561 unsigned int len; 562 }; 563 564 struct xgbe_i2c_op_state { 565 struct xgbe_i2c_op *op; 566 567 unsigned int tx_len; 568 unsigned char *tx_buf; 569 570 unsigned int rx_len; 571 unsigned char *rx_buf; 572 573 unsigned int tx_abort_source; 574 575 int ret; 576 }; 577 578 struct xgbe_i2c { 579 unsigned int started; 580 unsigned int max_speed_mode; 581 unsigned int rx_fifo_size; 582 unsigned int tx_fifo_size; 583 584 struct xgbe_i2c_op_state op_state; 585 }; 586 587 struct xgbe_mmc_stats { 588 /* Tx Stats */ 589 u64 txoctetcount_gb; 590 u64 txframecount_gb; 591 u64 txbroadcastframes_g; 592 u64 txmulticastframes_g; 593 u64 tx64octets_gb; 594 u64 tx65to127octets_gb; 595 u64 tx128to255octets_gb; 596 u64 tx256to511octets_gb; 597 u64 tx512to1023octets_gb; 598 u64 tx1024tomaxoctets_gb; 599 u64 txunicastframes_gb; 600 u64 txmulticastframes_gb; 601 u64 txbroadcastframes_gb; 602 u64 txunderflowerror; 603 u64 txoctetcount_g; 604 u64 txframecount_g; 605 u64 txpauseframes; 606 u64 txvlanframes_g; 607 608 /* Rx Stats */ 609 u64 rxframecount_gb; 610 u64 rxoctetcount_gb; 611 u64 rxoctetcount_g; 612 u64 rxbroadcastframes_g; 613 u64 rxmulticastframes_g; 614 u64 rxcrcerror; 615 u64 rxrunterror; 616 u64 rxjabbererror; 617 u64 rxundersize_g; 618 u64 rxoversize_g; 619 u64 rx64octets_gb; 620 u64 rx65to127octets_gb; 621 u64 rx128to255octets_gb; 622 u64 rx256to511octets_gb; 623 u64 rx512to1023octets_gb; 624 u64 rx1024tomaxoctets_gb; 625 u64 rxunicastframes_g; 626 u64 rxlengtherror; 627 u64 rxoutofrangetype; 628 u64 rxpauseframes; 629 u64 rxfifooverflow; 630 u64 rxvlanframes_gb; 631 u64 rxwatchdogerror; 632 }; 633 634 struct xgbe_ext_stats { 635 u64 tx_tso_packets; 636 u64 rx_split_header_packets; 637 u64 rx_buffer_unavailable; 638 639 u64 txq_packets[XGBE_MAX_DMA_CHANNELS]; 640 u64 txq_bytes[XGBE_MAX_DMA_CHANNELS]; 641 u64 rxq_packets[XGBE_MAX_DMA_CHANNELS]; 642 u64 rxq_bytes[XGBE_MAX_DMA_CHANNELS]; 643 644 u64 tx_vxlan_packets; 645 u64 rx_vxlan_packets; 646 u64 rx_csum_errors; 647 u64 rx_vxlan_csum_errors; 648 }; 649 650 struct xgbe_hw_if { 651 int (*tx_complete)(struct xgbe_ring_desc *); 652 653 int (*set_mac_address)(struct xgbe_prv_data *, const u8 *addr); 654 int (*config_rx_mode)(struct xgbe_prv_data *); 655 656 int (*enable_rx_csum)(struct xgbe_prv_data *); 657 int (*disable_rx_csum)(struct xgbe_prv_data *); 658 659 int (*enable_rx_vlan_stripping)(struct xgbe_prv_data *); 660 int (*disable_rx_vlan_stripping)(struct xgbe_prv_data *); 661 int (*enable_rx_vlan_filtering)(struct xgbe_prv_data *); 662 int (*disable_rx_vlan_filtering)(struct xgbe_prv_data *); 663 int (*update_vlan_hash_table)(struct xgbe_prv_data *); 664 665 int (*read_mmd_regs)(struct xgbe_prv_data *, int, int); 666 void (*write_mmd_regs)(struct xgbe_prv_data *, int, int, int); 667 int (*set_speed)(struct xgbe_prv_data *, int); 668 669 int (*set_ext_mii_mode)(struct xgbe_prv_data *, unsigned int, 670 enum xgbe_mdio_mode); 671 int (*read_ext_mii_regs_c22)(struct xgbe_prv_data *, int, int); 672 int (*write_ext_mii_regs_c22)(struct xgbe_prv_data *, int, int, u16); 673 int (*read_ext_mii_regs_c45)(struct xgbe_prv_data *, int, int, int); 674 int (*write_ext_mii_regs_c45)(struct xgbe_prv_data *, int, int, int, 675 u16); 676 677 int (*set_gpio)(struct xgbe_prv_data *, unsigned int); 678 int (*clr_gpio)(struct xgbe_prv_data *, unsigned int); 679 680 void (*enable_tx)(struct xgbe_prv_data *); 681 void (*disable_tx)(struct xgbe_prv_data *); 682 void (*enable_rx)(struct xgbe_prv_data *); 683 void (*disable_rx)(struct xgbe_prv_data *); 684 685 void (*powerup_tx)(struct xgbe_prv_data *); 686 void (*powerdown_tx)(struct xgbe_prv_data *); 687 void (*powerup_rx)(struct xgbe_prv_data *); 688 void (*powerdown_rx)(struct xgbe_prv_data *); 689 690 int (*init)(struct xgbe_prv_data *); 691 int (*exit)(struct xgbe_prv_data *); 692 693 int (*enable_int)(struct xgbe_channel *, enum xgbe_int); 694 int (*disable_int)(struct xgbe_channel *, enum xgbe_int); 695 void (*dev_xmit)(struct xgbe_channel *); 696 int (*dev_read)(struct xgbe_channel *); 697 void (*tx_desc_init)(struct xgbe_channel *); 698 void (*rx_desc_init)(struct xgbe_channel *); 699 void (*tx_desc_reset)(struct xgbe_ring_data *); 700 void (*rx_desc_reset)(struct xgbe_prv_data *, struct xgbe_ring_data *, 701 unsigned int); 702 int (*is_last_desc)(struct xgbe_ring_desc *); 703 int (*is_context_desc)(struct xgbe_ring_desc *); 704 void (*tx_start_xmit)(struct xgbe_channel *, struct xgbe_ring *); 705 706 /* For FLOW ctrl */ 707 int (*config_tx_flow_control)(struct xgbe_prv_data *); 708 int (*config_rx_flow_control)(struct xgbe_prv_data *); 709 710 /* For RX coalescing */ 711 int (*config_rx_coalesce)(struct xgbe_prv_data *); 712 int (*config_tx_coalesce)(struct xgbe_prv_data *); 713 unsigned int (*usec_to_riwt)(struct xgbe_prv_data *, unsigned int); 714 unsigned int (*riwt_to_usec)(struct xgbe_prv_data *, unsigned int); 715 716 /* For RX and TX threshold config */ 717 int (*config_rx_threshold)(struct xgbe_prv_data *, unsigned int); 718 int (*config_tx_threshold)(struct xgbe_prv_data *, unsigned int); 719 720 /* For RX and TX Store and Forward Mode config */ 721 int (*config_rsf_mode)(struct xgbe_prv_data *, unsigned int); 722 int (*config_tsf_mode)(struct xgbe_prv_data *, unsigned int); 723 724 /* For TX DMA Operate on Second Frame config */ 725 int (*config_osp_mode)(struct xgbe_prv_data *); 726 727 /* For MMC statistics */ 728 void (*rx_mmc_int)(struct xgbe_prv_data *); 729 void (*tx_mmc_int)(struct xgbe_prv_data *); 730 void (*read_mmc_stats)(struct xgbe_prv_data *); 731 732 /* For Timestamp config */ 733 int (*config_tstamp)(struct xgbe_prv_data *, unsigned int); 734 void (*update_tstamp_addend)(struct xgbe_prv_data *, unsigned int); 735 void (*set_tstamp_time)(struct xgbe_prv_data *, unsigned int sec, 736 unsigned int nsec); 737 u64 (*get_tstamp_time)(struct xgbe_prv_data *); 738 u64 (*get_tx_tstamp)(struct xgbe_prv_data *); 739 740 /* For Data Center Bridging config */ 741 void (*config_tc)(struct xgbe_prv_data *); 742 void (*config_dcb_tc)(struct xgbe_prv_data *); 743 void (*config_dcb_pfc)(struct xgbe_prv_data *); 744 745 /* For Receive Side Scaling */ 746 int (*enable_rss)(struct xgbe_prv_data *); 747 int (*disable_rss)(struct xgbe_prv_data *); 748 int (*set_rss_hash_key)(struct xgbe_prv_data *, const u8 *); 749 int (*set_rss_lookup_table)(struct xgbe_prv_data *, const u32 *); 750 751 /* For ECC */ 752 void (*disable_ecc_ded)(struct xgbe_prv_data *); 753 void (*disable_ecc_sec)(struct xgbe_prv_data *, enum xgbe_ecc_sec); 754 755 /* For VXLAN */ 756 void (*enable_vxlan)(struct xgbe_prv_data *); 757 void (*disable_vxlan)(struct xgbe_prv_data *); 758 void (*set_vxlan_id)(struct xgbe_prv_data *); 759 }; 760 761 /* This structure represents implementation specific routines for an 762 * implementation of a PHY. All routines are required unless noted below. 763 * Optional routines: 764 * an_pre, an_post 765 * kr_training_pre, kr_training_post 766 * module_info, module_eeprom 767 */ 768 struct xgbe_phy_impl_if { 769 /* Perform Setup/teardown actions */ 770 int (*init)(struct xgbe_prv_data *); 771 void (*exit)(struct xgbe_prv_data *); 772 773 /* Perform start/stop specific actions */ 774 int (*reset)(struct xgbe_prv_data *); 775 int (*start)(struct xgbe_prv_data *); 776 void (*stop)(struct xgbe_prv_data *); 777 778 /* Return the link status */ 779 int (*link_status)(struct xgbe_prv_data *, int *); 780 781 /* Indicate if a particular speed is valid */ 782 bool (*valid_speed)(struct xgbe_prv_data *, int); 783 784 /* Check if the specified mode can/should be used */ 785 bool (*use_mode)(struct xgbe_prv_data *, enum xgbe_mode); 786 /* Switch the PHY into various modes */ 787 void (*set_mode)(struct xgbe_prv_data *, enum xgbe_mode); 788 /* Retrieve mode needed for a specific speed */ 789 enum xgbe_mode (*get_mode)(struct xgbe_prv_data *, int); 790 /* Retrieve new/next mode when trying to auto-negotiate */ 791 enum xgbe_mode (*switch_mode)(struct xgbe_prv_data *); 792 /* Retrieve current mode */ 793 enum xgbe_mode (*cur_mode)(struct xgbe_prv_data *); 794 795 /* Retrieve current auto-negotiation mode */ 796 enum xgbe_an_mode (*an_mode)(struct xgbe_prv_data *); 797 798 /* Configure auto-negotiation settings */ 799 int (*an_config)(struct xgbe_prv_data *); 800 801 /* Set/override auto-negotiation advertisement settings */ 802 void (*an_advertising)(struct xgbe_prv_data *, 803 struct ethtool_link_ksettings *); 804 805 /* Process results of auto-negotiation */ 806 enum xgbe_mode (*an_outcome)(struct xgbe_prv_data *); 807 808 /* Pre/Post auto-negotiation support */ 809 void (*an_pre)(struct xgbe_prv_data *); 810 void (*an_post)(struct xgbe_prv_data *); 811 812 /* Pre/Post KR training enablement support */ 813 void (*kr_training_pre)(struct xgbe_prv_data *); 814 void (*kr_training_post)(struct xgbe_prv_data *); 815 816 /* SFP module related info */ 817 int (*module_info)(struct xgbe_prv_data *pdata, 818 struct ethtool_modinfo *modinfo); 819 int (*module_eeprom)(struct xgbe_prv_data *pdata, 820 struct ethtool_eeprom *eeprom, u8 *data); 821 }; 822 823 struct xgbe_phy_if { 824 /* For PHY setup/teardown */ 825 int (*phy_init)(struct xgbe_prv_data *); 826 void (*phy_exit)(struct xgbe_prv_data *); 827 828 /* For PHY support when setting device up/down */ 829 int (*phy_reset)(struct xgbe_prv_data *); 830 int (*phy_start)(struct xgbe_prv_data *); 831 void (*phy_stop)(struct xgbe_prv_data *); 832 833 /* For PHY support while device is up */ 834 void (*phy_status)(struct xgbe_prv_data *); 835 int (*phy_config_aneg)(struct xgbe_prv_data *); 836 837 /* For PHY settings validation */ 838 bool (*phy_valid_speed)(struct xgbe_prv_data *, int); 839 840 /* For single interrupt support */ 841 irqreturn_t (*an_isr)(struct xgbe_prv_data *); 842 843 /* For ethtool PHY support */ 844 int (*module_info)(struct xgbe_prv_data *pdata, 845 struct ethtool_modinfo *modinfo); 846 int (*module_eeprom)(struct xgbe_prv_data *pdata, 847 struct ethtool_eeprom *eeprom, u8 *data); 848 849 /* PHY implementation specific services */ 850 struct xgbe_phy_impl_if phy_impl; 851 }; 852 853 struct xgbe_i2c_if { 854 /* For initial I2C setup */ 855 int (*i2c_init)(struct xgbe_prv_data *); 856 857 /* For I2C support when setting device up/down */ 858 int (*i2c_start)(struct xgbe_prv_data *); 859 void (*i2c_stop)(struct xgbe_prv_data *); 860 861 /* For performing I2C operations */ 862 int (*i2c_xfer)(struct xgbe_prv_data *, struct xgbe_i2c_op *); 863 864 /* For single interrupt support */ 865 irqreturn_t (*i2c_isr)(struct xgbe_prv_data *); 866 }; 867 868 struct xgbe_desc_if { 869 int (*alloc_ring_resources)(struct xgbe_prv_data *); 870 void (*free_ring_resources)(struct xgbe_prv_data *); 871 int (*map_tx_skb)(struct xgbe_channel *, struct sk_buff *); 872 int (*map_rx_buffer)(struct xgbe_prv_data *, struct xgbe_ring *, 873 struct xgbe_ring_data *); 874 void (*unmap_rdata)(struct xgbe_prv_data *, struct xgbe_ring_data *); 875 void (*wrapper_tx_desc_init)(struct xgbe_prv_data *); 876 void (*wrapper_rx_desc_init)(struct xgbe_prv_data *); 877 }; 878 879 /* This structure contains flags that indicate what hardware features 880 * or configurations are present in the device. 881 */ 882 struct xgbe_hw_features { 883 /* HW Version */ 884 unsigned int version; 885 886 /* HW Feature Register0 */ 887 unsigned int gmii; /* 1000 Mbps support */ 888 unsigned int vlhash; /* VLAN Hash Filter */ 889 unsigned int sma; /* SMA(MDIO) Interface */ 890 unsigned int rwk; /* PMT remote wake-up packet */ 891 unsigned int mgk; /* PMT magic packet */ 892 unsigned int mmc; /* RMON module */ 893 unsigned int aoe; /* ARP Offload */ 894 unsigned int ts; /* IEEE 1588-2008 Advanced Timestamp */ 895 unsigned int eee; /* Energy Efficient Ethernet */ 896 unsigned int tx_coe; /* Tx Checksum Offload */ 897 unsigned int rx_coe; /* Rx Checksum Offload */ 898 unsigned int addn_mac; /* Additional MAC Addresses */ 899 unsigned int ts_src; /* Timestamp Source */ 900 unsigned int sa_vlan_ins; /* Source Address or VLAN Insertion */ 901 unsigned int vxn; /* VXLAN/NVGRE */ 902 903 /* HW Feature Register1 */ 904 unsigned int rx_fifo_size; /* MTL Receive FIFO Size */ 905 unsigned int tx_fifo_size; /* MTL Transmit FIFO Size */ 906 unsigned int adv_ts_hi; /* Advance Timestamping High Word */ 907 unsigned int dma_width; /* DMA width */ 908 unsigned int dcb; /* DCB Feature */ 909 unsigned int sph; /* Split Header Feature */ 910 unsigned int tso; /* TCP Segmentation Offload */ 911 unsigned int dma_debug; /* DMA Debug Registers */ 912 unsigned int rss; /* Receive Side Scaling */ 913 unsigned int tc_cnt; /* Number of Traffic Classes */ 914 unsigned int hash_table_size; /* Hash Table Size */ 915 unsigned int l3l4_filter_num; /* Number of L3-L4 Filters */ 916 917 /* HW Feature Register2 */ 918 unsigned int rx_q_cnt; /* Number of MTL Receive Queues */ 919 unsigned int tx_q_cnt; /* Number of MTL Transmit Queues */ 920 unsigned int rx_ch_cnt; /* Number of DMA Receive Channels */ 921 unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */ 922 unsigned int pps_out_num; /* Number of PPS outputs */ 923 unsigned int aux_snap_num; /* Number of Aux snapshot inputs */ 924 }; 925 926 struct xgbe_version_data { 927 void (*init_function_ptrs_phy_impl)(struct xgbe_phy_if *); 928 enum xgbe_xpcs_access xpcs_access; 929 unsigned int mmc_64bit; 930 unsigned int tx_max_fifo_size; 931 unsigned int rx_max_fifo_size; 932 unsigned int tx_tstamp_workaround; 933 unsigned int ecc_support; 934 unsigned int i2c_support; 935 unsigned int irq_reissue_support; 936 unsigned int tx_desc_prefetch; 937 unsigned int rx_desc_prefetch; 938 unsigned int an_cdr_workaround; 939 unsigned int enable_rrc; 940 }; 941 942 struct xgbe_prv_data { 943 struct net_device *netdev; 944 struct pci_dev *pcidev; 945 struct platform_device *platdev; 946 struct acpi_device *adev; 947 struct device *dev; 948 struct platform_device *phy_platdev; 949 struct device *phy_dev; 950 951 /* Version related data */ 952 struct xgbe_version_data *vdata; 953 954 /* ACPI or DT flag */ 955 unsigned int use_acpi; 956 957 /* XGMAC/XPCS related mmio registers */ 958 void __iomem *xgmac_regs; /* XGMAC CSRs */ 959 void __iomem *xpcs_regs; /* XPCS MMD registers */ 960 void __iomem *rxtx_regs; /* SerDes Rx/Tx CSRs */ 961 void __iomem *sir0_regs; /* SerDes integration registers (1/2) */ 962 void __iomem *sir1_regs; /* SerDes integration registers (2/2) */ 963 void __iomem *xprop_regs; /* XGBE property registers */ 964 void __iomem *xi2c_regs; /* XGBE I2C CSRs */ 965 966 /* Port property registers */ 967 unsigned int pp0; 968 unsigned int pp1; 969 unsigned int pp2; 970 unsigned int pp3; 971 unsigned int pp4; 972 973 /* Overall device lock */ 974 spinlock_t lock; 975 976 /* XPCS indirect addressing lock */ 977 spinlock_t xpcs_lock; 978 unsigned int xpcs_window_def_reg; 979 unsigned int xpcs_window_sel_reg; 980 unsigned int xpcs_window; 981 unsigned int xpcs_window_size; 982 unsigned int xpcs_window_mask; 983 984 /* RSS addressing mutex */ 985 struct mutex rss_mutex; 986 987 /* Flags representing xgbe_state */ 988 unsigned long dev_state; 989 990 /* ECC support */ 991 unsigned long tx_sec_period; 992 unsigned long tx_ded_period; 993 unsigned long rx_sec_period; 994 unsigned long rx_ded_period; 995 unsigned long desc_sec_period; 996 unsigned long desc_ded_period; 997 998 unsigned int tx_sec_count; 999 unsigned int tx_ded_count; 1000 unsigned int rx_sec_count; 1001 unsigned int rx_ded_count; 1002 unsigned int desc_ded_count; 1003 unsigned int desc_sec_count; 1004 1005 int dev_irq; 1006 int ecc_irq; 1007 int i2c_irq; 1008 int channel_irq[XGBE_MAX_DMA_CHANNELS]; 1009 1010 unsigned int per_channel_irq; 1011 unsigned int irq_count; 1012 unsigned int channel_irq_count; 1013 unsigned int channel_irq_mode; 1014 1015 char ecc_name[IFNAMSIZ + 32]; 1016 1017 struct xgbe_hw_if hw_if; 1018 struct xgbe_phy_if phy_if; 1019 struct xgbe_desc_if desc_if; 1020 struct xgbe_i2c_if i2c_if; 1021 1022 /* AXI DMA settings */ 1023 unsigned int coherent; 1024 unsigned int arcr; 1025 unsigned int awcr; 1026 unsigned int awarcr; 1027 1028 /* Service routine support */ 1029 struct workqueue_struct *dev_workqueue; 1030 struct work_struct service_work; 1031 struct timer_list service_timer; 1032 1033 /* Rings for Tx/Rx on a DMA channel */ 1034 struct xgbe_channel *channel[XGBE_MAX_DMA_CHANNELS]; 1035 unsigned int tx_max_channel_count; 1036 unsigned int rx_max_channel_count; 1037 unsigned int channel_count; 1038 unsigned int tx_ring_count; 1039 unsigned int tx_desc_count; 1040 unsigned int rx_ring_count; 1041 unsigned int rx_desc_count; 1042 1043 unsigned int new_tx_ring_count; 1044 unsigned int new_rx_ring_count; 1045 1046 unsigned int tx_max_q_count; 1047 unsigned int rx_max_q_count; 1048 unsigned int tx_q_count; 1049 unsigned int rx_q_count; 1050 1051 /* Tx/Rx common settings */ 1052 unsigned int blen; 1053 unsigned int pbl; 1054 unsigned int aal; 1055 unsigned int rd_osr_limit; 1056 unsigned int wr_osr_limit; 1057 1058 /* Tx settings */ 1059 unsigned int tx_sf_mode; 1060 unsigned int tx_threshold; 1061 unsigned int tx_osp_mode; 1062 unsigned int tx_max_fifo_size; 1063 1064 /* Rx settings */ 1065 unsigned int rx_sf_mode; 1066 unsigned int rx_threshold; 1067 unsigned int rx_max_fifo_size; 1068 1069 /* Tx coalescing settings */ 1070 unsigned int tx_usecs; 1071 unsigned int tx_frames; 1072 1073 /* Rx coalescing settings */ 1074 unsigned int rx_riwt; 1075 unsigned int rx_usecs; 1076 unsigned int rx_frames; 1077 1078 /* Current Rx buffer size */ 1079 unsigned int rx_buf_size; 1080 1081 /* Flow control settings */ 1082 unsigned int pause_autoneg; 1083 unsigned int tx_pause; 1084 unsigned int rx_pause; 1085 unsigned int rx_rfa[XGBE_MAX_QUEUES]; 1086 unsigned int rx_rfd[XGBE_MAX_QUEUES]; 1087 1088 /* Receive Side Scaling settings */ 1089 u8 rss_key[XGBE_RSS_HASH_KEY_SIZE]; 1090 u32 rss_table[XGBE_RSS_MAX_TABLE_SIZE]; 1091 u32 rss_options; 1092 1093 /* VXLAN settings */ 1094 u16 vxlan_port; 1095 1096 /* Netdev related settings */ 1097 unsigned char mac_addr[ETH_ALEN]; 1098 netdev_features_t netdev_features; 1099 struct napi_struct napi; 1100 struct xgbe_mmc_stats mmc_stats; 1101 struct xgbe_ext_stats ext_stats; 1102 1103 /* Filtering support */ 1104 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 1105 1106 /* Device clocks */ 1107 struct clk *sysclk; 1108 unsigned long sysclk_rate; 1109 struct clk *ptpclk; 1110 unsigned long ptpclk_rate; 1111 1112 /* Timestamp support */ 1113 spinlock_t tstamp_lock; 1114 struct ptp_clock_info ptp_clock_info; 1115 struct ptp_clock *ptp_clock; 1116 struct hwtstamp_config tstamp_config; 1117 struct cyclecounter tstamp_cc; 1118 struct timecounter tstamp_tc; 1119 unsigned int tstamp_addend; 1120 struct work_struct tx_tstamp_work; 1121 struct sk_buff *tx_tstamp_skb; 1122 u64 tx_tstamp; 1123 1124 /* DCB support */ 1125 struct ieee_ets *ets; 1126 struct ieee_pfc *pfc; 1127 unsigned int q2tc_map[XGBE_MAX_QUEUES]; 1128 unsigned int prio2q_map[IEEE_8021QAZ_MAX_TCS]; 1129 unsigned int pfcq[XGBE_MAX_QUEUES]; 1130 unsigned int pfc_rfa; 1131 u8 num_tcs; 1132 1133 /* Hardware features of the device */ 1134 struct xgbe_hw_features hw_feat; 1135 1136 /* Device work structures */ 1137 struct work_struct restart_work; 1138 struct work_struct stopdev_work; 1139 1140 /* Keeps track of power mode */ 1141 unsigned int power_down; 1142 1143 /* Network interface message level setting */ 1144 u32 msg_enable; 1145 1146 /* Current PHY settings */ 1147 phy_interface_t phy_mode; 1148 int phy_link; 1149 int phy_speed; 1150 1151 /* MDIO/PHY related settings */ 1152 unsigned int phy_started; 1153 void *phy_data; 1154 struct xgbe_phy phy; 1155 int mdio_mmd; 1156 unsigned long link_check; 1157 struct completion mdio_complete; 1158 1159 unsigned int kr_redrv; 1160 1161 char an_name[IFNAMSIZ + 32]; 1162 struct workqueue_struct *an_workqueue; 1163 1164 int an_irq; 1165 struct work_struct an_irq_work; 1166 1167 /* Auto-negotiation state machine support */ 1168 unsigned int an_int; 1169 unsigned int an_status; 1170 struct mutex an_mutex; 1171 enum xgbe_an an_result; 1172 enum xgbe_an an_state; 1173 enum xgbe_rx kr_state; 1174 enum xgbe_rx kx_state; 1175 struct work_struct an_work; 1176 unsigned int an_again; 1177 unsigned int an_supported; 1178 unsigned int parallel_detect; 1179 unsigned int fec_ability; 1180 unsigned long an_start; 1181 unsigned long kr_start_time; 1182 enum xgbe_an_mode an_mode; 1183 1184 /* I2C support */ 1185 struct xgbe_i2c i2c; 1186 struct mutex i2c_mutex; 1187 struct completion i2c_complete; 1188 char i2c_name[IFNAMSIZ + 32]; 1189 1190 unsigned int lpm_ctrl; /* CTRL1 for resume */ 1191 1192 unsigned int isr_as_bh_work; 1193 struct work_struct dev_bh_work; 1194 struct work_struct ecc_bh_work; 1195 struct work_struct i2c_bh_work; 1196 struct work_struct an_bh_work; 1197 1198 struct dentry *xgbe_debugfs; 1199 1200 unsigned int debugfs_xgmac_reg; 1201 1202 unsigned int debugfs_xpcs_mmd; 1203 unsigned int debugfs_xpcs_reg; 1204 1205 unsigned int debugfs_xprop_reg; 1206 1207 unsigned int debugfs_xi2c_reg; 1208 1209 bool debugfs_an_cdr_workaround; 1210 bool debugfs_an_cdr_track_early; 1211 bool en_rx_adap; 1212 int rx_adapt_retries; 1213 bool rx_adapt_done; 1214 bool mode_set; 1215 }; 1216 1217 /* Function prototypes*/ 1218 struct xgbe_prv_data *xgbe_alloc_pdata(struct device *); 1219 void xgbe_free_pdata(struct xgbe_prv_data *); 1220 void xgbe_set_counts(struct xgbe_prv_data *); 1221 int xgbe_config_netdev(struct xgbe_prv_data *); 1222 void xgbe_deconfig_netdev(struct xgbe_prv_data *); 1223 1224 int xgbe_platform_init(void); 1225 void xgbe_platform_exit(void); 1226 #ifdef CONFIG_PCI 1227 int xgbe_pci_init(void); 1228 void xgbe_pci_exit(void); 1229 #else 1230 static inline int xgbe_pci_init(void) { return 0; } 1231 static inline void xgbe_pci_exit(void) { } 1232 #endif 1233 1234 void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *); 1235 void xgbe_init_function_ptrs_phy(struct xgbe_phy_if *); 1236 void xgbe_init_function_ptrs_phy_v1(struct xgbe_phy_if *); 1237 void xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *); 1238 void xgbe_init_function_ptrs_desc(struct xgbe_desc_if *); 1239 void xgbe_init_function_ptrs_i2c(struct xgbe_i2c_if *); 1240 const struct net_device_ops *xgbe_get_netdev_ops(void); 1241 const struct ethtool_ops *xgbe_get_ethtool_ops(void); 1242 const struct udp_tunnel_nic_info *xgbe_get_udp_tunnel_info(void); 1243 1244 #ifdef CONFIG_AMD_XGBE_DCB 1245 const struct dcbnl_rtnl_ops *xgbe_get_dcbnl_ops(void); 1246 #endif 1247 1248 void xgbe_ptp_register(struct xgbe_prv_data *); 1249 void xgbe_ptp_unregister(struct xgbe_prv_data *); 1250 void xgbe_dump_tx_desc(struct xgbe_prv_data *, struct xgbe_ring *, 1251 unsigned int, unsigned int, unsigned int); 1252 void xgbe_dump_rx_desc(struct xgbe_prv_data *, struct xgbe_ring *, 1253 unsigned int); 1254 void xgbe_print_pkt(struct net_device *, struct sk_buff *, bool); 1255 void xgbe_get_all_hw_features(struct xgbe_prv_data *); 1256 int xgbe_powerup(struct net_device *, unsigned int); 1257 int xgbe_powerdown(struct net_device *, unsigned int); 1258 void xgbe_init_rx_coalesce(struct xgbe_prv_data *); 1259 void xgbe_init_tx_coalesce(struct xgbe_prv_data *); 1260 void xgbe_restart_dev(struct xgbe_prv_data *pdata); 1261 void xgbe_full_restart_dev(struct xgbe_prv_data *pdata); 1262 1263 #ifdef CONFIG_DEBUG_FS 1264 void xgbe_debugfs_init(struct xgbe_prv_data *); 1265 void xgbe_debugfs_exit(struct xgbe_prv_data *); 1266 void xgbe_debugfs_rename(struct xgbe_prv_data *pdata); 1267 #else 1268 static inline void xgbe_debugfs_init(struct xgbe_prv_data *pdata) {} 1269 static inline void xgbe_debugfs_exit(struct xgbe_prv_data *pdata) {} 1270 static inline void xgbe_debugfs_rename(struct xgbe_prv_data *pdata) {} 1271 #endif /* CONFIG_DEBUG_FS */ 1272 1273 /* NOTE: Uncomment for function trace log messages in KERNEL LOG */ 1274 #if 0 1275 #define YDEBUG 1276 #define YDEBUG_MDIO 1277 #endif 1278 1279 /* For debug prints */ 1280 #ifdef YDEBUG 1281 #define DBGPR(x...) pr_alert(x) 1282 #else 1283 #define DBGPR(x...) do { } while (0) 1284 #endif 1285 1286 #ifdef YDEBUG_MDIO 1287 #define DBGPR_MDIO(x...) pr_alert(x) 1288 #else 1289 #define DBGPR_MDIO(x...) do { } while (0) 1290 #endif 1291 1292 #endif 1293