1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) 2 /* 3 * Copyright (c) 2014-2025, Advanced Micro Devices, Inc. 4 * Copyright (c) 2014, Synopsys, Inc. 5 * All rights reserved 6 */ 7 8 #ifndef __XGBE_H__ 9 #define __XGBE_H__ 10 11 #include <linux/dma-mapping.h> 12 #include <linux/netdevice.h> 13 #include <linux/workqueue.h> 14 #include <linux/phy.h> 15 #include <linux/if_vlan.h> 16 #include <linux/bitops.h> 17 #include <linux/ptp_clock_kernel.h> 18 #include <linux/timecounter.h> 19 #include <linux/net_tstamp.h> 20 #include <net/dcbnl.h> 21 #include <linux/completion.h> 22 #include <linux/cpumask.h> 23 #include <linux/interrupt.h> 24 #include <linux/dcache.h> 25 #include <linux/ethtool.h> 26 #include <linux/list.h> 27 28 #define XGBE_DRV_NAME "amd-xgbe" 29 #define XGBE_DRV_DESC "AMD 10 Gigabit Ethernet Driver" 30 31 /* Descriptor related defines */ 32 #define XGBE_TX_DESC_CNT 512 33 #define XGBE_TX_DESC_MIN_FREE (XGBE_TX_DESC_CNT >> 3) 34 #define XGBE_TX_DESC_MAX_PROC (XGBE_TX_DESC_CNT >> 1) 35 #define XGBE_RX_DESC_CNT 512 36 37 #define XGBE_TX_DESC_CNT_MIN 64 38 #define XGBE_TX_DESC_CNT_MAX 4096 39 #define XGBE_RX_DESC_CNT_MIN 64 40 #define XGBE_RX_DESC_CNT_MAX 4096 41 42 #define XGBE_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1)) 43 44 /* Descriptors required for maximum contiguous TSO/GSO packet */ 45 #define XGBE_TX_MAX_SPLIT \ 46 ((GSO_LEGACY_MAX_SIZE / XGBE_TX_MAX_BUF_SIZE) + 1) 47 48 /* Maximum possible descriptors needed for an SKB: 49 * - Maximum number of SKB frags 50 * - Maximum descriptors for contiguous TSO/GSO packet 51 * - Possible context descriptor 52 * - Possible TSO header descriptor 53 */ 54 #define XGBE_TX_MAX_DESCS (MAX_SKB_FRAGS + XGBE_TX_MAX_SPLIT + 2) 55 56 #define XGBE_RX_MIN_BUF_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN) 57 #define XGBE_RX_BUF_ALIGN 64 58 #define XGBE_SKB_ALLOC_SIZE 256 59 #define XGBE_SPH_HDSMS_SIZE 2 /* Keep in sync with SKB_ALLOC_SIZE */ 60 61 #define XGBE_MAX_DMA_CHANNELS 16 62 #define XGBE_MAX_QUEUES 16 63 #define XGBE_PRIORITY_QUEUES 8 64 #define XGBE_DMA_STOP_TIMEOUT 1 65 66 /* DMA cache settings - Outer sharable, write-back, write-allocate */ 67 #define XGBE_DMA_OS_ARCR 0x002b2b2b 68 #define XGBE_DMA_OS_AWCR 0x2f2f2f2f 69 70 /* DMA cache settings - System, no caches used */ 71 #define XGBE_DMA_SYS_ARCR 0x00303030 72 #define XGBE_DMA_SYS_AWCR 0x30303030 73 74 /* DMA cache settings - PCI device */ 75 #define XGBE_DMA_PCI_ARCR 0x000f0f0f 76 #define XGBE_DMA_PCI_AWCR 0x0f0f0f0f 77 #define XGBE_DMA_PCI_AWARCR 0x00000f0f 78 79 /* DMA channel interrupt modes */ 80 #define XGBE_IRQ_MODE_EDGE 0 81 #define XGBE_IRQ_MODE_LEVEL 1 82 83 #define XGBE_ETH_FRAME_HDR (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN) 84 #define XGMAC_MIN_PACKET 60 85 #define XGMAC_STD_PACKET_MTU 1500 86 #define XGMAC_MAX_STD_PACKET 1518 87 #define XGMAC_JUMBO_PACKET_MTU 9000 88 #define XGMAC_MAX_JUMBO_PACKET 9018 89 #define XGMAC_GIANT_PACKET_MTU 16368 90 #define XGMAC_ETH_PREAMBLE (12 + 8) /* Inter-frame gap + preamble */ 91 92 #define XGMAC_PFC_DATA_LEN 46 93 #define XGMAC_PFC_DELAYS 14000 94 95 #define XGMAC_PRIO_QUEUES(_cnt) \ 96 min_t(unsigned int, IEEE_8021QAZ_MAX_TCS, (_cnt)) 97 98 /* Common property names */ 99 #define XGBE_MAC_ADDR_PROPERTY "mac-address" 100 #define XGBE_PHY_MODE_PROPERTY "phy-mode" 101 #define XGBE_DMA_IRQS_PROPERTY "amd,per-channel-interrupt" 102 #define XGBE_SPEEDSET_PROPERTY "amd,speed-set" 103 104 /* Device-tree clock names */ 105 #define XGBE_DMA_CLOCK "dma_clk" 106 #define XGBE_PTP_CLOCK "ptp_clk" 107 108 /* ACPI property names */ 109 #define XGBE_ACPI_DMA_FREQ "amd,dma-freq" 110 #define XGBE_ACPI_PTP_FREQ "amd,ptp-freq" 111 112 /* PCI BAR mapping */ 113 #define XGBE_XGMAC_BAR 0 114 #define XGBE_XPCS_BAR 1 115 #define XGBE_MAC_PROP_OFFSET 0x1d000 116 #define XGBE_I2C_CTRL_OFFSET 0x1e000 117 118 /* PCI MSI/MSIx support */ 119 #define XGBE_MSI_BASE_COUNT 4 120 #define XGBE_MSI_MIN_COUNT (XGBE_MSI_BASE_COUNT + 1) 121 122 /* Initial PTP register values based on Link Speed. */ 123 #define MAC_TICNR_1G_INITVAL 0x10 124 #define MAC_TECNR_1G_INITVAL 0x28 125 126 #define MAC_TICSNR_10G_INITVAL 0x33 127 #define MAC_TECNR_10G_INITVAL 0x14 128 #define MAC_TECSNR_10G_INITVAL 0xCC 129 130 /* PCI clock frequencies */ 131 #define XGBE_V2_DMA_CLOCK_FREQ 500000000 /* 500 MHz */ 132 #define XGBE_V2_PTP_CLOCK_FREQ 125000000 /* 125 MHz */ 133 134 /* Timestamp support - values based on 50MHz PTP clock 135 * 50MHz => 20 nsec 136 */ 137 #define XGBE_TSTAMP_SSINC 20 138 #define XGBE_TSTAMP_SNSINC 0 139 #define XGBE_PTP_ACT_CLK_FREQ 500000000 140 141 #define XGBE_V2_TSTAMP_SSINC 0xA 142 #define XGBE_V2_TSTAMP_SNSINC 0 143 #define XGBE_V2_PTP_ACT_CLK_FREQ 1000000000 144 145 /* Driver PMT macros */ 146 #define XGMAC_DRIVER_CONTEXT 1 147 #define XGMAC_IOCTL_CONTEXT 2 148 149 #define XGMAC_FIFO_MIN_ALLOC 2048 150 #define XGMAC_FIFO_UNIT 256 151 #define XGMAC_FIFO_ALIGN(_x) \ 152 (((_x) + XGMAC_FIFO_UNIT - 1) & ~(XGMAC_FIFO_UNIT - 1)) 153 #define XGMAC_FIFO_FC_OFF 2048 154 #define XGMAC_FIFO_FC_MIN 4096 155 156 #define XGBE_TC_MIN_QUANTUM 10 157 158 /* Helper macro for descriptor handling 159 * Always use XGBE_GET_DESC_DATA to access the descriptor data 160 * since the index is free-running and needs to be and-ed 161 * with the descriptor count value of the ring to index to 162 * the proper descriptor data. 163 */ 164 #define XGBE_GET_DESC_DATA(_ring, _idx) \ 165 ((_ring)->rdata + \ 166 ((_idx) & ((_ring)->rdesc_count - 1))) 167 168 /* Default coalescing parameters */ 169 #define XGMAC_INIT_DMA_TX_USECS 1000 170 #define XGMAC_INIT_DMA_TX_FRAMES 25 171 #define XGMAC_MAX_COAL_TX_TICK 100000 172 173 #define XGMAC_MAX_DMA_RIWT 0xff 174 #define XGMAC_INIT_DMA_RX_USECS 30 175 #define XGMAC_INIT_DMA_RX_FRAMES 25 176 177 /* Flow control queue count */ 178 #define XGMAC_MAX_FLOW_CONTROL_QUEUES 8 179 180 /* Flow control threshold units */ 181 #define XGMAC_FLOW_CONTROL_UNIT 512 182 #define XGMAC_FLOW_CONTROL_ALIGN(_x) \ 183 (((_x) + XGMAC_FLOW_CONTROL_UNIT - 1) & ~(XGMAC_FLOW_CONTROL_UNIT - 1)) 184 #define XGMAC_FLOW_CONTROL_VALUE(_x) \ 185 (((_x) < 1024) ? 0 : ((_x) / XGMAC_FLOW_CONTROL_UNIT) - 2) 186 #define XGMAC_FLOW_CONTROL_MAX 33280 187 188 /* Maximum MAC address hash table size (256 bits = 8 bytes) */ 189 #define XGBE_MAC_HASH_TABLE_SIZE 8 190 191 /* Receive Side Scaling */ 192 #define XGBE_RSS_HASH_KEY_SIZE 40 193 #define XGBE_RSS_MAX_TABLE_SIZE 256 194 #define XGBE_RSS_LOOKUP_TABLE_TYPE 0 195 #define XGBE_RSS_HASH_KEY_TYPE 1 196 197 /* Auto-negotiation */ 198 #define XGBE_AN_MS_TIMEOUT 500 199 #define XGBE_LINK_TIMEOUT 5 200 #define XGBE_KR_TRAINING_WAIT_ITER 50 201 202 #define XGBE_SGMII_AN_LINK_DUPLEX BIT(1) 203 #define XGBE_SGMII_AN_LINK_SPEED (BIT(2) | BIT(3)) 204 #define XGBE_SGMII_AN_LINK_SPEED_10 0x00 205 #define XGBE_SGMII_AN_LINK_SPEED_100 0x04 206 #define XGBE_SGMII_AN_LINK_SPEED_1000 0x08 207 #define XGBE_SGMII_AN_LINK_STATUS BIT(4) 208 209 /* ECC correctable error notification window (seconds) */ 210 #define XGBE_ECC_LIMIT 60 211 212 /* MDIO port types */ 213 #define XGMAC_MAX_C22_PORT 3 214 215 /* Link mode bit operations */ 216 #define XGBE_ZERO_SUP(_ls) \ 217 ethtool_link_ksettings_zero_link_mode((_ls), supported) 218 219 #define XGBE_SET_SUP(_ls, _mode) \ 220 ethtool_link_ksettings_add_link_mode((_ls), supported, _mode) 221 222 #define XGBE_CLR_SUP(_ls, _mode) \ 223 ethtool_link_ksettings_del_link_mode((_ls), supported, _mode) 224 225 #define XGBE_IS_SUP(_ls, _mode) \ 226 ethtool_link_ksettings_test_link_mode((_ls), supported, _mode) 227 228 #define XGBE_ZERO_ADV(_ls) \ 229 ethtool_link_ksettings_zero_link_mode((_ls), advertising) 230 231 #define XGBE_SET_ADV(_ls, _mode) \ 232 ethtool_link_ksettings_add_link_mode((_ls), advertising, _mode) 233 234 #define XGBE_CLR_ADV(_ls, _mode) \ 235 ethtool_link_ksettings_del_link_mode((_ls), advertising, _mode) 236 237 #define XGBE_ADV(_ls, _mode) \ 238 ethtool_link_ksettings_test_link_mode((_ls), advertising, _mode) 239 240 #define XGBE_ZERO_LP_ADV(_ls) \ 241 ethtool_link_ksettings_zero_link_mode((_ls), lp_advertising) 242 243 #define XGBE_SET_LP_ADV(_ls, _mode) \ 244 ethtool_link_ksettings_add_link_mode((_ls), lp_advertising, _mode) 245 246 #define XGBE_CLR_LP_ADV(_ls, _mode) \ 247 ethtool_link_ksettings_del_link_mode((_ls), lp_advertising, _mode) 248 249 #define XGBE_LP_ADV(_ls, _mode) \ 250 ethtool_link_ksettings_test_link_mode((_ls), lp_advertising, _mode) 251 252 #define XGBE_LM_COPY(_dst, _dname, _src, _sname) \ 253 bitmap_copy((_dst)->link_modes._dname, \ 254 (_src)->link_modes._sname, \ 255 __ETHTOOL_LINK_MODE_MASK_NBITS) 256 257 /* XGBE PCI device id */ 258 #define XGBE_RV_PCI_DEVICE_ID 0x15d0 259 #define XGBE_YC_PCI_DEVICE_ID 0x14b5 260 #define XGBE_RN_PCI_DEVICE_ID 0x1630 261 262 /* Generic low and high masks */ 263 #define XGBE_GEN_HI_MASK GENMASK(31, 16) 264 #define XGBE_GEN_LO_MASK GENMASK(15, 0) 265 266 struct xgbe_prv_data; 267 268 struct xgbe_packet_data { 269 struct sk_buff *skb; 270 271 unsigned int attributes; 272 273 unsigned int errors; 274 275 unsigned int rdesc_count; 276 unsigned int length; 277 278 unsigned int header_len; 279 unsigned int tcp_header_len; 280 unsigned int tcp_payload_len; 281 unsigned short mss; 282 283 unsigned short vlan_ctag; 284 285 u64 rx_tstamp; 286 287 u32 rss_hash; 288 enum pkt_hash_types rss_hash_type; 289 290 unsigned int tx_packets; 291 unsigned int tx_bytes; 292 }; 293 294 /* Common Rx and Tx descriptor mapping */ 295 struct xgbe_ring_desc { 296 __le32 desc0; 297 __le32 desc1; 298 __le32 desc2; 299 __le32 desc3; 300 }; 301 302 /* Page allocation related values */ 303 struct xgbe_page_alloc { 304 struct page *pages; 305 unsigned int pages_len; 306 unsigned int pages_offset; 307 308 dma_addr_t pages_dma; 309 }; 310 311 /* Ring entry buffer data */ 312 struct xgbe_buffer_data { 313 struct xgbe_page_alloc pa; 314 struct xgbe_page_alloc pa_unmap; 315 316 dma_addr_t dma_base; 317 unsigned long dma_off; 318 unsigned int dma_len; 319 }; 320 321 /* Tx-related ring data */ 322 struct xgbe_tx_ring_data { 323 unsigned int packets; /* BQL packet count */ 324 unsigned int bytes; /* BQL byte count */ 325 }; 326 327 /* Rx-related ring data */ 328 struct xgbe_rx_ring_data { 329 struct xgbe_buffer_data hdr; /* Header locations */ 330 struct xgbe_buffer_data buf; /* Payload locations */ 331 332 unsigned short hdr_len; /* Length of received header */ 333 unsigned short len; /* Length of received packet */ 334 }; 335 336 /* Structure used to hold information related to the descriptor 337 * and the packet associated with the descriptor (always use 338 * the XGBE_GET_DESC_DATA macro to access this data from the ring) 339 */ 340 struct xgbe_ring_data { 341 struct xgbe_ring_desc *rdesc; /* Virtual address of descriptor */ 342 dma_addr_t rdesc_dma; /* DMA address of descriptor */ 343 344 struct sk_buff *skb; /* Virtual address of SKB */ 345 dma_addr_t skb_dma; /* DMA address of SKB data */ 346 unsigned int skb_dma_len; /* Length of SKB DMA area */ 347 348 struct xgbe_tx_ring_data tx; /* Tx-related data */ 349 struct xgbe_rx_ring_data rx; /* Rx-related data */ 350 351 unsigned int mapped_as_page; 352 353 /* Incomplete receive save location. If the budget is exhausted 354 * or the last descriptor (last normal descriptor or a following 355 * context descriptor) has not been DMA'd yet the current state 356 * of the receive processing needs to be saved. 357 */ 358 unsigned int state_saved; 359 struct { 360 struct sk_buff *skb; 361 unsigned int len; 362 unsigned int error; 363 } state; 364 }; 365 366 struct xgbe_ring { 367 /* Ring lock - used just for TX rings at the moment */ 368 spinlock_t lock; 369 370 /* Per packet related information */ 371 struct xgbe_packet_data packet_data; 372 373 /* Virtual/DMA addresses and count of allocated descriptor memory */ 374 struct xgbe_ring_desc *rdesc; 375 dma_addr_t rdesc_dma; 376 unsigned int rdesc_count; 377 378 /* Array of descriptor data corresponding the descriptor memory 379 * (always use the XGBE_GET_DESC_DATA macro to access this data) 380 */ 381 struct xgbe_ring_data *rdata; 382 383 /* Page allocation for RX buffers */ 384 struct xgbe_page_alloc rx_hdr_pa; 385 struct xgbe_page_alloc rx_buf_pa; 386 int node; 387 388 /* Ring index values 389 * cur - Tx: index of descriptor to be used for current transfer 390 * Rx: index of descriptor to check for packet availability 391 * dirty - Tx: index of descriptor to check for transfer complete 392 * Rx: index of descriptor to check for buffer reallocation 393 */ 394 unsigned int cur; 395 unsigned int dirty; 396 397 /* Coalesce frame count used for interrupt bit setting */ 398 unsigned int coalesce_count; 399 400 union { 401 struct { 402 unsigned int queue_stopped; 403 unsigned int xmit_more; 404 unsigned short cur_mss; 405 unsigned short cur_vlan_ctag; 406 } tx; 407 }; 408 } ____cacheline_aligned; 409 410 /* Structure used to describe the descriptor rings associated with 411 * a DMA channel. 412 */ 413 struct xgbe_channel { 414 char name[20]; 415 416 /* Address of private data area for device */ 417 struct xgbe_prv_data *pdata; 418 419 /* Queue index and base address of queue's DMA registers */ 420 unsigned int queue_index; 421 void __iomem *dma_regs; 422 423 /* Per channel interrupt irq number */ 424 int dma_irq; 425 char dma_irq_name[IFNAMSIZ + 32]; 426 427 /* Netdev related settings */ 428 struct napi_struct napi; 429 430 /* Per channel interrupt enablement tracker */ 431 unsigned int curr_ier; 432 unsigned int saved_ier; 433 434 unsigned int tx_timer_active; 435 struct timer_list tx_timer; 436 437 struct xgbe_ring *tx_ring; 438 struct xgbe_ring *rx_ring; 439 440 int node; 441 cpumask_t affinity_mask; 442 } ____cacheline_aligned; 443 444 enum xgbe_state { 445 XGBE_DOWN, 446 XGBE_LINK_INIT, 447 XGBE_LINK_ERR, 448 XGBE_STOPPED, 449 }; 450 451 enum xgbe_int { 452 XGMAC_INT_DMA_CH_SR_TI, 453 XGMAC_INT_DMA_CH_SR_TPS, 454 XGMAC_INT_DMA_CH_SR_TBU, 455 XGMAC_INT_DMA_CH_SR_RI, 456 XGMAC_INT_DMA_CH_SR_RBU, 457 XGMAC_INT_DMA_CH_SR_RPS, 458 XGMAC_INT_DMA_CH_SR_TI_RI, 459 XGMAC_INT_DMA_CH_SR_FBE, 460 XGMAC_INT_DMA_ALL, 461 }; 462 463 enum xgbe_int_state { 464 XGMAC_INT_STATE_SAVE, 465 XGMAC_INT_STATE_RESTORE, 466 }; 467 468 enum xgbe_ecc_sec { 469 XGBE_ECC_SEC_TX, 470 XGBE_ECC_SEC_RX, 471 XGBE_ECC_SEC_DESC, 472 }; 473 474 enum xgbe_speed { 475 XGBE_SPEED_1000 = 0, 476 XGBE_SPEED_2500, 477 XGBE_SPEED_10000, 478 XGBE_SPEEDS, 479 }; 480 481 enum xgbe_xpcs_access { 482 XGBE_XPCS_ACCESS_V1 = 0, 483 XGBE_XPCS_ACCESS_V2, 484 XGBE_XPCS_ACCESS_V3, 485 }; 486 487 enum xgbe_an_mode { 488 XGBE_AN_MODE_CL73 = 0, 489 XGBE_AN_MODE_CL73_REDRV, 490 XGBE_AN_MODE_CL37, 491 XGBE_AN_MODE_CL37_SGMII, 492 XGBE_AN_MODE_NONE, 493 }; 494 495 enum xgbe_an { 496 XGBE_AN_READY = 0, 497 XGBE_AN_PAGE_RECEIVED, 498 XGBE_AN_INCOMPAT_LINK, 499 XGBE_AN_COMPLETE, 500 XGBE_AN_NO_LINK, 501 XGBE_AN_ERROR, 502 }; 503 504 enum xgbe_rx { 505 XGBE_RX_BPA = 0, 506 XGBE_RX_XNP, 507 XGBE_RX_COMPLETE, 508 XGBE_RX_ERROR, 509 }; 510 511 enum xgbe_mode { 512 XGBE_MODE_KX_1000 = 0, 513 XGBE_MODE_KX_2500, 514 XGBE_MODE_KR, 515 XGBE_MODE_X, 516 XGBE_MODE_SGMII_10, 517 XGBE_MODE_SGMII_100, 518 XGBE_MODE_SGMII_1000, 519 XGBE_MODE_SFI, 520 XGBE_MODE_UNKNOWN, 521 }; 522 523 enum xgbe_speedset { 524 XGBE_SPEEDSET_1000_10000 = 0, 525 XGBE_SPEEDSET_2500_10000, 526 }; 527 528 enum xgbe_mdio_mode { 529 XGBE_MDIO_MODE_NONE = 0, 530 XGBE_MDIO_MODE_CL22, 531 XGBE_MDIO_MODE_CL45, 532 }; 533 534 enum xgbe_mb_cmd { 535 XGBE_MB_CMD_POWER_OFF = 0, 536 XGBE_MB_CMD_SET_1G, 537 XGBE_MB_CMD_SET_2_5G, 538 XGBE_MB_CMD_SET_10G_SFI, 539 XGBE_MB_CMD_SET_10G_KR, 540 XGBE_MB_CMD_RRC 541 }; 542 543 enum xgbe_mb_subcmd { 544 XGBE_MB_SUBCMD_NONE = 0, 545 XGBE_MB_SUBCMD_RX_ADAP, 546 547 /* 10GbE SFP subcommands */ 548 XGBE_MB_SUBCMD_ACTIVE = 0, 549 XGBE_MB_SUBCMD_PASSIVE_1M, 550 XGBE_MB_SUBCMD_PASSIVE_3M, 551 XGBE_MB_SUBCMD_PASSIVE_OTHER, 552 553 /* 1GbE Mode subcommands */ 554 XGBE_MB_SUBCMD_10MBITS = 0, 555 XGBE_MB_SUBCMD_100MBITS, 556 XGBE_MB_SUBCMD_1G_SGMII, 557 XGBE_MB_SUBCMD_1G_KX 558 }; 559 560 struct xgbe_phy { 561 struct ethtool_link_ksettings lks; 562 563 int address; 564 565 int autoneg; 566 int speed; 567 int duplex; 568 569 int link; 570 571 int pause_autoneg; 572 int tx_pause; 573 int rx_pause; 574 }; 575 576 enum xgbe_i2c_cmd { 577 XGBE_I2C_CMD_READ = 0, 578 XGBE_I2C_CMD_WRITE, 579 }; 580 581 struct xgbe_i2c_op { 582 enum xgbe_i2c_cmd cmd; 583 584 unsigned int target; 585 586 void *buf; 587 unsigned int len; 588 }; 589 590 struct xgbe_i2c_op_state { 591 struct xgbe_i2c_op *op; 592 593 unsigned int tx_len; 594 unsigned char *tx_buf; 595 596 unsigned int rx_len; 597 unsigned char *rx_buf; 598 599 unsigned int tx_abort_source; 600 601 int ret; 602 }; 603 604 struct xgbe_i2c { 605 unsigned int started; 606 unsigned int max_speed_mode; 607 unsigned int rx_fifo_size; 608 unsigned int tx_fifo_size; 609 610 struct xgbe_i2c_op_state op_state; 611 }; 612 613 struct xgbe_mmc_stats { 614 /* Tx Stats */ 615 u64 txoctetcount_gb; 616 u64 txframecount_gb; 617 u64 txbroadcastframes_g; 618 u64 txmulticastframes_g; 619 u64 tx64octets_gb; 620 u64 tx65to127octets_gb; 621 u64 tx128to255octets_gb; 622 u64 tx256to511octets_gb; 623 u64 tx512to1023octets_gb; 624 u64 tx1024tomaxoctets_gb; 625 u64 txunicastframes_gb; 626 u64 txmulticastframes_gb; 627 u64 txbroadcastframes_gb; 628 u64 txunderflowerror; 629 u64 txoctetcount_g; 630 u64 txframecount_g; 631 u64 txpauseframes; 632 u64 txvlanframes_g; 633 634 /* Rx Stats */ 635 u64 rxframecount_gb; 636 u64 rxoctetcount_gb; 637 u64 rxoctetcount_g; 638 u64 rxbroadcastframes_g; 639 u64 rxmulticastframes_g; 640 u64 rxcrcerror; 641 u64 rxrunterror; 642 u64 rxjabbererror; 643 u64 rxundersize_g; 644 u64 rxoversize_g; 645 u64 rx64octets_gb; 646 u64 rx65to127octets_gb; 647 u64 rx128to255octets_gb; 648 u64 rx256to511octets_gb; 649 u64 rx512to1023octets_gb; 650 u64 rx1024tomaxoctets_gb; 651 u64 rxunicastframes_g; 652 u64 rxlengtherror; 653 u64 rxoutofrangetype; 654 u64 rxpauseframes; 655 u64 rxfifooverflow; 656 u64 rxvlanframes_gb; 657 u64 rxwatchdogerror; 658 }; 659 660 struct xgbe_ext_stats { 661 u64 tx_tso_packets; 662 u64 rx_split_header_packets; 663 u64 rx_buffer_unavailable; 664 665 u64 txq_packets[XGBE_MAX_DMA_CHANNELS]; 666 u64 txq_bytes[XGBE_MAX_DMA_CHANNELS]; 667 u64 rxq_packets[XGBE_MAX_DMA_CHANNELS]; 668 u64 rxq_bytes[XGBE_MAX_DMA_CHANNELS]; 669 670 u64 tx_vxlan_packets; 671 u64 rx_vxlan_packets; 672 u64 rx_csum_errors; 673 u64 rx_vxlan_csum_errors; 674 }; 675 676 struct xgbe_hw_if { 677 int (*tx_complete)(struct xgbe_ring_desc *); 678 679 int (*set_mac_address)(struct xgbe_prv_data *, const u8 *addr); 680 int (*config_rx_mode)(struct xgbe_prv_data *); 681 682 int (*enable_rx_csum)(struct xgbe_prv_data *); 683 int (*disable_rx_csum)(struct xgbe_prv_data *); 684 685 int (*enable_rx_vlan_stripping)(struct xgbe_prv_data *); 686 int (*disable_rx_vlan_stripping)(struct xgbe_prv_data *); 687 int (*enable_rx_vlan_filtering)(struct xgbe_prv_data *); 688 int (*disable_rx_vlan_filtering)(struct xgbe_prv_data *); 689 int (*update_vlan_hash_table)(struct xgbe_prv_data *); 690 691 int (*read_mmd_regs)(struct xgbe_prv_data *, int, int); 692 void (*write_mmd_regs)(struct xgbe_prv_data *, int, int, int); 693 int (*set_speed)(struct xgbe_prv_data *, int); 694 695 int (*set_ext_mii_mode)(struct xgbe_prv_data *, unsigned int, 696 enum xgbe_mdio_mode); 697 int (*read_ext_mii_regs_c22)(struct xgbe_prv_data *, int, int); 698 int (*write_ext_mii_regs_c22)(struct xgbe_prv_data *, int, int, u16); 699 int (*read_ext_mii_regs_c45)(struct xgbe_prv_data *, int, int, int); 700 int (*write_ext_mii_regs_c45)(struct xgbe_prv_data *, int, int, int, 701 u16); 702 703 int (*set_gpio)(struct xgbe_prv_data *, unsigned int); 704 int (*clr_gpio)(struct xgbe_prv_data *, unsigned int); 705 706 void (*enable_tx)(struct xgbe_prv_data *); 707 void (*disable_tx)(struct xgbe_prv_data *); 708 void (*enable_rx)(struct xgbe_prv_data *); 709 void (*disable_rx)(struct xgbe_prv_data *); 710 711 void (*powerup_tx)(struct xgbe_prv_data *); 712 void (*powerdown_tx)(struct xgbe_prv_data *); 713 void (*powerup_rx)(struct xgbe_prv_data *); 714 void (*powerdown_rx)(struct xgbe_prv_data *); 715 716 int (*init)(struct xgbe_prv_data *); 717 int (*exit)(struct xgbe_prv_data *); 718 719 int (*enable_int)(struct xgbe_channel *, enum xgbe_int); 720 int (*disable_int)(struct xgbe_channel *, enum xgbe_int); 721 void (*dev_xmit)(struct xgbe_channel *); 722 int (*dev_read)(struct xgbe_channel *); 723 void (*tx_desc_init)(struct xgbe_channel *); 724 void (*rx_desc_init)(struct xgbe_channel *); 725 void (*tx_desc_reset)(struct xgbe_ring_data *); 726 void (*rx_desc_reset)(struct xgbe_prv_data *, struct xgbe_ring_data *, 727 unsigned int); 728 int (*is_last_desc)(struct xgbe_ring_desc *); 729 int (*is_context_desc)(struct xgbe_ring_desc *); 730 void (*tx_start_xmit)(struct xgbe_channel *, struct xgbe_ring *); 731 732 /* For FLOW ctrl */ 733 int (*config_tx_flow_control)(struct xgbe_prv_data *); 734 int (*config_rx_flow_control)(struct xgbe_prv_data *); 735 736 /* For RX coalescing */ 737 int (*config_rx_coalesce)(struct xgbe_prv_data *); 738 int (*config_tx_coalesce)(struct xgbe_prv_data *); 739 unsigned int (*usec_to_riwt)(struct xgbe_prv_data *, unsigned int); 740 unsigned int (*riwt_to_usec)(struct xgbe_prv_data *, unsigned int); 741 742 /* For RX and TX threshold config */ 743 int (*config_rx_threshold)(struct xgbe_prv_data *, unsigned int); 744 int (*config_tx_threshold)(struct xgbe_prv_data *, unsigned int); 745 746 /* For RX and TX Store and Forward Mode config */ 747 int (*config_rsf_mode)(struct xgbe_prv_data *, unsigned int); 748 int (*config_tsf_mode)(struct xgbe_prv_data *, unsigned int); 749 750 /* For TX DMA Operate on Second Frame config */ 751 int (*config_osp_mode)(struct xgbe_prv_data *); 752 753 /* For MMC statistics */ 754 void (*rx_mmc_int)(struct xgbe_prv_data *); 755 void (*tx_mmc_int)(struct xgbe_prv_data *); 756 void (*read_mmc_stats)(struct xgbe_prv_data *); 757 758 /* For Data Center Bridging config */ 759 void (*config_tc)(struct xgbe_prv_data *); 760 void (*config_dcb_tc)(struct xgbe_prv_data *); 761 void (*config_dcb_pfc)(struct xgbe_prv_data *); 762 763 /* For Receive Side Scaling */ 764 int (*enable_rss)(struct xgbe_prv_data *); 765 int (*disable_rss)(struct xgbe_prv_data *); 766 int (*set_rss_hash_key)(struct xgbe_prv_data *, const u8 *); 767 int (*set_rss_lookup_table)(struct xgbe_prv_data *, const u32 *); 768 769 /* For ECC */ 770 void (*disable_ecc_ded)(struct xgbe_prv_data *); 771 void (*disable_ecc_sec)(struct xgbe_prv_data *, enum xgbe_ecc_sec); 772 773 /* For VXLAN */ 774 void (*enable_vxlan)(struct xgbe_prv_data *); 775 void (*disable_vxlan)(struct xgbe_prv_data *); 776 void (*set_vxlan_id)(struct xgbe_prv_data *); 777 778 /* For Split Header */ 779 void (*enable_sph)(struct xgbe_prv_data *pdata); 780 void (*disable_sph)(struct xgbe_prv_data *pdata); 781 }; 782 783 /* This structure represents implementation specific routines for an 784 * implementation of a PHY. All routines are required unless noted below. 785 * Optional routines: 786 * an_pre, an_post 787 * kr_training_pre, kr_training_post 788 * module_info, module_eeprom 789 */ 790 struct xgbe_phy_impl_if { 791 /* Perform Setup/teardown actions */ 792 int (*init)(struct xgbe_prv_data *); 793 void (*exit)(struct xgbe_prv_data *); 794 795 /* Perform start/stop specific actions */ 796 int (*reset)(struct xgbe_prv_data *); 797 int (*start)(struct xgbe_prv_data *); 798 void (*stop)(struct xgbe_prv_data *); 799 800 /* Return the link status */ 801 int (*link_status)(struct xgbe_prv_data *, int *); 802 803 /* Indicate if a particular speed is valid */ 804 bool (*valid_speed)(struct xgbe_prv_data *, int); 805 806 /* Check if the specified mode can/should be used */ 807 bool (*use_mode)(struct xgbe_prv_data *, enum xgbe_mode); 808 /* Switch the PHY into various modes */ 809 void (*set_mode)(struct xgbe_prv_data *, enum xgbe_mode); 810 /* Retrieve mode needed for a specific speed */ 811 enum xgbe_mode (*get_mode)(struct xgbe_prv_data *, int); 812 /* Retrieve new/next mode when trying to auto-negotiate */ 813 enum xgbe_mode (*switch_mode)(struct xgbe_prv_data *); 814 /* Retrieve current mode */ 815 enum xgbe_mode (*cur_mode)(struct xgbe_prv_data *); 816 817 /* Retrieve current auto-negotiation mode */ 818 enum xgbe_an_mode (*an_mode)(struct xgbe_prv_data *); 819 820 /* Configure auto-negotiation settings */ 821 int (*an_config)(struct xgbe_prv_data *); 822 823 /* Set/override auto-negotiation advertisement settings */ 824 void (*an_advertising)(struct xgbe_prv_data *, 825 struct ethtool_link_ksettings *); 826 827 /* Process results of auto-negotiation */ 828 enum xgbe_mode (*an_outcome)(struct xgbe_prv_data *); 829 830 /* Pre/Post auto-negotiation support */ 831 void (*an_pre)(struct xgbe_prv_data *); 832 void (*an_post)(struct xgbe_prv_data *); 833 834 /* Pre/Post KR training enablement support */ 835 void (*kr_training_pre)(struct xgbe_prv_data *); 836 void (*kr_training_post)(struct xgbe_prv_data *); 837 838 /* SFP module related info */ 839 int (*module_info)(struct xgbe_prv_data *pdata, 840 struct ethtool_modinfo *modinfo); 841 int (*module_eeprom)(struct xgbe_prv_data *pdata, 842 struct ethtool_eeprom *eeprom, u8 *data); 843 }; 844 845 struct xgbe_phy_if { 846 /* For PHY setup/teardown */ 847 int (*phy_init)(struct xgbe_prv_data *); 848 void (*phy_exit)(struct xgbe_prv_data *); 849 850 /* For PHY support when setting device up/down */ 851 int (*phy_reset)(struct xgbe_prv_data *); 852 int (*phy_start)(struct xgbe_prv_data *); 853 void (*phy_stop)(struct xgbe_prv_data *); 854 855 /* For PHY support while device is up */ 856 void (*phy_status)(struct xgbe_prv_data *); 857 int (*phy_config_aneg)(struct xgbe_prv_data *); 858 859 /* For PHY settings validation */ 860 bool (*phy_valid_speed)(struct xgbe_prv_data *, int); 861 862 /* For single interrupt support */ 863 irqreturn_t (*an_isr)(struct xgbe_prv_data *); 864 865 /* For ethtool PHY support */ 866 int (*module_info)(struct xgbe_prv_data *pdata, 867 struct ethtool_modinfo *modinfo); 868 int (*module_eeprom)(struct xgbe_prv_data *pdata, 869 struct ethtool_eeprom *eeprom, u8 *data); 870 871 /* PHY implementation specific services */ 872 struct xgbe_phy_impl_if phy_impl; 873 }; 874 875 struct xgbe_i2c_if { 876 /* For initial I2C setup */ 877 int (*i2c_init)(struct xgbe_prv_data *); 878 879 /* For I2C support when setting device up/down */ 880 int (*i2c_start)(struct xgbe_prv_data *); 881 void (*i2c_stop)(struct xgbe_prv_data *); 882 883 /* For performing I2C operations */ 884 int (*i2c_xfer)(struct xgbe_prv_data *, struct xgbe_i2c_op *); 885 886 /* For single interrupt support */ 887 irqreturn_t (*i2c_isr)(struct xgbe_prv_data *); 888 }; 889 890 struct xgbe_desc_if { 891 int (*alloc_ring_resources)(struct xgbe_prv_data *); 892 void (*free_ring_resources)(struct xgbe_prv_data *); 893 int (*map_tx_skb)(struct xgbe_channel *, struct sk_buff *); 894 int (*map_rx_buffer)(struct xgbe_prv_data *, struct xgbe_ring *, 895 struct xgbe_ring_data *); 896 void (*unmap_rdata)(struct xgbe_prv_data *, struct xgbe_ring_data *); 897 void (*wrapper_tx_desc_init)(struct xgbe_prv_data *); 898 void (*wrapper_rx_desc_init)(struct xgbe_prv_data *); 899 }; 900 901 /* This structure contains flags that indicate what hardware features 902 * or configurations are present in the device. 903 */ 904 struct xgbe_hw_features { 905 /* HW Version */ 906 unsigned int version; 907 908 /* HW Feature Register0 */ 909 unsigned int gmii; /* 1000 Mbps support */ 910 unsigned int vlhash; /* VLAN Hash Filter */ 911 unsigned int sma; /* SMA(MDIO) Interface */ 912 unsigned int rwk; /* PMT remote wake-up packet */ 913 unsigned int mgk; /* PMT magic packet */ 914 unsigned int mmc; /* RMON module */ 915 unsigned int aoe; /* ARP Offload */ 916 unsigned int ts; /* IEEE 1588-2008 Advanced Timestamp */ 917 unsigned int eee; /* Energy Efficient Ethernet */ 918 unsigned int tx_coe; /* Tx Checksum Offload */ 919 unsigned int rx_coe; /* Rx Checksum Offload */ 920 unsigned int addn_mac; /* Additional MAC Addresses */ 921 unsigned int ts_src; /* Timestamp Source */ 922 unsigned int sa_vlan_ins; /* Source Address or VLAN Insertion */ 923 unsigned int vxn; /* VXLAN/NVGRE */ 924 925 /* HW Feature Register1 */ 926 unsigned int rx_fifo_size; /* MTL Receive FIFO Size */ 927 unsigned int tx_fifo_size; /* MTL Transmit FIFO Size */ 928 unsigned int adv_ts_hi; /* Advance Timestamping High Word */ 929 unsigned int dma_width; /* DMA width */ 930 unsigned int dcb; /* DCB Feature */ 931 unsigned int sph; /* Split Header Feature */ 932 unsigned int tso; /* TCP Segmentation Offload */ 933 unsigned int dma_debug; /* DMA Debug Registers */ 934 unsigned int rss; /* Receive Side Scaling */ 935 unsigned int tc_cnt; /* Number of Traffic Classes */ 936 unsigned int hash_table_size; /* Hash Table Size */ 937 unsigned int l3l4_filter_num; /* Number of L3-L4 Filters */ 938 939 /* HW Feature Register2 */ 940 unsigned int rx_q_cnt; /* Number of MTL Receive Queues */ 941 unsigned int tx_q_cnt; /* Number of MTL Transmit Queues */ 942 unsigned int rx_ch_cnt; /* Number of DMA Receive Channels */ 943 unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */ 944 unsigned int pps_out_num; /* Number of PPS outputs */ 945 unsigned int aux_snap_num; /* Number of Aux snapshot inputs */ 946 }; 947 948 struct xgbe_version_data { 949 void (*init_function_ptrs_phy_impl)(struct xgbe_phy_if *); 950 enum xgbe_xpcs_access xpcs_access; 951 unsigned int mmc_64bit; 952 unsigned int tx_max_fifo_size; 953 unsigned int rx_max_fifo_size; 954 unsigned int tx_tstamp_workaround; 955 unsigned int tstamp_ptp_clock_freq; 956 unsigned int ecc_support; 957 unsigned int i2c_support; 958 unsigned int irq_reissue_support; 959 unsigned int tx_desc_prefetch; 960 unsigned int rx_desc_prefetch; 961 unsigned int an_cdr_workaround; 962 unsigned int enable_rrc; 963 }; 964 965 struct xgbe_prv_data { 966 struct net_device *netdev; 967 struct pci_dev *pcidev; 968 struct platform_device *platdev; 969 struct acpi_device *adev; 970 struct device *dev; 971 struct platform_device *phy_platdev; 972 struct device *phy_dev; 973 unsigned int smn_base; 974 975 /* Version related data */ 976 struct xgbe_version_data *vdata; 977 978 /* ACPI or DT flag */ 979 unsigned int use_acpi; 980 981 /* XGMAC/XPCS related mmio registers */ 982 void __iomem *xgmac_regs; /* XGMAC CSRs */ 983 void __iomem *xpcs_regs; /* XPCS MMD registers */ 984 void __iomem *rxtx_regs; /* SerDes Rx/Tx CSRs */ 985 void __iomem *sir0_regs; /* SerDes integration registers (1/2) */ 986 void __iomem *sir1_regs; /* SerDes integration registers (2/2) */ 987 void __iomem *xprop_regs; /* XGBE property registers */ 988 void __iomem *xi2c_regs; /* XGBE I2C CSRs */ 989 990 /* Port property registers */ 991 unsigned int pp0; 992 unsigned int pp1; 993 unsigned int pp2; 994 unsigned int pp3; 995 unsigned int pp4; 996 997 /* Overall device lock */ 998 spinlock_t lock; 999 1000 /* XPCS indirect addressing lock */ 1001 spinlock_t xpcs_lock; 1002 unsigned int xpcs_window_def_reg; 1003 unsigned int xpcs_window_sel_reg; 1004 unsigned int xpcs_window; 1005 unsigned int xpcs_window_size; 1006 unsigned int xpcs_window_mask; 1007 1008 /* RSS addressing mutex */ 1009 struct mutex rss_mutex; 1010 1011 /* Flags representing xgbe_state */ 1012 unsigned long dev_state; 1013 1014 /* ECC support */ 1015 unsigned long tx_sec_period; 1016 unsigned long tx_ded_period; 1017 unsigned long rx_sec_period; 1018 unsigned long rx_ded_period; 1019 unsigned long desc_sec_period; 1020 unsigned long desc_ded_period; 1021 1022 unsigned int tx_sec_count; 1023 unsigned int tx_ded_count; 1024 unsigned int rx_sec_count; 1025 unsigned int rx_ded_count; 1026 unsigned int desc_ded_count; 1027 unsigned int desc_sec_count; 1028 1029 int dev_irq; 1030 int ecc_irq; 1031 int i2c_irq; 1032 int channel_irq[XGBE_MAX_DMA_CHANNELS]; 1033 1034 unsigned int per_channel_irq; 1035 unsigned int irq_count; 1036 unsigned int channel_irq_count; 1037 unsigned int channel_irq_mode; 1038 1039 char ecc_name[IFNAMSIZ + 32]; 1040 1041 struct xgbe_hw_if hw_if; 1042 struct xgbe_phy_if phy_if; 1043 struct xgbe_desc_if desc_if; 1044 struct xgbe_i2c_if i2c_if; 1045 1046 /* AXI DMA settings */ 1047 unsigned int coherent; 1048 unsigned int arcr; 1049 unsigned int awcr; 1050 unsigned int awarcr; 1051 1052 /* Service routine support */ 1053 struct workqueue_struct *dev_workqueue; 1054 struct work_struct service_work; 1055 struct timer_list service_timer; 1056 1057 /* Rings for Tx/Rx on a DMA channel */ 1058 struct xgbe_channel *channel[XGBE_MAX_DMA_CHANNELS]; 1059 unsigned int tx_max_channel_count; 1060 unsigned int rx_max_channel_count; 1061 unsigned int channel_count; 1062 unsigned int tx_ring_count; 1063 unsigned int tx_desc_count; 1064 unsigned int rx_ring_count; 1065 unsigned int rx_desc_count; 1066 1067 unsigned int new_tx_ring_count; 1068 unsigned int new_rx_ring_count; 1069 1070 unsigned int tx_max_q_count; 1071 unsigned int rx_max_q_count; 1072 unsigned int tx_q_count; 1073 unsigned int rx_q_count; 1074 1075 /* Tx/Rx common settings */ 1076 unsigned int blen; 1077 unsigned int pbl; 1078 unsigned int aal; 1079 unsigned int rd_osr_limit; 1080 unsigned int wr_osr_limit; 1081 1082 /* Tx settings */ 1083 unsigned int tx_sf_mode; 1084 unsigned int tx_threshold; 1085 unsigned int tx_osp_mode; 1086 unsigned int tx_max_fifo_size; 1087 1088 /* Rx settings */ 1089 unsigned int rx_sf_mode; 1090 unsigned int rx_threshold; 1091 unsigned int rx_max_fifo_size; 1092 1093 /* Tx coalescing settings */ 1094 unsigned int tx_usecs; 1095 unsigned int tx_frames; 1096 1097 /* Rx coalescing settings */ 1098 unsigned int rx_riwt; 1099 unsigned int rx_usecs; 1100 unsigned int rx_frames; 1101 1102 /* Current Rx buffer size */ 1103 unsigned int rx_buf_size; 1104 1105 /* Flow control settings */ 1106 unsigned int pause_autoneg; 1107 unsigned int tx_pause; 1108 unsigned int rx_pause; 1109 unsigned int rx_rfa[XGBE_MAX_QUEUES]; 1110 unsigned int rx_rfd[XGBE_MAX_QUEUES]; 1111 1112 /* Receive Side Scaling settings */ 1113 u8 rss_key[XGBE_RSS_HASH_KEY_SIZE]; 1114 u32 rss_table[XGBE_RSS_MAX_TABLE_SIZE]; 1115 u32 rss_options; 1116 1117 /* VXLAN settings */ 1118 u16 vxlan_port; 1119 1120 /* Netdev related settings */ 1121 unsigned char mac_addr[ETH_ALEN]; 1122 netdev_features_t netdev_features; 1123 struct napi_struct napi; 1124 struct xgbe_mmc_stats mmc_stats; 1125 struct xgbe_ext_stats ext_stats; 1126 1127 /* Filtering support */ 1128 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 1129 1130 /* Device clocks */ 1131 struct clk *sysclk; 1132 unsigned long sysclk_rate; 1133 struct clk *ptpclk; 1134 unsigned long ptpclk_rate; 1135 1136 /* Timestamp support */ 1137 spinlock_t tstamp_lock; 1138 struct ptp_clock_info ptp_clock_info; 1139 struct ptp_clock *ptp_clock; 1140 struct hwtstamp_config tstamp_config; 1141 unsigned int tstamp_addend; 1142 struct work_struct tx_tstamp_work; 1143 struct sk_buff *tx_tstamp_skb; 1144 u64 tx_tstamp; 1145 1146 /* DCB support */ 1147 struct ieee_ets *ets; 1148 struct ieee_pfc *pfc; 1149 unsigned int q2tc_map[XGBE_MAX_QUEUES]; 1150 unsigned int prio2q_map[IEEE_8021QAZ_MAX_TCS]; 1151 unsigned int pfcq[XGBE_MAX_QUEUES]; 1152 unsigned int pfc_rfa; 1153 u8 num_tcs; 1154 1155 /* Hardware features of the device */ 1156 struct xgbe_hw_features hw_feat; 1157 1158 /* Device work structures */ 1159 struct work_struct restart_work; 1160 struct work_struct stopdev_work; 1161 1162 /* Keeps track of power mode */ 1163 unsigned int power_down; 1164 1165 /* Network interface message level setting */ 1166 u32 msg_enable; 1167 1168 /* Current PHY settings */ 1169 phy_interface_t phy_mode; 1170 int phy_link; 1171 int phy_speed; 1172 1173 /* MDIO/PHY related settings */ 1174 unsigned int phy_started; 1175 void *phy_data; 1176 struct xgbe_phy phy; 1177 int mdio_mmd; 1178 unsigned long link_check; 1179 struct completion mdio_complete; 1180 1181 unsigned int kr_redrv; 1182 1183 char an_name[IFNAMSIZ + 32]; 1184 struct workqueue_struct *an_workqueue; 1185 1186 int an_irq; 1187 struct work_struct an_irq_work; 1188 1189 /* Auto-negotiation state machine support */ 1190 unsigned int an_int; 1191 unsigned int an_status; 1192 struct mutex an_mutex; 1193 enum xgbe_an an_result; 1194 enum xgbe_an an_state; 1195 enum xgbe_rx kr_state; 1196 enum xgbe_rx kx_state; 1197 struct work_struct an_work; 1198 unsigned int an_again; 1199 unsigned int an_supported; 1200 unsigned int parallel_detect; 1201 unsigned int fec_ability; 1202 unsigned long an_start; 1203 unsigned long kr_start_time; 1204 enum xgbe_an_mode an_mode; 1205 1206 /* I2C support */ 1207 struct xgbe_i2c i2c; 1208 struct mutex i2c_mutex; 1209 struct completion i2c_complete; 1210 char i2c_name[IFNAMSIZ + 32]; 1211 1212 unsigned int lpm_ctrl; /* CTRL1 for resume */ 1213 1214 unsigned int isr_as_bh_work; 1215 struct work_struct dev_bh_work; 1216 struct work_struct ecc_bh_work; 1217 struct work_struct i2c_bh_work; 1218 struct work_struct an_bh_work; 1219 1220 struct dentry *xgbe_debugfs; 1221 1222 unsigned int debugfs_xgmac_reg; 1223 1224 unsigned int debugfs_xpcs_mmd; 1225 unsigned int debugfs_xpcs_reg; 1226 1227 unsigned int debugfs_xprop_reg; 1228 1229 unsigned int debugfs_xi2c_reg; 1230 1231 bool debugfs_an_cdr_workaround; 1232 bool debugfs_an_cdr_track_early; 1233 bool en_rx_adap; 1234 int rx_adapt_retries; 1235 bool rx_adapt_done; 1236 bool mode_set; 1237 }; 1238 1239 /* Function prototypes*/ 1240 struct xgbe_prv_data *xgbe_alloc_pdata(struct device *); 1241 void xgbe_free_pdata(struct xgbe_prv_data *); 1242 void xgbe_set_counts(struct xgbe_prv_data *); 1243 int xgbe_config_netdev(struct xgbe_prv_data *); 1244 void xgbe_deconfig_netdev(struct xgbe_prv_data *); 1245 1246 int xgbe_platform_init(void); 1247 void xgbe_platform_exit(void); 1248 #ifdef CONFIG_PCI 1249 int xgbe_pci_init(void); 1250 void xgbe_pci_exit(void); 1251 #else 1252 static inline int xgbe_pci_init(void) { return 0; } 1253 static inline void xgbe_pci_exit(void) { } 1254 #endif 1255 1256 void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *); 1257 void xgbe_init_function_ptrs_phy(struct xgbe_phy_if *); 1258 void xgbe_init_function_ptrs_phy_v1(struct xgbe_phy_if *); 1259 void xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *); 1260 void xgbe_init_function_ptrs_desc(struct xgbe_desc_if *); 1261 void xgbe_init_function_ptrs_i2c(struct xgbe_i2c_if *); 1262 const struct net_device_ops *xgbe_get_netdev_ops(void); 1263 const struct ethtool_ops *xgbe_get_ethtool_ops(void); 1264 const struct udp_tunnel_nic_info *xgbe_get_udp_tunnel_info(void); 1265 1266 #ifdef CONFIG_AMD_XGBE_DCB 1267 const struct dcbnl_rtnl_ops *xgbe_get_dcbnl_ops(void); 1268 #endif 1269 1270 void xgbe_ptp_register(struct xgbe_prv_data *); 1271 void xgbe_ptp_unregister(struct xgbe_prv_data *); 1272 void xgbe_dump_tx_desc(struct xgbe_prv_data *, struct xgbe_ring *, 1273 unsigned int, unsigned int, unsigned int); 1274 void xgbe_dump_rx_desc(struct xgbe_prv_data *, struct xgbe_ring *, 1275 unsigned int); 1276 void xgbe_print_pkt(struct net_device *, struct sk_buff *, bool); 1277 void xgbe_get_all_hw_features(struct xgbe_prv_data *); 1278 int xgbe_powerup(struct net_device *, unsigned int); 1279 int xgbe_powerdown(struct net_device *, unsigned int); 1280 void xgbe_init_rx_coalesce(struct xgbe_prv_data *); 1281 void xgbe_init_tx_coalesce(struct xgbe_prv_data *); 1282 void xgbe_restart_dev(struct xgbe_prv_data *pdata); 1283 void xgbe_full_restart_dev(struct xgbe_prv_data *pdata); 1284 1285 /* For Timestamp config */ 1286 void xgbe_config_tstamp(struct xgbe_prv_data *pdata, unsigned int mac_tscr); 1287 u64 xgbe_get_tstamp_time(struct xgbe_prv_data *pdata); 1288 u64 xgbe_get_tx_tstamp(struct xgbe_prv_data *pdata); 1289 void xgbe_get_rx_tstamp(struct xgbe_packet_data *packet, 1290 struct xgbe_ring_desc *rdesc); 1291 void xgbe_get_rx_tstamp(struct xgbe_packet_data *packet, 1292 struct xgbe_ring_desc *rdesc); 1293 void xgbe_update_tstamp_addend(struct xgbe_prv_data *pdata, 1294 unsigned int addend); 1295 void xgbe_set_tstamp_time(struct xgbe_prv_data *pdata, unsigned int sec, 1296 unsigned int nsec); 1297 void xgbe_tx_tstamp(struct work_struct *work); 1298 int xgbe_get_hwtstamp_settings(struct xgbe_prv_data *pdata, 1299 struct ifreq *ifreq); 1300 int xgbe_set_hwtstamp_settings(struct xgbe_prv_data *pdata, 1301 struct ifreq *ifreq); 1302 void xgbe_prep_tx_tstamp(struct xgbe_prv_data *pdata, 1303 struct sk_buff *skb, 1304 struct xgbe_packet_data *packet); 1305 int xgbe_init_ptp(struct xgbe_prv_data *pdata); 1306 void xgbe_update_tstamp_time(struct xgbe_prv_data *pdata, unsigned int sec, 1307 unsigned int nsec); 1308 #ifdef CONFIG_DEBUG_FS 1309 void xgbe_debugfs_init(struct xgbe_prv_data *); 1310 void xgbe_debugfs_exit(struct xgbe_prv_data *); 1311 void xgbe_debugfs_rename(struct xgbe_prv_data *pdata); 1312 #else 1313 static inline void xgbe_debugfs_init(struct xgbe_prv_data *pdata) {} 1314 static inline void xgbe_debugfs_exit(struct xgbe_prv_data *pdata) {} 1315 static inline void xgbe_debugfs_rename(struct xgbe_prv_data *pdata) {} 1316 #endif /* CONFIG_DEBUG_FS */ 1317 1318 /* NOTE: Uncomment for function trace log messages in KERNEL LOG */ 1319 #if 0 1320 #define YDEBUG 1321 #define YDEBUG_MDIO 1322 #endif 1323 1324 /* For debug prints */ 1325 #ifdef YDEBUG 1326 #define DBGPR(x...) pr_alert(x) 1327 #else 1328 #define DBGPR(x...) do { } while (0) 1329 #endif 1330 1331 #ifdef YDEBUG_MDIO 1332 #define DBGPR_MDIO(x...) pr_alert(x) 1333 #else 1334 #define DBGPR_MDIO(x...) do { } while (0) 1335 #endif 1336 1337 #endif 1338