1 /* 2 * AMD 10Gb Ethernet driver 3 * 4 * This file is available to you under your choice of the following two 5 * licenses: 6 * 7 * License 1: GPLv2 8 * 9 * Copyright (c) 2014 Advanced Micro Devices, Inc. 10 * 11 * This file is free software; you may copy, redistribute and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation, either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program. If not, see <http://www.gnu.org/licenses/>. 23 * 24 * This file incorporates work covered by the following copyright and 25 * permission notice: 26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 28 * Inc. unless otherwise expressly agreed to in writing between Synopsys 29 * and you. 30 * 31 * The Software IS NOT an item of Licensed Software or Licensed Product 32 * under any End User Software License Agreement or Agreement for Licensed 33 * Product with Synopsys or any supplement thereto. Permission is hereby 34 * granted, free of charge, to any person obtaining a copy of this software 35 * annotated with this license and the Software, to deal in the Software 36 * without restriction, including without limitation the rights to use, 37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 38 * of the Software, and to permit persons to whom the Software is furnished 39 * to do so, subject to the following conditions: 40 * 41 * The above copyright notice and this permission notice shall be included 42 * in all copies or substantial portions of the Software. 43 * 44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 54 * THE POSSIBILITY OF SUCH DAMAGE. 55 * 56 * 57 * License 2: Modified BSD 58 * 59 * Copyright (c) 2014 Advanced Micro Devices, Inc. 60 * All rights reserved. 61 * 62 * Redistribution and use in source and binary forms, with or without 63 * modification, are permitted provided that the following conditions are met: 64 * * Redistributions of source code must retain the above copyright 65 * notice, this list of conditions and the following disclaimer. 66 * * Redistributions in binary form must reproduce the above copyright 67 * notice, this list of conditions and the following disclaimer in the 68 * documentation and/or other materials provided with the distribution. 69 * * Neither the name of Advanced Micro Devices, Inc. nor the 70 * names of its contributors may be used to endorse or promote products 71 * derived from this software without specific prior written permission. 72 * 73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY 77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 83 * 84 * This file incorporates work covered by the following copyright and 85 * permission notice: 86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 88 * Inc. unless otherwise expressly agreed to in writing between Synopsys 89 * and you. 90 * 91 * The Software IS NOT an item of Licensed Software or Licensed Product 92 * under any End User Software License Agreement or Agreement for Licensed 93 * Product with Synopsys or any supplement thereto. Permission is hereby 94 * granted, free of charge, to any person obtaining a copy of this software 95 * annotated with this license and the Software, to deal in the Software 96 * without restriction, including without limitation the rights to use, 97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 98 * of the Software, and to permit persons to whom the Software is furnished 99 * to do so, subject to the following conditions: 100 * 101 * The above copyright notice and this permission notice shall be included 102 * in all copies or substantial portions of the Software. 103 * 104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 114 * THE POSSIBILITY OF SUCH DAMAGE. 115 */ 116 117 #ifndef __XGBE_H__ 118 #define __XGBE_H__ 119 120 #include <linux/dma-mapping.h> 121 #include <linux/netdevice.h> 122 #include <linux/workqueue.h> 123 #include <linux/phy.h> 124 #include <linux/if_vlan.h> 125 #include <linux/bitops.h> 126 #include <linux/ptp_clock_kernel.h> 127 #include <linux/clocksource.h> 128 #include <linux/net_tstamp.h> 129 #include <net/dcbnl.h> 130 131 132 #define XGBE_DRV_NAME "amd-xgbe" 133 #define XGBE_DRV_VERSION "1.0.0-a" 134 #define XGBE_DRV_DESC "AMD 10 Gigabit Ethernet Driver" 135 136 /* Descriptor related defines */ 137 #define XGBE_TX_DESC_CNT 512 138 #define XGBE_TX_DESC_MIN_FREE (XGBE_TX_DESC_CNT >> 3) 139 #define XGBE_TX_DESC_MAX_PROC (XGBE_TX_DESC_CNT >> 1) 140 #define XGBE_RX_DESC_CNT 512 141 142 #define XGBE_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1)) 143 144 #define XGBE_RX_MIN_BUF_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN) 145 #define XGBE_RX_BUF_ALIGN 64 146 147 #define XGBE_MAX_DMA_CHANNELS 16 148 #define XGBE_MAX_QUEUES 16 149 150 /* DMA cache settings - Outer sharable, write-back, write-allocate */ 151 #define XGBE_DMA_OS_AXDOMAIN 0x2 152 #define XGBE_DMA_OS_ARCACHE 0xb 153 #define XGBE_DMA_OS_AWCACHE 0xf 154 155 /* DMA cache settings - System, no caches used */ 156 #define XGBE_DMA_SYS_AXDOMAIN 0x3 157 #define XGBE_DMA_SYS_ARCACHE 0x0 158 #define XGBE_DMA_SYS_AWCACHE 0x0 159 160 #define XGBE_DMA_INTERRUPT_MASK 0x31c7 161 162 #define XGMAC_MIN_PACKET 60 163 #define XGMAC_STD_PACKET_MTU 1500 164 #define XGMAC_MAX_STD_PACKET 1518 165 #define XGMAC_JUMBO_PACKET_MTU 9000 166 #define XGMAC_MAX_JUMBO_PACKET 9018 167 168 /* MDIO bus phy name */ 169 #define XGBE_PHY_NAME "amd_xgbe_phy" 170 #define XGBE_PRTAD 0 171 172 /* Device-tree clock names */ 173 #define XGBE_DMA_CLOCK "dma_clk" 174 #define XGBE_PTP_CLOCK "ptp_clk" 175 176 /* Timestamp support - values based on 50MHz PTP clock 177 * 50MHz => 20 nsec 178 */ 179 #define XGBE_TSTAMP_SSINC 20 180 #define XGBE_TSTAMP_SNSINC 0 181 182 /* Driver PMT macros */ 183 #define XGMAC_DRIVER_CONTEXT 1 184 #define XGMAC_IOCTL_CONTEXT 2 185 186 #define XGBE_FIFO_MAX 81920 187 #define XGBE_FIFO_SIZE_B(x) (x) 188 #define XGBE_FIFO_SIZE_KB(x) (x * 1024) 189 190 #define XGBE_TC_MIN_QUANTUM 10 191 192 /* Helper macro for descriptor handling 193 * Always use XGBE_GET_DESC_DATA to access the descriptor data 194 * since the index is free-running and needs to be and-ed 195 * with the descriptor count value of the ring to index to 196 * the proper descriptor data. 197 */ 198 #define XGBE_GET_DESC_DATA(_ring, _idx) \ 199 ((_ring)->rdata + \ 200 ((_idx) & ((_ring)->rdesc_count - 1))) 201 202 203 /* Default coalescing parameters */ 204 #define XGMAC_INIT_DMA_TX_USECS 50 205 #define XGMAC_INIT_DMA_TX_FRAMES 25 206 207 #define XGMAC_MAX_DMA_RIWT 0xff 208 #define XGMAC_INIT_DMA_RX_USECS 30 209 #define XGMAC_INIT_DMA_RX_FRAMES 25 210 211 /* Flow control queue count */ 212 #define XGMAC_MAX_FLOW_CONTROL_QUEUES 8 213 214 /* Maximum MAC address hash table size (256 bits = 8 bytes) */ 215 #define XGBE_MAC_HASH_TABLE_SIZE 8 216 217 struct xgbe_prv_data; 218 219 struct xgbe_packet_data { 220 unsigned int attributes; 221 222 unsigned int errors; 223 224 unsigned int rdesc_count; 225 unsigned int length; 226 227 unsigned int header_len; 228 unsigned int tcp_header_len; 229 unsigned int tcp_payload_len; 230 unsigned short mss; 231 232 unsigned short vlan_ctag; 233 234 u64 rx_tstamp; 235 }; 236 237 /* Common Rx and Tx descriptor mapping */ 238 struct xgbe_ring_desc { 239 unsigned int desc0; 240 unsigned int desc1; 241 unsigned int desc2; 242 unsigned int desc3; 243 }; 244 245 /* Structure used to hold information related to the descriptor 246 * and the packet associated with the descriptor (always use 247 * use the XGBE_GET_DESC_DATA macro to access this data from the ring) 248 */ 249 struct xgbe_ring_data { 250 struct xgbe_ring_desc *rdesc; /* Virtual address of descriptor */ 251 dma_addr_t rdesc_dma; /* DMA address of descriptor */ 252 253 struct sk_buff *skb; /* Virtual address of SKB */ 254 dma_addr_t skb_dma; /* DMA address of SKB data */ 255 unsigned int skb_dma_len; /* Length of SKB DMA area */ 256 unsigned int tso_header; /* TSO header indicator */ 257 258 unsigned short len; /* Length of received Rx packet */ 259 260 unsigned int interrupt; /* Interrupt indicator */ 261 262 unsigned int mapped_as_page; 263 264 /* Incomplete receive save location. If the budget is exhausted 265 * or the last descriptor (last normal descriptor or a following 266 * context descriptor) has not been DMA'd yet the current state 267 * of the receive processing needs to be saved. 268 */ 269 unsigned int state_saved; 270 struct { 271 unsigned int incomplete; 272 unsigned int context_next; 273 struct sk_buff *skb; 274 unsigned int len; 275 unsigned int error; 276 } state; 277 }; 278 279 struct xgbe_ring { 280 /* Ring lock - used just for TX rings at the moment */ 281 spinlock_t lock; 282 283 /* Per packet related information */ 284 struct xgbe_packet_data packet_data; 285 286 /* Virtual/DMA addresses and count of allocated descriptor memory */ 287 struct xgbe_ring_desc *rdesc; 288 dma_addr_t rdesc_dma; 289 unsigned int rdesc_count; 290 291 /* Array of descriptor data corresponding the descriptor memory 292 * (always use the XGBE_GET_DESC_DATA macro to access this data) 293 */ 294 struct xgbe_ring_data *rdata; 295 296 /* Ring index values 297 * cur - Tx: index of descriptor to be used for current transfer 298 * Rx: index of descriptor to check for packet availability 299 * dirty - Tx: index of descriptor to check for transfer complete 300 * Rx: count of descriptors in which a packet has been received 301 * (used with skb_realloc_index to refresh the ring) 302 */ 303 unsigned int cur; 304 unsigned int dirty; 305 306 /* Coalesce frame count used for interrupt bit setting */ 307 unsigned int coalesce_count; 308 309 union { 310 struct { 311 unsigned int queue_stopped; 312 unsigned short cur_mss; 313 unsigned short cur_vlan_ctag; 314 } tx; 315 316 struct { 317 unsigned int realloc_index; 318 unsigned int realloc_threshold; 319 } rx; 320 }; 321 } ____cacheline_aligned; 322 323 /* Structure used to describe the descriptor rings associated with 324 * a DMA channel. 325 */ 326 struct xgbe_channel { 327 char name[16]; 328 329 /* Address of private data area for device */ 330 struct xgbe_prv_data *pdata; 331 332 /* Queue index and base address of queue's DMA registers */ 333 unsigned int queue_index; 334 void __iomem *dma_regs; 335 336 unsigned int saved_ier; 337 338 unsigned int tx_timer_active; 339 struct hrtimer tx_timer; 340 341 struct xgbe_ring *tx_ring; 342 struct xgbe_ring *rx_ring; 343 } ____cacheline_aligned; 344 345 enum xgbe_int { 346 XGMAC_INT_DMA_CH_SR_TI, 347 XGMAC_INT_DMA_CH_SR_TPS, 348 XGMAC_INT_DMA_CH_SR_TBU, 349 XGMAC_INT_DMA_CH_SR_RI, 350 XGMAC_INT_DMA_CH_SR_RBU, 351 XGMAC_INT_DMA_CH_SR_RPS, 352 XGMAC_INT_DMA_CH_SR_TI_RI, 353 XGMAC_INT_DMA_CH_SR_FBE, 354 XGMAC_INT_DMA_ALL, 355 }; 356 357 enum xgbe_int_state { 358 XGMAC_INT_STATE_SAVE, 359 XGMAC_INT_STATE_RESTORE, 360 }; 361 362 enum xgbe_mtl_fifo_size { 363 XGMAC_MTL_FIFO_SIZE_256 = 0x00, 364 XGMAC_MTL_FIFO_SIZE_512 = 0x01, 365 XGMAC_MTL_FIFO_SIZE_1K = 0x03, 366 XGMAC_MTL_FIFO_SIZE_2K = 0x07, 367 XGMAC_MTL_FIFO_SIZE_4K = 0x0f, 368 XGMAC_MTL_FIFO_SIZE_8K = 0x1f, 369 XGMAC_MTL_FIFO_SIZE_16K = 0x3f, 370 XGMAC_MTL_FIFO_SIZE_32K = 0x7f, 371 XGMAC_MTL_FIFO_SIZE_64K = 0xff, 372 XGMAC_MTL_FIFO_SIZE_128K = 0x1ff, 373 XGMAC_MTL_FIFO_SIZE_256K = 0x3ff, 374 }; 375 376 struct xgbe_mmc_stats { 377 /* Tx Stats */ 378 u64 txoctetcount_gb; 379 u64 txframecount_gb; 380 u64 txbroadcastframes_g; 381 u64 txmulticastframes_g; 382 u64 tx64octets_gb; 383 u64 tx65to127octets_gb; 384 u64 tx128to255octets_gb; 385 u64 tx256to511octets_gb; 386 u64 tx512to1023octets_gb; 387 u64 tx1024tomaxoctets_gb; 388 u64 txunicastframes_gb; 389 u64 txmulticastframes_gb; 390 u64 txbroadcastframes_gb; 391 u64 txunderflowerror; 392 u64 txoctetcount_g; 393 u64 txframecount_g; 394 u64 txpauseframes; 395 u64 txvlanframes_g; 396 397 /* Rx Stats */ 398 u64 rxframecount_gb; 399 u64 rxoctetcount_gb; 400 u64 rxoctetcount_g; 401 u64 rxbroadcastframes_g; 402 u64 rxmulticastframes_g; 403 u64 rxcrcerror; 404 u64 rxrunterror; 405 u64 rxjabbererror; 406 u64 rxundersize_g; 407 u64 rxoversize_g; 408 u64 rx64octets_gb; 409 u64 rx65to127octets_gb; 410 u64 rx128to255octets_gb; 411 u64 rx256to511octets_gb; 412 u64 rx512to1023octets_gb; 413 u64 rx1024tomaxoctets_gb; 414 u64 rxunicastframes_g; 415 u64 rxlengtherror; 416 u64 rxoutofrangetype; 417 u64 rxpauseframes; 418 u64 rxfifooverflow; 419 u64 rxvlanframes_gb; 420 u64 rxwatchdogerror; 421 }; 422 423 struct xgbe_hw_if { 424 int (*tx_complete)(struct xgbe_ring_desc *); 425 426 int (*set_promiscuous_mode)(struct xgbe_prv_data *, unsigned int); 427 int (*set_all_multicast_mode)(struct xgbe_prv_data *, unsigned int); 428 int (*add_mac_addresses)(struct xgbe_prv_data *); 429 int (*set_mac_address)(struct xgbe_prv_data *, u8 *addr); 430 431 int (*enable_rx_csum)(struct xgbe_prv_data *); 432 int (*disable_rx_csum)(struct xgbe_prv_data *); 433 434 int (*enable_rx_vlan_stripping)(struct xgbe_prv_data *); 435 int (*disable_rx_vlan_stripping)(struct xgbe_prv_data *); 436 int (*enable_rx_vlan_filtering)(struct xgbe_prv_data *); 437 int (*disable_rx_vlan_filtering)(struct xgbe_prv_data *); 438 int (*update_vlan_hash_table)(struct xgbe_prv_data *); 439 440 int (*read_mmd_regs)(struct xgbe_prv_data *, int, int); 441 void (*write_mmd_regs)(struct xgbe_prv_data *, int, int, int); 442 int (*set_gmii_speed)(struct xgbe_prv_data *); 443 int (*set_gmii_2500_speed)(struct xgbe_prv_data *); 444 int (*set_xgmii_speed)(struct xgbe_prv_data *); 445 446 void (*enable_tx)(struct xgbe_prv_data *); 447 void (*disable_tx)(struct xgbe_prv_data *); 448 void (*enable_rx)(struct xgbe_prv_data *); 449 void (*disable_rx)(struct xgbe_prv_data *); 450 451 void (*powerup_tx)(struct xgbe_prv_data *); 452 void (*powerdown_tx)(struct xgbe_prv_data *); 453 void (*powerup_rx)(struct xgbe_prv_data *); 454 void (*powerdown_rx)(struct xgbe_prv_data *); 455 456 int (*init)(struct xgbe_prv_data *); 457 int (*exit)(struct xgbe_prv_data *); 458 459 int (*enable_int)(struct xgbe_channel *, enum xgbe_int); 460 int (*disable_int)(struct xgbe_channel *, enum xgbe_int); 461 void (*pre_xmit)(struct xgbe_channel *); 462 int (*dev_read)(struct xgbe_channel *); 463 void (*tx_desc_init)(struct xgbe_channel *); 464 void (*rx_desc_init)(struct xgbe_channel *); 465 void (*rx_desc_reset)(struct xgbe_ring_data *); 466 void (*tx_desc_reset)(struct xgbe_ring_data *); 467 int (*is_last_desc)(struct xgbe_ring_desc *); 468 int (*is_context_desc)(struct xgbe_ring_desc *); 469 470 /* For FLOW ctrl */ 471 int (*config_tx_flow_control)(struct xgbe_prv_data *); 472 int (*config_rx_flow_control)(struct xgbe_prv_data *); 473 474 /* For RX coalescing */ 475 int (*config_rx_coalesce)(struct xgbe_prv_data *); 476 int (*config_tx_coalesce)(struct xgbe_prv_data *); 477 unsigned int (*usec_to_riwt)(struct xgbe_prv_data *, unsigned int); 478 unsigned int (*riwt_to_usec)(struct xgbe_prv_data *, unsigned int); 479 480 /* For RX and TX threshold config */ 481 int (*config_rx_threshold)(struct xgbe_prv_data *, unsigned int); 482 int (*config_tx_threshold)(struct xgbe_prv_data *, unsigned int); 483 484 /* For RX and TX Store and Forward Mode config */ 485 int (*config_rsf_mode)(struct xgbe_prv_data *, unsigned int); 486 int (*config_tsf_mode)(struct xgbe_prv_data *, unsigned int); 487 488 /* For TX DMA Operate on Second Frame config */ 489 int (*config_osp_mode)(struct xgbe_prv_data *); 490 491 /* For RX and TX PBL config */ 492 int (*config_rx_pbl_val)(struct xgbe_prv_data *); 493 int (*get_rx_pbl_val)(struct xgbe_prv_data *); 494 int (*config_tx_pbl_val)(struct xgbe_prv_data *); 495 int (*get_tx_pbl_val)(struct xgbe_prv_data *); 496 int (*config_pblx8)(struct xgbe_prv_data *); 497 498 /* For MMC statistics */ 499 void (*rx_mmc_int)(struct xgbe_prv_data *); 500 void (*tx_mmc_int)(struct xgbe_prv_data *); 501 void (*read_mmc_stats)(struct xgbe_prv_data *); 502 503 /* For Timestamp config */ 504 int (*config_tstamp)(struct xgbe_prv_data *, unsigned int); 505 void (*update_tstamp_addend)(struct xgbe_prv_data *, unsigned int); 506 void (*set_tstamp_time)(struct xgbe_prv_data *, unsigned int sec, 507 unsigned int nsec); 508 u64 (*get_tstamp_time)(struct xgbe_prv_data *); 509 u64 (*get_tx_tstamp)(struct xgbe_prv_data *); 510 511 /* For Data Center Bridging config */ 512 void (*config_dcb_tc)(struct xgbe_prv_data *); 513 void (*config_dcb_pfc)(struct xgbe_prv_data *); 514 }; 515 516 struct xgbe_desc_if { 517 int (*alloc_ring_resources)(struct xgbe_prv_data *); 518 void (*free_ring_resources)(struct xgbe_prv_data *); 519 int (*map_tx_skb)(struct xgbe_channel *, struct sk_buff *); 520 void (*realloc_skb)(struct xgbe_channel *); 521 void (*unmap_skb)(struct xgbe_prv_data *, struct xgbe_ring_data *); 522 void (*wrapper_tx_desc_init)(struct xgbe_prv_data *); 523 void (*wrapper_rx_desc_init)(struct xgbe_prv_data *); 524 }; 525 526 /* This structure contains flags that indicate what hardware features 527 * or configurations are present in the device. 528 */ 529 struct xgbe_hw_features { 530 /* HW Version */ 531 unsigned int version; 532 533 /* HW Feature Register0 */ 534 unsigned int gmii; /* 1000 Mbps support */ 535 unsigned int vlhash; /* VLAN Hash Filter */ 536 unsigned int sma; /* SMA(MDIO) Interface */ 537 unsigned int rwk; /* PMT remote wake-up packet */ 538 unsigned int mgk; /* PMT magic packet */ 539 unsigned int mmc; /* RMON module */ 540 unsigned int aoe; /* ARP Offload */ 541 unsigned int ts; /* IEEE 1588-2008 Adavanced Timestamp */ 542 unsigned int eee; /* Energy Efficient Ethernet */ 543 unsigned int tx_coe; /* Tx Checksum Offload */ 544 unsigned int rx_coe; /* Rx Checksum Offload */ 545 unsigned int addn_mac; /* Additional MAC Addresses */ 546 unsigned int ts_src; /* Timestamp Source */ 547 unsigned int sa_vlan_ins; /* Source Address or VLAN Insertion */ 548 549 /* HW Feature Register1 */ 550 unsigned int rx_fifo_size; /* MTL Receive FIFO Size */ 551 unsigned int tx_fifo_size; /* MTL Transmit FIFO Size */ 552 unsigned int adv_ts_hi; /* Advance Timestamping High Word */ 553 unsigned int dcb; /* DCB Feature */ 554 unsigned int sph; /* Split Header Feature */ 555 unsigned int tso; /* TCP Segmentation Offload */ 556 unsigned int dma_debug; /* DMA Debug Registers */ 557 unsigned int rss; /* Receive Side Scaling */ 558 unsigned int tc_cnt; /* Number of Traffic Classes */ 559 unsigned int hash_table_size; /* Hash Table Size */ 560 unsigned int l3l4_filter_num; /* Number of L3-L4 Filters */ 561 562 /* HW Feature Register2 */ 563 unsigned int rx_q_cnt; /* Number of MTL Receive Queues */ 564 unsigned int tx_q_cnt; /* Number of MTL Transmit Queues */ 565 unsigned int rx_ch_cnt; /* Number of DMA Receive Channels */ 566 unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */ 567 unsigned int pps_out_num; /* Number of PPS outputs */ 568 unsigned int aux_snap_num; /* Number of Aux snapshot inputs */ 569 }; 570 571 struct xgbe_prv_data { 572 struct net_device *netdev; 573 struct platform_device *pdev; 574 struct device *dev; 575 576 /* XGMAC/XPCS related mmio registers */ 577 void __iomem *xgmac_regs; /* XGMAC CSRs */ 578 void __iomem *xpcs_regs; /* XPCS MMD registers */ 579 580 /* Overall device lock */ 581 spinlock_t lock; 582 583 /* XPCS indirect addressing mutex */ 584 struct mutex xpcs_mutex; 585 586 int irq_number; 587 588 struct xgbe_hw_if hw_if; 589 struct xgbe_desc_if desc_if; 590 591 /* AXI DMA settings */ 592 unsigned int axdomain; 593 unsigned int arcache; 594 unsigned int awcache; 595 596 /* Rings for Tx/Rx on a DMA channel */ 597 struct xgbe_channel *channel; 598 unsigned int channel_count; 599 unsigned int tx_ring_count; 600 unsigned int tx_desc_count; 601 unsigned int rx_ring_count; 602 unsigned int rx_desc_count; 603 604 unsigned int tx_q_count; 605 unsigned int rx_q_count; 606 607 /* Tx/Rx common settings */ 608 unsigned int pblx8; 609 610 /* Tx settings */ 611 unsigned int tx_sf_mode; 612 unsigned int tx_threshold; 613 unsigned int tx_pbl; 614 unsigned int tx_osp_mode; 615 616 /* Rx settings */ 617 unsigned int rx_sf_mode; 618 unsigned int rx_threshold; 619 unsigned int rx_pbl; 620 621 /* Tx coalescing settings */ 622 unsigned int tx_usecs; 623 unsigned int tx_frames; 624 625 /* Rx coalescing settings */ 626 unsigned int rx_riwt; 627 unsigned int rx_frames; 628 629 /* Current MTU */ 630 unsigned int rx_buf_size; 631 632 /* Flow control settings */ 633 unsigned int pause_autoneg; 634 unsigned int tx_pause; 635 unsigned int rx_pause; 636 637 /* MDIO settings */ 638 struct module *phy_module; 639 char *mii_bus_id; 640 struct mii_bus *mii; 641 int mdio_mmd; 642 struct phy_device *phydev; 643 int default_autoneg; 644 int default_speed; 645 646 /* Current PHY settings */ 647 phy_interface_t phy_mode; 648 int phy_link; 649 int phy_speed; 650 unsigned int phy_tx_pause; 651 unsigned int phy_rx_pause; 652 653 /* Netdev related settings */ 654 netdev_features_t netdev_features; 655 struct napi_struct napi; 656 struct xgbe_mmc_stats mmc_stats; 657 658 /* Filtering support */ 659 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 660 661 /* Device clocks */ 662 struct clk *sysclk; 663 struct clk *ptpclk; 664 665 /* Timestamp support */ 666 spinlock_t tstamp_lock; 667 struct ptp_clock_info ptp_clock_info; 668 struct ptp_clock *ptp_clock; 669 struct hwtstamp_config tstamp_config; 670 struct cyclecounter tstamp_cc; 671 struct timecounter tstamp_tc; 672 unsigned int tstamp_addend; 673 struct work_struct tx_tstamp_work; 674 struct sk_buff *tx_tstamp_skb; 675 u64 tx_tstamp; 676 677 /* DCB support */ 678 struct ieee_ets *ets; 679 struct ieee_pfc *pfc; 680 unsigned int q2tc_map[XGBE_MAX_QUEUES]; 681 unsigned int prio2q_map[IEEE_8021QAZ_MAX_TCS]; 682 683 /* Hardware features of the device */ 684 struct xgbe_hw_features hw_feat; 685 686 /* Device restart work structure */ 687 struct work_struct restart_work; 688 689 /* Keeps track of power mode */ 690 unsigned int power_down; 691 692 #ifdef CONFIG_DEBUG_FS 693 struct dentry *xgbe_debugfs; 694 695 unsigned int debugfs_xgmac_reg; 696 697 unsigned int debugfs_xpcs_mmd; 698 unsigned int debugfs_xpcs_reg; 699 #endif 700 }; 701 702 /* Function prototypes*/ 703 704 void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *); 705 void xgbe_init_function_ptrs_desc(struct xgbe_desc_if *); 706 struct net_device_ops *xgbe_get_netdev_ops(void); 707 struct ethtool_ops *xgbe_get_ethtool_ops(void); 708 #ifdef CONFIG_AMD_XGBE_DCB 709 const struct dcbnl_rtnl_ops *xgbe_get_dcbnl_ops(void); 710 #endif 711 712 int xgbe_mdio_register(struct xgbe_prv_data *); 713 void xgbe_mdio_unregister(struct xgbe_prv_data *); 714 void xgbe_dump_phy_registers(struct xgbe_prv_data *); 715 void xgbe_ptp_register(struct xgbe_prv_data *); 716 void xgbe_ptp_unregister(struct xgbe_prv_data *); 717 void xgbe_dump_tx_desc(struct xgbe_ring *, unsigned int, unsigned int, 718 unsigned int); 719 void xgbe_dump_rx_desc(struct xgbe_ring *, struct xgbe_ring_desc *, 720 unsigned int); 721 void xgbe_print_pkt(struct net_device *, struct sk_buff *, bool); 722 void xgbe_get_all_hw_features(struct xgbe_prv_data *); 723 int xgbe_powerup(struct net_device *, unsigned int); 724 int xgbe_powerdown(struct net_device *, unsigned int); 725 void xgbe_init_rx_coalesce(struct xgbe_prv_data *); 726 void xgbe_init_tx_coalesce(struct xgbe_prv_data *); 727 728 #ifdef CONFIG_DEBUG_FS 729 void xgbe_debugfs_init(struct xgbe_prv_data *); 730 void xgbe_debugfs_exit(struct xgbe_prv_data *); 731 #else 732 static inline void xgbe_debugfs_init(struct xgbe_prv_data *pdata) {} 733 static inline void xgbe_debugfs_exit(struct xgbe_prv_data *pdata) {} 734 #endif /* CONFIG_DEBUG_FS */ 735 736 /* NOTE: Uncomment for TX and RX DESCRIPTOR DUMP in KERNEL LOG */ 737 #if 0 738 #define XGMAC_ENABLE_TX_DESC_DUMP 739 #define XGMAC_ENABLE_RX_DESC_DUMP 740 #endif 741 742 /* NOTE: Uncomment for TX and RX PACKET DUMP in KERNEL LOG */ 743 #if 0 744 #define XGMAC_ENABLE_TX_PKT_DUMP 745 #define XGMAC_ENABLE_RX_PKT_DUMP 746 #endif 747 748 /* NOTE: Uncomment for function trace log messages in KERNEL LOG */ 749 #if 0 750 #define YDEBUG 751 #define YDEBUG_MDIO 752 #endif 753 754 /* For debug prints */ 755 #ifdef YDEBUG 756 #define DBGPR(x...) pr_alert(x) 757 #define DBGPHY_REGS(x...) xgbe_dump_phy_registers(x) 758 #else 759 #define DBGPR(x...) do { } while (0) 760 #define DBGPHY_REGS(x...) do { } while (0) 761 #endif 762 763 #ifdef YDEBUG_MDIO 764 #define DBGPR_MDIO(x...) pr_alert(x) 765 #else 766 #define DBGPR_MDIO(x...) do { } while (0) 767 #endif 768 769 #endif 770