1 /* 2 * AMD 10Gb Ethernet driver 3 * 4 * This file is available to you under your choice of the following two 5 * licenses: 6 * 7 * License 1: GPLv2 8 * 9 * Copyright (c) 2016 Advanced Micro Devices, Inc. 10 * 11 * This file is free software; you may copy, redistribute and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation, either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program. If not, see <http://www.gnu.org/licenses/>. 23 * 24 * This file incorporates work covered by the following copyright and 25 * permission notice: 26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 28 * Inc. unless otherwise expressly agreed to in writing between Synopsys 29 * and you. 30 * 31 * The Software IS NOT an item of Licensed Software or Licensed Product 32 * under any End User Software License Agreement or Agreement for Licensed 33 * Product with Synopsys or any supplement thereto. Permission is hereby 34 * granted, free of charge, to any person obtaining a copy of this software 35 * annotated with this license and the Software, to deal in the Software 36 * without restriction, including without limitation the rights to use, 37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 38 * of the Software, and to permit persons to whom the Software is furnished 39 * to do so, subject to the following conditions: 40 * 41 * The above copyright notice and this permission notice shall be included 42 * in all copies or substantial portions of the Software. 43 * 44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 54 * THE POSSIBILITY OF SUCH DAMAGE. 55 * 56 * 57 * License 2: Modified BSD 58 * 59 * Copyright (c) 2016 Advanced Micro Devices, Inc. 60 * All rights reserved. 61 * 62 * Redistribution and use in source and binary forms, with or without 63 * modification, are permitted provided that the following conditions are met: 64 * * Redistributions of source code must retain the above copyright 65 * notice, this list of conditions and the following disclaimer. 66 * * Redistributions in binary form must reproduce the above copyright 67 * notice, this list of conditions and the following disclaimer in the 68 * documentation and/or other materials provided with the distribution. 69 * * Neither the name of Advanced Micro Devices, Inc. nor the 70 * names of its contributors may be used to endorse or promote products 71 * derived from this software without specific prior written permission. 72 * 73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY 77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 83 * 84 * This file incorporates work covered by the following copyright and 85 * permission notice: 86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 88 * Inc. unless otherwise expressly agreed to in writing between Synopsys 89 * and you. 90 * 91 * The Software IS NOT an item of Licensed Software or Licensed Product 92 * under any End User Software License Agreement or Agreement for Licensed 93 * Product with Synopsys or any supplement thereto. Permission is hereby 94 * granted, free of charge, to any person obtaining a copy of this software 95 * annotated with this license and the Software, to deal in the Software 96 * without restriction, including without limitation the rights to use, 97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 98 * of the Software, and to permit persons to whom the Software is furnished 99 * to do so, subject to the following conditions: 100 * 101 * The above copyright notice and this permission notice shall be included 102 * in all copies or substantial portions of the Software. 103 * 104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 114 * THE POSSIBILITY OF SUCH DAMAGE. 115 */ 116 117 #include <linux/module.h> 118 #include <linux/device.h> 119 #include <linux/kmod.h> 120 #include <linux/mdio.h> 121 #include <linux/phy.h> 122 #include <linux/ethtool.h> 123 124 #include "xgbe.h" 125 #include "xgbe-common.h" 126 127 #define XGBE_PHY_PORT_SPEED_100 BIT(0) 128 #define XGBE_PHY_PORT_SPEED_1000 BIT(1) 129 #define XGBE_PHY_PORT_SPEED_2500 BIT(2) 130 #define XGBE_PHY_PORT_SPEED_10000 BIT(3) 131 132 #define XGBE_MUTEX_RELEASE 0x80000000 133 134 #define XGBE_SFP_DIRECT 7 135 136 /* I2C target addresses */ 137 #define XGBE_SFP_SERIAL_ID_ADDRESS 0x50 138 #define XGBE_SFP_DIAG_INFO_ADDRESS 0x51 139 #define XGBE_SFP_PHY_ADDRESS 0x56 140 #define XGBE_GPIO_ADDRESS_PCA9555 0x20 141 142 /* SFP sideband signal indicators */ 143 #define XGBE_GPIO_NO_TX_FAULT BIT(0) 144 #define XGBE_GPIO_NO_RATE_SELECT BIT(1) 145 #define XGBE_GPIO_NO_MOD_ABSENT BIT(2) 146 #define XGBE_GPIO_NO_RX_LOS BIT(3) 147 148 /* Rate-change complete wait/retry count */ 149 #define XGBE_RATECHANGE_COUNT 500 150 151 /* CDR delay values for KR support (in usec) */ 152 #define XGBE_CDR_DELAY_INIT 10000 153 #define XGBE_CDR_DELAY_INC 10000 154 #define XGBE_CDR_DELAY_MAX 100000 155 156 /* RRC frequency during link status check */ 157 #define XGBE_RRC_FREQUENCY 10 158 159 enum xgbe_port_mode { 160 XGBE_PORT_MODE_RSVD = 0, 161 XGBE_PORT_MODE_BACKPLANE, 162 XGBE_PORT_MODE_BACKPLANE_2500, 163 XGBE_PORT_MODE_1000BASE_T, 164 XGBE_PORT_MODE_1000BASE_X, 165 XGBE_PORT_MODE_NBASE_T, 166 XGBE_PORT_MODE_10GBASE_T, 167 XGBE_PORT_MODE_10GBASE_R, 168 XGBE_PORT_MODE_SFP, 169 XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG, 170 XGBE_PORT_MODE_MAX, 171 }; 172 173 enum xgbe_conn_type { 174 XGBE_CONN_TYPE_NONE = 0, 175 XGBE_CONN_TYPE_SFP, 176 XGBE_CONN_TYPE_MDIO, 177 XGBE_CONN_TYPE_RSVD1, 178 XGBE_CONN_TYPE_BACKPLANE, 179 XGBE_CONN_TYPE_MAX, 180 }; 181 182 /* SFP/SFP+ related definitions */ 183 enum xgbe_sfp_comm { 184 XGBE_SFP_COMM_DIRECT = 0, 185 XGBE_SFP_COMM_PCA9545, 186 }; 187 188 enum xgbe_sfp_cable { 189 XGBE_SFP_CABLE_UNKNOWN = 0, 190 XGBE_SFP_CABLE_ACTIVE, 191 XGBE_SFP_CABLE_PASSIVE, 192 }; 193 194 enum xgbe_sfp_base { 195 XGBE_SFP_BASE_UNKNOWN = 0, 196 XGBE_SFP_BASE_1000_T, 197 XGBE_SFP_BASE_1000_SX, 198 XGBE_SFP_BASE_1000_LX, 199 XGBE_SFP_BASE_1000_CX, 200 XGBE_SFP_BASE_10000_SR, 201 XGBE_SFP_BASE_10000_LR, 202 XGBE_SFP_BASE_10000_LRM, 203 XGBE_SFP_BASE_10000_ER, 204 XGBE_SFP_BASE_10000_CR, 205 }; 206 207 enum xgbe_sfp_speed { 208 XGBE_SFP_SPEED_UNKNOWN = 0, 209 XGBE_SFP_SPEED_100_1000, 210 XGBE_SFP_SPEED_1000, 211 XGBE_SFP_SPEED_10000, 212 }; 213 214 /* SFP Serial ID Base ID values relative to an offset of 0 */ 215 #define XGBE_SFP_BASE_ID 0 216 #define XGBE_SFP_ID_SFP 0x03 217 218 #define XGBE_SFP_BASE_EXT_ID 1 219 #define XGBE_SFP_EXT_ID_SFP 0x04 220 221 #define XGBE_SFP_BASE_10GBE_CC 3 222 #define XGBE_SFP_BASE_10GBE_CC_SR BIT(4) 223 #define XGBE_SFP_BASE_10GBE_CC_LR BIT(5) 224 #define XGBE_SFP_BASE_10GBE_CC_LRM BIT(6) 225 #define XGBE_SFP_BASE_10GBE_CC_ER BIT(7) 226 227 #define XGBE_SFP_BASE_1GBE_CC 6 228 #define XGBE_SFP_BASE_1GBE_CC_SX BIT(0) 229 #define XGBE_SFP_BASE_1GBE_CC_LX BIT(1) 230 #define XGBE_SFP_BASE_1GBE_CC_CX BIT(2) 231 #define XGBE_SFP_BASE_1GBE_CC_T BIT(3) 232 233 #define XGBE_SFP_BASE_CABLE 8 234 #define XGBE_SFP_BASE_CABLE_PASSIVE BIT(2) 235 #define XGBE_SFP_BASE_CABLE_ACTIVE BIT(3) 236 237 #define XGBE_SFP_BASE_BR 12 238 #define XGBE_SFP_BASE_BR_1GBE_MIN 0x0a 239 #define XGBE_SFP_BASE_BR_1GBE_MAX 0x0d 240 #define XGBE_SFP_BASE_BR_10GBE_MIN 0x64 241 #define XGBE_SFP_BASE_BR_10GBE_MAX 0x68 242 243 #define XGBE_SFP_BASE_CU_CABLE_LEN 18 244 245 #define XGBE_SFP_BASE_VENDOR_NAME 20 246 #define XGBE_SFP_BASE_VENDOR_NAME_LEN 16 247 #define XGBE_SFP_BASE_VENDOR_PN 40 248 #define XGBE_SFP_BASE_VENDOR_PN_LEN 16 249 #define XGBE_SFP_BASE_VENDOR_REV 56 250 #define XGBE_SFP_BASE_VENDOR_REV_LEN 4 251 252 #define XGBE_SFP_BASE_CC 63 253 254 /* SFP Serial ID Extended ID values relative to an offset of 64 */ 255 #define XGBE_SFP_BASE_VENDOR_SN 4 256 #define XGBE_SFP_BASE_VENDOR_SN_LEN 16 257 258 #define XGBE_SFP_EXTD_OPT1 1 259 #define XGBE_SFP_EXTD_OPT1_RX_LOS BIT(1) 260 #define XGBE_SFP_EXTD_OPT1_TX_FAULT BIT(3) 261 262 #define XGBE_SFP_EXTD_DIAG 28 263 #define XGBE_SFP_EXTD_DIAG_ADDR_CHANGE BIT(2) 264 265 #define XGBE_SFP_EXTD_SFF_8472 30 266 267 #define XGBE_SFP_EXTD_CC 31 268 269 struct xgbe_sfp_eeprom { 270 u8 base[64]; 271 u8 extd[32]; 272 u8 vendor[32]; 273 }; 274 275 #define XGBE_SFP_DIAGS_SUPPORTED(_x) \ 276 ((_x)->extd[XGBE_SFP_EXTD_SFF_8472] && \ 277 !((_x)->extd[XGBE_SFP_EXTD_DIAG] & XGBE_SFP_EXTD_DIAG_ADDR_CHANGE)) 278 279 #define XGBE_SFP_EEPROM_BASE_LEN 256 280 #define XGBE_SFP_EEPROM_DIAG_LEN 256 281 #define XGBE_SFP_EEPROM_MAX (XGBE_SFP_EEPROM_BASE_LEN + \ 282 XGBE_SFP_EEPROM_DIAG_LEN) 283 284 #define XGBE_BEL_FUSE_VENDOR "BEL-FUSE " 285 #define XGBE_BEL_FUSE_PARTNO "1GBT-SFP06 " 286 287 struct xgbe_sfp_ascii { 288 union { 289 char vendor[XGBE_SFP_BASE_VENDOR_NAME_LEN + 1]; 290 char partno[XGBE_SFP_BASE_VENDOR_PN_LEN + 1]; 291 char rev[XGBE_SFP_BASE_VENDOR_REV_LEN + 1]; 292 char serno[XGBE_SFP_BASE_VENDOR_SN_LEN + 1]; 293 } u; 294 }; 295 296 /* MDIO PHY reset types */ 297 enum xgbe_mdio_reset { 298 XGBE_MDIO_RESET_NONE = 0, 299 XGBE_MDIO_RESET_I2C_GPIO, 300 XGBE_MDIO_RESET_INT_GPIO, 301 XGBE_MDIO_RESET_MAX, 302 }; 303 304 /* Re-driver related definitions */ 305 enum xgbe_phy_redrv_if { 306 XGBE_PHY_REDRV_IF_MDIO = 0, 307 XGBE_PHY_REDRV_IF_I2C, 308 XGBE_PHY_REDRV_IF_MAX, 309 }; 310 311 enum xgbe_phy_redrv_model { 312 XGBE_PHY_REDRV_MODEL_4223 = 0, 313 XGBE_PHY_REDRV_MODEL_4227, 314 XGBE_PHY_REDRV_MODEL_MAX, 315 }; 316 317 enum xgbe_phy_redrv_mode { 318 XGBE_PHY_REDRV_MODE_CX = 5, 319 XGBE_PHY_REDRV_MODE_SR = 9, 320 }; 321 322 #define XGBE_PHY_REDRV_MODE_REG 0x12b0 323 324 /* PHY related configuration information */ 325 struct xgbe_phy_data { 326 enum xgbe_port_mode port_mode; 327 328 unsigned int port_id; 329 330 unsigned int port_speeds; 331 332 enum xgbe_conn_type conn_type; 333 334 enum xgbe_mode cur_mode; 335 enum xgbe_mode start_mode; 336 337 unsigned int rrc_count; 338 339 unsigned int mdio_addr; 340 341 /* SFP Support */ 342 enum xgbe_sfp_comm sfp_comm; 343 unsigned int sfp_mux_address; 344 unsigned int sfp_mux_channel; 345 346 unsigned int sfp_gpio_address; 347 unsigned int sfp_gpio_mask; 348 unsigned int sfp_gpio_inputs; 349 unsigned int sfp_gpio_rx_los; 350 unsigned int sfp_gpio_tx_fault; 351 unsigned int sfp_gpio_mod_absent; 352 unsigned int sfp_gpio_rate_select; 353 354 unsigned int sfp_rx_los; 355 unsigned int sfp_tx_fault; 356 unsigned int sfp_mod_absent; 357 unsigned int sfp_changed; 358 unsigned int sfp_phy_avail; 359 unsigned int sfp_cable_len; 360 enum xgbe_sfp_base sfp_base; 361 enum xgbe_sfp_cable sfp_cable; 362 enum xgbe_sfp_speed sfp_speed; 363 struct xgbe_sfp_eeprom sfp_eeprom; 364 365 /* External PHY support */ 366 enum xgbe_mdio_mode phydev_mode; 367 struct mii_bus *mii; 368 struct phy_device *phydev; 369 enum xgbe_mdio_reset mdio_reset; 370 unsigned int mdio_reset_addr; 371 unsigned int mdio_reset_gpio; 372 373 /* Re-driver support */ 374 unsigned int redrv; 375 unsigned int redrv_if; 376 unsigned int redrv_addr; 377 unsigned int redrv_lane; 378 unsigned int redrv_model; 379 380 /* KR AN support */ 381 unsigned int phy_cdr_notrack; 382 unsigned int phy_cdr_delay; 383 }; 384 385 /* I2C, MDIO and GPIO lines are muxed, so only one device at a time */ 386 static DEFINE_MUTEX(xgbe_phy_comm_lock); 387 388 static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata); 389 390 static int xgbe_phy_i2c_xfer(struct xgbe_prv_data *pdata, 391 struct xgbe_i2c_op *i2c_op) 392 { 393 return pdata->i2c_if.i2c_xfer(pdata, i2c_op); 394 } 395 396 static int xgbe_phy_redrv_write(struct xgbe_prv_data *pdata, unsigned int reg, 397 unsigned int val) 398 { 399 struct xgbe_phy_data *phy_data = pdata->phy_data; 400 struct xgbe_i2c_op i2c_op; 401 __be16 *redrv_val; 402 u8 redrv_data[5], csum; 403 unsigned int i, retry; 404 int ret; 405 406 /* High byte of register contains read/write indicator */ 407 redrv_data[0] = ((reg >> 8) & 0xff) << 1; 408 redrv_data[1] = reg & 0xff; 409 redrv_val = (__be16 *)&redrv_data[2]; 410 *redrv_val = cpu_to_be16(val); 411 412 /* Calculate 1 byte checksum */ 413 csum = 0; 414 for (i = 0; i < 4; i++) { 415 csum += redrv_data[i]; 416 if (redrv_data[i] > csum) 417 csum++; 418 } 419 redrv_data[4] = ~csum; 420 421 retry = 1; 422 again1: 423 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 424 i2c_op.target = phy_data->redrv_addr; 425 i2c_op.len = sizeof(redrv_data); 426 i2c_op.buf = redrv_data; 427 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 428 if (ret) { 429 if ((ret == -EAGAIN) && retry--) 430 goto again1; 431 432 return ret; 433 } 434 435 retry = 1; 436 again2: 437 i2c_op.cmd = XGBE_I2C_CMD_READ; 438 i2c_op.target = phy_data->redrv_addr; 439 i2c_op.len = 1; 440 i2c_op.buf = redrv_data; 441 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 442 if (ret) { 443 if ((ret == -EAGAIN) && retry--) 444 goto again2; 445 446 return ret; 447 } 448 449 if (redrv_data[0] != 0xff) { 450 netif_dbg(pdata, drv, pdata->netdev, 451 "Redriver write checksum error\n"); 452 ret = -EIO; 453 } 454 455 return ret; 456 } 457 458 static int xgbe_phy_i2c_write(struct xgbe_prv_data *pdata, unsigned int target, 459 void *val, unsigned int val_len) 460 { 461 struct xgbe_i2c_op i2c_op; 462 int retry, ret; 463 464 retry = 1; 465 again: 466 /* Write the specfied register */ 467 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 468 i2c_op.target = target; 469 i2c_op.len = val_len; 470 i2c_op.buf = val; 471 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 472 if ((ret == -EAGAIN) && retry--) 473 goto again; 474 475 return ret; 476 } 477 478 static int xgbe_phy_i2c_read(struct xgbe_prv_data *pdata, unsigned int target, 479 void *reg, unsigned int reg_len, 480 void *val, unsigned int val_len) 481 { 482 struct xgbe_i2c_op i2c_op; 483 int retry, ret; 484 485 retry = 1; 486 again1: 487 /* Set the specified register to read */ 488 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 489 i2c_op.target = target; 490 i2c_op.len = reg_len; 491 i2c_op.buf = reg; 492 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 493 if (ret) { 494 if ((ret == -EAGAIN) && retry--) 495 goto again1; 496 497 return ret; 498 } 499 500 retry = 1; 501 again2: 502 /* Read the specfied register */ 503 i2c_op.cmd = XGBE_I2C_CMD_READ; 504 i2c_op.target = target; 505 i2c_op.len = val_len; 506 i2c_op.buf = val; 507 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 508 if ((ret == -EAGAIN) && retry--) 509 goto again2; 510 511 return ret; 512 } 513 514 static int xgbe_phy_sfp_put_mux(struct xgbe_prv_data *pdata) 515 { 516 struct xgbe_phy_data *phy_data = pdata->phy_data; 517 struct xgbe_i2c_op i2c_op; 518 u8 mux_channel; 519 520 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT) 521 return 0; 522 523 /* Select no mux channels */ 524 mux_channel = 0; 525 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 526 i2c_op.target = phy_data->sfp_mux_address; 527 i2c_op.len = sizeof(mux_channel); 528 i2c_op.buf = &mux_channel; 529 530 return xgbe_phy_i2c_xfer(pdata, &i2c_op); 531 } 532 533 static int xgbe_phy_sfp_get_mux(struct xgbe_prv_data *pdata) 534 { 535 struct xgbe_phy_data *phy_data = pdata->phy_data; 536 struct xgbe_i2c_op i2c_op; 537 u8 mux_channel; 538 539 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT) 540 return 0; 541 542 /* Select desired mux channel */ 543 mux_channel = 1 << phy_data->sfp_mux_channel; 544 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 545 i2c_op.target = phy_data->sfp_mux_address; 546 i2c_op.len = sizeof(mux_channel); 547 i2c_op.buf = &mux_channel; 548 549 return xgbe_phy_i2c_xfer(pdata, &i2c_op); 550 } 551 552 static void xgbe_phy_put_comm_ownership(struct xgbe_prv_data *pdata) 553 { 554 mutex_unlock(&xgbe_phy_comm_lock); 555 } 556 557 static int xgbe_phy_get_comm_ownership(struct xgbe_prv_data *pdata) 558 { 559 struct xgbe_phy_data *phy_data = pdata->phy_data; 560 unsigned long timeout; 561 unsigned int mutex_id; 562 563 /* The I2C and MDIO/GPIO bus is multiplexed between multiple devices, 564 * the driver needs to take the software mutex and then the hardware 565 * mutexes before being able to use the busses. 566 */ 567 mutex_lock(&xgbe_phy_comm_lock); 568 569 /* Clear the mutexes */ 570 XP_IOWRITE(pdata, XP_I2C_MUTEX, XGBE_MUTEX_RELEASE); 571 XP_IOWRITE(pdata, XP_MDIO_MUTEX, XGBE_MUTEX_RELEASE); 572 573 /* Mutex formats are the same for I2C and MDIO/GPIO */ 574 mutex_id = 0; 575 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ID, phy_data->port_id); 576 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ACTIVE, 1); 577 578 timeout = jiffies + (5 * HZ); 579 while (time_before(jiffies, timeout)) { 580 /* Must be all zeroes in order to obtain the mutex */ 581 if (XP_IOREAD(pdata, XP_I2C_MUTEX) || 582 XP_IOREAD(pdata, XP_MDIO_MUTEX)) { 583 usleep_range(100, 200); 584 continue; 585 } 586 587 /* Obtain the mutex */ 588 XP_IOWRITE(pdata, XP_I2C_MUTEX, mutex_id); 589 XP_IOWRITE(pdata, XP_MDIO_MUTEX, mutex_id); 590 591 return 0; 592 } 593 594 mutex_unlock(&xgbe_phy_comm_lock); 595 596 netdev_err(pdata->netdev, "unable to obtain hardware mutexes\n"); 597 598 return -ETIMEDOUT; 599 } 600 601 static int xgbe_phy_mdio_mii_write(struct xgbe_prv_data *pdata, int addr, 602 int reg, u16 val) 603 { 604 struct xgbe_phy_data *phy_data = pdata->phy_data; 605 606 if (reg & MII_ADDR_C45) { 607 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45) 608 return -ENOTSUPP; 609 } else { 610 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22) 611 return -ENOTSUPP; 612 } 613 614 return pdata->hw_if.write_ext_mii_regs(pdata, addr, reg, val); 615 } 616 617 static int xgbe_phy_i2c_mii_write(struct xgbe_prv_data *pdata, int reg, u16 val) 618 { 619 __be16 *mii_val; 620 u8 mii_data[3]; 621 int ret; 622 623 ret = xgbe_phy_sfp_get_mux(pdata); 624 if (ret) 625 return ret; 626 627 mii_data[0] = reg & 0xff; 628 mii_val = (__be16 *)&mii_data[1]; 629 *mii_val = cpu_to_be16(val); 630 631 ret = xgbe_phy_i2c_write(pdata, XGBE_SFP_PHY_ADDRESS, 632 mii_data, sizeof(mii_data)); 633 634 xgbe_phy_sfp_put_mux(pdata); 635 636 return ret; 637 } 638 639 static int xgbe_phy_mii_write(struct mii_bus *mii, int addr, int reg, u16 val) 640 { 641 struct xgbe_prv_data *pdata = mii->priv; 642 struct xgbe_phy_data *phy_data = pdata->phy_data; 643 int ret; 644 645 ret = xgbe_phy_get_comm_ownership(pdata); 646 if (ret) 647 return ret; 648 649 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP) 650 ret = xgbe_phy_i2c_mii_write(pdata, reg, val); 651 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO) 652 ret = xgbe_phy_mdio_mii_write(pdata, addr, reg, val); 653 else 654 ret = -ENOTSUPP; 655 656 xgbe_phy_put_comm_ownership(pdata); 657 658 return ret; 659 } 660 661 static int xgbe_phy_mdio_mii_read(struct xgbe_prv_data *pdata, int addr, 662 int reg) 663 { 664 struct xgbe_phy_data *phy_data = pdata->phy_data; 665 666 if (reg & MII_ADDR_C45) { 667 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45) 668 return -ENOTSUPP; 669 } else { 670 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22) 671 return -ENOTSUPP; 672 } 673 674 return pdata->hw_if.read_ext_mii_regs(pdata, addr, reg); 675 } 676 677 static int xgbe_phy_i2c_mii_read(struct xgbe_prv_data *pdata, int reg) 678 { 679 __be16 mii_val; 680 u8 mii_reg; 681 int ret; 682 683 ret = xgbe_phy_sfp_get_mux(pdata); 684 if (ret) 685 return ret; 686 687 mii_reg = reg; 688 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_PHY_ADDRESS, 689 &mii_reg, sizeof(mii_reg), 690 &mii_val, sizeof(mii_val)); 691 if (!ret) 692 ret = be16_to_cpu(mii_val); 693 694 xgbe_phy_sfp_put_mux(pdata); 695 696 return ret; 697 } 698 699 static int xgbe_phy_mii_read(struct mii_bus *mii, int addr, int reg) 700 { 701 struct xgbe_prv_data *pdata = mii->priv; 702 struct xgbe_phy_data *phy_data = pdata->phy_data; 703 int ret; 704 705 ret = xgbe_phy_get_comm_ownership(pdata); 706 if (ret) 707 return ret; 708 709 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP) 710 ret = xgbe_phy_i2c_mii_read(pdata, reg); 711 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO) 712 ret = xgbe_phy_mdio_mii_read(pdata, addr, reg); 713 else 714 ret = -ENOTSUPP; 715 716 xgbe_phy_put_comm_ownership(pdata); 717 718 return ret; 719 } 720 721 static void xgbe_phy_sfp_phy_settings(struct xgbe_prv_data *pdata) 722 { 723 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 724 struct xgbe_phy_data *phy_data = pdata->phy_data; 725 726 if (!phy_data->sfp_mod_absent && !phy_data->sfp_changed) 727 return; 728 729 XGBE_ZERO_SUP(lks); 730 731 if (phy_data->sfp_mod_absent) { 732 pdata->phy.speed = SPEED_UNKNOWN; 733 pdata->phy.duplex = DUPLEX_UNKNOWN; 734 pdata->phy.autoneg = AUTONEG_ENABLE; 735 pdata->phy.pause_autoneg = AUTONEG_ENABLE; 736 737 XGBE_SET_SUP(lks, Autoneg); 738 XGBE_SET_SUP(lks, Pause); 739 XGBE_SET_SUP(lks, Asym_Pause); 740 XGBE_SET_SUP(lks, TP); 741 XGBE_SET_SUP(lks, FIBRE); 742 743 XGBE_LM_COPY(lks, advertising, lks, supported); 744 745 return; 746 } 747 748 switch (phy_data->sfp_base) { 749 case XGBE_SFP_BASE_1000_T: 750 case XGBE_SFP_BASE_1000_SX: 751 case XGBE_SFP_BASE_1000_LX: 752 case XGBE_SFP_BASE_1000_CX: 753 pdata->phy.speed = SPEED_UNKNOWN; 754 pdata->phy.duplex = DUPLEX_UNKNOWN; 755 pdata->phy.autoneg = AUTONEG_ENABLE; 756 pdata->phy.pause_autoneg = AUTONEG_ENABLE; 757 XGBE_SET_SUP(lks, Autoneg); 758 XGBE_SET_SUP(lks, Pause); 759 XGBE_SET_SUP(lks, Asym_Pause); 760 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T) { 761 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) 762 XGBE_SET_SUP(lks, 100baseT_Full); 763 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) 764 XGBE_SET_SUP(lks, 1000baseT_Full); 765 } else { 766 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) 767 XGBE_SET_SUP(lks, 1000baseX_Full); 768 } 769 break; 770 case XGBE_SFP_BASE_10000_SR: 771 case XGBE_SFP_BASE_10000_LR: 772 case XGBE_SFP_BASE_10000_LRM: 773 case XGBE_SFP_BASE_10000_ER: 774 case XGBE_SFP_BASE_10000_CR: 775 pdata->phy.speed = SPEED_10000; 776 pdata->phy.duplex = DUPLEX_FULL; 777 pdata->phy.autoneg = AUTONEG_DISABLE; 778 pdata->phy.pause_autoneg = AUTONEG_DISABLE; 779 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) { 780 switch (phy_data->sfp_base) { 781 case XGBE_SFP_BASE_10000_SR: 782 XGBE_SET_SUP(lks, 10000baseSR_Full); 783 break; 784 case XGBE_SFP_BASE_10000_LR: 785 XGBE_SET_SUP(lks, 10000baseLR_Full); 786 break; 787 case XGBE_SFP_BASE_10000_LRM: 788 XGBE_SET_SUP(lks, 10000baseLRM_Full); 789 break; 790 case XGBE_SFP_BASE_10000_ER: 791 XGBE_SET_SUP(lks, 10000baseER_Full); 792 break; 793 case XGBE_SFP_BASE_10000_CR: 794 XGBE_SET_SUP(lks, 10000baseCR_Full); 795 break; 796 default: 797 break; 798 } 799 } 800 break; 801 default: 802 pdata->phy.speed = SPEED_UNKNOWN; 803 pdata->phy.duplex = DUPLEX_UNKNOWN; 804 pdata->phy.autoneg = AUTONEG_DISABLE; 805 pdata->phy.pause_autoneg = AUTONEG_DISABLE; 806 break; 807 } 808 809 switch (phy_data->sfp_base) { 810 case XGBE_SFP_BASE_1000_T: 811 case XGBE_SFP_BASE_1000_CX: 812 case XGBE_SFP_BASE_10000_CR: 813 XGBE_SET_SUP(lks, TP); 814 break; 815 default: 816 XGBE_SET_SUP(lks, FIBRE); 817 break; 818 } 819 820 XGBE_LM_COPY(lks, advertising, lks, supported); 821 } 822 823 static bool xgbe_phy_sfp_bit_rate(struct xgbe_sfp_eeprom *sfp_eeprom, 824 enum xgbe_sfp_speed sfp_speed) 825 { 826 u8 *sfp_base, min, max; 827 828 sfp_base = sfp_eeprom->base; 829 830 switch (sfp_speed) { 831 case XGBE_SFP_SPEED_1000: 832 min = XGBE_SFP_BASE_BR_1GBE_MIN; 833 max = XGBE_SFP_BASE_BR_1GBE_MAX; 834 break; 835 case XGBE_SFP_SPEED_10000: 836 min = XGBE_SFP_BASE_BR_10GBE_MIN; 837 max = XGBE_SFP_BASE_BR_10GBE_MAX; 838 break; 839 default: 840 return false; 841 } 842 843 return ((sfp_base[XGBE_SFP_BASE_BR] >= min) && 844 (sfp_base[XGBE_SFP_BASE_BR] <= max)); 845 } 846 847 static void xgbe_phy_free_phy_device(struct xgbe_prv_data *pdata) 848 { 849 struct xgbe_phy_data *phy_data = pdata->phy_data; 850 851 if (phy_data->phydev) { 852 phy_detach(phy_data->phydev); 853 phy_device_remove(phy_data->phydev); 854 phy_device_free(phy_data->phydev); 855 phy_data->phydev = NULL; 856 } 857 } 858 859 static bool xgbe_phy_finisar_phy_quirks(struct xgbe_prv_data *pdata) 860 { 861 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported) = { 0, }; 862 struct xgbe_phy_data *phy_data = pdata->phy_data; 863 unsigned int phy_id = phy_data->phydev->phy_id; 864 865 if (phy_data->port_mode != XGBE_PORT_MODE_SFP) 866 return false; 867 868 if ((phy_id & 0xfffffff0) != 0x01ff0cc0) 869 return false; 870 871 /* Enable Base-T AN */ 872 phy_write(phy_data->phydev, 0x16, 0x0001); 873 phy_write(phy_data->phydev, 0x00, 0x9140); 874 phy_write(phy_data->phydev, 0x16, 0x0000); 875 876 /* Enable SGMII at 100Base-T/1000Base-T Full Duplex */ 877 phy_write(phy_data->phydev, 0x1b, 0x9084); 878 phy_write(phy_data->phydev, 0x09, 0x0e00); 879 phy_write(phy_data->phydev, 0x00, 0x8140); 880 phy_write(phy_data->phydev, 0x04, 0x0d01); 881 phy_write(phy_data->phydev, 0x00, 0x9140); 882 883 linkmode_set_bit_array(phy_10_100_features_array, 884 ARRAY_SIZE(phy_10_100_features_array), 885 supported); 886 linkmode_set_bit_array(phy_gbit_features_array, 887 ARRAY_SIZE(phy_gbit_features_array), 888 supported); 889 890 linkmode_copy(phy_data->phydev->supported, supported); 891 892 phy_support_asym_pause(phy_data->phydev); 893 894 netif_dbg(pdata, drv, pdata->netdev, 895 "Finisar PHY quirk in place\n"); 896 897 return true; 898 } 899 900 static bool xgbe_phy_belfuse_phy_quirks(struct xgbe_prv_data *pdata) 901 { 902 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported) = { 0, }; 903 struct xgbe_phy_data *phy_data = pdata->phy_data; 904 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom; 905 unsigned int phy_id = phy_data->phydev->phy_id; 906 int reg; 907 908 if (phy_data->port_mode != XGBE_PORT_MODE_SFP) 909 return false; 910 911 if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME], 912 XGBE_BEL_FUSE_VENDOR, XGBE_SFP_BASE_VENDOR_NAME_LEN)) 913 return false; 914 915 /* For Bel-Fuse, use the extra AN flag */ 916 pdata->an_again = 1; 917 918 if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN], 919 XGBE_BEL_FUSE_PARTNO, XGBE_SFP_BASE_VENDOR_PN_LEN)) 920 return false; 921 922 if ((phy_id & 0xfffffff0) != 0x03625d10) 923 return false; 924 925 /* Disable RGMII mode */ 926 phy_write(phy_data->phydev, 0x18, 0x7007); 927 reg = phy_read(phy_data->phydev, 0x18); 928 phy_write(phy_data->phydev, 0x18, reg & ~0x0080); 929 930 /* Enable fiber register bank */ 931 phy_write(phy_data->phydev, 0x1c, 0x7c00); 932 reg = phy_read(phy_data->phydev, 0x1c); 933 reg &= 0x03ff; 934 reg &= ~0x0001; 935 phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg | 0x0001); 936 937 /* Power down SerDes */ 938 reg = phy_read(phy_data->phydev, 0x00); 939 phy_write(phy_data->phydev, 0x00, reg | 0x00800); 940 941 /* Configure SGMII-to-Copper mode */ 942 phy_write(phy_data->phydev, 0x1c, 0x7c00); 943 reg = phy_read(phy_data->phydev, 0x1c); 944 reg &= 0x03ff; 945 reg &= ~0x0006; 946 phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg | 0x0004); 947 948 /* Power up SerDes */ 949 reg = phy_read(phy_data->phydev, 0x00); 950 phy_write(phy_data->phydev, 0x00, reg & ~0x00800); 951 952 /* Enable copper register bank */ 953 phy_write(phy_data->phydev, 0x1c, 0x7c00); 954 reg = phy_read(phy_data->phydev, 0x1c); 955 reg &= 0x03ff; 956 reg &= ~0x0001; 957 phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg); 958 959 /* Power up SerDes */ 960 reg = phy_read(phy_data->phydev, 0x00); 961 phy_write(phy_data->phydev, 0x00, reg & ~0x00800); 962 963 linkmode_set_bit_array(phy_10_100_features_array, 964 ARRAY_SIZE(phy_10_100_features_array), 965 supported); 966 linkmode_set_bit_array(phy_gbit_features_array, 967 ARRAY_SIZE(phy_gbit_features_array), 968 supported); 969 linkmode_copy(phy_data->phydev->supported, supported); 970 phy_support_asym_pause(phy_data->phydev); 971 972 netif_dbg(pdata, drv, pdata->netdev, 973 "BelFuse PHY quirk in place\n"); 974 975 return true; 976 } 977 978 static void xgbe_phy_external_phy_quirks(struct xgbe_prv_data *pdata) 979 { 980 if (xgbe_phy_belfuse_phy_quirks(pdata)) 981 return; 982 983 if (xgbe_phy_finisar_phy_quirks(pdata)) 984 return; 985 } 986 987 static int xgbe_phy_find_phy_device(struct xgbe_prv_data *pdata) 988 { 989 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 990 struct xgbe_phy_data *phy_data = pdata->phy_data; 991 struct phy_device *phydev; 992 int ret; 993 994 /* If we already have a PHY, just return */ 995 if (phy_data->phydev) 996 return 0; 997 998 /* Clear the extra AN flag */ 999 pdata->an_again = 0; 1000 1001 /* Check for the use of an external PHY */ 1002 if (phy_data->phydev_mode == XGBE_MDIO_MODE_NONE) 1003 return 0; 1004 1005 /* For SFP, only use an external PHY if available */ 1006 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) && 1007 !phy_data->sfp_phy_avail) 1008 return 0; 1009 1010 /* Set the proper MDIO mode for the PHY */ 1011 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr, 1012 phy_data->phydev_mode); 1013 if (ret) { 1014 netdev_err(pdata->netdev, 1015 "mdio port/clause not compatible (%u/%u)\n", 1016 phy_data->mdio_addr, phy_data->phydev_mode); 1017 return ret; 1018 } 1019 1020 /* Create and connect to the PHY device */ 1021 phydev = get_phy_device(phy_data->mii, phy_data->mdio_addr, 1022 (phy_data->phydev_mode == XGBE_MDIO_MODE_CL45)); 1023 if (IS_ERR(phydev)) { 1024 netdev_err(pdata->netdev, "get_phy_device failed\n"); 1025 return -ENODEV; 1026 } 1027 netif_dbg(pdata, drv, pdata->netdev, "external PHY id is %#010x\n", 1028 phydev->phy_id); 1029 1030 /*TODO: If c45, add request_module based on one of the MMD ids? */ 1031 1032 ret = phy_device_register(phydev); 1033 if (ret) { 1034 netdev_err(pdata->netdev, "phy_device_register failed\n"); 1035 phy_device_free(phydev); 1036 return ret; 1037 } 1038 1039 ret = phy_attach_direct(pdata->netdev, phydev, phydev->dev_flags, 1040 PHY_INTERFACE_MODE_SGMII); 1041 if (ret) { 1042 netdev_err(pdata->netdev, "phy_attach_direct failed\n"); 1043 phy_device_remove(phydev); 1044 phy_device_free(phydev); 1045 return ret; 1046 } 1047 phy_data->phydev = phydev; 1048 1049 xgbe_phy_external_phy_quirks(pdata); 1050 1051 linkmode_and(phydev->advertising, phydev->advertising, 1052 lks->link_modes.advertising); 1053 1054 phy_start_aneg(phy_data->phydev); 1055 1056 return 0; 1057 } 1058 1059 static void xgbe_phy_sfp_external_phy(struct xgbe_prv_data *pdata) 1060 { 1061 struct xgbe_phy_data *phy_data = pdata->phy_data; 1062 int ret; 1063 1064 if (!phy_data->sfp_changed) 1065 return; 1066 1067 phy_data->sfp_phy_avail = 0; 1068 1069 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T) 1070 return; 1071 1072 /* Check access to the PHY by reading CTRL1 */ 1073 ret = xgbe_phy_i2c_mii_read(pdata, MII_BMCR); 1074 if (ret < 0) 1075 return; 1076 1077 /* Successfully accessed the PHY */ 1078 phy_data->sfp_phy_avail = 1; 1079 } 1080 1081 static bool xgbe_phy_check_sfp_rx_los(struct xgbe_phy_data *phy_data) 1082 { 1083 u8 *sfp_extd = phy_data->sfp_eeprom.extd; 1084 1085 if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_RX_LOS)) 1086 return false; 1087 1088 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_RX_LOS) 1089 return false; 1090 1091 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_rx_los)) 1092 return true; 1093 1094 return false; 1095 } 1096 1097 static bool xgbe_phy_check_sfp_tx_fault(struct xgbe_phy_data *phy_data) 1098 { 1099 u8 *sfp_extd = phy_data->sfp_eeprom.extd; 1100 1101 if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_TX_FAULT)) 1102 return false; 1103 1104 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_TX_FAULT) 1105 return false; 1106 1107 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_tx_fault)) 1108 return true; 1109 1110 return false; 1111 } 1112 1113 static bool xgbe_phy_check_sfp_mod_absent(struct xgbe_phy_data *phy_data) 1114 { 1115 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_MOD_ABSENT) 1116 return false; 1117 1118 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_mod_absent)) 1119 return true; 1120 1121 return false; 1122 } 1123 1124 static void xgbe_phy_sfp_parse_eeprom(struct xgbe_prv_data *pdata) 1125 { 1126 struct xgbe_phy_data *phy_data = pdata->phy_data; 1127 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom; 1128 u8 *sfp_base; 1129 1130 sfp_base = sfp_eeprom->base; 1131 1132 if (sfp_base[XGBE_SFP_BASE_ID] != XGBE_SFP_ID_SFP) 1133 return; 1134 1135 if (sfp_base[XGBE_SFP_BASE_EXT_ID] != XGBE_SFP_EXT_ID_SFP) 1136 return; 1137 1138 /* Update transceiver signals (eeprom extd/options) */ 1139 phy_data->sfp_tx_fault = xgbe_phy_check_sfp_tx_fault(phy_data); 1140 phy_data->sfp_rx_los = xgbe_phy_check_sfp_rx_los(phy_data); 1141 1142 /* Assume ACTIVE cable unless told it is PASSIVE */ 1143 if (sfp_base[XGBE_SFP_BASE_CABLE] & XGBE_SFP_BASE_CABLE_PASSIVE) { 1144 phy_data->sfp_cable = XGBE_SFP_CABLE_PASSIVE; 1145 phy_data->sfp_cable_len = sfp_base[XGBE_SFP_BASE_CU_CABLE_LEN]; 1146 } else { 1147 phy_data->sfp_cable = XGBE_SFP_CABLE_ACTIVE; 1148 } 1149 1150 /* Determine the type of SFP */ 1151 if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_SR) 1152 phy_data->sfp_base = XGBE_SFP_BASE_10000_SR; 1153 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LR) 1154 phy_data->sfp_base = XGBE_SFP_BASE_10000_LR; 1155 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LRM) 1156 phy_data->sfp_base = XGBE_SFP_BASE_10000_LRM; 1157 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_ER) 1158 phy_data->sfp_base = XGBE_SFP_BASE_10000_ER; 1159 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_SX) 1160 phy_data->sfp_base = XGBE_SFP_BASE_1000_SX; 1161 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_LX) 1162 phy_data->sfp_base = XGBE_SFP_BASE_1000_LX; 1163 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_CX) 1164 phy_data->sfp_base = XGBE_SFP_BASE_1000_CX; 1165 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_T) 1166 phy_data->sfp_base = XGBE_SFP_BASE_1000_T; 1167 else if ((phy_data->sfp_cable == XGBE_SFP_CABLE_PASSIVE) && 1168 xgbe_phy_sfp_bit_rate(sfp_eeprom, XGBE_SFP_SPEED_10000)) 1169 phy_data->sfp_base = XGBE_SFP_BASE_10000_CR; 1170 1171 switch (phy_data->sfp_base) { 1172 case XGBE_SFP_BASE_1000_T: 1173 phy_data->sfp_speed = XGBE_SFP_SPEED_100_1000; 1174 break; 1175 case XGBE_SFP_BASE_1000_SX: 1176 case XGBE_SFP_BASE_1000_LX: 1177 case XGBE_SFP_BASE_1000_CX: 1178 phy_data->sfp_speed = XGBE_SFP_SPEED_1000; 1179 break; 1180 case XGBE_SFP_BASE_10000_SR: 1181 case XGBE_SFP_BASE_10000_LR: 1182 case XGBE_SFP_BASE_10000_LRM: 1183 case XGBE_SFP_BASE_10000_ER: 1184 case XGBE_SFP_BASE_10000_CR: 1185 phy_data->sfp_speed = XGBE_SFP_SPEED_10000; 1186 break; 1187 default: 1188 break; 1189 } 1190 } 1191 1192 static void xgbe_phy_sfp_eeprom_info(struct xgbe_prv_data *pdata, 1193 struct xgbe_sfp_eeprom *sfp_eeprom) 1194 { 1195 struct xgbe_sfp_ascii sfp_ascii; 1196 char *sfp_data = (char *)&sfp_ascii; 1197 1198 netif_dbg(pdata, drv, pdata->netdev, "SFP detected:\n"); 1199 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME], 1200 XGBE_SFP_BASE_VENDOR_NAME_LEN); 1201 sfp_data[XGBE_SFP_BASE_VENDOR_NAME_LEN] = '\0'; 1202 netif_dbg(pdata, drv, pdata->netdev, " vendor: %s\n", 1203 sfp_data); 1204 1205 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN], 1206 XGBE_SFP_BASE_VENDOR_PN_LEN); 1207 sfp_data[XGBE_SFP_BASE_VENDOR_PN_LEN] = '\0'; 1208 netif_dbg(pdata, drv, pdata->netdev, " part number: %s\n", 1209 sfp_data); 1210 1211 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_REV], 1212 XGBE_SFP_BASE_VENDOR_REV_LEN); 1213 sfp_data[XGBE_SFP_BASE_VENDOR_REV_LEN] = '\0'; 1214 netif_dbg(pdata, drv, pdata->netdev, " revision level: %s\n", 1215 sfp_data); 1216 1217 memcpy(sfp_data, &sfp_eeprom->extd[XGBE_SFP_BASE_VENDOR_SN], 1218 XGBE_SFP_BASE_VENDOR_SN_LEN); 1219 sfp_data[XGBE_SFP_BASE_VENDOR_SN_LEN] = '\0'; 1220 netif_dbg(pdata, drv, pdata->netdev, " serial number: %s\n", 1221 sfp_data); 1222 } 1223 1224 static bool xgbe_phy_sfp_verify_eeprom(u8 cc_in, u8 *buf, unsigned int len) 1225 { 1226 u8 cc; 1227 1228 for (cc = 0; len; buf++, len--) 1229 cc += *buf; 1230 1231 return cc == cc_in; 1232 } 1233 1234 static int xgbe_phy_sfp_read_eeprom(struct xgbe_prv_data *pdata) 1235 { 1236 struct xgbe_phy_data *phy_data = pdata->phy_data; 1237 struct xgbe_sfp_eeprom sfp_eeprom; 1238 u8 eeprom_addr; 1239 int ret; 1240 1241 ret = xgbe_phy_sfp_get_mux(pdata); 1242 if (ret) { 1243 dev_err_once(pdata->dev, "%s: I2C error setting SFP MUX\n", 1244 netdev_name(pdata->netdev)); 1245 return ret; 1246 } 1247 1248 /* Read the SFP serial ID eeprom */ 1249 eeprom_addr = 0; 1250 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS, 1251 &eeprom_addr, sizeof(eeprom_addr), 1252 &sfp_eeprom, sizeof(sfp_eeprom)); 1253 if (ret) { 1254 dev_err_once(pdata->dev, "%s: I2C error reading SFP EEPROM\n", 1255 netdev_name(pdata->netdev)); 1256 goto put; 1257 } 1258 1259 /* Validate the contents read */ 1260 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.base[XGBE_SFP_BASE_CC], 1261 sfp_eeprom.base, 1262 sizeof(sfp_eeprom.base) - 1)) { 1263 ret = -EINVAL; 1264 goto put; 1265 } 1266 1267 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.extd[XGBE_SFP_EXTD_CC], 1268 sfp_eeprom.extd, 1269 sizeof(sfp_eeprom.extd) - 1)) { 1270 ret = -EINVAL; 1271 goto put; 1272 } 1273 1274 /* Check for an added or changed SFP */ 1275 if (memcmp(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom))) { 1276 phy_data->sfp_changed = 1; 1277 1278 if (netif_msg_drv(pdata)) 1279 xgbe_phy_sfp_eeprom_info(pdata, &sfp_eeprom); 1280 1281 memcpy(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom)); 1282 1283 xgbe_phy_free_phy_device(pdata); 1284 } else { 1285 phy_data->sfp_changed = 0; 1286 } 1287 1288 put: 1289 xgbe_phy_sfp_put_mux(pdata); 1290 1291 return ret; 1292 } 1293 1294 static void xgbe_phy_sfp_signals(struct xgbe_prv_data *pdata) 1295 { 1296 struct xgbe_phy_data *phy_data = pdata->phy_data; 1297 u8 gpio_reg, gpio_ports[2]; 1298 int ret; 1299 1300 /* Read the input port registers */ 1301 gpio_reg = 0; 1302 ret = xgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address, 1303 &gpio_reg, sizeof(gpio_reg), 1304 gpio_ports, sizeof(gpio_ports)); 1305 if (ret) { 1306 dev_err_once(pdata->dev, "%s: I2C error reading SFP GPIOs\n", 1307 netdev_name(pdata->netdev)); 1308 return; 1309 } 1310 1311 phy_data->sfp_gpio_inputs = (gpio_ports[1] << 8) | gpio_ports[0]; 1312 1313 phy_data->sfp_mod_absent = xgbe_phy_check_sfp_mod_absent(phy_data); 1314 } 1315 1316 static void xgbe_phy_sfp_mod_absent(struct xgbe_prv_data *pdata) 1317 { 1318 struct xgbe_phy_data *phy_data = pdata->phy_data; 1319 1320 xgbe_phy_free_phy_device(pdata); 1321 1322 phy_data->sfp_mod_absent = 1; 1323 phy_data->sfp_phy_avail = 0; 1324 memset(&phy_data->sfp_eeprom, 0, sizeof(phy_data->sfp_eeprom)); 1325 } 1326 1327 static void xgbe_phy_sfp_reset(struct xgbe_phy_data *phy_data) 1328 { 1329 phy_data->sfp_rx_los = 0; 1330 phy_data->sfp_tx_fault = 0; 1331 phy_data->sfp_mod_absent = 1; 1332 phy_data->sfp_base = XGBE_SFP_BASE_UNKNOWN; 1333 phy_data->sfp_cable = XGBE_SFP_CABLE_UNKNOWN; 1334 phy_data->sfp_speed = XGBE_SFP_SPEED_UNKNOWN; 1335 } 1336 1337 static void xgbe_phy_sfp_detect(struct xgbe_prv_data *pdata) 1338 { 1339 struct xgbe_phy_data *phy_data = pdata->phy_data; 1340 int ret; 1341 1342 /* Reset the SFP signals and info */ 1343 xgbe_phy_sfp_reset(phy_data); 1344 1345 ret = xgbe_phy_get_comm_ownership(pdata); 1346 if (ret) 1347 return; 1348 1349 /* Read the SFP signals and check for module presence */ 1350 xgbe_phy_sfp_signals(pdata); 1351 if (phy_data->sfp_mod_absent) { 1352 xgbe_phy_sfp_mod_absent(pdata); 1353 goto put; 1354 } 1355 1356 ret = xgbe_phy_sfp_read_eeprom(pdata); 1357 if (ret) { 1358 /* Treat any error as if there isn't an SFP plugged in */ 1359 xgbe_phy_sfp_reset(phy_data); 1360 xgbe_phy_sfp_mod_absent(pdata); 1361 goto put; 1362 } 1363 1364 xgbe_phy_sfp_parse_eeprom(pdata); 1365 1366 xgbe_phy_sfp_external_phy(pdata); 1367 1368 put: 1369 xgbe_phy_sfp_phy_settings(pdata); 1370 1371 xgbe_phy_put_comm_ownership(pdata); 1372 } 1373 1374 static int xgbe_phy_module_eeprom(struct xgbe_prv_data *pdata, 1375 struct ethtool_eeprom *eeprom, u8 *data) 1376 { 1377 struct xgbe_phy_data *phy_data = pdata->phy_data; 1378 u8 eeprom_addr, eeprom_data[XGBE_SFP_EEPROM_MAX]; 1379 struct xgbe_sfp_eeprom *sfp_eeprom; 1380 unsigned int i, j, rem; 1381 int ret; 1382 1383 rem = eeprom->len; 1384 1385 if (!eeprom->len) { 1386 ret = -EINVAL; 1387 goto done; 1388 } 1389 1390 if ((eeprom->offset + eeprom->len) > XGBE_SFP_EEPROM_MAX) { 1391 ret = -EINVAL; 1392 goto done; 1393 } 1394 1395 if (phy_data->port_mode != XGBE_PORT_MODE_SFP) { 1396 ret = -ENXIO; 1397 goto done; 1398 } 1399 1400 if (!netif_running(pdata->netdev)) { 1401 ret = -EIO; 1402 goto done; 1403 } 1404 1405 if (phy_data->sfp_mod_absent) { 1406 ret = -EIO; 1407 goto done; 1408 } 1409 1410 ret = xgbe_phy_get_comm_ownership(pdata); 1411 if (ret) { 1412 ret = -EIO; 1413 goto done; 1414 } 1415 1416 ret = xgbe_phy_sfp_get_mux(pdata); 1417 if (ret) { 1418 netdev_err(pdata->netdev, "I2C error setting SFP MUX\n"); 1419 ret = -EIO; 1420 goto put_own; 1421 } 1422 1423 /* Read the SFP serial ID eeprom */ 1424 eeprom_addr = 0; 1425 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS, 1426 &eeprom_addr, sizeof(eeprom_addr), 1427 eeprom_data, XGBE_SFP_EEPROM_BASE_LEN); 1428 if (ret) { 1429 netdev_err(pdata->netdev, 1430 "I2C error reading SFP EEPROM\n"); 1431 ret = -EIO; 1432 goto put_mux; 1433 } 1434 1435 sfp_eeprom = (struct xgbe_sfp_eeprom *)eeprom_data; 1436 1437 if (XGBE_SFP_DIAGS_SUPPORTED(sfp_eeprom)) { 1438 /* Read the SFP diagnostic eeprom */ 1439 eeprom_addr = 0; 1440 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_DIAG_INFO_ADDRESS, 1441 &eeprom_addr, sizeof(eeprom_addr), 1442 eeprom_data + XGBE_SFP_EEPROM_BASE_LEN, 1443 XGBE_SFP_EEPROM_DIAG_LEN); 1444 if (ret) { 1445 netdev_err(pdata->netdev, 1446 "I2C error reading SFP DIAGS\n"); 1447 ret = -EIO; 1448 goto put_mux; 1449 } 1450 } 1451 1452 for (i = 0, j = eeprom->offset; i < eeprom->len; i++, j++) { 1453 if ((j >= XGBE_SFP_EEPROM_BASE_LEN) && 1454 !XGBE_SFP_DIAGS_SUPPORTED(sfp_eeprom)) 1455 break; 1456 1457 data[i] = eeprom_data[j]; 1458 rem--; 1459 } 1460 1461 put_mux: 1462 xgbe_phy_sfp_put_mux(pdata); 1463 1464 put_own: 1465 xgbe_phy_put_comm_ownership(pdata); 1466 1467 done: 1468 eeprom->len -= rem; 1469 1470 return ret; 1471 } 1472 1473 static int xgbe_phy_module_info(struct xgbe_prv_data *pdata, 1474 struct ethtool_modinfo *modinfo) 1475 { 1476 struct xgbe_phy_data *phy_data = pdata->phy_data; 1477 1478 if (phy_data->port_mode != XGBE_PORT_MODE_SFP) 1479 return -ENXIO; 1480 1481 if (!netif_running(pdata->netdev)) 1482 return -EIO; 1483 1484 if (phy_data->sfp_mod_absent) 1485 return -EIO; 1486 1487 if (XGBE_SFP_DIAGS_SUPPORTED(&phy_data->sfp_eeprom)) { 1488 modinfo->type = ETH_MODULE_SFF_8472; 1489 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 1490 } else { 1491 modinfo->type = ETH_MODULE_SFF_8079; 1492 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN; 1493 } 1494 1495 return 0; 1496 } 1497 1498 static void xgbe_phy_phydev_flowctrl(struct xgbe_prv_data *pdata) 1499 { 1500 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1501 struct xgbe_phy_data *phy_data = pdata->phy_data; 1502 u16 lcl_adv = 0, rmt_adv = 0; 1503 u8 fc; 1504 1505 pdata->phy.tx_pause = 0; 1506 pdata->phy.rx_pause = 0; 1507 1508 if (!phy_data->phydev) 1509 return; 1510 1511 lcl_adv = linkmode_adv_to_lcl_adv_t(phy_data->phydev->advertising); 1512 1513 if (phy_data->phydev->pause) { 1514 XGBE_SET_LP_ADV(lks, Pause); 1515 rmt_adv |= LPA_PAUSE_CAP; 1516 } 1517 if (phy_data->phydev->asym_pause) { 1518 XGBE_SET_LP_ADV(lks, Asym_Pause); 1519 rmt_adv |= LPA_PAUSE_ASYM; 1520 } 1521 1522 fc = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); 1523 if (fc & FLOW_CTRL_TX) 1524 pdata->phy.tx_pause = 1; 1525 if (fc & FLOW_CTRL_RX) 1526 pdata->phy.rx_pause = 1; 1527 } 1528 1529 static enum xgbe_mode xgbe_phy_an37_sgmii_outcome(struct xgbe_prv_data *pdata) 1530 { 1531 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1532 enum xgbe_mode mode; 1533 1534 XGBE_SET_LP_ADV(lks, Autoneg); 1535 XGBE_SET_LP_ADV(lks, TP); 1536 1537 /* Use external PHY to determine flow control */ 1538 if (pdata->phy.pause_autoneg) 1539 xgbe_phy_phydev_flowctrl(pdata); 1540 1541 switch (pdata->an_status & XGBE_SGMII_AN_LINK_SPEED) { 1542 case XGBE_SGMII_AN_LINK_SPEED_100: 1543 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) { 1544 XGBE_SET_LP_ADV(lks, 100baseT_Full); 1545 mode = XGBE_MODE_SGMII_100; 1546 } else { 1547 /* Half-duplex not supported */ 1548 XGBE_SET_LP_ADV(lks, 100baseT_Half); 1549 mode = XGBE_MODE_UNKNOWN; 1550 } 1551 break; 1552 case XGBE_SGMII_AN_LINK_SPEED_1000: 1553 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) { 1554 XGBE_SET_LP_ADV(lks, 1000baseT_Full); 1555 mode = XGBE_MODE_SGMII_1000; 1556 } else { 1557 /* Half-duplex not supported */ 1558 XGBE_SET_LP_ADV(lks, 1000baseT_Half); 1559 mode = XGBE_MODE_UNKNOWN; 1560 } 1561 break; 1562 default: 1563 mode = XGBE_MODE_UNKNOWN; 1564 } 1565 1566 return mode; 1567 } 1568 1569 static enum xgbe_mode xgbe_phy_an37_outcome(struct xgbe_prv_data *pdata) 1570 { 1571 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1572 enum xgbe_mode mode; 1573 unsigned int ad_reg, lp_reg; 1574 1575 XGBE_SET_LP_ADV(lks, Autoneg); 1576 XGBE_SET_LP_ADV(lks, FIBRE); 1577 1578 /* Compare Advertisement and Link Partner register */ 1579 ad_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE); 1580 lp_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_LP_ABILITY); 1581 if (lp_reg & 0x100) 1582 XGBE_SET_LP_ADV(lks, Pause); 1583 if (lp_reg & 0x80) 1584 XGBE_SET_LP_ADV(lks, Asym_Pause); 1585 1586 if (pdata->phy.pause_autoneg) { 1587 /* Set flow control based on auto-negotiation result */ 1588 pdata->phy.tx_pause = 0; 1589 pdata->phy.rx_pause = 0; 1590 1591 if (ad_reg & lp_reg & 0x100) { 1592 pdata->phy.tx_pause = 1; 1593 pdata->phy.rx_pause = 1; 1594 } else if (ad_reg & lp_reg & 0x80) { 1595 if (ad_reg & 0x100) 1596 pdata->phy.rx_pause = 1; 1597 else if (lp_reg & 0x100) 1598 pdata->phy.tx_pause = 1; 1599 } 1600 } 1601 1602 if (lp_reg & 0x20) 1603 XGBE_SET_LP_ADV(lks, 1000baseX_Full); 1604 1605 /* Half duplex is not supported */ 1606 ad_reg &= lp_reg; 1607 mode = (ad_reg & 0x20) ? XGBE_MODE_X : XGBE_MODE_UNKNOWN; 1608 1609 return mode; 1610 } 1611 1612 static enum xgbe_mode xgbe_phy_an73_redrv_outcome(struct xgbe_prv_data *pdata) 1613 { 1614 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1615 struct xgbe_phy_data *phy_data = pdata->phy_data; 1616 enum xgbe_mode mode; 1617 unsigned int ad_reg, lp_reg; 1618 1619 XGBE_SET_LP_ADV(lks, Autoneg); 1620 XGBE_SET_LP_ADV(lks, Backplane); 1621 1622 /* Use external PHY to determine flow control */ 1623 if (pdata->phy.pause_autoneg) 1624 xgbe_phy_phydev_flowctrl(pdata); 1625 1626 /* Compare Advertisement and Link Partner register 2 */ 1627 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); 1628 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); 1629 if (lp_reg & 0x80) 1630 XGBE_SET_LP_ADV(lks, 10000baseKR_Full); 1631 if (lp_reg & 0x20) 1632 XGBE_SET_LP_ADV(lks, 1000baseKX_Full); 1633 1634 ad_reg &= lp_reg; 1635 if (ad_reg & 0x80) { 1636 switch (phy_data->port_mode) { 1637 case XGBE_PORT_MODE_BACKPLANE: 1638 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 1639 mode = XGBE_MODE_KR; 1640 break; 1641 default: 1642 mode = XGBE_MODE_SFI; 1643 break; 1644 } 1645 } else if (ad_reg & 0x20) { 1646 switch (phy_data->port_mode) { 1647 case XGBE_PORT_MODE_BACKPLANE: 1648 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 1649 mode = XGBE_MODE_KX_1000; 1650 break; 1651 case XGBE_PORT_MODE_1000BASE_X: 1652 mode = XGBE_MODE_X; 1653 break; 1654 case XGBE_PORT_MODE_SFP: 1655 switch (phy_data->sfp_base) { 1656 case XGBE_SFP_BASE_1000_T: 1657 if (phy_data->phydev && 1658 (phy_data->phydev->speed == SPEED_100)) 1659 mode = XGBE_MODE_SGMII_100; 1660 else 1661 mode = XGBE_MODE_SGMII_1000; 1662 break; 1663 case XGBE_SFP_BASE_1000_SX: 1664 case XGBE_SFP_BASE_1000_LX: 1665 case XGBE_SFP_BASE_1000_CX: 1666 default: 1667 mode = XGBE_MODE_X; 1668 break; 1669 } 1670 break; 1671 default: 1672 if (phy_data->phydev && 1673 (phy_data->phydev->speed == SPEED_100)) 1674 mode = XGBE_MODE_SGMII_100; 1675 else 1676 mode = XGBE_MODE_SGMII_1000; 1677 break; 1678 } 1679 } else { 1680 mode = XGBE_MODE_UNKNOWN; 1681 } 1682 1683 /* Compare Advertisement and Link Partner register 3 */ 1684 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); 1685 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); 1686 if (lp_reg & 0xc000) 1687 XGBE_SET_LP_ADV(lks, 10000baseR_FEC); 1688 1689 return mode; 1690 } 1691 1692 static enum xgbe_mode xgbe_phy_an73_outcome(struct xgbe_prv_data *pdata) 1693 { 1694 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1695 enum xgbe_mode mode; 1696 unsigned int ad_reg, lp_reg; 1697 1698 XGBE_SET_LP_ADV(lks, Autoneg); 1699 XGBE_SET_LP_ADV(lks, Backplane); 1700 1701 /* Compare Advertisement and Link Partner register 1 */ 1702 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE); 1703 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA); 1704 if (lp_reg & 0x400) 1705 XGBE_SET_LP_ADV(lks, Pause); 1706 if (lp_reg & 0x800) 1707 XGBE_SET_LP_ADV(lks, Asym_Pause); 1708 1709 if (pdata->phy.pause_autoneg) { 1710 /* Set flow control based on auto-negotiation result */ 1711 pdata->phy.tx_pause = 0; 1712 pdata->phy.rx_pause = 0; 1713 1714 if (ad_reg & lp_reg & 0x400) { 1715 pdata->phy.tx_pause = 1; 1716 pdata->phy.rx_pause = 1; 1717 } else if (ad_reg & lp_reg & 0x800) { 1718 if (ad_reg & 0x400) 1719 pdata->phy.rx_pause = 1; 1720 else if (lp_reg & 0x400) 1721 pdata->phy.tx_pause = 1; 1722 } 1723 } 1724 1725 /* Compare Advertisement and Link Partner register 2 */ 1726 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); 1727 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); 1728 if (lp_reg & 0x80) 1729 XGBE_SET_LP_ADV(lks, 10000baseKR_Full); 1730 if (lp_reg & 0x20) 1731 XGBE_SET_LP_ADV(lks, 1000baseKX_Full); 1732 1733 ad_reg &= lp_reg; 1734 if (ad_reg & 0x80) 1735 mode = XGBE_MODE_KR; 1736 else if (ad_reg & 0x20) 1737 mode = XGBE_MODE_KX_1000; 1738 else 1739 mode = XGBE_MODE_UNKNOWN; 1740 1741 /* Compare Advertisement and Link Partner register 3 */ 1742 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); 1743 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); 1744 if (lp_reg & 0xc000) 1745 XGBE_SET_LP_ADV(lks, 10000baseR_FEC); 1746 1747 return mode; 1748 } 1749 1750 static enum xgbe_mode xgbe_phy_an_outcome(struct xgbe_prv_data *pdata) 1751 { 1752 switch (pdata->an_mode) { 1753 case XGBE_AN_MODE_CL73: 1754 return xgbe_phy_an73_outcome(pdata); 1755 case XGBE_AN_MODE_CL73_REDRV: 1756 return xgbe_phy_an73_redrv_outcome(pdata); 1757 case XGBE_AN_MODE_CL37: 1758 return xgbe_phy_an37_outcome(pdata); 1759 case XGBE_AN_MODE_CL37_SGMII: 1760 return xgbe_phy_an37_sgmii_outcome(pdata); 1761 default: 1762 return XGBE_MODE_UNKNOWN; 1763 } 1764 } 1765 1766 static void xgbe_phy_an_advertising(struct xgbe_prv_data *pdata, 1767 struct ethtool_link_ksettings *dlks) 1768 { 1769 struct ethtool_link_ksettings *slks = &pdata->phy.lks; 1770 struct xgbe_phy_data *phy_data = pdata->phy_data; 1771 1772 XGBE_LM_COPY(dlks, advertising, slks, advertising); 1773 1774 /* Without a re-driver, just return current advertising */ 1775 if (!phy_data->redrv) 1776 return; 1777 1778 /* With the KR re-driver we need to advertise a single speed */ 1779 XGBE_CLR_ADV(dlks, 1000baseKX_Full); 1780 XGBE_CLR_ADV(dlks, 10000baseKR_Full); 1781 1782 /* Advertise FEC support is present */ 1783 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 1784 XGBE_SET_ADV(dlks, 10000baseR_FEC); 1785 1786 switch (phy_data->port_mode) { 1787 case XGBE_PORT_MODE_BACKPLANE: 1788 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 1789 XGBE_SET_ADV(dlks, 10000baseKR_Full); 1790 break; 1791 case XGBE_PORT_MODE_BACKPLANE_2500: 1792 XGBE_SET_ADV(dlks, 1000baseKX_Full); 1793 break; 1794 case XGBE_PORT_MODE_1000BASE_T: 1795 case XGBE_PORT_MODE_1000BASE_X: 1796 case XGBE_PORT_MODE_NBASE_T: 1797 XGBE_SET_ADV(dlks, 1000baseKX_Full); 1798 break; 1799 case XGBE_PORT_MODE_10GBASE_T: 1800 if (phy_data->phydev && 1801 (phy_data->phydev->speed == SPEED_10000)) 1802 XGBE_SET_ADV(dlks, 10000baseKR_Full); 1803 else 1804 XGBE_SET_ADV(dlks, 1000baseKX_Full); 1805 break; 1806 case XGBE_PORT_MODE_10GBASE_R: 1807 XGBE_SET_ADV(dlks, 10000baseKR_Full); 1808 break; 1809 case XGBE_PORT_MODE_SFP: 1810 switch (phy_data->sfp_base) { 1811 case XGBE_SFP_BASE_1000_T: 1812 case XGBE_SFP_BASE_1000_SX: 1813 case XGBE_SFP_BASE_1000_LX: 1814 case XGBE_SFP_BASE_1000_CX: 1815 XGBE_SET_ADV(dlks, 1000baseKX_Full); 1816 break; 1817 default: 1818 XGBE_SET_ADV(dlks, 10000baseKR_Full); 1819 break; 1820 } 1821 break; 1822 default: 1823 XGBE_SET_ADV(dlks, 10000baseKR_Full); 1824 break; 1825 } 1826 } 1827 1828 static int xgbe_phy_an_config(struct xgbe_prv_data *pdata) 1829 { 1830 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1831 struct xgbe_phy_data *phy_data = pdata->phy_data; 1832 int ret; 1833 1834 ret = xgbe_phy_find_phy_device(pdata); 1835 if (ret) 1836 return ret; 1837 1838 if (!phy_data->phydev) 1839 return 0; 1840 1841 phy_data->phydev->autoneg = pdata->phy.autoneg; 1842 linkmode_and(phy_data->phydev->advertising, 1843 phy_data->phydev->supported, 1844 lks->link_modes.advertising); 1845 1846 if (pdata->phy.autoneg != AUTONEG_ENABLE) { 1847 phy_data->phydev->speed = pdata->phy.speed; 1848 phy_data->phydev->duplex = pdata->phy.duplex; 1849 } 1850 1851 ret = phy_start_aneg(phy_data->phydev); 1852 1853 return ret; 1854 } 1855 1856 static enum xgbe_an_mode xgbe_phy_an_sfp_mode(struct xgbe_phy_data *phy_data) 1857 { 1858 switch (phy_data->sfp_base) { 1859 case XGBE_SFP_BASE_1000_T: 1860 return XGBE_AN_MODE_CL37_SGMII; 1861 case XGBE_SFP_BASE_1000_SX: 1862 case XGBE_SFP_BASE_1000_LX: 1863 case XGBE_SFP_BASE_1000_CX: 1864 return XGBE_AN_MODE_CL37; 1865 default: 1866 return XGBE_AN_MODE_NONE; 1867 } 1868 } 1869 1870 static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata) 1871 { 1872 struct xgbe_phy_data *phy_data = pdata->phy_data; 1873 1874 /* A KR re-driver will always require CL73 AN */ 1875 if (phy_data->redrv) 1876 return XGBE_AN_MODE_CL73_REDRV; 1877 1878 switch (phy_data->port_mode) { 1879 case XGBE_PORT_MODE_BACKPLANE: 1880 return XGBE_AN_MODE_CL73; 1881 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 1882 case XGBE_PORT_MODE_BACKPLANE_2500: 1883 return XGBE_AN_MODE_NONE; 1884 case XGBE_PORT_MODE_1000BASE_T: 1885 return XGBE_AN_MODE_CL37_SGMII; 1886 case XGBE_PORT_MODE_1000BASE_X: 1887 return XGBE_AN_MODE_CL37; 1888 case XGBE_PORT_MODE_NBASE_T: 1889 return XGBE_AN_MODE_CL37_SGMII; 1890 case XGBE_PORT_MODE_10GBASE_T: 1891 return XGBE_AN_MODE_CL73; 1892 case XGBE_PORT_MODE_10GBASE_R: 1893 return XGBE_AN_MODE_NONE; 1894 case XGBE_PORT_MODE_SFP: 1895 return xgbe_phy_an_sfp_mode(phy_data); 1896 default: 1897 return XGBE_AN_MODE_NONE; 1898 } 1899 } 1900 1901 static int xgbe_phy_set_redrv_mode_mdio(struct xgbe_prv_data *pdata, 1902 enum xgbe_phy_redrv_mode mode) 1903 { 1904 struct xgbe_phy_data *phy_data = pdata->phy_data; 1905 u16 redrv_reg, redrv_val; 1906 1907 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000); 1908 redrv_val = (u16)mode; 1909 1910 return pdata->hw_if.write_ext_mii_regs(pdata, phy_data->redrv_addr, 1911 redrv_reg, redrv_val); 1912 } 1913 1914 static int xgbe_phy_set_redrv_mode_i2c(struct xgbe_prv_data *pdata, 1915 enum xgbe_phy_redrv_mode mode) 1916 { 1917 struct xgbe_phy_data *phy_data = pdata->phy_data; 1918 unsigned int redrv_reg; 1919 int ret; 1920 1921 /* Calculate the register to write */ 1922 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000); 1923 1924 ret = xgbe_phy_redrv_write(pdata, redrv_reg, mode); 1925 1926 return ret; 1927 } 1928 1929 static void xgbe_phy_set_redrv_mode(struct xgbe_prv_data *pdata) 1930 { 1931 struct xgbe_phy_data *phy_data = pdata->phy_data; 1932 enum xgbe_phy_redrv_mode mode; 1933 int ret; 1934 1935 if (!phy_data->redrv) 1936 return; 1937 1938 mode = XGBE_PHY_REDRV_MODE_CX; 1939 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) && 1940 (phy_data->sfp_base != XGBE_SFP_BASE_1000_CX) && 1941 (phy_data->sfp_base != XGBE_SFP_BASE_10000_CR)) 1942 mode = XGBE_PHY_REDRV_MODE_SR; 1943 1944 ret = xgbe_phy_get_comm_ownership(pdata); 1945 if (ret) 1946 return; 1947 1948 if (phy_data->redrv_if) 1949 xgbe_phy_set_redrv_mode_i2c(pdata, mode); 1950 else 1951 xgbe_phy_set_redrv_mode_mdio(pdata, mode); 1952 1953 xgbe_phy_put_comm_ownership(pdata); 1954 } 1955 1956 static void xgbe_phy_perform_ratechange(struct xgbe_prv_data *pdata, 1957 unsigned int cmd, unsigned int sub_cmd) 1958 { 1959 unsigned int s0 = 0; 1960 unsigned int wait; 1961 1962 /* Log if a previous command did not complete */ 1963 if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) 1964 netif_dbg(pdata, link, pdata->netdev, 1965 "firmware mailbox not ready for command\n"); 1966 1967 /* Construct the command */ 1968 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, cmd); 1969 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, sub_cmd); 1970 1971 /* Issue the command */ 1972 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0); 1973 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0); 1974 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1); 1975 1976 /* Wait for command to complete */ 1977 wait = XGBE_RATECHANGE_COUNT; 1978 while (wait--) { 1979 if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) 1980 return; 1981 1982 usleep_range(1000, 2000); 1983 } 1984 1985 netif_dbg(pdata, link, pdata->netdev, 1986 "firmware mailbox command did not complete\n"); 1987 } 1988 1989 static void xgbe_phy_rrc(struct xgbe_prv_data *pdata) 1990 { 1991 /* Receiver Reset Cycle */ 1992 xgbe_phy_perform_ratechange(pdata, 5, 0); 1993 1994 netif_dbg(pdata, link, pdata->netdev, "receiver reset complete\n"); 1995 } 1996 1997 static void xgbe_phy_power_off(struct xgbe_prv_data *pdata) 1998 { 1999 struct xgbe_phy_data *phy_data = pdata->phy_data; 2000 2001 /* Power off */ 2002 xgbe_phy_perform_ratechange(pdata, 0, 0); 2003 2004 phy_data->cur_mode = XGBE_MODE_UNKNOWN; 2005 2006 netif_dbg(pdata, link, pdata->netdev, "phy powered off\n"); 2007 } 2008 2009 static void xgbe_phy_sfi_mode(struct xgbe_prv_data *pdata) 2010 { 2011 struct xgbe_phy_data *phy_data = pdata->phy_data; 2012 2013 xgbe_phy_set_redrv_mode(pdata); 2014 2015 /* 10G/SFI */ 2016 if (phy_data->sfp_cable != XGBE_SFP_CABLE_PASSIVE) { 2017 xgbe_phy_perform_ratechange(pdata, 3, 0); 2018 } else { 2019 if (phy_data->sfp_cable_len <= 1) 2020 xgbe_phy_perform_ratechange(pdata, 3, 1); 2021 else if (phy_data->sfp_cable_len <= 3) 2022 xgbe_phy_perform_ratechange(pdata, 3, 2); 2023 else 2024 xgbe_phy_perform_ratechange(pdata, 3, 3); 2025 } 2026 2027 phy_data->cur_mode = XGBE_MODE_SFI; 2028 2029 netif_dbg(pdata, link, pdata->netdev, "10GbE SFI mode set\n"); 2030 } 2031 2032 static void xgbe_phy_x_mode(struct xgbe_prv_data *pdata) 2033 { 2034 struct xgbe_phy_data *phy_data = pdata->phy_data; 2035 2036 xgbe_phy_set_redrv_mode(pdata); 2037 2038 /* 1G/X */ 2039 xgbe_phy_perform_ratechange(pdata, 1, 3); 2040 2041 phy_data->cur_mode = XGBE_MODE_X; 2042 2043 netif_dbg(pdata, link, pdata->netdev, "1GbE X mode set\n"); 2044 } 2045 2046 static void xgbe_phy_sgmii_1000_mode(struct xgbe_prv_data *pdata) 2047 { 2048 struct xgbe_phy_data *phy_data = pdata->phy_data; 2049 2050 xgbe_phy_set_redrv_mode(pdata); 2051 2052 /* 1G/SGMII */ 2053 xgbe_phy_perform_ratechange(pdata, 1, 2); 2054 2055 phy_data->cur_mode = XGBE_MODE_SGMII_1000; 2056 2057 netif_dbg(pdata, link, pdata->netdev, "1GbE SGMII mode set\n"); 2058 } 2059 2060 static void xgbe_phy_sgmii_100_mode(struct xgbe_prv_data *pdata) 2061 { 2062 struct xgbe_phy_data *phy_data = pdata->phy_data; 2063 2064 xgbe_phy_set_redrv_mode(pdata); 2065 2066 /* 100M/SGMII */ 2067 xgbe_phy_perform_ratechange(pdata, 1, 1); 2068 2069 phy_data->cur_mode = XGBE_MODE_SGMII_100; 2070 2071 netif_dbg(pdata, link, pdata->netdev, "100MbE SGMII mode set\n"); 2072 } 2073 2074 static void xgbe_phy_kr_mode(struct xgbe_prv_data *pdata) 2075 { 2076 struct xgbe_phy_data *phy_data = pdata->phy_data; 2077 2078 xgbe_phy_set_redrv_mode(pdata); 2079 2080 /* 10G/KR */ 2081 xgbe_phy_perform_ratechange(pdata, 4, 0); 2082 2083 phy_data->cur_mode = XGBE_MODE_KR; 2084 2085 netif_dbg(pdata, link, pdata->netdev, "10GbE KR mode set\n"); 2086 } 2087 2088 static void xgbe_phy_kx_2500_mode(struct xgbe_prv_data *pdata) 2089 { 2090 struct xgbe_phy_data *phy_data = pdata->phy_data; 2091 2092 xgbe_phy_set_redrv_mode(pdata); 2093 2094 /* 2.5G/KX */ 2095 xgbe_phy_perform_ratechange(pdata, 2, 0); 2096 2097 phy_data->cur_mode = XGBE_MODE_KX_2500; 2098 2099 netif_dbg(pdata, link, pdata->netdev, "2.5GbE KX mode set\n"); 2100 } 2101 2102 static void xgbe_phy_kx_1000_mode(struct xgbe_prv_data *pdata) 2103 { 2104 struct xgbe_phy_data *phy_data = pdata->phy_data; 2105 2106 xgbe_phy_set_redrv_mode(pdata); 2107 2108 /* 1G/KX */ 2109 xgbe_phy_perform_ratechange(pdata, 1, 3); 2110 2111 phy_data->cur_mode = XGBE_MODE_KX_1000; 2112 2113 netif_dbg(pdata, link, pdata->netdev, "1GbE KX mode set\n"); 2114 } 2115 2116 static enum xgbe_mode xgbe_phy_cur_mode(struct xgbe_prv_data *pdata) 2117 { 2118 struct xgbe_phy_data *phy_data = pdata->phy_data; 2119 2120 return phy_data->cur_mode; 2121 } 2122 2123 static enum xgbe_mode xgbe_phy_switch_baset_mode(struct xgbe_prv_data *pdata) 2124 { 2125 struct xgbe_phy_data *phy_data = pdata->phy_data; 2126 2127 /* No switching if not 10GBase-T */ 2128 if (phy_data->port_mode != XGBE_PORT_MODE_10GBASE_T) 2129 return xgbe_phy_cur_mode(pdata); 2130 2131 switch (xgbe_phy_cur_mode(pdata)) { 2132 case XGBE_MODE_SGMII_100: 2133 case XGBE_MODE_SGMII_1000: 2134 return XGBE_MODE_KR; 2135 case XGBE_MODE_KR: 2136 default: 2137 return XGBE_MODE_SGMII_1000; 2138 } 2139 } 2140 2141 static enum xgbe_mode xgbe_phy_switch_bp_2500_mode(struct xgbe_prv_data *pdata) 2142 { 2143 return XGBE_MODE_KX_2500; 2144 } 2145 2146 static enum xgbe_mode xgbe_phy_switch_bp_mode(struct xgbe_prv_data *pdata) 2147 { 2148 /* If we are in KR switch to KX, and vice-versa */ 2149 switch (xgbe_phy_cur_mode(pdata)) { 2150 case XGBE_MODE_KX_1000: 2151 return XGBE_MODE_KR; 2152 case XGBE_MODE_KR: 2153 default: 2154 return XGBE_MODE_KX_1000; 2155 } 2156 } 2157 2158 static enum xgbe_mode xgbe_phy_switch_mode(struct xgbe_prv_data *pdata) 2159 { 2160 struct xgbe_phy_data *phy_data = pdata->phy_data; 2161 2162 switch (phy_data->port_mode) { 2163 case XGBE_PORT_MODE_BACKPLANE: 2164 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 2165 return xgbe_phy_switch_bp_mode(pdata); 2166 case XGBE_PORT_MODE_BACKPLANE_2500: 2167 return xgbe_phy_switch_bp_2500_mode(pdata); 2168 case XGBE_PORT_MODE_1000BASE_T: 2169 case XGBE_PORT_MODE_NBASE_T: 2170 case XGBE_PORT_MODE_10GBASE_T: 2171 return xgbe_phy_switch_baset_mode(pdata); 2172 case XGBE_PORT_MODE_1000BASE_X: 2173 case XGBE_PORT_MODE_10GBASE_R: 2174 case XGBE_PORT_MODE_SFP: 2175 /* No switching, so just return current mode */ 2176 return xgbe_phy_cur_mode(pdata); 2177 default: 2178 return XGBE_MODE_UNKNOWN; 2179 } 2180 } 2181 2182 static enum xgbe_mode xgbe_phy_get_basex_mode(struct xgbe_phy_data *phy_data, 2183 int speed) 2184 { 2185 switch (speed) { 2186 case SPEED_1000: 2187 return XGBE_MODE_X; 2188 case SPEED_10000: 2189 return XGBE_MODE_KR; 2190 default: 2191 return XGBE_MODE_UNKNOWN; 2192 } 2193 } 2194 2195 static enum xgbe_mode xgbe_phy_get_baset_mode(struct xgbe_phy_data *phy_data, 2196 int speed) 2197 { 2198 switch (speed) { 2199 case SPEED_100: 2200 return XGBE_MODE_SGMII_100; 2201 case SPEED_1000: 2202 return XGBE_MODE_SGMII_1000; 2203 case SPEED_2500: 2204 return XGBE_MODE_KX_2500; 2205 case SPEED_10000: 2206 return XGBE_MODE_KR; 2207 default: 2208 return XGBE_MODE_UNKNOWN; 2209 } 2210 } 2211 2212 static enum xgbe_mode xgbe_phy_get_sfp_mode(struct xgbe_phy_data *phy_data, 2213 int speed) 2214 { 2215 switch (speed) { 2216 case SPEED_100: 2217 return XGBE_MODE_SGMII_100; 2218 case SPEED_1000: 2219 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T) 2220 return XGBE_MODE_SGMII_1000; 2221 else 2222 return XGBE_MODE_X; 2223 case SPEED_10000: 2224 case SPEED_UNKNOWN: 2225 return XGBE_MODE_SFI; 2226 default: 2227 return XGBE_MODE_UNKNOWN; 2228 } 2229 } 2230 2231 static enum xgbe_mode xgbe_phy_get_bp_2500_mode(int speed) 2232 { 2233 switch (speed) { 2234 case SPEED_2500: 2235 return XGBE_MODE_KX_2500; 2236 default: 2237 return XGBE_MODE_UNKNOWN; 2238 } 2239 } 2240 2241 static enum xgbe_mode xgbe_phy_get_bp_mode(int speed) 2242 { 2243 switch (speed) { 2244 case SPEED_1000: 2245 return XGBE_MODE_KX_1000; 2246 case SPEED_10000: 2247 return XGBE_MODE_KR; 2248 default: 2249 return XGBE_MODE_UNKNOWN; 2250 } 2251 } 2252 2253 static enum xgbe_mode xgbe_phy_get_mode(struct xgbe_prv_data *pdata, 2254 int speed) 2255 { 2256 struct xgbe_phy_data *phy_data = pdata->phy_data; 2257 2258 switch (phy_data->port_mode) { 2259 case XGBE_PORT_MODE_BACKPLANE: 2260 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 2261 return xgbe_phy_get_bp_mode(speed); 2262 case XGBE_PORT_MODE_BACKPLANE_2500: 2263 return xgbe_phy_get_bp_2500_mode(speed); 2264 case XGBE_PORT_MODE_1000BASE_T: 2265 case XGBE_PORT_MODE_NBASE_T: 2266 case XGBE_PORT_MODE_10GBASE_T: 2267 return xgbe_phy_get_baset_mode(phy_data, speed); 2268 case XGBE_PORT_MODE_1000BASE_X: 2269 case XGBE_PORT_MODE_10GBASE_R: 2270 return xgbe_phy_get_basex_mode(phy_data, speed); 2271 case XGBE_PORT_MODE_SFP: 2272 return xgbe_phy_get_sfp_mode(phy_data, speed); 2273 default: 2274 return XGBE_MODE_UNKNOWN; 2275 } 2276 } 2277 2278 static void xgbe_phy_set_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode) 2279 { 2280 switch (mode) { 2281 case XGBE_MODE_KX_1000: 2282 xgbe_phy_kx_1000_mode(pdata); 2283 break; 2284 case XGBE_MODE_KX_2500: 2285 xgbe_phy_kx_2500_mode(pdata); 2286 break; 2287 case XGBE_MODE_KR: 2288 xgbe_phy_kr_mode(pdata); 2289 break; 2290 case XGBE_MODE_SGMII_100: 2291 xgbe_phy_sgmii_100_mode(pdata); 2292 break; 2293 case XGBE_MODE_SGMII_1000: 2294 xgbe_phy_sgmii_1000_mode(pdata); 2295 break; 2296 case XGBE_MODE_X: 2297 xgbe_phy_x_mode(pdata); 2298 break; 2299 case XGBE_MODE_SFI: 2300 xgbe_phy_sfi_mode(pdata); 2301 break; 2302 default: 2303 break; 2304 } 2305 } 2306 2307 static bool xgbe_phy_check_mode(struct xgbe_prv_data *pdata, 2308 enum xgbe_mode mode, bool advert) 2309 { 2310 if (pdata->phy.autoneg == AUTONEG_ENABLE) { 2311 return advert; 2312 } else { 2313 enum xgbe_mode cur_mode; 2314 2315 cur_mode = xgbe_phy_get_mode(pdata, pdata->phy.speed); 2316 if (cur_mode == mode) 2317 return true; 2318 } 2319 2320 return false; 2321 } 2322 2323 static bool xgbe_phy_use_basex_mode(struct xgbe_prv_data *pdata, 2324 enum xgbe_mode mode) 2325 { 2326 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 2327 2328 switch (mode) { 2329 case XGBE_MODE_X: 2330 return xgbe_phy_check_mode(pdata, mode, 2331 XGBE_ADV(lks, 1000baseX_Full)); 2332 case XGBE_MODE_KR: 2333 return xgbe_phy_check_mode(pdata, mode, 2334 XGBE_ADV(lks, 10000baseKR_Full)); 2335 default: 2336 return false; 2337 } 2338 } 2339 2340 static bool xgbe_phy_use_baset_mode(struct xgbe_prv_data *pdata, 2341 enum xgbe_mode mode) 2342 { 2343 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 2344 2345 switch (mode) { 2346 case XGBE_MODE_SGMII_100: 2347 return xgbe_phy_check_mode(pdata, mode, 2348 XGBE_ADV(lks, 100baseT_Full)); 2349 case XGBE_MODE_SGMII_1000: 2350 return xgbe_phy_check_mode(pdata, mode, 2351 XGBE_ADV(lks, 1000baseT_Full)); 2352 case XGBE_MODE_KX_2500: 2353 return xgbe_phy_check_mode(pdata, mode, 2354 XGBE_ADV(lks, 2500baseT_Full)); 2355 case XGBE_MODE_KR: 2356 return xgbe_phy_check_mode(pdata, mode, 2357 XGBE_ADV(lks, 10000baseT_Full)); 2358 default: 2359 return false; 2360 } 2361 } 2362 2363 static bool xgbe_phy_use_sfp_mode(struct xgbe_prv_data *pdata, 2364 enum xgbe_mode mode) 2365 { 2366 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 2367 struct xgbe_phy_data *phy_data = pdata->phy_data; 2368 2369 switch (mode) { 2370 case XGBE_MODE_X: 2371 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T) 2372 return false; 2373 return xgbe_phy_check_mode(pdata, mode, 2374 XGBE_ADV(lks, 1000baseX_Full)); 2375 case XGBE_MODE_SGMII_100: 2376 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T) 2377 return false; 2378 return xgbe_phy_check_mode(pdata, mode, 2379 XGBE_ADV(lks, 100baseT_Full)); 2380 case XGBE_MODE_SGMII_1000: 2381 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T) 2382 return false; 2383 return xgbe_phy_check_mode(pdata, mode, 2384 XGBE_ADV(lks, 1000baseT_Full)); 2385 case XGBE_MODE_SFI: 2386 if (phy_data->sfp_mod_absent) 2387 return true; 2388 return xgbe_phy_check_mode(pdata, mode, 2389 XGBE_ADV(lks, 10000baseSR_Full) || 2390 XGBE_ADV(lks, 10000baseLR_Full) || 2391 XGBE_ADV(lks, 10000baseLRM_Full) || 2392 XGBE_ADV(lks, 10000baseER_Full) || 2393 XGBE_ADV(lks, 10000baseCR_Full)); 2394 default: 2395 return false; 2396 } 2397 } 2398 2399 static bool xgbe_phy_use_bp_2500_mode(struct xgbe_prv_data *pdata, 2400 enum xgbe_mode mode) 2401 { 2402 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 2403 2404 switch (mode) { 2405 case XGBE_MODE_KX_2500: 2406 return xgbe_phy_check_mode(pdata, mode, 2407 XGBE_ADV(lks, 2500baseX_Full)); 2408 default: 2409 return false; 2410 } 2411 } 2412 2413 static bool xgbe_phy_use_bp_mode(struct xgbe_prv_data *pdata, 2414 enum xgbe_mode mode) 2415 { 2416 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 2417 2418 switch (mode) { 2419 case XGBE_MODE_KX_1000: 2420 return xgbe_phy_check_mode(pdata, mode, 2421 XGBE_ADV(lks, 1000baseKX_Full)); 2422 case XGBE_MODE_KR: 2423 return xgbe_phy_check_mode(pdata, mode, 2424 XGBE_ADV(lks, 10000baseKR_Full)); 2425 default: 2426 return false; 2427 } 2428 } 2429 2430 static bool xgbe_phy_use_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode) 2431 { 2432 struct xgbe_phy_data *phy_data = pdata->phy_data; 2433 2434 switch (phy_data->port_mode) { 2435 case XGBE_PORT_MODE_BACKPLANE: 2436 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 2437 return xgbe_phy_use_bp_mode(pdata, mode); 2438 case XGBE_PORT_MODE_BACKPLANE_2500: 2439 return xgbe_phy_use_bp_2500_mode(pdata, mode); 2440 case XGBE_PORT_MODE_1000BASE_T: 2441 case XGBE_PORT_MODE_NBASE_T: 2442 case XGBE_PORT_MODE_10GBASE_T: 2443 return xgbe_phy_use_baset_mode(pdata, mode); 2444 case XGBE_PORT_MODE_1000BASE_X: 2445 case XGBE_PORT_MODE_10GBASE_R: 2446 return xgbe_phy_use_basex_mode(pdata, mode); 2447 case XGBE_PORT_MODE_SFP: 2448 return xgbe_phy_use_sfp_mode(pdata, mode); 2449 default: 2450 return false; 2451 } 2452 } 2453 2454 static bool xgbe_phy_valid_speed_basex_mode(struct xgbe_phy_data *phy_data, 2455 int speed) 2456 { 2457 switch (speed) { 2458 case SPEED_1000: 2459 return (phy_data->port_mode == XGBE_PORT_MODE_1000BASE_X); 2460 case SPEED_10000: 2461 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_R); 2462 default: 2463 return false; 2464 } 2465 } 2466 2467 static bool xgbe_phy_valid_speed_baset_mode(struct xgbe_phy_data *phy_data, 2468 int speed) 2469 { 2470 switch (speed) { 2471 case SPEED_100: 2472 case SPEED_1000: 2473 return true; 2474 case SPEED_2500: 2475 return (phy_data->port_mode == XGBE_PORT_MODE_NBASE_T); 2476 case SPEED_10000: 2477 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_T); 2478 default: 2479 return false; 2480 } 2481 } 2482 2483 static bool xgbe_phy_valid_speed_sfp_mode(struct xgbe_phy_data *phy_data, 2484 int speed) 2485 { 2486 switch (speed) { 2487 case SPEED_100: 2488 return (phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000); 2489 case SPEED_1000: 2490 return ((phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000) || 2491 (phy_data->sfp_speed == XGBE_SFP_SPEED_1000)); 2492 case SPEED_10000: 2493 return (phy_data->sfp_speed == XGBE_SFP_SPEED_10000); 2494 default: 2495 return false; 2496 } 2497 } 2498 2499 static bool xgbe_phy_valid_speed_bp_2500_mode(int speed) 2500 { 2501 switch (speed) { 2502 case SPEED_2500: 2503 return true; 2504 default: 2505 return false; 2506 } 2507 } 2508 2509 static bool xgbe_phy_valid_speed_bp_mode(int speed) 2510 { 2511 switch (speed) { 2512 case SPEED_1000: 2513 case SPEED_10000: 2514 return true; 2515 default: 2516 return false; 2517 } 2518 } 2519 2520 static bool xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed) 2521 { 2522 struct xgbe_phy_data *phy_data = pdata->phy_data; 2523 2524 switch (phy_data->port_mode) { 2525 case XGBE_PORT_MODE_BACKPLANE: 2526 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 2527 return xgbe_phy_valid_speed_bp_mode(speed); 2528 case XGBE_PORT_MODE_BACKPLANE_2500: 2529 return xgbe_phy_valid_speed_bp_2500_mode(speed); 2530 case XGBE_PORT_MODE_1000BASE_T: 2531 case XGBE_PORT_MODE_NBASE_T: 2532 case XGBE_PORT_MODE_10GBASE_T: 2533 return xgbe_phy_valid_speed_baset_mode(phy_data, speed); 2534 case XGBE_PORT_MODE_1000BASE_X: 2535 case XGBE_PORT_MODE_10GBASE_R: 2536 return xgbe_phy_valid_speed_basex_mode(phy_data, speed); 2537 case XGBE_PORT_MODE_SFP: 2538 return xgbe_phy_valid_speed_sfp_mode(phy_data, speed); 2539 default: 2540 return false; 2541 } 2542 } 2543 2544 static int xgbe_phy_link_status(struct xgbe_prv_data *pdata, int *an_restart) 2545 { 2546 struct xgbe_phy_data *phy_data = pdata->phy_data; 2547 unsigned int reg; 2548 int ret; 2549 2550 *an_restart = 0; 2551 2552 if (phy_data->port_mode == XGBE_PORT_MODE_SFP) { 2553 /* Check SFP signals */ 2554 xgbe_phy_sfp_detect(pdata); 2555 2556 if (phy_data->sfp_changed) { 2557 *an_restart = 1; 2558 return 0; 2559 } 2560 2561 if (phy_data->sfp_mod_absent || phy_data->sfp_rx_los) 2562 return 0; 2563 } 2564 2565 if (phy_data->phydev) { 2566 /* Check external PHY */ 2567 ret = phy_read_status(phy_data->phydev); 2568 if (ret < 0) 2569 return 0; 2570 2571 if ((pdata->phy.autoneg == AUTONEG_ENABLE) && 2572 !phy_aneg_done(phy_data->phydev)) 2573 return 0; 2574 2575 if (!phy_data->phydev->link) 2576 return 0; 2577 } 2578 2579 /* Link status is latched low, so read once to clear 2580 * and then read again to get current state 2581 */ 2582 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); 2583 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); 2584 if (reg & MDIO_STAT1_LSTATUS) 2585 return 1; 2586 2587 /* No link, attempt a receiver reset cycle */ 2588 if (phy_data->rrc_count++ > XGBE_RRC_FREQUENCY) { 2589 phy_data->rrc_count = 0; 2590 xgbe_phy_rrc(pdata); 2591 } 2592 2593 return 0; 2594 } 2595 2596 static void xgbe_phy_sfp_gpio_setup(struct xgbe_prv_data *pdata) 2597 { 2598 struct xgbe_phy_data *phy_data = pdata->phy_data; 2599 2600 phy_data->sfp_gpio_address = XGBE_GPIO_ADDRESS_PCA9555 + 2601 XP_GET_BITS(pdata->pp3, XP_PROP_3, 2602 GPIO_ADDR); 2603 2604 phy_data->sfp_gpio_mask = XP_GET_BITS(pdata->pp3, XP_PROP_3, 2605 GPIO_MASK); 2606 2607 phy_data->sfp_gpio_rx_los = XP_GET_BITS(pdata->pp3, XP_PROP_3, 2608 GPIO_RX_LOS); 2609 phy_data->sfp_gpio_tx_fault = XP_GET_BITS(pdata->pp3, XP_PROP_3, 2610 GPIO_TX_FAULT); 2611 phy_data->sfp_gpio_mod_absent = XP_GET_BITS(pdata->pp3, XP_PROP_3, 2612 GPIO_MOD_ABS); 2613 phy_data->sfp_gpio_rate_select = XP_GET_BITS(pdata->pp3, XP_PROP_3, 2614 GPIO_RATE_SELECT); 2615 2616 if (netif_msg_probe(pdata)) { 2617 dev_dbg(pdata->dev, "SFP: gpio_address=%#x\n", 2618 phy_data->sfp_gpio_address); 2619 dev_dbg(pdata->dev, "SFP: gpio_mask=%#x\n", 2620 phy_data->sfp_gpio_mask); 2621 dev_dbg(pdata->dev, "SFP: gpio_rx_los=%u\n", 2622 phy_data->sfp_gpio_rx_los); 2623 dev_dbg(pdata->dev, "SFP: gpio_tx_fault=%u\n", 2624 phy_data->sfp_gpio_tx_fault); 2625 dev_dbg(pdata->dev, "SFP: gpio_mod_absent=%u\n", 2626 phy_data->sfp_gpio_mod_absent); 2627 dev_dbg(pdata->dev, "SFP: gpio_rate_select=%u\n", 2628 phy_data->sfp_gpio_rate_select); 2629 } 2630 } 2631 2632 static void xgbe_phy_sfp_comm_setup(struct xgbe_prv_data *pdata) 2633 { 2634 struct xgbe_phy_data *phy_data = pdata->phy_data; 2635 unsigned int mux_addr_hi, mux_addr_lo; 2636 2637 mux_addr_hi = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_HI); 2638 mux_addr_lo = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_LO); 2639 if (mux_addr_lo == XGBE_SFP_DIRECT) 2640 return; 2641 2642 phy_data->sfp_comm = XGBE_SFP_COMM_PCA9545; 2643 phy_data->sfp_mux_address = (mux_addr_hi << 2) + mux_addr_lo; 2644 phy_data->sfp_mux_channel = XP_GET_BITS(pdata->pp4, XP_PROP_4, 2645 MUX_CHAN); 2646 2647 if (netif_msg_probe(pdata)) { 2648 dev_dbg(pdata->dev, "SFP: mux_address=%#x\n", 2649 phy_data->sfp_mux_address); 2650 dev_dbg(pdata->dev, "SFP: mux_channel=%u\n", 2651 phy_data->sfp_mux_channel); 2652 } 2653 } 2654 2655 static void xgbe_phy_sfp_setup(struct xgbe_prv_data *pdata) 2656 { 2657 xgbe_phy_sfp_comm_setup(pdata); 2658 xgbe_phy_sfp_gpio_setup(pdata); 2659 } 2660 2661 static int xgbe_phy_int_mdio_reset(struct xgbe_prv_data *pdata) 2662 { 2663 struct xgbe_phy_data *phy_data = pdata->phy_data; 2664 unsigned int ret; 2665 2666 ret = pdata->hw_if.set_gpio(pdata, phy_data->mdio_reset_gpio); 2667 if (ret) 2668 return ret; 2669 2670 ret = pdata->hw_if.clr_gpio(pdata, phy_data->mdio_reset_gpio); 2671 2672 return ret; 2673 } 2674 2675 static int xgbe_phy_i2c_mdio_reset(struct xgbe_prv_data *pdata) 2676 { 2677 struct xgbe_phy_data *phy_data = pdata->phy_data; 2678 u8 gpio_reg, gpio_ports[2], gpio_data[3]; 2679 int ret; 2680 2681 /* Read the output port registers */ 2682 gpio_reg = 2; 2683 ret = xgbe_phy_i2c_read(pdata, phy_data->mdio_reset_addr, 2684 &gpio_reg, sizeof(gpio_reg), 2685 gpio_ports, sizeof(gpio_ports)); 2686 if (ret) 2687 return ret; 2688 2689 /* Prepare to write the GPIO data */ 2690 gpio_data[0] = 2; 2691 gpio_data[1] = gpio_ports[0]; 2692 gpio_data[2] = gpio_ports[1]; 2693 2694 /* Set the GPIO pin */ 2695 if (phy_data->mdio_reset_gpio < 8) 2696 gpio_data[1] |= (1 << (phy_data->mdio_reset_gpio % 8)); 2697 else 2698 gpio_data[2] |= (1 << (phy_data->mdio_reset_gpio % 8)); 2699 2700 /* Write the output port registers */ 2701 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr, 2702 gpio_data, sizeof(gpio_data)); 2703 if (ret) 2704 return ret; 2705 2706 /* Clear the GPIO pin */ 2707 if (phy_data->mdio_reset_gpio < 8) 2708 gpio_data[1] &= ~(1 << (phy_data->mdio_reset_gpio % 8)); 2709 else 2710 gpio_data[2] &= ~(1 << (phy_data->mdio_reset_gpio % 8)); 2711 2712 /* Write the output port registers */ 2713 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr, 2714 gpio_data, sizeof(gpio_data)); 2715 2716 return ret; 2717 } 2718 2719 static int xgbe_phy_mdio_reset(struct xgbe_prv_data *pdata) 2720 { 2721 struct xgbe_phy_data *phy_data = pdata->phy_data; 2722 int ret; 2723 2724 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO) 2725 return 0; 2726 2727 ret = xgbe_phy_get_comm_ownership(pdata); 2728 if (ret) 2729 return ret; 2730 2731 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO) 2732 ret = xgbe_phy_i2c_mdio_reset(pdata); 2733 else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO) 2734 ret = xgbe_phy_int_mdio_reset(pdata); 2735 2736 xgbe_phy_put_comm_ownership(pdata); 2737 2738 return ret; 2739 } 2740 2741 static bool xgbe_phy_redrv_error(struct xgbe_phy_data *phy_data) 2742 { 2743 if (!phy_data->redrv) 2744 return false; 2745 2746 if (phy_data->redrv_if >= XGBE_PHY_REDRV_IF_MAX) 2747 return true; 2748 2749 switch (phy_data->redrv_model) { 2750 case XGBE_PHY_REDRV_MODEL_4223: 2751 if (phy_data->redrv_lane > 3) 2752 return true; 2753 break; 2754 case XGBE_PHY_REDRV_MODEL_4227: 2755 if (phy_data->redrv_lane > 1) 2756 return true; 2757 break; 2758 default: 2759 return true; 2760 } 2761 2762 return false; 2763 } 2764 2765 static int xgbe_phy_mdio_reset_setup(struct xgbe_prv_data *pdata) 2766 { 2767 struct xgbe_phy_data *phy_data = pdata->phy_data; 2768 2769 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO) 2770 return 0; 2771 2772 phy_data->mdio_reset = XP_GET_BITS(pdata->pp3, XP_PROP_3, MDIO_RESET); 2773 switch (phy_data->mdio_reset) { 2774 case XGBE_MDIO_RESET_NONE: 2775 case XGBE_MDIO_RESET_I2C_GPIO: 2776 case XGBE_MDIO_RESET_INT_GPIO: 2777 break; 2778 default: 2779 dev_err(pdata->dev, "unsupported MDIO reset (%#x)\n", 2780 phy_data->mdio_reset); 2781 return -EINVAL; 2782 } 2783 2784 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO) { 2785 phy_data->mdio_reset_addr = XGBE_GPIO_ADDRESS_PCA9555 + 2786 XP_GET_BITS(pdata->pp3, XP_PROP_3, 2787 MDIO_RESET_I2C_ADDR); 2788 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3, 2789 MDIO_RESET_I2C_GPIO); 2790 } else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO) { 2791 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3, 2792 MDIO_RESET_INT_GPIO); 2793 } 2794 2795 return 0; 2796 } 2797 2798 static bool xgbe_phy_port_mode_mismatch(struct xgbe_prv_data *pdata) 2799 { 2800 struct xgbe_phy_data *phy_data = pdata->phy_data; 2801 2802 switch (phy_data->port_mode) { 2803 case XGBE_PORT_MODE_BACKPLANE: 2804 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 2805 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) || 2806 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)) 2807 return false; 2808 break; 2809 case XGBE_PORT_MODE_BACKPLANE_2500: 2810 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) 2811 return false; 2812 break; 2813 case XGBE_PORT_MODE_1000BASE_T: 2814 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 2815 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)) 2816 return false; 2817 break; 2818 case XGBE_PORT_MODE_1000BASE_X: 2819 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) 2820 return false; 2821 break; 2822 case XGBE_PORT_MODE_NBASE_T: 2823 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 2824 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) || 2825 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500)) 2826 return false; 2827 break; 2828 case XGBE_PORT_MODE_10GBASE_T: 2829 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 2830 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) || 2831 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)) 2832 return false; 2833 break; 2834 case XGBE_PORT_MODE_10GBASE_R: 2835 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) 2836 return false; 2837 break; 2838 case XGBE_PORT_MODE_SFP: 2839 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 2840 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) || 2841 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)) 2842 return false; 2843 break; 2844 default: 2845 break; 2846 } 2847 2848 return true; 2849 } 2850 2851 static bool xgbe_phy_conn_type_mismatch(struct xgbe_prv_data *pdata) 2852 { 2853 struct xgbe_phy_data *phy_data = pdata->phy_data; 2854 2855 switch (phy_data->port_mode) { 2856 case XGBE_PORT_MODE_BACKPLANE: 2857 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 2858 case XGBE_PORT_MODE_BACKPLANE_2500: 2859 if (phy_data->conn_type == XGBE_CONN_TYPE_BACKPLANE) 2860 return false; 2861 break; 2862 case XGBE_PORT_MODE_1000BASE_T: 2863 case XGBE_PORT_MODE_1000BASE_X: 2864 case XGBE_PORT_MODE_NBASE_T: 2865 case XGBE_PORT_MODE_10GBASE_T: 2866 case XGBE_PORT_MODE_10GBASE_R: 2867 if (phy_data->conn_type == XGBE_CONN_TYPE_MDIO) 2868 return false; 2869 break; 2870 case XGBE_PORT_MODE_SFP: 2871 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP) 2872 return false; 2873 break; 2874 default: 2875 break; 2876 } 2877 2878 return true; 2879 } 2880 2881 static bool xgbe_phy_port_enabled(struct xgbe_prv_data *pdata) 2882 { 2883 if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS)) 2884 return false; 2885 if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE)) 2886 return false; 2887 2888 return true; 2889 } 2890 2891 static void xgbe_phy_cdr_track(struct xgbe_prv_data *pdata) 2892 { 2893 struct xgbe_phy_data *phy_data = pdata->phy_data; 2894 2895 if (!pdata->debugfs_an_cdr_workaround) 2896 return; 2897 2898 if (!phy_data->phy_cdr_notrack) 2899 return; 2900 2901 usleep_range(phy_data->phy_cdr_delay, 2902 phy_data->phy_cdr_delay + 500); 2903 2904 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL, 2905 XGBE_PMA_CDR_TRACK_EN_MASK, 2906 XGBE_PMA_CDR_TRACK_EN_ON); 2907 2908 phy_data->phy_cdr_notrack = 0; 2909 } 2910 2911 static void xgbe_phy_cdr_notrack(struct xgbe_prv_data *pdata) 2912 { 2913 struct xgbe_phy_data *phy_data = pdata->phy_data; 2914 2915 if (!pdata->debugfs_an_cdr_workaround) 2916 return; 2917 2918 if (phy_data->phy_cdr_notrack) 2919 return; 2920 2921 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL, 2922 XGBE_PMA_CDR_TRACK_EN_MASK, 2923 XGBE_PMA_CDR_TRACK_EN_OFF); 2924 2925 xgbe_phy_rrc(pdata); 2926 2927 phy_data->phy_cdr_notrack = 1; 2928 } 2929 2930 static void xgbe_phy_kr_training_post(struct xgbe_prv_data *pdata) 2931 { 2932 if (!pdata->debugfs_an_cdr_track_early) 2933 xgbe_phy_cdr_track(pdata); 2934 } 2935 2936 static void xgbe_phy_kr_training_pre(struct xgbe_prv_data *pdata) 2937 { 2938 if (pdata->debugfs_an_cdr_track_early) 2939 xgbe_phy_cdr_track(pdata); 2940 } 2941 2942 static void xgbe_phy_an_post(struct xgbe_prv_data *pdata) 2943 { 2944 struct xgbe_phy_data *phy_data = pdata->phy_data; 2945 2946 switch (pdata->an_mode) { 2947 case XGBE_AN_MODE_CL73: 2948 case XGBE_AN_MODE_CL73_REDRV: 2949 if (phy_data->cur_mode != XGBE_MODE_KR) 2950 break; 2951 2952 xgbe_phy_cdr_track(pdata); 2953 2954 switch (pdata->an_result) { 2955 case XGBE_AN_READY: 2956 case XGBE_AN_COMPLETE: 2957 break; 2958 default: 2959 if (phy_data->phy_cdr_delay < XGBE_CDR_DELAY_MAX) 2960 phy_data->phy_cdr_delay += XGBE_CDR_DELAY_INC; 2961 else 2962 phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT; 2963 break; 2964 } 2965 break; 2966 default: 2967 break; 2968 } 2969 } 2970 2971 static void xgbe_phy_an_pre(struct xgbe_prv_data *pdata) 2972 { 2973 struct xgbe_phy_data *phy_data = pdata->phy_data; 2974 2975 switch (pdata->an_mode) { 2976 case XGBE_AN_MODE_CL73: 2977 case XGBE_AN_MODE_CL73_REDRV: 2978 if (phy_data->cur_mode != XGBE_MODE_KR) 2979 break; 2980 2981 xgbe_phy_cdr_notrack(pdata); 2982 break; 2983 default: 2984 break; 2985 } 2986 } 2987 2988 static void xgbe_phy_stop(struct xgbe_prv_data *pdata) 2989 { 2990 struct xgbe_phy_data *phy_data = pdata->phy_data; 2991 2992 /* If we have an external PHY, free it */ 2993 xgbe_phy_free_phy_device(pdata); 2994 2995 /* Reset SFP data */ 2996 xgbe_phy_sfp_reset(phy_data); 2997 xgbe_phy_sfp_mod_absent(pdata); 2998 2999 /* Reset CDR support */ 3000 xgbe_phy_cdr_track(pdata); 3001 3002 /* Power off the PHY */ 3003 xgbe_phy_power_off(pdata); 3004 3005 /* Stop the I2C controller */ 3006 pdata->i2c_if.i2c_stop(pdata); 3007 } 3008 3009 static int xgbe_phy_start(struct xgbe_prv_data *pdata) 3010 { 3011 struct xgbe_phy_data *phy_data = pdata->phy_data; 3012 int ret; 3013 3014 /* Start the I2C controller */ 3015 ret = pdata->i2c_if.i2c_start(pdata); 3016 if (ret) 3017 return ret; 3018 3019 /* Set the proper MDIO mode for the re-driver */ 3020 if (phy_data->redrv && !phy_data->redrv_if) { 3021 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr, 3022 XGBE_MDIO_MODE_CL22); 3023 if (ret) { 3024 netdev_err(pdata->netdev, 3025 "redriver mdio port not compatible (%u)\n", 3026 phy_data->redrv_addr); 3027 return ret; 3028 } 3029 } 3030 3031 /* Start in highest supported mode */ 3032 xgbe_phy_set_mode(pdata, phy_data->start_mode); 3033 3034 /* Reset CDR support */ 3035 xgbe_phy_cdr_track(pdata); 3036 3037 /* After starting the I2C controller, we can check for an SFP */ 3038 switch (phy_data->port_mode) { 3039 case XGBE_PORT_MODE_SFP: 3040 xgbe_phy_sfp_detect(pdata); 3041 break; 3042 default: 3043 break; 3044 } 3045 3046 /* If we have an external PHY, start it */ 3047 ret = xgbe_phy_find_phy_device(pdata); 3048 if (ret) 3049 goto err_i2c; 3050 3051 return 0; 3052 3053 err_i2c: 3054 pdata->i2c_if.i2c_stop(pdata); 3055 3056 return ret; 3057 } 3058 3059 static int xgbe_phy_reset(struct xgbe_prv_data *pdata) 3060 { 3061 struct xgbe_phy_data *phy_data = pdata->phy_data; 3062 enum xgbe_mode cur_mode; 3063 int ret; 3064 3065 /* Reset by power cycling the PHY */ 3066 cur_mode = phy_data->cur_mode; 3067 xgbe_phy_power_off(pdata); 3068 xgbe_phy_set_mode(pdata, cur_mode); 3069 3070 if (!phy_data->phydev) 3071 return 0; 3072 3073 /* Reset the external PHY */ 3074 ret = xgbe_phy_mdio_reset(pdata); 3075 if (ret) 3076 return ret; 3077 3078 return phy_init_hw(phy_data->phydev); 3079 } 3080 3081 static void xgbe_phy_exit(struct xgbe_prv_data *pdata) 3082 { 3083 struct xgbe_phy_data *phy_data = pdata->phy_data; 3084 3085 /* Unregister for driving external PHYs */ 3086 mdiobus_unregister(phy_data->mii); 3087 } 3088 3089 static int xgbe_phy_init(struct xgbe_prv_data *pdata) 3090 { 3091 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 3092 struct xgbe_phy_data *phy_data; 3093 struct mii_bus *mii; 3094 int ret; 3095 3096 /* Check if enabled */ 3097 if (!xgbe_phy_port_enabled(pdata)) { 3098 dev_info(pdata->dev, "device is not enabled\n"); 3099 return -ENODEV; 3100 } 3101 3102 /* Initialize the I2C controller */ 3103 ret = pdata->i2c_if.i2c_init(pdata); 3104 if (ret) 3105 return ret; 3106 3107 phy_data = devm_kzalloc(pdata->dev, sizeof(*phy_data), GFP_KERNEL); 3108 if (!phy_data) 3109 return -ENOMEM; 3110 pdata->phy_data = phy_data; 3111 3112 phy_data->port_mode = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_MODE); 3113 phy_data->port_id = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_ID); 3114 phy_data->port_speeds = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS); 3115 phy_data->conn_type = XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE); 3116 phy_data->mdio_addr = XP_GET_BITS(pdata->pp0, XP_PROP_0, MDIO_ADDR); 3117 if (netif_msg_probe(pdata)) { 3118 dev_dbg(pdata->dev, "port mode=%u\n", phy_data->port_mode); 3119 dev_dbg(pdata->dev, "port id=%u\n", phy_data->port_id); 3120 dev_dbg(pdata->dev, "port speeds=%#x\n", phy_data->port_speeds); 3121 dev_dbg(pdata->dev, "conn type=%u\n", phy_data->conn_type); 3122 dev_dbg(pdata->dev, "mdio addr=%u\n", phy_data->mdio_addr); 3123 } 3124 3125 phy_data->redrv = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_PRESENT); 3126 phy_data->redrv_if = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_IF); 3127 phy_data->redrv_addr = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_ADDR); 3128 phy_data->redrv_lane = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_LANE); 3129 phy_data->redrv_model = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_MODEL); 3130 if (phy_data->redrv && netif_msg_probe(pdata)) { 3131 dev_dbg(pdata->dev, "redrv present\n"); 3132 dev_dbg(pdata->dev, "redrv i/f=%u\n", phy_data->redrv_if); 3133 dev_dbg(pdata->dev, "redrv addr=%#x\n", phy_data->redrv_addr); 3134 dev_dbg(pdata->dev, "redrv lane=%u\n", phy_data->redrv_lane); 3135 dev_dbg(pdata->dev, "redrv model=%u\n", phy_data->redrv_model); 3136 } 3137 3138 /* Validate the connection requested */ 3139 if (xgbe_phy_conn_type_mismatch(pdata)) { 3140 dev_err(pdata->dev, "phy mode/connection mismatch (%#x/%#x)\n", 3141 phy_data->port_mode, phy_data->conn_type); 3142 return -EINVAL; 3143 } 3144 3145 /* Validate the mode requested */ 3146 if (xgbe_phy_port_mode_mismatch(pdata)) { 3147 dev_err(pdata->dev, "phy mode/speed mismatch (%#x/%#x)\n", 3148 phy_data->port_mode, phy_data->port_speeds); 3149 return -EINVAL; 3150 } 3151 3152 /* Check for and validate MDIO reset support */ 3153 ret = xgbe_phy_mdio_reset_setup(pdata); 3154 if (ret) 3155 return ret; 3156 3157 /* Validate the re-driver information */ 3158 if (xgbe_phy_redrv_error(phy_data)) { 3159 dev_err(pdata->dev, "phy re-driver settings error\n"); 3160 return -EINVAL; 3161 } 3162 pdata->kr_redrv = phy_data->redrv; 3163 3164 /* Indicate current mode is unknown */ 3165 phy_data->cur_mode = XGBE_MODE_UNKNOWN; 3166 3167 /* Initialize supported features */ 3168 XGBE_ZERO_SUP(lks); 3169 3170 switch (phy_data->port_mode) { 3171 /* Backplane support */ 3172 case XGBE_PORT_MODE_BACKPLANE: 3173 XGBE_SET_SUP(lks, Autoneg); 3174 fallthrough; 3175 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 3176 XGBE_SET_SUP(lks, Pause); 3177 XGBE_SET_SUP(lks, Asym_Pause); 3178 XGBE_SET_SUP(lks, Backplane); 3179 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) { 3180 XGBE_SET_SUP(lks, 1000baseKX_Full); 3181 phy_data->start_mode = XGBE_MODE_KX_1000; 3182 } 3183 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) { 3184 XGBE_SET_SUP(lks, 10000baseKR_Full); 3185 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 3186 XGBE_SET_SUP(lks, 10000baseR_FEC); 3187 phy_data->start_mode = XGBE_MODE_KR; 3188 } 3189 3190 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE; 3191 break; 3192 case XGBE_PORT_MODE_BACKPLANE_2500: 3193 XGBE_SET_SUP(lks, Pause); 3194 XGBE_SET_SUP(lks, Asym_Pause); 3195 XGBE_SET_SUP(lks, Backplane); 3196 XGBE_SET_SUP(lks, 2500baseX_Full); 3197 phy_data->start_mode = XGBE_MODE_KX_2500; 3198 3199 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE; 3200 break; 3201 3202 /* MDIO 1GBase-T support */ 3203 case XGBE_PORT_MODE_1000BASE_T: 3204 XGBE_SET_SUP(lks, Autoneg); 3205 XGBE_SET_SUP(lks, Pause); 3206 XGBE_SET_SUP(lks, Asym_Pause); 3207 XGBE_SET_SUP(lks, TP); 3208 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) { 3209 XGBE_SET_SUP(lks, 100baseT_Full); 3210 phy_data->start_mode = XGBE_MODE_SGMII_100; 3211 } 3212 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) { 3213 XGBE_SET_SUP(lks, 1000baseT_Full); 3214 phy_data->start_mode = XGBE_MODE_SGMII_1000; 3215 } 3216 3217 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22; 3218 break; 3219 3220 /* MDIO Base-X support */ 3221 case XGBE_PORT_MODE_1000BASE_X: 3222 XGBE_SET_SUP(lks, Autoneg); 3223 XGBE_SET_SUP(lks, Pause); 3224 XGBE_SET_SUP(lks, Asym_Pause); 3225 XGBE_SET_SUP(lks, FIBRE); 3226 XGBE_SET_SUP(lks, 1000baseX_Full); 3227 phy_data->start_mode = XGBE_MODE_X; 3228 3229 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22; 3230 break; 3231 3232 /* MDIO NBase-T support */ 3233 case XGBE_PORT_MODE_NBASE_T: 3234 XGBE_SET_SUP(lks, Autoneg); 3235 XGBE_SET_SUP(lks, Pause); 3236 XGBE_SET_SUP(lks, Asym_Pause); 3237 XGBE_SET_SUP(lks, TP); 3238 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) { 3239 XGBE_SET_SUP(lks, 100baseT_Full); 3240 phy_data->start_mode = XGBE_MODE_SGMII_100; 3241 } 3242 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) { 3243 XGBE_SET_SUP(lks, 1000baseT_Full); 3244 phy_data->start_mode = XGBE_MODE_SGMII_1000; 3245 } 3246 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) { 3247 XGBE_SET_SUP(lks, 2500baseT_Full); 3248 phy_data->start_mode = XGBE_MODE_KX_2500; 3249 } 3250 3251 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45; 3252 break; 3253 3254 /* 10GBase-T support */ 3255 case XGBE_PORT_MODE_10GBASE_T: 3256 XGBE_SET_SUP(lks, Autoneg); 3257 XGBE_SET_SUP(lks, Pause); 3258 XGBE_SET_SUP(lks, Asym_Pause); 3259 XGBE_SET_SUP(lks, TP); 3260 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) { 3261 XGBE_SET_SUP(lks, 100baseT_Full); 3262 phy_data->start_mode = XGBE_MODE_SGMII_100; 3263 } 3264 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) { 3265 XGBE_SET_SUP(lks, 1000baseT_Full); 3266 phy_data->start_mode = XGBE_MODE_SGMII_1000; 3267 } 3268 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) { 3269 XGBE_SET_SUP(lks, 10000baseT_Full); 3270 phy_data->start_mode = XGBE_MODE_KR; 3271 } 3272 3273 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45; 3274 break; 3275 3276 /* 10GBase-R support */ 3277 case XGBE_PORT_MODE_10GBASE_R: 3278 XGBE_SET_SUP(lks, Autoneg); 3279 XGBE_SET_SUP(lks, Pause); 3280 XGBE_SET_SUP(lks, Asym_Pause); 3281 XGBE_SET_SUP(lks, FIBRE); 3282 XGBE_SET_SUP(lks, 10000baseSR_Full); 3283 XGBE_SET_SUP(lks, 10000baseLR_Full); 3284 XGBE_SET_SUP(lks, 10000baseLRM_Full); 3285 XGBE_SET_SUP(lks, 10000baseER_Full); 3286 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 3287 XGBE_SET_SUP(lks, 10000baseR_FEC); 3288 phy_data->start_mode = XGBE_MODE_SFI; 3289 3290 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE; 3291 break; 3292 3293 /* SFP support */ 3294 case XGBE_PORT_MODE_SFP: 3295 XGBE_SET_SUP(lks, Autoneg); 3296 XGBE_SET_SUP(lks, Pause); 3297 XGBE_SET_SUP(lks, Asym_Pause); 3298 XGBE_SET_SUP(lks, TP); 3299 XGBE_SET_SUP(lks, FIBRE); 3300 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) 3301 phy_data->start_mode = XGBE_MODE_SGMII_100; 3302 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) 3303 phy_data->start_mode = XGBE_MODE_SGMII_1000; 3304 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) 3305 phy_data->start_mode = XGBE_MODE_SFI; 3306 3307 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22; 3308 3309 xgbe_phy_sfp_setup(pdata); 3310 break; 3311 default: 3312 return -EINVAL; 3313 } 3314 3315 if (netif_msg_probe(pdata)) 3316 dev_dbg(pdata->dev, "phy supported=0x%*pb\n", 3317 __ETHTOOL_LINK_MODE_MASK_NBITS, 3318 lks->link_modes.supported); 3319 3320 if ((phy_data->conn_type & XGBE_CONN_TYPE_MDIO) && 3321 (phy_data->phydev_mode != XGBE_MDIO_MODE_NONE)) { 3322 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr, 3323 phy_data->phydev_mode); 3324 if (ret) { 3325 dev_err(pdata->dev, 3326 "mdio port/clause not compatible (%d/%u)\n", 3327 phy_data->mdio_addr, phy_data->phydev_mode); 3328 return -EINVAL; 3329 } 3330 } 3331 3332 if (phy_data->redrv && !phy_data->redrv_if) { 3333 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr, 3334 XGBE_MDIO_MODE_CL22); 3335 if (ret) { 3336 dev_err(pdata->dev, 3337 "redriver mdio port not compatible (%u)\n", 3338 phy_data->redrv_addr); 3339 return -EINVAL; 3340 } 3341 } 3342 3343 phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT; 3344 3345 /* Register for driving external PHYs */ 3346 mii = devm_mdiobus_alloc(pdata->dev); 3347 if (!mii) { 3348 dev_err(pdata->dev, "mdiobus_alloc failed\n"); 3349 return -ENOMEM; 3350 } 3351 3352 mii->priv = pdata; 3353 mii->name = "amd-xgbe-mii"; 3354 mii->read = xgbe_phy_mii_read; 3355 mii->write = xgbe_phy_mii_write; 3356 mii->parent = pdata->dev; 3357 mii->phy_mask = ~0; 3358 snprintf(mii->id, sizeof(mii->id), "%s", dev_name(pdata->dev)); 3359 ret = mdiobus_register(mii); 3360 if (ret) { 3361 dev_err(pdata->dev, "mdiobus_register failed\n"); 3362 return ret; 3363 } 3364 phy_data->mii = mii; 3365 3366 return 0; 3367 } 3368 3369 void xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *phy_if) 3370 { 3371 struct xgbe_phy_impl_if *phy_impl = &phy_if->phy_impl; 3372 3373 phy_impl->init = xgbe_phy_init; 3374 phy_impl->exit = xgbe_phy_exit; 3375 3376 phy_impl->reset = xgbe_phy_reset; 3377 phy_impl->start = xgbe_phy_start; 3378 phy_impl->stop = xgbe_phy_stop; 3379 3380 phy_impl->link_status = xgbe_phy_link_status; 3381 3382 phy_impl->valid_speed = xgbe_phy_valid_speed; 3383 3384 phy_impl->use_mode = xgbe_phy_use_mode; 3385 phy_impl->set_mode = xgbe_phy_set_mode; 3386 phy_impl->get_mode = xgbe_phy_get_mode; 3387 phy_impl->switch_mode = xgbe_phy_switch_mode; 3388 phy_impl->cur_mode = xgbe_phy_cur_mode; 3389 3390 phy_impl->an_mode = xgbe_phy_an_mode; 3391 3392 phy_impl->an_config = xgbe_phy_an_config; 3393 3394 phy_impl->an_advertising = xgbe_phy_an_advertising; 3395 3396 phy_impl->an_outcome = xgbe_phy_an_outcome; 3397 3398 phy_impl->an_pre = xgbe_phy_an_pre; 3399 phy_impl->an_post = xgbe_phy_an_post; 3400 3401 phy_impl->kr_training_pre = xgbe_phy_kr_training_pre; 3402 phy_impl->kr_training_post = xgbe_phy_kr_training_post; 3403 3404 phy_impl->module_info = xgbe_phy_module_info; 3405 phy_impl->module_eeprom = xgbe_phy_module_eeprom; 3406 } 3407