1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) 2 /* 3 * Copyright (c) 2014-2025, Advanced Micro Devices, Inc. 4 * Copyright (c) 2014, Synopsys, Inc. 5 * All rights reserved 6 */ 7 8 #include <linux/module.h> 9 #include <linux/device.h> 10 #include <linux/kmod.h> 11 #include <linux/mdio.h> 12 #include <linux/phy.h> 13 #include <linux/ethtool.h> 14 15 #include "xgbe.h" 16 #include "xgbe-common.h" 17 18 #define XGBE_PHY_PORT_SPEED_10 BIT(0) 19 #define XGBE_PHY_PORT_SPEED_100 BIT(1) 20 #define XGBE_PHY_PORT_SPEED_1000 BIT(2) 21 #define XGBE_PHY_PORT_SPEED_2500 BIT(3) 22 #define XGBE_PHY_PORT_SPEED_10000 BIT(4) 23 24 #define XGBE_MUTEX_RELEASE 0x80000000 25 26 #define XGBE_SFP_DIRECT 7 27 28 /* I2C target addresses */ 29 #define XGBE_SFP_SERIAL_ID_ADDRESS 0x50 30 #define XGBE_SFP_DIAG_INFO_ADDRESS 0x51 31 #define XGBE_SFP_PHY_ADDRESS 0x56 32 #define XGBE_GPIO_ADDRESS_PCA9555 0x20 33 34 /* SFP sideband signal indicators */ 35 #define XGBE_GPIO_NO_TX_FAULT BIT(0) 36 #define XGBE_GPIO_NO_RATE_SELECT BIT(1) 37 #define XGBE_GPIO_NO_MOD_ABSENT BIT(2) 38 #define XGBE_GPIO_NO_RX_LOS BIT(3) 39 40 /* Rate-change complete wait/retry count */ 41 #define XGBE_RATECHANGE_COUNT 500 42 43 /* CDR delay values for KR support (in usec) */ 44 #define XGBE_CDR_DELAY_INIT 10000 45 #define XGBE_CDR_DELAY_INC 10000 46 #define XGBE_CDR_DELAY_MAX 100000 47 48 /* RRC frequency during link status check */ 49 #define XGBE_RRC_FREQUENCY 10 50 51 enum xgbe_port_mode { 52 XGBE_PORT_MODE_RSVD = 0, 53 XGBE_PORT_MODE_BACKPLANE, 54 XGBE_PORT_MODE_BACKPLANE_2500, 55 XGBE_PORT_MODE_1000BASE_T, 56 XGBE_PORT_MODE_1000BASE_X, 57 XGBE_PORT_MODE_NBASE_T, 58 XGBE_PORT_MODE_10GBASE_T, 59 XGBE_PORT_MODE_10GBASE_R, 60 XGBE_PORT_MODE_SFP, 61 XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG, 62 XGBE_PORT_MODE_MAX, 63 }; 64 65 enum xgbe_conn_type { 66 XGBE_CONN_TYPE_NONE = 0, 67 XGBE_CONN_TYPE_SFP, 68 XGBE_CONN_TYPE_MDIO, 69 XGBE_CONN_TYPE_RSVD1, 70 XGBE_CONN_TYPE_BACKPLANE, 71 XGBE_CONN_TYPE_MAX, 72 }; 73 74 /* SFP/SFP+ related definitions */ 75 enum xgbe_sfp_comm { 76 XGBE_SFP_COMM_DIRECT = 0, 77 XGBE_SFP_COMM_PCA9545, 78 }; 79 80 enum xgbe_sfp_cable { 81 XGBE_SFP_CABLE_UNKNOWN = 0, 82 XGBE_SFP_CABLE_ACTIVE, 83 XGBE_SFP_CABLE_PASSIVE, 84 XGBE_SFP_CABLE_FIBER, 85 }; 86 87 enum xgbe_sfp_base { 88 XGBE_SFP_BASE_UNKNOWN = 0, 89 XGBE_SFP_BASE_1000_T, 90 XGBE_SFP_BASE_1000_SX, 91 XGBE_SFP_BASE_1000_LX, 92 XGBE_SFP_BASE_1000_CX, 93 XGBE_SFP_BASE_10000_SR, 94 XGBE_SFP_BASE_10000_LR, 95 XGBE_SFP_BASE_10000_LRM, 96 XGBE_SFP_BASE_10000_ER, 97 XGBE_SFP_BASE_10000_CR, 98 }; 99 100 enum xgbe_sfp_speed { 101 XGBE_SFP_SPEED_UNKNOWN = 0, 102 XGBE_SFP_SPEED_100_1000, 103 XGBE_SFP_SPEED_1000, 104 XGBE_SFP_SPEED_10000, 105 }; 106 107 /* SFP Serial ID Base ID values relative to an offset of 0 */ 108 #define XGBE_SFP_BASE_ID 0 109 #define XGBE_SFP_ID_SFP 0x03 110 111 #define XGBE_SFP_BASE_EXT_ID 1 112 #define XGBE_SFP_EXT_ID_SFP 0x04 113 114 #define XGBE_SFP_BASE_10GBE_CC 3 115 #define XGBE_SFP_BASE_10GBE_CC_SR BIT(4) 116 #define XGBE_SFP_BASE_10GBE_CC_LR BIT(5) 117 #define XGBE_SFP_BASE_10GBE_CC_LRM BIT(6) 118 #define XGBE_SFP_BASE_10GBE_CC_ER BIT(7) 119 120 #define XGBE_SFP_BASE_1GBE_CC 6 121 #define XGBE_SFP_BASE_1GBE_CC_SX BIT(0) 122 #define XGBE_SFP_BASE_1GBE_CC_LX BIT(1) 123 #define XGBE_SFP_BASE_1GBE_CC_CX BIT(2) 124 #define XGBE_SFP_BASE_1GBE_CC_T BIT(3) 125 126 #define XGBE_SFP_BASE_CABLE 8 127 #define XGBE_SFP_BASE_CABLE_PASSIVE BIT(2) 128 #define XGBE_SFP_BASE_CABLE_ACTIVE BIT(3) 129 130 #define XGBE_SFP_BASE_BR 12 131 #define XGBE_SFP_BASE_BR_1GBE_MIN 0x0a 132 #define XGBE_SFP_BASE_BR_10GBE_MIN 0x64 133 134 #define XGBE_SFP_BASE_CU_CABLE_LEN 18 135 136 #define XGBE_SFP_BASE_VENDOR_NAME 20 137 #define XGBE_SFP_BASE_VENDOR_NAME_LEN 16 138 #define XGBE_SFP_BASE_VENDOR_PN 40 139 #define XGBE_SFP_BASE_VENDOR_PN_LEN 16 140 #define XGBE_SFP_BASE_VENDOR_REV 56 141 #define XGBE_SFP_BASE_VENDOR_REV_LEN 4 142 143 #define XGBE_SFP_BASE_CC 63 144 145 /* SFP Serial ID Extended ID values relative to an offset of 64 */ 146 #define XGBE_SFP_BASE_VENDOR_SN 4 147 #define XGBE_SFP_BASE_VENDOR_SN_LEN 16 148 149 #define XGBE_SFP_EXTD_OPT1 1 150 #define XGBE_SFP_EXTD_OPT1_RX_LOS BIT(1) 151 #define XGBE_SFP_EXTD_OPT1_TX_FAULT BIT(3) 152 153 #define XGBE_SFP_EXTD_DIAG 28 154 #define XGBE_SFP_EXTD_DIAG_ADDR_CHANGE BIT(2) 155 156 #define XGBE_SFP_EXTD_SFF_8472 30 157 158 #define XGBE_SFP_EXTD_CC 31 159 160 struct xgbe_sfp_eeprom { 161 u8 base[64]; 162 u8 extd[32]; 163 u8 vendor[32]; 164 }; 165 166 #define XGBE_SFP_DIAGS_SUPPORTED(_x) \ 167 ((_x)->extd[XGBE_SFP_EXTD_SFF_8472] && \ 168 !((_x)->extd[XGBE_SFP_EXTD_DIAG] & XGBE_SFP_EXTD_DIAG_ADDR_CHANGE)) 169 170 #define XGBE_SFP_EEPROM_BASE_LEN 256 171 #define XGBE_SFP_EEPROM_DIAG_LEN 256 172 #define XGBE_SFP_EEPROM_MAX (XGBE_SFP_EEPROM_BASE_LEN + \ 173 XGBE_SFP_EEPROM_DIAG_LEN) 174 175 #define XGBE_BEL_FUSE_VENDOR "BEL-FUSE " 176 #define XGBE_BEL_FUSE_PARTNO "1GBT-SFP06 " 177 178 #define XGBE_MOLEX_VENDOR "Molex Inc. " 179 180 struct xgbe_sfp_ascii { 181 union { 182 char vendor[XGBE_SFP_BASE_VENDOR_NAME_LEN + 1]; 183 char partno[XGBE_SFP_BASE_VENDOR_PN_LEN + 1]; 184 char rev[XGBE_SFP_BASE_VENDOR_REV_LEN + 1]; 185 char serno[XGBE_SFP_BASE_VENDOR_SN_LEN + 1]; 186 } u; 187 }; 188 189 /* MDIO PHY reset types */ 190 enum xgbe_mdio_reset { 191 XGBE_MDIO_RESET_NONE = 0, 192 XGBE_MDIO_RESET_I2C_GPIO, 193 XGBE_MDIO_RESET_INT_GPIO, 194 XGBE_MDIO_RESET_MAX, 195 }; 196 197 /* Re-driver related definitions */ 198 enum xgbe_phy_redrv_if { 199 XGBE_PHY_REDRV_IF_MDIO = 0, 200 XGBE_PHY_REDRV_IF_I2C, 201 XGBE_PHY_REDRV_IF_MAX, 202 }; 203 204 enum xgbe_phy_redrv_model { 205 XGBE_PHY_REDRV_MODEL_4223 = 0, 206 XGBE_PHY_REDRV_MODEL_4227, 207 XGBE_PHY_REDRV_MODEL_MAX, 208 }; 209 210 enum xgbe_phy_redrv_mode { 211 XGBE_PHY_REDRV_MODE_CX = 5, 212 XGBE_PHY_REDRV_MODE_SR = 9, 213 }; 214 215 #define XGBE_PHY_REDRV_MODE_REG 0x12b0 216 217 /* PHY related configuration information */ 218 struct xgbe_phy_data { 219 enum xgbe_port_mode port_mode; 220 221 unsigned int port_id; 222 223 unsigned int port_speeds; 224 225 enum xgbe_conn_type conn_type; 226 227 enum xgbe_mode cur_mode; 228 enum xgbe_mode start_mode; 229 230 unsigned int rrc_count; 231 232 unsigned int mdio_addr; 233 234 /* SFP Support */ 235 enum xgbe_sfp_comm sfp_comm; 236 unsigned int sfp_mux_address; 237 unsigned int sfp_mux_channel; 238 239 unsigned int sfp_gpio_address; 240 unsigned int sfp_gpio_mask; 241 unsigned int sfp_gpio_inputs; 242 unsigned int sfp_gpio_rx_los; 243 unsigned int sfp_gpio_tx_fault; 244 unsigned int sfp_gpio_mod_absent; 245 unsigned int sfp_gpio_rate_select; 246 247 unsigned int sfp_rx_los; 248 unsigned int sfp_tx_fault; 249 unsigned int sfp_mod_absent; 250 unsigned int sfp_changed; 251 unsigned int sfp_phy_avail; 252 unsigned int sfp_cable_len; 253 enum xgbe_sfp_base sfp_base; 254 enum xgbe_sfp_cable sfp_cable; 255 enum xgbe_sfp_speed sfp_speed; 256 struct xgbe_sfp_eeprom sfp_eeprom; 257 258 /* External PHY support */ 259 enum xgbe_mdio_mode phydev_mode; 260 struct mii_bus *mii; 261 struct phy_device *phydev; 262 enum xgbe_mdio_reset mdio_reset; 263 unsigned int mdio_reset_addr; 264 unsigned int mdio_reset_gpio; 265 266 /* Re-driver support */ 267 unsigned int redrv; 268 unsigned int redrv_if; 269 unsigned int redrv_addr; 270 unsigned int redrv_lane; 271 unsigned int redrv_model; 272 273 /* KR AN support */ 274 unsigned int phy_cdr_notrack; 275 unsigned int phy_cdr_delay; 276 }; 277 278 /* I2C, MDIO and GPIO lines are muxed, so only one device at a time */ 279 static DEFINE_MUTEX(xgbe_phy_comm_lock); 280 281 static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata); 282 static void xgbe_phy_rrc(struct xgbe_prv_data *pdata); 283 static void xgbe_phy_perform_ratechange(struct xgbe_prv_data *pdata, 284 enum xgbe_mb_cmd cmd, 285 enum xgbe_mb_subcmd sub_cmd); 286 287 static int xgbe_phy_i2c_xfer(struct xgbe_prv_data *pdata, 288 struct xgbe_i2c_op *i2c_op) 289 { 290 return pdata->i2c_if.i2c_xfer(pdata, i2c_op); 291 } 292 293 static int xgbe_phy_redrv_write(struct xgbe_prv_data *pdata, unsigned int reg, 294 unsigned int val) 295 { 296 struct xgbe_phy_data *phy_data = pdata->phy_data; 297 struct xgbe_i2c_op i2c_op; 298 __be16 *redrv_val; 299 u8 redrv_data[5], csum; 300 unsigned int i, retry; 301 int ret; 302 303 /* High byte of register contains read/write indicator */ 304 redrv_data[0] = ((reg >> 8) & 0xff) << 1; 305 redrv_data[1] = reg & 0xff; 306 redrv_val = (__be16 *)&redrv_data[2]; 307 *redrv_val = cpu_to_be16(val); 308 309 /* Calculate 1 byte checksum */ 310 csum = 0; 311 for (i = 0; i < 4; i++) { 312 csum += redrv_data[i]; 313 if (redrv_data[i] > csum) 314 csum++; 315 } 316 redrv_data[4] = ~csum; 317 318 retry = 1; 319 again1: 320 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 321 i2c_op.target = phy_data->redrv_addr; 322 i2c_op.len = sizeof(redrv_data); 323 i2c_op.buf = redrv_data; 324 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 325 if (ret) { 326 if ((ret == -EAGAIN) && retry--) 327 goto again1; 328 329 return ret; 330 } 331 332 retry = 1; 333 again2: 334 i2c_op.cmd = XGBE_I2C_CMD_READ; 335 i2c_op.target = phy_data->redrv_addr; 336 i2c_op.len = 1; 337 i2c_op.buf = redrv_data; 338 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 339 if (ret) { 340 if ((ret == -EAGAIN) && retry--) 341 goto again2; 342 343 return ret; 344 } 345 346 if (redrv_data[0] != 0xff) { 347 netif_dbg(pdata, drv, pdata->netdev, 348 "Redriver write checksum error\n"); 349 ret = -EIO; 350 } 351 352 return ret; 353 } 354 355 static int xgbe_phy_i2c_write(struct xgbe_prv_data *pdata, unsigned int target, 356 void *val, unsigned int val_len) 357 { 358 struct xgbe_i2c_op i2c_op; 359 int retry, ret; 360 361 retry = 1; 362 again: 363 /* Write the specfied register */ 364 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 365 i2c_op.target = target; 366 i2c_op.len = val_len; 367 i2c_op.buf = val; 368 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 369 if ((ret == -EAGAIN) && retry--) 370 goto again; 371 372 return ret; 373 } 374 375 static int xgbe_phy_i2c_read(struct xgbe_prv_data *pdata, unsigned int target, 376 void *reg, unsigned int reg_len, 377 void *val, unsigned int val_len) 378 { 379 struct xgbe_i2c_op i2c_op; 380 int retry, ret; 381 382 retry = 1; 383 again1: 384 /* Set the specified register to read */ 385 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 386 i2c_op.target = target; 387 i2c_op.len = reg_len; 388 i2c_op.buf = reg; 389 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 390 if (ret) { 391 if ((ret == -EAGAIN) && retry--) 392 goto again1; 393 394 return ret; 395 } 396 397 retry = 1; 398 again2: 399 /* Read the specfied register */ 400 i2c_op.cmd = XGBE_I2C_CMD_READ; 401 i2c_op.target = target; 402 i2c_op.len = val_len; 403 i2c_op.buf = val; 404 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 405 if ((ret == -EAGAIN) && retry--) 406 goto again2; 407 408 return ret; 409 } 410 411 static int xgbe_phy_sfp_put_mux(struct xgbe_prv_data *pdata) 412 { 413 struct xgbe_phy_data *phy_data = pdata->phy_data; 414 struct xgbe_i2c_op i2c_op; 415 u8 mux_channel; 416 417 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT) 418 return 0; 419 420 /* Select no mux channels */ 421 mux_channel = 0; 422 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 423 i2c_op.target = phy_data->sfp_mux_address; 424 i2c_op.len = sizeof(mux_channel); 425 i2c_op.buf = &mux_channel; 426 427 return xgbe_phy_i2c_xfer(pdata, &i2c_op); 428 } 429 430 static int xgbe_phy_sfp_get_mux(struct xgbe_prv_data *pdata) 431 { 432 struct xgbe_phy_data *phy_data = pdata->phy_data; 433 struct xgbe_i2c_op i2c_op; 434 u8 mux_channel; 435 436 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT) 437 return 0; 438 439 /* Select desired mux channel */ 440 mux_channel = 1 << phy_data->sfp_mux_channel; 441 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 442 i2c_op.target = phy_data->sfp_mux_address; 443 i2c_op.len = sizeof(mux_channel); 444 i2c_op.buf = &mux_channel; 445 446 return xgbe_phy_i2c_xfer(pdata, &i2c_op); 447 } 448 449 static void xgbe_phy_put_comm_ownership(struct xgbe_prv_data *pdata) 450 { 451 mutex_unlock(&xgbe_phy_comm_lock); 452 } 453 454 static int xgbe_phy_get_comm_ownership(struct xgbe_prv_data *pdata) 455 { 456 struct xgbe_phy_data *phy_data = pdata->phy_data; 457 unsigned long timeout; 458 unsigned int mutex_id; 459 460 /* The I2C and MDIO/GPIO bus is multiplexed between multiple devices, 461 * the driver needs to take the software mutex and then the hardware 462 * mutexes before being able to use the busses. 463 */ 464 mutex_lock(&xgbe_phy_comm_lock); 465 466 /* Clear the mutexes */ 467 XP_IOWRITE(pdata, XP_I2C_MUTEX, XGBE_MUTEX_RELEASE); 468 XP_IOWRITE(pdata, XP_MDIO_MUTEX, XGBE_MUTEX_RELEASE); 469 470 /* Mutex formats are the same for I2C and MDIO/GPIO */ 471 mutex_id = 0; 472 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ID, phy_data->port_id); 473 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ACTIVE, 1); 474 475 timeout = jiffies + (5 * HZ); 476 while (time_before(jiffies, timeout)) { 477 /* Must be all zeroes in order to obtain the mutex */ 478 if (XP_IOREAD(pdata, XP_I2C_MUTEX) || 479 XP_IOREAD(pdata, XP_MDIO_MUTEX)) { 480 usleep_range(100, 200); 481 continue; 482 } 483 484 /* Obtain the mutex */ 485 XP_IOWRITE(pdata, XP_I2C_MUTEX, mutex_id); 486 XP_IOWRITE(pdata, XP_MDIO_MUTEX, mutex_id); 487 488 return 0; 489 } 490 491 mutex_unlock(&xgbe_phy_comm_lock); 492 493 netdev_err(pdata->netdev, "unable to obtain hardware mutexes\n"); 494 495 return -ETIMEDOUT; 496 } 497 498 static int xgbe_phy_mdio_mii_write_c22(struct xgbe_prv_data *pdata, int addr, 499 int reg, u16 val) 500 { 501 struct xgbe_phy_data *phy_data = pdata->phy_data; 502 503 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22) 504 return -EOPNOTSUPP; 505 506 return pdata->hw_if.write_ext_mii_regs_c22(pdata, addr, reg, val); 507 } 508 509 static int xgbe_phy_mdio_mii_write_c45(struct xgbe_prv_data *pdata, int addr, 510 int devad, int reg, u16 val) 511 { 512 struct xgbe_phy_data *phy_data = pdata->phy_data; 513 514 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45) 515 return -EOPNOTSUPP; 516 517 return pdata->hw_if.write_ext_mii_regs_c45(pdata, addr, devad, 518 reg, val); 519 } 520 521 static int xgbe_phy_i2c_mii_write(struct xgbe_prv_data *pdata, int reg, u16 val) 522 { 523 __be16 *mii_val; 524 u8 mii_data[3]; 525 int ret; 526 527 ret = xgbe_phy_sfp_get_mux(pdata); 528 if (ret) 529 return ret; 530 531 mii_data[0] = reg & 0xff; 532 mii_val = (__be16 *)&mii_data[1]; 533 *mii_val = cpu_to_be16(val); 534 535 ret = xgbe_phy_i2c_write(pdata, XGBE_SFP_PHY_ADDRESS, 536 mii_data, sizeof(mii_data)); 537 538 xgbe_phy_sfp_put_mux(pdata); 539 540 return ret; 541 } 542 543 static int xgbe_phy_mii_write_c22(struct mii_bus *mii, int addr, int reg, 544 u16 val) 545 { 546 struct xgbe_prv_data *pdata = mii->priv; 547 struct xgbe_phy_data *phy_data = pdata->phy_data; 548 int ret; 549 550 ret = xgbe_phy_get_comm_ownership(pdata); 551 if (ret) 552 return ret; 553 554 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP) 555 ret = xgbe_phy_i2c_mii_write(pdata, reg, val); 556 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO) 557 ret = xgbe_phy_mdio_mii_write_c22(pdata, addr, reg, val); 558 else 559 ret = -EOPNOTSUPP; 560 561 xgbe_phy_put_comm_ownership(pdata); 562 563 return ret; 564 } 565 566 static int xgbe_phy_mii_write_c45(struct mii_bus *mii, int addr, int devad, 567 int reg, u16 val) 568 { 569 struct xgbe_prv_data *pdata = mii->priv; 570 struct xgbe_phy_data *phy_data = pdata->phy_data; 571 int ret; 572 573 ret = xgbe_phy_get_comm_ownership(pdata); 574 if (ret) 575 return ret; 576 577 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP) 578 ret = -EOPNOTSUPP; 579 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO) 580 ret = xgbe_phy_mdio_mii_write_c45(pdata, addr, devad, reg, val); 581 else 582 ret = -EOPNOTSUPP; 583 584 xgbe_phy_put_comm_ownership(pdata); 585 586 return ret; 587 } 588 589 static int xgbe_phy_mdio_mii_read_c22(struct xgbe_prv_data *pdata, int addr, 590 int reg) 591 { 592 struct xgbe_phy_data *phy_data = pdata->phy_data; 593 594 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22) 595 return -EOPNOTSUPP; 596 597 return pdata->hw_if.read_ext_mii_regs_c22(pdata, addr, reg); 598 } 599 600 static int xgbe_phy_mdio_mii_read_c45(struct xgbe_prv_data *pdata, int addr, 601 int devad, int reg) 602 { 603 struct xgbe_phy_data *phy_data = pdata->phy_data; 604 605 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45) 606 return -EOPNOTSUPP; 607 608 return pdata->hw_if.read_ext_mii_regs_c45(pdata, addr, devad, reg); 609 } 610 611 static int xgbe_phy_i2c_mii_read(struct xgbe_prv_data *pdata, int reg) 612 { 613 __be16 mii_val; 614 u8 mii_reg; 615 int ret; 616 617 ret = xgbe_phy_sfp_get_mux(pdata); 618 if (ret) 619 return ret; 620 621 mii_reg = reg; 622 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_PHY_ADDRESS, 623 &mii_reg, sizeof(mii_reg), 624 &mii_val, sizeof(mii_val)); 625 if (!ret) 626 ret = be16_to_cpu(mii_val); 627 628 xgbe_phy_sfp_put_mux(pdata); 629 630 return ret; 631 } 632 633 static int xgbe_phy_mii_read_c22(struct mii_bus *mii, int addr, int reg) 634 { 635 struct xgbe_prv_data *pdata = mii->priv; 636 struct xgbe_phy_data *phy_data = pdata->phy_data; 637 int ret; 638 639 ret = xgbe_phy_get_comm_ownership(pdata); 640 if (ret) 641 return ret; 642 643 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP) 644 ret = xgbe_phy_i2c_mii_read(pdata, reg); 645 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO) 646 ret = xgbe_phy_mdio_mii_read_c22(pdata, addr, reg); 647 else 648 ret = -EOPNOTSUPP; 649 650 xgbe_phy_put_comm_ownership(pdata); 651 652 return ret; 653 } 654 655 static int xgbe_phy_mii_read_c45(struct mii_bus *mii, int addr, int devad, 656 int reg) 657 { 658 struct xgbe_prv_data *pdata = mii->priv; 659 struct xgbe_phy_data *phy_data = pdata->phy_data; 660 int ret; 661 662 ret = xgbe_phy_get_comm_ownership(pdata); 663 if (ret) 664 return ret; 665 666 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP) 667 ret = -EOPNOTSUPP; 668 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO) 669 ret = xgbe_phy_mdio_mii_read_c45(pdata, addr, devad, reg); 670 else 671 ret = -EOPNOTSUPP; 672 673 xgbe_phy_put_comm_ownership(pdata); 674 675 return ret; 676 } 677 678 static void xgbe_phy_sfp_phy_settings(struct xgbe_prv_data *pdata) 679 { 680 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 681 struct xgbe_phy_data *phy_data = pdata->phy_data; 682 683 if (!phy_data->sfp_mod_absent && !phy_data->sfp_changed) 684 return; 685 686 XGBE_ZERO_SUP(lks); 687 688 if (phy_data->sfp_mod_absent) { 689 pdata->phy.speed = SPEED_UNKNOWN; 690 pdata->phy.duplex = DUPLEX_UNKNOWN; 691 pdata->phy.autoneg = AUTONEG_ENABLE; 692 pdata->phy.pause_autoneg = AUTONEG_ENABLE; 693 694 XGBE_SET_SUP(lks, Autoneg); 695 XGBE_SET_SUP(lks, Pause); 696 XGBE_SET_SUP(lks, Asym_Pause); 697 XGBE_SET_SUP(lks, TP); 698 XGBE_SET_SUP(lks, FIBRE); 699 700 XGBE_LM_COPY(lks, advertising, lks, supported); 701 702 return; 703 } 704 705 switch (phy_data->sfp_base) { 706 case XGBE_SFP_BASE_1000_T: 707 case XGBE_SFP_BASE_1000_SX: 708 case XGBE_SFP_BASE_1000_LX: 709 case XGBE_SFP_BASE_1000_CX: 710 pdata->phy.speed = SPEED_UNKNOWN; 711 pdata->phy.duplex = DUPLEX_UNKNOWN; 712 pdata->phy.autoneg = AUTONEG_ENABLE; 713 pdata->phy.pause_autoneg = AUTONEG_ENABLE; 714 XGBE_SET_SUP(lks, Autoneg); 715 XGBE_SET_SUP(lks, Pause); 716 XGBE_SET_SUP(lks, Asym_Pause); 717 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T) { 718 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10) 719 XGBE_SET_SUP(lks, 10baseT_Full); 720 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) 721 XGBE_SET_SUP(lks, 100baseT_Full); 722 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) 723 XGBE_SET_SUP(lks, 1000baseT_Full); 724 } else { 725 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) 726 XGBE_SET_SUP(lks, 1000baseX_Full); 727 } 728 break; 729 case XGBE_SFP_BASE_10000_SR: 730 case XGBE_SFP_BASE_10000_LR: 731 case XGBE_SFP_BASE_10000_LRM: 732 case XGBE_SFP_BASE_10000_ER: 733 case XGBE_SFP_BASE_10000_CR: 734 pdata->phy.speed = SPEED_10000; 735 pdata->phy.duplex = DUPLEX_FULL; 736 pdata->phy.autoneg = AUTONEG_DISABLE; 737 pdata->phy.pause_autoneg = AUTONEG_DISABLE; 738 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) { 739 switch (phy_data->sfp_base) { 740 case XGBE_SFP_BASE_10000_SR: 741 XGBE_SET_SUP(lks, 10000baseSR_Full); 742 break; 743 case XGBE_SFP_BASE_10000_LR: 744 XGBE_SET_SUP(lks, 10000baseLR_Full); 745 break; 746 case XGBE_SFP_BASE_10000_LRM: 747 XGBE_SET_SUP(lks, 10000baseLRM_Full); 748 break; 749 case XGBE_SFP_BASE_10000_ER: 750 XGBE_SET_SUP(lks, 10000baseER_Full); 751 break; 752 case XGBE_SFP_BASE_10000_CR: 753 XGBE_SET_SUP(lks, 10000baseCR_Full); 754 break; 755 default: 756 break; 757 } 758 } 759 break; 760 default: 761 pdata->phy.speed = SPEED_UNKNOWN; 762 pdata->phy.duplex = DUPLEX_UNKNOWN; 763 pdata->phy.autoneg = AUTONEG_DISABLE; 764 pdata->phy.pause_autoneg = AUTONEG_DISABLE; 765 break; 766 } 767 768 switch (phy_data->sfp_base) { 769 case XGBE_SFP_BASE_1000_T: 770 case XGBE_SFP_BASE_1000_CX: 771 case XGBE_SFP_BASE_10000_CR: 772 XGBE_SET_SUP(lks, TP); 773 break; 774 default: 775 XGBE_SET_SUP(lks, FIBRE); 776 break; 777 } 778 779 XGBE_LM_COPY(lks, advertising, lks, supported); 780 } 781 782 static bool xgbe_phy_sfp_bit_rate(struct xgbe_sfp_eeprom *sfp_eeprom, 783 enum xgbe_sfp_speed sfp_speed) 784 { 785 u8 *sfp_base, min; 786 787 sfp_base = sfp_eeprom->base; 788 789 switch (sfp_speed) { 790 case XGBE_SFP_SPEED_1000: 791 min = XGBE_SFP_BASE_BR_1GBE_MIN; 792 break; 793 case XGBE_SFP_SPEED_10000: 794 min = XGBE_SFP_BASE_BR_10GBE_MIN; 795 break; 796 default: 797 return false; 798 } 799 800 return sfp_base[XGBE_SFP_BASE_BR] >= min; 801 } 802 803 static void xgbe_phy_free_phy_device(struct xgbe_prv_data *pdata) 804 { 805 struct xgbe_phy_data *phy_data = pdata->phy_data; 806 807 if (phy_data->phydev) { 808 phy_detach(phy_data->phydev); 809 phy_device_remove(phy_data->phydev); 810 phy_device_free(phy_data->phydev); 811 phy_data->phydev = NULL; 812 } 813 } 814 815 static bool xgbe_phy_finisar_phy_quirks(struct xgbe_prv_data *pdata) 816 { 817 struct xgbe_phy_data *phy_data = pdata->phy_data; 818 unsigned int phy_id = phy_data->phydev->phy_id; 819 820 if (phy_data->port_mode != XGBE_PORT_MODE_SFP) 821 return false; 822 823 if ((phy_id & 0xfffffff0) != 0x01ff0cc0) 824 return false; 825 826 /* Enable Base-T AN */ 827 phy_write(phy_data->phydev, 0x16, 0x0001); 828 phy_write(phy_data->phydev, 0x00, 0x9140); 829 phy_write(phy_data->phydev, 0x16, 0x0000); 830 831 /* Enable SGMII at 100Base-T/1000Base-T Full Duplex */ 832 phy_write(phy_data->phydev, 0x1b, 0x9084); 833 phy_write(phy_data->phydev, 0x09, 0x0e00); 834 phy_write(phy_data->phydev, 0x00, 0x8140); 835 phy_write(phy_data->phydev, 0x04, 0x0d01); 836 phy_write(phy_data->phydev, 0x00, 0x9140); 837 838 linkmode_copy(phy_data->phydev->supported, PHY_GBIT_FEATURES); 839 840 phy_support_asym_pause(phy_data->phydev); 841 842 netif_dbg(pdata, drv, pdata->netdev, 843 "Finisar PHY quirk in place\n"); 844 845 return true; 846 } 847 848 static bool xgbe_phy_belfuse_phy_quirks(struct xgbe_prv_data *pdata) 849 { 850 struct xgbe_phy_data *phy_data = pdata->phy_data; 851 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom; 852 unsigned int phy_id = phy_data->phydev->phy_id; 853 int reg; 854 855 if (phy_data->port_mode != XGBE_PORT_MODE_SFP) 856 return false; 857 858 if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME], 859 XGBE_BEL_FUSE_VENDOR, XGBE_SFP_BASE_VENDOR_NAME_LEN)) 860 return false; 861 862 /* For Bel-Fuse, use the extra AN flag */ 863 pdata->an_again = 1; 864 865 if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN], 866 XGBE_BEL_FUSE_PARTNO, XGBE_SFP_BASE_VENDOR_PN_LEN)) 867 return false; 868 869 if ((phy_id & 0xfffffff0) != 0x03625d10) 870 return false; 871 872 /* Reset PHY - wait for self-clearing reset bit to clear */ 873 genphy_soft_reset(phy_data->phydev); 874 875 /* Disable RGMII mode */ 876 phy_write(phy_data->phydev, 0x18, 0x7007); 877 reg = phy_read(phy_data->phydev, 0x18); 878 phy_write(phy_data->phydev, 0x18, reg & ~0x0080); 879 880 /* Enable fiber register bank */ 881 phy_write(phy_data->phydev, 0x1c, 0x7c00); 882 reg = phy_read(phy_data->phydev, 0x1c); 883 reg &= 0x03ff; 884 reg &= ~0x0001; 885 phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg | 0x0001); 886 887 /* Power down SerDes */ 888 reg = phy_read(phy_data->phydev, 0x00); 889 phy_write(phy_data->phydev, 0x00, reg | 0x00800); 890 891 /* Configure SGMII-to-Copper mode */ 892 phy_write(phy_data->phydev, 0x1c, 0x7c00); 893 reg = phy_read(phy_data->phydev, 0x1c); 894 reg &= 0x03ff; 895 reg &= ~0x0006; 896 phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg | 0x0004); 897 898 /* Power up SerDes */ 899 reg = phy_read(phy_data->phydev, 0x00); 900 phy_write(phy_data->phydev, 0x00, reg & ~0x00800); 901 902 /* Enable copper register bank */ 903 phy_write(phy_data->phydev, 0x1c, 0x7c00); 904 reg = phy_read(phy_data->phydev, 0x1c); 905 reg &= 0x03ff; 906 reg &= ~0x0001; 907 phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg); 908 909 /* Power up SerDes */ 910 reg = phy_read(phy_data->phydev, 0x00); 911 phy_write(phy_data->phydev, 0x00, reg & ~0x00800); 912 913 linkmode_copy(phy_data->phydev->supported, PHY_GBIT_FEATURES); 914 phy_support_asym_pause(phy_data->phydev); 915 916 netif_dbg(pdata, drv, pdata->netdev, 917 "BelFuse PHY quirk in place\n"); 918 919 return true; 920 } 921 922 static void xgbe_phy_external_phy_quirks(struct xgbe_prv_data *pdata) 923 { 924 if (xgbe_phy_belfuse_phy_quirks(pdata)) 925 return; 926 927 if (xgbe_phy_finisar_phy_quirks(pdata)) 928 return; 929 } 930 931 static int xgbe_phy_find_phy_device(struct xgbe_prv_data *pdata) 932 { 933 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 934 struct xgbe_phy_data *phy_data = pdata->phy_data; 935 struct phy_device *phydev; 936 int ret; 937 938 /* If we already have a PHY, just return */ 939 if (phy_data->phydev) 940 return 0; 941 942 /* Clear the extra AN flag */ 943 pdata->an_again = 0; 944 945 /* Check for the use of an external PHY */ 946 if (phy_data->phydev_mode == XGBE_MDIO_MODE_NONE) 947 return 0; 948 949 /* For SFP, only use an external PHY if available */ 950 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) && 951 !phy_data->sfp_phy_avail) 952 return 0; 953 954 /* Set the proper MDIO mode for the PHY */ 955 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr, 956 phy_data->phydev_mode); 957 if (ret) { 958 netdev_err(pdata->netdev, 959 "mdio port/clause not compatible (%u/%u)\n", 960 phy_data->mdio_addr, phy_data->phydev_mode); 961 return ret; 962 } 963 964 /* Create and connect to the PHY device */ 965 phydev = get_phy_device(phy_data->mii, phy_data->mdio_addr, 966 (phy_data->phydev_mode == XGBE_MDIO_MODE_CL45)); 967 if (IS_ERR(phydev)) { 968 netdev_err(pdata->netdev, "get_phy_device failed\n"); 969 return -ENODEV; 970 } 971 netif_dbg(pdata, drv, pdata->netdev, "external PHY id is %#010x\n", 972 phydev->phy_id); 973 974 /*TODO: If c45, add request_module based on one of the MMD ids? */ 975 976 ret = phy_device_register(phydev); 977 if (ret) { 978 netdev_err(pdata->netdev, "phy_device_register failed\n"); 979 phy_device_free(phydev); 980 return ret; 981 } 982 983 ret = phy_attach_direct(pdata->netdev, phydev, phydev->dev_flags, 984 PHY_INTERFACE_MODE_SGMII); 985 if (ret) { 986 netdev_err(pdata->netdev, "phy_attach_direct failed\n"); 987 phy_device_remove(phydev); 988 phy_device_free(phydev); 989 return ret; 990 } 991 phy_data->phydev = phydev; 992 phy_data->phydev->mac_managed_pm = true; 993 994 xgbe_phy_external_phy_quirks(pdata); 995 996 linkmode_and(phydev->advertising, phydev->advertising, 997 lks->link_modes.advertising); 998 999 phy_start_aneg(phy_data->phydev); 1000 1001 return 0; 1002 } 1003 1004 static void xgbe_phy_sfp_external_phy(struct xgbe_prv_data *pdata) 1005 { 1006 struct xgbe_phy_data *phy_data = pdata->phy_data; 1007 int ret; 1008 1009 if (!phy_data->sfp_changed) 1010 return; 1011 1012 phy_data->sfp_phy_avail = 0; 1013 1014 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T) 1015 return; 1016 1017 /* Check access to the PHY by reading CTRL1 */ 1018 ret = xgbe_phy_i2c_mii_read(pdata, MII_BMCR); 1019 if (ret < 0) 1020 return; 1021 1022 /* Successfully accessed the PHY */ 1023 phy_data->sfp_phy_avail = 1; 1024 } 1025 1026 static bool xgbe_phy_check_sfp_rx_los(struct xgbe_phy_data *phy_data) 1027 { 1028 u8 *sfp_extd = phy_data->sfp_eeprom.extd; 1029 1030 if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_RX_LOS)) 1031 return false; 1032 1033 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_RX_LOS) 1034 return false; 1035 1036 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_rx_los)) 1037 return true; 1038 1039 return false; 1040 } 1041 1042 static bool xgbe_phy_check_sfp_tx_fault(struct xgbe_phy_data *phy_data) 1043 { 1044 u8 *sfp_extd = phy_data->sfp_eeprom.extd; 1045 1046 if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_TX_FAULT)) 1047 return false; 1048 1049 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_TX_FAULT) 1050 return false; 1051 1052 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_tx_fault)) 1053 return true; 1054 1055 return false; 1056 } 1057 1058 static bool xgbe_phy_check_sfp_mod_absent(struct xgbe_phy_data *phy_data) 1059 { 1060 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_MOD_ABSENT) 1061 return false; 1062 1063 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_mod_absent)) 1064 return true; 1065 1066 return false; 1067 } 1068 1069 static void xgbe_phy_sfp_parse_eeprom(struct xgbe_prv_data *pdata) 1070 { 1071 struct xgbe_phy_data *phy_data = pdata->phy_data; 1072 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom; 1073 u8 *sfp_base; 1074 1075 sfp_base = sfp_eeprom->base; 1076 1077 if (sfp_base[XGBE_SFP_BASE_ID] != XGBE_SFP_ID_SFP) 1078 return; 1079 1080 if (sfp_base[XGBE_SFP_BASE_EXT_ID] != XGBE_SFP_EXT_ID_SFP) 1081 return; 1082 1083 /* Update transceiver signals (eeprom extd/options) */ 1084 phy_data->sfp_tx_fault = xgbe_phy_check_sfp_tx_fault(phy_data); 1085 phy_data->sfp_rx_los = xgbe_phy_check_sfp_rx_los(phy_data); 1086 1087 /* Assume FIBER cable unless told otherwise */ 1088 if (sfp_base[XGBE_SFP_BASE_CABLE] & XGBE_SFP_BASE_CABLE_PASSIVE) { 1089 phy_data->sfp_cable = XGBE_SFP_CABLE_PASSIVE; 1090 phy_data->sfp_cable_len = sfp_base[XGBE_SFP_BASE_CU_CABLE_LEN]; 1091 } else if (sfp_base[XGBE_SFP_BASE_CABLE] & XGBE_SFP_BASE_CABLE_ACTIVE) { 1092 phy_data->sfp_cable = XGBE_SFP_CABLE_ACTIVE; 1093 } else { 1094 phy_data->sfp_cable = XGBE_SFP_CABLE_FIBER; 1095 } 1096 1097 /* Determine the type of SFP */ 1098 if (phy_data->sfp_cable != XGBE_SFP_CABLE_FIBER && 1099 xgbe_phy_sfp_bit_rate(sfp_eeprom, XGBE_SFP_SPEED_10000)) 1100 phy_data->sfp_base = XGBE_SFP_BASE_10000_CR; 1101 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_SR) 1102 phy_data->sfp_base = XGBE_SFP_BASE_10000_SR; 1103 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LR) 1104 phy_data->sfp_base = XGBE_SFP_BASE_10000_LR; 1105 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LRM) 1106 phy_data->sfp_base = XGBE_SFP_BASE_10000_LRM; 1107 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_ER) 1108 phy_data->sfp_base = XGBE_SFP_BASE_10000_ER; 1109 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_SX) 1110 phy_data->sfp_base = XGBE_SFP_BASE_1000_SX; 1111 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_LX) 1112 phy_data->sfp_base = XGBE_SFP_BASE_1000_LX; 1113 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_CX) 1114 phy_data->sfp_base = XGBE_SFP_BASE_1000_CX; 1115 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_T) 1116 phy_data->sfp_base = XGBE_SFP_BASE_1000_T; 1117 1118 switch (phy_data->sfp_base) { 1119 case XGBE_SFP_BASE_1000_T: 1120 phy_data->sfp_speed = XGBE_SFP_SPEED_100_1000; 1121 break; 1122 case XGBE_SFP_BASE_1000_SX: 1123 case XGBE_SFP_BASE_1000_LX: 1124 case XGBE_SFP_BASE_1000_CX: 1125 phy_data->sfp_speed = XGBE_SFP_SPEED_1000; 1126 break; 1127 case XGBE_SFP_BASE_10000_SR: 1128 case XGBE_SFP_BASE_10000_LR: 1129 case XGBE_SFP_BASE_10000_LRM: 1130 case XGBE_SFP_BASE_10000_ER: 1131 case XGBE_SFP_BASE_10000_CR: 1132 phy_data->sfp_speed = XGBE_SFP_SPEED_10000; 1133 break; 1134 default: 1135 break; 1136 } 1137 } 1138 1139 static void xgbe_phy_sfp_eeprom_info(struct xgbe_prv_data *pdata, 1140 struct xgbe_sfp_eeprom *sfp_eeprom) 1141 { 1142 struct xgbe_sfp_ascii sfp_ascii; 1143 char *sfp_data = (char *)&sfp_ascii; 1144 1145 netif_dbg(pdata, drv, pdata->netdev, "SFP detected:\n"); 1146 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME], 1147 XGBE_SFP_BASE_VENDOR_NAME_LEN); 1148 sfp_data[XGBE_SFP_BASE_VENDOR_NAME_LEN] = '\0'; 1149 netif_dbg(pdata, drv, pdata->netdev, " vendor: %s\n", 1150 sfp_data); 1151 1152 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN], 1153 XGBE_SFP_BASE_VENDOR_PN_LEN); 1154 sfp_data[XGBE_SFP_BASE_VENDOR_PN_LEN] = '\0'; 1155 netif_dbg(pdata, drv, pdata->netdev, " part number: %s\n", 1156 sfp_data); 1157 1158 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_REV], 1159 XGBE_SFP_BASE_VENDOR_REV_LEN); 1160 sfp_data[XGBE_SFP_BASE_VENDOR_REV_LEN] = '\0'; 1161 netif_dbg(pdata, drv, pdata->netdev, " revision level: %s\n", 1162 sfp_data); 1163 1164 memcpy(sfp_data, &sfp_eeprom->extd[XGBE_SFP_BASE_VENDOR_SN], 1165 XGBE_SFP_BASE_VENDOR_SN_LEN); 1166 sfp_data[XGBE_SFP_BASE_VENDOR_SN_LEN] = '\0'; 1167 netif_dbg(pdata, drv, pdata->netdev, " serial number: %s\n", 1168 sfp_data); 1169 } 1170 1171 static bool xgbe_phy_sfp_verify_eeprom(u8 cc_in, u8 *buf, unsigned int len) 1172 { 1173 u8 cc; 1174 1175 for (cc = 0; len; buf++, len--) 1176 cc += *buf; 1177 1178 return cc == cc_in; 1179 } 1180 1181 static int xgbe_phy_sfp_read_eeprom(struct xgbe_prv_data *pdata) 1182 { 1183 struct xgbe_phy_data *phy_data = pdata->phy_data; 1184 struct xgbe_sfp_eeprom sfp_eeprom; 1185 u8 eeprom_addr; 1186 int ret; 1187 1188 ret = xgbe_phy_sfp_get_mux(pdata); 1189 if (ret) { 1190 dev_err_once(pdata->dev, "%s: I2C error setting SFP MUX\n", 1191 netdev_name(pdata->netdev)); 1192 return ret; 1193 } 1194 1195 /* Read the SFP serial ID eeprom */ 1196 eeprom_addr = 0; 1197 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS, 1198 &eeprom_addr, sizeof(eeprom_addr), 1199 &sfp_eeprom, sizeof(sfp_eeprom)); 1200 if (ret) { 1201 dev_err_once(pdata->dev, "%s: I2C error reading SFP EEPROM\n", 1202 netdev_name(pdata->netdev)); 1203 goto put; 1204 } 1205 1206 /* Validate the contents read */ 1207 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.base[XGBE_SFP_BASE_CC], 1208 sfp_eeprom.base, 1209 sizeof(sfp_eeprom.base) - 1)) { 1210 ret = -EINVAL; 1211 goto put; 1212 } 1213 1214 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.extd[XGBE_SFP_EXTD_CC], 1215 sfp_eeprom.extd, 1216 sizeof(sfp_eeprom.extd) - 1)) { 1217 ret = -EINVAL; 1218 goto put; 1219 } 1220 1221 /* Check for an added or changed SFP */ 1222 if (memcmp(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom))) { 1223 phy_data->sfp_changed = 1; 1224 1225 if (netif_msg_drv(pdata)) 1226 xgbe_phy_sfp_eeprom_info(pdata, &sfp_eeprom); 1227 1228 memcpy(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom)); 1229 1230 xgbe_phy_free_phy_device(pdata); 1231 } else { 1232 phy_data->sfp_changed = 0; 1233 } 1234 1235 put: 1236 xgbe_phy_sfp_put_mux(pdata); 1237 1238 return ret; 1239 } 1240 1241 static void xgbe_phy_sfp_signals(struct xgbe_prv_data *pdata) 1242 { 1243 struct xgbe_phy_data *phy_data = pdata->phy_data; 1244 u8 gpio_reg, gpio_ports[2]; 1245 int ret; 1246 1247 /* Read the input port registers */ 1248 gpio_reg = 0; 1249 ret = xgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address, 1250 &gpio_reg, sizeof(gpio_reg), 1251 gpio_ports, sizeof(gpio_ports)); 1252 if (ret) { 1253 dev_err_once(pdata->dev, "%s: I2C error reading SFP GPIOs\n", 1254 netdev_name(pdata->netdev)); 1255 return; 1256 } 1257 1258 phy_data->sfp_gpio_inputs = (gpio_ports[1] << 8) | gpio_ports[0]; 1259 1260 phy_data->sfp_mod_absent = xgbe_phy_check_sfp_mod_absent(phy_data); 1261 } 1262 1263 static void xgbe_phy_sfp_mod_absent(struct xgbe_prv_data *pdata) 1264 { 1265 struct xgbe_phy_data *phy_data = pdata->phy_data; 1266 1267 xgbe_phy_free_phy_device(pdata); 1268 1269 phy_data->sfp_mod_absent = 1; 1270 phy_data->sfp_phy_avail = 0; 1271 memset(&phy_data->sfp_eeprom, 0, sizeof(phy_data->sfp_eeprom)); 1272 } 1273 1274 static void xgbe_phy_sfp_reset(struct xgbe_phy_data *phy_data) 1275 { 1276 phy_data->sfp_rx_los = 0; 1277 phy_data->sfp_tx_fault = 0; 1278 phy_data->sfp_mod_absent = 1; 1279 phy_data->sfp_base = XGBE_SFP_BASE_UNKNOWN; 1280 phy_data->sfp_cable = XGBE_SFP_CABLE_UNKNOWN; 1281 phy_data->sfp_speed = XGBE_SFP_SPEED_UNKNOWN; 1282 } 1283 1284 static void xgbe_phy_sfp_detect(struct xgbe_prv_data *pdata) 1285 { 1286 struct xgbe_phy_data *phy_data = pdata->phy_data; 1287 int ret; 1288 1289 /* Reset the SFP signals and info */ 1290 xgbe_phy_sfp_reset(phy_data); 1291 1292 ret = xgbe_phy_get_comm_ownership(pdata); 1293 if (ret) 1294 return; 1295 1296 /* Read the SFP signals and check for module presence */ 1297 xgbe_phy_sfp_signals(pdata); 1298 if (phy_data->sfp_mod_absent) { 1299 xgbe_phy_sfp_mod_absent(pdata); 1300 goto put; 1301 } 1302 1303 ret = xgbe_phy_sfp_read_eeprom(pdata); 1304 if (ret) { 1305 /* Treat any error as if there isn't an SFP plugged in */ 1306 xgbe_phy_sfp_reset(phy_data); 1307 xgbe_phy_sfp_mod_absent(pdata); 1308 goto put; 1309 } 1310 1311 xgbe_phy_sfp_parse_eeprom(pdata); 1312 1313 xgbe_phy_sfp_external_phy(pdata); 1314 1315 put: 1316 xgbe_phy_sfp_phy_settings(pdata); 1317 1318 xgbe_phy_put_comm_ownership(pdata); 1319 } 1320 1321 static int xgbe_phy_module_eeprom(struct xgbe_prv_data *pdata, 1322 struct ethtool_eeprom *eeprom, u8 *data) 1323 { 1324 struct xgbe_phy_data *phy_data = pdata->phy_data; 1325 u8 eeprom_addr, eeprom_data[XGBE_SFP_EEPROM_MAX]; 1326 struct xgbe_sfp_eeprom *sfp_eeprom; 1327 unsigned int i, j, rem; 1328 int ret; 1329 1330 rem = eeprom->len; 1331 1332 if (!eeprom->len) { 1333 ret = -EINVAL; 1334 goto done; 1335 } 1336 1337 if ((eeprom->offset + eeprom->len) > XGBE_SFP_EEPROM_MAX) { 1338 ret = -EINVAL; 1339 goto done; 1340 } 1341 1342 if (phy_data->port_mode != XGBE_PORT_MODE_SFP) { 1343 ret = -ENXIO; 1344 goto done; 1345 } 1346 1347 if (!netif_running(pdata->netdev)) { 1348 ret = -EIO; 1349 goto done; 1350 } 1351 1352 if (phy_data->sfp_mod_absent) { 1353 ret = -EIO; 1354 goto done; 1355 } 1356 1357 ret = xgbe_phy_get_comm_ownership(pdata); 1358 if (ret) { 1359 ret = -EIO; 1360 goto done; 1361 } 1362 1363 ret = xgbe_phy_sfp_get_mux(pdata); 1364 if (ret) { 1365 netdev_err(pdata->netdev, "I2C error setting SFP MUX\n"); 1366 ret = -EIO; 1367 goto put_own; 1368 } 1369 1370 /* Read the SFP serial ID eeprom */ 1371 eeprom_addr = 0; 1372 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS, 1373 &eeprom_addr, sizeof(eeprom_addr), 1374 eeprom_data, XGBE_SFP_EEPROM_BASE_LEN); 1375 if (ret) { 1376 netdev_err(pdata->netdev, 1377 "I2C error reading SFP EEPROM\n"); 1378 ret = -EIO; 1379 goto put_mux; 1380 } 1381 1382 sfp_eeprom = (struct xgbe_sfp_eeprom *)eeprom_data; 1383 1384 if (XGBE_SFP_DIAGS_SUPPORTED(sfp_eeprom)) { 1385 /* Read the SFP diagnostic eeprom */ 1386 eeprom_addr = 0; 1387 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_DIAG_INFO_ADDRESS, 1388 &eeprom_addr, sizeof(eeprom_addr), 1389 eeprom_data + XGBE_SFP_EEPROM_BASE_LEN, 1390 XGBE_SFP_EEPROM_DIAG_LEN); 1391 if (ret) { 1392 netdev_err(pdata->netdev, 1393 "I2C error reading SFP DIAGS\n"); 1394 ret = -EIO; 1395 goto put_mux; 1396 } 1397 } 1398 1399 for (i = 0, j = eeprom->offset; i < eeprom->len; i++, j++) { 1400 if ((j >= XGBE_SFP_EEPROM_BASE_LEN) && 1401 !XGBE_SFP_DIAGS_SUPPORTED(sfp_eeprom)) 1402 break; 1403 1404 data[i] = eeprom_data[j]; 1405 rem--; 1406 } 1407 1408 put_mux: 1409 xgbe_phy_sfp_put_mux(pdata); 1410 1411 put_own: 1412 xgbe_phy_put_comm_ownership(pdata); 1413 1414 done: 1415 eeprom->len -= rem; 1416 1417 return ret; 1418 } 1419 1420 static int xgbe_phy_module_info(struct xgbe_prv_data *pdata, 1421 struct ethtool_modinfo *modinfo) 1422 { 1423 struct xgbe_phy_data *phy_data = pdata->phy_data; 1424 1425 if (phy_data->port_mode != XGBE_PORT_MODE_SFP) 1426 return -ENXIO; 1427 1428 if (!netif_running(pdata->netdev)) 1429 return -EIO; 1430 1431 if (phy_data->sfp_mod_absent) 1432 return -EIO; 1433 1434 if (XGBE_SFP_DIAGS_SUPPORTED(&phy_data->sfp_eeprom)) { 1435 modinfo->type = ETH_MODULE_SFF_8472; 1436 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 1437 } else { 1438 modinfo->type = ETH_MODULE_SFF_8079; 1439 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN; 1440 } 1441 1442 return 0; 1443 } 1444 1445 static void xgbe_phy_phydev_flowctrl(struct xgbe_prv_data *pdata) 1446 { 1447 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1448 struct xgbe_phy_data *phy_data = pdata->phy_data; 1449 u16 lcl_adv = 0, rmt_adv = 0; 1450 u8 fc; 1451 1452 pdata->phy.tx_pause = 0; 1453 pdata->phy.rx_pause = 0; 1454 1455 if (!phy_data->phydev) 1456 return; 1457 1458 lcl_adv = linkmode_adv_to_lcl_adv_t(phy_data->phydev->advertising); 1459 1460 if (phy_data->phydev->pause) { 1461 XGBE_SET_LP_ADV(lks, Pause); 1462 rmt_adv |= LPA_PAUSE_CAP; 1463 } 1464 if (phy_data->phydev->asym_pause) { 1465 XGBE_SET_LP_ADV(lks, Asym_Pause); 1466 rmt_adv |= LPA_PAUSE_ASYM; 1467 } 1468 1469 fc = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); 1470 if (fc & FLOW_CTRL_TX) 1471 pdata->phy.tx_pause = 1; 1472 if (fc & FLOW_CTRL_RX) 1473 pdata->phy.rx_pause = 1; 1474 } 1475 1476 static enum xgbe_mode xgbe_phy_an37_sgmii_outcome(struct xgbe_prv_data *pdata) 1477 { 1478 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1479 enum xgbe_mode mode; 1480 1481 XGBE_SET_LP_ADV(lks, Autoneg); 1482 XGBE_SET_LP_ADV(lks, TP); 1483 1484 /* Use external PHY to determine flow control */ 1485 if (pdata->phy.pause_autoneg) 1486 xgbe_phy_phydev_flowctrl(pdata); 1487 1488 switch (pdata->an_status & XGBE_SGMII_AN_LINK_SPEED) { 1489 case XGBE_SGMII_AN_LINK_SPEED_10: 1490 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) { 1491 XGBE_SET_LP_ADV(lks, 10baseT_Full); 1492 mode = XGBE_MODE_SGMII_10; 1493 } else { 1494 /* Half-duplex not supported */ 1495 XGBE_SET_LP_ADV(lks, 10baseT_Half); 1496 mode = XGBE_MODE_UNKNOWN; 1497 } 1498 break; 1499 case XGBE_SGMII_AN_LINK_SPEED_100: 1500 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) { 1501 XGBE_SET_LP_ADV(lks, 100baseT_Full); 1502 mode = XGBE_MODE_SGMII_100; 1503 } else { 1504 /* Half-duplex not supported */ 1505 XGBE_SET_LP_ADV(lks, 100baseT_Half); 1506 mode = XGBE_MODE_UNKNOWN; 1507 } 1508 break; 1509 case XGBE_SGMII_AN_LINK_SPEED_1000: 1510 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) { 1511 XGBE_SET_LP_ADV(lks, 1000baseT_Full); 1512 mode = XGBE_MODE_SGMII_1000; 1513 } else { 1514 /* Half-duplex not supported */ 1515 XGBE_SET_LP_ADV(lks, 1000baseT_Half); 1516 mode = XGBE_MODE_UNKNOWN; 1517 } 1518 break; 1519 default: 1520 mode = XGBE_MODE_UNKNOWN; 1521 } 1522 1523 return mode; 1524 } 1525 1526 static enum xgbe_mode xgbe_phy_an37_outcome(struct xgbe_prv_data *pdata) 1527 { 1528 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1529 enum xgbe_mode mode; 1530 unsigned int ad_reg, lp_reg; 1531 1532 XGBE_SET_LP_ADV(lks, Autoneg); 1533 XGBE_SET_LP_ADV(lks, FIBRE); 1534 1535 /* Compare Advertisement and Link Partner register */ 1536 ad_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE); 1537 lp_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_LP_ABILITY); 1538 if (lp_reg & 0x100) 1539 XGBE_SET_LP_ADV(lks, Pause); 1540 if (lp_reg & 0x80) 1541 XGBE_SET_LP_ADV(lks, Asym_Pause); 1542 1543 if (pdata->phy.pause_autoneg) { 1544 /* Set flow control based on auto-negotiation result */ 1545 pdata->phy.tx_pause = 0; 1546 pdata->phy.rx_pause = 0; 1547 1548 if (ad_reg & lp_reg & 0x100) { 1549 pdata->phy.tx_pause = 1; 1550 pdata->phy.rx_pause = 1; 1551 } else if (ad_reg & lp_reg & 0x80) { 1552 if (ad_reg & 0x100) 1553 pdata->phy.rx_pause = 1; 1554 else if (lp_reg & 0x100) 1555 pdata->phy.tx_pause = 1; 1556 } 1557 } 1558 1559 if (lp_reg & 0x20) 1560 XGBE_SET_LP_ADV(lks, 1000baseX_Full); 1561 1562 /* Half duplex is not supported */ 1563 ad_reg &= lp_reg; 1564 mode = (ad_reg & 0x20) ? XGBE_MODE_X : XGBE_MODE_UNKNOWN; 1565 1566 return mode; 1567 } 1568 1569 static enum xgbe_mode xgbe_phy_an73_redrv_outcome(struct xgbe_prv_data *pdata) 1570 { 1571 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1572 struct xgbe_phy_data *phy_data = pdata->phy_data; 1573 enum xgbe_mode mode; 1574 unsigned int ad_reg, lp_reg; 1575 1576 XGBE_SET_LP_ADV(lks, Autoneg); 1577 XGBE_SET_LP_ADV(lks, Backplane); 1578 1579 /* Use external PHY to determine flow control */ 1580 if (pdata->phy.pause_autoneg) 1581 xgbe_phy_phydev_flowctrl(pdata); 1582 1583 /* Compare Advertisement and Link Partner register 2 */ 1584 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); 1585 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); 1586 if (lp_reg & 0x80) 1587 XGBE_SET_LP_ADV(lks, 10000baseKR_Full); 1588 if (lp_reg & 0x20) 1589 XGBE_SET_LP_ADV(lks, 1000baseKX_Full); 1590 1591 ad_reg &= lp_reg; 1592 if (ad_reg & 0x80) { 1593 switch (phy_data->port_mode) { 1594 case XGBE_PORT_MODE_BACKPLANE: 1595 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 1596 mode = XGBE_MODE_KR; 1597 break; 1598 default: 1599 mode = XGBE_MODE_SFI; 1600 break; 1601 } 1602 } else if (ad_reg & 0x20) { 1603 switch (phy_data->port_mode) { 1604 case XGBE_PORT_MODE_BACKPLANE: 1605 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 1606 mode = XGBE_MODE_KX_1000; 1607 break; 1608 case XGBE_PORT_MODE_1000BASE_X: 1609 mode = XGBE_MODE_X; 1610 break; 1611 case XGBE_PORT_MODE_SFP: 1612 switch (phy_data->sfp_base) { 1613 case XGBE_SFP_BASE_1000_T: 1614 if (phy_data->phydev && 1615 (phy_data->phydev->speed == SPEED_10)) 1616 mode = XGBE_MODE_SGMII_10; 1617 else if (phy_data->phydev && 1618 (phy_data->phydev->speed == SPEED_100)) 1619 mode = XGBE_MODE_SGMII_100; 1620 else 1621 mode = XGBE_MODE_SGMII_1000; 1622 break; 1623 case XGBE_SFP_BASE_1000_SX: 1624 case XGBE_SFP_BASE_1000_LX: 1625 case XGBE_SFP_BASE_1000_CX: 1626 default: 1627 mode = XGBE_MODE_X; 1628 break; 1629 } 1630 break; 1631 default: 1632 if (phy_data->phydev && 1633 (phy_data->phydev->speed == SPEED_10)) 1634 mode = XGBE_MODE_SGMII_10; 1635 else if (phy_data->phydev && 1636 (phy_data->phydev->speed == SPEED_100)) 1637 mode = XGBE_MODE_SGMII_100; 1638 else 1639 mode = XGBE_MODE_SGMII_1000; 1640 break; 1641 } 1642 } else { 1643 mode = XGBE_MODE_UNKNOWN; 1644 } 1645 1646 /* Compare Advertisement and Link Partner register 3 */ 1647 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); 1648 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); 1649 if (lp_reg & 0xc000) 1650 XGBE_SET_LP_ADV(lks, 10000baseR_FEC); 1651 1652 return mode; 1653 } 1654 1655 static enum xgbe_mode xgbe_phy_an73_outcome(struct xgbe_prv_data *pdata) 1656 { 1657 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1658 enum xgbe_mode mode; 1659 unsigned int ad_reg, lp_reg; 1660 1661 XGBE_SET_LP_ADV(lks, Autoneg); 1662 XGBE_SET_LP_ADV(lks, Backplane); 1663 1664 /* Compare Advertisement and Link Partner register 1 */ 1665 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE); 1666 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA); 1667 if (lp_reg & 0x400) 1668 XGBE_SET_LP_ADV(lks, Pause); 1669 if (lp_reg & 0x800) 1670 XGBE_SET_LP_ADV(lks, Asym_Pause); 1671 1672 if (pdata->phy.pause_autoneg) { 1673 /* Set flow control based on auto-negotiation result */ 1674 pdata->phy.tx_pause = 0; 1675 pdata->phy.rx_pause = 0; 1676 1677 if (ad_reg & lp_reg & 0x400) { 1678 pdata->phy.tx_pause = 1; 1679 pdata->phy.rx_pause = 1; 1680 } else if (ad_reg & lp_reg & 0x800) { 1681 if (ad_reg & 0x400) 1682 pdata->phy.rx_pause = 1; 1683 else if (lp_reg & 0x400) 1684 pdata->phy.tx_pause = 1; 1685 } 1686 } 1687 1688 /* Compare Advertisement and Link Partner register 2 */ 1689 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); 1690 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); 1691 if (lp_reg & 0x80) 1692 XGBE_SET_LP_ADV(lks, 10000baseKR_Full); 1693 if (lp_reg & 0x20) 1694 XGBE_SET_LP_ADV(lks, 1000baseKX_Full); 1695 1696 ad_reg &= lp_reg; 1697 if (ad_reg & 0x80) 1698 mode = XGBE_MODE_KR; 1699 else if (ad_reg & 0x20) 1700 mode = XGBE_MODE_KX_1000; 1701 else 1702 mode = XGBE_MODE_UNKNOWN; 1703 1704 /* Compare Advertisement and Link Partner register 3 */ 1705 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); 1706 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); 1707 if (lp_reg & 0xc000) 1708 XGBE_SET_LP_ADV(lks, 10000baseR_FEC); 1709 1710 return mode; 1711 } 1712 1713 static enum xgbe_mode xgbe_phy_an_outcome(struct xgbe_prv_data *pdata) 1714 { 1715 switch (pdata->an_mode) { 1716 case XGBE_AN_MODE_CL73: 1717 return xgbe_phy_an73_outcome(pdata); 1718 case XGBE_AN_MODE_CL73_REDRV: 1719 return xgbe_phy_an73_redrv_outcome(pdata); 1720 case XGBE_AN_MODE_CL37: 1721 return xgbe_phy_an37_outcome(pdata); 1722 case XGBE_AN_MODE_CL37_SGMII: 1723 return xgbe_phy_an37_sgmii_outcome(pdata); 1724 default: 1725 return XGBE_MODE_UNKNOWN; 1726 } 1727 } 1728 1729 static void xgbe_phy_an_advertising(struct xgbe_prv_data *pdata, 1730 struct ethtool_link_ksettings *dlks) 1731 { 1732 struct ethtool_link_ksettings *slks = &pdata->phy.lks; 1733 struct xgbe_phy_data *phy_data = pdata->phy_data; 1734 1735 XGBE_LM_COPY(dlks, advertising, slks, advertising); 1736 1737 /* Without a re-driver, just return current advertising */ 1738 if (!phy_data->redrv) 1739 return; 1740 1741 /* With the KR re-driver we need to advertise a single speed */ 1742 XGBE_CLR_ADV(dlks, 1000baseKX_Full); 1743 XGBE_CLR_ADV(dlks, 10000baseKR_Full); 1744 1745 /* Advertise FEC support is present */ 1746 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 1747 XGBE_SET_ADV(dlks, 10000baseR_FEC); 1748 1749 switch (phy_data->port_mode) { 1750 case XGBE_PORT_MODE_BACKPLANE: 1751 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 1752 XGBE_SET_ADV(dlks, 10000baseKR_Full); 1753 break; 1754 case XGBE_PORT_MODE_BACKPLANE_2500: 1755 XGBE_SET_ADV(dlks, 1000baseKX_Full); 1756 break; 1757 case XGBE_PORT_MODE_1000BASE_T: 1758 case XGBE_PORT_MODE_1000BASE_X: 1759 case XGBE_PORT_MODE_NBASE_T: 1760 XGBE_SET_ADV(dlks, 1000baseKX_Full); 1761 break; 1762 case XGBE_PORT_MODE_10GBASE_T: 1763 if (phy_data->phydev && 1764 (phy_data->phydev->speed == SPEED_10000)) 1765 XGBE_SET_ADV(dlks, 10000baseKR_Full); 1766 else if (phy_data->phydev && 1767 (phy_data->phydev->speed == SPEED_2500)) 1768 XGBE_SET_ADV(dlks, 2500baseX_Full); 1769 else 1770 XGBE_SET_ADV(dlks, 1000baseKX_Full); 1771 break; 1772 case XGBE_PORT_MODE_10GBASE_R: 1773 XGBE_SET_ADV(dlks, 10000baseKR_Full); 1774 break; 1775 case XGBE_PORT_MODE_SFP: 1776 switch (phy_data->sfp_base) { 1777 case XGBE_SFP_BASE_1000_T: 1778 case XGBE_SFP_BASE_1000_SX: 1779 case XGBE_SFP_BASE_1000_LX: 1780 case XGBE_SFP_BASE_1000_CX: 1781 XGBE_SET_ADV(dlks, 1000baseKX_Full); 1782 break; 1783 default: 1784 XGBE_SET_ADV(dlks, 10000baseKR_Full); 1785 break; 1786 } 1787 break; 1788 default: 1789 XGBE_SET_ADV(dlks, 10000baseKR_Full); 1790 break; 1791 } 1792 } 1793 1794 static int xgbe_phy_an_config(struct xgbe_prv_data *pdata) 1795 { 1796 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1797 struct xgbe_phy_data *phy_data = pdata->phy_data; 1798 int ret; 1799 1800 ret = xgbe_phy_find_phy_device(pdata); 1801 if (ret) 1802 return ret; 1803 1804 if (!phy_data->phydev) 1805 return 0; 1806 1807 phy_data->phydev->autoneg = pdata->phy.autoneg; 1808 linkmode_and(phy_data->phydev->advertising, 1809 phy_data->phydev->supported, 1810 lks->link_modes.advertising); 1811 1812 if (pdata->phy.autoneg != AUTONEG_ENABLE) { 1813 phy_data->phydev->speed = pdata->phy.speed; 1814 phy_data->phydev->duplex = pdata->phy.duplex; 1815 } 1816 1817 ret = phy_start_aneg(phy_data->phydev); 1818 1819 return ret; 1820 } 1821 1822 static enum xgbe_an_mode xgbe_phy_an_sfp_mode(struct xgbe_phy_data *phy_data) 1823 { 1824 switch (phy_data->sfp_base) { 1825 case XGBE_SFP_BASE_1000_T: 1826 return XGBE_AN_MODE_CL37_SGMII; 1827 case XGBE_SFP_BASE_1000_SX: 1828 case XGBE_SFP_BASE_1000_LX: 1829 case XGBE_SFP_BASE_1000_CX: 1830 return XGBE_AN_MODE_CL37; 1831 default: 1832 return XGBE_AN_MODE_NONE; 1833 } 1834 } 1835 1836 static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata) 1837 { 1838 struct xgbe_phy_data *phy_data = pdata->phy_data; 1839 1840 /* A KR re-driver will always require CL73 AN */ 1841 if (phy_data->redrv) 1842 return XGBE_AN_MODE_CL73_REDRV; 1843 1844 switch (phy_data->port_mode) { 1845 case XGBE_PORT_MODE_BACKPLANE: 1846 return XGBE_AN_MODE_CL73; 1847 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 1848 case XGBE_PORT_MODE_BACKPLANE_2500: 1849 return XGBE_AN_MODE_NONE; 1850 case XGBE_PORT_MODE_1000BASE_T: 1851 return XGBE_AN_MODE_CL37_SGMII; 1852 case XGBE_PORT_MODE_1000BASE_X: 1853 return XGBE_AN_MODE_CL37; 1854 case XGBE_PORT_MODE_NBASE_T: 1855 return XGBE_AN_MODE_CL37_SGMII; 1856 case XGBE_PORT_MODE_10GBASE_T: 1857 return XGBE_AN_MODE_CL73; 1858 case XGBE_PORT_MODE_10GBASE_R: 1859 return XGBE_AN_MODE_NONE; 1860 case XGBE_PORT_MODE_SFP: 1861 return xgbe_phy_an_sfp_mode(phy_data); 1862 default: 1863 return XGBE_AN_MODE_NONE; 1864 } 1865 } 1866 1867 static int xgbe_phy_set_redrv_mode_mdio(struct xgbe_prv_data *pdata, 1868 enum xgbe_phy_redrv_mode mode) 1869 { 1870 struct xgbe_phy_data *phy_data = pdata->phy_data; 1871 u16 redrv_reg, redrv_val; 1872 1873 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000); 1874 redrv_val = (u16)mode; 1875 1876 return pdata->hw_if.write_ext_mii_regs_c22(pdata, phy_data->redrv_addr, 1877 redrv_reg, redrv_val); 1878 } 1879 1880 static int xgbe_phy_set_redrv_mode_i2c(struct xgbe_prv_data *pdata, 1881 enum xgbe_phy_redrv_mode mode) 1882 { 1883 struct xgbe_phy_data *phy_data = pdata->phy_data; 1884 unsigned int redrv_reg; 1885 int ret; 1886 1887 /* Calculate the register to write */ 1888 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000); 1889 1890 ret = xgbe_phy_redrv_write(pdata, redrv_reg, mode); 1891 1892 return ret; 1893 } 1894 1895 static void xgbe_phy_set_redrv_mode(struct xgbe_prv_data *pdata) 1896 { 1897 struct xgbe_phy_data *phy_data = pdata->phy_data; 1898 enum xgbe_phy_redrv_mode mode; 1899 int ret; 1900 1901 if (!phy_data->redrv) 1902 return; 1903 1904 mode = XGBE_PHY_REDRV_MODE_CX; 1905 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) && 1906 (phy_data->sfp_base != XGBE_SFP_BASE_1000_CX) && 1907 (phy_data->sfp_base != XGBE_SFP_BASE_10000_CR)) 1908 mode = XGBE_PHY_REDRV_MODE_SR; 1909 1910 ret = xgbe_phy_get_comm_ownership(pdata); 1911 if (ret) 1912 return; 1913 1914 if (phy_data->redrv_if) 1915 xgbe_phy_set_redrv_mode_i2c(pdata, mode); 1916 else 1917 xgbe_phy_set_redrv_mode_mdio(pdata, mode); 1918 1919 xgbe_phy_put_comm_ownership(pdata); 1920 } 1921 1922 #define MAX_RX_ADAPT_RETRIES 1 1923 #define XGBE_PMA_RX_VAL_SIG_MASK (XGBE_PMA_RX_SIG_DET_0_MASK | \ 1924 XGBE_PMA_RX_VALID_0_MASK) 1925 1926 static void xgbe_set_rx_adap_mode(struct xgbe_prv_data *pdata, 1927 enum xgbe_mode mode) 1928 { 1929 if (pdata->rx_adapt_retries++ >= MAX_RX_ADAPT_RETRIES) { 1930 pdata->rx_adapt_retries = 0; 1931 pdata->mode_set = false; 1932 return; 1933 } 1934 1935 xgbe_phy_perform_ratechange(pdata, 1936 mode == XGBE_MODE_KR ? 1937 XGBE_MB_CMD_SET_10G_KR : 1938 XGBE_MB_CMD_SET_10G_SFI, 1939 XGBE_MB_SUBCMD_RX_ADAP); 1940 } 1941 1942 static void xgbe_rx_adaptation(struct xgbe_prv_data *pdata) 1943 { 1944 struct xgbe_phy_data *phy_data = pdata->phy_data; 1945 unsigned int reg; 1946 1947 /* step 2: force PCS to send RX_ADAPT Req to PHY */ 1948 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_EQ_CTRL4, 1949 XGBE_PMA_RX_AD_REQ_MASK, XGBE_PMA_RX_AD_REQ_ENABLE); 1950 1951 /* Step 3: Wait for RX_ADAPT ACK from the PHY */ 1952 msleep(200); 1953 1954 /* Software polls for coefficient update command (given by local PHY) */ 1955 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_PHY_RX_EQ_CEU); 1956 1957 /* Clear the RX_AD_REQ bit */ 1958 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_EQ_CTRL4, 1959 XGBE_PMA_RX_AD_REQ_MASK, XGBE_PMA_RX_AD_REQ_DISABLE); 1960 1961 /* Check if coefficient update command is set */ 1962 if ((reg & XGBE_PMA_CFF_UPDT_MASK) != XGBE_PMA_CFF_UPDT_MASK) 1963 goto set_mode; 1964 1965 /* Step 4: Check for Block lock */ 1966 1967 /* Link status is latched low, so read once to clear 1968 * and then read again to get current state 1969 */ 1970 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); 1971 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); 1972 if (reg & MDIO_STAT1_LSTATUS) { 1973 /* If the block lock is found, update the helpers 1974 * and declare the link up 1975 */ 1976 netif_dbg(pdata, link, pdata->netdev, "Block_lock done"); 1977 pdata->rx_adapt_done = true; 1978 pdata->rx_adapt_retries = 0; 1979 pdata->mode_set = false; 1980 return; 1981 } 1982 1983 set_mode: 1984 xgbe_set_rx_adap_mode(pdata, phy_data->cur_mode); 1985 } 1986 1987 static void xgbe_phy_rx_adaptation(struct xgbe_prv_data *pdata) 1988 { 1989 unsigned int reg; 1990 1991 rx_adapt_reinit: 1992 reg = XMDIO_READ_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_LSTS, 1993 XGBE_PMA_RX_VAL_SIG_MASK); 1994 1995 /* step 1: Check for RX_VALID && LF_SIGDET */ 1996 if ((reg & XGBE_PMA_RX_VAL_SIG_MASK) != XGBE_PMA_RX_VAL_SIG_MASK) { 1997 netif_dbg(pdata, link, pdata->netdev, 1998 "RX_VALID or LF_SIGDET is unset, issue rrc"); 1999 xgbe_phy_rrc(pdata); 2000 if (pdata->rx_adapt_retries++ >= MAX_RX_ADAPT_RETRIES) { 2001 pdata->rx_adapt_retries = 0; 2002 return; 2003 } 2004 goto rx_adapt_reinit; 2005 } 2006 2007 /* perform rx adaptation */ 2008 xgbe_rx_adaptation(pdata); 2009 } 2010 2011 static void xgbe_phy_rx_reset(struct xgbe_prv_data *pdata) 2012 { 2013 int reg; 2014 2015 reg = XMDIO_READ_BITS(pdata, MDIO_MMD_PCS, MDIO_PCS_DIGITAL_STAT, 2016 XGBE_PCS_PSEQ_STATE_MASK); 2017 if (reg == XGBE_PCS_PSEQ_STATE_POWER_GOOD) { 2018 /* Mailbox command timed out, reset of RX block is required. 2019 * This can be done by asseting the reset bit and wait for 2020 * its compeletion. 2021 */ 2022 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1, 2023 XGBE_PMA_RX_RST_0_MASK, XGBE_PMA_RX_RST_0_RESET_ON); 2024 ndelay(20); 2025 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1, 2026 XGBE_PMA_RX_RST_0_MASK, XGBE_PMA_RX_RST_0_RESET_OFF); 2027 usleep_range(40, 50); 2028 netif_err(pdata, link, pdata->netdev, "firmware mailbox reset performed\n"); 2029 } 2030 } 2031 2032 static void xgbe_phy_pll_ctrl(struct xgbe_prv_data *pdata, bool enable) 2033 { 2034 /* PLL_CTRL feature needs to be enabled for fixed PHY modes (Non-Autoneg) only */ 2035 if (pdata->phy.autoneg != AUTONEG_DISABLE) 2036 return; 2037 2038 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_MISC_CTRL0, 2039 XGBE_PMA_PLL_CTRL_MASK, 2040 enable ? XGBE_PMA_PLL_CTRL_ENABLE 2041 : XGBE_PMA_PLL_CTRL_DISABLE); 2042 2043 /* Wait for command to complete */ 2044 usleep_range(100, 200); 2045 } 2046 2047 static void xgbe_phy_perform_ratechange(struct xgbe_prv_data *pdata, 2048 enum xgbe_mb_cmd cmd, enum xgbe_mb_subcmd sub_cmd) 2049 { 2050 unsigned int s0 = 0; 2051 unsigned int wait; 2052 2053 /* Disable PLL re-initialization during FW command processing */ 2054 xgbe_phy_pll_ctrl(pdata, false); 2055 2056 /* Log if a previous command did not complete */ 2057 if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) { 2058 netif_dbg(pdata, link, pdata->netdev, 2059 "firmware mailbox not ready for command\n"); 2060 xgbe_phy_rx_reset(pdata); 2061 } 2062 2063 /* Construct the command */ 2064 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, cmd); 2065 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, sub_cmd); 2066 2067 /* Issue the command */ 2068 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0); 2069 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0); 2070 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1); 2071 2072 /* Wait for command to complete */ 2073 wait = XGBE_RATECHANGE_COUNT; 2074 while (wait--) { 2075 if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) 2076 goto do_rx_adaptation; 2077 2078 usleep_range(1000, 2000); 2079 } 2080 2081 netif_dbg(pdata, link, pdata->netdev, 2082 "firmware mailbox command did not complete\n"); 2083 2084 /* Reset on error */ 2085 xgbe_phy_rx_reset(pdata); 2086 goto reenable_pll; 2087 2088 do_rx_adaptation: 2089 if (pdata->en_rx_adap && sub_cmd == XGBE_MB_SUBCMD_RX_ADAP && 2090 (cmd == XGBE_MB_CMD_SET_10G_KR || cmd == XGBE_MB_CMD_SET_10G_SFI)) { 2091 netif_dbg(pdata, link, pdata->netdev, 2092 "Enabling RX adaptation\n"); 2093 pdata->mode_set = true; 2094 xgbe_phy_rx_adaptation(pdata); 2095 /* return from here to avoid enabling PLL ctrl 2096 * during adaptation phase 2097 */ 2098 return; 2099 } 2100 2101 reenable_pll: 2102 /* Enable PLL re-initialization, not needed for PHY Power Off and RRC cmds */ 2103 if (cmd != XGBE_MB_CMD_POWER_OFF && 2104 cmd != XGBE_MB_CMD_RRC) 2105 xgbe_phy_pll_ctrl(pdata, true); 2106 } 2107 2108 static void xgbe_phy_rrc(struct xgbe_prv_data *pdata) 2109 { 2110 /* Receiver Reset Cycle */ 2111 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_RRC, XGBE_MB_SUBCMD_NONE); 2112 2113 netif_dbg(pdata, link, pdata->netdev, "receiver reset complete\n"); 2114 } 2115 2116 static void xgbe_phy_power_off(struct xgbe_prv_data *pdata) 2117 { 2118 struct xgbe_phy_data *phy_data = pdata->phy_data; 2119 2120 /* Power off */ 2121 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_POWER_OFF, XGBE_MB_SUBCMD_NONE); 2122 2123 phy_data->cur_mode = XGBE_MODE_UNKNOWN; 2124 2125 netif_dbg(pdata, link, pdata->netdev, "phy powered off\n"); 2126 } 2127 2128 static bool enable_rx_adap(struct xgbe_prv_data *pdata, enum xgbe_mode mode) 2129 { 2130 struct xgbe_phy_data *phy_data = pdata->phy_data; 2131 unsigned int ver; 2132 2133 /* Rx-Adaptation is not supported on older platforms(< 0x30H) */ 2134 ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER); 2135 if (ver < 0x30) 2136 return false; 2137 2138 /* Re-driver models 4223 && 4227 do not support Rx-Adaptation */ 2139 if (phy_data->redrv && 2140 (phy_data->redrv_model == XGBE_PHY_REDRV_MODEL_4223 || 2141 phy_data->redrv_model == XGBE_PHY_REDRV_MODEL_4227)) 2142 return false; 2143 2144 /* 10G KR mode with AN does not support Rx-Adaptation */ 2145 if (mode == XGBE_MODE_KR && 2146 phy_data->port_mode != XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG) 2147 return false; 2148 2149 pdata->en_rx_adap = 1; 2150 return true; 2151 } 2152 2153 static void xgbe_phy_sfi_mode(struct xgbe_prv_data *pdata) 2154 { 2155 struct xgbe_phy_data *phy_data = pdata->phy_data; 2156 2157 xgbe_phy_set_redrv_mode(pdata); 2158 2159 /* 10G/SFI */ 2160 if (phy_data->sfp_cable != XGBE_SFP_CABLE_PASSIVE) { 2161 pdata->en_rx_adap = 0; 2162 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_10G_SFI, XGBE_MB_SUBCMD_ACTIVE); 2163 } else if ((phy_data->sfp_cable == XGBE_SFP_CABLE_PASSIVE) && 2164 (enable_rx_adap(pdata, XGBE_MODE_SFI))) { 2165 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_10G_SFI, 2166 XGBE_MB_SUBCMD_RX_ADAP); 2167 } else { 2168 if (phy_data->sfp_cable_len <= 1) 2169 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_10G_SFI, 2170 XGBE_MB_SUBCMD_PASSIVE_1M); 2171 else if (phy_data->sfp_cable_len <= 3) 2172 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_10G_SFI, 2173 XGBE_MB_SUBCMD_PASSIVE_3M); 2174 else 2175 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_10G_SFI, 2176 XGBE_MB_SUBCMD_PASSIVE_OTHER); 2177 } 2178 2179 phy_data->cur_mode = XGBE_MODE_SFI; 2180 2181 netif_dbg(pdata, link, pdata->netdev, "10GbE SFI mode set\n"); 2182 } 2183 2184 static void xgbe_phy_x_mode(struct xgbe_prv_data *pdata) 2185 { 2186 struct xgbe_phy_data *phy_data = pdata->phy_data; 2187 2188 xgbe_phy_set_redrv_mode(pdata); 2189 2190 /* 1G/X */ 2191 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_1G, XGBE_MB_SUBCMD_1G_KX); 2192 2193 phy_data->cur_mode = XGBE_MODE_X; 2194 2195 netif_dbg(pdata, link, pdata->netdev, "1GbE X mode set\n"); 2196 } 2197 2198 static void xgbe_phy_sgmii_1000_mode(struct xgbe_prv_data *pdata) 2199 { 2200 struct xgbe_phy_data *phy_data = pdata->phy_data; 2201 2202 xgbe_phy_set_redrv_mode(pdata); 2203 2204 /* 1G/SGMII */ 2205 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_1G, XGBE_MB_SUBCMD_1G_SGMII); 2206 2207 phy_data->cur_mode = XGBE_MODE_SGMII_1000; 2208 2209 netif_dbg(pdata, link, pdata->netdev, "1GbE SGMII mode set\n"); 2210 } 2211 2212 static void xgbe_phy_sgmii_100_mode(struct xgbe_prv_data *pdata) 2213 { 2214 struct xgbe_phy_data *phy_data = pdata->phy_data; 2215 2216 xgbe_phy_set_redrv_mode(pdata); 2217 2218 /* 100M/SGMII */ 2219 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_1G, XGBE_MB_SUBCMD_100MBITS); 2220 2221 phy_data->cur_mode = XGBE_MODE_SGMII_100; 2222 2223 netif_dbg(pdata, link, pdata->netdev, "100MbE SGMII mode set\n"); 2224 } 2225 2226 static void xgbe_phy_sgmii_10_mode(struct xgbe_prv_data *pdata) 2227 { 2228 struct xgbe_phy_data *phy_data = pdata->phy_data; 2229 2230 xgbe_phy_set_redrv_mode(pdata); 2231 2232 /* 10M/SGMII */ 2233 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_1G, XGBE_MB_SUBCMD_10MBITS); 2234 2235 phy_data->cur_mode = XGBE_MODE_SGMII_10; 2236 2237 netif_dbg(pdata, link, pdata->netdev, "10MbE SGMII mode set\n"); 2238 } 2239 2240 static void xgbe_phy_kr_mode(struct xgbe_prv_data *pdata) 2241 { 2242 struct xgbe_phy_data *phy_data = pdata->phy_data; 2243 2244 xgbe_phy_set_redrv_mode(pdata); 2245 2246 /* 10G/KR */ 2247 if (enable_rx_adap(pdata, XGBE_MODE_KR)) 2248 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_10G_KR, 2249 XGBE_MB_SUBCMD_RX_ADAP); 2250 else 2251 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_10G_KR, 2252 XGBE_MB_SUBCMD_NONE); 2253 2254 phy_data->cur_mode = XGBE_MODE_KR; 2255 2256 netif_dbg(pdata, link, pdata->netdev, "10GbE KR mode set\n"); 2257 } 2258 2259 static void xgbe_phy_kx_2500_mode(struct xgbe_prv_data *pdata) 2260 { 2261 struct xgbe_phy_data *phy_data = pdata->phy_data; 2262 2263 xgbe_phy_set_redrv_mode(pdata); 2264 2265 /* 2.5G/KX */ 2266 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_2_5G, XGBE_MB_SUBCMD_NONE); 2267 2268 phy_data->cur_mode = XGBE_MODE_KX_2500; 2269 2270 netif_dbg(pdata, link, pdata->netdev, "2.5GbE KX mode set\n"); 2271 } 2272 2273 static void xgbe_phy_kx_1000_mode(struct xgbe_prv_data *pdata) 2274 { 2275 struct xgbe_phy_data *phy_data = pdata->phy_data; 2276 2277 xgbe_phy_set_redrv_mode(pdata); 2278 2279 /* 1G/KX */ 2280 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_1G, XGBE_MB_SUBCMD_1G_KX); 2281 2282 phy_data->cur_mode = XGBE_MODE_KX_1000; 2283 2284 netif_dbg(pdata, link, pdata->netdev, "1GbE KX mode set\n"); 2285 } 2286 2287 static enum xgbe_mode xgbe_phy_cur_mode(struct xgbe_prv_data *pdata) 2288 { 2289 struct xgbe_phy_data *phy_data = pdata->phy_data; 2290 2291 return phy_data->cur_mode; 2292 } 2293 2294 static enum xgbe_mode xgbe_phy_switch_baset_mode(struct xgbe_prv_data *pdata) 2295 { 2296 struct xgbe_phy_data *phy_data = pdata->phy_data; 2297 2298 /* No switching if not 10GBase-T */ 2299 if (phy_data->port_mode != XGBE_PORT_MODE_10GBASE_T) 2300 return xgbe_phy_cur_mode(pdata); 2301 2302 switch (xgbe_phy_cur_mode(pdata)) { 2303 case XGBE_MODE_SGMII_10: 2304 case XGBE_MODE_SGMII_100: 2305 case XGBE_MODE_SGMII_1000: 2306 return XGBE_MODE_KR; 2307 case XGBE_MODE_KX_2500: 2308 return XGBE_MODE_SGMII_1000; 2309 case XGBE_MODE_KR: 2310 default: 2311 return XGBE_MODE_KX_2500; 2312 } 2313 } 2314 2315 static enum xgbe_mode xgbe_phy_switch_bp_2500_mode(struct xgbe_prv_data *pdata) 2316 { 2317 return XGBE_MODE_KX_2500; 2318 } 2319 2320 static enum xgbe_mode xgbe_phy_switch_bp_mode(struct xgbe_prv_data *pdata) 2321 { 2322 /* If we are in KR switch to KX, and vice-versa */ 2323 switch (xgbe_phy_cur_mode(pdata)) { 2324 case XGBE_MODE_KX_1000: 2325 return XGBE_MODE_KR; 2326 case XGBE_MODE_KR: 2327 default: 2328 return XGBE_MODE_KX_1000; 2329 } 2330 } 2331 2332 static enum xgbe_mode xgbe_phy_switch_mode(struct xgbe_prv_data *pdata) 2333 { 2334 struct xgbe_phy_data *phy_data = pdata->phy_data; 2335 2336 switch (phy_data->port_mode) { 2337 case XGBE_PORT_MODE_BACKPLANE: 2338 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 2339 return xgbe_phy_switch_bp_mode(pdata); 2340 case XGBE_PORT_MODE_BACKPLANE_2500: 2341 return xgbe_phy_switch_bp_2500_mode(pdata); 2342 case XGBE_PORT_MODE_1000BASE_T: 2343 case XGBE_PORT_MODE_NBASE_T: 2344 case XGBE_PORT_MODE_10GBASE_T: 2345 return xgbe_phy_switch_baset_mode(pdata); 2346 case XGBE_PORT_MODE_1000BASE_X: 2347 case XGBE_PORT_MODE_10GBASE_R: 2348 case XGBE_PORT_MODE_SFP: 2349 /* No switching, so just return current mode */ 2350 return xgbe_phy_cur_mode(pdata); 2351 default: 2352 return XGBE_MODE_UNKNOWN; 2353 } 2354 } 2355 2356 static enum xgbe_mode xgbe_phy_get_basex_mode(struct xgbe_phy_data *phy_data, 2357 int speed) 2358 { 2359 switch (speed) { 2360 case SPEED_1000: 2361 return XGBE_MODE_X; 2362 case SPEED_10000: 2363 return XGBE_MODE_KR; 2364 default: 2365 return XGBE_MODE_UNKNOWN; 2366 } 2367 } 2368 2369 static enum xgbe_mode xgbe_phy_get_baset_mode(struct xgbe_phy_data *phy_data, 2370 int speed) 2371 { 2372 switch (speed) { 2373 case SPEED_10: 2374 return XGBE_MODE_SGMII_10; 2375 case SPEED_100: 2376 return XGBE_MODE_SGMII_100; 2377 case SPEED_1000: 2378 return XGBE_MODE_SGMII_1000; 2379 case SPEED_2500: 2380 return XGBE_MODE_KX_2500; 2381 case SPEED_10000: 2382 return XGBE_MODE_KR; 2383 default: 2384 return XGBE_MODE_UNKNOWN; 2385 } 2386 } 2387 2388 static enum xgbe_mode xgbe_phy_get_sfp_mode(struct xgbe_phy_data *phy_data, 2389 int speed) 2390 { 2391 switch (speed) { 2392 case SPEED_10: 2393 return XGBE_MODE_SGMII_10; 2394 case SPEED_100: 2395 return XGBE_MODE_SGMII_100; 2396 case SPEED_1000: 2397 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T) 2398 return XGBE_MODE_SGMII_1000; 2399 else 2400 return XGBE_MODE_X; 2401 case SPEED_10000: 2402 case SPEED_UNKNOWN: 2403 return XGBE_MODE_SFI; 2404 default: 2405 return XGBE_MODE_UNKNOWN; 2406 } 2407 } 2408 2409 static enum xgbe_mode xgbe_phy_get_bp_2500_mode(int speed) 2410 { 2411 switch (speed) { 2412 case SPEED_2500: 2413 return XGBE_MODE_KX_2500; 2414 default: 2415 return XGBE_MODE_UNKNOWN; 2416 } 2417 } 2418 2419 static enum xgbe_mode xgbe_phy_get_bp_mode(int speed) 2420 { 2421 switch (speed) { 2422 case SPEED_1000: 2423 return XGBE_MODE_KX_1000; 2424 case SPEED_10000: 2425 return XGBE_MODE_KR; 2426 default: 2427 return XGBE_MODE_UNKNOWN; 2428 } 2429 } 2430 2431 static enum xgbe_mode xgbe_phy_get_mode(struct xgbe_prv_data *pdata, 2432 int speed) 2433 { 2434 struct xgbe_phy_data *phy_data = pdata->phy_data; 2435 2436 switch (phy_data->port_mode) { 2437 case XGBE_PORT_MODE_BACKPLANE: 2438 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 2439 return xgbe_phy_get_bp_mode(speed); 2440 case XGBE_PORT_MODE_BACKPLANE_2500: 2441 return xgbe_phy_get_bp_2500_mode(speed); 2442 case XGBE_PORT_MODE_1000BASE_T: 2443 case XGBE_PORT_MODE_NBASE_T: 2444 case XGBE_PORT_MODE_10GBASE_T: 2445 return xgbe_phy_get_baset_mode(phy_data, speed); 2446 case XGBE_PORT_MODE_1000BASE_X: 2447 case XGBE_PORT_MODE_10GBASE_R: 2448 return xgbe_phy_get_basex_mode(phy_data, speed); 2449 case XGBE_PORT_MODE_SFP: 2450 return xgbe_phy_get_sfp_mode(phy_data, speed); 2451 default: 2452 return XGBE_MODE_UNKNOWN; 2453 } 2454 } 2455 2456 static void xgbe_phy_set_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode) 2457 { 2458 switch (mode) { 2459 case XGBE_MODE_KX_1000: 2460 xgbe_phy_kx_1000_mode(pdata); 2461 break; 2462 case XGBE_MODE_KX_2500: 2463 xgbe_phy_kx_2500_mode(pdata); 2464 break; 2465 case XGBE_MODE_KR: 2466 xgbe_phy_kr_mode(pdata); 2467 break; 2468 case XGBE_MODE_SGMII_10: 2469 xgbe_phy_sgmii_10_mode(pdata); 2470 break; 2471 case XGBE_MODE_SGMII_100: 2472 xgbe_phy_sgmii_100_mode(pdata); 2473 break; 2474 case XGBE_MODE_SGMII_1000: 2475 xgbe_phy_sgmii_1000_mode(pdata); 2476 break; 2477 case XGBE_MODE_X: 2478 xgbe_phy_x_mode(pdata); 2479 break; 2480 case XGBE_MODE_SFI: 2481 xgbe_phy_sfi_mode(pdata); 2482 break; 2483 default: 2484 break; 2485 } 2486 } 2487 2488 static bool xgbe_phy_check_mode(struct xgbe_prv_data *pdata, 2489 enum xgbe_mode mode, bool advert) 2490 { 2491 if (pdata->phy.autoneg == AUTONEG_ENABLE) { 2492 return advert; 2493 } else { 2494 enum xgbe_mode cur_mode; 2495 2496 cur_mode = xgbe_phy_get_mode(pdata, pdata->phy.speed); 2497 if (cur_mode == mode) 2498 return true; 2499 } 2500 2501 return false; 2502 } 2503 2504 static bool xgbe_phy_use_basex_mode(struct xgbe_prv_data *pdata, 2505 enum xgbe_mode mode) 2506 { 2507 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 2508 2509 switch (mode) { 2510 case XGBE_MODE_X: 2511 return xgbe_phy_check_mode(pdata, mode, 2512 XGBE_ADV(lks, 1000baseX_Full)); 2513 case XGBE_MODE_KR: 2514 return xgbe_phy_check_mode(pdata, mode, 2515 XGBE_ADV(lks, 10000baseKR_Full)); 2516 default: 2517 return false; 2518 } 2519 } 2520 2521 static bool xgbe_phy_use_baset_mode(struct xgbe_prv_data *pdata, 2522 enum xgbe_mode mode) 2523 { 2524 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 2525 2526 switch (mode) { 2527 case XGBE_MODE_SGMII_10: 2528 return xgbe_phy_check_mode(pdata, mode, 2529 XGBE_ADV(lks, 10baseT_Full)); 2530 case XGBE_MODE_SGMII_100: 2531 return xgbe_phy_check_mode(pdata, mode, 2532 XGBE_ADV(lks, 100baseT_Full)); 2533 case XGBE_MODE_SGMII_1000: 2534 return xgbe_phy_check_mode(pdata, mode, 2535 XGBE_ADV(lks, 1000baseT_Full)); 2536 case XGBE_MODE_KX_2500: 2537 return xgbe_phy_check_mode(pdata, mode, 2538 XGBE_ADV(lks, 2500baseT_Full)); 2539 case XGBE_MODE_KR: 2540 return xgbe_phy_check_mode(pdata, mode, 2541 XGBE_ADV(lks, 10000baseT_Full)); 2542 default: 2543 return false; 2544 } 2545 } 2546 2547 static bool xgbe_phy_use_sfp_mode(struct xgbe_prv_data *pdata, 2548 enum xgbe_mode mode) 2549 { 2550 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 2551 struct xgbe_phy_data *phy_data = pdata->phy_data; 2552 2553 switch (mode) { 2554 case XGBE_MODE_X: 2555 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T) 2556 return false; 2557 return xgbe_phy_check_mode(pdata, mode, 2558 XGBE_ADV(lks, 1000baseX_Full)); 2559 case XGBE_MODE_SGMII_10: 2560 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T) 2561 return false; 2562 return xgbe_phy_check_mode(pdata, mode, 2563 XGBE_ADV(lks, 10baseT_Full)); 2564 case XGBE_MODE_SGMII_100: 2565 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T) 2566 return false; 2567 return xgbe_phy_check_mode(pdata, mode, 2568 XGBE_ADV(lks, 100baseT_Full)); 2569 case XGBE_MODE_SGMII_1000: 2570 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T) 2571 return false; 2572 return xgbe_phy_check_mode(pdata, mode, 2573 XGBE_ADV(lks, 1000baseT_Full)); 2574 case XGBE_MODE_SFI: 2575 if (phy_data->sfp_mod_absent) 2576 return true; 2577 return xgbe_phy_check_mode(pdata, mode, 2578 XGBE_ADV(lks, 10000baseSR_Full) || 2579 XGBE_ADV(lks, 10000baseLR_Full) || 2580 XGBE_ADV(lks, 10000baseLRM_Full) || 2581 XGBE_ADV(lks, 10000baseER_Full) || 2582 XGBE_ADV(lks, 10000baseCR_Full)); 2583 default: 2584 return false; 2585 } 2586 } 2587 2588 static bool xgbe_phy_use_bp_2500_mode(struct xgbe_prv_data *pdata, 2589 enum xgbe_mode mode) 2590 { 2591 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 2592 2593 switch (mode) { 2594 case XGBE_MODE_KX_2500: 2595 return xgbe_phy_check_mode(pdata, mode, 2596 XGBE_ADV(lks, 2500baseX_Full)); 2597 default: 2598 return false; 2599 } 2600 } 2601 2602 static bool xgbe_phy_use_bp_mode(struct xgbe_prv_data *pdata, 2603 enum xgbe_mode mode) 2604 { 2605 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 2606 2607 switch (mode) { 2608 case XGBE_MODE_KX_1000: 2609 return xgbe_phy_check_mode(pdata, mode, 2610 XGBE_ADV(lks, 1000baseKX_Full)); 2611 case XGBE_MODE_KR: 2612 return xgbe_phy_check_mode(pdata, mode, 2613 XGBE_ADV(lks, 10000baseKR_Full)); 2614 default: 2615 return false; 2616 } 2617 } 2618 2619 static bool xgbe_phy_use_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode) 2620 { 2621 struct xgbe_phy_data *phy_data = pdata->phy_data; 2622 2623 switch (phy_data->port_mode) { 2624 case XGBE_PORT_MODE_BACKPLANE: 2625 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 2626 return xgbe_phy_use_bp_mode(pdata, mode); 2627 case XGBE_PORT_MODE_BACKPLANE_2500: 2628 return xgbe_phy_use_bp_2500_mode(pdata, mode); 2629 case XGBE_PORT_MODE_1000BASE_T: 2630 case XGBE_PORT_MODE_NBASE_T: 2631 case XGBE_PORT_MODE_10GBASE_T: 2632 return xgbe_phy_use_baset_mode(pdata, mode); 2633 case XGBE_PORT_MODE_1000BASE_X: 2634 case XGBE_PORT_MODE_10GBASE_R: 2635 return xgbe_phy_use_basex_mode(pdata, mode); 2636 case XGBE_PORT_MODE_SFP: 2637 return xgbe_phy_use_sfp_mode(pdata, mode); 2638 default: 2639 return false; 2640 } 2641 } 2642 2643 static bool xgbe_phy_valid_speed_basex_mode(struct xgbe_phy_data *phy_data, 2644 int speed) 2645 { 2646 switch (speed) { 2647 case SPEED_1000: 2648 return (phy_data->port_mode == XGBE_PORT_MODE_1000BASE_X); 2649 case SPEED_10000: 2650 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_R); 2651 default: 2652 return false; 2653 } 2654 } 2655 2656 static bool xgbe_phy_valid_speed_baset_mode(struct xgbe_prv_data *pdata, 2657 int speed) 2658 { 2659 struct xgbe_phy_data *phy_data = pdata->phy_data; 2660 unsigned int ver; 2661 2662 switch (speed) { 2663 case SPEED_10: 2664 /* Supported in ver 21H and ver >= 30H */ 2665 ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER); 2666 return (ver == 0x21 || ver >= 0x30); 2667 case SPEED_100: 2668 case SPEED_1000: 2669 return true; 2670 case SPEED_2500: 2671 return ((phy_data->port_mode == XGBE_PORT_MODE_10GBASE_T) || 2672 (phy_data->port_mode == XGBE_PORT_MODE_NBASE_T)); 2673 case SPEED_10000: 2674 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_T); 2675 default: 2676 return false; 2677 } 2678 } 2679 2680 static bool xgbe_phy_valid_speed_sfp_mode(struct xgbe_prv_data *pdata, 2681 int speed) 2682 { 2683 struct xgbe_phy_data *phy_data = pdata->phy_data; 2684 unsigned int ver; 2685 2686 switch (speed) { 2687 case SPEED_10: 2688 /* Supported in ver 21H and ver >= 30H */ 2689 ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER); 2690 return ((ver == 0x21 || ver >= 0x30) && 2691 (phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000)); 2692 case SPEED_100: 2693 return (phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000); 2694 case SPEED_1000: 2695 return ((phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000) || 2696 (phy_data->sfp_speed == XGBE_SFP_SPEED_1000)); 2697 case SPEED_10000: 2698 return (phy_data->sfp_speed == XGBE_SFP_SPEED_10000); 2699 default: 2700 return false; 2701 } 2702 } 2703 2704 static bool xgbe_phy_valid_speed_bp_2500_mode(int speed) 2705 { 2706 switch (speed) { 2707 case SPEED_2500: 2708 return true; 2709 default: 2710 return false; 2711 } 2712 } 2713 2714 static bool xgbe_phy_valid_speed_bp_mode(int speed) 2715 { 2716 switch (speed) { 2717 case SPEED_1000: 2718 case SPEED_10000: 2719 return true; 2720 default: 2721 return false; 2722 } 2723 } 2724 2725 static bool xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed) 2726 { 2727 struct xgbe_phy_data *phy_data = pdata->phy_data; 2728 2729 switch (phy_data->port_mode) { 2730 case XGBE_PORT_MODE_BACKPLANE: 2731 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 2732 return xgbe_phy_valid_speed_bp_mode(speed); 2733 case XGBE_PORT_MODE_BACKPLANE_2500: 2734 return xgbe_phy_valid_speed_bp_2500_mode(speed); 2735 case XGBE_PORT_MODE_1000BASE_T: 2736 case XGBE_PORT_MODE_NBASE_T: 2737 case XGBE_PORT_MODE_10GBASE_T: 2738 return xgbe_phy_valid_speed_baset_mode(pdata, speed); 2739 case XGBE_PORT_MODE_1000BASE_X: 2740 case XGBE_PORT_MODE_10GBASE_R: 2741 return xgbe_phy_valid_speed_basex_mode(phy_data, speed); 2742 case XGBE_PORT_MODE_SFP: 2743 return xgbe_phy_valid_speed_sfp_mode(pdata, speed); 2744 default: 2745 return false; 2746 } 2747 } 2748 2749 static int xgbe_phy_link_status(struct xgbe_prv_data *pdata, int *an_restart) 2750 { 2751 struct xgbe_phy_data *phy_data = pdata->phy_data; 2752 int reg, ret; 2753 2754 *an_restart = 0; 2755 2756 if (phy_data->port_mode == XGBE_PORT_MODE_SFP) { 2757 /* Check SFP signals */ 2758 xgbe_phy_sfp_detect(pdata); 2759 2760 if (phy_data->sfp_changed) { 2761 *an_restart = 1; 2762 return 0; 2763 } 2764 2765 if (phy_data->sfp_mod_absent || phy_data->sfp_rx_los) { 2766 if (pdata->en_rx_adap) 2767 pdata->rx_adapt_done = false; 2768 return 0; 2769 } 2770 } 2771 2772 if (phy_data->phydev) { 2773 /* Check external PHY */ 2774 ret = phy_read_status(phy_data->phydev); 2775 if (ret < 0) 2776 return 0; 2777 2778 if ((pdata->phy.autoneg == AUTONEG_ENABLE) && 2779 !phy_aneg_done(phy_data->phydev)) 2780 return 0; 2781 2782 if (!phy_data->phydev->link) 2783 return 0; 2784 } 2785 2786 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); 2787 if (reg < 0) 2788 return reg; 2789 2790 /* Link status is latched low so that momentary link drops 2791 * can be detected. If link was already down read again 2792 * to get the latest state. 2793 */ 2794 2795 if (!pdata->phy.link && !(reg & MDIO_STAT1_LSTATUS)) { 2796 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); 2797 if (reg < 0) 2798 return reg; 2799 } 2800 2801 if (pdata->en_rx_adap) { 2802 /* if the link is available and adaptation is done, 2803 * declare link up 2804 */ 2805 if ((reg & MDIO_STAT1_LSTATUS) && pdata->rx_adapt_done) 2806 return 1; 2807 /* If either link is not available or adaptation is not done, 2808 * retrigger the adaptation logic. (if the mode is not set, 2809 * then issue mailbox command first) 2810 */ 2811 if (pdata->mode_set) { 2812 xgbe_phy_rx_adaptation(pdata); 2813 } else { 2814 pdata->rx_adapt_done = false; 2815 xgbe_phy_set_mode(pdata, phy_data->cur_mode); 2816 } 2817 2818 if (pdata->rx_adapt_done) 2819 return 1; 2820 } else if (reg & MDIO_STAT1_LSTATUS) 2821 return 1; 2822 2823 if (pdata->phy.autoneg == AUTONEG_ENABLE && 2824 phy_data->port_mode == XGBE_PORT_MODE_BACKPLANE) { 2825 if (!test_bit(XGBE_LINK_INIT, &pdata->dev_state)) { 2826 netif_carrier_off(pdata->netdev); 2827 *an_restart = 1; 2828 } 2829 } 2830 2831 /* No link, attempt a receiver reset cycle */ 2832 if (pdata->vdata->enable_rrc && phy_data->rrc_count++ > XGBE_RRC_FREQUENCY) { 2833 phy_data->rrc_count = 0; 2834 xgbe_phy_rrc(pdata); 2835 } 2836 2837 return 0; 2838 } 2839 2840 static void xgbe_phy_sfp_gpio_setup(struct xgbe_prv_data *pdata) 2841 { 2842 struct xgbe_phy_data *phy_data = pdata->phy_data; 2843 2844 phy_data->sfp_gpio_address = XGBE_GPIO_ADDRESS_PCA9555 + 2845 XP_GET_BITS(pdata->pp3, XP_PROP_3, 2846 GPIO_ADDR); 2847 2848 phy_data->sfp_gpio_mask = XP_GET_BITS(pdata->pp3, XP_PROP_3, 2849 GPIO_MASK); 2850 2851 phy_data->sfp_gpio_rx_los = XP_GET_BITS(pdata->pp3, XP_PROP_3, 2852 GPIO_RX_LOS); 2853 phy_data->sfp_gpio_tx_fault = XP_GET_BITS(pdata->pp3, XP_PROP_3, 2854 GPIO_TX_FAULT); 2855 phy_data->sfp_gpio_mod_absent = XP_GET_BITS(pdata->pp3, XP_PROP_3, 2856 GPIO_MOD_ABS); 2857 phy_data->sfp_gpio_rate_select = XP_GET_BITS(pdata->pp3, XP_PROP_3, 2858 GPIO_RATE_SELECT); 2859 2860 if (netif_msg_probe(pdata)) { 2861 dev_dbg(pdata->dev, "SFP: gpio_address=%#x\n", 2862 phy_data->sfp_gpio_address); 2863 dev_dbg(pdata->dev, "SFP: gpio_mask=%#x\n", 2864 phy_data->sfp_gpio_mask); 2865 dev_dbg(pdata->dev, "SFP: gpio_rx_los=%u\n", 2866 phy_data->sfp_gpio_rx_los); 2867 dev_dbg(pdata->dev, "SFP: gpio_tx_fault=%u\n", 2868 phy_data->sfp_gpio_tx_fault); 2869 dev_dbg(pdata->dev, "SFP: gpio_mod_absent=%u\n", 2870 phy_data->sfp_gpio_mod_absent); 2871 dev_dbg(pdata->dev, "SFP: gpio_rate_select=%u\n", 2872 phy_data->sfp_gpio_rate_select); 2873 } 2874 } 2875 2876 static void xgbe_phy_sfp_comm_setup(struct xgbe_prv_data *pdata) 2877 { 2878 struct xgbe_phy_data *phy_data = pdata->phy_data; 2879 unsigned int mux_addr_hi, mux_addr_lo; 2880 2881 mux_addr_hi = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_HI); 2882 mux_addr_lo = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_LO); 2883 if (mux_addr_lo == XGBE_SFP_DIRECT) 2884 return; 2885 2886 phy_data->sfp_comm = XGBE_SFP_COMM_PCA9545; 2887 phy_data->sfp_mux_address = (mux_addr_hi << 2) + mux_addr_lo; 2888 phy_data->sfp_mux_channel = XP_GET_BITS(pdata->pp4, XP_PROP_4, 2889 MUX_CHAN); 2890 2891 if (netif_msg_probe(pdata)) { 2892 dev_dbg(pdata->dev, "SFP: mux_address=%#x\n", 2893 phy_data->sfp_mux_address); 2894 dev_dbg(pdata->dev, "SFP: mux_channel=%u\n", 2895 phy_data->sfp_mux_channel); 2896 } 2897 } 2898 2899 static void xgbe_phy_sfp_setup(struct xgbe_prv_data *pdata) 2900 { 2901 xgbe_phy_sfp_comm_setup(pdata); 2902 xgbe_phy_sfp_gpio_setup(pdata); 2903 } 2904 2905 static int xgbe_phy_int_mdio_reset(struct xgbe_prv_data *pdata) 2906 { 2907 struct xgbe_phy_data *phy_data = pdata->phy_data; 2908 int ret; 2909 2910 ret = pdata->hw_if.set_gpio(pdata, phy_data->mdio_reset_gpio); 2911 if (ret) 2912 return ret; 2913 2914 ret = pdata->hw_if.clr_gpio(pdata, phy_data->mdio_reset_gpio); 2915 2916 return ret; 2917 } 2918 2919 static int xgbe_phy_i2c_mdio_reset(struct xgbe_prv_data *pdata) 2920 { 2921 struct xgbe_phy_data *phy_data = pdata->phy_data; 2922 u8 gpio_reg, gpio_ports[2], gpio_data[3]; 2923 int ret; 2924 2925 /* Read the output port registers */ 2926 gpio_reg = 2; 2927 ret = xgbe_phy_i2c_read(pdata, phy_data->mdio_reset_addr, 2928 &gpio_reg, sizeof(gpio_reg), 2929 gpio_ports, sizeof(gpio_ports)); 2930 if (ret) 2931 return ret; 2932 2933 /* Prepare to write the GPIO data */ 2934 gpio_data[0] = 2; 2935 gpio_data[1] = gpio_ports[0]; 2936 gpio_data[2] = gpio_ports[1]; 2937 2938 /* Set the GPIO pin */ 2939 if (phy_data->mdio_reset_gpio < 8) 2940 gpio_data[1] |= (1 << (phy_data->mdio_reset_gpio % 8)); 2941 else 2942 gpio_data[2] |= (1 << (phy_data->mdio_reset_gpio % 8)); 2943 2944 /* Write the output port registers */ 2945 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr, 2946 gpio_data, sizeof(gpio_data)); 2947 if (ret) 2948 return ret; 2949 2950 /* Clear the GPIO pin */ 2951 if (phy_data->mdio_reset_gpio < 8) 2952 gpio_data[1] &= ~(1 << (phy_data->mdio_reset_gpio % 8)); 2953 else 2954 gpio_data[2] &= ~(1 << (phy_data->mdio_reset_gpio % 8)); 2955 2956 /* Write the output port registers */ 2957 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr, 2958 gpio_data, sizeof(gpio_data)); 2959 2960 return ret; 2961 } 2962 2963 static int xgbe_phy_mdio_reset(struct xgbe_prv_data *pdata) 2964 { 2965 struct xgbe_phy_data *phy_data = pdata->phy_data; 2966 int ret; 2967 2968 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO) 2969 return 0; 2970 2971 ret = xgbe_phy_get_comm_ownership(pdata); 2972 if (ret) 2973 return ret; 2974 2975 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO) 2976 ret = xgbe_phy_i2c_mdio_reset(pdata); 2977 else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO) 2978 ret = xgbe_phy_int_mdio_reset(pdata); 2979 2980 xgbe_phy_put_comm_ownership(pdata); 2981 2982 return ret; 2983 } 2984 2985 static bool xgbe_phy_redrv_error(struct xgbe_phy_data *phy_data) 2986 { 2987 if (!phy_data->redrv) 2988 return false; 2989 2990 if (phy_data->redrv_if >= XGBE_PHY_REDRV_IF_MAX) 2991 return true; 2992 2993 switch (phy_data->redrv_model) { 2994 case XGBE_PHY_REDRV_MODEL_4223: 2995 if (phy_data->redrv_lane > 3) 2996 return true; 2997 break; 2998 case XGBE_PHY_REDRV_MODEL_4227: 2999 if (phy_data->redrv_lane > 1) 3000 return true; 3001 break; 3002 default: 3003 return true; 3004 } 3005 3006 return false; 3007 } 3008 3009 static int xgbe_phy_mdio_reset_setup(struct xgbe_prv_data *pdata) 3010 { 3011 struct xgbe_phy_data *phy_data = pdata->phy_data; 3012 3013 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO) 3014 return 0; 3015 3016 phy_data->mdio_reset = XP_GET_BITS(pdata->pp3, XP_PROP_3, MDIO_RESET); 3017 switch (phy_data->mdio_reset) { 3018 case XGBE_MDIO_RESET_NONE: 3019 case XGBE_MDIO_RESET_I2C_GPIO: 3020 case XGBE_MDIO_RESET_INT_GPIO: 3021 break; 3022 default: 3023 dev_err(pdata->dev, "unsupported MDIO reset (%#x)\n", 3024 phy_data->mdio_reset); 3025 return -EINVAL; 3026 } 3027 3028 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO) { 3029 phy_data->mdio_reset_addr = XGBE_GPIO_ADDRESS_PCA9555 + 3030 XP_GET_BITS(pdata->pp3, XP_PROP_3, 3031 MDIO_RESET_I2C_ADDR); 3032 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3, 3033 MDIO_RESET_I2C_GPIO); 3034 } else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO) { 3035 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3, 3036 MDIO_RESET_INT_GPIO); 3037 } 3038 3039 return 0; 3040 } 3041 3042 static bool xgbe_phy_port_mode_mismatch(struct xgbe_prv_data *pdata) 3043 { 3044 struct xgbe_phy_data *phy_data = pdata->phy_data; 3045 unsigned int ver; 3046 3047 /* 10 Mbps speed is supported in ver 21H and ver >= 30H */ 3048 ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER); 3049 if ((ver < 0x30 && ver != 0x21) && (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10)) 3050 return true; 3051 3052 switch (phy_data->port_mode) { 3053 case XGBE_PORT_MODE_BACKPLANE: 3054 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 3055 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) || 3056 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)) 3057 return false; 3058 break; 3059 case XGBE_PORT_MODE_BACKPLANE_2500: 3060 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) 3061 return false; 3062 break; 3063 case XGBE_PORT_MODE_1000BASE_T: 3064 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10) || 3065 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 3066 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)) 3067 return false; 3068 break; 3069 case XGBE_PORT_MODE_1000BASE_X: 3070 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) 3071 return false; 3072 break; 3073 case XGBE_PORT_MODE_NBASE_T: 3074 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10) || 3075 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 3076 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) || 3077 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500)) 3078 return false; 3079 break; 3080 case XGBE_PORT_MODE_10GBASE_T: 3081 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10) || 3082 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 3083 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) || 3084 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) || 3085 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)) 3086 return false; 3087 break; 3088 case XGBE_PORT_MODE_10GBASE_R: 3089 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) 3090 return false; 3091 break; 3092 case XGBE_PORT_MODE_SFP: 3093 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10) || 3094 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 3095 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) || 3096 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)) 3097 return false; 3098 break; 3099 default: 3100 break; 3101 } 3102 3103 return true; 3104 } 3105 3106 static bool xgbe_phy_conn_type_mismatch(struct xgbe_prv_data *pdata) 3107 { 3108 struct xgbe_phy_data *phy_data = pdata->phy_data; 3109 3110 switch (phy_data->port_mode) { 3111 case XGBE_PORT_MODE_BACKPLANE: 3112 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 3113 case XGBE_PORT_MODE_BACKPLANE_2500: 3114 if (phy_data->conn_type == XGBE_CONN_TYPE_BACKPLANE) 3115 return false; 3116 break; 3117 case XGBE_PORT_MODE_1000BASE_T: 3118 case XGBE_PORT_MODE_1000BASE_X: 3119 case XGBE_PORT_MODE_NBASE_T: 3120 case XGBE_PORT_MODE_10GBASE_T: 3121 case XGBE_PORT_MODE_10GBASE_R: 3122 if (phy_data->conn_type == XGBE_CONN_TYPE_MDIO) 3123 return false; 3124 break; 3125 case XGBE_PORT_MODE_SFP: 3126 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP) 3127 return false; 3128 break; 3129 default: 3130 break; 3131 } 3132 3133 return true; 3134 } 3135 3136 static bool xgbe_phy_port_enabled(struct xgbe_prv_data *pdata) 3137 { 3138 if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS)) 3139 return false; 3140 if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE)) 3141 return false; 3142 3143 return true; 3144 } 3145 3146 static void xgbe_phy_cdr_track(struct xgbe_prv_data *pdata) 3147 { 3148 struct xgbe_phy_data *phy_data = pdata->phy_data; 3149 3150 if (!pdata->debugfs_an_cdr_workaround) 3151 return; 3152 3153 if (!phy_data->phy_cdr_notrack) 3154 return; 3155 3156 usleep_range(phy_data->phy_cdr_delay, 3157 phy_data->phy_cdr_delay + 500); 3158 3159 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL, 3160 XGBE_PMA_CDR_TRACK_EN_MASK, 3161 XGBE_PMA_CDR_TRACK_EN_ON); 3162 3163 phy_data->phy_cdr_notrack = 0; 3164 } 3165 3166 static void xgbe_phy_cdr_notrack(struct xgbe_prv_data *pdata) 3167 { 3168 struct xgbe_phy_data *phy_data = pdata->phy_data; 3169 3170 if (!pdata->debugfs_an_cdr_workaround) 3171 return; 3172 3173 if (phy_data->phy_cdr_notrack) 3174 return; 3175 3176 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL, 3177 XGBE_PMA_CDR_TRACK_EN_MASK, 3178 XGBE_PMA_CDR_TRACK_EN_OFF); 3179 3180 xgbe_phy_rrc(pdata); 3181 3182 phy_data->phy_cdr_notrack = 1; 3183 } 3184 3185 static void xgbe_phy_kr_training_post(struct xgbe_prv_data *pdata) 3186 { 3187 if (!pdata->debugfs_an_cdr_track_early) 3188 xgbe_phy_cdr_track(pdata); 3189 } 3190 3191 static void xgbe_phy_kr_training_pre(struct xgbe_prv_data *pdata) 3192 { 3193 if (pdata->debugfs_an_cdr_track_early) 3194 xgbe_phy_cdr_track(pdata); 3195 } 3196 3197 static void xgbe_phy_an_post(struct xgbe_prv_data *pdata) 3198 { 3199 struct xgbe_phy_data *phy_data = pdata->phy_data; 3200 3201 switch (pdata->an_mode) { 3202 case XGBE_AN_MODE_CL73: 3203 case XGBE_AN_MODE_CL73_REDRV: 3204 if (phy_data->cur_mode != XGBE_MODE_KR) 3205 break; 3206 3207 xgbe_phy_cdr_track(pdata); 3208 3209 switch (pdata->an_result) { 3210 case XGBE_AN_READY: 3211 case XGBE_AN_COMPLETE: 3212 break; 3213 default: 3214 if (phy_data->phy_cdr_delay < XGBE_CDR_DELAY_MAX) 3215 phy_data->phy_cdr_delay += XGBE_CDR_DELAY_INC; 3216 else 3217 phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT; 3218 break; 3219 } 3220 break; 3221 default: 3222 break; 3223 } 3224 } 3225 3226 static void xgbe_phy_an_pre(struct xgbe_prv_data *pdata) 3227 { 3228 struct xgbe_phy_data *phy_data = pdata->phy_data; 3229 3230 switch (pdata->an_mode) { 3231 case XGBE_AN_MODE_CL73: 3232 case XGBE_AN_MODE_CL73_REDRV: 3233 if (phy_data->cur_mode != XGBE_MODE_KR) 3234 break; 3235 3236 xgbe_phy_cdr_notrack(pdata); 3237 break; 3238 default: 3239 break; 3240 } 3241 } 3242 3243 static void xgbe_phy_stop(struct xgbe_prv_data *pdata) 3244 { 3245 struct xgbe_phy_data *phy_data = pdata->phy_data; 3246 3247 /* If we have an external PHY, free it */ 3248 xgbe_phy_free_phy_device(pdata); 3249 3250 /* Reset SFP data */ 3251 xgbe_phy_sfp_reset(phy_data); 3252 xgbe_phy_sfp_mod_absent(pdata); 3253 3254 /* Reset CDR support */ 3255 xgbe_phy_cdr_track(pdata); 3256 3257 /* Power off the PHY */ 3258 xgbe_phy_power_off(pdata); 3259 3260 /* Stop the I2C controller */ 3261 pdata->i2c_if.i2c_stop(pdata); 3262 } 3263 3264 static int xgbe_phy_start(struct xgbe_prv_data *pdata) 3265 { 3266 struct xgbe_phy_data *phy_data = pdata->phy_data; 3267 int ret; 3268 3269 /* Start the I2C controller */ 3270 ret = pdata->i2c_if.i2c_start(pdata); 3271 if (ret) 3272 return ret; 3273 3274 /* Set the proper MDIO mode for the re-driver */ 3275 if (phy_data->redrv && !phy_data->redrv_if) { 3276 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr, 3277 XGBE_MDIO_MODE_CL22); 3278 if (ret) { 3279 netdev_err(pdata->netdev, 3280 "redriver mdio port not compatible (%u)\n", 3281 phy_data->redrv_addr); 3282 return ret; 3283 } 3284 } 3285 3286 /* Start in highest supported mode */ 3287 xgbe_phy_set_mode(pdata, phy_data->start_mode); 3288 3289 /* Reset CDR support */ 3290 xgbe_phy_cdr_track(pdata); 3291 3292 /* After starting the I2C controller, we can check for an SFP */ 3293 switch (phy_data->port_mode) { 3294 case XGBE_PORT_MODE_SFP: 3295 xgbe_phy_sfp_detect(pdata); 3296 break; 3297 default: 3298 break; 3299 } 3300 3301 /* If we have an external PHY, start it */ 3302 ret = xgbe_phy_find_phy_device(pdata); 3303 if (ret) 3304 goto err_i2c; 3305 3306 return 0; 3307 3308 err_i2c: 3309 pdata->i2c_if.i2c_stop(pdata); 3310 3311 return ret; 3312 } 3313 3314 static int xgbe_phy_reset(struct xgbe_prv_data *pdata) 3315 { 3316 struct xgbe_phy_data *phy_data = pdata->phy_data; 3317 enum xgbe_mode cur_mode; 3318 int ret; 3319 3320 /* Reset by power cycling the PHY */ 3321 cur_mode = phy_data->cur_mode; 3322 xgbe_phy_power_off(pdata); 3323 xgbe_phy_set_mode(pdata, cur_mode); 3324 3325 if (!phy_data->phydev) 3326 return 0; 3327 3328 /* Reset the external PHY */ 3329 ret = xgbe_phy_mdio_reset(pdata); 3330 if (ret) 3331 return ret; 3332 3333 return phy_init_hw(phy_data->phydev); 3334 } 3335 3336 static void xgbe_phy_exit(struct xgbe_prv_data *pdata) 3337 { 3338 struct xgbe_phy_data *phy_data = pdata->phy_data; 3339 3340 /* Unregister for driving external PHYs */ 3341 mdiobus_unregister(phy_data->mii); 3342 } 3343 3344 static int xgbe_phy_init(struct xgbe_prv_data *pdata) 3345 { 3346 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 3347 struct xgbe_phy_data *phy_data; 3348 struct mii_bus *mii; 3349 int ret; 3350 3351 /* Check if enabled */ 3352 if (!xgbe_phy_port_enabled(pdata)) { 3353 dev_info(pdata->dev, "device is not enabled\n"); 3354 return -ENODEV; 3355 } 3356 3357 /* Initialize the I2C controller */ 3358 ret = pdata->i2c_if.i2c_init(pdata); 3359 if (ret) 3360 return ret; 3361 3362 phy_data = devm_kzalloc(pdata->dev, sizeof(*phy_data), GFP_KERNEL); 3363 if (!phy_data) 3364 return -ENOMEM; 3365 pdata->phy_data = phy_data; 3366 3367 phy_data->port_mode = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_MODE); 3368 phy_data->port_id = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_ID); 3369 phy_data->port_speeds = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS); 3370 phy_data->conn_type = XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE); 3371 phy_data->mdio_addr = XP_GET_BITS(pdata->pp0, XP_PROP_0, MDIO_ADDR); 3372 if (netif_msg_probe(pdata)) { 3373 dev_dbg(pdata->dev, "port mode=%u\n", phy_data->port_mode); 3374 dev_dbg(pdata->dev, "port id=%u\n", phy_data->port_id); 3375 dev_dbg(pdata->dev, "port speeds=%#x\n", phy_data->port_speeds); 3376 dev_dbg(pdata->dev, "conn type=%u\n", phy_data->conn_type); 3377 dev_dbg(pdata->dev, "mdio addr=%u\n", phy_data->mdio_addr); 3378 } 3379 3380 phy_data->redrv = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_PRESENT); 3381 phy_data->redrv_if = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_IF); 3382 phy_data->redrv_addr = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_ADDR); 3383 phy_data->redrv_lane = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_LANE); 3384 phy_data->redrv_model = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_MODEL); 3385 if (phy_data->redrv && netif_msg_probe(pdata)) { 3386 dev_dbg(pdata->dev, "redrv present\n"); 3387 dev_dbg(pdata->dev, "redrv i/f=%u\n", phy_data->redrv_if); 3388 dev_dbg(pdata->dev, "redrv addr=%#x\n", phy_data->redrv_addr); 3389 dev_dbg(pdata->dev, "redrv lane=%u\n", phy_data->redrv_lane); 3390 dev_dbg(pdata->dev, "redrv model=%u\n", phy_data->redrv_model); 3391 } 3392 3393 /* Validate the connection requested */ 3394 if (xgbe_phy_conn_type_mismatch(pdata)) { 3395 dev_err(pdata->dev, "phy mode/connection mismatch (%#x/%#x)\n", 3396 phy_data->port_mode, phy_data->conn_type); 3397 return -EINVAL; 3398 } 3399 3400 /* Validate the mode requested */ 3401 if (xgbe_phy_port_mode_mismatch(pdata)) { 3402 dev_err(pdata->dev, "phy mode/speed mismatch (%#x/%#x)\n", 3403 phy_data->port_mode, phy_data->port_speeds); 3404 return -EINVAL; 3405 } 3406 3407 /* Check for and validate MDIO reset support */ 3408 ret = xgbe_phy_mdio_reset_setup(pdata); 3409 if (ret) 3410 return ret; 3411 3412 /* Validate the re-driver information */ 3413 if (xgbe_phy_redrv_error(phy_data)) { 3414 dev_err(pdata->dev, "phy re-driver settings error\n"); 3415 return -EINVAL; 3416 } 3417 pdata->kr_redrv = phy_data->redrv; 3418 3419 /* Indicate current mode is unknown */ 3420 phy_data->cur_mode = XGBE_MODE_UNKNOWN; 3421 3422 /* Initialize supported features */ 3423 XGBE_ZERO_SUP(lks); 3424 3425 switch (phy_data->port_mode) { 3426 /* Backplane support */ 3427 case XGBE_PORT_MODE_BACKPLANE: 3428 XGBE_SET_SUP(lks, Autoneg); 3429 fallthrough; 3430 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 3431 XGBE_SET_SUP(lks, Pause); 3432 XGBE_SET_SUP(lks, Asym_Pause); 3433 XGBE_SET_SUP(lks, Backplane); 3434 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) { 3435 XGBE_SET_SUP(lks, 1000baseKX_Full); 3436 phy_data->start_mode = XGBE_MODE_KX_1000; 3437 } 3438 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) { 3439 XGBE_SET_SUP(lks, 10000baseKR_Full); 3440 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 3441 XGBE_SET_SUP(lks, 10000baseR_FEC); 3442 phy_data->start_mode = XGBE_MODE_KR; 3443 } 3444 3445 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE; 3446 break; 3447 case XGBE_PORT_MODE_BACKPLANE_2500: 3448 XGBE_SET_SUP(lks, Pause); 3449 XGBE_SET_SUP(lks, Asym_Pause); 3450 XGBE_SET_SUP(lks, Backplane); 3451 XGBE_SET_SUP(lks, 2500baseX_Full); 3452 phy_data->start_mode = XGBE_MODE_KX_2500; 3453 3454 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE; 3455 break; 3456 3457 /* MDIO 1GBase-T support */ 3458 case XGBE_PORT_MODE_1000BASE_T: 3459 XGBE_SET_SUP(lks, Autoneg); 3460 XGBE_SET_SUP(lks, Pause); 3461 XGBE_SET_SUP(lks, Asym_Pause); 3462 XGBE_SET_SUP(lks, TP); 3463 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10) { 3464 XGBE_SET_SUP(lks, 10baseT_Full); 3465 phy_data->start_mode = XGBE_MODE_SGMII_10; 3466 } 3467 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) { 3468 XGBE_SET_SUP(lks, 100baseT_Full); 3469 phy_data->start_mode = XGBE_MODE_SGMII_100; 3470 } 3471 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) { 3472 XGBE_SET_SUP(lks, 1000baseT_Full); 3473 phy_data->start_mode = XGBE_MODE_SGMII_1000; 3474 } 3475 3476 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22; 3477 break; 3478 3479 /* MDIO Base-X support */ 3480 case XGBE_PORT_MODE_1000BASE_X: 3481 XGBE_SET_SUP(lks, Autoneg); 3482 XGBE_SET_SUP(lks, Pause); 3483 XGBE_SET_SUP(lks, Asym_Pause); 3484 XGBE_SET_SUP(lks, FIBRE); 3485 XGBE_SET_SUP(lks, 1000baseX_Full); 3486 phy_data->start_mode = XGBE_MODE_X; 3487 3488 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22; 3489 break; 3490 3491 /* MDIO NBase-T support */ 3492 case XGBE_PORT_MODE_NBASE_T: 3493 XGBE_SET_SUP(lks, Autoneg); 3494 XGBE_SET_SUP(lks, Pause); 3495 XGBE_SET_SUP(lks, Asym_Pause); 3496 XGBE_SET_SUP(lks, TP); 3497 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10) { 3498 XGBE_SET_SUP(lks, 10baseT_Full); 3499 phy_data->start_mode = XGBE_MODE_SGMII_10; 3500 } 3501 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) { 3502 XGBE_SET_SUP(lks, 100baseT_Full); 3503 phy_data->start_mode = XGBE_MODE_SGMII_100; 3504 } 3505 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) { 3506 XGBE_SET_SUP(lks, 1000baseT_Full); 3507 phy_data->start_mode = XGBE_MODE_SGMII_1000; 3508 } 3509 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) { 3510 XGBE_SET_SUP(lks, 2500baseT_Full); 3511 phy_data->start_mode = XGBE_MODE_KX_2500; 3512 } 3513 3514 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45; 3515 break; 3516 3517 /* 10GBase-T support */ 3518 case XGBE_PORT_MODE_10GBASE_T: 3519 XGBE_SET_SUP(lks, Autoneg); 3520 XGBE_SET_SUP(lks, Pause); 3521 XGBE_SET_SUP(lks, Asym_Pause); 3522 XGBE_SET_SUP(lks, TP); 3523 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10) { 3524 XGBE_SET_SUP(lks, 10baseT_Full); 3525 phy_data->start_mode = XGBE_MODE_SGMII_10; 3526 } 3527 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) { 3528 XGBE_SET_SUP(lks, 100baseT_Full); 3529 phy_data->start_mode = XGBE_MODE_SGMII_100; 3530 } 3531 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) { 3532 XGBE_SET_SUP(lks, 1000baseT_Full); 3533 phy_data->start_mode = XGBE_MODE_SGMII_1000; 3534 } 3535 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) { 3536 XGBE_SET_SUP(lks, 2500baseT_Full); 3537 phy_data->start_mode = XGBE_MODE_KX_2500; 3538 } 3539 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) { 3540 XGBE_SET_SUP(lks, 10000baseT_Full); 3541 phy_data->start_mode = XGBE_MODE_KR; 3542 } 3543 3544 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45; 3545 break; 3546 3547 /* 10GBase-R support */ 3548 case XGBE_PORT_MODE_10GBASE_R: 3549 XGBE_SET_SUP(lks, Autoneg); 3550 XGBE_SET_SUP(lks, Pause); 3551 XGBE_SET_SUP(lks, Asym_Pause); 3552 XGBE_SET_SUP(lks, FIBRE); 3553 XGBE_SET_SUP(lks, 10000baseSR_Full); 3554 XGBE_SET_SUP(lks, 10000baseLR_Full); 3555 XGBE_SET_SUP(lks, 10000baseLRM_Full); 3556 XGBE_SET_SUP(lks, 10000baseER_Full); 3557 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 3558 XGBE_SET_SUP(lks, 10000baseR_FEC); 3559 phy_data->start_mode = XGBE_MODE_SFI; 3560 3561 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE; 3562 break; 3563 3564 /* SFP support */ 3565 case XGBE_PORT_MODE_SFP: 3566 XGBE_SET_SUP(lks, Autoneg); 3567 XGBE_SET_SUP(lks, Pause); 3568 XGBE_SET_SUP(lks, Asym_Pause); 3569 XGBE_SET_SUP(lks, TP); 3570 XGBE_SET_SUP(lks, FIBRE); 3571 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10) 3572 phy_data->start_mode = XGBE_MODE_SGMII_10; 3573 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) 3574 phy_data->start_mode = XGBE_MODE_SGMII_100; 3575 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) 3576 phy_data->start_mode = XGBE_MODE_SGMII_1000; 3577 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) 3578 phy_data->start_mode = XGBE_MODE_SFI; 3579 3580 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22; 3581 3582 xgbe_phy_sfp_setup(pdata); 3583 break; 3584 default: 3585 return -EINVAL; 3586 } 3587 3588 if (netif_msg_probe(pdata)) 3589 dev_dbg(pdata->dev, "phy supported=0x%*pb\n", 3590 __ETHTOOL_LINK_MODE_MASK_NBITS, 3591 lks->link_modes.supported); 3592 3593 if ((phy_data->conn_type & XGBE_CONN_TYPE_MDIO) && 3594 (phy_data->phydev_mode != XGBE_MDIO_MODE_NONE)) { 3595 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr, 3596 phy_data->phydev_mode); 3597 if (ret) { 3598 dev_err(pdata->dev, 3599 "mdio port/clause not compatible (%d/%u)\n", 3600 phy_data->mdio_addr, phy_data->phydev_mode); 3601 return -EINVAL; 3602 } 3603 } 3604 3605 if (phy_data->redrv && !phy_data->redrv_if) { 3606 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr, 3607 XGBE_MDIO_MODE_CL22); 3608 if (ret) { 3609 dev_err(pdata->dev, 3610 "redriver mdio port not compatible (%u)\n", 3611 phy_data->redrv_addr); 3612 return -EINVAL; 3613 } 3614 } 3615 3616 phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT; 3617 3618 /* Register for driving external PHYs */ 3619 mii = devm_mdiobus_alloc(pdata->dev); 3620 if (!mii) { 3621 dev_err(pdata->dev, "mdiobus_alloc failed\n"); 3622 return -ENOMEM; 3623 } 3624 3625 mii->priv = pdata; 3626 mii->name = "amd-xgbe-mii"; 3627 mii->read = xgbe_phy_mii_read_c22; 3628 mii->write = xgbe_phy_mii_write_c22; 3629 mii->read_c45 = xgbe_phy_mii_read_c45; 3630 mii->write_c45 = xgbe_phy_mii_write_c45; 3631 mii->parent = pdata->dev; 3632 mii->phy_mask = ~0; 3633 snprintf(mii->id, sizeof(mii->id), "%s", dev_name(pdata->dev)); 3634 ret = mdiobus_register(mii); 3635 if (ret) { 3636 dev_err(pdata->dev, "mdiobus_register failed\n"); 3637 return ret; 3638 } 3639 phy_data->mii = mii; 3640 3641 return 0; 3642 } 3643 3644 void xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *phy_if) 3645 { 3646 struct xgbe_phy_impl_if *phy_impl = &phy_if->phy_impl; 3647 3648 phy_impl->init = xgbe_phy_init; 3649 phy_impl->exit = xgbe_phy_exit; 3650 3651 phy_impl->reset = xgbe_phy_reset; 3652 phy_impl->start = xgbe_phy_start; 3653 phy_impl->stop = xgbe_phy_stop; 3654 3655 phy_impl->link_status = xgbe_phy_link_status; 3656 3657 phy_impl->valid_speed = xgbe_phy_valid_speed; 3658 3659 phy_impl->use_mode = xgbe_phy_use_mode; 3660 phy_impl->set_mode = xgbe_phy_set_mode; 3661 phy_impl->get_mode = xgbe_phy_get_mode; 3662 phy_impl->switch_mode = xgbe_phy_switch_mode; 3663 phy_impl->cur_mode = xgbe_phy_cur_mode; 3664 3665 phy_impl->an_mode = xgbe_phy_an_mode; 3666 3667 phy_impl->an_config = xgbe_phy_an_config; 3668 3669 phy_impl->an_advertising = xgbe_phy_an_advertising; 3670 3671 phy_impl->an_outcome = xgbe_phy_an_outcome; 3672 3673 phy_impl->an_pre = xgbe_phy_an_pre; 3674 phy_impl->an_post = xgbe_phy_an_post; 3675 3676 phy_impl->kr_training_pre = xgbe_phy_kr_training_pre; 3677 phy_impl->kr_training_post = xgbe_phy_kr_training_post; 3678 3679 phy_impl->module_info = xgbe_phy_module_info; 3680 phy_impl->module_eeprom = xgbe_phy_module_eeprom; 3681 } 3682