1 /* 2 * AMD 10Gb Ethernet driver 3 * 4 * This file is available to you under your choice of the following two 5 * licenses: 6 * 7 * License 1: GPLv2 8 * 9 * Copyright (c) 2016 Advanced Micro Devices, Inc. 10 * 11 * This file is free software; you may copy, redistribute and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation, either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program. If not, see <http://www.gnu.org/licenses/>. 23 * 24 * This file incorporates work covered by the following copyright and 25 * permission notice: 26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 28 * Inc. unless otherwise expressly agreed to in writing between Synopsys 29 * and you. 30 * 31 * The Software IS NOT an item of Licensed Software or Licensed Product 32 * under any End User Software License Agreement or Agreement for Licensed 33 * Product with Synopsys or any supplement thereto. Permission is hereby 34 * granted, free of charge, to any person obtaining a copy of this software 35 * annotated with this license and the Software, to deal in the Software 36 * without restriction, including without limitation the rights to use, 37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 38 * of the Software, and to permit persons to whom the Software is furnished 39 * to do so, subject to the following conditions: 40 * 41 * The above copyright notice and this permission notice shall be included 42 * in all copies or substantial portions of the Software. 43 * 44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 54 * THE POSSIBILITY OF SUCH DAMAGE. 55 * 56 * 57 * License 2: Modified BSD 58 * 59 * Copyright (c) 2016 Advanced Micro Devices, Inc. 60 * All rights reserved. 61 * 62 * Redistribution and use in source and binary forms, with or without 63 * modification, are permitted provided that the following conditions are met: 64 * * Redistributions of source code must retain the above copyright 65 * notice, this list of conditions and the following disclaimer. 66 * * Redistributions in binary form must reproduce the above copyright 67 * notice, this list of conditions and the following disclaimer in the 68 * documentation and/or other materials provided with the distribution. 69 * * Neither the name of Advanced Micro Devices, Inc. nor the 70 * names of its contributors may be used to endorse or promote products 71 * derived from this software without specific prior written permission. 72 * 73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY 77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 83 * 84 * This file incorporates work covered by the following copyright and 85 * permission notice: 86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 88 * Inc. unless otherwise expressly agreed to in writing between Synopsys 89 * and you. 90 * 91 * The Software IS NOT an item of Licensed Software or Licensed Product 92 * under any End User Software License Agreement or Agreement for Licensed 93 * Product with Synopsys or any supplement thereto. Permission is hereby 94 * granted, free of charge, to any person obtaining a copy of this software 95 * annotated with this license and the Software, to deal in the Software 96 * without restriction, including without limitation the rights to use, 97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 98 * of the Software, and to permit persons to whom the Software is furnished 99 * to do so, subject to the following conditions: 100 * 101 * The above copyright notice and this permission notice shall be included 102 * in all copies or substantial portions of the Software. 103 * 104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 114 * THE POSSIBILITY OF SUCH DAMAGE. 115 */ 116 117 #include <linux/module.h> 118 #include <linux/device.h> 119 #include <linux/kmod.h> 120 #include <linux/mdio.h> 121 #include <linux/phy.h> 122 #include <linux/ethtool.h> 123 124 #include "xgbe.h" 125 #include "xgbe-common.h" 126 127 #define XGBE_PHY_PORT_SPEED_100 BIT(0) 128 #define XGBE_PHY_PORT_SPEED_1000 BIT(1) 129 #define XGBE_PHY_PORT_SPEED_2500 BIT(2) 130 #define XGBE_PHY_PORT_SPEED_10000 BIT(3) 131 132 #define XGBE_MUTEX_RELEASE 0x80000000 133 134 #define XGBE_SFP_DIRECT 7 135 136 /* I2C target addresses */ 137 #define XGBE_SFP_SERIAL_ID_ADDRESS 0x50 138 #define XGBE_SFP_DIAG_INFO_ADDRESS 0x51 139 #define XGBE_SFP_PHY_ADDRESS 0x56 140 #define XGBE_GPIO_ADDRESS_PCA9555 0x20 141 142 /* SFP sideband signal indicators */ 143 #define XGBE_GPIO_NO_TX_FAULT BIT(0) 144 #define XGBE_GPIO_NO_RATE_SELECT BIT(1) 145 #define XGBE_GPIO_NO_MOD_ABSENT BIT(2) 146 #define XGBE_GPIO_NO_RX_LOS BIT(3) 147 148 /* Rate-change complete wait/retry count */ 149 #define XGBE_RATECHANGE_COUNT 500 150 151 /* CDR delay values for KR support (in usec) */ 152 #define XGBE_CDR_DELAY_INIT 10000 153 #define XGBE_CDR_DELAY_INC 10000 154 #define XGBE_CDR_DELAY_MAX 100000 155 156 /* RRC frequency during link status check */ 157 #define XGBE_RRC_FREQUENCY 10 158 159 enum xgbe_port_mode { 160 XGBE_PORT_MODE_RSVD = 0, 161 XGBE_PORT_MODE_BACKPLANE, 162 XGBE_PORT_MODE_BACKPLANE_2500, 163 XGBE_PORT_MODE_1000BASE_T, 164 XGBE_PORT_MODE_1000BASE_X, 165 XGBE_PORT_MODE_NBASE_T, 166 XGBE_PORT_MODE_10GBASE_T, 167 XGBE_PORT_MODE_10GBASE_R, 168 XGBE_PORT_MODE_SFP, 169 XGBE_PORT_MODE_MAX, 170 }; 171 172 enum xgbe_conn_type { 173 XGBE_CONN_TYPE_NONE = 0, 174 XGBE_CONN_TYPE_SFP, 175 XGBE_CONN_TYPE_MDIO, 176 XGBE_CONN_TYPE_RSVD1, 177 XGBE_CONN_TYPE_BACKPLANE, 178 XGBE_CONN_TYPE_MAX, 179 }; 180 181 /* SFP/SFP+ related definitions */ 182 enum xgbe_sfp_comm { 183 XGBE_SFP_COMM_DIRECT = 0, 184 XGBE_SFP_COMM_PCA9545, 185 }; 186 187 enum xgbe_sfp_cable { 188 XGBE_SFP_CABLE_UNKNOWN = 0, 189 XGBE_SFP_CABLE_ACTIVE, 190 XGBE_SFP_CABLE_PASSIVE, 191 }; 192 193 enum xgbe_sfp_base { 194 XGBE_SFP_BASE_UNKNOWN = 0, 195 XGBE_SFP_BASE_1000_T, 196 XGBE_SFP_BASE_1000_SX, 197 XGBE_SFP_BASE_1000_LX, 198 XGBE_SFP_BASE_1000_CX, 199 XGBE_SFP_BASE_10000_SR, 200 XGBE_SFP_BASE_10000_LR, 201 XGBE_SFP_BASE_10000_LRM, 202 XGBE_SFP_BASE_10000_ER, 203 XGBE_SFP_BASE_10000_CR, 204 }; 205 206 enum xgbe_sfp_speed { 207 XGBE_SFP_SPEED_UNKNOWN = 0, 208 XGBE_SFP_SPEED_100_1000, 209 XGBE_SFP_SPEED_1000, 210 XGBE_SFP_SPEED_10000, 211 }; 212 213 /* SFP Serial ID Base ID values relative to an offset of 0 */ 214 #define XGBE_SFP_BASE_ID 0 215 #define XGBE_SFP_ID_SFP 0x03 216 217 #define XGBE_SFP_BASE_EXT_ID 1 218 #define XGBE_SFP_EXT_ID_SFP 0x04 219 220 #define XGBE_SFP_BASE_10GBE_CC 3 221 #define XGBE_SFP_BASE_10GBE_CC_SR BIT(4) 222 #define XGBE_SFP_BASE_10GBE_CC_LR BIT(5) 223 #define XGBE_SFP_BASE_10GBE_CC_LRM BIT(6) 224 #define XGBE_SFP_BASE_10GBE_CC_ER BIT(7) 225 226 #define XGBE_SFP_BASE_1GBE_CC 6 227 #define XGBE_SFP_BASE_1GBE_CC_SX BIT(0) 228 #define XGBE_SFP_BASE_1GBE_CC_LX BIT(1) 229 #define XGBE_SFP_BASE_1GBE_CC_CX BIT(2) 230 #define XGBE_SFP_BASE_1GBE_CC_T BIT(3) 231 232 #define XGBE_SFP_BASE_CABLE 8 233 #define XGBE_SFP_BASE_CABLE_PASSIVE BIT(2) 234 #define XGBE_SFP_BASE_CABLE_ACTIVE BIT(3) 235 236 #define XGBE_SFP_BASE_BR 12 237 #define XGBE_SFP_BASE_BR_1GBE_MIN 0x0a 238 #define XGBE_SFP_BASE_BR_1GBE_MAX 0x0d 239 #define XGBE_SFP_BASE_BR_10GBE_MIN 0x64 240 #define XGBE_SFP_BASE_BR_10GBE_MAX 0x68 241 242 #define XGBE_SFP_BASE_CU_CABLE_LEN 18 243 244 #define XGBE_SFP_BASE_VENDOR_NAME 20 245 #define XGBE_SFP_BASE_VENDOR_NAME_LEN 16 246 #define XGBE_SFP_BASE_VENDOR_PN 40 247 #define XGBE_SFP_BASE_VENDOR_PN_LEN 16 248 #define XGBE_SFP_BASE_VENDOR_REV 56 249 #define XGBE_SFP_BASE_VENDOR_REV_LEN 4 250 251 #define XGBE_SFP_BASE_CC 63 252 253 /* SFP Serial ID Extended ID values relative to an offset of 64 */ 254 #define XGBE_SFP_BASE_VENDOR_SN 4 255 #define XGBE_SFP_BASE_VENDOR_SN_LEN 16 256 257 #define XGBE_SFP_EXTD_OPT1 1 258 #define XGBE_SFP_EXTD_OPT1_RX_LOS BIT(1) 259 #define XGBE_SFP_EXTD_OPT1_TX_FAULT BIT(3) 260 261 #define XGBE_SFP_EXTD_DIAG 28 262 #define XGBE_SFP_EXTD_DIAG_ADDR_CHANGE BIT(2) 263 264 #define XGBE_SFP_EXTD_SFF_8472 30 265 266 #define XGBE_SFP_EXTD_CC 31 267 268 struct xgbe_sfp_eeprom { 269 u8 base[64]; 270 u8 extd[32]; 271 u8 vendor[32]; 272 }; 273 274 #define XGBE_SFP_DIAGS_SUPPORTED(_x) \ 275 ((_x)->extd[XGBE_SFP_EXTD_SFF_8472] && \ 276 !((_x)->extd[XGBE_SFP_EXTD_DIAG] & XGBE_SFP_EXTD_DIAG_ADDR_CHANGE)) 277 278 #define XGBE_SFP_EEPROM_BASE_LEN 256 279 #define XGBE_SFP_EEPROM_DIAG_LEN 256 280 #define XGBE_SFP_EEPROM_MAX (XGBE_SFP_EEPROM_BASE_LEN + \ 281 XGBE_SFP_EEPROM_DIAG_LEN) 282 283 #define XGBE_BEL_FUSE_VENDOR "BEL-FUSE " 284 #define XGBE_BEL_FUSE_PARTNO "1GBT-SFP06 " 285 286 struct xgbe_sfp_ascii { 287 union { 288 char vendor[XGBE_SFP_BASE_VENDOR_NAME_LEN + 1]; 289 char partno[XGBE_SFP_BASE_VENDOR_PN_LEN + 1]; 290 char rev[XGBE_SFP_BASE_VENDOR_REV_LEN + 1]; 291 char serno[XGBE_SFP_BASE_VENDOR_SN_LEN + 1]; 292 } u; 293 }; 294 295 /* MDIO PHY reset types */ 296 enum xgbe_mdio_reset { 297 XGBE_MDIO_RESET_NONE = 0, 298 XGBE_MDIO_RESET_I2C_GPIO, 299 XGBE_MDIO_RESET_INT_GPIO, 300 XGBE_MDIO_RESET_MAX, 301 }; 302 303 /* Re-driver related definitions */ 304 enum xgbe_phy_redrv_if { 305 XGBE_PHY_REDRV_IF_MDIO = 0, 306 XGBE_PHY_REDRV_IF_I2C, 307 XGBE_PHY_REDRV_IF_MAX, 308 }; 309 310 enum xgbe_phy_redrv_model { 311 XGBE_PHY_REDRV_MODEL_4223 = 0, 312 XGBE_PHY_REDRV_MODEL_4227, 313 XGBE_PHY_REDRV_MODEL_MAX, 314 }; 315 316 enum xgbe_phy_redrv_mode { 317 XGBE_PHY_REDRV_MODE_CX = 5, 318 XGBE_PHY_REDRV_MODE_SR = 9, 319 }; 320 321 #define XGBE_PHY_REDRV_MODE_REG 0x12b0 322 323 /* PHY related configuration information */ 324 struct xgbe_phy_data { 325 enum xgbe_port_mode port_mode; 326 327 unsigned int port_id; 328 329 unsigned int port_speeds; 330 331 enum xgbe_conn_type conn_type; 332 333 enum xgbe_mode cur_mode; 334 enum xgbe_mode start_mode; 335 336 unsigned int rrc_count; 337 338 unsigned int mdio_addr; 339 340 /* SFP Support */ 341 enum xgbe_sfp_comm sfp_comm; 342 unsigned int sfp_mux_address; 343 unsigned int sfp_mux_channel; 344 345 unsigned int sfp_gpio_address; 346 unsigned int sfp_gpio_mask; 347 unsigned int sfp_gpio_inputs; 348 unsigned int sfp_gpio_rx_los; 349 unsigned int sfp_gpio_tx_fault; 350 unsigned int sfp_gpio_mod_absent; 351 unsigned int sfp_gpio_rate_select; 352 353 unsigned int sfp_rx_los; 354 unsigned int sfp_tx_fault; 355 unsigned int sfp_mod_absent; 356 unsigned int sfp_changed; 357 unsigned int sfp_phy_avail; 358 unsigned int sfp_cable_len; 359 enum xgbe_sfp_base sfp_base; 360 enum xgbe_sfp_cable sfp_cable; 361 enum xgbe_sfp_speed sfp_speed; 362 struct xgbe_sfp_eeprom sfp_eeprom; 363 364 /* External PHY support */ 365 enum xgbe_mdio_mode phydev_mode; 366 struct mii_bus *mii; 367 struct phy_device *phydev; 368 enum xgbe_mdio_reset mdio_reset; 369 unsigned int mdio_reset_addr; 370 unsigned int mdio_reset_gpio; 371 372 /* Re-driver support */ 373 unsigned int redrv; 374 unsigned int redrv_if; 375 unsigned int redrv_addr; 376 unsigned int redrv_lane; 377 unsigned int redrv_model; 378 379 /* KR AN support */ 380 unsigned int phy_cdr_notrack; 381 unsigned int phy_cdr_delay; 382 }; 383 384 /* I2C, MDIO and GPIO lines are muxed, so only one device at a time */ 385 static DEFINE_MUTEX(xgbe_phy_comm_lock); 386 387 static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata); 388 389 static int xgbe_phy_i2c_xfer(struct xgbe_prv_data *pdata, 390 struct xgbe_i2c_op *i2c_op) 391 { 392 return pdata->i2c_if.i2c_xfer(pdata, i2c_op); 393 } 394 395 static int xgbe_phy_redrv_write(struct xgbe_prv_data *pdata, unsigned int reg, 396 unsigned int val) 397 { 398 struct xgbe_phy_data *phy_data = pdata->phy_data; 399 struct xgbe_i2c_op i2c_op; 400 __be16 *redrv_val; 401 u8 redrv_data[5], csum; 402 unsigned int i, retry; 403 int ret; 404 405 /* High byte of register contains read/write indicator */ 406 redrv_data[0] = ((reg >> 8) & 0xff) << 1; 407 redrv_data[1] = reg & 0xff; 408 redrv_val = (__be16 *)&redrv_data[2]; 409 *redrv_val = cpu_to_be16(val); 410 411 /* Calculate 1 byte checksum */ 412 csum = 0; 413 for (i = 0; i < 4; i++) { 414 csum += redrv_data[i]; 415 if (redrv_data[i] > csum) 416 csum++; 417 } 418 redrv_data[4] = ~csum; 419 420 retry = 1; 421 again1: 422 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 423 i2c_op.target = phy_data->redrv_addr; 424 i2c_op.len = sizeof(redrv_data); 425 i2c_op.buf = redrv_data; 426 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 427 if (ret) { 428 if ((ret == -EAGAIN) && retry--) 429 goto again1; 430 431 return ret; 432 } 433 434 retry = 1; 435 again2: 436 i2c_op.cmd = XGBE_I2C_CMD_READ; 437 i2c_op.target = phy_data->redrv_addr; 438 i2c_op.len = 1; 439 i2c_op.buf = redrv_data; 440 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 441 if (ret) { 442 if ((ret == -EAGAIN) && retry--) 443 goto again2; 444 445 return ret; 446 } 447 448 if (redrv_data[0] != 0xff) { 449 netif_dbg(pdata, drv, pdata->netdev, 450 "Redriver write checksum error\n"); 451 ret = -EIO; 452 } 453 454 return ret; 455 } 456 457 static int xgbe_phy_i2c_write(struct xgbe_prv_data *pdata, unsigned int target, 458 void *val, unsigned int val_len) 459 { 460 struct xgbe_i2c_op i2c_op; 461 int retry, ret; 462 463 retry = 1; 464 again: 465 /* Write the specfied register */ 466 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 467 i2c_op.target = target; 468 i2c_op.len = val_len; 469 i2c_op.buf = val; 470 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 471 if ((ret == -EAGAIN) && retry--) 472 goto again; 473 474 return ret; 475 } 476 477 static int xgbe_phy_i2c_read(struct xgbe_prv_data *pdata, unsigned int target, 478 void *reg, unsigned int reg_len, 479 void *val, unsigned int val_len) 480 { 481 struct xgbe_i2c_op i2c_op; 482 int retry, ret; 483 484 retry = 1; 485 again1: 486 /* Set the specified register to read */ 487 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 488 i2c_op.target = target; 489 i2c_op.len = reg_len; 490 i2c_op.buf = reg; 491 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 492 if (ret) { 493 if ((ret == -EAGAIN) && retry--) 494 goto again1; 495 496 return ret; 497 } 498 499 retry = 1; 500 again2: 501 /* Read the specfied register */ 502 i2c_op.cmd = XGBE_I2C_CMD_READ; 503 i2c_op.target = target; 504 i2c_op.len = val_len; 505 i2c_op.buf = val; 506 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 507 if ((ret == -EAGAIN) && retry--) 508 goto again2; 509 510 return ret; 511 } 512 513 static int xgbe_phy_sfp_put_mux(struct xgbe_prv_data *pdata) 514 { 515 struct xgbe_phy_data *phy_data = pdata->phy_data; 516 struct xgbe_i2c_op i2c_op; 517 u8 mux_channel; 518 519 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT) 520 return 0; 521 522 /* Select no mux channels */ 523 mux_channel = 0; 524 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 525 i2c_op.target = phy_data->sfp_mux_address; 526 i2c_op.len = sizeof(mux_channel); 527 i2c_op.buf = &mux_channel; 528 529 return xgbe_phy_i2c_xfer(pdata, &i2c_op); 530 } 531 532 static int xgbe_phy_sfp_get_mux(struct xgbe_prv_data *pdata) 533 { 534 struct xgbe_phy_data *phy_data = pdata->phy_data; 535 struct xgbe_i2c_op i2c_op; 536 u8 mux_channel; 537 538 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT) 539 return 0; 540 541 /* Select desired mux channel */ 542 mux_channel = 1 << phy_data->sfp_mux_channel; 543 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 544 i2c_op.target = phy_data->sfp_mux_address; 545 i2c_op.len = sizeof(mux_channel); 546 i2c_op.buf = &mux_channel; 547 548 return xgbe_phy_i2c_xfer(pdata, &i2c_op); 549 } 550 551 static void xgbe_phy_put_comm_ownership(struct xgbe_prv_data *pdata) 552 { 553 mutex_unlock(&xgbe_phy_comm_lock); 554 } 555 556 static int xgbe_phy_get_comm_ownership(struct xgbe_prv_data *pdata) 557 { 558 struct xgbe_phy_data *phy_data = pdata->phy_data; 559 unsigned long timeout; 560 unsigned int mutex_id; 561 562 /* The I2C and MDIO/GPIO bus is multiplexed between multiple devices, 563 * the driver needs to take the software mutex and then the hardware 564 * mutexes before being able to use the busses. 565 */ 566 mutex_lock(&xgbe_phy_comm_lock); 567 568 /* Clear the mutexes */ 569 XP_IOWRITE(pdata, XP_I2C_MUTEX, XGBE_MUTEX_RELEASE); 570 XP_IOWRITE(pdata, XP_MDIO_MUTEX, XGBE_MUTEX_RELEASE); 571 572 /* Mutex formats are the same for I2C and MDIO/GPIO */ 573 mutex_id = 0; 574 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ID, phy_data->port_id); 575 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ACTIVE, 1); 576 577 timeout = jiffies + (5 * HZ); 578 while (time_before(jiffies, timeout)) { 579 /* Must be all zeroes in order to obtain the mutex */ 580 if (XP_IOREAD(pdata, XP_I2C_MUTEX) || 581 XP_IOREAD(pdata, XP_MDIO_MUTEX)) { 582 usleep_range(100, 200); 583 continue; 584 } 585 586 /* Obtain the mutex */ 587 XP_IOWRITE(pdata, XP_I2C_MUTEX, mutex_id); 588 XP_IOWRITE(pdata, XP_MDIO_MUTEX, mutex_id); 589 590 return 0; 591 } 592 593 mutex_unlock(&xgbe_phy_comm_lock); 594 595 netdev_err(pdata->netdev, "unable to obtain hardware mutexes\n"); 596 597 return -ETIMEDOUT; 598 } 599 600 static int xgbe_phy_mdio_mii_write(struct xgbe_prv_data *pdata, int addr, 601 int reg, u16 val) 602 { 603 struct xgbe_phy_data *phy_data = pdata->phy_data; 604 605 if (reg & MII_ADDR_C45) { 606 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45) 607 return -ENOTSUPP; 608 } else { 609 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22) 610 return -ENOTSUPP; 611 } 612 613 return pdata->hw_if.write_ext_mii_regs(pdata, addr, reg, val); 614 } 615 616 static int xgbe_phy_i2c_mii_write(struct xgbe_prv_data *pdata, int reg, u16 val) 617 { 618 __be16 *mii_val; 619 u8 mii_data[3]; 620 int ret; 621 622 ret = xgbe_phy_sfp_get_mux(pdata); 623 if (ret) 624 return ret; 625 626 mii_data[0] = reg & 0xff; 627 mii_val = (__be16 *)&mii_data[1]; 628 *mii_val = cpu_to_be16(val); 629 630 ret = xgbe_phy_i2c_write(pdata, XGBE_SFP_PHY_ADDRESS, 631 mii_data, sizeof(mii_data)); 632 633 xgbe_phy_sfp_put_mux(pdata); 634 635 return ret; 636 } 637 638 static int xgbe_phy_mii_write(struct mii_bus *mii, int addr, int reg, u16 val) 639 { 640 struct xgbe_prv_data *pdata = mii->priv; 641 struct xgbe_phy_data *phy_data = pdata->phy_data; 642 int ret; 643 644 ret = xgbe_phy_get_comm_ownership(pdata); 645 if (ret) 646 return ret; 647 648 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP) 649 ret = xgbe_phy_i2c_mii_write(pdata, reg, val); 650 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO) 651 ret = xgbe_phy_mdio_mii_write(pdata, addr, reg, val); 652 else 653 ret = -ENOTSUPP; 654 655 xgbe_phy_put_comm_ownership(pdata); 656 657 return ret; 658 } 659 660 static int xgbe_phy_mdio_mii_read(struct xgbe_prv_data *pdata, int addr, 661 int reg) 662 { 663 struct xgbe_phy_data *phy_data = pdata->phy_data; 664 665 if (reg & MII_ADDR_C45) { 666 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45) 667 return -ENOTSUPP; 668 } else { 669 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22) 670 return -ENOTSUPP; 671 } 672 673 return pdata->hw_if.read_ext_mii_regs(pdata, addr, reg); 674 } 675 676 static int xgbe_phy_i2c_mii_read(struct xgbe_prv_data *pdata, int reg) 677 { 678 __be16 mii_val; 679 u8 mii_reg; 680 int ret; 681 682 ret = xgbe_phy_sfp_get_mux(pdata); 683 if (ret) 684 return ret; 685 686 mii_reg = reg; 687 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_PHY_ADDRESS, 688 &mii_reg, sizeof(mii_reg), 689 &mii_val, sizeof(mii_val)); 690 if (!ret) 691 ret = be16_to_cpu(mii_val); 692 693 xgbe_phy_sfp_put_mux(pdata); 694 695 return ret; 696 } 697 698 static int xgbe_phy_mii_read(struct mii_bus *mii, int addr, int reg) 699 { 700 struct xgbe_prv_data *pdata = mii->priv; 701 struct xgbe_phy_data *phy_data = pdata->phy_data; 702 int ret; 703 704 ret = xgbe_phy_get_comm_ownership(pdata); 705 if (ret) 706 return ret; 707 708 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP) 709 ret = xgbe_phy_i2c_mii_read(pdata, reg); 710 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO) 711 ret = xgbe_phy_mdio_mii_read(pdata, addr, reg); 712 else 713 ret = -ENOTSUPP; 714 715 xgbe_phy_put_comm_ownership(pdata); 716 717 return ret; 718 } 719 720 static void xgbe_phy_sfp_phy_settings(struct xgbe_prv_data *pdata) 721 { 722 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 723 struct xgbe_phy_data *phy_data = pdata->phy_data; 724 725 if (!phy_data->sfp_mod_absent && !phy_data->sfp_changed) 726 return; 727 728 XGBE_ZERO_SUP(lks); 729 730 if (phy_data->sfp_mod_absent) { 731 pdata->phy.speed = SPEED_UNKNOWN; 732 pdata->phy.duplex = DUPLEX_UNKNOWN; 733 pdata->phy.autoneg = AUTONEG_ENABLE; 734 pdata->phy.pause_autoneg = AUTONEG_ENABLE; 735 736 XGBE_SET_SUP(lks, Autoneg); 737 XGBE_SET_SUP(lks, Pause); 738 XGBE_SET_SUP(lks, Asym_Pause); 739 XGBE_SET_SUP(lks, TP); 740 XGBE_SET_SUP(lks, FIBRE); 741 742 XGBE_LM_COPY(lks, advertising, lks, supported); 743 744 return; 745 } 746 747 switch (phy_data->sfp_base) { 748 case XGBE_SFP_BASE_1000_T: 749 case XGBE_SFP_BASE_1000_SX: 750 case XGBE_SFP_BASE_1000_LX: 751 case XGBE_SFP_BASE_1000_CX: 752 pdata->phy.speed = SPEED_UNKNOWN; 753 pdata->phy.duplex = DUPLEX_UNKNOWN; 754 pdata->phy.autoneg = AUTONEG_ENABLE; 755 pdata->phy.pause_autoneg = AUTONEG_ENABLE; 756 XGBE_SET_SUP(lks, Autoneg); 757 XGBE_SET_SUP(lks, Pause); 758 XGBE_SET_SUP(lks, Asym_Pause); 759 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T) { 760 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) 761 XGBE_SET_SUP(lks, 100baseT_Full); 762 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) 763 XGBE_SET_SUP(lks, 1000baseT_Full); 764 } else { 765 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) 766 XGBE_SET_SUP(lks, 1000baseX_Full); 767 } 768 break; 769 case XGBE_SFP_BASE_10000_SR: 770 case XGBE_SFP_BASE_10000_LR: 771 case XGBE_SFP_BASE_10000_LRM: 772 case XGBE_SFP_BASE_10000_ER: 773 case XGBE_SFP_BASE_10000_CR: 774 pdata->phy.speed = SPEED_10000; 775 pdata->phy.duplex = DUPLEX_FULL; 776 pdata->phy.autoneg = AUTONEG_DISABLE; 777 pdata->phy.pause_autoneg = AUTONEG_DISABLE; 778 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) { 779 switch (phy_data->sfp_base) { 780 case XGBE_SFP_BASE_10000_SR: 781 XGBE_SET_SUP(lks, 10000baseSR_Full); 782 break; 783 case XGBE_SFP_BASE_10000_LR: 784 XGBE_SET_SUP(lks, 10000baseLR_Full); 785 break; 786 case XGBE_SFP_BASE_10000_LRM: 787 XGBE_SET_SUP(lks, 10000baseLRM_Full); 788 break; 789 case XGBE_SFP_BASE_10000_ER: 790 XGBE_SET_SUP(lks, 10000baseER_Full); 791 break; 792 case XGBE_SFP_BASE_10000_CR: 793 XGBE_SET_SUP(lks, 10000baseCR_Full); 794 break; 795 default: 796 break; 797 } 798 } 799 break; 800 default: 801 pdata->phy.speed = SPEED_UNKNOWN; 802 pdata->phy.duplex = DUPLEX_UNKNOWN; 803 pdata->phy.autoneg = AUTONEG_DISABLE; 804 pdata->phy.pause_autoneg = AUTONEG_DISABLE; 805 break; 806 } 807 808 switch (phy_data->sfp_base) { 809 case XGBE_SFP_BASE_1000_T: 810 case XGBE_SFP_BASE_1000_CX: 811 case XGBE_SFP_BASE_10000_CR: 812 XGBE_SET_SUP(lks, TP); 813 break; 814 default: 815 XGBE_SET_SUP(lks, FIBRE); 816 break; 817 } 818 819 XGBE_LM_COPY(lks, advertising, lks, supported); 820 } 821 822 static bool xgbe_phy_sfp_bit_rate(struct xgbe_sfp_eeprom *sfp_eeprom, 823 enum xgbe_sfp_speed sfp_speed) 824 { 825 u8 *sfp_base, min, max; 826 827 sfp_base = sfp_eeprom->base; 828 829 switch (sfp_speed) { 830 case XGBE_SFP_SPEED_1000: 831 min = XGBE_SFP_BASE_BR_1GBE_MIN; 832 max = XGBE_SFP_BASE_BR_1GBE_MAX; 833 break; 834 case XGBE_SFP_SPEED_10000: 835 min = XGBE_SFP_BASE_BR_10GBE_MIN; 836 max = XGBE_SFP_BASE_BR_10GBE_MAX; 837 break; 838 default: 839 return false; 840 } 841 842 return ((sfp_base[XGBE_SFP_BASE_BR] >= min) && 843 (sfp_base[XGBE_SFP_BASE_BR] <= max)); 844 } 845 846 static void xgbe_phy_free_phy_device(struct xgbe_prv_data *pdata) 847 { 848 struct xgbe_phy_data *phy_data = pdata->phy_data; 849 850 if (phy_data->phydev) { 851 phy_detach(phy_data->phydev); 852 phy_device_remove(phy_data->phydev); 853 phy_device_free(phy_data->phydev); 854 phy_data->phydev = NULL; 855 } 856 } 857 858 static bool xgbe_phy_finisar_phy_quirks(struct xgbe_prv_data *pdata) 859 { 860 struct xgbe_phy_data *phy_data = pdata->phy_data; 861 unsigned int phy_id = phy_data->phydev->phy_id; 862 863 if (phy_data->port_mode != XGBE_PORT_MODE_SFP) 864 return false; 865 866 if ((phy_id & 0xfffffff0) != 0x01ff0cc0) 867 return false; 868 869 /* Enable Base-T AN */ 870 phy_write(phy_data->phydev, 0x16, 0x0001); 871 phy_write(phy_data->phydev, 0x00, 0x9140); 872 phy_write(phy_data->phydev, 0x16, 0x0000); 873 874 /* Enable SGMII at 100Base-T/1000Base-T Full Duplex */ 875 phy_write(phy_data->phydev, 0x1b, 0x9084); 876 phy_write(phy_data->phydev, 0x09, 0x0e00); 877 phy_write(phy_data->phydev, 0x00, 0x8140); 878 phy_write(phy_data->phydev, 0x04, 0x0d01); 879 phy_write(phy_data->phydev, 0x00, 0x9140); 880 881 phy_data->phydev->supported = PHY_GBIT_FEATURES; 882 phy_data->phydev->supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 883 phy_data->phydev->advertising = phy_data->phydev->supported; 884 885 netif_dbg(pdata, drv, pdata->netdev, 886 "Finisar PHY quirk in place\n"); 887 888 return true; 889 } 890 891 static bool xgbe_phy_belfuse_phy_quirks(struct xgbe_prv_data *pdata) 892 { 893 struct xgbe_phy_data *phy_data = pdata->phy_data; 894 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom; 895 unsigned int phy_id = phy_data->phydev->phy_id; 896 int reg; 897 898 if (phy_data->port_mode != XGBE_PORT_MODE_SFP) 899 return false; 900 901 if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME], 902 XGBE_BEL_FUSE_VENDOR, XGBE_SFP_BASE_VENDOR_NAME_LEN)) 903 return false; 904 905 /* For Bel-Fuse, use the extra AN flag */ 906 pdata->an_again = 1; 907 908 if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN], 909 XGBE_BEL_FUSE_PARTNO, XGBE_SFP_BASE_VENDOR_PN_LEN)) 910 return false; 911 912 if ((phy_id & 0xfffffff0) != 0x03625d10) 913 return false; 914 915 /* Disable RGMII mode */ 916 phy_write(phy_data->phydev, 0x18, 0x7007); 917 reg = phy_read(phy_data->phydev, 0x18); 918 phy_write(phy_data->phydev, 0x18, reg & ~0x0080); 919 920 /* Enable fiber register bank */ 921 phy_write(phy_data->phydev, 0x1c, 0x7c00); 922 reg = phy_read(phy_data->phydev, 0x1c); 923 reg &= 0x03ff; 924 reg &= ~0x0001; 925 phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg | 0x0001); 926 927 /* Power down SerDes */ 928 reg = phy_read(phy_data->phydev, 0x00); 929 phy_write(phy_data->phydev, 0x00, reg | 0x00800); 930 931 /* Configure SGMII-to-Copper mode */ 932 phy_write(phy_data->phydev, 0x1c, 0x7c00); 933 reg = phy_read(phy_data->phydev, 0x1c); 934 reg &= 0x03ff; 935 reg &= ~0x0006; 936 phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg | 0x0004); 937 938 /* Power up SerDes */ 939 reg = phy_read(phy_data->phydev, 0x00); 940 phy_write(phy_data->phydev, 0x00, reg & ~0x00800); 941 942 /* Enable copper register bank */ 943 phy_write(phy_data->phydev, 0x1c, 0x7c00); 944 reg = phy_read(phy_data->phydev, 0x1c); 945 reg &= 0x03ff; 946 reg &= ~0x0001; 947 phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg); 948 949 /* Power up SerDes */ 950 reg = phy_read(phy_data->phydev, 0x00); 951 phy_write(phy_data->phydev, 0x00, reg & ~0x00800); 952 953 phy_data->phydev->supported = PHY_GBIT_FEATURES; 954 phy_data->phydev->supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 955 phy_data->phydev->advertising = phy_data->phydev->supported; 956 957 netif_dbg(pdata, drv, pdata->netdev, 958 "BelFuse PHY quirk in place\n"); 959 960 return true; 961 } 962 963 static void xgbe_phy_external_phy_quirks(struct xgbe_prv_data *pdata) 964 { 965 if (xgbe_phy_belfuse_phy_quirks(pdata)) 966 return; 967 968 if (xgbe_phy_finisar_phy_quirks(pdata)) 969 return; 970 } 971 972 static int xgbe_phy_find_phy_device(struct xgbe_prv_data *pdata) 973 { 974 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 975 struct xgbe_phy_data *phy_data = pdata->phy_data; 976 struct phy_device *phydev; 977 u32 advertising; 978 int ret; 979 980 /* If we already have a PHY, just return */ 981 if (phy_data->phydev) 982 return 0; 983 984 /* Clear the extra AN flag */ 985 pdata->an_again = 0; 986 987 /* Check for the use of an external PHY */ 988 if (phy_data->phydev_mode == XGBE_MDIO_MODE_NONE) 989 return 0; 990 991 /* For SFP, only use an external PHY if available */ 992 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) && 993 !phy_data->sfp_phy_avail) 994 return 0; 995 996 /* Set the proper MDIO mode for the PHY */ 997 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr, 998 phy_data->phydev_mode); 999 if (ret) { 1000 netdev_err(pdata->netdev, 1001 "mdio port/clause not compatible (%u/%u)\n", 1002 phy_data->mdio_addr, phy_data->phydev_mode); 1003 return ret; 1004 } 1005 1006 /* Create and connect to the PHY device */ 1007 phydev = get_phy_device(phy_data->mii, phy_data->mdio_addr, 1008 (phy_data->phydev_mode == XGBE_MDIO_MODE_CL45)); 1009 if (IS_ERR(phydev)) { 1010 netdev_err(pdata->netdev, "get_phy_device failed\n"); 1011 return -ENODEV; 1012 } 1013 netif_dbg(pdata, drv, pdata->netdev, "external PHY id is %#010x\n", 1014 phydev->phy_id); 1015 1016 /*TODO: If c45, add request_module based on one of the MMD ids? */ 1017 1018 ret = phy_device_register(phydev); 1019 if (ret) { 1020 netdev_err(pdata->netdev, "phy_device_register failed\n"); 1021 phy_device_free(phydev); 1022 return ret; 1023 } 1024 1025 ret = phy_attach_direct(pdata->netdev, phydev, phydev->dev_flags, 1026 PHY_INTERFACE_MODE_SGMII); 1027 if (ret) { 1028 netdev_err(pdata->netdev, "phy_attach_direct failed\n"); 1029 phy_device_remove(phydev); 1030 phy_device_free(phydev); 1031 return ret; 1032 } 1033 phy_data->phydev = phydev; 1034 1035 xgbe_phy_external_phy_quirks(pdata); 1036 1037 ethtool_convert_link_mode_to_legacy_u32(&advertising, 1038 lks->link_modes.advertising); 1039 phydev->advertising &= advertising; 1040 1041 phy_start_aneg(phy_data->phydev); 1042 1043 return 0; 1044 } 1045 1046 static void xgbe_phy_sfp_external_phy(struct xgbe_prv_data *pdata) 1047 { 1048 struct xgbe_phy_data *phy_data = pdata->phy_data; 1049 int ret; 1050 1051 if (!phy_data->sfp_changed) 1052 return; 1053 1054 phy_data->sfp_phy_avail = 0; 1055 1056 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T) 1057 return; 1058 1059 /* Check access to the PHY by reading CTRL1 */ 1060 ret = xgbe_phy_i2c_mii_read(pdata, MII_BMCR); 1061 if (ret < 0) 1062 return; 1063 1064 /* Successfully accessed the PHY */ 1065 phy_data->sfp_phy_avail = 1; 1066 } 1067 1068 static bool xgbe_phy_check_sfp_rx_los(struct xgbe_phy_data *phy_data) 1069 { 1070 u8 *sfp_extd = phy_data->sfp_eeprom.extd; 1071 1072 if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_RX_LOS)) 1073 return false; 1074 1075 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_RX_LOS) 1076 return false; 1077 1078 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_rx_los)) 1079 return true; 1080 1081 return false; 1082 } 1083 1084 static bool xgbe_phy_check_sfp_tx_fault(struct xgbe_phy_data *phy_data) 1085 { 1086 u8 *sfp_extd = phy_data->sfp_eeprom.extd; 1087 1088 if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_TX_FAULT)) 1089 return false; 1090 1091 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_TX_FAULT) 1092 return false; 1093 1094 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_tx_fault)) 1095 return true; 1096 1097 return false; 1098 } 1099 1100 static bool xgbe_phy_check_sfp_mod_absent(struct xgbe_phy_data *phy_data) 1101 { 1102 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_MOD_ABSENT) 1103 return false; 1104 1105 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_mod_absent)) 1106 return true; 1107 1108 return false; 1109 } 1110 1111 static void xgbe_phy_sfp_parse_eeprom(struct xgbe_prv_data *pdata) 1112 { 1113 struct xgbe_phy_data *phy_data = pdata->phy_data; 1114 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom; 1115 u8 *sfp_base; 1116 1117 sfp_base = sfp_eeprom->base; 1118 1119 if (sfp_base[XGBE_SFP_BASE_ID] != XGBE_SFP_ID_SFP) 1120 return; 1121 1122 if (sfp_base[XGBE_SFP_BASE_EXT_ID] != XGBE_SFP_EXT_ID_SFP) 1123 return; 1124 1125 /* Update transceiver signals (eeprom extd/options) */ 1126 phy_data->sfp_tx_fault = xgbe_phy_check_sfp_tx_fault(phy_data); 1127 phy_data->sfp_rx_los = xgbe_phy_check_sfp_rx_los(phy_data); 1128 1129 /* Assume ACTIVE cable unless told it is PASSIVE */ 1130 if (sfp_base[XGBE_SFP_BASE_CABLE] & XGBE_SFP_BASE_CABLE_PASSIVE) { 1131 phy_data->sfp_cable = XGBE_SFP_CABLE_PASSIVE; 1132 phy_data->sfp_cable_len = sfp_base[XGBE_SFP_BASE_CU_CABLE_LEN]; 1133 } else { 1134 phy_data->sfp_cable = XGBE_SFP_CABLE_ACTIVE; 1135 } 1136 1137 /* Determine the type of SFP */ 1138 if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_SR) 1139 phy_data->sfp_base = XGBE_SFP_BASE_10000_SR; 1140 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LR) 1141 phy_data->sfp_base = XGBE_SFP_BASE_10000_LR; 1142 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LRM) 1143 phy_data->sfp_base = XGBE_SFP_BASE_10000_LRM; 1144 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_ER) 1145 phy_data->sfp_base = XGBE_SFP_BASE_10000_ER; 1146 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_SX) 1147 phy_data->sfp_base = XGBE_SFP_BASE_1000_SX; 1148 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_LX) 1149 phy_data->sfp_base = XGBE_SFP_BASE_1000_LX; 1150 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_CX) 1151 phy_data->sfp_base = XGBE_SFP_BASE_1000_CX; 1152 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_T) 1153 phy_data->sfp_base = XGBE_SFP_BASE_1000_T; 1154 else if ((phy_data->sfp_cable == XGBE_SFP_CABLE_PASSIVE) && 1155 xgbe_phy_sfp_bit_rate(sfp_eeprom, XGBE_SFP_SPEED_10000)) 1156 phy_data->sfp_base = XGBE_SFP_BASE_10000_CR; 1157 1158 switch (phy_data->sfp_base) { 1159 case XGBE_SFP_BASE_1000_T: 1160 phy_data->sfp_speed = XGBE_SFP_SPEED_100_1000; 1161 break; 1162 case XGBE_SFP_BASE_1000_SX: 1163 case XGBE_SFP_BASE_1000_LX: 1164 case XGBE_SFP_BASE_1000_CX: 1165 phy_data->sfp_speed = XGBE_SFP_SPEED_1000; 1166 break; 1167 case XGBE_SFP_BASE_10000_SR: 1168 case XGBE_SFP_BASE_10000_LR: 1169 case XGBE_SFP_BASE_10000_LRM: 1170 case XGBE_SFP_BASE_10000_ER: 1171 case XGBE_SFP_BASE_10000_CR: 1172 phy_data->sfp_speed = XGBE_SFP_SPEED_10000; 1173 break; 1174 default: 1175 break; 1176 } 1177 } 1178 1179 static void xgbe_phy_sfp_eeprom_info(struct xgbe_prv_data *pdata, 1180 struct xgbe_sfp_eeprom *sfp_eeprom) 1181 { 1182 struct xgbe_sfp_ascii sfp_ascii; 1183 char *sfp_data = (char *)&sfp_ascii; 1184 1185 netif_dbg(pdata, drv, pdata->netdev, "SFP detected:\n"); 1186 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME], 1187 XGBE_SFP_BASE_VENDOR_NAME_LEN); 1188 sfp_data[XGBE_SFP_BASE_VENDOR_NAME_LEN] = '\0'; 1189 netif_dbg(pdata, drv, pdata->netdev, " vendor: %s\n", 1190 sfp_data); 1191 1192 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN], 1193 XGBE_SFP_BASE_VENDOR_PN_LEN); 1194 sfp_data[XGBE_SFP_BASE_VENDOR_PN_LEN] = '\0'; 1195 netif_dbg(pdata, drv, pdata->netdev, " part number: %s\n", 1196 sfp_data); 1197 1198 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_REV], 1199 XGBE_SFP_BASE_VENDOR_REV_LEN); 1200 sfp_data[XGBE_SFP_BASE_VENDOR_REV_LEN] = '\0'; 1201 netif_dbg(pdata, drv, pdata->netdev, " revision level: %s\n", 1202 sfp_data); 1203 1204 memcpy(sfp_data, &sfp_eeprom->extd[XGBE_SFP_BASE_VENDOR_SN], 1205 XGBE_SFP_BASE_VENDOR_SN_LEN); 1206 sfp_data[XGBE_SFP_BASE_VENDOR_SN_LEN] = '\0'; 1207 netif_dbg(pdata, drv, pdata->netdev, " serial number: %s\n", 1208 sfp_data); 1209 } 1210 1211 static bool xgbe_phy_sfp_verify_eeprom(u8 cc_in, u8 *buf, unsigned int len) 1212 { 1213 u8 cc; 1214 1215 for (cc = 0; len; buf++, len--) 1216 cc += *buf; 1217 1218 return (cc == cc_in) ? true : false; 1219 } 1220 1221 static int xgbe_phy_sfp_read_eeprom(struct xgbe_prv_data *pdata) 1222 { 1223 struct xgbe_phy_data *phy_data = pdata->phy_data; 1224 struct xgbe_sfp_eeprom sfp_eeprom; 1225 u8 eeprom_addr; 1226 int ret; 1227 1228 ret = xgbe_phy_sfp_get_mux(pdata); 1229 if (ret) { 1230 dev_err_once(pdata->dev, "%s: I2C error setting SFP MUX\n", 1231 netdev_name(pdata->netdev)); 1232 return ret; 1233 } 1234 1235 /* Read the SFP serial ID eeprom */ 1236 eeprom_addr = 0; 1237 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS, 1238 &eeprom_addr, sizeof(eeprom_addr), 1239 &sfp_eeprom, sizeof(sfp_eeprom)); 1240 if (ret) { 1241 dev_err_once(pdata->dev, "%s: I2C error reading SFP EEPROM\n", 1242 netdev_name(pdata->netdev)); 1243 goto put; 1244 } 1245 1246 /* Validate the contents read */ 1247 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.base[XGBE_SFP_BASE_CC], 1248 sfp_eeprom.base, 1249 sizeof(sfp_eeprom.base) - 1)) { 1250 ret = -EINVAL; 1251 goto put; 1252 } 1253 1254 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.extd[XGBE_SFP_EXTD_CC], 1255 sfp_eeprom.extd, 1256 sizeof(sfp_eeprom.extd) - 1)) { 1257 ret = -EINVAL; 1258 goto put; 1259 } 1260 1261 /* Check for an added or changed SFP */ 1262 if (memcmp(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom))) { 1263 phy_data->sfp_changed = 1; 1264 1265 if (netif_msg_drv(pdata)) 1266 xgbe_phy_sfp_eeprom_info(pdata, &sfp_eeprom); 1267 1268 memcpy(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom)); 1269 1270 xgbe_phy_free_phy_device(pdata); 1271 } else { 1272 phy_data->sfp_changed = 0; 1273 } 1274 1275 put: 1276 xgbe_phy_sfp_put_mux(pdata); 1277 1278 return ret; 1279 } 1280 1281 static void xgbe_phy_sfp_signals(struct xgbe_prv_data *pdata) 1282 { 1283 struct xgbe_phy_data *phy_data = pdata->phy_data; 1284 u8 gpio_reg, gpio_ports[2]; 1285 int ret; 1286 1287 /* Read the input port registers */ 1288 gpio_reg = 0; 1289 ret = xgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address, 1290 &gpio_reg, sizeof(gpio_reg), 1291 gpio_ports, sizeof(gpio_ports)); 1292 if (ret) { 1293 dev_err_once(pdata->dev, "%s: I2C error reading SFP GPIOs\n", 1294 netdev_name(pdata->netdev)); 1295 return; 1296 } 1297 1298 phy_data->sfp_gpio_inputs = (gpio_ports[1] << 8) | gpio_ports[0]; 1299 1300 phy_data->sfp_mod_absent = xgbe_phy_check_sfp_mod_absent(phy_data); 1301 } 1302 1303 static void xgbe_phy_sfp_mod_absent(struct xgbe_prv_data *pdata) 1304 { 1305 struct xgbe_phy_data *phy_data = pdata->phy_data; 1306 1307 xgbe_phy_free_phy_device(pdata); 1308 1309 phy_data->sfp_mod_absent = 1; 1310 phy_data->sfp_phy_avail = 0; 1311 memset(&phy_data->sfp_eeprom, 0, sizeof(phy_data->sfp_eeprom)); 1312 } 1313 1314 static void xgbe_phy_sfp_reset(struct xgbe_phy_data *phy_data) 1315 { 1316 phy_data->sfp_rx_los = 0; 1317 phy_data->sfp_tx_fault = 0; 1318 phy_data->sfp_mod_absent = 1; 1319 phy_data->sfp_base = XGBE_SFP_BASE_UNKNOWN; 1320 phy_data->sfp_cable = XGBE_SFP_CABLE_UNKNOWN; 1321 phy_data->sfp_speed = XGBE_SFP_SPEED_UNKNOWN; 1322 } 1323 1324 static void xgbe_phy_sfp_detect(struct xgbe_prv_data *pdata) 1325 { 1326 struct xgbe_phy_data *phy_data = pdata->phy_data; 1327 int ret; 1328 1329 /* Reset the SFP signals and info */ 1330 xgbe_phy_sfp_reset(phy_data); 1331 1332 ret = xgbe_phy_get_comm_ownership(pdata); 1333 if (ret) 1334 return; 1335 1336 /* Read the SFP signals and check for module presence */ 1337 xgbe_phy_sfp_signals(pdata); 1338 if (phy_data->sfp_mod_absent) { 1339 xgbe_phy_sfp_mod_absent(pdata); 1340 goto put; 1341 } 1342 1343 ret = xgbe_phy_sfp_read_eeprom(pdata); 1344 if (ret) { 1345 /* Treat any error as if there isn't an SFP plugged in */ 1346 xgbe_phy_sfp_reset(phy_data); 1347 xgbe_phy_sfp_mod_absent(pdata); 1348 goto put; 1349 } 1350 1351 xgbe_phy_sfp_parse_eeprom(pdata); 1352 1353 xgbe_phy_sfp_external_phy(pdata); 1354 1355 put: 1356 xgbe_phy_sfp_phy_settings(pdata); 1357 1358 xgbe_phy_put_comm_ownership(pdata); 1359 } 1360 1361 static int xgbe_phy_module_eeprom(struct xgbe_prv_data *pdata, 1362 struct ethtool_eeprom *eeprom, u8 *data) 1363 { 1364 struct xgbe_phy_data *phy_data = pdata->phy_data; 1365 u8 eeprom_addr, eeprom_data[XGBE_SFP_EEPROM_MAX]; 1366 struct xgbe_sfp_eeprom *sfp_eeprom; 1367 unsigned int i, j, rem; 1368 int ret; 1369 1370 rem = eeprom->len; 1371 1372 if (!eeprom->len) { 1373 ret = -EINVAL; 1374 goto done; 1375 } 1376 1377 if ((eeprom->offset + eeprom->len) > XGBE_SFP_EEPROM_MAX) { 1378 ret = -EINVAL; 1379 goto done; 1380 } 1381 1382 if (phy_data->port_mode != XGBE_PORT_MODE_SFP) { 1383 ret = -ENXIO; 1384 goto done; 1385 } 1386 1387 if (!netif_running(pdata->netdev)) { 1388 ret = -EIO; 1389 goto done; 1390 } 1391 1392 if (phy_data->sfp_mod_absent) { 1393 ret = -EIO; 1394 goto done; 1395 } 1396 1397 ret = xgbe_phy_get_comm_ownership(pdata); 1398 if (ret) { 1399 ret = -EIO; 1400 goto done; 1401 } 1402 1403 ret = xgbe_phy_sfp_get_mux(pdata); 1404 if (ret) { 1405 netdev_err(pdata->netdev, "I2C error setting SFP MUX\n"); 1406 ret = -EIO; 1407 goto put_own; 1408 } 1409 1410 /* Read the SFP serial ID eeprom */ 1411 eeprom_addr = 0; 1412 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS, 1413 &eeprom_addr, sizeof(eeprom_addr), 1414 eeprom_data, XGBE_SFP_EEPROM_BASE_LEN); 1415 if (ret) { 1416 netdev_err(pdata->netdev, 1417 "I2C error reading SFP EEPROM\n"); 1418 ret = -EIO; 1419 goto put_mux; 1420 } 1421 1422 sfp_eeprom = (struct xgbe_sfp_eeprom *)eeprom_data; 1423 1424 if (XGBE_SFP_DIAGS_SUPPORTED(sfp_eeprom)) { 1425 /* Read the SFP diagnostic eeprom */ 1426 eeprom_addr = 0; 1427 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_DIAG_INFO_ADDRESS, 1428 &eeprom_addr, sizeof(eeprom_addr), 1429 eeprom_data + XGBE_SFP_EEPROM_BASE_LEN, 1430 XGBE_SFP_EEPROM_DIAG_LEN); 1431 if (ret) { 1432 netdev_err(pdata->netdev, 1433 "I2C error reading SFP DIAGS\n"); 1434 ret = -EIO; 1435 goto put_mux; 1436 } 1437 } 1438 1439 for (i = 0, j = eeprom->offset; i < eeprom->len; i++, j++) { 1440 if ((j >= XGBE_SFP_EEPROM_BASE_LEN) && 1441 !XGBE_SFP_DIAGS_SUPPORTED(sfp_eeprom)) 1442 break; 1443 1444 data[i] = eeprom_data[j]; 1445 rem--; 1446 } 1447 1448 put_mux: 1449 xgbe_phy_sfp_put_mux(pdata); 1450 1451 put_own: 1452 xgbe_phy_put_comm_ownership(pdata); 1453 1454 done: 1455 eeprom->len -= rem; 1456 1457 return ret; 1458 } 1459 1460 static int xgbe_phy_module_info(struct xgbe_prv_data *pdata, 1461 struct ethtool_modinfo *modinfo) 1462 { 1463 struct xgbe_phy_data *phy_data = pdata->phy_data; 1464 1465 if (phy_data->port_mode != XGBE_PORT_MODE_SFP) 1466 return -ENXIO; 1467 1468 if (!netif_running(pdata->netdev)) 1469 return -EIO; 1470 1471 if (phy_data->sfp_mod_absent) 1472 return -EIO; 1473 1474 if (XGBE_SFP_DIAGS_SUPPORTED(&phy_data->sfp_eeprom)) { 1475 modinfo->type = ETH_MODULE_SFF_8472; 1476 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 1477 } else { 1478 modinfo->type = ETH_MODULE_SFF_8079; 1479 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN; 1480 } 1481 1482 return 0; 1483 } 1484 1485 static void xgbe_phy_phydev_flowctrl(struct xgbe_prv_data *pdata) 1486 { 1487 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1488 struct xgbe_phy_data *phy_data = pdata->phy_data; 1489 u16 lcl_adv = 0, rmt_adv = 0; 1490 u8 fc; 1491 1492 pdata->phy.tx_pause = 0; 1493 pdata->phy.rx_pause = 0; 1494 1495 if (!phy_data->phydev) 1496 return; 1497 1498 if (phy_data->phydev->advertising & ADVERTISED_Pause) 1499 lcl_adv |= ADVERTISE_PAUSE_CAP; 1500 if (phy_data->phydev->advertising & ADVERTISED_Asym_Pause) 1501 lcl_adv |= ADVERTISE_PAUSE_ASYM; 1502 1503 if (phy_data->phydev->pause) { 1504 XGBE_SET_LP_ADV(lks, Pause); 1505 rmt_adv |= LPA_PAUSE_CAP; 1506 } 1507 if (phy_data->phydev->asym_pause) { 1508 XGBE_SET_LP_ADV(lks, Asym_Pause); 1509 rmt_adv |= LPA_PAUSE_ASYM; 1510 } 1511 1512 fc = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); 1513 if (fc & FLOW_CTRL_TX) 1514 pdata->phy.tx_pause = 1; 1515 if (fc & FLOW_CTRL_RX) 1516 pdata->phy.rx_pause = 1; 1517 } 1518 1519 static enum xgbe_mode xgbe_phy_an37_sgmii_outcome(struct xgbe_prv_data *pdata) 1520 { 1521 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1522 enum xgbe_mode mode; 1523 1524 XGBE_SET_LP_ADV(lks, Autoneg); 1525 XGBE_SET_LP_ADV(lks, TP); 1526 1527 /* Use external PHY to determine flow control */ 1528 if (pdata->phy.pause_autoneg) 1529 xgbe_phy_phydev_flowctrl(pdata); 1530 1531 switch (pdata->an_status & XGBE_SGMII_AN_LINK_SPEED) { 1532 case XGBE_SGMII_AN_LINK_SPEED_100: 1533 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) { 1534 XGBE_SET_LP_ADV(lks, 100baseT_Full); 1535 mode = XGBE_MODE_SGMII_100; 1536 } else { 1537 /* Half-duplex not supported */ 1538 XGBE_SET_LP_ADV(lks, 100baseT_Half); 1539 mode = XGBE_MODE_UNKNOWN; 1540 } 1541 break; 1542 case XGBE_SGMII_AN_LINK_SPEED_1000: 1543 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) { 1544 XGBE_SET_LP_ADV(lks, 1000baseT_Full); 1545 mode = XGBE_MODE_SGMII_1000; 1546 } else { 1547 /* Half-duplex not supported */ 1548 XGBE_SET_LP_ADV(lks, 1000baseT_Half); 1549 mode = XGBE_MODE_UNKNOWN; 1550 } 1551 break; 1552 default: 1553 mode = XGBE_MODE_UNKNOWN; 1554 } 1555 1556 return mode; 1557 } 1558 1559 static enum xgbe_mode xgbe_phy_an37_outcome(struct xgbe_prv_data *pdata) 1560 { 1561 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1562 enum xgbe_mode mode; 1563 unsigned int ad_reg, lp_reg; 1564 1565 XGBE_SET_LP_ADV(lks, Autoneg); 1566 XGBE_SET_LP_ADV(lks, FIBRE); 1567 1568 /* Compare Advertisement and Link Partner register */ 1569 ad_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE); 1570 lp_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_LP_ABILITY); 1571 if (lp_reg & 0x100) 1572 XGBE_SET_LP_ADV(lks, Pause); 1573 if (lp_reg & 0x80) 1574 XGBE_SET_LP_ADV(lks, Asym_Pause); 1575 1576 if (pdata->phy.pause_autoneg) { 1577 /* Set flow control based on auto-negotiation result */ 1578 pdata->phy.tx_pause = 0; 1579 pdata->phy.rx_pause = 0; 1580 1581 if (ad_reg & lp_reg & 0x100) { 1582 pdata->phy.tx_pause = 1; 1583 pdata->phy.rx_pause = 1; 1584 } else if (ad_reg & lp_reg & 0x80) { 1585 if (ad_reg & 0x100) 1586 pdata->phy.rx_pause = 1; 1587 else if (lp_reg & 0x100) 1588 pdata->phy.tx_pause = 1; 1589 } 1590 } 1591 1592 if (lp_reg & 0x20) 1593 XGBE_SET_LP_ADV(lks, 1000baseX_Full); 1594 1595 /* Half duplex is not supported */ 1596 ad_reg &= lp_reg; 1597 mode = (ad_reg & 0x20) ? XGBE_MODE_X : XGBE_MODE_UNKNOWN; 1598 1599 return mode; 1600 } 1601 1602 static enum xgbe_mode xgbe_phy_an73_redrv_outcome(struct xgbe_prv_data *pdata) 1603 { 1604 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1605 struct xgbe_phy_data *phy_data = pdata->phy_data; 1606 enum xgbe_mode mode; 1607 unsigned int ad_reg, lp_reg; 1608 1609 XGBE_SET_LP_ADV(lks, Autoneg); 1610 XGBE_SET_LP_ADV(lks, Backplane); 1611 1612 /* Use external PHY to determine flow control */ 1613 if (pdata->phy.pause_autoneg) 1614 xgbe_phy_phydev_flowctrl(pdata); 1615 1616 /* Compare Advertisement and Link Partner register 2 */ 1617 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); 1618 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); 1619 if (lp_reg & 0x80) 1620 XGBE_SET_LP_ADV(lks, 10000baseKR_Full); 1621 if (lp_reg & 0x20) 1622 XGBE_SET_LP_ADV(lks, 1000baseKX_Full); 1623 1624 ad_reg &= lp_reg; 1625 if (ad_reg & 0x80) { 1626 switch (phy_data->port_mode) { 1627 case XGBE_PORT_MODE_BACKPLANE: 1628 mode = XGBE_MODE_KR; 1629 break; 1630 default: 1631 mode = XGBE_MODE_SFI; 1632 break; 1633 } 1634 } else if (ad_reg & 0x20) { 1635 switch (phy_data->port_mode) { 1636 case XGBE_PORT_MODE_BACKPLANE: 1637 mode = XGBE_MODE_KX_1000; 1638 break; 1639 case XGBE_PORT_MODE_1000BASE_X: 1640 mode = XGBE_MODE_X; 1641 break; 1642 case XGBE_PORT_MODE_SFP: 1643 switch (phy_data->sfp_base) { 1644 case XGBE_SFP_BASE_1000_T: 1645 if (phy_data->phydev && 1646 (phy_data->phydev->speed == SPEED_100)) 1647 mode = XGBE_MODE_SGMII_100; 1648 else 1649 mode = XGBE_MODE_SGMII_1000; 1650 break; 1651 case XGBE_SFP_BASE_1000_SX: 1652 case XGBE_SFP_BASE_1000_LX: 1653 case XGBE_SFP_BASE_1000_CX: 1654 default: 1655 mode = XGBE_MODE_X; 1656 break; 1657 } 1658 break; 1659 default: 1660 if (phy_data->phydev && 1661 (phy_data->phydev->speed == SPEED_100)) 1662 mode = XGBE_MODE_SGMII_100; 1663 else 1664 mode = XGBE_MODE_SGMII_1000; 1665 break; 1666 } 1667 } else { 1668 mode = XGBE_MODE_UNKNOWN; 1669 } 1670 1671 /* Compare Advertisement and Link Partner register 3 */ 1672 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); 1673 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); 1674 if (lp_reg & 0xc000) 1675 XGBE_SET_LP_ADV(lks, 10000baseR_FEC); 1676 1677 return mode; 1678 } 1679 1680 static enum xgbe_mode xgbe_phy_an73_outcome(struct xgbe_prv_data *pdata) 1681 { 1682 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1683 enum xgbe_mode mode; 1684 unsigned int ad_reg, lp_reg; 1685 1686 XGBE_SET_LP_ADV(lks, Autoneg); 1687 XGBE_SET_LP_ADV(lks, Backplane); 1688 1689 /* Compare Advertisement and Link Partner register 1 */ 1690 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE); 1691 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA); 1692 if (lp_reg & 0x400) 1693 XGBE_SET_LP_ADV(lks, Pause); 1694 if (lp_reg & 0x800) 1695 XGBE_SET_LP_ADV(lks, Asym_Pause); 1696 1697 if (pdata->phy.pause_autoneg) { 1698 /* Set flow control based on auto-negotiation result */ 1699 pdata->phy.tx_pause = 0; 1700 pdata->phy.rx_pause = 0; 1701 1702 if (ad_reg & lp_reg & 0x400) { 1703 pdata->phy.tx_pause = 1; 1704 pdata->phy.rx_pause = 1; 1705 } else if (ad_reg & lp_reg & 0x800) { 1706 if (ad_reg & 0x400) 1707 pdata->phy.rx_pause = 1; 1708 else if (lp_reg & 0x400) 1709 pdata->phy.tx_pause = 1; 1710 } 1711 } 1712 1713 /* Compare Advertisement and Link Partner register 2 */ 1714 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); 1715 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); 1716 if (lp_reg & 0x80) 1717 XGBE_SET_LP_ADV(lks, 10000baseKR_Full); 1718 if (lp_reg & 0x20) 1719 XGBE_SET_LP_ADV(lks, 1000baseKX_Full); 1720 1721 ad_reg &= lp_reg; 1722 if (ad_reg & 0x80) 1723 mode = XGBE_MODE_KR; 1724 else if (ad_reg & 0x20) 1725 mode = XGBE_MODE_KX_1000; 1726 else 1727 mode = XGBE_MODE_UNKNOWN; 1728 1729 /* Compare Advertisement and Link Partner register 3 */ 1730 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); 1731 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); 1732 if (lp_reg & 0xc000) 1733 XGBE_SET_LP_ADV(lks, 10000baseR_FEC); 1734 1735 return mode; 1736 } 1737 1738 static enum xgbe_mode xgbe_phy_an_outcome(struct xgbe_prv_data *pdata) 1739 { 1740 switch (pdata->an_mode) { 1741 case XGBE_AN_MODE_CL73: 1742 return xgbe_phy_an73_outcome(pdata); 1743 case XGBE_AN_MODE_CL73_REDRV: 1744 return xgbe_phy_an73_redrv_outcome(pdata); 1745 case XGBE_AN_MODE_CL37: 1746 return xgbe_phy_an37_outcome(pdata); 1747 case XGBE_AN_MODE_CL37_SGMII: 1748 return xgbe_phy_an37_sgmii_outcome(pdata); 1749 default: 1750 return XGBE_MODE_UNKNOWN; 1751 } 1752 } 1753 1754 static void xgbe_phy_an_advertising(struct xgbe_prv_data *pdata, 1755 struct ethtool_link_ksettings *dlks) 1756 { 1757 struct ethtool_link_ksettings *slks = &pdata->phy.lks; 1758 struct xgbe_phy_data *phy_data = pdata->phy_data; 1759 1760 XGBE_LM_COPY(dlks, advertising, slks, advertising); 1761 1762 /* Without a re-driver, just return current advertising */ 1763 if (!phy_data->redrv) 1764 return; 1765 1766 /* With the KR re-driver we need to advertise a single speed */ 1767 XGBE_CLR_ADV(dlks, 1000baseKX_Full); 1768 XGBE_CLR_ADV(dlks, 10000baseKR_Full); 1769 1770 /* Advertise FEC support is present */ 1771 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 1772 XGBE_SET_ADV(dlks, 10000baseR_FEC); 1773 1774 switch (phy_data->port_mode) { 1775 case XGBE_PORT_MODE_BACKPLANE: 1776 XGBE_SET_ADV(dlks, 10000baseKR_Full); 1777 break; 1778 case XGBE_PORT_MODE_BACKPLANE_2500: 1779 XGBE_SET_ADV(dlks, 1000baseKX_Full); 1780 break; 1781 case XGBE_PORT_MODE_1000BASE_T: 1782 case XGBE_PORT_MODE_1000BASE_X: 1783 case XGBE_PORT_MODE_NBASE_T: 1784 XGBE_SET_ADV(dlks, 1000baseKX_Full); 1785 break; 1786 case XGBE_PORT_MODE_10GBASE_T: 1787 if (phy_data->phydev && 1788 (phy_data->phydev->speed == SPEED_10000)) 1789 XGBE_SET_ADV(dlks, 10000baseKR_Full); 1790 else 1791 XGBE_SET_ADV(dlks, 1000baseKX_Full); 1792 break; 1793 case XGBE_PORT_MODE_10GBASE_R: 1794 XGBE_SET_ADV(dlks, 10000baseKR_Full); 1795 break; 1796 case XGBE_PORT_MODE_SFP: 1797 switch (phy_data->sfp_base) { 1798 case XGBE_SFP_BASE_1000_T: 1799 case XGBE_SFP_BASE_1000_SX: 1800 case XGBE_SFP_BASE_1000_LX: 1801 case XGBE_SFP_BASE_1000_CX: 1802 XGBE_SET_ADV(dlks, 1000baseKX_Full); 1803 break; 1804 default: 1805 XGBE_SET_ADV(dlks, 10000baseKR_Full); 1806 break; 1807 } 1808 break; 1809 default: 1810 XGBE_SET_ADV(dlks, 10000baseKR_Full); 1811 break; 1812 } 1813 } 1814 1815 static int xgbe_phy_an_config(struct xgbe_prv_data *pdata) 1816 { 1817 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1818 struct xgbe_phy_data *phy_data = pdata->phy_data; 1819 u32 advertising; 1820 int ret; 1821 1822 ret = xgbe_phy_find_phy_device(pdata); 1823 if (ret) 1824 return ret; 1825 1826 if (!phy_data->phydev) 1827 return 0; 1828 1829 ethtool_convert_link_mode_to_legacy_u32(&advertising, 1830 lks->link_modes.advertising); 1831 1832 phy_data->phydev->autoneg = pdata->phy.autoneg; 1833 phy_data->phydev->advertising = phy_data->phydev->supported & 1834 advertising; 1835 1836 if (pdata->phy.autoneg != AUTONEG_ENABLE) { 1837 phy_data->phydev->speed = pdata->phy.speed; 1838 phy_data->phydev->duplex = pdata->phy.duplex; 1839 } 1840 1841 ret = phy_start_aneg(phy_data->phydev); 1842 1843 return ret; 1844 } 1845 1846 static enum xgbe_an_mode xgbe_phy_an_sfp_mode(struct xgbe_phy_data *phy_data) 1847 { 1848 switch (phy_data->sfp_base) { 1849 case XGBE_SFP_BASE_1000_T: 1850 return XGBE_AN_MODE_CL37_SGMII; 1851 case XGBE_SFP_BASE_1000_SX: 1852 case XGBE_SFP_BASE_1000_LX: 1853 case XGBE_SFP_BASE_1000_CX: 1854 return XGBE_AN_MODE_CL37; 1855 default: 1856 return XGBE_AN_MODE_NONE; 1857 } 1858 } 1859 1860 static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata) 1861 { 1862 struct xgbe_phy_data *phy_data = pdata->phy_data; 1863 1864 /* A KR re-driver will always require CL73 AN */ 1865 if (phy_data->redrv) 1866 return XGBE_AN_MODE_CL73_REDRV; 1867 1868 switch (phy_data->port_mode) { 1869 case XGBE_PORT_MODE_BACKPLANE: 1870 return XGBE_AN_MODE_CL73; 1871 case XGBE_PORT_MODE_BACKPLANE_2500: 1872 return XGBE_AN_MODE_NONE; 1873 case XGBE_PORT_MODE_1000BASE_T: 1874 return XGBE_AN_MODE_CL37_SGMII; 1875 case XGBE_PORT_MODE_1000BASE_X: 1876 return XGBE_AN_MODE_CL37; 1877 case XGBE_PORT_MODE_NBASE_T: 1878 return XGBE_AN_MODE_CL37_SGMII; 1879 case XGBE_PORT_MODE_10GBASE_T: 1880 return XGBE_AN_MODE_CL73; 1881 case XGBE_PORT_MODE_10GBASE_R: 1882 return XGBE_AN_MODE_NONE; 1883 case XGBE_PORT_MODE_SFP: 1884 return xgbe_phy_an_sfp_mode(phy_data); 1885 default: 1886 return XGBE_AN_MODE_NONE; 1887 } 1888 } 1889 1890 static int xgbe_phy_set_redrv_mode_mdio(struct xgbe_prv_data *pdata, 1891 enum xgbe_phy_redrv_mode mode) 1892 { 1893 struct xgbe_phy_data *phy_data = pdata->phy_data; 1894 u16 redrv_reg, redrv_val; 1895 1896 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000); 1897 redrv_val = (u16)mode; 1898 1899 return pdata->hw_if.write_ext_mii_regs(pdata, phy_data->redrv_addr, 1900 redrv_reg, redrv_val); 1901 } 1902 1903 static int xgbe_phy_set_redrv_mode_i2c(struct xgbe_prv_data *pdata, 1904 enum xgbe_phy_redrv_mode mode) 1905 { 1906 struct xgbe_phy_data *phy_data = pdata->phy_data; 1907 unsigned int redrv_reg; 1908 int ret; 1909 1910 /* Calculate the register to write */ 1911 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000); 1912 1913 ret = xgbe_phy_redrv_write(pdata, redrv_reg, mode); 1914 1915 return ret; 1916 } 1917 1918 static void xgbe_phy_set_redrv_mode(struct xgbe_prv_data *pdata) 1919 { 1920 struct xgbe_phy_data *phy_data = pdata->phy_data; 1921 enum xgbe_phy_redrv_mode mode; 1922 int ret; 1923 1924 if (!phy_data->redrv) 1925 return; 1926 1927 mode = XGBE_PHY_REDRV_MODE_CX; 1928 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) && 1929 (phy_data->sfp_base != XGBE_SFP_BASE_1000_CX) && 1930 (phy_data->sfp_base != XGBE_SFP_BASE_10000_CR)) 1931 mode = XGBE_PHY_REDRV_MODE_SR; 1932 1933 ret = xgbe_phy_get_comm_ownership(pdata); 1934 if (ret) 1935 return; 1936 1937 if (phy_data->redrv_if) 1938 xgbe_phy_set_redrv_mode_i2c(pdata, mode); 1939 else 1940 xgbe_phy_set_redrv_mode_mdio(pdata, mode); 1941 1942 xgbe_phy_put_comm_ownership(pdata); 1943 } 1944 1945 static void xgbe_phy_perform_ratechange(struct xgbe_prv_data *pdata, 1946 unsigned int cmd, unsigned int sub_cmd) 1947 { 1948 unsigned int s0 = 0; 1949 unsigned int wait; 1950 1951 /* Log if a previous command did not complete */ 1952 if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) 1953 netif_dbg(pdata, link, pdata->netdev, 1954 "firmware mailbox not ready for command\n"); 1955 1956 /* Construct the command */ 1957 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, cmd); 1958 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, sub_cmd); 1959 1960 /* Issue the command */ 1961 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0); 1962 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0); 1963 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1); 1964 1965 /* Wait for command to complete */ 1966 wait = XGBE_RATECHANGE_COUNT; 1967 while (wait--) { 1968 if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) 1969 return; 1970 1971 usleep_range(1000, 2000); 1972 } 1973 1974 netif_dbg(pdata, link, pdata->netdev, 1975 "firmware mailbox command did not complete\n"); 1976 } 1977 1978 static void xgbe_phy_rrc(struct xgbe_prv_data *pdata) 1979 { 1980 /* Receiver Reset Cycle */ 1981 xgbe_phy_perform_ratechange(pdata, 5, 0); 1982 1983 netif_dbg(pdata, link, pdata->netdev, "receiver reset complete\n"); 1984 } 1985 1986 static void xgbe_phy_power_off(struct xgbe_prv_data *pdata) 1987 { 1988 struct xgbe_phy_data *phy_data = pdata->phy_data; 1989 1990 /* Power off */ 1991 xgbe_phy_perform_ratechange(pdata, 0, 0); 1992 1993 phy_data->cur_mode = XGBE_MODE_UNKNOWN; 1994 1995 netif_dbg(pdata, link, pdata->netdev, "phy powered off\n"); 1996 } 1997 1998 static void xgbe_phy_sfi_mode(struct xgbe_prv_data *pdata) 1999 { 2000 struct xgbe_phy_data *phy_data = pdata->phy_data; 2001 2002 xgbe_phy_set_redrv_mode(pdata); 2003 2004 /* 10G/SFI */ 2005 if (phy_data->sfp_cable != XGBE_SFP_CABLE_PASSIVE) { 2006 xgbe_phy_perform_ratechange(pdata, 3, 0); 2007 } else { 2008 if (phy_data->sfp_cable_len <= 1) 2009 xgbe_phy_perform_ratechange(pdata, 3, 1); 2010 else if (phy_data->sfp_cable_len <= 3) 2011 xgbe_phy_perform_ratechange(pdata, 3, 2); 2012 else 2013 xgbe_phy_perform_ratechange(pdata, 3, 3); 2014 } 2015 2016 phy_data->cur_mode = XGBE_MODE_SFI; 2017 2018 netif_dbg(pdata, link, pdata->netdev, "10GbE SFI mode set\n"); 2019 } 2020 2021 static void xgbe_phy_x_mode(struct xgbe_prv_data *pdata) 2022 { 2023 struct xgbe_phy_data *phy_data = pdata->phy_data; 2024 2025 xgbe_phy_set_redrv_mode(pdata); 2026 2027 /* 1G/X */ 2028 xgbe_phy_perform_ratechange(pdata, 1, 3); 2029 2030 phy_data->cur_mode = XGBE_MODE_X; 2031 2032 netif_dbg(pdata, link, pdata->netdev, "1GbE X mode set\n"); 2033 } 2034 2035 static void xgbe_phy_sgmii_1000_mode(struct xgbe_prv_data *pdata) 2036 { 2037 struct xgbe_phy_data *phy_data = pdata->phy_data; 2038 2039 xgbe_phy_set_redrv_mode(pdata); 2040 2041 /* 1G/SGMII */ 2042 xgbe_phy_perform_ratechange(pdata, 1, 2); 2043 2044 phy_data->cur_mode = XGBE_MODE_SGMII_1000; 2045 2046 netif_dbg(pdata, link, pdata->netdev, "1GbE SGMII mode set\n"); 2047 } 2048 2049 static void xgbe_phy_sgmii_100_mode(struct xgbe_prv_data *pdata) 2050 { 2051 struct xgbe_phy_data *phy_data = pdata->phy_data; 2052 2053 xgbe_phy_set_redrv_mode(pdata); 2054 2055 /* 100M/SGMII */ 2056 xgbe_phy_perform_ratechange(pdata, 1, 1); 2057 2058 phy_data->cur_mode = XGBE_MODE_SGMII_100; 2059 2060 netif_dbg(pdata, link, pdata->netdev, "100MbE SGMII mode set\n"); 2061 } 2062 2063 static void xgbe_phy_kr_mode(struct xgbe_prv_data *pdata) 2064 { 2065 struct xgbe_phy_data *phy_data = pdata->phy_data; 2066 2067 xgbe_phy_set_redrv_mode(pdata); 2068 2069 /* 10G/KR */ 2070 xgbe_phy_perform_ratechange(pdata, 4, 0); 2071 2072 phy_data->cur_mode = XGBE_MODE_KR; 2073 2074 netif_dbg(pdata, link, pdata->netdev, "10GbE KR mode set\n"); 2075 } 2076 2077 static void xgbe_phy_kx_2500_mode(struct xgbe_prv_data *pdata) 2078 { 2079 struct xgbe_phy_data *phy_data = pdata->phy_data; 2080 2081 xgbe_phy_set_redrv_mode(pdata); 2082 2083 /* 2.5G/KX */ 2084 xgbe_phy_perform_ratechange(pdata, 2, 0); 2085 2086 phy_data->cur_mode = XGBE_MODE_KX_2500; 2087 2088 netif_dbg(pdata, link, pdata->netdev, "2.5GbE KX mode set\n"); 2089 } 2090 2091 static void xgbe_phy_kx_1000_mode(struct xgbe_prv_data *pdata) 2092 { 2093 struct xgbe_phy_data *phy_data = pdata->phy_data; 2094 2095 xgbe_phy_set_redrv_mode(pdata); 2096 2097 /* 1G/KX */ 2098 xgbe_phy_perform_ratechange(pdata, 1, 3); 2099 2100 phy_data->cur_mode = XGBE_MODE_KX_1000; 2101 2102 netif_dbg(pdata, link, pdata->netdev, "1GbE KX mode set\n"); 2103 } 2104 2105 static enum xgbe_mode xgbe_phy_cur_mode(struct xgbe_prv_data *pdata) 2106 { 2107 struct xgbe_phy_data *phy_data = pdata->phy_data; 2108 2109 return phy_data->cur_mode; 2110 } 2111 2112 static enum xgbe_mode xgbe_phy_switch_baset_mode(struct xgbe_prv_data *pdata) 2113 { 2114 struct xgbe_phy_data *phy_data = pdata->phy_data; 2115 2116 /* No switching if not 10GBase-T */ 2117 if (phy_data->port_mode != XGBE_PORT_MODE_10GBASE_T) 2118 return xgbe_phy_cur_mode(pdata); 2119 2120 switch (xgbe_phy_cur_mode(pdata)) { 2121 case XGBE_MODE_SGMII_100: 2122 case XGBE_MODE_SGMII_1000: 2123 return XGBE_MODE_KR; 2124 case XGBE_MODE_KR: 2125 default: 2126 return XGBE_MODE_SGMII_1000; 2127 } 2128 } 2129 2130 static enum xgbe_mode xgbe_phy_switch_bp_2500_mode(struct xgbe_prv_data *pdata) 2131 { 2132 return XGBE_MODE_KX_2500; 2133 } 2134 2135 static enum xgbe_mode xgbe_phy_switch_bp_mode(struct xgbe_prv_data *pdata) 2136 { 2137 /* If we are in KR switch to KX, and vice-versa */ 2138 switch (xgbe_phy_cur_mode(pdata)) { 2139 case XGBE_MODE_KX_1000: 2140 return XGBE_MODE_KR; 2141 case XGBE_MODE_KR: 2142 default: 2143 return XGBE_MODE_KX_1000; 2144 } 2145 } 2146 2147 static enum xgbe_mode xgbe_phy_switch_mode(struct xgbe_prv_data *pdata) 2148 { 2149 struct xgbe_phy_data *phy_data = pdata->phy_data; 2150 2151 switch (phy_data->port_mode) { 2152 case XGBE_PORT_MODE_BACKPLANE: 2153 return xgbe_phy_switch_bp_mode(pdata); 2154 case XGBE_PORT_MODE_BACKPLANE_2500: 2155 return xgbe_phy_switch_bp_2500_mode(pdata); 2156 case XGBE_PORT_MODE_1000BASE_T: 2157 case XGBE_PORT_MODE_NBASE_T: 2158 case XGBE_PORT_MODE_10GBASE_T: 2159 return xgbe_phy_switch_baset_mode(pdata); 2160 case XGBE_PORT_MODE_1000BASE_X: 2161 case XGBE_PORT_MODE_10GBASE_R: 2162 case XGBE_PORT_MODE_SFP: 2163 /* No switching, so just return current mode */ 2164 return xgbe_phy_cur_mode(pdata); 2165 default: 2166 return XGBE_MODE_UNKNOWN; 2167 } 2168 } 2169 2170 static enum xgbe_mode xgbe_phy_get_basex_mode(struct xgbe_phy_data *phy_data, 2171 int speed) 2172 { 2173 switch (speed) { 2174 case SPEED_1000: 2175 return XGBE_MODE_X; 2176 case SPEED_10000: 2177 return XGBE_MODE_KR; 2178 default: 2179 return XGBE_MODE_UNKNOWN; 2180 } 2181 } 2182 2183 static enum xgbe_mode xgbe_phy_get_baset_mode(struct xgbe_phy_data *phy_data, 2184 int speed) 2185 { 2186 switch (speed) { 2187 case SPEED_100: 2188 return XGBE_MODE_SGMII_100; 2189 case SPEED_1000: 2190 return XGBE_MODE_SGMII_1000; 2191 case SPEED_2500: 2192 return XGBE_MODE_KX_2500; 2193 case SPEED_10000: 2194 return XGBE_MODE_KR; 2195 default: 2196 return XGBE_MODE_UNKNOWN; 2197 } 2198 } 2199 2200 static enum xgbe_mode xgbe_phy_get_sfp_mode(struct xgbe_phy_data *phy_data, 2201 int speed) 2202 { 2203 switch (speed) { 2204 case SPEED_100: 2205 return XGBE_MODE_SGMII_100; 2206 case SPEED_1000: 2207 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T) 2208 return XGBE_MODE_SGMII_1000; 2209 else 2210 return XGBE_MODE_X; 2211 case SPEED_10000: 2212 case SPEED_UNKNOWN: 2213 return XGBE_MODE_SFI; 2214 default: 2215 return XGBE_MODE_UNKNOWN; 2216 } 2217 } 2218 2219 static enum xgbe_mode xgbe_phy_get_bp_2500_mode(int speed) 2220 { 2221 switch (speed) { 2222 case SPEED_2500: 2223 return XGBE_MODE_KX_2500; 2224 default: 2225 return XGBE_MODE_UNKNOWN; 2226 } 2227 } 2228 2229 static enum xgbe_mode xgbe_phy_get_bp_mode(int speed) 2230 { 2231 switch (speed) { 2232 case SPEED_1000: 2233 return XGBE_MODE_KX_1000; 2234 case SPEED_10000: 2235 return XGBE_MODE_KR; 2236 default: 2237 return XGBE_MODE_UNKNOWN; 2238 } 2239 } 2240 2241 static enum xgbe_mode xgbe_phy_get_mode(struct xgbe_prv_data *pdata, 2242 int speed) 2243 { 2244 struct xgbe_phy_data *phy_data = pdata->phy_data; 2245 2246 switch (phy_data->port_mode) { 2247 case XGBE_PORT_MODE_BACKPLANE: 2248 return xgbe_phy_get_bp_mode(speed); 2249 case XGBE_PORT_MODE_BACKPLANE_2500: 2250 return xgbe_phy_get_bp_2500_mode(speed); 2251 case XGBE_PORT_MODE_1000BASE_T: 2252 case XGBE_PORT_MODE_NBASE_T: 2253 case XGBE_PORT_MODE_10GBASE_T: 2254 return xgbe_phy_get_baset_mode(phy_data, speed); 2255 case XGBE_PORT_MODE_1000BASE_X: 2256 case XGBE_PORT_MODE_10GBASE_R: 2257 return xgbe_phy_get_basex_mode(phy_data, speed); 2258 case XGBE_PORT_MODE_SFP: 2259 return xgbe_phy_get_sfp_mode(phy_data, speed); 2260 default: 2261 return XGBE_MODE_UNKNOWN; 2262 } 2263 } 2264 2265 static void xgbe_phy_set_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode) 2266 { 2267 switch (mode) { 2268 case XGBE_MODE_KX_1000: 2269 xgbe_phy_kx_1000_mode(pdata); 2270 break; 2271 case XGBE_MODE_KX_2500: 2272 xgbe_phy_kx_2500_mode(pdata); 2273 break; 2274 case XGBE_MODE_KR: 2275 xgbe_phy_kr_mode(pdata); 2276 break; 2277 case XGBE_MODE_SGMII_100: 2278 xgbe_phy_sgmii_100_mode(pdata); 2279 break; 2280 case XGBE_MODE_SGMII_1000: 2281 xgbe_phy_sgmii_1000_mode(pdata); 2282 break; 2283 case XGBE_MODE_X: 2284 xgbe_phy_x_mode(pdata); 2285 break; 2286 case XGBE_MODE_SFI: 2287 xgbe_phy_sfi_mode(pdata); 2288 break; 2289 default: 2290 break; 2291 } 2292 } 2293 2294 static bool xgbe_phy_check_mode(struct xgbe_prv_data *pdata, 2295 enum xgbe_mode mode, bool advert) 2296 { 2297 if (pdata->phy.autoneg == AUTONEG_ENABLE) { 2298 return advert; 2299 } else { 2300 enum xgbe_mode cur_mode; 2301 2302 cur_mode = xgbe_phy_get_mode(pdata, pdata->phy.speed); 2303 if (cur_mode == mode) 2304 return true; 2305 } 2306 2307 return false; 2308 } 2309 2310 static bool xgbe_phy_use_basex_mode(struct xgbe_prv_data *pdata, 2311 enum xgbe_mode mode) 2312 { 2313 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 2314 2315 switch (mode) { 2316 case XGBE_MODE_X: 2317 return xgbe_phy_check_mode(pdata, mode, 2318 XGBE_ADV(lks, 1000baseX_Full)); 2319 case XGBE_MODE_KR: 2320 return xgbe_phy_check_mode(pdata, mode, 2321 XGBE_ADV(lks, 10000baseKR_Full)); 2322 default: 2323 return false; 2324 } 2325 } 2326 2327 static bool xgbe_phy_use_baset_mode(struct xgbe_prv_data *pdata, 2328 enum xgbe_mode mode) 2329 { 2330 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 2331 2332 switch (mode) { 2333 case XGBE_MODE_SGMII_100: 2334 return xgbe_phy_check_mode(pdata, mode, 2335 XGBE_ADV(lks, 100baseT_Full)); 2336 case XGBE_MODE_SGMII_1000: 2337 return xgbe_phy_check_mode(pdata, mode, 2338 XGBE_ADV(lks, 1000baseT_Full)); 2339 case XGBE_MODE_KX_2500: 2340 return xgbe_phy_check_mode(pdata, mode, 2341 XGBE_ADV(lks, 2500baseT_Full)); 2342 case XGBE_MODE_KR: 2343 return xgbe_phy_check_mode(pdata, mode, 2344 XGBE_ADV(lks, 10000baseT_Full)); 2345 default: 2346 return false; 2347 } 2348 } 2349 2350 static bool xgbe_phy_use_sfp_mode(struct xgbe_prv_data *pdata, 2351 enum xgbe_mode mode) 2352 { 2353 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 2354 struct xgbe_phy_data *phy_data = pdata->phy_data; 2355 2356 switch (mode) { 2357 case XGBE_MODE_X: 2358 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T) 2359 return false; 2360 return xgbe_phy_check_mode(pdata, mode, 2361 XGBE_ADV(lks, 1000baseX_Full)); 2362 case XGBE_MODE_SGMII_100: 2363 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T) 2364 return false; 2365 return xgbe_phy_check_mode(pdata, mode, 2366 XGBE_ADV(lks, 100baseT_Full)); 2367 case XGBE_MODE_SGMII_1000: 2368 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T) 2369 return false; 2370 return xgbe_phy_check_mode(pdata, mode, 2371 XGBE_ADV(lks, 1000baseT_Full)); 2372 case XGBE_MODE_SFI: 2373 if (phy_data->sfp_mod_absent) 2374 return true; 2375 return xgbe_phy_check_mode(pdata, mode, 2376 XGBE_ADV(lks, 10000baseSR_Full) || 2377 XGBE_ADV(lks, 10000baseLR_Full) || 2378 XGBE_ADV(lks, 10000baseLRM_Full) || 2379 XGBE_ADV(lks, 10000baseER_Full) || 2380 XGBE_ADV(lks, 10000baseCR_Full)); 2381 default: 2382 return false; 2383 } 2384 } 2385 2386 static bool xgbe_phy_use_bp_2500_mode(struct xgbe_prv_data *pdata, 2387 enum xgbe_mode mode) 2388 { 2389 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 2390 2391 switch (mode) { 2392 case XGBE_MODE_KX_2500: 2393 return xgbe_phy_check_mode(pdata, mode, 2394 XGBE_ADV(lks, 2500baseX_Full)); 2395 default: 2396 return false; 2397 } 2398 } 2399 2400 static bool xgbe_phy_use_bp_mode(struct xgbe_prv_data *pdata, 2401 enum xgbe_mode mode) 2402 { 2403 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 2404 2405 switch (mode) { 2406 case XGBE_MODE_KX_1000: 2407 return xgbe_phy_check_mode(pdata, mode, 2408 XGBE_ADV(lks, 1000baseKX_Full)); 2409 case XGBE_MODE_KR: 2410 return xgbe_phy_check_mode(pdata, mode, 2411 XGBE_ADV(lks, 10000baseKR_Full)); 2412 default: 2413 return false; 2414 } 2415 } 2416 2417 static bool xgbe_phy_use_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode) 2418 { 2419 struct xgbe_phy_data *phy_data = pdata->phy_data; 2420 2421 switch (phy_data->port_mode) { 2422 case XGBE_PORT_MODE_BACKPLANE: 2423 return xgbe_phy_use_bp_mode(pdata, mode); 2424 case XGBE_PORT_MODE_BACKPLANE_2500: 2425 return xgbe_phy_use_bp_2500_mode(pdata, mode); 2426 case XGBE_PORT_MODE_1000BASE_T: 2427 case XGBE_PORT_MODE_NBASE_T: 2428 case XGBE_PORT_MODE_10GBASE_T: 2429 return xgbe_phy_use_baset_mode(pdata, mode); 2430 case XGBE_PORT_MODE_1000BASE_X: 2431 case XGBE_PORT_MODE_10GBASE_R: 2432 return xgbe_phy_use_basex_mode(pdata, mode); 2433 case XGBE_PORT_MODE_SFP: 2434 return xgbe_phy_use_sfp_mode(pdata, mode); 2435 default: 2436 return false; 2437 } 2438 } 2439 2440 static bool xgbe_phy_valid_speed_basex_mode(struct xgbe_phy_data *phy_data, 2441 int speed) 2442 { 2443 switch (speed) { 2444 case SPEED_1000: 2445 return (phy_data->port_mode == XGBE_PORT_MODE_1000BASE_X); 2446 case SPEED_10000: 2447 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_R); 2448 default: 2449 return false; 2450 } 2451 } 2452 2453 static bool xgbe_phy_valid_speed_baset_mode(struct xgbe_phy_data *phy_data, 2454 int speed) 2455 { 2456 switch (speed) { 2457 case SPEED_100: 2458 case SPEED_1000: 2459 return true; 2460 case SPEED_2500: 2461 return (phy_data->port_mode == XGBE_PORT_MODE_NBASE_T); 2462 case SPEED_10000: 2463 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_T); 2464 default: 2465 return false; 2466 } 2467 } 2468 2469 static bool xgbe_phy_valid_speed_sfp_mode(struct xgbe_phy_data *phy_data, 2470 int speed) 2471 { 2472 switch (speed) { 2473 case SPEED_100: 2474 return (phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000); 2475 case SPEED_1000: 2476 return ((phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000) || 2477 (phy_data->sfp_speed == XGBE_SFP_SPEED_1000)); 2478 case SPEED_10000: 2479 return (phy_data->sfp_speed == XGBE_SFP_SPEED_10000); 2480 default: 2481 return false; 2482 } 2483 } 2484 2485 static bool xgbe_phy_valid_speed_bp_2500_mode(int speed) 2486 { 2487 switch (speed) { 2488 case SPEED_2500: 2489 return true; 2490 default: 2491 return false; 2492 } 2493 } 2494 2495 static bool xgbe_phy_valid_speed_bp_mode(int speed) 2496 { 2497 switch (speed) { 2498 case SPEED_1000: 2499 case SPEED_10000: 2500 return true; 2501 default: 2502 return false; 2503 } 2504 } 2505 2506 static bool xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed) 2507 { 2508 struct xgbe_phy_data *phy_data = pdata->phy_data; 2509 2510 switch (phy_data->port_mode) { 2511 case XGBE_PORT_MODE_BACKPLANE: 2512 return xgbe_phy_valid_speed_bp_mode(speed); 2513 case XGBE_PORT_MODE_BACKPLANE_2500: 2514 return xgbe_phy_valid_speed_bp_2500_mode(speed); 2515 case XGBE_PORT_MODE_1000BASE_T: 2516 case XGBE_PORT_MODE_NBASE_T: 2517 case XGBE_PORT_MODE_10GBASE_T: 2518 return xgbe_phy_valid_speed_baset_mode(phy_data, speed); 2519 case XGBE_PORT_MODE_1000BASE_X: 2520 case XGBE_PORT_MODE_10GBASE_R: 2521 return xgbe_phy_valid_speed_basex_mode(phy_data, speed); 2522 case XGBE_PORT_MODE_SFP: 2523 return xgbe_phy_valid_speed_sfp_mode(phy_data, speed); 2524 default: 2525 return false; 2526 } 2527 } 2528 2529 static int xgbe_phy_link_status(struct xgbe_prv_data *pdata, int *an_restart) 2530 { 2531 struct xgbe_phy_data *phy_data = pdata->phy_data; 2532 unsigned int reg; 2533 int ret; 2534 2535 *an_restart = 0; 2536 2537 if (phy_data->port_mode == XGBE_PORT_MODE_SFP) { 2538 /* Check SFP signals */ 2539 xgbe_phy_sfp_detect(pdata); 2540 2541 if (phy_data->sfp_changed) { 2542 *an_restart = 1; 2543 return 0; 2544 } 2545 2546 if (phy_data->sfp_mod_absent || phy_data->sfp_rx_los) 2547 return 0; 2548 } 2549 2550 if (phy_data->phydev) { 2551 /* Check external PHY */ 2552 ret = phy_read_status(phy_data->phydev); 2553 if (ret < 0) 2554 return 0; 2555 2556 if ((pdata->phy.autoneg == AUTONEG_ENABLE) && 2557 !phy_aneg_done(phy_data->phydev)) 2558 return 0; 2559 2560 if (!phy_data->phydev->link) 2561 return 0; 2562 } 2563 2564 /* Link status is latched low, so read once to clear 2565 * and then read again to get current state 2566 */ 2567 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); 2568 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); 2569 if (reg & MDIO_STAT1_LSTATUS) 2570 return 1; 2571 2572 /* No link, attempt a receiver reset cycle */ 2573 if (phy_data->rrc_count++ > XGBE_RRC_FREQUENCY) { 2574 phy_data->rrc_count = 0; 2575 xgbe_phy_rrc(pdata); 2576 } 2577 2578 return 0; 2579 } 2580 2581 static void xgbe_phy_sfp_gpio_setup(struct xgbe_prv_data *pdata) 2582 { 2583 struct xgbe_phy_data *phy_data = pdata->phy_data; 2584 2585 phy_data->sfp_gpio_address = XGBE_GPIO_ADDRESS_PCA9555 + 2586 XP_GET_BITS(pdata->pp3, XP_PROP_3, 2587 GPIO_ADDR); 2588 2589 phy_data->sfp_gpio_mask = XP_GET_BITS(pdata->pp3, XP_PROP_3, 2590 GPIO_MASK); 2591 2592 phy_data->sfp_gpio_rx_los = XP_GET_BITS(pdata->pp3, XP_PROP_3, 2593 GPIO_RX_LOS); 2594 phy_data->sfp_gpio_tx_fault = XP_GET_BITS(pdata->pp3, XP_PROP_3, 2595 GPIO_TX_FAULT); 2596 phy_data->sfp_gpio_mod_absent = XP_GET_BITS(pdata->pp3, XP_PROP_3, 2597 GPIO_MOD_ABS); 2598 phy_data->sfp_gpio_rate_select = XP_GET_BITS(pdata->pp3, XP_PROP_3, 2599 GPIO_RATE_SELECT); 2600 2601 if (netif_msg_probe(pdata)) { 2602 dev_dbg(pdata->dev, "SFP: gpio_address=%#x\n", 2603 phy_data->sfp_gpio_address); 2604 dev_dbg(pdata->dev, "SFP: gpio_mask=%#x\n", 2605 phy_data->sfp_gpio_mask); 2606 dev_dbg(pdata->dev, "SFP: gpio_rx_los=%u\n", 2607 phy_data->sfp_gpio_rx_los); 2608 dev_dbg(pdata->dev, "SFP: gpio_tx_fault=%u\n", 2609 phy_data->sfp_gpio_tx_fault); 2610 dev_dbg(pdata->dev, "SFP: gpio_mod_absent=%u\n", 2611 phy_data->sfp_gpio_mod_absent); 2612 dev_dbg(pdata->dev, "SFP: gpio_rate_select=%u\n", 2613 phy_data->sfp_gpio_rate_select); 2614 } 2615 } 2616 2617 static void xgbe_phy_sfp_comm_setup(struct xgbe_prv_data *pdata) 2618 { 2619 struct xgbe_phy_data *phy_data = pdata->phy_data; 2620 unsigned int mux_addr_hi, mux_addr_lo; 2621 2622 mux_addr_hi = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_HI); 2623 mux_addr_lo = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_LO); 2624 if (mux_addr_lo == XGBE_SFP_DIRECT) 2625 return; 2626 2627 phy_data->sfp_comm = XGBE_SFP_COMM_PCA9545; 2628 phy_data->sfp_mux_address = (mux_addr_hi << 2) + mux_addr_lo; 2629 phy_data->sfp_mux_channel = XP_GET_BITS(pdata->pp4, XP_PROP_4, 2630 MUX_CHAN); 2631 2632 if (netif_msg_probe(pdata)) { 2633 dev_dbg(pdata->dev, "SFP: mux_address=%#x\n", 2634 phy_data->sfp_mux_address); 2635 dev_dbg(pdata->dev, "SFP: mux_channel=%u\n", 2636 phy_data->sfp_mux_channel); 2637 } 2638 } 2639 2640 static void xgbe_phy_sfp_setup(struct xgbe_prv_data *pdata) 2641 { 2642 xgbe_phy_sfp_comm_setup(pdata); 2643 xgbe_phy_sfp_gpio_setup(pdata); 2644 } 2645 2646 static int xgbe_phy_int_mdio_reset(struct xgbe_prv_data *pdata) 2647 { 2648 struct xgbe_phy_data *phy_data = pdata->phy_data; 2649 unsigned int ret; 2650 2651 ret = pdata->hw_if.set_gpio(pdata, phy_data->mdio_reset_gpio); 2652 if (ret) 2653 return ret; 2654 2655 ret = pdata->hw_if.clr_gpio(pdata, phy_data->mdio_reset_gpio); 2656 2657 return ret; 2658 } 2659 2660 static int xgbe_phy_i2c_mdio_reset(struct xgbe_prv_data *pdata) 2661 { 2662 struct xgbe_phy_data *phy_data = pdata->phy_data; 2663 u8 gpio_reg, gpio_ports[2], gpio_data[3]; 2664 int ret; 2665 2666 /* Read the output port registers */ 2667 gpio_reg = 2; 2668 ret = xgbe_phy_i2c_read(pdata, phy_data->mdio_reset_addr, 2669 &gpio_reg, sizeof(gpio_reg), 2670 gpio_ports, sizeof(gpio_ports)); 2671 if (ret) 2672 return ret; 2673 2674 /* Prepare to write the GPIO data */ 2675 gpio_data[0] = 2; 2676 gpio_data[1] = gpio_ports[0]; 2677 gpio_data[2] = gpio_ports[1]; 2678 2679 /* Set the GPIO pin */ 2680 if (phy_data->mdio_reset_gpio < 8) 2681 gpio_data[1] |= (1 << (phy_data->mdio_reset_gpio % 8)); 2682 else 2683 gpio_data[2] |= (1 << (phy_data->mdio_reset_gpio % 8)); 2684 2685 /* Write the output port registers */ 2686 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr, 2687 gpio_data, sizeof(gpio_data)); 2688 if (ret) 2689 return ret; 2690 2691 /* Clear the GPIO pin */ 2692 if (phy_data->mdio_reset_gpio < 8) 2693 gpio_data[1] &= ~(1 << (phy_data->mdio_reset_gpio % 8)); 2694 else 2695 gpio_data[2] &= ~(1 << (phy_data->mdio_reset_gpio % 8)); 2696 2697 /* Write the output port registers */ 2698 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr, 2699 gpio_data, sizeof(gpio_data)); 2700 2701 return ret; 2702 } 2703 2704 static int xgbe_phy_mdio_reset(struct xgbe_prv_data *pdata) 2705 { 2706 struct xgbe_phy_data *phy_data = pdata->phy_data; 2707 int ret; 2708 2709 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO) 2710 return 0; 2711 2712 ret = xgbe_phy_get_comm_ownership(pdata); 2713 if (ret) 2714 return ret; 2715 2716 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO) 2717 ret = xgbe_phy_i2c_mdio_reset(pdata); 2718 else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO) 2719 ret = xgbe_phy_int_mdio_reset(pdata); 2720 2721 xgbe_phy_put_comm_ownership(pdata); 2722 2723 return ret; 2724 } 2725 2726 static bool xgbe_phy_redrv_error(struct xgbe_phy_data *phy_data) 2727 { 2728 if (!phy_data->redrv) 2729 return false; 2730 2731 if (phy_data->redrv_if >= XGBE_PHY_REDRV_IF_MAX) 2732 return true; 2733 2734 switch (phy_data->redrv_model) { 2735 case XGBE_PHY_REDRV_MODEL_4223: 2736 if (phy_data->redrv_lane > 3) 2737 return true; 2738 break; 2739 case XGBE_PHY_REDRV_MODEL_4227: 2740 if (phy_data->redrv_lane > 1) 2741 return true; 2742 break; 2743 default: 2744 return true; 2745 } 2746 2747 return false; 2748 } 2749 2750 static int xgbe_phy_mdio_reset_setup(struct xgbe_prv_data *pdata) 2751 { 2752 struct xgbe_phy_data *phy_data = pdata->phy_data; 2753 2754 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO) 2755 return 0; 2756 2757 phy_data->mdio_reset = XP_GET_BITS(pdata->pp3, XP_PROP_3, MDIO_RESET); 2758 switch (phy_data->mdio_reset) { 2759 case XGBE_MDIO_RESET_NONE: 2760 case XGBE_MDIO_RESET_I2C_GPIO: 2761 case XGBE_MDIO_RESET_INT_GPIO: 2762 break; 2763 default: 2764 dev_err(pdata->dev, "unsupported MDIO reset (%#x)\n", 2765 phy_data->mdio_reset); 2766 return -EINVAL; 2767 } 2768 2769 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO) { 2770 phy_data->mdio_reset_addr = XGBE_GPIO_ADDRESS_PCA9555 + 2771 XP_GET_BITS(pdata->pp3, XP_PROP_3, 2772 MDIO_RESET_I2C_ADDR); 2773 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3, 2774 MDIO_RESET_I2C_GPIO); 2775 } else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO) { 2776 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3, 2777 MDIO_RESET_INT_GPIO); 2778 } 2779 2780 return 0; 2781 } 2782 2783 static bool xgbe_phy_port_mode_mismatch(struct xgbe_prv_data *pdata) 2784 { 2785 struct xgbe_phy_data *phy_data = pdata->phy_data; 2786 2787 switch (phy_data->port_mode) { 2788 case XGBE_PORT_MODE_BACKPLANE: 2789 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) || 2790 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)) 2791 return false; 2792 break; 2793 case XGBE_PORT_MODE_BACKPLANE_2500: 2794 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) 2795 return false; 2796 break; 2797 case XGBE_PORT_MODE_1000BASE_T: 2798 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 2799 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)) 2800 return false; 2801 break; 2802 case XGBE_PORT_MODE_1000BASE_X: 2803 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) 2804 return false; 2805 break; 2806 case XGBE_PORT_MODE_NBASE_T: 2807 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 2808 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) || 2809 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500)) 2810 return false; 2811 break; 2812 case XGBE_PORT_MODE_10GBASE_T: 2813 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 2814 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) || 2815 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)) 2816 return false; 2817 break; 2818 case XGBE_PORT_MODE_10GBASE_R: 2819 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) 2820 return false; 2821 break; 2822 case XGBE_PORT_MODE_SFP: 2823 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 2824 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) || 2825 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)) 2826 return false; 2827 break; 2828 default: 2829 break; 2830 } 2831 2832 return true; 2833 } 2834 2835 static bool xgbe_phy_conn_type_mismatch(struct xgbe_prv_data *pdata) 2836 { 2837 struct xgbe_phy_data *phy_data = pdata->phy_data; 2838 2839 switch (phy_data->port_mode) { 2840 case XGBE_PORT_MODE_BACKPLANE: 2841 case XGBE_PORT_MODE_BACKPLANE_2500: 2842 if (phy_data->conn_type == XGBE_CONN_TYPE_BACKPLANE) 2843 return false; 2844 break; 2845 case XGBE_PORT_MODE_1000BASE_T: 2846 case XGBE_PORT_MODE_1000BASE_X: 2847 case XGBE_PORT_MODE_NBASE_T: 2848 case XGBE_PORT_MODE_10GBASE_T: 2849 case XGBE_PORT_MODE_10GBASE_R: 2850 if (phy_data->conn_type == XGBE_CONN_TYPE_MDIO) 2851 return false; 2852 break; 2853 case XGBE_PORT_MODE_SFP: 2854 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP) 2855 return false; 2856 break; 2857 default: 2858 break; 2859 } 2860 2861 return true; 2862 } 2863 2864 static bool xgbe_phy_port_enabled(struct xgbe_prv_data *pdata) 2865 { 2866 if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS)) 2867 return false; 2868 if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE)) 2869 return false; 2870 2871 return true; 2872 } 2873 2874 static void xgbe_phy_cdr_track(struct xgbe_prv_data *pdata) 2875 { 2876 struct xgbe_phy_data *phy_data = pdata->phy_data; 2877 2878 if (!pdata->debugfs_an_cdr_workaround) 2879 return; 2880 2881 if (!phy_data->phy_cdr_notrack) 2882 return; 2883 2884 usleep_range(phy_data->phy_cdr_delay, 2885 phy_data->phy_cdr_delay + 500); 2886 2887 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL, 2888 XGBE_PMA_CDR_TRACK_EN_MASK, 2889 XGBE_PMA_CDR_TRACK_EN_ON); 2890 2891 phy_data->phy_cdr_notrack = 0; 2892 } 2893 2894 static void xgbe_phy_cdr_notrack(struct xgbe_prv_data *pdata) 2895 { 2896 struct xgbe_phy_data *phy_data = pdata->phy_data; 2897 2898 if (!pdata->debugfs_an_cdr_workaround) 2899 return; 2900 2901 if (phy_data->phy_cdr_notrack) 2902 return; 2903 2904 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL, 2905 XGBE_PMA_CDR_TRACK_EN_MASK, 2906 XGBE_PMA_CDR_TRACK_EN_OFF); 2907 2908 xgbe_phy_rrc(pdata); 2909 2910 phy_data->phy_cdr_notrack = 1; 2911 } 2912 2913 static void xgbe_phy_kr_training_post(struct xgbe_prv_data *pdata) 2914 { 2915 if (!pdata->debugfs_an_cdr_track_early) 2916 xgbe_phy_cdr_track(pdata); 2917 } 2918 2919 static void xgbe_phy_kr_training_pre(struct xgbe_prv_data *pdata) 2920 { 2921 if (pdata->debugfs_an_cdr_track_early) 2922 xgbe_phy_cdr_track(pdata); 2923 } 2924 2925 static void xgbe_phy_an_post(struct xgbe_prv_data *pdata) 2926 { 2927 struct xgbe_phy_data *phy_data = pdata->phy_data; 2928 2929 switch (pdata->an_mode) { 2930 case XGBE_AN_MODE_CL73: 2931 case XGBE_AN_MODE_CL73_REDRV: 2932 if (phy_data->cur_mode != XGBE_MODE_KR) 2933 break; 2934 2935 xgbe_phy_cdr_track(pdata); 2936 2937 switch (pdata->an_result) { 2938 case XGBE_AN_READY: 2939 case XGBE_AN_COMPLETE: 2940 break; 2941 default: 2942 if (phy_data->phy_cdr_delay < XGBE_CDR_DELAY_MAX) 2943 phy_data->phy_cdr_delay += XGBE_CDR_DELAY_INC; 2944 else 2945 phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT; 2946 break; 2947 } 2948 break; 2949 default: 2950 break; 2951 } 2952 } 2953 2954 static void xgbe_phy_an_pre(struct xgbe_prv_data *pdata) 2955 { 2956 struct xgbe_phy_data *phy_data = pdata->phy_data; 2957 2958 switch (pdata->an_mode) { 2959 case XGBE_AN_MODE_CL73: 2960 case XGBE_AN_MODE_CL73_REDRV: 2961 if (phy_data->cur_mode != XGBE_MODE_KR) 2962 break; 2963 2964 xgbe_phy_cdr_notrack(pdata); 2965 break; 2966 default: 2967 break; 2968 } 2969 } 2970 2971 static void xgbe_phy_stop(struct xgbe_prv_data *pdata) 2972 { 2973 struct xgbe_phy_data *phy_data = pdata->phy_data; 2974 2975 /* If we have an external PHY, free it */ 2976 xgbe_phy_free_phy_device(pdata); 2977 2978 /* Reset SFP data */ 2979 xgbe_phy_sfp_reset(phy_data); 2980 xgbe_phy_sfp_mod_absent(pdata); 2981 2982 /* Reset CDR support */ 2983 xgbe_phy_cdr_track(pdata); 2984 2985 /* Power off the PHY */ 2986 xgbe_phy_power_off(pdata); 2987 2988 /* Stop the I2C controller */ 2989 pdata->i2c_if.i2c_stop(pdata); 2990 } 2991 2992 static int xgbe_phy_start(struct xgbe_prv_data *pdata) 2993 { 2994 struct xgbe_phy_data *phy_data = pdata->phy_data; 2995 int ret; 2996 2997 /* Start the I2C controller */ 2998 ret = pdata->i2c_if.i2c_start(pdata); 2999 if (ret) 3000 return ret; 3001 3002 /* Set the proper MDIO mode for the re-driver */ 3003 if (phy_data->redrv && !phy_data->redrv_if) { 3004 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr, 3005 XGBE_MDIO_MODE_CL22); 3006 if (ret) { 3007 netdev_err(pdata->netdev, 3008 "redriver mdio port not compatible (%u)\n", 3009 phy_data->redrv_addr); 3010 return ret; 3011 } 3012 } 3013 3014 /* Start in highest supported mode */ 3015 xgbe_phy_set_mode(pdata, phy_data->start_mode); 3016 3017 /* Reset CDR support */ 3018 xgbe_phy_cdr_track(pdata); 3019 3020 /* After starting the I2C controller, we can check for an SFP */ 3021 switch (phy_data->port_mode) { 3022 case XGBE_PORT_MODE_SFP: 3023 xgbe_phy_sfp_detect(pdata); 3024 break; 3025 default: 3026 break; 3027 } 3028 3029 /* If we have an external PHY, start it */ 3030 ret = xgbe_phy_find_phy_device(pdata); 3031 if (ret) 3032 goto err_i2c; 3033 3034 return 0; 3035 3036 err_i2c: 3037 pdata->i2c_if.i2c_stop(pdata); 3038 3039 return ret; 3040 } 3041 3042 static int xgbe_phy_reset(struct xgbe_prv_data *pdata) 3043 { 3044 struct xgbe_phy_data *phy_data = pdata->phy_data; 3045 enum xgbe_mode cur_mode; 3046 int ret; 3047 3048 /* Reset by power cycling the PHY */ 3049 cur_mode = phy_data->cur_mode; 3050 xgbe_phy_power_off(pdata); 3051 xgbe_phy_set_mode(pdata, cur_mode); 3052 3053 if (!phy_data->phydev) 3054 return 0; 3055 3056 /* Reset the external PHY */ 3057 ret = xgbe_phy_mdio_reset(pdata); 3058 if (ret) 3059 return ret; 3060 3061 return phy_init_hw(phy_data->phydev); 3062 } 3063 3064 static void xgbe_phy_exit(struct xgbe_prv_data *pdata) 3065 { 3066 struct xgbe_phy_data *phy_data = pdata->phy_data; 3067 3068 /* Unregister for driving external PHYs */ 3069 mdiobus_unregister(phy_data->mii); 3070 } 3071 3072 static int xgbe_phy_init(struct xgbe_prv_data *pdata) 3073 { 3074 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 3075 struct xgbe_phy_data *phy_data; 3076 struct mii_bus *mii; 3077 int ret; 3078 3079 /* Check if enabled */ 3080 if (!xgbe_phy_port_enabled(pdata)) { 3081 dev_info(pdata->dev, "device is not enabled\n"); 3082 return -ENODEV; 3083 } 3084 3085 /* Initialize the I2C controller */ 3086 ret = pdata->i2c_if.i2c_init(pdata); 3087 if (ret) 3088 return ret; 3089 3090 phy_data = devm_kzalloc(pdata->dev, sizeof(*phy_data), GFP_KERNEL); 3091 if (!phy_data) 3092 return -ENOMEM; 3093 pdata->phy_data = phy_data; 3094 3095 phy_data->port_mode = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_MODE); 3096 phy_data->port_id = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_ID); 3097 phy_data->port_speeds = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS); 3098 phy_data->conn_type = XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE); 3099 phy_data->mdio_addr = XP_GET_BITS(pdata->pp0, XP_PROP_0, MDIO_ADDR); 3100 if (netif_msg_probe(pdata)) { 3101 dev_dbg(pdata->dev, "port mode=%u\n", phy_data->port_mode); 3102 dev_dbg(pdata->dev, "port id=%u\n", phy_data->port_id); 3103 dev_dbg(pdata->dev, "port speeds=%#x\n", phy_data->port_speeds); 3104 dev_dbg(pdata->dev, "conn type=%u\n", phy_data->conn_type); 3105 dev_dbg(pdata->dev, "mdio addr=%u\n", phy_data->mdio_addr); 3106 } 3107 3108 phy_data->redrv = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_PRESENT); 3109 phy_data->redrv_if = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_IF); 3110 phy_data->redrv_addr = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_ADDR); 3111 phy_data->redrv_lane = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_LANE); 3112 phy_data->redrv_model = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_MODEL); 3113 if (phy_data->redrv && netif_msg_probe(pdata)) { 3114 dev_dbg(pdata->dev, "redrv present\n"); 3115 dev_dbg(pdata->dev, "redrv i/f=%u\n", phy_data->redrv_if); 3116 dev_dbg(pdata->dev, "redrv addr=%#x\n", phy_data->redrv_addr); 3117 dev_dbg(pdata->dev, "redrv lane=%u\n", phy_data->redrv_lane); 3118 dev_dbg(pdata->dev, "redrv model=%u\n", phy_data->redrv_model); 3119 } 3120 3121 /* Validate the connection requested */ 3122 if (xgbe_phy_conn_type_mismatch(pdata)) { 3123 dev_err(pdata->dev, "phy mode/connection mismatch (%#x/%#x)\n", 3124 phy_data->port_mode, phy_data->conn_type); 3125 return -EINVAL; 3126 } 3127 3128 /* Validate the mode requested */ 3129 if (xgbe_phy_port_mode_mismatch(pdata)) { 3130 dev_err(pdata->dev, "phy mode/speed mismatch (%#x/%#x)\n", 3131 phy_data->port_mode, phy_data->port_speeds); 3132 return -EINVAL; 3133 } 3134 3135 /* Check for and validate MDIO reset support */ 3136 ret = xgbe_phy_mdio_reset_setup(pdata); 3137 if (ret) 3138 return ret; 3139 3140 /* Validate the re-driver information */ 3141 if (xgbe_phy_redrv_error(phy_data)) { 3142 dev_err(pdata->dev, "phy re-driver settings error\n"); 3143 return -EINVAL; 3144 } 3145 pdata->kr_redrv = phy_data->redrv; 3146 3147 /* Indicate current mode is unknown */ 3148 phy_data->cur_mode = XGBE_MODE_UNKNOWN; 3149 3150 /* Initialize supported features */ 3151 XGBE_ZERO_SUP(lks); 3152 3153 switch (phy_data->port_mode) { 3154 /* Backplane support */ 3155 case XGBE_PORT_MODE_BACKPLANE: 3156 XGBE_SET_SUP(lks, Autoneg); 3157 XGBE_SET_SUP(lks, Pause); 3158 XGBE_SET_SUP(lks, Asym_Pause); 3159 XGBE_SET_SUP(lks, Backplane); 3160 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) { 3161 XGBE_SET_SUP(lks, 1000baseKX_Full); 3162 phy_data->start_mode = XGBE_MODE_KX_1000; 3163 } 3164 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) { 3165 XGBE_SET_SUP(lks, 10000baseKR_Full); 3166 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 3167 XGBE_SET_SUP(lks, 10000baseR_FEC); 3168 phy_data->start_mode = XGBE_MODE_KR; 3169 } 3170 3171 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE; 3172 break; 3173 case XGBE_PORT_MODE_BACKPLANE_2500: 3174 XGBE_SET_SUP(lks, Pause); 3175 XGBE_SET_SUP(lks, Asym_Pause); 3176 XGBE_SET_SUP(lks, Backplane); 3177 XGBE_SET_SUP(lks, 2500baseX_Full); 3178 phy_data->start_mode = XGBE_MODE_KX_2500; 3179 3180 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE; 3181 break; 3182 3183 /* MDIO 1GBase-T support */ 3184 case XGBE_PORT_MODE_1000BASE_T: 3185 XGBE_SET_SUP(lks, Autoneg); 3186 XGBE_SET_SUP(lks, Pause); 3187 XGBE_SET_SUP(lks, Asym_Pause); 3188 XGBE_SET_SUP(lks, TP); 3189 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) { 3190 XGBE_SET_SUP(lks, 100baseT_Full); 3191 phy_data->start_mode = XGBE_MODE_SGMII_100; 3192 } 3193 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) { 3194 XGBE_SET_SUP(lks, 1000baseT_Full); 3195 phy_data->start_mode = XGBE_MODE_SGMII_1000; 3196 } 3197 3198 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22; 3199 break; 3200 3201 /* MDIO Base-X support */ 3202 case XGBE_PORT_MODE_1000BASE_X: 3203 XGBE_SET_SUP(lks, Autoneg); 3204 XGBE_SET_SUP(lks, Pause); 3205 XGBE_SET_SUP(lks, Asym_Pause); 3206 XGBE_SET_SUP(lks, FIBRE); 3207 XGBE_SET_SUP(lks, 1000baseX_Full); 3208 phy_data->start_mode = XGBE_MODE_X; 3209 3210 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22; 3211 break; 3212 3213 /* MDIO NBase-T support */ 3214 case XGBE_PORT_MODE_NBASE_T: 3215 XGBE_SET_SUP(lks, Autoneg); 3216 XGBE_SET_SUP(lks, Pause); 3217 XGBE_SET_SUP(lks, Asym_Pause); 3218 XGBE_SET_SUP(lks, TP); 3219 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) { 3220 XGBE_SET_SUP(lks, 100baseT_Full); 3221 phy_data->start_mode = XGBE_MODE_SGMII_100; 3222 } 3223 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) { 3224 XGBE_SET_SUP(lks, 1000baseT_Full); 3225 phy_data->start_mode = XGBE_MODE_SGMII_1000; 3226 } 3227 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) { 3228 XGBE_SET_SUP(lks, 2500baseT_Full); 3229 phy_data->start_mode = XGBE_MODE_KX_2500; 3230 } 3231 3232 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45; 3233 break; 3234 3235 /* 10GBase-T support */ 3236 case XGBE_PORT_MODE_10GBASE_T: 3237 XGBE_SET_SUP(lks, Autoneg); 3238 XGBE_SET_SUP(lks, Pause); 3239 XGBE_SET_SUP(lks, Asym_Pause); 3240 XGBE_SET_SUP(lks, TP); 3241 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) { 3242 XGBE_SET_SUP(lks, 100baseT_Full); 3243 phy_data->start_mode = XGBE_MODE_SGMII_100; 3244 } 3245 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) { 3246 XGBE_SET_SUP(lks, 1000baseT_Full); 3247 phy_data->start_mode = XGBE_MODE_SGMII_1000; 3248 } 3249 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) { 3250 XGBE_SET_SUP(lks, 10000baseT_Full); 3251 phy_data->start_mode = XGBE_MODE_KR; 3252 } 3253 3254 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45; 3255 break; 3256 3257 /* 10GBase-R support */ 3258 case XGBE_PORT_MODE_10GBASE_R: 3259 XGBE_SET_SUP(lks, Autoneg); 3260 XGBE_SET_SUP(lks, Pause); 3261 XGBE_SET_SUP(lks, Asym_Pause); 3262 XGBE_SET_SUP(lks, FIBRE); 3263 XGBE_SET_SUP(lks, 10000baseSR_Full); 3264 XGBE_SET_SUP(lks, 10000baseLR_Full); 3265 XGBE_SET_SUP(lks, 10000baseLRM_Full); 3266 XGBE_SET_SUP(lks, 10000baseER_Full); 3267 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 3268 XGBE_SET_SUP(lks, 10000baseR_FEC); 3269 phy_data->start_mode = XGBE_MODE_SFI; 3270 3271 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE; 3272 break; 3273 3274 /* SFP support */ 3275 case XGBE_PORT_MODE_SFP: 3276 XGBE_SET_SUP(lks, Autoneg); 3277 XGBE_SET_SUP(lks, Pause); 3278 XGBE_SET_SUP(lks, Asym_Pause); 3279 XGBE_SET_SUP(lks, TP); 3280 XGBE_SET_SUP(lks, FIBRE); 3281 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) 3282 phy_data->start_mode = XGBE_MODE_SGMII_100; 3283 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) 3284 phy_data->start_mode = XGBE_MODE_SGMII_1000; 3285 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) 3286 phy_data->start_mode = XGBE_MODE_SFI; 3287 3288 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22; 3289 3290 xgbe_phy_sfp_setup(pdata); 3291 break; 3292 default: 3293 return -EINVAL; 3294 } 3295 3296 if (netif_msg_probe(pdata)) 3297 dev_dbg(pdata->dev, "phy supported=0x%*pb\n", 3298 __ETHTOOL_LINK_MODE_MASK_NBITS, 3299 lks->link_modes.supported); 3300 3301 if ((phy_data->conn_type & XGBE_CONN_TYPE_MDIO) && 3302 (phy_data->phydev_mode != XGBE_MDIO_MODE_NONE)) { 3303 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr, 3304 phy_data->phydev_mode); 3305 if (ret) { 3306 dev_err(pdata->dev, 3307 "mdio port/clause not compatible (%d/%u)\n", 3308 phy_data->mdio_addr, phy_data->phydev_mode); 3309 return -EINVAL; 3310 } 3311 } 3312 3313 if (phy_data->redrv && !phy_data->redrv_if) { 3314 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr, 3315 XGBE_MDIO_MODE_CL22); 3316 if (ret) { 3317 dev_err(pdata->dev, 3318 "redriver mdio port not compatible (%u)\n", 3319 phy_data->redrv_addr); 3320 return -EINVAL; 3321 } 3322 } 3323 3324 phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT; 3325 3326 /* Register for driving external PHYs */ 3327 mii = devm_mdiobus_alloc(pdata->dev); 3328 if (!mii) { 3329 dev_err(pdata->dev, "mdiobus_alloc failed\n"); 3330 return -ENOMEM; 3331 } 3332 3333 mii->priv = pdata; 3334 mii->name = "amd-xgbe-mii"; 3335 mii->read = xgbe_phy_mii_read; 3336 mii->write = xgbe_phy_mii_write; 3337 mii->parent = pdata->dev; 3338 mii->phy_mask = ~0; 3339 snprintf(mii->id, sizeof(mii->id), "%s", dev_name(pdata->dev)); 3340 ret = mdiobus_register(mii); 3341 if (ret) { 3342 dev_err(pdata->dev, "mdiobus_register failed\n"); 3343 return ret; 3344 } 3345 phy_data->mii = mii; 3346 3347 return 0; 3348 } 3349 3350 void xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *phy_if) 3351 { 3352 struct xgbe_phy_impl_if *phy_impl = &phy_if->phy_impl; 3353 3354 phy_impl->init = xgbe_phy_init; 3355 phy_impl->exit = xgbe_phy_exit; 3356 3357 phy_impl->reset = xgbe_phy_reset; 3358 phy_impl->start = xgbe_phy_start; 3359 phy_impl->stop = xgbe_phy_stop; 3360 3361 phy_impl->link_status = xgbe_phy_link_status; 3362 3363 phy_impl->valid_speed = xgbe_phy_valid_speed; 3364 3365 phy_impl->use_mode = xgbe_phy_use_mode; 3366 phy_impl->set_mode = xgbe_phy_set_mode; 3367 phy_impl->get_mode = xgbe_phy_get_mode; 3368 phy_impl->switch_mode = xgbe_phy_switch_mode; 3369 phy_impl->cur_mode = xgbe_phy_cur_mode; 3370 3371 phy_impl->an_mode = xgbe_phy_an_mode; 3372 3373 phy_impl->an_config = xgbe_phy_an_config; 3374 3375 phy_impl->an_advertising = xgbe_phy_an_advertising; 3376 3377 phy_impl->an_outcome = xgbe_phy_an_outcome; 3378 3379 phy_impl->an_pre = xgbe_phy_an_pre; 3380 phy_impl->an_post = xgbe_phy_an_post; 3381 3382 phy_impl->kr_training_pre = xgbe_phy_kr_training_pre; 3383 phy_impl->kr_training_post = xgbe_phy_kr_training_post; 3384 3385 phy_impl->module_info = xgbe_phy_module_info; 3386 phy_impl->module_eeprom = xgbe_phy_module_eeprom; 3387 } 3388