1 /* 2 * AMD 10Gb Ethernet driver 3 * 4 * This file is available to you under your choice of the following two 5 * licenses: 6 * 7 * License 1: GPLv2 8 * 9 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. 10 * 11 * This file is free software; you may copy, redistribute and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation, either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program. If not, see <http://www.gnu.org/licenses/>. 23 * 24 * This file incorporates work covered by the following copyright and 25 * permission notice: 26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 28 * Inc. unless otherwise expressly agreed to in writing between Synopsys 29 * and you. 30 * 31 * The Software IS NOT an item of Licensed Software or Licensed Product 32 * under any End User Software License Agreement or Agreement for Licensed 33 * Product with Synopsys or any supplement thereto. Permission is hereby 34 * granted, free of charge, to any person obtaining a copy of this software 35 * annotated with this license and the Software, to deal in the Software 36 * without restriction, including without limitation the rights to use, 37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 38 * of the Software, and to permit persons to whom the Software is furnished 39 * to do so, subject to the following conditions: 40 * 41 * The above copyright notice and this permission notice shall be included 42 * in all copies or substantial portions of the Software. 43 * 44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 54 * THE POSSIBILITY OF SUCH DAMAGE. 55 * 56 * 57 * License 2: Modified BSD 58 * 59 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. 60 * All rights reserved. 61 * 62 * Redistribution and use in source and binary forms, with or without 63 * modification, are permitted provided that the following conditions are met: 64 * * Redistributions of source code must retain the above copyright 65 * notice, this list of conditions and the following disclaimer. 66 * * Redistributions in binary form must reproduce the above copyright 67 * notice, this list of conditions and the following disclaimer in the 68 * documentation and/or other materials provided with the distribution. 69 * * Neither the name of Advanced Micro Devices, Inc. nor the 70 * names of its contributors may be used to endorse or promote products 71 * derived from this software without specific prior written permission. 72 * 73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY 77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 83 * 84 * This file incorporates work covered by the following copyright and 85 * permission notice: 86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 88 * Inc. unless otherwise expressly agreed to in writing between Synopsys 89 * and you. 90 * 91 * The Software IS NOT an item of Licensed Software or Licensed Product 92 * under any End User Software License Agreement or Agreement for Licensed 93 * Product with Synopsys or any supplement thereto. Permission is hereby 94 * granted, free of charge, to any person obtaining a copy of this software 95 * annotated with this license and the Software, to deal in the Software 96 * without restriction, including without limitation the rights to use, 97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 98 * of the Software, and to permit persons to whom the Software is furnished 99 * to do so, subject to the following conditions: 100 * 101 * The above copyright notice and this permission notice shall be included 102 * in all copies or substantial portions of the Software. 103 * 104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 114 * THE POSSIBILITY OF SUCH DAMAGE. 115 */ 116 117 #include <linux/module.h> 118 #include <linux/kmod.h> 119 #include <linux/mdio.h> 120 #include <linux/phy.h> 121 #include <linux/of.h> 122 #include <linux/bitops.h> 123 #include <linux/jiffies.h> 124 125 #include "xgbe.h" 126 #include "xgbe-common.h" 127 128 static void xgbe_an_enable_kr_training(struct xgbe_prv_data *pdata) 129 { 130 unsigned int reg; 131 132 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL); 133 134 reg |= XGBE_KR_TRAINING_ENABLE; 135 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg); 136 } 137 138 static void xgbe_an_disable_kr_training(struct xgbe_prv_data *pdata) 139 { 140 unsigned int reg; 141 142 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL); 143 144 reg &= ~XGBE_KR_TRAINING_ENABLE; 145 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg); 146 } 147 148 static void xgbe_pcs_power_cycle(struct xgbe_prv_data *pdata) 149 { 150 unsigned int reg; 151 152 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1); 153 154 reg |= MDIO_CTRL1_LPOWER; 155 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg); 156 157 usleep_range(75, 100); 158 159 reg &= ~MDIO_CTRL1_LPOWER; 160 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg); 161 } 162 163 static void xgbe_serdes_start_ratechange(struct xgbe_prv_data *pdata) 164 { 165 /* Assert Rx and Tx ratechange */ 166 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, RATECHANGE, 1); 167 } 168 169 static void xgbe_serdes_complete_ratechange(struct xgbe_prv_data *pdata) 170 { 171 unsigned int wait; 172 u16 status; 173 174 /* Release Rx and Tx ratechange */ 175 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, RATECHANGE, 0); 176 177 /* Wait for Rx and Tx ready */ 178 wait = XGBE_RATECHANGE_COUNT; 179 while (wait--) { 180 usleep_range(50, 75); 181 182 status = XSIR0_IOREAD(pdata, SIR0_STATUS); 183 if (XSIR_GET_BITS(status, SIR0_STATUS, RX_READY) && 184 XSIR_GET_BITS(status, SIR0_STATUS, TX_READY)) 185 goto rx_reset; 186 } 187 188 netif_dbg(pdata, link, pdata->netdev, "SerDes rx/tx not ready (%#hx)\n", 189 status); 190 191 rx_reset: 192 /* Perform Rx reset for the DFE changes */ 193 XRXTX_IOWRITE_BITS(pdata, RXTX_REG6, RESETB_RXD, 0); 194 XRXTX_IOWRITE_BITS(pdata, RXTX_REG6, RESETB_RXD, 1); 195 } 196 197 static void xgbe_xgmii_mode(struct xgbe_prv_data *pdata) 198 { 199 unsigned int reg; 200 201 /* Enable KR training */ 202 xgbe_an_enable_kr_training(pdata); 203 204 /* Set MAC to 10G speed */ 205 pdata->hw_if.set_xgmii_speed(pdata); 206 207 /* Set PCS to KR/10G speed */ 208 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2); 209 reg &= ~MDIO_PCS_CTRL2_TYPE; 210 reg |= MDIO_PCS_CTRL2_10GBR; 211 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL2, reg); 212 213 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1); 214 reg &= ~MDIO_CTRL1_SPEEDSEL; 215 reg |= MDIO_CTRL1_SPEED10G; 216 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg); 217 218 xgbe_pcs_power_cycle(pdata); 219 220 /* Set SerDes to 10G speed */ 221 xgbe_serdes_start_ratechange(pdata); 222 223 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, DATARATE, XGBE_SPEED_10000_RATE); 224 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, WORDMODE, XGBE_SPEED_10000_WORD); 225 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, PLLSEL, XGBE_SPEED_10000_PLL); 226 227 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, CDR_RATE, 228 pdata->serdes_cdr_rate[XGBE_SPEED_10000]); 229 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, TXAMP, 230 pdata->serdes_tx_amp[XGBE_SPEED_10000]); 231 XRXTX_IOWRITE_BITS(pdata, RXTX_REG20, BLWC_ENA, 232 pdata->serdes_blwc[XGBE_SPEED_10000]); 233 XRXTX_IOWRITE_BITS(pdata, RXTX_REG114, PQ_REG, 234 pdata->serdes_pq_skew[XGBE_SPEED_10000]); 235 XRXTX_IOWRITE_BITS(pdata, RXTX_REG129, RXDFE_CONFIG, 236 pdata->serdes_dfe_tap_cfg[XGBE_SPEED_10000]); 237 XRXTX_IOWRITE(pdata, RXTX_REG22, 238 pdata->serdes_dfe_tap_ena[XGBE_SPEED_10000]); 239 240 xgbe_serdes_complete_ratechange(pdata); 241 242 netif_dbg(pdata, link, pdata->netdev, "10GbE KR mode set\n"); 243 } 244 245 static void xgbe_gmii_2500_mode(struct xgbe_prv_data *pdata) 246 { 247 unsigned int reg; 248 249 /* Disable KR training */ 250 xgbe_an_disable_kr_training(pdata); 251 252 /* Set MAC to 2.5G speed */ 253 pdata->hw_if.set_gmii_2500_speed(pdata); 254 255 /* Set PCS to KX/1G speed */ 256 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2); 257 reg &= ~MDIO_PCS_CTRL2_TYPE; 258 reg |= MDIO_PCS_CTRL2_10GBX; 259 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL2, reg); 260 261 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1); 262 reg &= ~MDIO_CTRL1_SPEEDSEL; 263 reg |= MDIO_CTRL1_SPEED1G; 264 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg); 265 266 xgbe_pcs_power_cycle(pdata); 267 268 /* Set SerDes to 2.5G speed */ 269 xgbe_serdes_start_ratechange(pdata); 270 271 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, DATARATE, XGBE_SPEED_2500_RATE); 272 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, WORDMODE, XGBE_SPEED_2500_WORD); 273 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, PLLSEL, XGBE_SPEED_2500_PLL); 274 275 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, CDR_RATE, 276 pdata->serdes_cdr_rate[XGBE_SPEED_2500]); 277 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, TXAMP, 278 pdata->serdes_tx_amp[XGBE_SPEED_2500]); 279 XRXTX_IOWRITE_BITS(pdata, RXTX_REG20, BLWC_ENA, 280 pdata->serdes_blwc[XGBE_SPEED_2500]); 281 XRXTX_IOWRITE_BITS(pdata, RXTX_REG114, PQ_REG, 282 pdata->serdes_pq_skew[XGBE_SPEED_2500]); 283 XRXTX_IOWRITE_BITS(pdata, RXTX_REG129, RXDFE_CONFIG, 284 pdata->serdes_dfe_tap_cfg[XGBE_SPEED_2500]); 285 XRXTX_IOWRITE(pdata, RXTX_REG22, 286 pdata->serdes_dfe_tap_ena[XGBE_SPEED_2500]); 287 288 xgbe_serdes_complete_ratechange(pdata); 289 290 netif_dbg(pdata, link, pdata->netdev, "2.5GbE KX mode set\n"); 291 } 292 293 static void xgbe_gmii_mode(struct xgbe_prv_data *pdata) 294 { 295 unsigned int reg; 296 297 /* Disable KR training */ 298 xgbe_an_disable_kr_training(pdata); 299 300 /* Set MAC to 1G speed */ 301 pdata->hw_if.set_gmii_speed(pdata); 302 303 /* Set PCS to KX/1G speed */ 304 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2); 305 reg &= ~MDIO_PCS_CTRL2_TYPE; 306 reg |= MDIO_PCS_CTRL2_10GBX; 307 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL2, reg); 308 309 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1); 310 reg &= ~MDIO_CTRL1_SPEEDSEL; 311 reg |= MDIO_CTRL1_SPEED1G; 312 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg); 313 314 xgbe_pcs_power_cycle(pdata); 315 316 /* Set SerDes to 1G speed */ 317 xgbe_serdes_start_ratechange(pdata); 318 319 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, DATARATE, XGBE_SPEED_1000_RATE); 320 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, WORDMODE, XGBE_SPEED_1000_WORD); 321 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, PLLSEL, XGBE_SPEED_1000_PLL); 322 323 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, CDR_RATE, 324 pdata->serdes_cdr_rate[XGBE_SPEED_1000]); 325 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, TXAMP, 326 pdata->serdes_tx_amp[XGBE_SPEED_1000]); 327 XRXTX_IOWRITE_BITS(pdata, RXTX_REG20, BLWC_ENA, 328 pdata->serdes_blwc[XGBE_SPEED_1000]); 329 XRXTX_IOWRITE_BITS(pdata, RXTX_REG114, PQ_REG, 330 pdata->serdes_pq_skew[XGBE_SPEED_1000]); 331 XRXTX_IOWRITE_BITS(pdata, RXTX_REG129, RXDFE_CONFIG, 332 pdata->serdes_dfe_tap_cfg[XGBE_SPEED_1000]); 333 XRXTX_IOWRITE(pdata, RXTX_REG22, 334 pdata->serdes_dfe_tap_ena[XGBE_SPEED_1000]); 335 336 xgbe_serdes_complete_ratechange(pdata); 337 338 netif_dbg(pdata, link, pdata->netdev, "1GbE KX mode set\n"); 339 } 340 341 static void xgbe_cur_mode(struct xgbe_prv_data *pdata, 342 enum xgbe_mode *mode) 343 { 344 unsigned int reg; 345 346 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2); 347 if ((reg & MDIO_PCS_CTRL2_TYPE) == MDIO_PCS_CTRL2_10GBR) 348 *mode = XGBE_MODE_KR; 349 else 350 *mode = XGBE_MODE_KX; 351 } 352 353 static bool xgbe_in_kr_mode(struct xgbe_prv_data *pdata) 354 { 355 enum xgbe_mode mode; 356 357 xgbe_cur_mode(pdata, &mode); 358 359 return (mode == XGBE_MODE_KR); 360 } 361 362 static void xgbe_switch_mode(struct xgbe_prv_data *pdata) 363 { 364 /* If we are in KR switch to KX, and vice-versa */ 365 if (xgbe_in_kr_mode(pdata)) { 366 if (pdata->speed_set == XGBE_SPEEDSET_1000_10000) 367 xgbe_gmii_mode(pdata); 368 else 369 xgbe_gmii_2500_mode(pdata); 370 } else { 371 xgbe_xgmii_mode(pdata); 372 } 373 } 374 375 static void xgbe_set_mode(struct xgbe_prv_data *pdata, 376 enum xgbe_mode mode) 377 { 378 enum xgbe_mode cur_mode; 379 380 xgbe_cur_mode(pdata, &cur_mode); 381 if (mode != cur_mode) 382 xgbe_switch_mode(pdata); 383 } 384 385 static bool xgbe_use_xgmii_mode(struct xgbe_prv_data *pdata) 386 { 387 if (pdata->phy.autoneg == AUTONEG_ENABLE) { 388 if (pdata->phy.advertising & ADVERTISED_10000baseKR_Full) 389 return true; 390 } else { 391 if (pdata->phy.speed == SPEED_10000) 392 return true; 393 } 394 395 return false; 396 } 397 398 static bool xgbe_use_gmii_2500_mode(struct xgbe_prv_data *pdata) 399 { 400 if (pdata->phy.autoneg == AUTONEG_ENABLE) { 401 if (pdata->phy.advertising & ADVERTISED_2500baseX_Full) 402 return true; 403 } else { 404 if (pdata->phy.speed == SPEED_2500) 405 return true; 406 } 407 408 return false; 409 } 410 411 static bool xgbe_use_gmii_mode(struct xgbe_prv_data *pdata) 412 { 413 if (pdata->phy.autoneg == AUTONEG_ENABLE) { 414 if (pdata->phy.advertising & ADVERTISED_1000baseKX_Full) 415 return true; 416 } else { 417 if (pdata->phy.speed == SPEED_1000) 418 return true; 419 } 420 421 return false; 422 } 423 424 static void xgbe_set_an(struct xgbe_prv_data *pdata, bool enable, bool restart) 425 { 426 unsigned int reg; 427 428 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1); 429 reg &= ~MDIO_AN_CTRL1_ENABLE; 430 431 if (enable) 432 reg |= MDIO_AN_CTRL1_ENABLE; 433 434 if (restart) 435 reg |= MDIO_AN_CTRL1_RESTART; 436 437 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_CTRL1, reg); 438 } 439 440 static void xgbe_restart_an(struct xgbe_prv_data *pdata) 441 { 442 xgbe_set_an(pdata, true, true); 443 444 netif_dbg(pdata, link, pdata->netdev, "AN enabled/restarted\n"); 445 } 446 447 static void xgbe_disable_an(struct xgbe_prv_data *pdata) 448 { 449 xgbe_set_an(pdata, false, false); 450 451 netif_dbg(pdata, link, pdata->netdev, "AN disabled\n"); 452 } 453 454 static enum xgbe_an xgbe_an_tx_training(struct xgbe_prv_data *pdata, 455 enum xgbe_rx *state) 456 { 457 unsigned int ad_reg, lp_reg, reg; 458 459 *state = XGBE_RX_COMPLETE; 460 461 /* If we're not in KR mode then we're done */ 462 if (!xgbe_in_kr_mode(pdata)) 463 return XGBE_AN_PAGE_RECEIVED; 464 465 /* Enable/Disable FEC */ 466 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); 467 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); 468 469 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL); 470 reg &= ~(MDIO_PMA_10GBR_FECABLE_ABLE | MDIO_PMA_10GBR_FECABLE_ERRABLE); 471 if ((ad_reg & 0xc000) && (lp_reg & 0xc000)) 472 reg |= pdata->fec_ability; 473 474 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL, reg); 475 476 /* Start KR training */ 477 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL); 478 if (reg & XGBE_KR_TRAINING_ENABLE) { 479 XSIR0_IOWRITE_BITS(pdata, SIR0_KR_RT_1, RESET, 1); 480 481 reg |= XGBE_KR_TRAINING_START; 482 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, 483 reg); 484 485 XSIR0_IOWRITE_BITS(pdata, SIR0_KR_RT_1, RESET, 0); 486 487 netif_dbg(pdata, link, pdata->netdev, 488 "KR training initiated\n"); 489 } 490 491 return XGBE_AN_PAGE_RECEIVED; 492 } 493 494 static enum xgbe_an xgbe_an_tx_xnp(struct xgbe_prv_data *pdata, 495 enum xgbe_rx *state) 496 { 497 u16 msg; 498 499 *state = XGBE_RX_XNP; 500 501 msg = XGBE_XNP_MCF_NULL_MESSAGE; 502 msg |= XGBE_XNP_MP_FORMATTED; 503 504 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 2, 0); 505 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 1, 0); 506 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP, msg); 507 508 return XGBE_AN_PAGE_RECEIVED; 509 } 510 511 static enum xgbe_an xgbe_an_rx_bpa(struct xgbe_prv_data *pdata, 512 enum xgbe_rx *state) 513 { 514 unsigned int link_support; 515 unsigned int reg, ad_reg, lp_reg; 516 517 /* Read Base Ability register 2 first */ 518 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); 519 520 /* Check for a supported mode, otherwise restart in a different one */ 521 link_support = xgbe_in_kr_mode(pdata) ? 0x80 : 0x20; 522 if (!(reg & link_support)) 523 return XGBE_AN_INCOMPAT_LINK; 524 525 /* Check Extended Next Page support */ 526 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE); 527 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA); 528 529 return ((ad_reg & XGBE_XNP_NP_EXCHANGE) || 530 (lp_reg & XGBE_XNP_NP_EXCHANGE)) 531 ? xgbe_an_tx_xnp(pdata, state) 532 : xgbe_an_tx_training(pdata, state); 533 } 534 535 static enum xgbe_an xgbe_an_rx_xnp(struct xgbe_prv_data *pdata, 536 enum xgbe_rx *state) 537 { 538 unsigned int ad_reg, lp_reg; 539 540 /* Check Extended Next Page support */ 541 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_XNP); 542 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPX); 543 544 return ((ad_reg & XGBE_XNP_NP_EXCHANGE) || 545 (lp_reg & XGBE_XNP_NP_EXCHANGE)) 546 ? xgbe_an_tx_xnp(pdata, state) 547 : xgbe_an_tx_training(pdata, state); 548 } 549 550 static enum xgbe_an xgbe_an_page_received(struct xgbe_prv_data *pdata) 551 { 552 enum xgbe_rx *state; 553 unsigned long an_timeout; 554 enum xgbe_an ret; 555 556 if (!pdata->an_start) { 557 pdata->an_start = jiffies; 558 } else { 559 an_timeout = pdata->an_start + 560 msecs_to_jiffies(XGBE_AN_MS_TIMEOUT); 561 if (time_after(jiffies, an_timeout)) { 562 /* Auto-negotiation timed out, reset state */ 563 pdata->kr_state = XGBE_RX_BPA; 564 pdata->kx_state = XGBE_RX_BPA; 565 566 pdata->an_start = jiffies; 567 568 netif_dbg(pdata, link, pdata->netdev, 569 "AN timed out, resetting state\n"); 570 } 571 } 572 573 state = xgbe_in_kr_mode(pdata) ? &pdata->kr_state 574 : &pdata->kx_state; 575 576 switch (*state) { 577 case XGBE_RX_BPA: 578 ret = xgbe_an_rx_bpa(pdata, state); 579 break; 580 581 case XGBE_RX_XNP: 582 ret = xgbe_an_rx_xnp(pdata, state); 583 break; 584 585 default: 586 ret = XGBE_AN_ERROR; 587 } 588 589 return ret; 590 } 591 592 static enum xgbe_an xgbe_an_incompat_link(struct xgbe_prv_data *pdata) 593 { 594 /* Be sure we aren't looping trying to negotiate */ 595 if (xgbe_in_kr_mode(pdata)) { 596 pdata->kr_state = XGBE_RX_ERROR; 597 598 if (!(pdata->phy.advertising & ADVERTISED_1000baseKX_Full) && 599 !(pdata->phy.advertising & ADVERTISED_2500baseX_Full)) 600 return XGBE_AN_NO_LINK; 601 602 if (pdata->kx_state != XGBE_RX_BPA) 603 return XGBE_AN_NO_LINK; 604 } else { 605 pdata->kx_state = XGBE_RX_ERROR; 606 607 if (!(pdata->phy.advertising & ADVERTISED_10000baseKR_Full)) 608 return XGBE_AN_NO_LINK; 609 610 if (pdata->kr_state != XGBE_RX_BPA) 611 return XGBE_AN_NO_LINK; 612 } 613 614 xgbe_disable_an(pdata); 615 616 xgbe_switch_mode(pdata); 617 618 xgbe_restart_an(pdata); 619 620 return XGBE_AN_INCOMPAT_LINK; 621 } 622 623 static irqreturn_t xgbe_an_isr(int irq, void *data) 624 { 625 struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data; 626 627 netif_dbg(pdata, intr, pdata->netdev, "AN interrupt received\n"); 628 629 /* Disable AN interrupts */ 630 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, 0); 631 632 /* Save the interrupt(s) that fired */ 633 pdata->an_int = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_INT); 634 635 if (pdata->an_int) { 636 /* Clear the interrupt(s) that fired and process them */ 637 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, ~pdata->an_int); 638 639 queue_work(pdata->an_workqueue, &pdata->an_irq_work); 640 } else { 641 /* Enable AN interrupts */ 642 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, 643 XGBE_AN_INT_MASK); 644 } 645 646 return IRQ_HANDLED; 647 } 648 649 static void xgbe_an_irq_work(struct work_struct *work) 650 { 651 struct xgbe_prv_data *pdata = container_of(work, 652 struct xgbe_prv_data, 653 an_irq_work); 654 655 /* Avoid a race between enabling the IRQ and exiting the work by 656 * waiting for the work to finish and then queueing it 657 */ 658 flush_work(&pdata->an_work); 659 queue_work(pdata->an_workqueue, &pdata->an_work); 660 } 661 662 static const char *xgbe_state_as_string(enum xgbe_an state) 663 { 664 switch (state) { 665 case XGBE_AN_READY: 666 return "Ready"; 667 case XGBE_AN_PAGE_RECEIVED: 668 return "Page-Received"; 669 case XGBE_AN_INCOMPAT_LINK: 670 return "Incompatible-Link"; 671 case XGBE_AN_COMPLETE: 672 return "Complete"; 673 case XGBE_AN_NO_LINK: 674 return "No-Link"; 675 case XGBE_AN_ERROR: 676 return "Error"; 677 default: 678 return "Undefined"; 679 } 680 } 681 682 static void xgbe_an_state_machine(struct work_struct *work) 683 { 684 struct xgbe_prv_data *pdata = container_of(work, 685 struct xgbe_prv_data, 686 an_work); 687 enum xgbe_an cur_state = pdata->an_state; 688 689 mutex_lock(&pdata->an_mutex); 690 691 if (!pdata->an_int) 692 goto out; 693 694 next_int: 695 if (pdata->an_int & XGBE_AN_PG_RCV) { 696 pdata->an_state = XGBE_AN_PAGE_RECEIVED; 697 pdata->an_int &= ~XGBE_AN_PG_RCV; 698 } else if (pdata->an_int & XGBE_AN_INC_LINK) { 699 pdata->an_state = XGBE_AN_INCOMPAT_LINK; 700 pdata->an_int &= ~XGBE_AN_INC_LINK; 701 } else if (pdata->an_int & XGBE_AN_INT_CMPLT) { 702 pdata->an_state = XGBE_AN_COMPLETE; 703 pdata->an_int &= ~XGBE_AN_INT_CMPLT; 704 } else { 705 pdata->an_state = XGBE_AN_ERROR; 706 } 707 708 pdata->an_result = pdata->an_state; 709 710 again: 711 netif_dbg(pdata, link, pdata->netdev, "AN %s\n", 712 xgbe_state_as_string(pdata->an_state)); 713 714 cur_state = pdata->an_state; 715 716 switch (pdata->an_state) { 717 case XGBE_AN_READY: 718 pdata->an_supported = 0; 719 break; 720 721 case XGBE_AN_PAGE_RECEIVED: 722 pdata->an_state = xgbe_an_page_received(pdata); 723 pdata->an_supported++; 724 break; 725 726 case XGBE_AN_INCOMPAT_LINK: 727 pdata->an_supported = 0; 728 pdata->parallel_detect = 0; 729 pdata->an_state = xgbe_an_incompat_link(pdata); 730 break; 731 732 case XGBE_AN_COMPLETE: 733 pdata->parallel_detect = pdata->an_supported ? 0 : 1; 734 netif_dbg(pdata, link, pdata->netdev, "%s successful\n", 735 pdata->an_supported ? "Auto negotiation" 736 : "Parallel detection"); 737 break; 738 739 case XGBE_AN_NO_LINK: 740 break; 741 742 default: 743 pdata->an_state = XGBE_AN_ERROR; 744 } 745 746 if (pdata->an_state == XGBE_AN_NO_LINK) { 747 pdata->an_int = 0; 748 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0); 749 } else if (pdata->an_state == XGBE_AN_ERROR) { 750 netdev_err(pdata->netdev, 751 "error during auto-negotiation, state=%u\n", 752 cur_state); 753 754 pdata->an_int = 0; 755 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0); 756 } 757 758 if (pdata->an_state >= XGBE_AN_COMPLETE) { 759 pdata->an_result = pdata->an_state; 760 pdata->an_state = XGBE_AN_READY; 761 pdata->kr_state = XGBE_RX_BPA; 762 pdata->kx_state = XGBE_RX_BPA; 763 pdata->an_start = 0; 764 765 netif_dbg(pdata, link, pdata->netdev, "AN result: %s\n", 766 xgbe_state_as_string(pdata->an_result)); 767 } 768 769 if (cur_state != pdata->an_state) 770 goto again; 771 772 if (pdata->an_int) 773 goto next_int; 774 775 out: 776 /* Enable AN interrupts on the way out */ 777 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, XGBE_AN_INT_MASK); 778 779 mutex_unlock(&pdata->an_mutex); 780 } 781 782 static void xgbe_an_init(struct xgbe_prv_data *pdata) 783 { 784 unsigned int reg; 785 786 /* Set up Advertisement register 3 first */ 787 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); 788 if (pdata->phy.advertising & ADVERTISED_10000baseR_FEC) 789 reg |= 0xc000; 790 else 791 reg &= ~0xc000; 792 793 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2, reg); 794 795 /* Set up Advertisement register 2 next */ 796 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); 797 if (pdata->phy.advertising & ADVERTISED_10000baseKR_Full) 798 reg |= 0x80; 799 else 800 reg &= ~0x80; 801 802 if ((pdata->phy.advertising & ADVERTISED_1000baseKX_Full) || 803 (pdata->phy.advertising & ADVERTISED_2500baseX_Full)) 804 reg |= 0x20; 805 else 806 reg &= ~0x20; 807 808 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1, reg); 809 810 /* Set up Advertisement register 1 last */ 811 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE); 812 if (pdata->phy.advertising & ADVERTISED_Pause) 813 reg |= 0x400; 814 else 815 reg &= ~0x400; 816 817 if (pdata->phy.advertising & ADVERTISED_Asym_Pause) 818 reg |= 0x800; 819 else 820 reg &= ~0x800; 821 822 /* We don't intend to perform XNP */ 823 reg &= ~XGBE_XNP_NP_EXCHANGE; 824 825 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE, reg); 826 827 netif_dbg(pdata, link, pdata->netdev, "AN initialized\n"); 828 } 829 830 static const char *xgbe_phy_fc_string(struct xgbe_prv_data *pdata) 831 { 832 if (pdata->tx_pause && pdata->rx_pause) 833 return "rx/tx"; 834 else if (pdata->rx_pause) 835 return "rx"; 836 else if (pdata->tx_pause) 837 return "tx"; 838 else 839 return "off"; 840 } 841 842 static const char *xgbe_phy_speed_string(int speed) 843 { 844 switch (speed) { 845 case SPEED_1000: 846 return "1Gbps"; 847 case SPEED_2500: 848 return "2.5Gbps"; 849 case SPEED_10000: 850 return "10Gbps"; 851 case SPEED_UNKNOWN: 852 return "Unknown"; 853 default: 854 return "Unsupported"; 855 } 856 } 857 858 static void xgbe_phy_print_status(struct xgbe_prv_data *pdata) 859 { 860 if (pdata->phy.link) 861 netdev_info(pdata->netdev, 862 "Link is Up - %s/%s - flow control %s\n", 863 xgbe_phy_speed_string(pdata->phy.speed), 864 pdata->phy.duplex == DUPLEX_FULL ? "Full" : "Half", 865 xgbe_phy_fc_string(pdata)); 866 else 867 netdev_info(pdata->netdev, "Link is Down\n"); 868 } 869 870 static void xgbe_phy_adjust_link(struct xgbe_prv_data *pdata) 871 { 872 int new_state = 0; 873 874 if (pdata->phy.link) { 875 /* Flow control support */ 876 pdata->pause_autoneg = pdata->phy.pause_autoneg; 877 878 if (pdata->tx_pause != pdata->phy.tx_pause) { 879 new_state = 1; 880 pdata->hw_if.config_tx_flow_control(pdata); 881 pdata->tx_pause = pdata->phy.tx_pause; 882 } 883 884 if (pdata->rx_pause != pdata->phy.rx_pause) { 885 new_state = 1; 886 pdata->hw_if.config_rx_flow_control(pdata); 887 pdata->rx_pause = pdata->phy.rx_pause; 888 } 889 890 /* Speed support */ 891 if (pdata->phy_speed != pdata->phy.speed) { 892 new_state = 1; 893 pdata->phy_speed = pdata->phy.speed; 894 } 895 896 if (pdata->phy_link != pdata->phy.link) { 897 new_state = 1; 898 pdata->phy_link = pdata->phy.link; 899 } 900 } else if (pdata->phy_link) { 901 new_state = 1; 902 pdata->phy_link = 0; 903 pdata->phy_speed = SPEED_UNKNOWN; 904 } 905 906 if (new_state && netif_msg_link(pdata)) 907 xgbe_phy_print_status(pdata); 908 } 909 910 static int xgbe_phy_config_fixed(struct xgbe_prv_data *pdata) 911 { 912 netif_dbg(pdata, link, pdata->netdev, "fixed PHY configuration\n"); 913 914 /* Disable auto-negotiation */ 915 xgbe_disable_an(pdata); 916 917 /* Validate/Set specified speed */ 918 switch (pdata->phy.speed) { 919 case SPEED_10000: 920 xgbe_set_mode(pdata, XGBE_MODE_KR); 921 break; 922 923 case SPEED_2500: 924 case SPEED_1000: 925 xgbe_set_mode(pdata, XGBE_MODE_KX); 926 break; 927 928 default: 929 return -EINVAL; 930 } 931 932 /* Validate duplex mode */ 933 if (pdata->phy.duplex != DUPLEX_FULL) 934 return -EINVAL; 935 936 return 0; 937 } 938 939 static int __xgbe_phy_config_aneg(struct xgbe_prv_data *pdata) 940 { 941 set_bit(XGBE_LINK_INIT, &pdata->dev_state); 942 pdata->link_check = jiffies; 943 944 if (pdata->phy.autoneg != AUTONEG_ENABLE) 945 return xgbe_phy_config_fixed(pdata); 946 947 netif_dbg(pdata, link, pdata->netdev, "AN PHY configuration\n"); 948 949 /* Disable auto-negotiation interrupt */ 950 disable_irq(pdata->an_irq); 951 952 /* Start auto-negotiation in a supported mode */ 953 if (pdata->phy.advertising & ADVERTISED_10000baseKR_Full) { 954 xgbe_set_mode(pdata, XGBE_MODE_KR); 955 } else if ((pdata->phy.advertising & ADVERTISED_1000baseKX_Full) || 956 (pdata->phy.advertising & ADVERTISED_2500baseX_Full)) { 957 xgbe_set_mode(pdata, XGBE_MODE_KX); 958 } else { 959 enable_irq(pdata->an_irq); 960 return -EINVAL; 961 } 962 963 /* Disable and stop any in progress auto-negotiation */ 964 xgbe_disable_an(pdata); 965 966 /* Clear any auto-negotitation interrupts */ 967 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0); 968 969 pdata->an_result = XGBE_AN_READY; 970 pdata->an_state = XGBE_AN_READY; 971 pdata->kr_state = XGBE_RX_BPA; 972 pdata->kx_state = XGBE_RX_BPA; 973 974 /* Re-enable auto-negotiation interrupt */ 975 enable_irq(pdata->an_irq); 976 977 /* Set up advertisement registers based on current settings */ 978 xgbe_an_init(pdata); 979 980 /* Enable and start auto-negotiation */ 981 xgbe_restart_an(pdata); 982 983 return 0; 984 } 985 986 static int xgbe_phy_config_aneg(struct xgbe_prv_data *pdata) 987 { 988 int ret; 989 990 mutex_lock(&pdata->an_mutex); 991 992 ret = __xgbe_phy_config_aneg(pdata); 993 if (ret) 994 set_bit(XGBE_LINK_ERR, &pdata->dev_state); 995 else 996 clear_bit(XGBE_LINK_ERR, &pdata->dev_state); 997 998 mutex_unlock(&pdata->an_mutex); 999 1000 return ret; 1001 } 1002 1003 static bool xgbe_phy_aneg_done(struct xgbe_prv_data *pdata) 1004 { 1005 return (pdata->an_result == XGBE_AN_COMPLETE); 1006 } 1007 1008 static void xgbe_check_link_timeout(struct xgbe_prv_data *pdata) 1009 { 1010 unsigned long link_timeout; 1011 1012 link_timeout = pdata->link_check + (XGBE_LINK_TIMEOUT * HZ); 1013 if (time_after(jiffies, link_timeout)) { 1014 netif_dbg(pdata, link, pdata->netdev, "AN link timeout\n"); 1015 xgbe_phy_config_aneg(pdata); 1016 } 1017 } 1018 1019 static void xgbe_phy_status_force(struct xgbe_prv_data *pdata) 1020 { 1021 if (xgbe_in_kr_mode(pdata)) { 1022 pdata->phy.speed = SPEED_10000; 1023 } else { 1024 switch (pdata->speed_set) { 1025 case XGBE_SPEEDSET_1000_10000: 1026 pdata->phy.speed = SPEED_1000; 1027 break; 1028 1029 case XGBE_SPEEDSET_2500_10000: 1030 pdata->phy.speed = SPEED_2500; 1031 break; 1032 } 1033 } 1034 pdata->phy.duplex = DUPLEX_FULL; 1035 } 1036 1037 static void xgbe_phy_status_aneg(struct xgbe_prv_data *pdata) 1038 { 1039 unsigned int ad_reg, lp_reg; 1040 1041 pdata->phy.lp_advertising = 0; 1042 1043 if ((pdata->phy.autoneg != AUTONEG_ENABLE) || pdata->parallel_detect) 1044 return xgbe_phy_status_force(pdata); 1045 1046 pdata->phy.lp_advertising |= ADVERTISED_Autoneg; 1047 pdata->phy.lp_advertising |= ADVERTISED_Backplane; 1048 1049 /* Compare Advertisement and Link Partner register 1 */ 1050 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE); 1051 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA); 1052 if (lp_reg & 0x400) 1053 pdata->phy.lp_advertising |= ADVERTISED_Pause; 1054 if (lp_reg & 0x800) 1055 pdata->phy.lp_advertising |= ADVERTISED_Asym_Pause; 1056 1057 if (pdata->phy.pause_autoneg) { 1058 /* Set flow control based on auto-negotiation result */ 1059 pdata->phy.tx_pause = 0; 1060 pdata->phy.rx_pause = 0; 1061 1062 if (ad_reg & lp_reg & 0x400) { 1063 pdata->phy.tx_pause = 1; 1064 pdata->phy.rx_pause = 1; 1065 } else if (ad_reg & lp_reg & 0x800) { 1066 if (ad_reg & 0x400) 1067 pdata->phy.rx_pause = 1; 1068 else if (lp_reg & 0x400) 1069 pdata->phy.tx_pause = 1; 1070 } 1071 } 1072 1073 /* Compare Advertisement and Link Partner register 2 */ 1074 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); 1075 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); 1076 if (lp_reg & 0x80) 1077 pdata->phy.lp_advertising |= ADVERTISED_10000baseKR_Full; 1078 if (lp_reg & 0x20) { 1079 switch (pdata->speed_set) { 1080 case XGBE_SPEEDSET_1000_10000: 1081 pdata->phy.lp_advertising |= ADVERTISED_1000baseKX_Full; 1082 break; 1083 case XGBE_SPEEDSET_2500_10000: 1084 pdata->phy.lp_advertising |= ADVERTISED_2500baseX_Full; 1085 break; 1086 } 1087 } 1088 1089 ad_reg &= lp_reg; 1090 if (ad_reg & 0x80) { 1091 pdata->phy.speed = SPEED_10000; 1092 xgbe_set_mode(pdata, XGBE_MODE_KR); 1093 } else if (ad_reg & 0x20) { 1094 switch (pdata->speed_set) { 1095 case XGBE_SPEEDSET_1000_10000: 1096 pdata->phy.speed = SPEED_1000; 1097 break; 1098 1099 case XGBE_SPEEDSET_2500_10000: 1100 pdata->phy.speed = SPEED_2500; 1101 break; 1102 } 1103 1104 xgbe_set_mode(pdata, XGBE_MODE_KX); 1105 } else { 1106 pdata->phy.speed = SPEED_UNKNOWN; 1107 } 1108 1109 /* Compare Advertisement and Link Partner register 3 */ 1110 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); 1111 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); 1112 if (lp_reg & 0xc000) 1113 pdata->phy.lp_advertising |= ADVERTISED_10000baseR_FEC; 1114 1115 pdata->phy.duplex = DUPLEX_FULL; 1116 } 1117 1118 static void xgbe_phy_status(struct xgbe_prv_data *pdata) 1119 { 1120 unsigned int reg, link_aneg; 1121 1122 if (test_bit(XGBE_LINK_ERR, &pdata->dev_state)) { 1123 netif_carrier_off(pdata->netdev); 1124 1125 pdata->phy.link = 0; 1126 goto adjust_link; 1127 } 1128 1129 link_aneg = (pdata->phy.autoneg == AUTONEG_ENABLE); 1130 1131 /* Get the link status. Link status is latched low, so read 1132 * once to clear and then read again to get current state 1133 */ 1134 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); 1135 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); 1136 pdata->phy.link = (reg & MDIO_STAT1_LSTATUS) ? 1 : 0; 1137 1138 if (pdata->phy.link) { 1139 if (link_aneg && !xgbe_phy_aneg_done(pdata)) { 1140 xgbe_check_link_timeout(pdata); 1141 return; 1142 } 1143 1144 xgbe_phy_status_aneg(pdata); 1145 1146 if (test_bit(XGBE_LINK_INIT, &pdata->dev_state)) 1147 clear_bit(XGBE_LINK_INIT, &pdata->dev_state); 1148 1149 netif_carrier_on(pdata->netdev); 1150 } else { 1151 if (test_bit(XGBE_LINK_INIT, &pdata->dev_state)) { 1152 xgbe_check_link_timeout(pdata); 1153 1154 if (link_aneg) 1155 return; 1156 } 1157 1158 xgbe_phy_status_aneg(pdata); 1159 1160 netif_carrier_off(pdata->netdev); 1161 } 1162 1163 adjust_link: 1164 xgbe_phy_adjust_link(pdata); 1165 } 1166 1167 static void xgbe_phy_stop(struct xgbe_prv_data *pdata) 1168 { 1169 netif_dbg(pdata, link, pdata->netdev, "stopping PHY\n"); 1170 1171 /* Disable auto-negotiation */ 1172 xgbe_disable_an(pdata); 1173 1174 /* Disable auto-negotiation interrupts */ 1175 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, 0); 1176 1177 devm_free_irq(pdata->dev, pdata->an_irq, pdata); 1178 1179 pdata->phy.link = 0; 1180 netif_carrier_off(pdata->netdev); 1181 1182 xgbe_phy_adjust_link(pdata); 1183 } 1184 1185 static int xgbe_phy_start(struct xgbe_prv_data *pdata) 1186 { 1187 struct net_device *netdev = pdata->netdev; 1188 int ret; 1189 1190 netif_dbg(pdata, link, pdata->netdev, "starting PHY\n"); 1191 1192 ret = devm_request_irq(pdata->dev, pdata->an_irq, 1193 xgbe_an_isr, 0, pdata->an_name, 1194 pdata); 1195 if (ret) { 1196 netdev_err(netdev, "phy irq request failed\n"); 1197 return ret; 1198 } 1199 1200 /* Set initial mode - call the mode setting routines 1201 * directly to insure we are properly configured 1202 */ 1203 if (xgbe_use_xgmii_mode(pdata)) { 1204 xgbe_xgmii_mode(pdata); 1205 } else if (xgbe_use_gmii_mode(pdata)) { 1206 xgbe_gmii_mode(pdata); 1207 } else if (xgbe_use_gmii_2500_mode(pdata)) { 1208 xgbe_gmii_2500_mode(pdata); 1209 } else { 1210 ret = -EINVAL; 1211 goto err_irq; 1212 } 1213 1214 /* Set up advertisement registers based on current settings */ 1215 xgbe_an_init(pdata); 1216 1217 /* Enable auto-negotiation interrupts */ 1218 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, 0x07); 1219 1220 return xgbe_phy_config_aneg(pdata); 1221 1222 err_irq: 1223 devm_free_irq(pdata->dev, pdata->an_irq, pdata); 1224 1225 return ret; 1226 } 1227 1228 static int xgbe_phy_reset(struct xgbe_prv_data *pdata) 1229 { 1230 unsigned int count, reg; 1231 1232 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1); 1233 reg |= MDIO_CTRL1_RESET; 1234 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg); 1235 1236 count = 50; 1237 do { 1238 msleep(20); 1239 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1); 1240 } while ((reg & MDIO_CTRL1_RESET) && --count); 1241 1242 if (reg & MDIO_CTRL1_RESET) 1243 return -ETIMEDOUT; 1244 1245 /* Disable auto-negotiation for now */ 1246 xgbe_disable_an(pdata); 1247 1248 /* Clear auto-negotiation interrupts */ 1249 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0); 1250 1251 return 0; 1252 } 1253 1254 static void xgbe_dump_phy_registers(struct xgbe_prv_data *pdata) 1255 { 1256 struct device *dev = pdata->dev; 1257 1258 dev_dbg(dev, "\n************* PHY Reg dump **********************\n"); 1259 1260 dev_dbg(dev, "PCS Control Reg (%#04x) = %#04x\n", MDIO_CTRL1, 1261 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1)); 1262 dev_dbg(dev, "PCS Status Reg (%#04x) = %#04x\n", MDIO_STAT1, 1263 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1)); 1264 dev_dbg(dev, "Phy Id (PHYS ID 1 %#04x)= %#04x\n", MDIO_DEVID1, 1265 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID1)); 1266 dev_dbg(dev, "Phy Id (PHYS ID 2 %#04x)= %#04x\n", MDIO_DEVID2, 1267 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID2)); 1268 dev_dbg(dev, "Devices in Package (%#04x)= %#04x\n", MDIO_DEVS1, 1269 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS1)); 1270 dev_dbg(dev, "Devices in Package (%#04x)= %#04x\n", MDIO_DEVS2, 1271 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS2)); 1272 1273 dev_dbg(dev, "Auto-Neg Control Reg (%#04x) = %#04x\n", MDIO_CTRL1, 1274 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1)); 1275 dev_dbg(dev, "Auto-Neg Status Reg (%#04x) = %#04x\n", MDIO_STAT1, 1276 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_STAT1)); 1277 dev_dbg(dev, "Auto-Neg Ad Reg 1 (%#04x) = %#04x\n", 1278 MDIO_AN_ADVERTISE, 1279 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE)); 1280 dev_dbg(dev, "Auto-Neg Ad Reg 2 (%#04x) = %#04x\n", 1281 MDIO_AN_ADVERTISE + 1, 1282 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1)); 1283 dev_dbg(dev, "Auto-Neg Ad Reg 3 (%#04x) = %#04x\n", 1284 MDIO_AN_ADVERTISE + 2, 1285 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2)); 1286 dev_dbg(dev, "Auto-Neg Completion Reg (%#04x) = %#04x\n", 1287 MDIO_AN_COMP_STAT, 1288 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_COMP_STAT)); 1289 1290 dev_dbg(dev, "\n*************************************************\n"); 1291 } 1292 1293 static void xgbe_phy_init(struct xgbe_prv_data *pdata) 1294 { 1295 mutex_init(&pdata->an_mutex); 1296 INIT_WORK(&pdata->an_irq_work, xgbe_an_irq_work); 1297 INIT_WORK(&pdata->an_work, xgbe_an_state_machine); 1298 pdata->mdio_mmd = MDIO_MMD_PCS; 1299 1300 /* Initialize supported features */ 1301 pdata->phy.supported = SUPPORTED_Autoneg; 1302 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 1303 pdata->phy.supported |= SUPPORTED_Backplane; 1304 pdata->phy.supported |= SUPPORTED_10000baseKR_Full; 1305 switch (pdata->speed_set) { 1306 case XGBE_SPEEDSET_1000_10000: 1307 pdata->phy.supported |= SUPPORTED_1000baseKX_Full; 1308 break; 1309 case XGBE_SPEEDSET_2500_10000: 1310 pdata->phy.supported |= SUPPORTED_2500baseX_Full; 1311 break; 1312 } 1313 1314 pdata->fec_ability = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, 1315 MDIO_PMA_10GBR_FECABLE); 1316 pdata->fec_ability &= (MDIO_PMA_10GBR_FECABLE_ABLE | 1317 MDIO_PMA_10GBR_FECABLE_ERRABLE); 1318 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 1319 pdata->phy.supported |= SUPPORTED_10000baseR_FEC; 1320 1321 pdata->phy.advertising = pdata->phy.supported; 1322 1323 pdata->phy.address = 0; 1324 1325 pdata->phy.autoneg = AUTONEG_ENABLE; 1326 pdata->phy.speed = SPEED_UNKNOWN; 1327 pdata->phy.duplex = DUPLEX_UNKNOWN; 1328 1329 pdata->phy.link = 0; 1330 1331 pdata->phy.pause_autoneg = pdata->pause_autoneg; 1332 pdata->phy.tx_pause = pdata->tx_pause; 1333 pdata->phy.rx_pause = pdata->rx_pause; 1334 1335 /* Fix up Flow Control advertising */ 1336 pdata->phy.advertising &= ~ADVERTISED_Pause; 1337 pdata->phy.advertising &= ~ADVERTISED_Asym_Pause; 1338 1339 if (pdata->rx_pause) { 1340 pdata->phy.advertising |= ADVERTISED_Pause; 1341 pdata->phy.advertising |= ADVERTISED_Asym_Pause; 1342 } 1343 1344 if (pdata->tx_pause) 1345 pdata->phy.advertising ^= ADVERTISED_Asym_Pause; 1346 1347 if (netif_msg_drv(pdata)) 1348 xgbe_dump_phy_registers(pdata); 1349 } 1350 1351 void xgbe_init_function_ptrs_phy(struct xgbe_phy_if *phy_if) 1352 { 1353 phy_if->phy_init = xgbe_phy_init; 1354 1355 phy_if->phy_reset = xgbe_phy_reset; 1356 phy_if->phy_start = xgbe_phy_start; 1357 phy_if->phy_stop = xgbe_phy_stop; 1358 1359 phy_if->phy_status = xgbe_phy_status; 1360 phy_if->phy_config_aneg = xgbe_phy_config_aneg; 1361 } 1362