1 /* 2 * AMD 10Gb Ethernet driver 3 * 4 * This file is available to you under your choice of the following two 5 * licenses: 6 * 7 * License 1: GPLv2 8 * 9 * Copyright (c) 2016 Advanced Micro Devices, Inc. 10 * 11 * This file is free software; you may copy, redistribute and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation, either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program. If not, see <http://www.gnu.org/licenses/>. 23 * 24 * This file incorporates work covered by the following copyright and 25 * permission notice: 26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 28 * Inc. unless otherwise expressly agreed to in writing between Synopsys 29 * and you. 30 * 31 * The Software IS NOT an item of Licensed Software or Licensed Product 32 * under any End User Software License Agreement or Agreement for Licensed 33 * Product with Synopsys or any supplement thereto. Permission is hereby 34 * granted, free of charge, to any person obtaining a copy of this software 35 * annotated with this license and the Software, to deal in the Software 36 * without restriction, including without limitation the rights to use, 37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 38 * of the Software, and to permit persons to whom the Software is furnished 39 * to do so, subject to the following conditions: 40 * 41 * The above copyright notice and this permission notice shall be included 42 * in all copies or substantial portions of the Software. 43 * 44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 54 * THE POSSIBILITY OF SUCH DAMAGE. 55 * 56 * 57 * License 2: Modified BSD 58 * 59 * Copyright (c) 2016 Advanced Micro Devices, Inc. 60 * All rights reserved. 61 * 62 * Redistribution and use in source and binary forms, with or without 63 * modification, are permitted provided that the following conditions are met: 64 * * Redistributions of source code must retain the above copyright 65 * notice, this list of conditions and the following disclaimer. 66 * * Redistributions in binary form must reproduce the above copyright 67 * notice, this list of conditions and the following disclaimer in the 68 * documentation and/or other materials provided with the distribution. 69 * * Neither the name of Advanced Micro Devices, Inc. nor the 70 * names of its contributors may be used to endorse or promote products 71 * derived from this software without specific prior written permission. 72 * 73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY 77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 83 * 84 * This file incorporates work covered by the following copyright and 85 * permission notice: 86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 88 * Inc. unless otherwise expressly agreed to in writing between Synopsys 89 * and you. 90 * 91 * The Software IS NOT an item of Licensed Software or Licensed Product 92 * under any End User Software License Agreement or Agreement for Licensed 93 * Product with Synopsys or any supplement thereto. Permission is hereby 94 * granted, free of charge, to any person obtaining a copy of this software 95 * annotated with this license and the Software, to deal in the Software 96 * without restriction, including without limitation the rights to use, 97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 98 * of the Software, and to permit persons to whom the Software is furnished 99 * to do so, subject to the following conditions: 100 * 101 * The above copyright notice and this permission notice shall be included 102 * in all copies or substantial portions of the Software. 103 * 104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 114 * THE POSSIBILITY OF SUCH DAMAGE. 115 */ 116 117 #include <linux/module.h> 118 #include <linux/interrupt.h> 119 #include <linux/kmod.h> 120 #include <linux/delay.h> 121 #include <linux/completion.h> 122 #include <linux/mutex.h> 123 124 #include "xgbe.h" 125 #include "xgbe-common.h" 126 127 #define XGBE_ABORT_COUNT 500 128 #define XGBE_DISABLE_COUNT 1000 129 130 #define XGBE_STD_SPEED 1 131 132 #define XGBE_INTR_RX_FULL BIT(IC_RAW_INTR_STAT_RX_FULL_INDEX) 133 #define XGBE_INTR_TX_EMPTY BIT(IC_RAW_INTR_STAT_TX_EMPTY_INDEX) 134 #define XGBE_INTR_TX_ABRT BIT(IC_RAW_INTR_STAT_TX_ABRT_INDEX) 135 #define XGBE_INTR_STOP_DET BIT(IC_RAW_INTR_STAT_STOP_DET_INDEX) 136 #define XGBE_DEFAULT_INT_MASK (XGBE_INTR_RX_FULL | \ 137 XGBE_INTR_TX_EMPTY | \ 138 XGBE_INTR_TX_ABRT | \ 139 XGBE_INTR_STOP_DET) 140 141 #define XGBE_I2C_READ BIT(8) 142 #define XGBE_I2C_STOP BIT(9) 143 144 static int xgbe_i2c_abort(struct xgbe_prv_data *pdata) 145 { 146 unsigned int wait = XGBE_ABORT_COUNT; 147 148 /* Must be enabled to recognize the abort request */ 149 XI2C_IOWRITE_BITS(pdata, IC_ENABLE, EN, 1); 150 151 /* Issue the abort */ 152 XI2C_IOWRITE_BITS(pdata, IC_ENABLE, ABORT, 1); 153 154 while (wait--) { 155 if (!XI2C_IOREAD_BITS(pdata, IC_ENABLE, ABORT)) 156 return 0; 157 158 usleep_range(500, 600); 159 } 160 161 return -EBUSY; 162 } 163 164 static int xgbe_i2c_set_enable(struct xgbe_prv_data *pdata, bool enable) 165 { 166 unsigned int wait = XGBE_DISABLE_COUNT; 167 unsigned int mode = enable ? 1 : 0; 168 169 while (wait--) { 170 XI2C_IOWRITE_BITS(pdata, IC_ENABLE, EN, mode); 171 if (XI2C_IOREAD_BITS(pdata, IC_ENABLE_STATUS, EN) == mode) 172 return 0; 173 174 usleep_range(100, 110); 175 } 176 177 return -EBUSY; 178 } 179 180 static int xgbe_i2c_disable(struct xgbe_prv_data *pdata) 181 { 182 unsigned int ret; 183 184 ret = xgbe_i2c_set_enable(pdata, false); 185 if (ret) { 186 /* Disable failed, try an abort */ 187 ret = xgbe_i2c_abort(pdata); 188 if (ret) 189 return ret; 190 191 /* Abort succeeded, try to disable again */ 192 ret = xgbe_i2c_set_enable(pdata, false); 193 } 194 195 return ret; 196 } 197 198 static int xgbe_i2c_enable(struct xgbe_prv_data *pdata) 199 { 200 return xgbe_i2c_set_enable(pdata, true); 201 } 202 203 static void xgbe_i2c_clear_all_interrupts(struct xgbe_prv_data *pdata) 204 { 205 XI2C_IOREAD(pdata, IC_CLR_INTR); 206 } 207 208 static void xgbe_i2c_disable_interrupts(struct xgbe_prv_data *pdata) 209 { 210 XI2C_IOWRITE(pdata, IC_INTR_MASK, 0); 211 } 212 213 static void xgbe_i2c_enable_interrupts(struct xgbe_prv_data *pdata) 214 { 215 XI2C_IOWRITE(pdata, IC_INTR_MASK, XGBE_DEFAULT_INT_MASK); 216 } 217 218 static void xgbe_i2c_write(struct xgbe_prv_data *pdata) 219 { 220 struct xgbe_i2c_op_state *state = &pdata->i2c.op_state; 221 unsigned int tx_slots; 222 unsigned int cmd; 223 224 /* Configured to never receive Rx overflows, so fill up Tx fifo */ 225 tx_slots = pdata->i2c.tx_fifo_size - XI2C_IOREAD(pdata, IC_TXFLR); 226 while (tx_slots && state->tx_len) { 227 if (state->op->cmd == XGBE_I2C_CMD_READ) 228 cmd = XGBE_I2C_READ; 229 else 230 cmd = *state->tx_buf++; 231 232 if (state->tx_len == 1) 233 XI2C_SET_BITS(cmd, IC_DATA_CMD, STOP, 1); 234 235 XI2C_IOWRITE(pdata, IC_DATA_CMD, cmd); 236 237 tx_slots--; 238 state->tx_len--; 239 } 240 241 /* No more Tx operations, so ignore TX_EMPTY and return */ 242 if (!state->tx_len) 243 XI2C_IOWRITE_BITS(pdata, IC_INTR_MASK, TX_EMPTY, 0); 244 } 245 246 static void xgbe_i2c_read(struct xgbe_prv_data *pdata) 247 { 248 struct xgbe_i2c_op_state *state = &pdata->i2c.op_state; 249 unsigned int rx_slots; 250 251 /* Anything to be read? */ 252 if (state->op->cmd != XGBE_I2C_CMD_READ) 253 return; 254 255 rx_slots = XI2C_IOREAD(pdata, IC_RXFLR); 256 while (rx_slots && state->rx_len) { 257 *state->rx_buf++ = XI2C_IOREAD(pdata, IC_DATA_CMD); 258 state->rx_len--; 259 rx_slots--; 260 } 261 } 262 263 static void xgbe_i2c_clear_isr_interrupts(struct xgbe_prv_data *pdata, 264 unsigned int isr) 265 { 266 struct xgbe_i2c_op_state *state = &pdata->i2c.op_state; 267 268 if (isr & XGBE_INTR_TX_ABRT) { 269 state->tx_abort_source = XI2C_IOREAD(pdata, IC_TX_ABRT_SOURCE); 270 XI2C_IOREAD(pdata, IC_CLR_TX_ABRT); 271 } 272 273 if (isr & XGBE_INTR_STOP_DET) 274 XI2C_IOREAD(pdata, IC_CLR_STOP_DET); 275 } 276 277 static irqreturn_t xgbe_i2c_isr(int irq, void *data) 278 { 279 struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data; 280 struct xgbe_i2c_op_state *state = &pdata->i2c.op_state; 281 unsigned int isr; 282 283 isr = XI2C_IOREAD(pdata, IC_RAW_INTR_STAT); 284 netif_dbg(pdata, intr, pdata->netdev, 285 "I2C interrupt received: status=%#010x\n", isr); 286 287 xgbe_i2c_clear_isr_interrupts(pdata, isr); 288 289 if (isr & XGBE_INTR_TX_ABRT) { 290 netif_dbg(pdata, link, pdata->netdev, 291 "I2C TX_ABRT received (%#010x) for target %#04x\n", 292 state->tx_abort_source, state->op->target); 293 294 xgbe_i2c_disable_interrupts(pdata); 295 296 state->ret = -EIO; 297 goto out; 298 } 299 300 /* Check for data in the Rx fifo */ 301 xgbe_i2c_read(pdata); 302 303 /* Fill up the Tx fifo next */ 304 xgbe_i2c_write(pdata); 305 306 out: 307 /* Complete on an error or STOP condition */ 308 if (state->ret || XI2C_GET_BITS(isr, IC_RAW_INTR_STAT, STOP_DET)) 309 complete(&pdata->i2c_complete); 310 311 return IRQ_HANDLED; 312 } 313 314 static void xgbe_i2c_set_mode(struct xgbe_prv_data *pdata) 315 { 316 unsigned int reg; 317 318 reg = XI2C_IOREAD(pdata, IC_CON); 319 XI2C_SET_BITS(reg, IC_CON, MASTER_MODE, 1); 320 XI2C_SET_BITS(reg, IC_CON, SLAVE_DISABLE, 1); 321 XI2C_SET_BITS(reg, IC_CON, RESTART_EN, 1); 322 XI2C_SET_BITS(reg, IC_CON, SPEED, XGBE_STD_SPEED); 323 XI2C_SET_BITS(reg, IC_CON, RX_FIFO_FULL_HOLD, 1); 324 XI2C_IOWRITE(pdata, IC_CON, reg); 325 } 326 327 static void xgbe_i2c_get_features(struct xgbe_prv_data *pdata) 328 { 329 struct xgbe_i2c *i2c = &pdata->i2c; 330 unsigned int reg; 331 332 reg = XI2C_IOREAD(pdata, IC_COMP_PARAM_1); 333 i2c->max_speed_mode = XI2C_GET_BITS(reg, IC_COMP_PARAM_1, 334 MAX_SPEED_MODE); 335 i2c->rx_fifo_size = XI2C_GET_BITS(reg, IC_COMP_PARAM_1, 336 RX_BUFFER_DEPTH); 337 i2c->tx_fifo_size = XI2C_GET_BITS(reg, IC_COMP_PARAM_1, 338 TX_BUFFER_DEPTH); 339 340 if (netif_msg_probe(pdata)) 341 dev_dbg(pdata->dev, "I2C features: %s=%u, %s=%u, %s=%u\n", 342 "MAX_SPEED_MODE", i2c->max_speed_mode, 343 "RX_BUFFER_DEPTH", i2c->rx_fifo_size, 344 "TX_BUFFER_DEPTH", i2c->tx_fifo_size); 345 } 346 347 static void xgbe_i2c_set_target(struct xgbe_prv_data *pdata, unsigned int addr) 348 { 349 XI2C_IOWRITE(pdata, IC_TAR, addr); 350 } 351 352 static irqreturn_t xgbe_i2c_combined_isr(int irq, struct xgbe_prv_data *pdata) 353 { 354 if (!XI2C_IOREAD(pdata, IC_RAW_INTR_STAT)) 355 return IRQ_HANDLED; 356 357 return xgbe_i2c_isr(irq, pdata); 358 } 359 360 static int xgbe_i2c_xfer(struct xgbe_prv_data *pdata, struct xgbe_i2c_op *op) 361 { 362 struct xgbe_i2c_op_state *state = &pdata->i2c.op_state; 363 int ret; 364 365 mutex_lock(&pdata->i2c_mutex); 366 367 reinit_completion(&pdata->i2c_complete); 368 369 ret = xgbe_i2c_disable(pdata); 370 if (ret) { 371 netdev_err(pdata->netdev, "failed to disable i2c master\n"); 372 goto unlock; 373 } 374 375 xgbe_i2c_set_target(pdata, op->target); 376 377 memset(state, 0, sizeof(*state)); 378 state->op = op; 379 state->tx_len = op->len; 380 state->tx_buf = op->buf; 381 state->rx_len = op->len; 382 state->rx_buf = op->buf; 383 384 xgbe_i2c_clear_all_interrupts(pdata); 385 ret = xgbe_i2c_enable(pdata); 386 if (ret) { 387 netdev_err(pdata->netdev, "failed to enable i2c master\n"); 388 goto unlock; 389 } 390 391 /* Enabling the interrupts will cause the TX FIFO empty interrupt to 392 * fire and begin to process the command via the ISR. 393 */ 394 xgbe_i2c_enable_interrupts(pdata); 395 396 if (!wait_for_completion_timeout(&pdata->i2c_complete, HZ)) { 397 netdev_err(pdata->netdev, "i2c operation timed out\n"); 398 ret = -ETIMEDOUT; 399 goto disable; 400 } 401 402 ret = state->ret; 403 if (ret) { 404 if (state->tx_abort_source & IC_TX_ABRT_7B_ADDR_NOACK) 405 ret = -ENOTCONN; 406 else if (state->tx_abort_source & IC_TX_ABRT_ARB_LOST) 407 ret = -EAGAIN; 408 } 409 410 disable: 411 xgbe_i2c_disable_interrupts(pdata); 412 xgbe_i2c_disable(pdata); 413 414 unlock: 415 mutex_unlock(&pdata->i2c_mutex); 416 417 return ret; 418 } 419 420 static void xgbe_i2c_stop(struct xgbe_prv_data *pdata) 421 { 422 if (!pdata->i2c.started) 423 return; 424 425 netif_dbg(pdata, link, pdata->netdev, "stopping I2C\n"); 426 427 pdata->i2c.started = 0; 428 429 xgbe_i2c_disable_interrupts(pdata); 430 xgbe_i2c_disable(pdata); 431 xgbe_i2c_clear_all_interrupts(pdata); 432 433 if (pdata->dev_irq != pdata->i2c_irq) 434 devm_free_irq(pdata->dev, pdata->i2c_irq, pdata); 435 } 436 437 static int xgbe_i2c_start(struct xgbe_prv_data *pdata) 438 { 439 int ret; 440 441 if (pdata->i2c.started) 442 return 0; 443 444 netif_dbg(pdata, link, pdata->netdev, "starting I2C\n"); 445 446 /* If we have a separate I2C irq, enable it */ 447 if (pdata->dev_irq != pdata->i2c_irq) { 448 ret = devm_request_irq(pdata->dev, pdata->i2c_irq, 449 xgbe_i2c_isr, 0, pdata->i2c_name, 450 pdata); 451 if (ret) { 452 netdev_err(pdata->netdev, "i2c irq request failed\n"); 453 return ret; 454 } 455 } 456 457 pdata->i2c.started = 1; 458 459 return 0; 460 } 461 462 static int xgbe_i2c_init(struct xgbe_prv_data *pdata) 463 { 464 int ret; 465 466 xgbe_i2c_disable_interrupts(pdata); 467 468 ret = xgbe_i2c_disable(pdata); 469 if (ret) { 470 dev_err(pdata->dev, "failed to disable i2c master\n"); 471 return ret; 472 } 473 474 xgbe_i2c_get_features(pdata); 475 476 xgbe_i2c_set_mode(pdata); 477 478 xgbe_i2c_clear_all_interrupts(pdata); 479 480 return 0; 481 } 482 483 void xgbe_init_function_ptrs_i2c(struct xgbe_i2c_if *i2c_if) 484 { 485 i2c_if->i2c_init = xgbe_i2c_init; 486 487 i2c_if->i2c_start = xgbe_i2c_start; 488 i2c_if->i2c_stop = xgbe_i2c_stop; 489 490 i2c_if->i2c_xfer = xgbe_i2c_xfer; 491 492 i2c_if->i2c_isr = xgbe_i2c_combined_isr; 493 } 494