1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) 2 /* 3 * Copyright (c) 2014-2025, Advanced Micro Devices, Inc. 4 * Copyright (c) 2014, Synopsys, Inc. 5 * All rights reserved 6 * 7 * Author: Raju Rangoju <Raju.Rangoju@amd.com> 8 */ 9 10 #include "xgbe.h" 11 #include "xgbe-common.h" 12 13 void xgbe_update_tstamp_time(struct xgbe_prv_data *pdata, 14 unsigned int sec, unsigned int nsec) 15 { 16 int count; 17 18 /* Set the time values and tell the device */ 19 XGMAC_IOWRITE(pdata, MAC_STSUR, sec); 20 XGMAC_IOWRITE(pdata, MAC_STNUR, nsec); 21 22 /* issue command to update the system time value */ 23 XGMAC_IOWRITE(pdata, MAC_TSCR, 24 XGMAC_IOREAD(pdata, MAC_TSCR) | 25 (1 << MAC_TSCR_TSUPDT_INDEX)); 26 27 /* Wait for the time adjust/update to complete */ 28 count = 10000; 29 while (--count && XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSUPDT)) 30 udelay(5); 31 32 if (count < 0) 33 netdev_err(pdata->netdev, 34 "timed out updating system timestamp\n"); 35 } 36 37 void xgbe_update_tstamp_addend(struct xgbe_prv_data *pdata, 38 unsigned int addend) 39 { 40 unsigned int count = 10000; 41 42 /* Set the addend register value and tell the device */ 43 XGMAC_IOWRITE(pdata, MAC_TSAR, addend); 44 XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 1); 45 46 /* Wait for addend update to complete */ 47 while (--count && XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSADDREG)) 48 udelay(5); 49 50 if (!count) 51 netdev_err(pdata->netdev, 52 "timed out updating timestamp addend register\n"); 53 } 54 55 void xgbe_set_tstamp_time(struct xgbe_prv_data *pdata, unsigned int sec, 56 unsigned int nsec) 57 { 58 unsigned int count = 10000; 59 60 /* Set the time values and tell the device */ 61 XGMAC_IOWRITE(pdata, MAC_STSUR, sec); 62 XGMAC_IOWRITE(pdata, MAC_STNUR, nsec); 63 XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSINIT, 1); 64 65 /* Wait for time update to complete */ 66 while (--count && XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSINIT)) 67 udelay(5); 68 69 if (!count) 70 netdev_err(pdata->netdev, "timed out initializing timestamp\n"); 71 } 72 73 u64 xgbe_get_tstamp_time(struct xgbe_prv_data *pdata) 74 { 75 u64 nsec; 76 77 nsec = XGMAC_IOREAD(pdata, MAC_STSR); 78 nsec *= NSEC_PER_SEC; 79 nsec += XGMAC_IOREAD(pdata, MAC_STNR); 80 81 return nsec; 82 } 83 84 u64 xgbe_get_tx_tstamp(struct xgbe_prv_data *pdata) 85 { 86 unsigned int tx_snr, tx_ssr; 87 u64 nsec; 88 89 if (pdata->vdata->tx_tstamp_workaround) { 90 tx_snr = XGMAC_IOREAD(pdata, MAC_TXSNR); 91 tx_ssr = XGMAC_IOREAD(pdata, MAC_TXSSR); 92 } else { 93 tx_ssr = XGMAC_IOREAD(pdata, MAC_TXSSR); 94 tx_snr = XGMAC_IOREAD(pdata, MAC_TXSNR); 95 } 96 97 if (XGMAC_GET_BITS(tx_snr, MAC_TXSNR, TXTSSTSMIS)) 98 return 0; 99 100 nsec = tx_ssr; 101 nsec *= NSEC_PER_SEC; 102 nsec += tx_snr; 103 104 return nsec; 105 } 106 107 void xgbe_get_rx_tstamp(struct xgbe_packet_data *packet, 108 struct xgbe_ring_desc *rdesc) 109 { 110 u64 nsec; 111 112 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_CONTEXT_DESC3, TSA) && 113 !XGMAC_GET_BITS_LE(rdesc->desc3, RX_CONTEXT_DESC3, TSD)) { 114 nsec = le32_to_cpu(rdesc->desc1); 115 nsec *= NSEC_PER_SEC; 116 nsec += le32_to_cpu(rdesc->desc0); 117 if (nsec != 0xffffffffffffffffULL) { 118 packet->rx_tstamp = nsec; 119 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 120 RX_TSTAMP, 1); 121 } 122 } 123 } 124 125 void xgbe_config_tstamp(struct xgbe_prv_data *pdata, unsigned int mac_tscr) 126 { 127 unsigned int value = 0; 128 129 value = XGMAC_IOREAD(pdata, MAC_TSCR); 130 value |= mac_tscr; 131 XGMAC_IOWRITE(pdata, MAC_TSCR, value); 132 } 133 134 void xgbe_tx_tstamp(struct work_struct *work) 135 { 136 struct xgbe_prv_data *pdata = container_of(work, 137 struct xgbe_prv_data, 138 tx_tstamp_work); 139 struct skb_shared_hwtstamps hwtstamps; 140 unsigned long flags; 141 142 spin_lock_irqsave(&pdata->tstamp_lock, flags); 143 if (!pdata->tx_tstamp_skb) 144 goto unlock; 145 146 if (pdata->tx_tstamp) { 147 memset(&hwtstamps, 0, sizeof(hwtstamps)); 148 hwtstamps.hwtstamp = ns_to_ktime(pdata->tx_tstamp); 149 skb_tstamp_tx(pdata->tx_tstamp_skb, &hwtstamps); 150 } 151 152 dev_kfree_skb_any(pdata->tx_tstamp_skb); 153 154 pdata->tx_tstamp_skb = NULL; 155 156 unlock: 157 spin_unlock_irqrestore(&pdata->tstamp_lock, flags); 158 } 159 160 int xgbe_get_hwtstamp_settings(struct xgbe_prv_data *pdata, struct ifreq *ifreq) 161 { 162 if (copy_to_user(ifreq->ifr_data, &pdata->tstamp_config, 163 sizeof(pdata->tstamp_config))) 164 return -EFAULT; 165 166 return 0; 167 } 168 169 int xgbe_set_hwtstamp_settings(struct xgbe_prv_data *pdata, struct ifreq *ifreq) 170 { 171 struct hwtstamp_config config; 172 unsigned int mac_tscr; 173 174 if (copy_from_user(&config, ifreq->ifr_data, sizeof(config))) 175 return -EFAULT; 176 177 mac_tscr = 0; 178 179 switch (config.tx_type) { 180 case HWTSTAMP_TX_OFF: 181 break; 182 183 case HWTSTAMP_TX_ON: 184 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 185 break; 186 187 default: 188 return -ERANGE; 189 } 190 191 switch (config.rx_filter) { 192 case HWTSTAMP_FILTER_NONE: 193 break; 194 195 case HWTSTAMP_FILTER_NTP_ALL: 196 case HWTSTAMP_FILTER_ALL: 197 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 1); 198 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 199 break; 200 201 /* PTP v2, UDP, any kind of event packet */ 202 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 203 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); 204 fallthrough; /* to PTP v1, UDP, any kind of event packet */ 205 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 206 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); 207 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); 208 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1); 209 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 210 break; 211 /* PTP v2, UDP, Sync packet */ 212 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 213 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); 214 fallthrough; /* to PTP v1, UDP, Sync packet */ 215 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 216 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); 217 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); 218 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); 219 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 220 break; 221 222 /* PTP v2, UDP, Delay_req packet */ 223 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 224 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); 225 fallthrough; /* to PTP v1, UDP, Delay_req packet */ 226 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 227 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); 228 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); 229 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); 230 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1); 231 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 232 break; 233 234 /* 802.AS1, Ethernet, any kind of event packet */ 235 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 236 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1); 237 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1); 238 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 239 break; 240 241 /* 802.AS1, Ethernet, Sync packet */ 242 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 243 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1); 244 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); 245 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 246 break; 247 248 /* 802.AS1, Ethernet, Delay_req packet */ 249 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 250 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1); 251 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1); 252 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); 253 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 254 break; 255 256 /* PTP v2/802.AS1, any layer, any kind of event packet */ 257 case HWTSTAMP_FILTER_PTP_V2_EVENT: 258 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); 259 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1); 260 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); 261 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); 262 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1); 263 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 264 break; 265 266 /* PTP v2/802.AS1, any layer, Sync packet */ 267 case HWTSTAMP_FILTER_PTP_V2_SYNC: 268 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); 269 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1); 270 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); 271 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); 272 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); 273 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 274 break; 275 276 /* PTP v2/802.AS1, any layer, Delay_req packet */ 277 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 278 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); 279 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1); 280 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); 281 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); 282 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1); 283 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); 284 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 285 break; 286 287 default: 288 return -ERANGE; 289 } 290 291 xgbe_config_tstamp(pdata, mac_tscr); 292 293 memcpy(&pdata->tstamp_config, &config, sizeof(config)); 294 295 return 0; 296 } 297 298 void xgbe_prep_tx_tstamp(struct xgbe_prv_data *pdata, 299 struct sk_buff *skb, 300 struct xgbe_packet_data *packet) 301 { 302 unsigned long flags; 303 304 if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP)) { 305 spin_lock_irqsave(&pdata->tstamp_lock, flags); 306 if (pdata->tx_tstamp_skb) { 307 /* Another timestamp in progress, ignore this one */ 308 XGMAC_SET_BITS(packet->attributes, 309 TX_PACKET_ATTRIBUTES, PTP, 0); 310 } else { 311 pdata->tx_tstamp_skb = skb_get(skb); 312 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 313 } 314 spin_unlock_irqrestore(&pdata->tstamp_lock, flags); 315 } 316 317 skb_tx_timestamp(skb); 318 } 319 320 int xgbe_init_ptp(struct xgbe_prv_data *pdata) 321 { 322 unsigned int mac_tscr = 0; 323 struct timespec64 now; 324 u64 dividend; 325 326 /* Register Settings to be done based on the link speed. */ 327 switch (pdata->phy.speed) { 328 case SPEED_1000: 329 XGMAC_IOWRITE(pdata, MAC_TICNR, MAC_TICNR_1G_INITVAL); 330 XGMAC_IOWRITE(pdata, MAC_TECNR, MAC_TECNR_1G_INITVAL); 331 break; 332 case SPEED_2500: 333 case SPEED_10000: 334 XGMAC_IOWRITE_BITS(pdata, MAC_TICSNR, TSICSNS, 335 MAC_TICSNR_10G_INITVAL); 336 XGMAC_IOWRITE(pdata, MAC_TECNR, MAC_TECNR_10G_INITVAL); 337 XGMAC_IOWRITE_BITS(pdata, MAC_TECSNR, TSECSNS, 338 MAC_TECSNR_10G_INITVAL); 339 break; 340 case SPEED_UNKNOWN: 341 default: 342 break; 343 } 344 345 /* Enable IEEE1588 PTP clock. */ 346 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 347 348 /* Overwrite earlier timestamps */ 349 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TXTSSTSM, 1); 350 351 /* Set one nano-second accuracy */ 352 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCTRLSSR, 1); 353 354 /* Set fine timestamp update */ 355 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 1); 356 357 xgbe_config_tstamp(pdata, mac_tscr); 358 359 /* Exit if timestamping is not enabled */ 360 if (!XGMAC_GET_BITS(mac_tscr, MAC_TSCR, TSENA)) 361 return -EOPNOTSUPP; 362 363 if (pdata->vdata->tstamp_ptp_clock_freq) { 364 /* Initialize time registers based on 365 * 125MHz PTP Clock Frequency 366 */ 367 XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SSINC, 368 XGBE_V2_TSTAMP_SSINC); 369 XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SNSINC, 370 XGBE_V2_TSTAMP_SNSINC); 371 } else { 372 /* Initialize time registers based on 373 * 50MHz PTP Clock Frequency 374 */ 375 XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SSINC, XGBE_TSTAMP_SSINC); 376 XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SNSINC, XGBE_TSTAMP_SNSINC); 377 } 378 379 /* Calculate the addend: 380 * addend = 2^32 / (PTP ref clock / (PTP clock based on SSINC)) 381 * = (2^32 * (PTP clock based on SSINC)) / PTP ref clock 382 */ 383 if (pdata->vdata->tstamp_ptp_clock_freq) 384 dividend = XGBE_V2_PTP_ACT_CLK_FREQ; 385 else 386 dividend = XGBE_PTP_ACT_CLK_FREQ; 387 388 dividend = (u64)(dividend << 32); 389 pdata->tstamp_addend = div_u64(dividend, pdata->ptpclk_rate); 390 391 xgbe_update_tstamp_addend(pdata, pdata->tstamp_addend); 392 393 dma_wmb(); 394 /* initialize system time */ 395 ktime_get_real_ts64(&now); 396 397 /* lower 32 bits of tv_sec are safe until y2106 */ 398 xgbe_set_tstamp_time(pdata, (u32)now.tv_sec, now.tv_nsec); 399 400 return 0; 401 } 402