1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) 2 /* 3 * Copyright (c) 2014-2025, Advanced Micro Devices, Inc. 4 * Copyright (c) 2014, Synopsys, Inc. 5 * All rights reserved 6 */ 7 8 #include <linux/module.h> 9 #include <linux/spinlock.h> 10 #include <linux/tcp.h> 11 #include <linux/if_vlan.h> 12 #include <linux/interrupt.h> 13 #include <linux/clk.h> 14 #include <linux/if_ether.h> 15 #include <linux/net_tstamp.h> 16 #include <linux/phy.h> 17 #include <net/vxlan.h> 18 19 #include "xgbe.h" 20 #include "xgbe-common.h" 21 22 static unsigned int ecc_sec_info_threshold = 10; 23 static unsigned int ecc_sec_warn_threshold = 10000; 24 static unsigned int ecc_sec_period = 600; 25 static unsigned int ecc_ded_threshold = 2; 26 static unsigned int ecc_ded_period = 600; 27 28 #ifdef CONFIG_AMD_XGBE_HAVE_ECC 29 /* Only expose the ECC parameters if supported */ 30 module_param(ecc_sec_info_threshold, uint, 0644); 31 MODULE_PARM_DESC(ecc_sec_info_threshold, 32 " ECC corrected error informational threshold setting"); 33 34 module_param(ecc_sec_warn_threshold, uint, 0644); 35 MODULE_PARM_DESC(ecc_sec_warn_threshold, 36 " ECC corrected error warning threshold setting"); 37 38 module_param(ecc_sec_period, uint, 0644); 39 MODULE_PARM_DESC(ecc_sec_period, " ECC corrected error period (in seconds)"); 40 41 module_param(ecc_ded_threshold, uint, 0644); 42 MODULE_PARM_DESC(ecc_ded_threshold, " ECC detected error threshold setting"); 43 44 module_param(ecc_ded_period, uint, 0644); 45 MODULE_PARM_DESC(ecc_ded_period, " ECC detected error period (in seconds)"); 46 #endif 47 48 static int xgbe_one_poll(struct napi_struct *, int); 49 static int xgbe_all_poll(struct napi_struct *, int); 50 static void xgbe_stop(struct xgbe_prv_data *); 51 52 static void *xgbe_alloc_node(size_t size, int node) 53 { 54 void *mem; 55 56 mem = kzalloc_node(size, GFP_KERNEL, node); 57 if (!mem) 58 mem = kzalloc(size, GFP_KERNEL); 59 60 return mem; 61 } 62 63 static void xgbe_free_channels(struct xgbe_prv_data *pdata) 64 { 65 unsigned int i; 66 67 for (i = 0; i < ARRAY_SIZE(pdata->channel); i++) { 68 if (!pdata->channel[i]) 69 continue; 70 71 kfree(pdata->channel[i]->rx_ring); 72 kfree(pdata->channel[i]->tx_ring); 73 kfree(pdata->channel[i]); 74 75 pdata->channel[i] = NULL; 76 } 77 78 pdata->channel_count = 0; 79 } 80 81 static int xgbe_alloc_channels(struct xgbe_prv_data *pdata) 82 { 83 struct xgbe_channel *channel; 84 struct xgbe_ring *ring; 85 unsigned int count, i; 86 unsigned int cpu; 87 int node; 88 89 count = max_t(unsigned int, pdata->tx_ring_count, pdata->rx_ring_count); 90 for (i = 0; i < count; i++) { 91 /* Attempt to use a CPU on the node the device is on */ 92 cpu = cpumask_local_spread(i, dev_to_node(pdata->dev)); 93 94 /* Set the allocation node based on the returned CPU */ 95 node = cpu_to_node(cpu); 96 97 channel = xgbe_alloc_node(sizeof(*channel), node); 98 if (!channel) 99 goto err_mem; 100 pdata->channel[i] = channel; 101 102 snprintf(channel->name, sizeof(channel->name), "channel-%u", i); 103 channel->pdata = pdata; 104 channel->queue_index = i; 105 channel->dma_regs = pdata->xgmac_regs + DMA_CH_BASE + 106 (DMA_CH_INC * i); 107 channel->node = node; 108 cpumask_set_cpu(cpu, &channel->affinity_mask); 109 110 if (pdata->per_channel_irq) 111 channel->dma_irq = pdata->channel_irq[i]; 112 113 if (i < pdata->tx_ring_count) { 114 ring = xgbe_alloc_node(sizeof(*ring), node); 115 if (!ring) 116 goto err_mem; 117 118 spin_lock_init(&ring->lock); 119 ring->node = node; 120 121 channel->tx_ring = ring; 122 } 123 124 if (i < pdata->rx_ring_count) { 125 ring = xgbe_alloc_node(sizeof(*ring), node); 126 if (!ring) 127 goto err_mem; 128 129 spin_lock_init(&ring->lock); 130 ring->node = node; 131 132 channel->rx_ring = ring; 133 } 134 135 netif_dbg(pdata, drv, pdata->netdev, 136 "%s: cpu=%u, node=%d\n", channel->name, cpu, node); 137 138 netif_dbg(pdata, drv, pdata->netdev, 139 "%s: dma_regs=%p, dma_irq=%d, tx=%p, rx=%p\n", 140 channel->name, channel->dma_regs, channel->dma_irq, 141 channel->tx_ring, channel->rx_ring); 142 } 143 144 pdata->channel_count = count; 145 146 return 0; 147 148 err_mem: 149 xgbe_free_channels(pdata); 150 151 return -ENOMEM; 152 } 153 154 static inline unsigned int xgbe_tx_avail_desc(struct xgbe_ring *ring) 155 { 156 return (ring->rdesc_count - (ring->cur - ring->dirty)); 157 } 158 159 static inline unsigned int xgbe_rx_dirty_desc(struct xgbe_ring *ring) 160 { 161 return (ring->cur - ring->dirty); 162 } 163 164 static int xgbe_maybe_stop_tx_queue(struct xgbe_channel *channel, 165 struct xgbe_ring *ring, unsigned int count) 166 { 167 struct xgbe_prv_data *pdata = channel->pdata; 168 169 if (count > xgbe_tx_avail_desc(ring)) { 170 netif_info(pdata, drv, pdata->netdev, 171 "Tx queue stopped, not enough descriptors available\n"); 172 netif_stop_subqueue(pdata->netdev, channel->queue_index); 173 ring->tx.queue_stopped = 1; 174 175 /* If we haven't notified the hardware because of xmit_more 176 * support, tell it now 177 */ 178 if (ring->tx.xmit_more) 179 pdata->hw_if.tx_start_xmit(channel, ring); 180 181 return NETDEV_TX_BUSY; 182 } 183 184 return 0; 185 } 186 187 static int xgbe_calc_rx_buf_size(struct net_device *netdev, unsigned int mtu) 188 { 189 unsigned int rx_buf_size; 190 191 rx_buf_size = mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 192 rx_buf_size = clamp_val(rx_buf_size, XGBE_RX_MIN_BUF_SIZE, PAGE_SIZE); 193 194 rx_buf_size = (rx_buf_size + XGBE_RX_BUF_ALIGN - 1) & 195 ~(XGBE_RX_BUF_ALIGN - 1); 196 197 return rx_buf_size; 198 } 199 200 static void xgbe_enable_rx_tx_int(struct xgbe_prv_data *pdata, 201 struct xgbe_channel *channel) 202 { 203 struct xgbe_hw_if *hw_if = &pdata->hw_if; 204 enum xgbe_int int_id; 205 206 if (channel->tx_ring && channel->rx_ring) 207 int_id = XGMAC_INT_DMA_CH_SR_TI_RI; 208 else if (channel->tx_ring) 209 int_id = XGMAC_INT_DMA_CH_SR_TI; 210 else if (channel->rx_ring) 211 int_id = XGMAC_INT_DMA_CH_SR_RI; 212 else 213 return; 214 215 hw_if->enable_int(channel, int_id); 216 } 217 218 static void xgbe_enable_rx_tx_ints(struct xgbe_prv_data *pdata) 219 { 220 unsigned int i; 221 222 for (i = 0; i < pdata->channel_count; i++) 223 xgbe_enable_rx_tx_int(pdata, pdata->channel[i]); 224 } 225 226 static void xgbe_disable_rx_tx_int(struct xgbe_prv_data *pdata, 227 struct xgbe_channel *channel) 228 { 229 struct xgbe_hw_if *hw_if = &pdata->hw_if; 230 enum xgbe_int int_id; 231 232 if (channel->tx_ring && channel->rx_ring) 233 int_id = XGMAC_INT_DMA_CH_SR_TI_RI; 234 else if (channel->tx_ring) 235 int_id = XGMAC_INT_DMA_CH_SR_TI; 236 else if (channel->rx_ring) 237 int_id = XGMAC_INT_DMA_CH_SR_RI; 238 else 239 return; 240 241 hw_if->disable_int(channel, int_id); 242 } 243 244 static void xgbe_disable_rx_tx_ints(struct xgbe_prv_data *pdata) 245 { 246 unsigned int i; 247 248 for (i = 0; i < pdata->channel_count; i++) 249 xgbe_disable_rx_tx_int(pdata, pdata->channel[i]); 250 } 251 252 static bool xgbe_ecc_sec(struct xgbe_prv_data *pdata, unsigned long *period, 253 unsigned int *count, const char *area) 254 { 255 if (time_before(jiffies, *period)) { 256 (*count)++; 257 } else { 258 *period = jiffies + (ecc_sec_period * HZ); 259 *count = 1; 260 } 261 262 if (*count > ecc_sec_info_threshold) 263 dev_warn_once(pdata->dev, 264 "%s ECC corrected errors exceed informational threshold\n", 265 area); 266 267 if (*count > ecc_sec_warn_threshold) { 268 dev_warn_once(pdata->dev, 269 "%s ECC corrected errors exceed warning threshold\n", 270 area); 271 return true; 272 } 273 274 return false; 275 } 276 277 static bool xgbe_ecc_ded(struct xgbe_prv_data *pdata, unsigned long *period, 278 unsigned int *count, const char *area) 279 { 280 if (time_before(jiffies, *period)) { 281 (*count)++; 282 } else { 283 *period = jiffies + (ecc_ded_period * HZ); 284 *count = 1; 285 } 286 287 if (*count > ecc_ded_threshold) { 288 netdev_alert(pdata->netdev, 289 "%s ECC detected errors exceed threshold\n", 290 area); 291 return true; 292 } 293 294 return false; 295 } 296 297 static void xgbe_ecc_isr_bh_work(struct work_struct *work) 298 { 299 struct xgbe_prv_data *pdata = from_work(pdata, work, ecc_bh_work); 300 unsigned int ecc_isr; 301 bool stop = false; 302 303 /* Mask status with only the interrupts we care about */ 304 ecc_isr = XP_IOREAD(pdata, XP_ECC_ISR); 305 ecc_isr &= XP_IOREAD(pdata, XP_ECC_IER); 306 netif_dbg(pdata, intr, pdata->netdev, "ECC_ISR=%#010x\n", ecc_isr); 307 308 if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, TX_DED)) { 309 stop |= xgbe_ecc_ded(pdata, &pdata->tx_ded_period, 310 &pdata->tx_ded_count, "TX fifo"); 311 } 312 313 if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, RX_DED)) { 314 stop |= xgbe_ecc_ded(pdata, &pdata->rx_ded_period, 315 &pdata->rx_ded_count, "RX fifo"); 316 } 317 318 if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, DESC_DED)) { 319 stop |= xgbe_ecc_ded(pdata, &pdata->desc_ded_period, 320 &pdata->desc_ded_count, 321 "descriptor cache"); 322 } 323 324 if (stop) { 325 pdata->hw_if.disable_ecc_ded(pdata); 326 schedule_work(&pdata->stopdev_work); 327 goto out; 328 } 329 330 if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, TX_SEC)) { 331 if (xgbe_ecc_sec(pdata, &pdata->tx_sec_period, 332 &pdata->tx_sec_count, "TX fifo")) 333 pdata->hw_if.disable_ecc_sec(pdata, XGBE_ECC_SEC_TX); 334 } 335 336 if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, RX_SEC)) 337 if (xgbe_ecc_sec(pdata, &pdata->rx_sec_period, 338 &pdata->rx_sec_count, "RX fifo")) 339 pdata->hw_if.disable_ecc_sec(pdata, XGBE_ECC_SEC_RX); 340 341 if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, DESC_SEC)) 342 if (xgbe_ecc_sec(pdata, &pdata->desc_sec_period, 343 &pdata->desc_sec_count, "descriptor cache")) 344 pdata->hw_if.disable_ecc_sec(pdata, XGBE_ECC_SEC_DESC); 345 346 out: 347 /* Clear all ECC interrupts */ 348 XP_IOWRITE(pdata, XP_ECC_ISR, ecc_isr); 349 350 /* Reissue interrupt if status is not clear */ 351 if (pdata->vdata->irq_reissue_support) 352 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 1); 353 } 354 355 static irqreturn_t xgbe_ecc_isr(int irq, void *data) 356 { 357 struct xgbe_prv_data *pdata = data; 358 359 if (pdata->isr_as_bh_work) 360 queue_work(system_bh_wq, &pdata->ecc_bh_work); 361 else 362 xgbe_ecc_isr_bh_work(&pdata->ecc_bh_work); 363 364 return IRQ_HANDLED; 365 } 366 367 static void xgbe_isr_bh_work(struct work_struct *work) 368 { 369 struct xgbe_prv_data *pdata = from_work(pdata, work, dev_bh_work); 370 struct xgbe_hw_if *hw_if = &pdata->hw_if; 371 struct xgbe_channel *channel; 372 unsigned int dma_isr, dma_ch_isr; 373 unsigned int mac_isr, mac_tssr, mac_mdioisr; 374 unsigned int i; 375 376 /* The DMA interrupt status register also reports MAC and MTL 377 * interrupts. So for polling mode, we just need to check for 378 * this register to be non-zero 379 */ 380 dma_isr = XGMAC_IOREAD(pdata, DMA_ISR); 381 if (!dma_isr) 382 goto isr_done; 383 384 netif_dbg(pdata, intr, pdata->netdev, "DMA_ISR=%#010x\n", dma_isr); 385 386 for (i = 0; i < pdata->channel_count; i++) { 387 if (!(dma_isr & (1 << i))) 388 continue; 389 390 channel = pdata->channel[i]; 391 392 dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR); 393 netif_dbg(pdata, intr, pdata->netdev, "DMA_CH%u_ISR=%#010x\n", 394 i, dma_ch_isr); 395 396 /* The TI or RI interrupt bits may still be set even if using 397 * per channel DMA interrupts. Check to be sure those are not 398 * enabled before using the private data napi structure. 399 */ 400 if (!pdata->per_channel_irq && 401 (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, TI) || 402 XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RI))) { 403 if (napi_schedule_prep(&pdata->napi)) { 404 /* Disable Tx and Rx interrupts */ 405 xgbe_disable_rx_tx_ints(pdata); 406 407 /* Turn on polling */ 408 __napi_schedule(&pdata->napi); 409 } 410 } else { 411 /* Don't clear Rx/Tx status if doing per channel DMA 412 * interrupts, these will be cleared by the ISR for 413 * per channel DMA interrupts. 414 */ 415 XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, TI, 0); 416 XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, RI, 0); 417 } 418 419 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RBU)) 420 pdata->ext_stats.rx_buffer_unavailable++; 421 422 /* Restart the device on a Fatal Bus Error */ 423 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, FBE)) 424 schedule_work(&pdata->restart_work); 425 426 /* Clear interrupt signals */ 427 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr); 428 } 429 430 if (XGMAC_GET_BITS(dma_isr, DMA_ISR, MACIS)) { 431 mac_isr = XGMAC_IOREAD(pdata, MAC_ISR); 432 433 netif_dbg(pdata, intr, pdata->netdev, "MAC_ISR=%#010x\n", 434 mac_isr); 435 436 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCTXIS)) 437 hw_if->tx_mmc_int(pdata); 438 439 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCRXIS)) 440 hw_if->rx_mmc_int(pdata); 441 442 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, TSIS)) { 443 mac_tssr = XGMAC_IOREAD(pdata, MAC_TSSR); 444 445 netif_dbg(pdata, intr, pdata->netdev, 446 "MAC_TSSR=%#010x\n", mac_tssr); 447 448 if (XGMAC_GET_BITS(mac_tssr, MAC_TSSR, TXTSC)) { 449 /* Read Tx Timestamp to clear interrupt */ 450 pdata->tx_tstamp = 451 hw_if->get_tx_tstamp(pdata); 452 queue_work(pdata->dev_workqueue, 453 &pdata->tx_tstamp_work); 454 } 455 } 456 457 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, SMI)) { 458 mac_mdioisr = XGMAC_IOREAD(pdata, MAC_MDIOISR); 459 460 netif_dbg(pdata, intr, pdata->netdev, 461 "MAC_MDIOISR=%#010x\n", mac_mdioisr); 462 463 if (XGMAC_GET_BITS(mac_mdioisr, MAC_MDIOISR, 464 SNGLCOMPINT)) 465 complete(&pdata->mdio_complete); 466 } 467 } 468 469 isr_done: 470 /* If there is not a separate AN irq, handle it here */ 471 if (pdata->dev_irq == pdata->an_irq) 472 pdata->phy_if.an_isr(pdata); 473 474 /* If there is not a separate ECC irq, handle it here */ 475 if (pdata->vdata->ecc_support && (pdata->dev_irq == pdata->ecc_irq)) 476 xgbe_ecc_isr_bh_work(&pdata->ecc_bh_work); 477 478 /* If there is not a separate I2C irq, handle it here */ 479 if (pdata->vdata->i2c_support && (pdata->dev_irq == pdata->i2c_irq)) 480 pdata->i2c_if.i2c_isr(pdata); 481 482 /* Reissue interrupt if status is not clear */ 483 if (pdata->vdata->irq_reissue_support) { 484 unsigned int reissue_mask; 485 486 reissue_mask = 1 << 0; 487 if (!pdata->per_channel_irq) 488 reissue_mask |= 0xffff << 4; 489 490 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, reissue_mask); 491 } 492 } 493 494 static irqreturn_t xgbe_isr(int irq, void *data) 495 { 496 struct xgbe_prv_data *pdata = data; 497 498 if (pdata->isr_as_bh_work) 499 queue_work(system_bh_wq, &pdata->dev_bh_work); 500 else 501 xgbe_isr_bh_work(&pdata->dev_bh_work); 502 503 return IRQ_HANDLED; 504 } 505 506 static irqreturn_t xgbe_dma_isr(int irq, void *data) 507 { 508 struct xgbe_channel *channel = data; 509 struct xgbe_prv_data *pdata = channel->pdata; 510 unsigned int dma_status; 511 512 /* Per channel DMA interrupts are enabled, so we use the per 513 * channel napi structure and not the private data napi structure 514 */ 515 if (napi_schedule_prep(&channel->napi)) { 516 /* Disable Tx and Rx interrupts */ 517 if (pdata->channel_irq_mode) 518 xgbe_disable_rx_tx_int(pdata, channel); 519 else 520 disable_irq_nosync(channel->dma_irq); 521 522 /* Turn on polling */ 523 __napi_schedule_irqoff(&channel->napi); 524 } 525 526 /* Clear Tx/Rx signals */ 527 dma_status = 0; 528 XGMAC_SET_BITS(dma_status, DMA_CH_SR, TI, 1); 529 XGMAC_SET_BITS(dma_status, DMA_CH_SR, RI, 1); 530 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_status); 531 532 return IRQ_HANDLED; 533 } 534 535 static void xgbe_tx_timer(struct timer_list *t) 536 { 537 struct xgbe_channel *channel = from_timer(channel, t, tx_timer); 538 struct xgbe_prv_data *pdata = channel->pdata; 539 struct napi_struct *napi; 540 541 DBGPR("-->xgbe_tx_timer\n"); 542 543 napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi; 544 545 if (napi_schedule_prep(napi)) { 546 /* Disable Tx and Rx interrupts */ 547 if (pdata->per_channel_irq) 548 if (pdata->channel_irq_mode) 549 xgbe_disable_rx_tx_int(pdata, channel); 550 else 551 disable_irq_nosync(channel->dma_irq); 552 else 553 xgbe_disable_rx_tx_ints(pdata); 554 555 /* Turn on polling */ 556 __napi_schedule(napi); 557 } 558 559 channel->tx_timer_active = 0; 560 561 DBGPR("<--xgbe_tx_timer\n"); 562 } 563 564 static void xgbe_service(struct work_struct *work) 565 { 566 struct xgbe_prv_data *pdata = container_of(work, 567 struct xgbe_prv_data, 568 service_work); 569 570 pdata->phy_if.phy_status(pdata); 571 } 572 573 static void xgbe_service_timer(struct timer_list *t) 574 { 575 struct xgbe_prv_data *pdata = from_timer(pdata, t, service_timer); 576 struct xgbe_channel *channel; 577 unsigned int i; 578 579 queue_work(pdata->dev_workqueue, &pdata->service_work); 580 581 mod_timer(&pdata->service_timer, jiffies + HZ); 582 583 if (!pdata->tx_usecs) 584 return; 585 586 for (i = 0; i < pdata->channel_count; i++) { 587 channel = pdata->channel[i]; 588 if (!channel->tx_ring || channel->tx_timer_active) 589 break; 590 channel->tx_timer_active = 1; 591 mod_timer(&channel->tx_timer, 592 jiffies + usecs_to_jiffies(pdata->tx_usecs)); 593 } 594 } 595 596 static void xgbe_init_timers(struct xgbe_prv_data *pdata) 597 { 598 struct xgbe_channel *channel; 599 unsigned int i; 600 601 timer_setup(&pdata->service_timer, xgbe_service_timer, 0); 602 603 for (i = 0; i < pdata->channel_count; i++) { 604 channel = pdata->channel[i]; 605 if (!channel->tx_ring) 606 break; 607 608 timer_setup(&channel->tx_timer, xgbe_tx_timer, 0); 609 } 610 } 611 612 static void xgbe_start_timers(struct xgbe_prv_data *pdata) 613 { 614 mod_timer(&pdata->service_timer, jiffies + HZ); 615 } 616 617 static void xgbe_stop_timers(struct xgbe_prv_data *pdata) 618 { 619 struct xgbe_channel *channel; 620 unsigned int i; 621 622 timer_delete_sync(&pdata->service_timer); 623 624 for (i = 0; i < pdata->channel_count; i++) { 625 channel = pdata->channel[i]; 626 if (!channel->tx_ring) 627 break; 628 629 /* Deactivate the Tx timer */ 630 timer_delete_sync(&channel->tx_timer); 631 channel->tx_timer_active = 0; 632 } 633 } 634 635 void xgbe_get_all_hw_features(struct xgbe_prv_data *pdata) 636 { 637 unsigned int mac_hfr0, mac_hfr1, mac_hfr2; 638 struct xgbe_hw_features *hw_feat = &pdata->hw_feat; 639 640 mac_hfr0 = XGMAC_IOREAD(pdata, MAC_HWF0R); 641 mac_hfr1 = XGMAC_IOREAD(pdata, MAC_HWF1R); 642 mac_hfr2 = XGMAC_IOREAD(pdata, MAC_HWF2R); 643 644 memset(hw_feat, 0, sizeof(*hw_feat)); 645 646 hw_feat->version = XGMAC_IOREAD(pdata, MAC_VR); 647 648 /* Hardware feature register 0 */ 649 hw_feat->gmii = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL); 650 hw_feat->vlhash = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH); 651 hw_feat->sma = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL); 652 hw_feat->rwk = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL); 653 hw_feat->mgk = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL); 654 hw_feat->mmc = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL); 655 hw_feat->aoe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL); 656 hw_feat->ts = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL); 657 hw_feat->eee = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL); 658 hw_feat->tx_coe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL); 659 hw_feat->rx_coe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL); 660 hw_feat->addn_mac = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, 661 ADDMACADRSEL); 662 hw_feat->ts_src = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL); 663 hw_feat->sa_vlan_ins = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS); 664 hw_feat->vxn = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VXN); 665 666 /* Hardware feature register 1 */ 667 hw_feat->rx_fifo_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 668 RXFIFOSIZE); 669 hw_feat->tx_fifo_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 670 TXFIFOSIZE); 671 hw_feat->adv_ts_hi = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADVTHWORD); 672 hw_feat->dma_width = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADDR64); 673 hw_feat->dcb = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN); 674 hw_feat->sph = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN); 675 hw_feat->tso = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN); 676 hw_feat->dma_debug = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA); 677 hw_feat->rss = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, RSSEN); 678 hw_feat->tc_cnt = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC); 679 hw_feat->hash_table_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 680 HASHTBLSZ); 681 hw_feat->l3l4_filter_num = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 682 L3L4FNUM); 683 684 /* Hardware feature register 2 */ 685 hw_feat->rx_q_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT); 686 hw_feat->tx_q_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT); 687 hw_feat->rx_ch_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT); 688 hw_feat->tx_ch_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT); 689 hw_feat->pps_out_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM); 690 hw_feat->aux_snap_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, AUXSNAPNUM); 691 692 /* Translate the Hash Table size into actual number */ 693 switch (hw_feat->hash_table_size) { 694 case 0: 695 break; 696 case 1: 697 hw_feat->hash_table_size = 64; 698 break; 699 case 2: 700 hw_feat->hash_table_size = 128; 701 break; 702 case 3: 703 hw_feat->hash_table_size = 256; 704 break; 705 } 706 707 /* Translate the address width setting into actual number */ 708 switch (hw_feat->dma_width) { 709 case 0: 710 hw_feat->dma_width = 32; 711 break; 712 case 1: 713 hw_feat->dma_width = 40; 714 break; 715 case 2: 716 hw_feat->dma_width = 48; 717 break; 718 default: 719 hw_feat->dma_width = 32; 720 } 721 722 /* The Queue, Channel and TC counts are zero based so increment them 723 * to get the actual number 724 */ 725 hw_feat->rx_q_cnt++; 726 hw_feat->tx_q_cnt++; 727 hw_feat->rx_ch_cnt++; 728 hw_feat->tx_ch_cnt++; 729 hw_feat->tc_cnt++; 730 731 /* Translate the fifo sizes into actual numbers */ 732 hw_feat->rx_fifo_size = 1 << (hw_feat->rx_fifo_size + 7); 733 hw_feat->tx_fifo_size = 1 << (hw_feat->tx_fifo_size + 7); 734 735 if (netif_msg_probe(pdata)) { 736 dev_dbg(pdata->dev, "Hardware features:\n"); 737 738 /* Hardware feature register 0 */ 739 dev_dbg(pdata->dev, " 1GbE support : %s\n", 740 hw_feat->gmii ? "yes" : "no"); 741 dev_dbg(pdata->dev, " VLAN hash filter : %s\n", 742 hw_feat->vlhash ? "yes" : "no"); 743 dev_dbg(pdata->dev, " MDIO interface : %s\n", 744 hw_feat->sma ? "yes" : "no"); 745 dev_dbg(pdata->dev, " Wake-up packet support : %s\n", 746 hw_feat->rwk ? "yes" : "no"); 747 dev_dbg(pdata->dev, " Magic packet support : %s\n", 748 hw_feat->mgk ? "yes" : "no"); 749 dev_dbg(pdata->dev, " Management counters : %s\n", 750 hw_feat->mmc ? "yes" : "no"); 751 dev_dbg(pdata->dev, " ARP offload : %s\n", 752 hw_feat->aoe ? "yes" : "no"); 753 dev_dbg(pdata->dev, " IEEE 1588-2008 Timestamp : %s\n", 754 hw_feat->ts ? "yes" : "no"); 755 dev_dbg(pdata->dev, " Energy Efficient Ethernet : %s\n", 756 hw_feat->eee ? "yes" : "no"); 757 dev_dbg(pdata->dev, " TX checksum offload : %s\n", 758 hw_feat->tx_coe ? "yes" : "no"); 759 dev_dbg(pdata->dev, " RX checksum offload : %s\n", 760 hw_feat->rx_coe ? "yes" : "no"); 761 dev_dbg(pdata->dev, " Additional MAC addresses : %u\n", 762 hw_feat->addn_mac); 763 dev_dbg(pdata->dev, " Timestamp source : %s\n", 764 (hw_feat->ts_src == 1) ? "internal" : 765 (hw_feat->ts_src == 2) ? "external" : 766 (hw_feat->ts_src == 3) ? "internal/external" : "n/a"); 767 dev_dbg(pdata->dev, " SA/VLAN insertion : %s\n", 768 hw_feat->sa_vlan_ins ? "yes" : "no"); 769 dev_dbg(pdata->dev, " VXLAN/NVGRE support : %s\n", 770 hw_feat->vxn ? "yes" : "no"); 771 772 /* Hardware feature register 1 */ 773 dev_dbg(pdata->dev, " RX fifo size : %u\n", 774 hw_feat->rx_fifo_size); 775 dev_dbg(pdata->dev, " TX fifo size : %u\n", 776 hw_feat->tx_fifo_size); 777 dev_dbg(pdata->dev, " IEEE 1588 high word : %s\n", 778 hw_feat->adv_ts_hi ? "yes" : "no"); 779 dev_dbg(pdata->dev, " DMA width : %u\n", 780 hw_feat->dma_width); 781 dev_dbg(pdata->dev, " Data Center Bridging : %s\n", 782 hw_feat->dcb ? "yes" : "no"); 783 dev_dbg(pdata->dev, " Split header : %s\n", 784 hw_feat->sph ? "yes" : "no"); 785 dev_dbg(pdata->dev, " TCP Segmentation Offload : %s\n", 786 hw_feat->tso ? "yes" : "no"); 787 dev_dbg(pdata->dev, " Debug memory interface : %s\n", 788 hw_feat->dma_debug ? "yes" : "no"); 789 dev_dbg(pdata->dev, " Receive Side Scaling : %s\n", 790 hw_feat->rss ? "yes" : "no"); 791 dev_dbg(pdata->dev, " Traffic Class count : %u\n", 792 hw_feat->tc_cnt); 793 dev_dbg(pdata->dev, " Hash table size : %u\n", 794 hw_feat->hash_table_size); 795 dev_dbg(pdata->dev, " L3/L4 Filters : %u\n", 796 hw_feat->l3l4_filter_num); 797 798 /* Hardware feature register 2 */ 799 dev_dbg(pdata->dev, " RX queue count : %u\n", 800 hw_feat->rx_q_cnt); 801 dev_dbg(pdata->dev, " TX queue count : %u\n", 802 hw_feat->tx_q_cnt); 803 dev_dbg(pdata->dev, " RX DMA channel count : %u\n", 804 hw_feat->rx_ch_cnt); 805 dev_dbg(pdata->dev, " TX DMA channel count : %u\n", 806 hw_feat->rx_ch_cnt); 807 dev_dbg(pdata->dev, " PPS outputs : %u\n", 808 hw_feat->pps_out_num); 809 dev_dbg(pdata->dev, " Auxiliary snapshot inputs : %u\n", 810 hw_feat->aux_snap_num); 811 } 812 } 813 814 static int xgbe_vxlan_set_port(struct net_device *netdev, unsigned int table, 815 unsigned int entry, struct udp_tunnel_info *ti) 816 { 817 struct xgbe_prv_data *pdata = netdev_priv(netdev); 818 819 pdata->vxlan_port = be16_to_cpu(ti->port); 820 pdata->hw_if.enable_vxlan(pdata); 821 822 return 0; 823 } 824 825 static int xgbe_vxlan_unset_port(struct net_device *netdev, unsigned int table, 826 unsigned int entry, struct udp_tunnel_info *ti) 827 { 828 struct xgbe_prv_data *pdata = netdev_priv(netdev); 829 830 pdata->hw_if.disable_vxlan(pdata); 831 pdata->vxlan_port = 0; 832 833 return 0; 834 } 835 836 static const struct udp_tunnel_nic_info xgbe_udp_tunnels = { 837 .set_port = xgbe_vxlan_set_port, 838 .unset_port = xgbe_vxlan_unset_port, 839 .flags = UDP_TUNNEL_NIC_INFO_OPEN_ONLY, 840 .tables = { 841 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN, }, 842 }, 843 }; 844 845 const struct udp_tunnel_nic_info *xgbe_get_udp_tunnel_info(void) 846 { 847 return &xgbe_udp_tunnels; 848 } 849 850 static void xgbe_napi_enable(struct xgbe_prv_data *pdata, unsigned int add) 851 { 852 struct xgbe_channel *channel; 853 unsigned int i; 854 855 if (pdata->per_channel_irq) { 856 for (i = 0; i < pdata->channel_count; i++) { 857 channel = pdata->channel[i]; 858 if (add) 859 netif_napi_add(pdata->netdev, &channel->napi, 860 xgbe_one_poll); 861 862 napi_enable(&channel->napi); 863 } 864 } else { 865 if (add) 866 netif_napi_add(pdata->netdev, &pdata->napi, 867 xgbe_all_poll); 868 869 napi_enable(&pdata->napi); 870 } 871 } 872 873 static void xgbe_napi_disable(struct xgbe_prv_data *pdata, unsigned int del) 874 { 875 struct xgbe_channel *channel; 876 unsigned int i; 877 878 if (pdata->per_channel_irq) { 879 for (i = 0; i < pdata->channel_count; i++) { 880 channel = pdata->channel[i]; 881 napi_disable(&channel->napi); 882 883 if (del) 884 netif_napi_del(&channel->napi); 885 } 886 } else { 887 napi_disable(&pdata->napi); 888 889 if (del) 890 netif_napi_del(&pdata->napi); 891 } 892 } 893 894 static int xgbe_request_irqs(struct xgbe_prv_data *pdata) 895 { 896 struct xgbe_channel *channel; 897 struct net_device *netdev = pdata->netdev; 898 unsigned int i; 899 int ret; 900 901 INIT_WORK(&pdata->dev_bh_work, xgbe_isr_bh_work); 902 INIT_WORK(&pdata->ecc_bh_work, xgbe_ecc_isr_bh_work); 903 904 ret = devm_request_irq(pdata->dev, pdata->dev_irq, xgbe_isr, 0, 905 netdev_name(netdev), pdata); 906 if (ret) { 907 netdev_alert(netdev, "error requesting irq %d\n", 908 pdata->dev_irq); 909 return ret; 910 } 911 912 if (pdata->vdata->ecc_support && (pdata->dev_irq != pdata->ecc_irq)) { 913 ret = devm_request_irq(pdata->dev, pdata->ecc_irq, xgbe_ecc_isr, 914 0, pdata->ecc_name, pdata); 915 if (ret) { 916 netdev_alert(netdev, "error requesting ecc irq %d\n", 917 pdata->ecc_irq); 918 goto err_dev_irq; 919 } 920 } 921 922 if (!pdata->per_channel_irq) 923 return 0; 924 925 for (i = 0; i < pdata->channel_count; i++) { 926 channel = pdata->channel[i]; 927 snprintf(channel->dma_irq_name, 928 sizeof(channel->dma_irq_name) - 1, 929 "%s-TxRx-%u", netdev_name(netdev), 930 channel->queue_index); 931 932 ret = devm_request_irq(pdata->dev, channel->dma_irq, 933 xgbe_dma_isr, 0, 934 channel->dma_irq_name, channel); 935 if (ret) { 936 netdev_alert(netdev, "error requesting irq %d\n", 937 channel->dma_irq); 938 goto err_dma_irq; 939 } 940 941 irq_set_affinity_hint(channel->dma_irq, 942 &channel->affinity_mask); 943 } 944 945 return 0; 946 947 err_dma_irq: 948 /* Using an unsigned int, 'i' will go to UINT_MAX and exit */ 949 for (i--; i < pdata->channel_count; i--) { 950 channel = pdata->channel[i]; 951 952 irq_set_affinity_hint(channel->dma_irq, NULL); 953 devm_free_irq(pdata->dev, channel->dma_irq, channel); 954 } 955 956 if (pdata->vdata->ecc_support && (pdata->dev_irq != pdata->ecc_irq)) 957 devm_free_irq(pdata->dev, pdata->ecc_irq, pdata); 958 959 err_dev_irq: 960 devm_free_irq(pdata->dev, pdata->dev_irq, pdata); 961 962 return ret; 963 } 964 965 static void xgbe_free_irqs(struct xgbe_prv_data *pdata) 966 { 967 struct xgbe_channel *channel; 968 unsigned int i; 969 970 devm_free_irq(pdata->dev, pdata->dev_irq, pdata); 971 972 cancel_work_sync(&pdata->dev_bh_work); 973 cancel_work_sync(&pdata->ecc_bh_work); 974 975 if (pdata->vdata->ecc_support && (pdata->dev_irq != pdata->ecc_irq)) 976 devm_free_irq(pdata->dev, pdata->ecc_irq, pdata); 977 978 if (!pdata->per_channel_irq) 979 return; 980 981 for (i = 0; i < pdata->channel_count; i++) { 982 channel = pdata->channel[i]; 983 984 irq_set_affinity_hint(channel->dma_irq, NULL); 985 devm_free_irq(pdata->dev, channel->dma_irq, channel); 986 } 987 } 988 989 void xgbe_init_tx_coalesce(struct xgbe_prv_data *pdata) 990 { 991 struct xgbe_hw_if *hw_if = &pdata->hw_if; 992 993 DBGPR("-->xgbe_init_tx_coalesce\n"); 994 995 pdata->tx_usecs = XGMAC_INIT_DMA_TX_USECS; 996 pdata->tx_frames = XGMAC_INIT_DMA_TX_FRAMES; 997 998 hw_if->config_tx_coalesce(pdata); 999 1000 DBGPR("<--xgbe_init_tx_coalesce\n"); 1001 } 1002 1003 void xgbe_init_rx_coalesce(struct xgbe_prv_data *pdata) 1004 { 1005 struct xgbe_hw_if *hw_if = &pdata->hw_if; 1006 1007 DBGPR("-->xgbe_init_rx_coalesce\n"); 1008 1009 pdata->rx_riwt = hw_if->usec_to_riwt(pdata, XGMAC_INIT_DMA_RX_USECS); 1010 pdata->rx_usecs = XGMAC_INIT_DMA_RX_USECS; 1011 pdata->rx_frames = XGMAC_INIT_DMA_RX_FRAMES; 1012 1013 hw_if->config_rx_coalesce(pdata); 1014 1015 DBGPR("<--xgbe_init_rx_coalesce\n"); 1016 } 1017 1018 static void xgbe_free_tx_data(struct xgbe_prv_data *pdata) 1019 { 1020 struct xgbe_desc_if *desc_if = &pdata->desc_if; 1021 struct xgbe_ring *ring; 1022 struct xgbe_ring_data *rdata; 1023 unsigned int i, j; 1024 1025 DBGPR("-->xgbe_free_tx_data\n"); 1026 1027 for (i = 0; i < pdata->channel_count; i++) { 1028 ring = pdata->channel[i]->tx_ring; 1029 if (!ring) 1030 break; 1031 1032 for (j = 0; j < ring->rdesc_count; j++) { 1033 rdata = XGBE_GET_DESC_DATA(ring, j); 1034 desc_if->unmap_rdata(pdata, rdata); 1035 } 1036 } 1037 1038 DBGPR("<--xgbe_free_tx_data\n"); 1039 } 1040 1041 static void xgbe_free_rx_data(struct xgbe_prv_data *pdata) 1042 { 1043 struct xgbe_desc_if *desc_if = &pdata->desc_if; 1044 struct xgbe_ring *ring; 1045 struct xgbe_ring_data *rdata; 1046 unsigned int i, j; 1047 1048 DBGPR("-->xgbe_free_rx_data\n"); 1049 1050 for (i = 0; i < pdata->channel_count; i++) { 1051 ring = pdata->channel[i]->rx_ring; 1052 if (!ring) 1053 break; 1054 1055 for (j = 0; j < ring->rdesc_count; j++) { 1056 rdata = XGBE_GET_DESC_DATA(ring, j); 1057 desc_if->unmap_rdata(pdata, rdata); 1058 } 1059 } 1060 1061 DBGPR("<--xgbe_free_rx_data\n"); 1062 } 1063 1064 static int xgbe_phy_reset(struct xgbe_prv_data *pdata) 1065 { 1066 pdata->phy_link = -1; 1067 pdata->phy_speed = SPEED_UNKNOWN; 1068 1069 return pdata->phy_if.phy_reset(pdata); 1070 } 1071 1072 int xgbe_powerdown(struct net_device *netdev, unsigned int caller) 1073 { 1074 struct xgbe_prv_data *pdata = netdev_priv(netdev); 1075 struct xgbe_hw_if *hw_if = &pdata->hw_if; 1076 unsigned long flags; 1077 1078 DBGPR("-->xgbe_powerdown\n"); 1079 1080 if (!netif_running(netdev) || 1081 (caller == XGMAC_IOCTL_CONTEXT && pdata->power_down)) { 1082 netdev_alert(netdev, "Device is already powered down\n"); 1083 DBGPR("<--xgbe_powerdown\n"); 1084 return -EINVAL; 1085 } 1086 1087 spin_lock_irqsave(&pdata->lock, flags); 1088 1089 if (caller == XGMAC_DRIVER_CONTEXT) 1090 netif_device_detach(netdev); 1091 1092 netif_tx_stop_all_queues(netdev); 1093 1094 xgbe_stop_timers(pdata); 1095 flush_workqueue(pdata->dev_workqueue); 1096 1097 hw_if->powerdown_tx(pdata); 1098 hw_if->powerdown_rx(pdata); 1099 1100 xgbe_napi_disable(pdata, 0); 1101 1102 pdata->power_down = 1; 1103 1104 spin_unlock_irqrestore(&pdata->lock, flags); 1105 1106 DBGPR("<--xgbe_powerdown\n"); 1107 1108 return 0; 1109 } 1110 1111 int xgbe_powerup(struct net_device *netdev, unsigned int caller) 1112 { 1113 struct xgbe_prv_data *pdata = netdev_priv(netdev); 1114 struct xgbe_hw_if *hw_if = &pdata->hw_if; 1115 unsigned long flags; 1116 1117 DBGPR("-->xgbe_powerup\n"); 1118 1119 if (!netif_running(netdev) || 1120 (caller == XGMAC_IOCTL_CONTEXT && !pdata->power_down)) { 1121 netdev_alert(netdev, "Device is already powered up\n"); 1122 DBGPR("<--xgbe_powerup\n"); 1123 return -EINVAL; 1124 } 1125 1126 spin_lock_irqsave(&pdata->lock, flags); 1127 1128 pdata->power_down = 0; 1129 1130 xgbe_napi_enable(pdata, 0); 1131 1132 hw_if->powerup_tx(pdata); 1133 hw_if->powerup_rx(pdata); 1134 1135 if (caller == XGMAC_DRIVER_CONTEXT) 1136 netif_device_attach(netdev); 1137 1138 netif_tx_start_all_queues(netdev); 1139 1140 xgbe_start_timers(pdata); 1141 1142 spin_unlock_irqrestore(&pdata->lock, flags); 1143 1144 DBGPR("<--xgbe_powerup\n"); 1145 1146 return 0; 1147 } 1148 1149 static void xgbe_free_memory(struct xgbe_prv_data *pdata) 1150 { 1151 struct xgbe_desc_if *desc_if = &pdata->desc_if; 1152 1153 /* Free the ring descriptors and buffers */ 1154 desc_if->free_ring_resources(pdata); 1155 1156 /* Free the channel and ring structures */ 1157 xgbe_free_channels(pdata); 1158 } 1159 1160 static int xgbe_alloc_memory(struct xgbe_prv_data *pdata) 1161 { 1162 struct xgbe_desc_if *desc_if = &pdata->desc_if; 1163 struct net_device *netdev = pdata->netdev; 1164 int ret; 1165 1166 if (pdata->new_tx_ring_count) { 1167 pdata->tx_ring_count = pdata->new_tx_ring_count; 1168 pdata->tx_q_count = pdata->tx_ring_count; 1169 pdata->new_tx_ring_count = 0; 1170 } 1171 1172 if (pdata->new_rx_ring_count) { 1173 pdata->rx_ring_count = pdata->new_rx_ring_count; 1174 pdata->new_rx_ring_count = 0; 1175 } 1176 1177 /* Calculate the Rx buffer size before allocating rings */ 1178 pdata->rx_buf_size = xgbe_calc_rx_buf_size(netdev, netdev->mtu); 1179 1180 /* Allocate the channel and ring structures */ 1181 ret = xgbe_alloc_channels(pdata); 1182 if (ret) 1183 return ret; 1184 1185 /* Allocate the ring descriptors and buffers */ 1186 ret = desc_if->alloc_ring_resources(pdata); 1187 if (ret) 1188 goto err_channels; 1189 1190 /* Initialize the service and Tx timers */ 1191 xgbe_init_timers(pdata); 1192 1193 return 0; 1194 1195 err_channels: 1196 xgbe_free_memory(pdata); 1197 1198 return ret; 1199 } 1200 1201 static int xgbe_start(struct xgbe_prv_data *pdata) 1202 { 1203 struct xgbe_hw_if *hw_if = &pdata->hw_if; 1204 struct xgbe_phy_if *phy_if = &pdata->phy_if; 1205 struct net_device *netdev = pdata->netdev; 1206 unsigned int i; 1207 int ret; 1208 1209 /* Set the number of queues */ 1210 ret = netif_set_real_num_tx_queues(netdev, pdata->tx_ring_count); 1211 if (ret) { 1212 netdev_err(netdev, "error setting real tx queue count\n"); 1213 return ret; 1214 } 1215 1216 ret = netif_set_real_num_rx_queues(netdev, pdata->rx_ring_count); 1217 if (ret) { 1218 netdev_err(netdev, "error setting real rx queue count\n"); 1219 return ret; 1220 } 1221 1222 /* Set RSS lookup table data for programming */ 1223 for (i = 0; i < XGBE_RSS_MAX_TABLE_SIZE; i++) 1224 XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH, 1225 i % pdata->rx_ring_count); 1226 1227 ret = hw_if->init(pdata); 1228 if (ret) 1229 return ret; 1230 1231 xgbe_napi_enable(pdata, 1); 1232 1233 ret = xgbe_request_irqs(pdata); 1234 if (ret) 1235 goto err_napi; 1236 1237 ret = phy_if->phy_start(pdata); 1238 if (ret) 1239 goto err_irqs; 1240 1241 hw_if->enable_tx(pdata); 1242 hw_if->enable_rx(pdata); 1243 1244 udp_tunnel_nic_reset_ntf(netdev); 1245 1246 netif_tx_start_all_queues(netdev); 1247 1248 xgbe_start_timers(pdata); 1249 queue_work(pdata->dev_workqueue, &pdata->service_work); 1250 1251 clear_bit(XGBE_STOPPED, &pdata->dev_state); 1252 1253 return 0; 1254 1255 err_irqs: 1256 xgbe_free_irqs(pdata); 1257 1258 err_napi: 1259 xgbe_napi_disable(pdata, 1); 1260 1261 hw_if->exit(pdata); 1262 1263 return ret; 1264 } 1265 1266 static void xgbe_stop(struct xgbe_prv_data *pdata) 1267 { 1268 struct xgbe_hw_if *hw_if = &pdata->hw_if; 1269 struct xgbe_phy_if *phy_if = &pdata->phy_if; 1270 struct xgbe_channel *channel; 1271 struct net_device *netdev = pdata->netdev; 1272 struct netdev_queue *txq; 1273 unsigned int i; 1274 1275 DBGPR("-->xgbe_stop\n"); 1276 1277 if (test_bit(XGBE_STOPPED, &pdata->dev_state)) 1278 return; 1279 1280 netif_tx_stop_all_queues(netdev); 1281 netif_carrier_off(pdata->netdev); 1282 1283 xgbe_stop_timers(pdata); 1284 flush_workqueue(pdata->dev_workqueue); 1285 1286 xgbe_vxlan_unset_port(netdev, 0, 0, NULL); 1287 1288 hw_if->disable_tx(pdata); 1289 hw_if->disable_rx(pdata); 1290 1291 phy_if->phy_stop(pdata); 1292 1293 xgbe_free_irqs(pdata); 1294 1295 xgbe_napi_disable(pdata, 1); 1296 1297 hw_if->exit(pdata); 1298 1299 for (i = 0; i < pdata->channel_count; i++) { 1300 channel = pdata->channel[i]; 1301 if (!channel->tx_ring) 1302 continue; 1303 1304 txq = netdev_get_tx_queue(netdev, channel->queue_index); 1305 netdev_tx_reset_queue(txq); 1306 } 1307 1308 set_bit(XGBE_STOPPED, &pdata->dev_state); 1309 1310 DBGPR("<--xgbe_stop\n"); 1311 } 1312 1313 static void xgbe_stopdev(struct work_struct *work) 1314 { 1315 struct xgbe_prv_data *pdata = container_of(work, 1316 struct xgbe_prv_data, 1317 stopdev_work); 1318 1319 rtnl_lock(); 1320 1321 xgbe_stop(pdata); 1322 1323 xgbe_free_tx_data(pdata); 1324 xgbe_free_rx_data(pdata); 1325 1326 rtnl_unlock(); 1327 1328 netdev_alert(pdata->netdev, "device stopped\n"); 1329 } 1330 1331 void xgbe_full_restart_dev(struct xgbe_prv_data *pdata) 1332 { 1333 /* If not running, "restart" will happen on open */ 1334 if (!netif_running(pdata->netdev)) 1335 return; 1336 1337 xgbe_stop(pdata); 1338 1339 xgbe_free_memory(pdata); 1340 xgbe_alloc_memory(pdata); 1341 1342 xgbe_start(pdata); 1343 } 1344 1345 void xgbe_restart_dev(struct xgbe_prv_data *pdata) 1346 { 1347 /* If not running, "restart" will happen on open */ 1348 if (!netif_running(pdata->netdev)) 1349 return; 1350 1351 xgbe_stop(pdata); 1352 1353 xgbe_free_tx_data(pdata); 1354 xgbe_free_rx_data(pdata); 1355 1356 xgbe_start(pdata); 1357 } 1358 1359 static void xgbe_restart(struct work_struct *work) 1360 { 1361 struct xgbe_prv_data *pdata = container_of(work, 1362 struct xgbe_prv_data, 1363 restart_work); 1364 1365 rtnl_lock(); 1366 1367 xgbe_restart_dev(pdata); 1368 1369 rtnl_unlock(); 1370 } 1371 1372 static void xgbe_tx_tstamp(struct work_struct *work) 1373 { 1374 struct xgbe_prv_data *pdata = container_of(work, 1375 struct xgbe_prv_data, 1376 tx_tstamp_work); 1377 struct skb_shared_hwtstamps hwtstamps; 1378 u64 nsec; 1379 unsigned long flags; 1380 1381 spin_lock_irqsave(&pdata->tstamp_lock, flags); 1382 if (!pdata->tx_tstamp_skb) 1383 goto unlock; 1384 1385 if (pdata->tx_tstamp) { 1386 nsec = timecounter_cyc2time(&pdata->tstamp_tc, 1387 pdata->tx_tstamp); 1388 1389 memset(&hwtstamps, 0, sizeof(hwtstamps)); 1390 hwtstamps.hwtstamp = ns_to_ktime(nsec); 1391 skb_tstamp_tx(pdata->tx_tstamp_skb, &hwtstamps); 1392 } 1393 1394 dev_kfree_skb_any(pdata->tx_tstamp_skb); 1395 1396 pdata->tx_tstamp_skb = NULL; 1397 1398 unlock: 1399 spin_unlock_irqrestore(&pdata->tstamp_lock, flags); 1400 } 1401 1402 static int xgbe_get_hwtstamp_settings(struct xgbe_prv_data *pdata, 1403 struct ifreq *ifreq) 1404 { 1405 if (copy_to_user(ifreq->ifr_data, &pdata->tstamp_config, 1406 sizeof(pdata->tstamp_config))) 1407 return -EFAULT; 1408 1409 return 0; 1410 } 1411 1412 static int xgbe_set_hwtstamp_settings(struct xgbe_prv_data *pdata, 1413 struct ifreq *ifreq) 1414 { 1415 struct hwtstamp_config config; 1416 unsigned int mac_tscr; 1417 1418 if (copy_from_user(&config, ifreq->ifr_data, sizeof(config))) 1419 return -EFAULT; 1420 1421 mac_tscr = 0; 1422 1423 switch (config.tx_type) { 1424 case HWTSTAMP_TX_OFF: 1425 break; 1426 1427 case HWTSTAMP_TX_ON: 1428 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 1429 break; 1430 1431 default: 1432 return -ERANGE; 1433 } 1434 1435 switch (config.rx_filter) { 1436 case HWTSTAMP_FILTER_NONE: 1437 break; 1438 1439 case HWTSTAMP_FILTER_NTP_ALL: 1440 case HWTSTAMP_FILTER_ALL: 1441 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 1); 1442 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 1443 break; 1444 1445 /* PTP v2, UDP, any kind of event packet */ 1446 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1447 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); 1448 fallthrough; /* to PTP v1, UDP, any kind of event packet */ 1449 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1450 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); 1451 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); 1452 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1); 1453 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 1454 break; 1455 1456 /* PTP v2, UDP, Sync packet */ 1457 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1458 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); 1459 fallthrough; /* to PTP v1, UDP, Sync packet */ 1460 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1461 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); 1462 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); 1463 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); 1464 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 1465 break; 1466 1467 /* PTP v2, UDP, Delay_req packet */ 1468 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1469 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); 1470 fallthrough; /* to PTP v1, UDP, Delay_req packet */ 1471 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1472 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); 1473 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); 1474 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); 1475 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1); 1476 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 1477 break; 1478 1479 /* 802.AS1, Ethernet, any kind of event packet */ 1480 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1481 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1); 1482 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1); 1483 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 1484 break; 1485 1486 /* 802.AS1, Ethernet, Sync packet */ 1487 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1488 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1); 1489 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); 1490 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 1491 break; 1492 1493 /* 802.AS1, Ethernet, Delay_req packet */ 1494 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1495 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1); 1496 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1); 1497 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); 1498 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 1499 break; 1500 1501 /* PTP v2/802.AS1, any layer, any kind of event packet */ 1502 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1503 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); 1504 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1); 1505 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); 1506 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); 1507 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1); 1508 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 1509 break; 1510 1511 /* PTP v2/802.AS1, any layer, Sync packet */ 1512 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1513 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); 1514 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1); 1515 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); 1516 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); 1517 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); 1518 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 1519 break; 1520 1521 /* PTP v2/802.AS1, any layer, Delay_req packet */ 1522 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1523 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); 1524 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1); 1525 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); 1526 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); 1527 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1); 1528 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); 1529 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 1530 break; 1531 1532 default: 1533 return -ERANGE; 1534 } 1535 1536 pdata->hw_if.config_tstamp(pdata, mac_tscr); 1537 1538 memcpy(&pdata->tstamp_config, &config, sizeof(config)); 1539 1540 return 0; 1541 } 1542 1543 static void xgbe_prep_tx_tstamp(struct xgbe_prv_data *pdata, 1544 struct sk_buff *skb, 1545 struct xgbe_packet_data *packet) 1546 { 1547 unsigned long flags; 1548 1549 if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP)) { 1550 spin_lock_irqsave(&pdata->tstamp_lock, flags); 1551 if (pdata->tx_tstamp_skb) { 1552 /* Another timestamp in progress, ignore this one */ 1553 XGMAC_SET_BITS(packet->attributes, 1554 TX_PACKET_ATTRIBUTES, PTP, 0); 1555 } else { 1556 pdata->tx_tstamp_skb = skb_get(skb); 1557 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1558 } 1559 spin_unlock_irqrestore(&pdata->tstamp_lock, flags); 1560 } 1561 1562 skb_tx_timestamp(skb); 1563 } 1564 1565 static void xgbe_prep_vlan(struct sk_buff *skb, struct xgbe_packet_data *packet) 1566 { 1567 if (skb_vlan_tag_present(skb)) 1568 packet->vlan_ctag = skb_vlan_tag_get(skb); 1569 } 1570 1571 static int xgbe_prep_tso(struct sk_buff *skb, struct xgbe_packet_data *packet) 1572 { 1573 int ret; 1574 1575 if (!XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, 1576 TSO_ENABLE)) 1577 return 0; 1578 1579 ret = skb_cow_head(skb, 0); 1580 if (ret) 1581 return ret; 1582 1583 if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, VXLAN)) { 1584 packet->header_len = skb_inner_tcp_all_headers(skb); 1585 packet->tcp_header_len = inner_tcp_hdrlen(skb); 1586 } else { 1587 packet->header_len = skb_tcp_all_headers(skb); 1588 packet->tcp_header_len = tcp_hdrlen(skb); 1589 } 1590 packet->tcp_payload_len = skb->len - packet->header_len; 1591 packet->mss = skb_shinfo(skb)->gso_size; 1592 1593 DBGPR(" packet->header_len=%u\n", packet->header_len); 1594 DBGPR(" packet->tcp_header_len=%u, packet->tcp_payload_len=%u\n", 1595 packet->tcp_header_len, packet->tcp_payload_len); 1596 DBGPR(" packet->mss=%u\n", packet->mss); 1597 1598 /* Update the number of packets that will ultimately be transmitted 1599 * along with the extra bytes for each extra packet 1600 */ 1601 packet->tx_packets = skb_shinfo(skb)->gso_segs; 1602 packet->tx_bytes += (packet->tx_packets - 1) * packet->header_len; 1603 1604 return 0; 1605 } 1606 1607 static bool xgbe_is_vxlan(struct sk_buff *skb) 1608 { 1609 if (!skb->encapsulation) 1610 return false; 1611 1612 if (skb->ip_summed != CHECKSUM_PARTIAL) 1613 return false; 1614 1615 switch (skb->protocol) { 1616 case htons(ETH_P_IP): 1617 if (ip_hdr(skb)->protocol != IPPROTO_UDP) 1618 return false; 1619 break; 1620 1621 case htons(ETH_P_IPV6): 1622 if (ipv6_hdr(skb)->nexthdr != IPPROTO_UDP) 1623 return false; 1624 break; 1625 1626 default: 1627 return false; 1628 } 1629 1630 if (skb->inner_protocol_type != ENCAP_TYPE_ETHER || 1631 skb->inner_protocol != htons(ETH_P_TEB) || 1632 (skb_inner_mac_header(skb) - skb_transport_header(skb) != 1633 sizeof(struct udphdr) + sizeof(struct vxlanhdr))) 1634 return false; 1635 1636 return true; 1637 } 1638 1639 static int xgbe_is_tso(struct sk_buff *skb) 1640 { 1641 if (skb->ip_summed != CHECKSUM_PARTIAL) 1642 return 0; 1643 1644 if (!skb_is_gso(skb)) 1645 return 0; 1646 1647 DBGPR(" TSO packet to be processed\n"); 1648 1649 return 1; 1650 } 1651 1652 static void xgbe_packet_info(struct xgbe_prv_data *pdata, 1653 struct xgbe_ring *ring, struct sk_buff *skb, 1654 struct xgbe_packet_data *packet) 1655 { 1656 skb_frag_t *frag; 1657 unsigned int context_desc; 1658 unsigned int len; 1659 unsigned int i; 1660 1661 packet->skb = skb; 1662 1663 context_desc = 0; 1664 packet->rdesc_count = 0; 1665 1666 packet->tx_packets = 1; 1667 packet->tx_bytes = skb->len; 1668 1669 if (xgbe_is_tso(skb)) { 1670 /* TSO requires an extra descriptor if mss is different */ 1671 if (skb_shinfo(skb)->gso_size != ring->tx.cur_mss) { 1672 context_desc = 1; 1673 packet->rdesc_count++; 1674 } 1675 1676 /* TSO requires an extra descriptor for TSO header */ 1677 packet->rdesc_count++; 1678 1679 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, 1680 TSO_ENABLE, 1); 1681 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, 1682 CSUM_ENABLE, 1); 1683 } else if (skb->ip_summed == CHECKSUM_PARTIAL) 1684 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, 1685 CSUM_ENABLE, 1); 1686 1687 if (xgbe_is_vxlan(skb)) 1688 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, 1689 VXLAN, 1); 1690 1691 if (skb_vlan_tag_present(skb)) { 1692 /* VLAN requires an extra descriptor if tag is different */ 1693 if (skb_vlan_tag_get(skb) != ring->tx.cur_vlan_ctag) 1694 /* We can share with the TSO context descriptor */ 1695 if (!context_desc) { 1696 context_desc = 1; 1697 packet->rdesc_count++; 1698 } 1699 1700 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, 1701 VLAN_CTAG, 1); 1702 } 1703 1704 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 1705 (pdata->tstamp_config.tx_type == HWTSTAMP_TX_ON)) 1706 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, 1707 PTP, 1); 1708 1709 for (len = skb_headlen(skb); len;) { 1710 packet->rdesc_count++; 1711 len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE); 1712 } 1713 1714 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1715 frag = &skb_shinfo(skb)->frags[i]; 1716 for (len = skb_frag_size(frag); len; ) { 1717 packet->rdesc_count++; 1718 len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE); 1719 } 1720 } 1721 } 1722 1723 static int xgbe_open(struct net_device *netdev) 1724 { 1725 struct xgbe_prv_data *pdata = netdev_priv(netdev); 1726 int ret; 1727 1728 /* Create the various names based on netdev name */ 1729 snprintf(pdata->an_name, sizeof(pdata->an_name) - 1, "%s-pcs", 1730 netdev_name(netdev)); 1731 1732 snprintf(pdata->ecc_name, sizeof(pdata->ecc_name) - 1, "%s-ecc", 1733 netdev_name(netdev)); 1734 1735 snprintf(pdata->i2c_name, sizeof(pdata->i2c_name) - 1, "%s-i2c", 1736 netdev_name(netdev)); 1737 1738 /* Create workqueues */ 1739 pdata->dev_workqueue = 1740 create_singlethread_workqueue(netdev_name(netdev)); 1741 if (!pdata->dev_workqueue) { 1742 netdev_err(netdev, "device workqueue creation failed\n"); 1743 return -ENOMEM; 1744 } 1745 1746 pdata->an_workqueue = 1747 create_singlethread_workqueue(pdata->an_name); 1748 if (!pdata->an_workqueue) { 1749 netdev_err(netdev, "phy workqueue creation failed\n"); 1750 ret = -ENOMEM; 1751 goto err_dev_wq; 1752 } 1753 1754 /* Reset the phy settings */ 1755 ret = xgbe_phy_reset(pdata); 1756 if (ret) 1757 goto err_an_wq; 1758 1759 /* Enable the clocks */ 1760 ret = clk_prepare_enable(pdata->sysclk); 1761 if (ret) { 1762 netdev_alert(netdev, "dma clk_prepare_enable failed\n"); 1763 goto err_an_wq; 1764 } 1765 1766 ret = clk_prepare_enable(pdata->ptpclk); 1767 if (ret) { 1768 netdev_alert(netdev, "ptp clk_prepare_enable failed\n"); 1769 goto err_sysclk; 1770 } 1771 1772 INIT_WORK(&pdata->service_work, xgbe_service); 1773 INIT_WORK(&pdata->restart_work, xgbe_restart); 1774 INIT_WORK(&pdata->stopdev_work, xgbe_stopdev); 1775 INIT_WORK(&pdata->tx_tstamp_work, xgbe_tx_tstamp); 1776 1777 ret = xgbe_alloc_memory(pdata); 1778 if (ret) 1779 goto err_ptpclk; 1780 1781 ret = xgbe_start(pdata); 1782 if (ret) 1783 goto err_mem; 1784 1785 clear_bit(XGBE_DOWN, &pdata->dev_state); 1786 1787 return 0; 1788 1789 err_mem: 1790 xgbe_free_memory(pdata); 1791 1792 err_ptpclk: 1793 clk_disable_unprepare(pdata->ptpclk); 1794 1795 err_sysclk: 1796 clk_disable_unprepare(pdata->sysclk); 1797 1798 err_an_wq: 1799 destroy_workqueue(pdata->an_workqueue); 1800 1801 err_dev_wq: 1802 destroy_workqueue(pdata->dev_workqueue); 1803 1804 return ret; 1805 } 1806 1807 static int xgbe_close(struct net_device *netdev) 1808 { 1809 struct xgbe_prv_data *pdata = netdev_priv(netdev); 1810 1811 /* Stop the device */ 1812 xgbe_stop(pdata); 1813 1814 xgbe_free_memory(pdata); 1815 1816 /* Disable the clocks */ 1817 clk_disable_unprepare(pdata->ptpclk); 1818 clk_disable_unprepare(pdata->sysclk); 1819 1820 destroy_workqueue(pdata->an_workqueue); 1821 1822 destroy_workqueue(pdata->dev_workqueue); 1823 1824 set_bit(XGBE_DOWN, &pdata->dev_state); 1825 1826 return 0; 1827 } 1828 1829 static netdev_tx_t xgbe_xmit(struct sk_buff *skb, struct net_device *netdev) 1830 { 1831 struct xgbe_prv_data *pdata = netdev_priv(netdev); 1832 struct xgbe_hw_if *hw_if = &pdata->hw_if; 1833 struct xgbe_desc_if *desc_if = &pdata->desc_if; 1834 struct xgbe_channel *channel; 1835 struct xgbe_ring *ring; 1836 struct xgbe_packet_data *packet; 1837 struct netdev_queue *txq; 1838 netdev_tx_t ret; 1839 1840 DBGPR("-->xgbe_xmit: skb->len = %d\n", skb->len); 1841 1842 channel = pdata->channel[skb->queue_mapping]; 1843 txq = netdev_get_tx_queue(netdev, channel->queue_index); 1844 ring = channel->tx_ring; 1845 packet = &ring->packet_data; 1846 1847 ret = NETDEV_TX_OK; 1848 1849 if (skb->len == 0) { 1850 netif_err(pdata, tx_err, netdev, 1851 "empty skb received from stack\n"); 1852 dev_kfree_skb_any(skb); 1853 goto tx_netdev_return; 1854 } 1855 1856 /* Calculate preliminary packet info */ 1857 memset(packet, 0, sizeof(*packet)); 1858 xgbe_packet_info(pdata, ring, skb, packet); 1859 1860 /* Check that there are enough descriptors available */ 1861 ret = xgbe_maybe_stop_tx_queue(channel, ring, packet->rdesc_count); 1862 if (ret) 1863 goto tx_netdev_return; 1864 1865 ret = xgbe_prep_tso(skb, packet); 1866 if (ret) { 1867 netif_err(pdata, tx_err, netdev, 1868 "error processing TSO packet\n"); 1869 dev_kfree_skb_any(skb); 1870 goto tx_netdev_return; 1871 } 1872 xgbe_prep_vlan(skb, packet); 1873 1874 if (!desc_if->map_tx_skb(channel, skb)) { 1875 dev_kfree_skb_any(skb); 1876 goto tx_netdev_return; 1877 } 1878 1879 xgbe_prep_tx_tstamp(pdata, skb, packet); 1880 1881 /* Report on the actual number of bytes (to be) sent */ 1882 netdev_tx_sent_queue(txq, packet->tx_bytes); 1883 1884 /* Configure required descriptor fields for transmission */ 1885 hw_if->dev_xmit(channel); 1886 1887 if (netif_msg_pktdata(pdata)) 1888 xgbe_print_pkt(netdev, skb, true); 1889 1890 /* Stop the queue in advance if there may not be enough descriptors */ 1891 xgbe_maybe_stop_tx_queue(channel, ring, XGBE_TX_MAX_DESCS); 1892 1893 ret = NETDEV_TX_OK; 1894 1895 tx_netdev_return: 1896 return ret; 1897 } 1898 1899 static void xgbe_set_rx_mode(struct net_device *netdev) 1900 { 1901 struct xgbe_prv_data *pdata = netdev_priv(netdev); 1902 struct xgbe_hw_if *hw_if = &pdata->hw_if; 1903 1904 DBGPR("-->xgbe_set_rx_mode\n"); 1905 1906 hw_if->config_rx_mode(pdata); 1907 1908 DBGPR("<--xgbe_set_rx_mode\n"); 1909 } 1910 1911 static int xgbe_set_mac_address(struct net_device *netdev, void *addr) 1912 { 1913 struct xgbe_prv_data *pdata = netdev_priv(netdev); 1914 struct xgbe_hw_if *hw_if = &pdata->hw_if; 1915 struct sockaddr *saddr = addr; 1916 1917 DBGPR("-->xgbe_set_mac_address\n"); 1918 1919 if (!is_valid_ether_addr(saddr->sa_data)) 1920 return -EADDRNOTAVAIL; 1921 1922 eth_hw_addr_set(netdev, saddr->sa_data); 1923 1924 hw_if->set_mac_address(pdata, netdev->dev_addr); 1925 1926 DBGPR("<--xgbe_set_mac_address\n"); 1927 1928 return 0; 1929 } 1930 1931 static int xgbe_ioctl(struct net_device *netdev, struct ifreq *ifreq, int cmd) 1932 { 1933 struct xgbe_prv_data *pdata = netdev_priv(netdev); 1934 int ret; 1935 1936 switch (cmd) { 1937 case SIOCGHWTSTAMP: 1938 ret = xgbe_get_hwtstamp_settings(pdata, ifreq); 1939 break; 1940 1941 case SIOCSHWTSTAMP: 1942 ret = xgbe_set_hwtstamp_settings(pdata, ifreq); 1943 break; 1944 1945 default: 1946 ret = -EOPNOTSUPP; 1947 } 1948 1949 return ret; 1950 } 1951 1952 static int xgbe_change_mtu(struct net_device *netdev, int mtu) 1953 { 1954 struct xgbe_prv_data *pdata = netdev_priv(netdev); 1955 int ret; 1956 1957 DBGPR("-->xgbe_change_mtu\n"); 1958 1959 ret = xgbe_calc_rx_buf_size(netdev, mtu); 1960 if (ret < 0) 1961 return ret; 1962 1963 pdata->rx_buf_size = ret; 1964 WRITE_ONCE(netdev->mtu, mtu); 1965 1966 xgbe_restart_dev(pdata); 1967 1968 DBGPR("<--xgbe_change_mtu\n"); 1969 1970 return 0; 1971 } 1972 1973 static void xgbe_tx_timeout(struct net_device *netdev, unsigned int txqueue) 1974 { 1975 struct xgbe_prv_data *pdata = netdev_priv(netdev); 1976 1977 netdev_warn(netdev, "tx timeout, device restarting\n"); 1978 schedule_work(&pdata->restart_work); 1979 } 1980 1981 static void xgbe_get_stats64(struct net_device *netdev, 1982 struct rtnl_link_stats64 *s) 1983 { 1984 struct xgbe_prv_data *pdata = netdev_priv(netdev); 1985 struct xgbe_mmc_stats *pstats = &pdata->mmc_stats; 1986 1987 DBGPR("-->%s\n", __func__); 1988 1989 pdata->hw_if.read_mmc_stats(pdata); 1990 1991 s->rx_packets = pstats->rxframecount_gb; 1992 s->rx_bytes = pstats->rxoctetcount_gb; 1993 s->rx_errors = pstats->rxframecount_gb - 1994 pstats->rxbroadcastframes_g - 1995 pstats->rxmulticastframes_g - 1996 pstats->rxunicastframes_g; 1997 s->multicast = pstats->rxmulticastframes_g; 1998 s->rx_length_errors = pstats->rxlengtherror; 1999 s->rx_crc_errors = pstats->rxcrcerror; 2000 s->rx_fifo_errors = pstats->rxfifooverflow; 2001 2002 s->tx_packets = pstats->txframecount_gb; 2003 s->tx_bytes = pstats->txoctetcount_gb; 2004 s->tx_errors = pstats->txframecount_gb - pstats->txframecount_g; 2005 s->tx_dropped = netdev->stats.tx_dropped; 2006 2007 DBGPR("<--%s\n", __func__); 2008 } 2009 2010 static int xgbe_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, 2011 u16 vid) 2012 { 2013 struct xgbe_prv_data *pdata = netdev_priv(netdev); 2014 struct xgbe_hw_if *hw_if = &pdata->hw_if; 2015 2016 DBGPR("-->%s\n", __func__); 2017 2018 set_bit(vid, pdata->active_vlans); 2019 hw_if->update_vlan_hash_table(pdata); 2020 2021 DBGPR("<--%s\n", __func__); 2022 2023 return 0; 2024 } 2025 2026 static int xgbe_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, 2027 u16 vid) 2028 { 2029 struct xgbe_prv_data *pdata = netdev_priv(netdev); 2030 struct xgbe_hw_if *hw_if = &pdata->hw_if; 2031 2032 DBGPR("-->%s\n", __func__); 2033 2034 clear_bit(vid, pdata->active_vlans); 2035 hw_if->update_vlan_hash_table(pdata); 2036 2037 DBGPR("<--%s\n", __func__); 2038 2039 return 0; 2040 } 2041 2042 #ifdef CONFIG_NET_POLL_CONTROLLER 2043 static void xgbe_poll_controller(struct net_device *netdev) 2044 { 2045 struct xgbe_prv_data *pdata = netdev_priv(netdev); 2046 struct xgbe_channel *channel; 2047 unsigned int i; 2048 2049 DBGPR("-->xgbe_poll_controller\n"); 2050 2051 if (pdata->per_channel_irq) { 2052 for (i = 0; i < pdata->channel_count; i++) { 2053 channel = pdata->channel[i]; 2054 xgbe_dma_isr(channel->dma_irq, channel); 2055 } 2056 } else { 2057 disable_irq(pdata->dev_irq); 2058 xgbe_isr(pdata->dev_irq, pdata); 2059 enable_irq(pdata->dev_irq); 2060 } 2061 2062 DBGPR("<--xgbe_poll_controller\n"); 2063 } 2064 #endif /* End CONFIG_NET_POLL_CONTROLLER */ 2065 2066 static int xgbe_setup_tc(struct net_device *netdev, enum tc_setup_type type, 2067 void *type_data) 2068 { 2069 struct xgbe_prv_data *pdata = netdev_priv(netdev); 2070 struct tc_mqprio_qopt *mqprio = type_data; 2071 u8 tc; 2072 2073 if (type != TC_SETUP_QDISC_MQPRIO) 2074 return -EOPNOTSUPP; 2075 2076 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; 2077 tc = mqprio->num_tc; 2078 2079 if (tc > pdata->hw_feat.tc_cnt) 2080 return -EINVAL; 2081 2082 pdata->num_tcs = tc; 2083 pdata->hw_if.config_tc(pdata); 2084 2085 return 0; 2086 } 2087 2088 static netdev_features_t xgbe_fix_features(struct net_device *netdev, 2089 netdev_features_t features) 2090 { 2091 struct xgbe_prv_data *pdata = netdev_priv(netdev); 2092 netdev_features_t vxlan_base; 2093 2094 vxlan_base = NETIF_F_GSO_UDP_TUNNEL | NETIF_F_RX_UDP_TUNNEL_PORT; 2095 2096 if (!pdata->hw_feat.vxn) 2097 return features; 2098 2099 /* VXLAN CSUM requires VXLAN base */ 2100 if ((features & NETIF_F_GSO_UDP_TUNNEL_CSUM) && 2101 !(features & NETIF_F_GSO_UDP_TUNNEL)) { 2102 netdev_notice(netdev, 2103 "forcing tx udp tunnel support\n"); 2104 features |= NETIF_F_GSO_UDP_TUNNEL; 2105 } 2106 2107 /* Can't do one without doing the other */ 2108 if ((features & vxlan_base) != vxlan_base) { 2109 netdev_notice(netdev, 2110 "forcing both tx and rx udp tunnel support\n"); 2111 features |= vxlan_base; 2112 } 2113 2114 if (features & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)) { 2115 if (!(features & NETIF_F_GSO_UDP_TUNNEL_CSUM)) { 2116 netdev_notice(netdev, 2117 "forcing tx udp tunnel checksumming on\n"); 2118 features |= NETIF_F_GSO_UDP_TUNNEL_CSUM; 2119 } 2120 } else { 2121 if (features & NETIF_F_GSO_UDP_TUNNEL_CSUM) { 2122 netdev_notice(netdev, 2123 "forcing tx udp tunnel checksumming off\n"); 2124 features &= ~NETIF_F_GSO_UDP_TUNNEL_CSUM; 2125 } 2126 } 2127 2128 return features; 2129 } 2130 2131 static int xgbe_set_features(struct net_device *netdev, 2132 netdev_features_t features) 2133 { 2134 struct xgbe_prv_data *pdata = netdev_priv(netdev); 2135 struct xgbe_hw_if *hw_if = &pdata->hw_if; 2136 netdev_features_t rxhash, rxcsum, rxvlan, rxvlan_filter; 2137 int ret = 0; 2138 2139 rxhash = pdata->netdev_features & NETIF_F_RXHASH; 2140 rxcsum = pdata->netdev_features & NETIF_F_RXCSUM; 2141 rxvlan = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_RX; 2142 rxvlan_filter = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_FILTER; 2143 2144 if ((features & NETIF_F_RXHASH) && !rxhash) 2145 ret = hw_if->enable_rss(pdata); 2146 else if (!(features & NETIF_F_RXHASH) && rxhash) 2147 ret = hw_if->disable_rss(pdata); 2148 if (ret) 2149 return ret; 2150 2151 if ((features & NETIF_F_RXCSUM) && !rxcsum) 2152 hw_if->enable_rx_csum(pdata); 2153 else if (!(features & NETIF_F_RXCSUM) && rxcsum) 2154 hw_if->disable_rx_csum(pdata); 2155 2156 if ((features & NETIF_F_HW_VLAN_CTAG_RX) && !rxvlan) 2157 hw_if->enable_rx_vlan_stripping(pdata); 2158 else if (!(features & NETIF_F_HW_VLAN_CTAG_RX) && rxvlan) 2159 hw_if->disable_rx_vlan_stripping(pdata); 2160 2161 if ((features & NETIF_F_HW_VLAN_CTAG_FILTER) && !rxvlan_filter) 2162 hw_if->enable_rx_vlan_filtering(pdata); 2163 else if (!(features & NETIF_F_HW_VLAN_CTAG_FILTER) && rxvlan_filter) 2164 hw_if->disable_rx_vlan_filtering(pdata); 2165 2166 pdata->netdev_features = features; 2167 2168 DBGPR("<--xgbe_set_features\n"); 2169 2170 return 0; 2171 } 2172 2173 static netdev_features_t xgbe_features_check(struct sk_buff *skb, 2174 struct net_device *netdev, 2175 netdev_features_t features) 2176 { 2177 features = vlan_features_check(skb, features); 2178 features = vxlan_features_check(skb, features); 2179 2180 return features; 2181 } 2182 2183 static const struct net_device_ops xgbe_netdev_ops = { 2184 .ndo_open = xgbe_open, 2185 .ndo_stop = xgbe_close, 2186 .ndo_start_xmit = xgbe_xmit, 2187 .ndo_set_rx_mode = xgbe_set_rx_mode, 2188 .ndo_set_mac_address = xgbe_set_mac_address, 2189 .ndo_validate_addr = eth_validate_addr, 2190 .ndo_eth_ioctl = xgbe_ioctl, 2191 .ndo_change_mtu = xgbe_change_mtu, 2192 .ndo_tx_timeout = xgbe_tx_timeout, 2193 .ndo_get_stats64 = xgbe_get_stats64, 2194 .ndo_vlan_rx_add_vid = xgbe_vlan_rx_add_vid, 2195 .ndo_vlan_rx_kill_vid = xgbe_vlan_rx_kill_vid, 2196 #ifdef CONFIG_NET_POLL_CONTROLLER 2197 .ndo_poll_controller = xgbe_poll_controller, 2198 #endif 2199 .ndo_setup_tc = xgbe_setup_tc, 2200 .ndo_fix_features = xgbe_fix_features, 2201 .ndo_set_features = xgbe_set_features, 2202 .ndo_features_check = xgbe_features_check, 2203 }; 2204 2205 const struct net_device_ops *xgbe_get_netdev_ops(void) 2206 { 2207 return &xgbe_netdev_ops; 2208 } 2209 2210 static void xgbe_rx_refresh(struct xgbe_channel *channel) 2211 { 2212 struct xgbe_prv_data *pdata = channel->pdata; 2213 struct xgbe_hw_if *hw_if = &pdata->hw_if; 2214 struct xgbe_desc_if *desc_if = &pdata->desc_if; 2215 struct xgbe_ring *ring = channel->rx_ring; 2216 struct xgbe_ring_data *rdata; 2217 2218 while (ring->dirty != ring->cur) { 2219 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty); 2220 2221 /* Reset rdata values */ 2222 desc_if->unmap_rdata(pdata, rdata); 2223 2224 if (desc_if->map_rx_buffer(pdata, ring, rdata)) 2225 break; 2226 2227 hw_if->rx_desc_reset(pdata, rdata, ring->dirty); 2228 2229 ring->dirty++; 2230 } 2231 2232 /* Make sure everything is written before the register write */ 2233 wmb(); 2234 2235 /* Update the Rx Tail Pointer Register with address of 2236 * the last cleaned entry */ 2237 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty - 1); 2238 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO, 2239 lower_32_bits(rdata->rdesc_dma)); 2240 } 2241 2242 static struct sk_buff *xgbe_create_skb(struct xgbe_prv_data *pdata, 2243 struct napi_struct *napi, 2244 struct xgbe_ring_data *rdata, 2245 unsigned int len) 2246 { 2247 struct sk_buff *skb; 2248 u8 *packet; 2249 2250 skb = napi_alloc_skb(napi, rdata->rx.hdr.dma_len); 2251 if (!skb) 2252 return NULL; 2253 2254 /* Pull in the header buffer which may contain just the header 2255 * or the header plus data 2256 */ 2257 dma_sync_single_range_for_cpu(pdata->dev, rdata->rx.hdr.dma_base, 2258 rdata->rx.hdr.dma_off, 2259 rdata->rx.hdr.dma_len, DMA_FROM_DEVICE); 2260 2261 packet = page_address(rdata->rx.hdr.pa.pages) + 2262 rdata->rx.hdr.pa.pages_offset; 2263 skb_copy_to_linear_data(skb, packet, len); 2264 skb_put(skb, len); 2265 2266 return skb; 2267 } 2268 2269 static unsigned int xgbe_rx_buf1_len(struct xgbe_ring_data *rdata, 2270 struct xgbe_packet_data *packet) 2271 { 2272 /* Always zero if not the first descriptor */ 2273 if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, FIRST)) 2274 return 0; 2275 2276 /* First descriptor with split header, return header length */ 2277 if (rdata->rx.hdr_len) 2278 return rdata->rx.hdr_len; 2279 2280 /* First descriptor but not the last descriptor and no split header, 2281 * so the full buffer was used 2282 */ 2283 if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, LAST)) 2284 return rdata->rx.hdr.dma_len; 2285 2286 /* First descriptor and last descriptor and no split header, so 2287 * calculate how much of the buffer was used 2288 */ 2289 return min_t(unsigned int, rdata->rx.hdr.dma_len, rdata->rx.len); 2290 } 2291 2292 static unsigned int xgbe_rx_buf2_len(struct xgbe_ring_data *rdata, 2293 struct xgbe_packet_data *packet, 2294 unsigned int len) 2295 { 2296 /* Always the full buffer if not the last descriptor */ 2297 if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, LAST)) 2298 return rdata->rx.buf.dma_len; 2299 2300 /* Last descriptor so calculate how much of the buffer was used 2301 * for the last bit of data 2302 */ 2303 return rdata->rx.len - len; 2304 } 2305 2306 static int xgbe_tx_poll(struct xgbe_channel *channel) 2307 { 2308 struct xgbe_prv_data *pdata = channel->pdata; 2309 struct xgbe_hw_if *hw_if = &pdata->hw_if; 2310 struct xgbe_desc_if *desc_if = &pdata->desc_if; 2311 struct xgbe_ring *ring = channel->tx_ring; 2312 struct xgbe_ring_data *rdata; 2313 struct xgbe_ring_desc *rdesc; 2314 struct net_device *netdev = pdata->netdev; 2315 struct netdev_queue *txq; 2316 int processed = 0; 2317 unsigned int tx_packets = 0, tx_bytes = 0; 2318 unsigned int cur; 2319 2320 DBGPR("-->xgbe_tx_poll\n"); 2321 2322 /* Nothing to do if there isn't a Tx ring for this channel */ 2323 if (!ring) 2324 return 0; 2325 2326 cur = ring->cur; 2327 2328 /* Be sure we get ring->cur before accessing descriptor data */ 2329 smp_rmb(); 2330 2331 txq = netdev_get_tx_queue(netdev, channel->queue_index); 2332 2333 while ((processed < XGBE_TX_DESC_MAX_PROC) && 2334 (ring->dirty != cur)) { 2335 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty); 2336 rdesc = rdata->rdesc; 2337 2338 if (!hw_if->tx_complete(rdesc)) 2339 break; 2340 2341 /* Make sure descriptor fields are read after reading the OWN 2342 * bit */ 2343 dma_rmb(); 2344 2345 if (netif_msg_tx_done(pdata)) 2346 xgbe_dump_tx_desc(pdata, ring, ring->dirty, 1, 0); 2347 2348 if (hw_if->is_last_desc(rdesc)) { 2349 tx_packets += rdata->tx.packets; 2350 tx_bytes += rdata->tx.bytes; 2351 } 2352 2353 /* Free the SKB and reset the descriptor for re-use */ 2354 desc_if->unmap_rdata(pdata, rdata); 2355 hw_if->tx_desc_reset(rdata); 2356 2357 processed++; 2358 ring->dirty++; 2359 } 2360 2361 if (!processed) 2362 return 0; 2363 2364 netdev_tx_completed_queue(txq, tx_packets, tx_bytes); 2365 2366 if ((ring->tx.queue_stopped == 1) && 2367 (xgbe_tx_avail_desc(ring) > XGBE_TX_DESC_MIN_FREE)) { 2368 ring->tx.queue_stopped = 0; 2369 netif_tx_wake_queue(txq); 2370 } 2371 2372 DBGPR("<--xgbe_tx_poll: processed=%d\n", processed); 2373 2374 return processed; 2375 } 2376 2377 static int xgbe_rx_poll(struct xgbe_channel *channel, int budget) 2378 { 2379 struct xgbe_prv_data *pdata = channel->pdata; 2380 struct xgbe_hw_if *hw_if = &pdata->hw_if; 2381 struct xgbe_ring *ring = channel->rx_ring; 2382 struct xgbe_ring_data *rdata; 2383 struct xgbe_packet_data *packet; 2384 struct net_device *netdev = pdata->netdev; 2385 struct napi_struct *napi; 2386 struct sk_buff *skb; 2387 struct skb_shared_hwtstamps *hwtstamps; 2388 unsigned int last, error, context_next, context; 2389 unsigned int len, buf1_len, buf2_len, max_len; 2390 unsigned int received = 0; 2391 int packet_count = 0; 2392 2393 DBGPR("-->xgbe_rx_poll: budget=%d\n", budget); 2394 2395 /* Nothing to do if there isn't a Rx ring for this channel */ 2396 if (!ring) 2397 return 0; 2398 2399 last = 0; 2400 context_next = 0; 2401 2402 napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi; 2403 2404 rdata = XGBE_GET_DESC_DATA(ring, ring->cur); 2405 packet = &ring->packet_data; 2406 while (packet_count < budget) { 2407 DBGPR(" cur = %d\n", ring->cur); 2408 2409 /* First time in loop see if we need to restore state */ 2410 if (!received && rdata->state_saved) { 2411 skb = rdata->state.skb; 2412 error = rdata->state.error; 2413 len = rdata->state.len; 2414 } else { 2415 memset(packet, 0, sizeof(*packet)); 2416 skb = NULL; 2417 error = 0; 2418 len = 0; 2419 } 2420 2421 read_again: 2422 rdata = XGBE_GET_DESC_DATA(ring, ring->cur); 2423 2424 if (xgbe_rx_dirty_desc(ring) > (XGBE_RX_DESC_CNT >> 3)) 2425 xgbe_rx_refresh(channel); 2426 2427 if (hw_if->dev_read(channel)) 2428 break; 2429 2430 received++; 2431 ring->cur++; 2432 2433 last = XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 2434 LAST); 2435 context_next = XGMAC_GET_BITS(packet->attributes, 2436 RX_PACKET_ATTRIBUTES, 2437 CONTEXT_NEXT); 2438 context = XGMAC_GET_BITS(packet->attributes, 2439 RX_PACKET_ATTRIBUTES, 2440 CONTEXT); 2441 2442 /* Earlier error, just drain the remaining data */ 2443 if ((!last || context_next) && error) 2444 goto read_again; 2445 2446 if (error || packet->errors) { 2447 if (packet->errors) 2448 netif_err(pdata, rx_err, netdev, 2449 "error in received packet\n"); 2450 dev_kfree_skb(skb); 2451 goto next_packet; 2452 } 2453 2454 if (!context) { 2455 /* Get the data length in the descriptor buffers */ 2456 buf1_len = xgbe_rx_buf1_len(rdata, packet); 2457 len += buf1_len; 2458 buf2_len = xgbe_rx_buf2_len(rdata, packet, len); 2459 len += buf2_len; 2460 2461 if (buf2_len > rdata->rx.buf.dma_len) { 2462 /* Hardware inconsistency within the descriptors 2463 * that has resulted in a length underflow. 2464 */ 2465 error = 1; 2466 goto skip_data; 2467 } 2468 2469 if (!skb) { 2470 skb = xgbe_create_skb(pdata, napi, rdata, 2471 buf1_len); 2472 if (!skb) { 2473 error = 1; 2474 goto skip_data; 2475 } 2476 } 2477 2478 if (buf2_len) { 2479 dma_sync_single_range_for_cpu(pdata->dev, 2480 rdata->rx.buf.dma_base, 2481 rdata->rx.buf.dma_off, 2482 rdata->rx.buf.dma_len, 2483 DMA_FROM_DEVICE); 2484 2485 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 2486 rdata->rx.buf.pa.pages, 2487 rdata->rx.buf.pa.pages_offset, 2488 buf2_len, 2489 rdata->rx.buf.dma_len); 2490 rdata->rx.buf.pa.pages = NULL; 2491 } 2492 } 2493 2494 skip_data: 2495 if (!last || context_next) 2496 goto read_again; 2497 2498 if (!skb || error) { 2499 dev_kfree_skb(skb); 2500 goto next_packet; 2501 } 2502 2503 /* Be sure we don't exceed the configured MTU */ 2504 max_len = netdev->mtu + ETH_HLEN; 2505 if (!(netdev->features & NETIF_F_HW_VLAN_CTAG_RX) && 2506 (skb->protocol == htons(ETH_P_8021Q))) 2507 max_len += VLAN_HLEN; 2508 2509 if (skb->len > max_len) { 2510 netif_err(pdata, rx_err, netdev, 2511 "packet length exceeds configured MTU\n"); 2512 dev_kfree_skb(skb); 2513 goto next_packet; 2514 } 2515 2516 if (netif_msg_pktdata(pdata)) 2517 xgbe_print_pkt(netdev, skb, false); 2518 2519 skb_checksum_none_assert(skb); 2520 if (XGMAC_GET_BITS(packet->attributes, 2521 RX_PACKET_ATTRIBUTES, CSUM_DONE)) 2522 skb->ip_summed = CHECKSUM_UNNECESSARY; 2523 2524 if (XGMAC_GET_BITS(packet->attributes, 2525 RX_PACKET_ATTRIBUTES, TNP)) { 2526 skb->encapsulation = 1; 2527 2528 if (XGMAC_GET_BITS(packet->attributes, 2529 RX_PACKET_ATTRIBUTES, TNPCSUM_DONE)) 2530 skb->csum_level = 1; 2531 } 2532 2533 if (XGMAC_GET_BITS(packet->attributes, 2534 RX_PACKET_ATTRIBUTES, VLAN_CTAG)) 2535 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 2536 packet->vlan_ctag); 2537 2538 if (XGMAC_GET_BITS(packet->attributes, 2539 RX_PACKET_ATTRIBUTES, RX_TSTAMP)) { 2540 u64 nsec; 2541 2542 nsec = timecounter_cyc2time(&pdata->tstamp_tc, 2543 packet->rx_tstamp); 2544 hwtstamps = skb_hwtstamps(skb); 2545 hwtstamps->hwtstamp = ns_to_ktime(nsec); 2546 } 2547 2548 if (XGMAC_GET_BITS(packet->attributes, 2549 RX_PACKET_ATTRIBUTES, RSS_HASH)) 2550 skb_set_hash(skb, packet->rss_hash, 2551 packet->rss_hash_type); 2552 2553 skb->dev = netdev; 2554 skb->protocol = eth_type_trans(skb, netdev); 2555 skb_record_rx_queue(skb, channel->queue_index); 2556 2557 napi_gro_receive(napi, skb); 2558 2559 next_packet: 2560 packet_count++; 2561 } 2562 2563 /* Check if we need to save state before leaving */ 2564 if (received && (!last || context_next)) { 2565 rdata = XGBE_GET_DESC_DATA(ring, ring->cur); 2566 rdata->state_saved = 1; 2567 rdata->state.skb = skb; 2568 rdata->state.len = len; 2569 rdata->state.error = error; 2570 } 2571 2572 DBGPR("<--xgbe_rx_poll: packet_count = %d\n", packet_count); 2573 2574 return packet_count; 2575 } 2576 2577 static int xgbe_one_poll(struct napi_struct *napi, int budget) 2578 { 2579 struct xgbe_channel *channel = container_of(napi, struct xgbe_channel, 2580 napi); 2581 struct xgbe_prv_data *pdata = channel->pdata; 2582 int processed = 0; 2583 2584 DBGPR("-->xgbe_one_poll: budget=%d\n", budget); 2585 2586 /* Cleanup Tx ring first */ 2587 xgbe_tx_poll(channel); 2588 2589 /* Process Rx ring next */ 2590 processed = xgbe_rx_poll(channel, budget); 2591 2592 /* If we processed everything, we are done */ 2593 if ((processed < budget) && napi_complete_done(napi, processed)) { 2594 /* Enable Tx and Rx interrupts */ 2595 if (pdata->channel_irq_mode) 2596 xgbe_enable_rx_tx_int(pdata, channel); 2597 else 2598 enable_irq(channel->dma_irq); 2599 } 2600 2601 DBGPR("<--xgbe_one_poll: received = %d\n", processed); 2602 2603 return processed; 2604 } 2605 2606 static int xgbe_all_poll(struct napi_struct *napi, int budget) 2607 { 2608 struct xgbe_prv_data *pdata = container_of(napi, struct xgbe_prv_data, 2609 napi); 2610 struct xgbe_channel *channel; 2611 int ring_budget; 2612 int processed, last_processed; 2613 unsigned int i; 2614 2615 DBGPR("-->xgbe_all_poll: budget=%d\n", budget); 2616 2617 processed = 0; 2618 ring_budget = budget / pdata->rx_ring_count; 2619 do { 2620 last_processed = processed; 2621 2622 for (i = 0; i < pdata->channel_count; i++) { 2623 channel = pdata->channel[i]; 2624 2625 /* Cleanup Tx ring first */ 2626 xgbe_tx_poll(channel); 2627 2628 /* Process Rx ring next */ 2629 if (ring_budget > (budget - processed)) 2630 ring_budget = budget - processed; 2631 processed += xgbe_rx_poll(channel, ring_budget); 2632 } 2633 } while ((processed < budget) && (processed != last_processed)); 2634 2635 /* If we processed everything, we are done */ 2636 if ((processed < budget) && napi_complete_done(napi, processed)) { 2637 /* Enable Tx and Rx interrupts */ 2638 xgbe_enable_rx_tx_ints(pdata); 2639 } 2640 2641 DBGPR("<--xgbe_all_poll: received = %d\n", processed); 2642 2643 return processed; 2644 } 2645 2646 void xgbe_dump_tx_desc(struct xgbe_prv_data *pdata, struct xgbe_ring *ring, 2647 unsigned int idx, unsigned int count, unsigned int flag) 2648 { 2649 struct xgbe_ring_data *rdata; 2650 struct xgbe_ring_desc *rdesc; 2651 2652 while (count--) { 2653 rdata = XGBE_GET_DESC_DATA(ring, idx); 2654 rdesc = rdata->rdesc; 2655 netdev_dbg(pdata->netdev, 2656 "TX_NORMAL_DESC[%d %s] = %08x:%08x:%08x:%08x\n", idx, 2657 (flag == 1) ? "QUEUED FOR TX" : "TX BY DEVICE", 2658 le32_to_cpu(rdesc->desc0), 2659 le32_to_cpu(rdesc->desc1), 2660 le32_to_cpu(rdesc->desc2), 2661 le32_to_cpu(rdesc->desc3)); 2662 idx++; 2663 } 2664 } 2665 2666 void xgbe_dump_rx_desc(struct xgbe_prv_data *pdata, struct xgbe_ring *ring, 2667 unsigned int idx) 2668 { 2669 struct xgbe_ring_data *rdata; 2670 struct xgbe_ring_desc *rdesc; 2671 2672 rdata = XGBE_GET_DESC_DATA(ring, idx); 2673 rdesc = rdata->rdesc; 2674 netdev_dbg(pdata->netdev, 2675 "RX_NORMAL_DESC[%d RX BY DEVICE] = %08x:%08x:%08x:%08x\n", 2676 idx, le32_to_cpu(rdesc->desc0), le32_to_cpu(rdesc->desc1), 2677 le32_to_cpu(rdesc->desc2), le32_to_cpu(rdesc->desc3)); 2678 } 2679 2680 void xgbe_print_pkt(struct net_device *netdev, struct sk_buff *skb, bool tx_rx) 2681 { 2682 struct ethhdr *eth = (struct ethhdr *)skb->data; 2683 unsigned char buffer[128]; 2684 unsigned int i; 2685 2686 netdev_dbg(netdev, "\n************** SKB dump ****************\n"); 2687 2688 netdev_dbg(netdev, "%s packet of %d bytes\n", 2689 (tx_rx ? "TX" : "RX"), skb->len); 2690 2691 netdev_dbg(netdev, "Dst MAC addr: %pM\n", eth->h_dest); 2692 netdev_dbg(netdev, "Src MAC addr: %pM\n", eth->h_source); 2693 netdev_dbg(netdev, "Protocol: %#06x\n", ntohs(eth->h_proto)); 2694 2695 for (i = 0; i < skb->len; i += 32) { 2696 unsigned int len = min(skb->len - i, 32U); 2697 2698 hex_dump_to_buffer(&skb->data[i], len, 32, 1, 2699 buffer, sizeof(buffer), false); 2700 netdev_dbg(netdev, " %#06x: %s\n", i, buffer); 2701 } 2702 2703 netdev_dbg(netdev, "\n************** SKB dump ****************\n"); 2704 } 2705