1 /* 2 * AMD 10Gb Ethernet driver 3 * 4 * This file is available to you under your choice of the following two 5 * licenses: 6 * 7 * License 1: GPLv2 8 * 9 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. 10 * 11 * This file is free software; you may copy, redistribute and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation, either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program. If not, see <http://www.gnu.org/licenses/>. 23 * 24 * This file incorporates work covered by the following copyright and 25 * permission notice: 26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 28 * Inc. unless otherwise expressly agreed to in writing between Synopsys 29 * and you. 30 * 31 * The Software IS NOT an item of Licensed Software or Licensed Product 32 * under any End User Software License Agreement or Agreement for Licensed 33 * Product with Synopsys or any supplement thereto. Permission is hereby 34 * granted, free of charge, to any person obtaining a copy of this software 35 * annotated with this license and the Software, to deal in the Software 36 * without restriction, including without limitation the rights to use, 37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 38 * of the Software, and to permit persons to whom the Software is furnished 39 * to do so, subject to the following conditions: 40 * 41 * The above copyright notice and this permission notice shall be included 42 * in all copies or substantial portions of the Software. 43 * 44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 54 * THE POSSIBILITY OF SUCH DAMAGE. 55 * 56 * 57 * License 2: Modified BSD 58 * 59 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. 60 * All rights reserved. 61 * 62 * Redistribution and use in source and binary forms, with or without 63 * modification, are permitted provided that the following conditions are met: 64 * * Redistributions of source code must retain the above copyright 65 * notice, this list of conditions and the following disclaimer. 66 * * Redistributions in binary form must reproduce the above copyright 67 * notice, this list of conditions and the following disclaimer in the 68 * documentation and/or other materials provided with the distribution. 69 * * Neither the name of Advanced Micro Devices, Inc. nor the 70 * names of its contributors may be used to endorse or promote products 71 * derived from this software without specific prior written permission. 72 * 73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY 77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 83 * 84 * This file incorporates work covered by the following copyright and 85 * permission notice: 86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 88 * Inc. unless otherwise expressly agreed to in writing between Synopsys 89 * and you. 90 * 91 * The Software IS NOT an item of Licensed Software or Licensed Product 92 * under any End User Software License Agreement or Agreement for Licensed 93 * Product with Synopsys or any supplement thereto. Permission is hereby 94 * granted, free of charge, to any person obtaining a copy of this software 95 * annotated with this license and the Software, to deal in the Software 96 * without restriction, including without limitation the rights to use, 97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 98 * of the Software, and to permit persons to whom the Software is furnished 99 * to do so, subject to the following conditions: 100 * 101 * The above copyright notice and this permission notice shall be included 102 * in all copies or substantial portions of the Software. 103 * 104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 114 * THE POSSIBILITY OF SUCH DAMAGE. 115 */ 116 117 #include <linux/phy.h> 118 #include <linux/mdio.h> 119 #include <linux/clk.h> 120 #include <linux/bitrev.h> 121 #include <linux/crc32.h> 122 #include <linux/crc32poly.h> 123 124 #include "xgbe.h" 125 #include "xgbe-common.h" 126 127 static inline unsigned int xgbe_get_max_frame(struct xgbe_prv_data *pdata) 128 { 129 return pdata->netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 130 } 131 132 static unsigned int xgbe_usec_to_riwt(struct xgbe_prv_data *pdata, 133 unsigned int usec) 134 { 135 unsigned long rate; 136 unsigned int ret; 137 138 DBGPR("-->xgbe_usec_to_riwt\n"); 139 140 rate = pdata->sysclk_rate; 141 142 /* 143 * Convert the input usec value to the watchdog timer value. Each 144 * watchdog timer value is equivalent to 256 clock cycles. 145 * Calculate the required value as: 146 * ( usec * ( system_clock_mhz / 10^6 ) / 256 147 */ 148 ret = (usec * (rate / 1000000)) / 256; 149 150 DBGPR("<--xgbe_usec_to_riwt\n"); 151 152 return ret; 153 } 154 155 static unsigned int xgbe_riwt_to_usec(struct xgbe_prv_data *pdata, 156 unsigned int riwt) 157 { 158 unsigned long rate; 159 unsigned int ret; 160 161 DBGPR("-->xgbe_riwt_to_usec\n"); 162 163 rate = pdata->sysclk_rate; 164 165 /* 166 * Convert the input watchdog timer value to the usec value. Each 167 * watchdog timer value is equivalent to 256 clock cycles. 168 * Calculate the required value as: 169 * ( riwt * 256 ) / ( system_clock_mhz / 10^6 ) 170 */ 171 ret = (riwt * 256) / (rate / 1000000); 172 173 DBGPR("<--xgbe_riwt_to_usec\n"); 174 175 return ret; 176 } 177 178 static int xgbe_config_pbl_val(struct xgbe_prv_data *pdata) 179 { 180 unsigned int pblx8, pbl; 181 unsigned int i; 182 183 pblx8 = DMA_PBL_X8_DISABLE; 184 pbl = pdata->pbl; 185 186 if (pdata->pbl > 32) { 187 pblx8 = DMA_PBL_X8_ENABLE; 188 pbl >>= 3; 189 } 190 191 for (i = 0; i < pdata->channel_count; i++) { 192 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, PBLX8, 193 pblx8); 194 195 if (pdata->channel[i]->tx_ring) 196 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, 197 PBL, pbl); 198 199 if (pdata->channel[i]->rx_ring) 200 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, 201 PBL, pbl); 202 } 203 204 return 0; 205 } 206 207 static int xgbe_config_osp_mode(struct xgbe_prv_data *pdata) 208 { 209 unsigned int i; 210 211 for (i = 0; i < pdata->channel_count; i++) { 212 if (!pdata->channel[i]->tx_ring) 213 break; 214 215 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, OSP, 216 pdata->tx_osp_mode); 217 } 218 219 return 0; 220 } 221 222 static int xgbe_config_rsf_mode(struct xgbe_prv_data *pdata, unsigned int val) 223 { 224 unsigned int i; 225 226 for (i = 0; i < pdata->rx_q_count; i++) 227 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RSF, val); 228 229 return 0; 230 } 231 232 static int xgbe_config_tsf_mode(struct xgbe_prv_data *pdata, unsigned int val) 233 { 234 unsigned int i; 235 236 for (i = 0; i < pdata->tx_q_count; i++) 237 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TSF, val); 238 239 return 0; 240 } 241 242 static int xgbe_config_rx_threshold(struct xgbe_prv_data *pdata, 243 unsigned int val) 244 { 245 unsigned int i; 246 247 for (i = 0; i < pdata->rx_q_count; i++) 248 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RTC, val); 249 250 return 0; 251 } 252 253 static int xgbe_config_tx_threshold(struct xgbe_prv_data *pdata, 254 unsigned int val) 255 { 256 unsigned int i; 257 258 for (i = 0; i < pdata->tx_q_count; i++) 259 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TTC, val); 260 261 return 0; 262 } 263 264 static int xgbe_config_rx_coalesce(struct xgbe_prv_data *pdata) 265 { 266 unsigned int i; 267 268 for (i = 0; i < pdata->channel_count; i++) { 269 if (!pdata->channel[i]->rx_ring) 270 break; 271 272 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RIWT, RWT, 273 pdata->rx_riwt); 274 } 275 276 return 0; 277 } 278 279 static int xgbe_config_tx_coalesce(struct xgbe_prv_data *pdata) 280 { 281 return 0; 282 } 283 284 static void xgbe_config_rx_buffer_size(struct xgbe_prv_data *pdata) 285 { 286 unsigned int i; 287 288 for (i = 0; i < pdata->channel_count; i++) { 289 if (!pdata->channel[i]->rx_ring) 290 break; 291 292 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, RBSZ, 293 pdata->rx_buf_size); 294 } 295 } 296 297 static void xgbe_config_tso_mode(struct xgbe_prv_data *pdata) 298 { 299 unsigned int i; 300 301 for (i = 0; i < pdata->channel_count; i++) { 302 if (!pdata->channel[i]->tx_ring) 303 break; 304 305 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, TSE, 1); 306 } 307 } 308 309 static void xgbe_config_sph_mode(struct xgbe_prv_data *pdata) 310 { 311 unsigned int i; 312 313 for (i = 0; i < pdata->channel_count; i++) { 314 if (!pdata->channel[i]->rx_ring) 315 break; 316 317 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, SPH, 1); 318 } 319 320 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, HDSMS, XGBE_SPH_HDSMS_SIZE); 321 } 322 323 static int xgbe_write_rss_reg(struct xgbe_prv_data *pdata, unsigned int type, 324 unsigned int index, unsigned int val) 325 { 326 unsigned int wait; 327 int ret = 0; 328 329 mutex_lock(&pdata->rss_mutex); 330 331 if (XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB)) { 332 ret = -EBUSY; 333 goto unlock; 334 } 335 336 XGMAC_IOWRITE(pdata, MAC_RSSDR, val); 337 338 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, RSSIA, index); 339 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, ADDRT, type); 340 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, CT, 0); 341 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, OB, 1); 342 343 wait = 1000; 344 while (wait--) { 345 if (!XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB)) 346 goto unlock; 347 348 usleep_range(1000, 1500); 349 } 350 351 ret = -EBUSY; 352 353 unlock: 354 mutex_unlock(&pdata->rss_mutex); 355 356 return ret; 357 } 358 359 static int xgbe_write_rss_hash_key(struct xgbe_prv_data *pdata) 360 { 361 unsigned int key_regs = sizeof(pdata->rss_key) / sizeof(u32); 362 unsigned int *key = (unsigned int *)&pdata->rss_key; 363 int ret; 364 365 while (key_regs--) { 366 ret = xgbe_write_rss_reg(pdata, XGBE_RSS_HASH_KEY_TYPE, 367 key_regs, *key++); 368 if (ret) 369 return ret; 370 } 371 372 return 0; 373 } 374 375 static int xgbe_write_rss_lookup_table(struct xgbe_prv_data *pdata) 376 { 377 unsigned int i; 378 int ret; 379 380 for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) { 381 ret = xgbe_write_rss_reg(pdata, 382 XGBE_RSS_LOOKUP_TABLE_TYPE, i, 383 pdata->rss_table[i]); 384 if (ret) 385 return ret; 386 } 387 388 return 0; 389 } 390 391 static int xgbe_set_rss_hash_key(struct xgbe_prv_data *pdata, const u8 *key) 392 { 393 memcpy(pdata->rss_key, key, sizeof(pdata->rss_key)); 394 395 return xgbe_write_rss_hash_key(pdata); 396 } 397 398 static int xgbe_set_rss_lookup_table(struct xgbe_prv_data *pdata, 399 const u32 *table) 400 { 401 unsigned int i; 402 403 for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) 404 XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH, table[i]); 405 406 return xgbe_write_rss_lookup_table(pdata); 407 } 408 409 static int xgbe_enable_rss(struct xgbe_prv_data *pdata) 410 { 411 int ret; 412 413 if (!pdata->hw_feat.rss) 414 return -EOPNOTSUPP; 415 416 /* Program the hash key */ 417 ret = xgbe_write_rss_hash_key(pdata); 418 if (ret) 419 return ret; 420 421 /* Program the lookup table */ 422 ret = xgbe_write_rss_lookup_table(pdata); 423 if (ret) 424 return ret; 425 426 /* Set the RSS options */ 427 XGMAC_IOWRITE(pdata, MAC_RSSCR, pdata->rss_options); 428 429 /* Enable RSS */ 430 XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 1); 431 432 return 0; 433 } 434 435 static int xgbe_disable_rss(struct xgbe_prv_data *pdata) 436 { 437 if (!pdata->hw_feat.rss) 438 return -EOPNOTSUPP; 439 440 XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 0); 441 442 return 0; 443 } 444 445 static void xgbe_config_rss(struct xgbe_prv_data *pdata) 446 { 447 int ret; 448 449 if (!pdata->hw_feat.rss) 450 return; 451 452 if (pdata->netdev->features & NETIF_F_RXHASH) 453 ret = xgbe_enable_rss(pdata); 454 else 455 ret = xgbe_disable_rss(pdata); 456 457 if (ret) 458 netdev_err(pdata->netdev, 459 "error configuring RSS, RSS disabled\n"); 460 } 461 462 static bool xgbe_is_pfc_queue(struct xgbe_prv_data *pdata, 463 unsigned int queue) 464 { 465 unsigned int prio, tc; 466 467 for (prio = 0; prio < IEEE_8021QAZ_MAX_TCS; prio++) { 468 /* Does this queue handle the priority? */ 469 if (pdata->prio2q_map[prio] != queue) 470 continue; 471 472 /* Get the Traffic Class for this priority */ 473 tc = pdata->ets->prio_tc[prio]; 474 475 /* Check if PFC is enabled for this traffic class */ 476 if (pdata->pfc->pfc_en & (1 << tc)) 477 return true; 478 } 479 480 return false; 481 } 482 483 static void xgbe_set_vxlan_id(struct xgbe_prv_data *pdata) 484 { 485 /* Program the VXLAN port */ 486 XGMAC_IOWRITE_BITS(pdata, MAC_TIR, TNID, pdata->vxlan_port); 487 488 netif_dbg(pdata, drv, pdata->netdev, "VXLAN tunnel id set to %hx\n", 489 pdata->vxlan_port); 490 } 491 492 static void xgbe_enable_vxlan(struct xgbe_prv_data *pdata) 493 { 494 if (!pdata->hw_feat.vxn) 495 return; 496 497 /* Program the VXLAN port */ 498 xgbe_set_vxlan_id(pdata); 499 500 /* Allow for IPv6/UDP zero-checksum VXLAN packets */ 501 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VUCC, 1); 502 503 /* Enable VXLAN tunneling mode */ 504 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, VNM, 0); 505 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, VNE, 1); 506 507 netif_dbg(pdata, drv, pdata->netdev, "VXLAN acceleration enabled\n"); 508 } 509 510 static void xgbe_disable_vxlan(struct xgbe_prv_data *pdata) 511 { 512 if (!pdata->hw_feat.vxn) 513 return; 514 515 /* Disable tunneling mode */ 516 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, VNE, 0); 517 518 /* Clear IPv6/UDP zero-checksum VXLAN packets setting */ 519 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VUCC, 0); 520 521 /* Clear the VXLAN port */ 522 XGMAC_IOWRITE_BITS(pdata, MAC_TIR, TNID, 0); 523 524 netif_dbg(pdata, drv, pdata->netdev, "VXLAN acceleration disabled\n"); 525 } 526 527 static unsigned int xgbe_get_fc_queue_count(struct xgbe_prv_data *pdata) 528 { 529 unsigned int max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES; 530 531 /* From MAC ver 30H the TFCR is per priority, instead of per queue */ 532 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) >= 0x30) 533 return max_q_count; 534 else 535 return min_t(unsigned int, pdata->tx_q_count, max_q_count); 536 } 537 538 static int xgbe_disable_tx_flow_control(struct xgbe_prv_data *pdata) 539 { 540 unsigned int reg, reg_val; 541 unsigned int i, q_count; 542 543 /* Clear MTL flow control */ 544 for (i = 0; i < pdata->rx_q_count; i++) 545 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 0); 546 547 /* Clear MAC flow control */ 548 q_count = xgbe_get_fc_queue_count(pdata); 549 reg = MAC_Q0TFCR; 550 for (i = 0; i < q_count; i++) { 551 reg_val = XGMAC_IOREAD(pdata, reg); 552 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 0); 553 XGMAC_IOWRITE(pdata, reg, reg_val); 554 555 reg += MAC_QTFCR_INC; 556 } 557 558 return 0; 559 } 560 561 static int xgbe_enable_tx_flow_control(struct xgbe_prv_data *pdata) 562 { 563 struct ieee_pfc *pfc = pdata->pfc; 564 struct ieee_ets *ets = pdata->ets; 565 unsigned int reg, reg_val; 566 unsigned int i, q_count; 567 568 /* Set MTL flow control */ 569 for (i = 0; i < pdata->rx_q_count; i++) { 570 unsigned int ehfc = 0; 571 572 if (pdata->rx_rfd[i]) { 573 /* Flow control thresholds are established */ 574 if (pfc && ets) { 575 if (xgbe_is_pfc_queue(pdata, i)) 576 ehfc = 1; 577 } else { 578 ehfc = 1; 579 } 580 } 581 582 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, ehfc); 583 584 netif_dbg(pdata, drv, pdata->netdev, 585 "flow control %s for RXq%u\n", 586 ehfc ? "enabled" : "disabled", i); 587 } 588 589 /* Set MAC flow control */ 590 q_count = xgbe_get_fc_queue_count(pdata); 591 reg = MAC_Q0TFCR; 592 for (i = 0; i < q_count; i++) { 593 reg_val = XGMAC_IOREAD(pdata, reg); 594 595 /* Enable transmit flow control */ 596 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 1); 597 /* Set pause time */ 598 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, PT, 0xffff); 599 600 XGMAC_IOWRITE(pdata, reg, reg_val); 601 602 reg += MAC_QTFCR_INC; 603 } 604 605 return 0; 606 } 607 608 static int xgbe_disable_rx_flow_control(struct xgbe_prv_data *pdata) 609 { 610 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 0); 611 612 return 0; 613 } 614 615 static int xgbe_enable_rx_flow_control(struct xgbe_prv_data *pdata) 616 { 617 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 1); 618 619 return 0; 620 } 621 622 static int xgbe_config_tx_flow_control(struct xgbe_prv_data *pdata) 623 { 624 struct ieee_pfc *pfc = pdata->pfc; 625 626 if (pdata->tx_pause || (pfc && pfc->pfc_en)) 627 xgbe_enable_tx_flow_control(pdata); 628 else 629 xgbe_disable_tx_flow_control(pdata); 630 631 return 0; 632 } 633 634 static int xgbe_config_rx_flow_control(struct xgbe_prv_data *pdata) 635 { 636 struct ieee_pfc *pfc = pdata->pfc; 637 638 if (pdata->rx_pause || (pfc && pfc->pfc_en)) 639 xgbe_enable_rx_flow_control(pdata); 640 else 641 xgbe_disable_rx_flow_control(pdata); 642 643 return 0; 644 } 645 646 static void xgbe_config_flow_control(struct xgbe_prv_data *pdata) 647 { 648 struct ieee_pfc *pfc = pdata->pfc; 649 650 xgbe_config_tx_flow_control(pdata); 651 xgbe_config_rx_flow_control(pdata); 652 653 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 654 (pfc && pfc->pfc_en) ? 1 : 0); 655 } 656 657 static void xgbe_enable_dma_interrupts(struct xgbe_prv_data *pdata) 658 { 659 struct xgbe_channel *channel; 660 unsigned int i, ver; 661 662 /* Set the interrupt mode if supported */ 663 if (pdata->channel_irq_mode) 664 XGMAC_IOWRITE_BITS(pdata, DMA_MR, INTM, 665 pdata->channel_irq_mode); 666 667 ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER); 668 669 for (i = 0; i < pdata->channel_count; i++) { 670 channel = pdata->channel[i]; 671 672 /* Clear all the interrupts which are set */ 673 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, 674 XGMAC_DMA_IOREAD(channel, DMA_CH_SR)); 675 676 /* Clear all interrupt enable bits */ 677 channel->curr_ier = 0; 678 679 /* Enable following interrupts 680 * NIE - Normal Interrupt Summary Enable 681 * AIE - Abnormal Interrupt Summary Enable 682 * FBEE - Fatal Bus Error Enable 683 */ 684 if (ver < 0x21) { 685 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, NIE20, 1); 686 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, AIE20, 1); 687 } else { 688 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, NIE, 1); 689 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, AIE, 1); 690 } 691 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, FBEE, 1); 692 693 if (channel->tx_ring) { 694 /* Enable the following Tx interrupts 695 * TIE - Transmit Interrupt Enable (unless using 696 * per channel interrupts in edge triggered 697 * mode) 698 */ 699 if (!pdata->per_channel_irq || pdata->channel_irq_mode) 700 XGMAC_SET_BITS(channel->curr_ier, 701 DMA_CH_IER, TIE, 1); 702 } 703 if (channel->rx_ring) { 704 /* Enable following Rx interrupts 705 * RBUE - Receive Buffer Unavailable Enable 706 * RIE - Receive Interrupt Enable (unless using 707 * per channel interrupts in edge triggered 708 * mode) 709 */ 710 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RBUE, 1); 711 if (!pdata->per_channel_irq || pdata->channel_irq_mode) 712 XGMAC_SET_BITS(channel->curr_ier, 713 DMA_CH_IER, RIE, 1); 714 } 715 716 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, channel->curr_ier); 717 } 718 } 719 720 static void xgbe_enable_mtl_interrupts(struct xgbe_prv_data *pdata) 721 { 722 unsigned int mtl_q_isr; 723 unsigned int q_count, i; 724 725 q_count = max(pdata->hw_feat.tx_q_cnt, pdata->hw_feat.rx_q_cnt); 726 for (i = 0; i < q_count; i++) { 727 /* Clear all the interrupts which are set */ 728 mtl_q_isr = XGMAC_MTL_IOREAD(pdata, i, MTL_Q_ISR); 729 XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_ISR, mtl_q_isr); 730 731 /* No MTL interrupts to be enabled */ 732 XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_IER, 0); 733 } 734 } 735 736 static void xgbe_enable_mac_interrupts(struct xgbe_prv_data *pdata) 737 { 738 unsigned int mac_ier = 0; 739 740 /* Enable Timestamp interrupt */ 741 XGMAC_SET_BITS(mac_ier, MAC_IER, TSIE, 1); 742 743 XGMAC_IOWRITE(pdata, MAC_IER, mac_ier); 744 745 /* Enable all counter interrupts */ 746 XGMAC_IOWRITE_BITS(pdata, MMC_RIER, ALL_INTERRUPTS, 0xffffffff); 747 XGMAC_IOWRITE_BITS(pdata, MMC_TIER, ALL_INTERRUPTS, 0xffffffff); 748 749 /* Enable MDIO single command completion interrupt */ 750 XGMAC_IOWRITE_BITS(pdata, MAC_MDIOIER, SNGLCOMPIE, 1); 751 } 752 753 static void xgbe_enable_ecc_interrupts(struct xgbe_prv_data *pdata) 754 { 755 unsigned int ecc_isr, ecc_ier = 0; 756 757 if (!pdata->vdata->ecc_support) 758 return; 759 760 /* Clear all the interrupts which are set */ 761 ecc_isr = XP_IOREAD(pdata, XP_ECC_ISR); 762 XP_IOWRITE(pdata, XP_ECC_ISR, ecc_isr); 763 764 /* Enable ECC interrupts */ 765 XP_SET_BITS(ecc_ier, XP_ECC_IER, TX_DED, 1); 766 XP_SET_BITS(ecc_ier, XP_ECC_IER, TX_SEC, 1); 767 XP_SET_BITS(ecc_ier, XP_ECC_IER, RX_DED, 1); 768 XP_SET_BITS(ecc_ier, XP_ECC_IER, RX_SEC, 1); 769 XP_SET_BITS(ecc_ier, XP_ECC_IER, DESC_DED, 1); 770 XP_SET_BITS(ecc_ier, XP_ECC_IER, DESC_SEC, 1); 771 772 XP_IOWRITE(pdata, XP_ECC_IER, ecc_ier); 773 } 774 775 static void xgbe_disable_ecc_ded(struct xgbe_prv_data *pdata) 776 { 777 unsigned int ecc_ier; 778 779 ecc_ier = XP_IOREAD(pdata, XP_ECC_IER); 780 781 /* Disable ECC DED interrupts */ 782 XP_SET_BITS(ecc_ier, XP_ECC_IER, TX_DED, 0); 783 XP_SET_BITS(ecc_ier, XP_ECC_IER, RX_DED, 0); 784 XP_SET_BITS(ecc_ier, XP_ECC_IER, DESC_DED, 0); 785 786 XP_IOWRITE(pdata, XP_ECC_IER, ecc_ier); 787 } 788 789 static void xgbe_disable_ecc_sec(struct xgbe_prv_data *pdata, 790 enum xgbe_ecc_sec sec) 791 { 792 unsigned int ecc_ier; 793 794 ecc_ier = XP_IOREAD(pdata, XP_ECC_IER); 795 796 /* Disable ECC SEC interrupt */ 797 switch (sec) { 798 case XGBE_ECC_SEC_TX: 799 XP_SET_BITS(ecc_ier, XP_ECC_IER, TX_SEC, 0); 800 break; 801 case XGBE_ECC_SEC_RX: 802 XP_SET_BITS(ecc_ier, XP_ECC_IER, RX_SEC, 0); 803 break; 804 case XGBE_ECC_SEC_DESC: 805 XP_SET_BITS(ecc_ier, XP_ECC_IER, DESC_SEC, 0); 806 break; 807 } 808 809 XP_IOWRITE(pdata, XP_ECC_IER, ecc_ier); 810 } 811 812 static int xgbe_set_speed(struct xgbe_prv_data *pdata, int speed) 813 { 814 unsigned int ss; 815 816 switch (speed) { 817 case SPEED_1000: 818 ss = 0x03; 819 break; 820 case SPEED_2500: 821 ss = 0x02; 822 break; 823 case SPEED_10000: 824 ss = 0x00; 825 break; 826 default: 827 return -EINVAL; 828 } 829 830 if (XGMAC_IOREAD_BITS(pdata, MAC_TCR, SS) != ss) 831 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, ss); 832 833 return 0; 834 } 835 836 static int xgbe_enable_rx_vlan_stripping(struct xgbe_prv_data *pdata) 837 { 838 /* Put the VLAN tag in the Rx descriptor */ 839 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLRXS, 1); 840 841 /* Don't check the VLAN type */ 842 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, DOVLTC, 1); 843 844 /* Check only C-TAG (0x8100) packets */ 845 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ERSVLM, 0); 846 847 /* Don't consider an S-TAG (0x88A8) packet as a VLAN packet */ 848 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ESVL, 0); 849 850 /* Enable VLAN tag stripping */ 851 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0x3); 852 853 return 0; 854 } 855 856 static int xgbe_disable_rx_vlan_stripping(struct xgbe_prv_data *pdata) 857 { 858 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0); 859 860 return 0; 861 } 862 863 static int xgbe_enable_rx_vlan_filtering(struct xgbe_prv_data *pdata) 864 { 865 /* Enable VLAN filtering */ 866 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 1); 867 868 /* Enable VLAN Hash Table filtering */ 869 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTHM, 1); 870 871 /* Disable VLAN tag inverse matching */ 872 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTIM, 0); 873 874 /* Only filter on the lower 12-bits of the VLAN tag */ 875 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ETV, 1); 876 877 /* In order for the VLAN Hash Table filtering to be effective, 878 * the VLAN tag identifier in the VLAN Tag Register must not 879 * be zero. Set the VLAN tag identifier to "1" to enable the 880 * VLAN Hash Table filtering. This implies that a VLAN tag of 881 * 1 will always pass filtering. 882 */ 883 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VL, 1); 884 885 return 0; 886 } 887 888 static int xgbe_disable_rx_vlan_filtering(struct xgbe_prv_data *pdata) 889 { 890 /* Disable VLAN filtering */ 891 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 0); 892 893 return 0; 894 } 895 896 static u32 xgbe_vid_crc32_le(__le16 vid_le) 897 { 898 u32 crc = ~0; 899 u32 temp = 0; 900 unsigned char *data = (unsigned char *)&vid_le; 901 unsigned char data_byte = 0; 902 int i, bits; 903 904 bits = get_bitmask_order(VLAN_VID_MASK); 905 for (i = 0; i < bits; i++) { 906 if ((i % 8) == 0) 907 data_byte = data[i / 8]; 908 909 temp = ((crc & 1) ^ data_byte) & 1; 910 crc >>= 1; 911 data_byte >>= 1; 912 913 if (temp) 914 crc ^= CRC32_POLY_LE; 915 } 916 917 return crc; 918 } 919 920 static int xgbe_update_vlan_hash_table(struct xgbe_prv_data *pdata) 921 { 922 u32 crc; 923 u16 vid; 924 __le16 vid_le; 925 u16 vlan_hash_table = 0; 926 927 /* Generate the VLAN Hash Table value */ 928 for_each_set_bit(vid, pdata->active_vlans, VLAN_N_VID) { 929 /* Get the CRC32 value of the VLAN ID */ 930 vid_le = cpu_to_le16(vid); 931 crc = bitrev32(~xgbe_vid_crc32_le(vid_le)) >> 28; 932 933 vlan_hash_table |= (1 << crc); 934 } 935 936 /* Set the VLAN Hash Table filtering register */ 937 XGMAC_IOWRITE_BITS(pdata, MAC_VLANHTR, VLHT, vlan_hash_table); 938 939 return 0; 940 } 941 942 static int xgbe_set_promiscuous_mode(struct xgbe_prv_data *pdata, 943 unsigned int enable) 944 { 945 unsigned int val = enable ? 1 : 0; 946 947 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PR) == val) 948 return 0; 949 950 netif_dbg(pdata, drv, pdata->netdev, "%s promiscuous mode\n", 951 enable ? "entering" : "leaving"); 952 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, val); 953 954 /* Hardware will still perform VLAN filtering in promiscuous mode */ 955 if (enable) { 956 xgbe_disable_rx_vlan_filtering(pdata); 957 } else { 958 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER) 959 xgbe_enable_rx_vlan_filtering(pdata); 960 } 961 962 return 0; 963 } 964 965 static int xgbe_set_all_multicast_mode(struct xgbe_prv_data *pdata, 966 unsigned int enable) 967 { 968 unsigned int val = enable ? 1 : 0; 969 970 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PM) == val) 971 return 0; 972 973 netif_dbg(pdata, drv, pdata->netdev, "%s allmulti mode\n", 974 enable ? "entering" : "leaving"); 975 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, val); 976 977 return 0; 978 } 979 980 static void xgbe_set_mac_reg(struct xgbe_prv_data *pdata, 981 struct netdev_hw_addr *ha, unsigned int *mac_reg) 982 { 983 unsigned int mac_addr_hi, mac_addr_lo; 984 u8 *mac_addr; 985 986 mac_addr_lo = 0; 987 mac_addr_hi = 0; 988 989 if (ha) { 990 mac_addr = (u8 *)&mac_addr_lo; 991 mac_addr[0] = ha->addr[0]; 992 mac_addr[1] = ha->addr[1]; 993 mac_addr[2] = ha->addr[2]; 994 mac_addr[3] = ha->addr[3]; 995 mac_addr = (u8 *)&mac_addr_hi; 996 mac_addr[0] = ha->addr[4]; 997 mac_addr[1] = ha->addr[5]; 998 999 netif_dbg(pdata, drv, pdata->netdev, 1000 "adding mac address %pM at %#x\n", 1001 ha->addr, *mac_reg); 1002 1003 XGMAC_SET_BITS(mac_addr_hi, MAC_MACA1HR, AE, 1); 1004 } 1005 1006 XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_hi); 1007 *mac_reg += MAC_MACA_INC; 1008 XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_lo); 1009 *mac_reg += MAC_MACA_INC; 1010 } 1011 1012 static void xgbe_set_mac_addn_addrs(struct xgbe_prv_data *pdata) 1013 { 1014 struct net_device *netdev = pdata->netdev; 1015 struct netdev_hw_addr *ha; 1016 unsigned int mac_reg; 1017 unsigned int addn_macs; 1018 1019 mac_reg = MAC_MACA1HR; 1020 addn_macs = pdata->hw_feat.addn_mac; 1021 1022 if (netdev_uc_count(netdev) > addn_macs) { 1023 xgbe_set_promiscuous_mode(pdata, 1); 1024 } else { 1025 netdev_for_each_uc_addr(ha, netdev) { 1026 xgbe_set_mac_reg(pdata, ha, &mac_reg); 1027 addn_macs--; 1028 } 1029 1030 if (netdev_mc_count(netdev) > addn_macs) { 1031 xgbe_set_all_multicast_mode(pdata, 1); 1032 } else { 1033 netdev_for_each_mc_addr(ha, netdev) { 1034 xgbe_set_mac_reg(pdata, ha, &mac_reg); 1035 addn_macs--; 1036 } 1037 } 1038 } 1039 1040 /* Clear remaining additional MAC address entries */ 1041 while (addn_macs--) 1042 xgbe_set_mac_reg(pdata, NULL, &mac_reg); 1043 } 1044 1045 static void xgbe_set_mac_hash_table(struct xgbe_prv_data *pdata) 1046 { 1047 struct net_device *netdev = pdata->netdev; 1048 struct netdev_hw_addr *ha; 1049 unsigned int hash_reg; 1050 unsigned int hash_table_shift, hash_table_count; 1051 u32 hash_table[XGBE_MAC_HASH_TABLE_SIZE]; 1052 u32 crc; 1053 unsigned int i; 1054 1055 hash_table_shift = 26 - (pdata->hw_feat.hash_table_size >> 7); 1056 hash_table_count = pdata->hw_feat.hash_table_size / 32; 1057 memset(hash_table, 0, sizeof(hash_table)); 1058 1059 /* Build the MAC Hash Table register values */ 1060 netdev_for_each_uc_addr(ha, netdev) { 1061 crc = bitrev32(~crc32_le(~0, ha->addr, ETH_ALEN)); 1062 crc >>= hash_table_shift; 1063 hash_table[crc >> 5] |= (1 << (crc & 0x1f)); 1064 } 1065 1066 netdev_for_each_mc_addr(ha, netdev) { 1067 crc = bitrev32(~crc32_le(~0, ha->addr, ETH_ALEN)); 1068 crc >>= hash_table_shift; 1069 hash_table[crc >> 5] |= (1 << (crc & 0x1f)); 1070 } 1071 1072 /* Set the MAC Hash Table registers */ 1073 hash_reg = MAC_HTR0; 1074 for (i = 0; i < hash_table_count; i++) { 1075 XGMAC_IOWRITE(pdata, hash_reg, hash_table[i]); 1076 hash_reg += MAC_HTR_INC; 1077 } 1078 } 1079 1080 static int xgbe_add_mac_addresses(struct xgbe_prv_data *pdata) 1081 { 1082 if (pdata->hw_feat.hash_table_size) 1083 xgbe_set_mac_hash_table(pdata); 1084 else 1085 xgbe_set_mac_addn_addrs(pdata); 1086 1087 return 0; 1088 } 1089 1090 static int xgbe_set_mac_address(struct xgbe_prv_data *pdata, const u8 *addr) 1091 { 1092 unsigned int mac_addr_hi, mac_addr_lo; 1093 1094 mac_addr_hi = (addr[5] << 8) | (addr[4] << 0); 1095 mac_addr_lo = (addr[3] << 24) | (addr[2] << 16) | 1096 (addr[1] << 8) | (addr[0] << 0); 1097 1098 XGMAC_IOWRITE(pdata, MAC_MACA0HR, mac_addr_hi); 1099 XGMAC_IOWRITE(pdata, MAC_MACA0LR, mac_addr_lo); 1100 1101 return 0; 1102 } 1103 1104 static int xgbe_config_rx_mode(struct xgbe_prv_data *pdata) 1105 { 1106 struct net_device *netdev = pdata->netdev; 1107 unsigned int pr_mode, am_mode; 1108 1109 pr_mode = ((netdev->flags & IFF_PROMISC) != 0); 1110 am_mode = ((netdev->flags & IFF_ALLMULTI) != 0); 1111 1112 xgbe_set_promiscuous_mode(pdata, pr_mode); 1113 xgbe_set_all_multicast_mode(pdata, am_mode); 1114 1115 xgbe_add_mac_addresses(pdata); 1116 1117 return 0; 1118 } 1119 1120 static int xgbe_clr_gpio(struct xgbe_prv_data *pdata, unsigned int gpio) 1121 { 1122 unsigned int reg; 1123 1124 if (gpio > 15) 1125 return -EINVAL; 1126 1127 reg = XGMAC_IOREAD(pdata, MAC_GPIOSR); 1128 1129 reg &= ~(1 << (gpio + 16)); 1130 XGMAC_IOWRITE(pdata, MAC_GPIOSR, reg); 1131 1132 return 0; 1133 } 1134 1135 static int xgbe_set_gpio(struct xgbe_prv_data *pdata, unsigned int gpio) 1136 { 1137 unsigned int reg; 1138 1139 if (gpio > 15) 1140 return -EINVAL; 1141 1142 reg = XGMAC_IOREAD(pdata, MAC_GPIOSR); 1143 1144 reg |= (1 << (gpio + 16)); 1145 XGMAC_IOWRITE(pdata, MAC_GPIOSR, reg); 1146 1147 return 0; 1148 } 1149 1150 static int xgbe_read_mmd_regs_v2(struct xgbe_prv_data *pdata, int prtad, 1151 int mmd_reg) 1152 { 1153 unsigned long flags; 1154 unsigned int mmd_address, index, offset; 1155 int mmd_data; 1156 1157 if (mmd_reg & MII_ADDR_C45) 1158 mmd_address = mmd_reg & ~MII_ADDR_C45; 1159 else 1160 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); 1161 1162 /* The PCS registers are accessed using mmio. The underlying 1163 * management interface uses indirect addressing to access the MMD 1164 * register sets. This requires accessing of the PCS register in two 1165 * phases, an address phase and a data phase. 1166 * 1167 * The mmio interface is based on 16-bit offsets and values. All 1168 * register offsets must therefore be adjusted by left shifting the 1169 * offset 1 bit and reading 16 bits of data. 1170 */ 1171 mmd_address <<= 1; 1172 index = mmd_address & ~pdata->xpcs_window_mask; 1173 offset = pdata->xpcs_window + (mmd_address & pdata->xpcs_window_mask); 1174 1175 spin_lock_irqsave(&pdata->xpcs_lock, flags); 1176 XPCS32_IOWRITE(pdata, pdata->xpcs_window_sel_reg, index); 1177 mmd_data = XPCS16_IOREAD(pdata, offset); 1178 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); 1179 1180 return mmd_data; 1181 } 1182 1183 static void xgbe_write_mmd_regs_v2(struct xgbe_prv_data *pdata, int prtad, 1184 int mmd_reg, int mmd_data) 1185 { 1186 unsigned long flags; 1187 unsigned int mmd_address, index, offset; 1188 1189 if (mmd_reg & MII_ADDR_C45) 1190 mmd_address = mmd_reg & ~MII_ADDR_C45; 1191 else 1192 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); 1193 1194 /* The PCS registers are accessed using mmio. The underlying 1195 * management interface uses indirect addressing to access the MMD 1196 * register sets. This requires accessing of the PCS register in two 1197 * phases, an address phase and a data phase. 1198 * 1199 * The mmio interface is based on 16-bit offsets and values. All 1200 * register offsets must therefore be adjusted by left shifting the 1201 * offset 1 bit and writing 16 bits of data. 1202 */ 1203 mmd_address <<= 1; 1204 index = mmd_address & ~pdata->xpcs_window_mask; 1205 offset = pdata->xpcs_window + (mmd_address & pdata->xpcs_window_mask); 1206 1207 spin_lock_irqsave(&pdata->xpcs_lock, flags); 1208 XPCS32_IOWRITE(pdata, pdata->xpcs_window_sel_reg, index); 1209 XPCS16_IOWRITE(pdata, offset, mmd_data); 1210 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); 1211 } 1212 1213 static int xgbe_read_mmd_regs_v1(struct xgbe_prv_data *pdata, int prtad, 1214 int mmd_reg) 1215 { 1216 unsigned long flags; 1217 unsigned int mmd_address; 1218 int mmd_data; 1219 1220 if (mmd_reg & MII_ADDR_C45) 1221 mmd_address = mmd_reg & ~MII_ADDR_C45; 1222 else 1223 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); 1224 1225 /* The PCS registers are accessed using mmio. The underlying APB3 1226 * management interface uses indirect addressing to access the MMD 1227 * register sets. This requires accessing of the PCS register in two 1228 * phases, an address phase and a data phase. 1229 * 1230 * The mmio interface is based on 32-bit offsets and values. All 1231 * register offsets must therefore be adjusted by left shifting the 1232 * offset 2 bits and reading 32 bits of data. 1233 */ 1234 spin_lock_irqsave(&pdata->xpcs_lock, flags); 1235 XPCS32_IOWRITE(pdata, PCS_V1_WINDOW_SELECT, mmd_address >> 8); 1236 mmd_data = XPCS32_IOREAD(pdata, (mmd_address & 0xff) << 2); 1237 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); 1238 1239 return mmd_data; 1240 } 1241 1242 static void xgbe_write_mmd_regs_v1(struct xgbe_prv_data *pdata, int prtad, 1243 int mmd_reg, int mmd_data) 1244 { 1245 unsigned int mmd_address; 1246 unsigned long flags; 1247 1248 if (mmd_reg & MII_ADDR_C45) 1249 mmd_address = mmd_reg & ~MII_ADDR_C45; 1250 else 1251 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); 1252 1253 /* The PCS registers are accessed using mmio. The underlying APB3 1254 * management interface uses indirect addressing to access the MMD 1255 * register sets. This requires accessing of the PCS register in two 1256 * phases, an address phase and a data phase. 1257 * 1258 * The mmio interface is based on 32-bit offsets and values. All 1259 * register offsets must therefore be adjusted by left shifting the 1260 * offset 2 bits and writing 32 bits of data. 1261 */ 1262 spin_lock_irqsave(&pdata->xpcs_lock, flags); 1263 XPCS32_IOWRITE(pdata, PCS_V1_WINDOW_SELECT, mmd_address >> 8); 1264 XPCS32_IOWRITE(pdata, (mmd_address & 0xff) << 2, mmd_data); 1265 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); 1266 } 1267 1268 static int xgbe_read_mmd_regs(struct xgbe_prv_data *pdata, int prtad, 1269 int mmd_reg) 1270 { 1271 switch (pdata->vdata->xpcs_access) { 1272 case XGBE_XPCS_ACCESS_V1: 1273 return xgbe_read_mmd_regs_v1(pdata, prtad, mmd_reg); 1274 1275 case XGBE_XPCS_ACCESS_V2: 1276 default: 1277 return xgbe_read_mmd_regs_v2(pdata, prtad, mmd_reg); 1278 } 1279 } 1280 1281 static void xgbe_write_mmd_regs(struct xgbe_prv_data *pdata, int prtad, 1282 int mmd_reg, int mmd_data) 1283 { 1284 switch (pdata->vdata->xpcs_access) { 1285 case XGBE_XPCS_ACCESS_V1: 1286 return xgbe_write_mmd_regs_v1(pdata, prtad, mmd_reg, mmd_data); 1287 1288 case XGBE_XPCS_ACCESS_V2: 1289 default: 1290 return xgbe_write_mmd_regs_v2(pdata, prtad, mmd_reg, mmd_data); 1291 } 1292 } 1293 1294 static unsigned int xgbe_create_mdio_sca(int port, int reg) 1295 { 1296 unsigned int mdio_sca, da; 1297 1298 da = (reg & MII_ADDR_C45) ? reg >> 16 : 0; 1299 1300 mdio_sca = 0; 1301 XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, RA, reg); 1302 XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, PA, port); 1303 XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, DA, da); 1304 1305 return mdio_sca; 1306 } 1307 1308 static int xgbe_write_ext_mii_regs(struct xgbe_prv_data *pdata, int addr, 1309 int reg, u16 val) 1310 { 1311 unsigned int mdio_sca, mdio_sccd; 1312 1313 reinit_completion(&pdata->mdio_complete); 1314 1315 mdio_sca = xgbe_create_mdio_sca(addr, reg); 1316 XGMAC_IOWRITE(pdata, MAC_MDIOSCAR, mdio_sca); 1317 1318 mdio_sccd = 0; 1319 XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, DATA, val); 1320 XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, CMD, 1); 1321 XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, BUSY, 1); 1322 XGMAC_IOWRITE(pdata, MAC_MDIOSCCDR, mdio_sccd); 1323 1324 if (!wait_for_completion_timeout(&pdata->mdio_complete, HZ)) { 1325 netdev_err(pdata->netdev, "mdio write operation timed out\n"); 1326 return -ETIMEDOUT; 1327 } 1328 1329 return 0; 1330 } 1331 1332 static int xgbe_read_ext_mii_regs(struct xgbe_prv_data *pdata, int addr, 1333 int reg) 1334 { 1335 unsigned int mdio_sca, mdio_sccd; 1336 1337 reinit_completion(&pdata->mdio_complete); 1338 1339 mdio_sca = xgbe_create_mdio_sca(addr, reg); 1340 XGMAC_IOWRITE(pdata, MAC_MDIOSCAR, mdio_sca); 1341 1342 mdio_sccd = 0; 1343 XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, CMD, 3); 1344 XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, BUSY, 1); 1345 XGMAC_IOWRITE(pdata, MAC_MDIOSCCDR, mdio_sccd); 1346 1347 if (!wait_for_completion_timeout(&pdata->mdio_complete, HZ)) { 1348 netdev_err(pdata->netdev, "mdio read operation timed out\n"); 1349 return -ETIMEDOUT; 1350 } 1351 1352 return XGMAC_IOREAD_BITS(pdata, MAC_MDIOSCCDR, DATA); 1353 } 1354 1355 static int xgbe_set_ext_mii_mode(struct xgbe_prv_data *pdata, unsigned int port, 1356 enum xgbe_mdio_mode mode) 1357 { 1358 unsigned int reg_val = XGMAC_IOREAD(pdata, MAC_MDIOCL22R); 1359 1360 switch (mode) { 1361 case XGBE_MDIO_MODE_CL22: 1362 if (port > XGMAC_MAX_C22_PORT) 1363 return -EINVAL; 1364 reg_val |= (1 << port); 1365 break; 1366 case XGBE_MDIO_MODE_CL45: 1367 break; 1368 default: 1369 return -EINVAL; 1370 } 1371 1372 XGMAC_IOWRITE(pdata, MAC_MDIOCL22R, reg_val); 1373 1374 return 0; 1375 } 1376 1377 static int xgbe_tx_complete(struct xgbe_ring_desc *rdesc) 1378 { 1379 return !XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN); 1380 } 1381 1382 static int xgbe_disable_rx_csum(struct xgbe_prv_data *pdata) 1383 { 1384 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 0); 1385 1386 return 0; 1387 } 1388 1389 static int xgbe_enable_rx_csum(struct xgbe_prv_data *pdata) 1390 { 1391 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 1); 1392 1393 return 0; 1394 } 1395 1396 static void xgbe_tx_desc_reset(struct xgbe_ring_data *rdata) 1397 { 1398 struct xgbe_ring_desc *rdesc = rdata->rdesc; 1399 1400 /* Reset the Tx descriptor 1401 * Set buffer 1 (lo) address to zero 1402 * Set buffer 1 (hi) address to zero 1403 * Reset all other control bits (IC, TTSE, B2L & B1L) 1404 * Reset all other control bits (OWN, CTXT, FD, LD, CPC, CIC, etc) 1405 */ 1406 rdesc->desc0 = 0; 1407 rdesc->desc1 = 0; 1408 rdesc->desc2 = 0; 1409 rdesc->desc3 = 0; 1410 1411 /* Make sure ownership is written to the descriptor */ 1412 dma_wmb(); 1413 } 1414 1415 static void xgbe_tx_desc_init(struct xgbe_channel *channel) 1416 { 1417 struct xgbe_ring *ring = channel->tx_ring; 1418 struct xgbe_ring_data *rdata; 1419 int i; 1420 int start_index = ring->cur; 1421 1422 DBGPR("-->tx_desc_init\n"); 1423 1424 /* Initialze all descriptors */ 1425 for (i = 0; i < ring->rdesc_count; i++) { 1426 rdata = XGBE_GET_DESC_DATA(ring, i); 1427 1428 /* Initialize Tx descriptor */ 1429 xgbe_tx_desc_reset(rdata); 1430 } 1431 1432 /* Update the total number of Tx descriptors */ 1433 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDRLR, ring->rdesc_count - 1); 1434 1435 /* Update the starting address of descriptor ring */ 1436 rdata = XGBE_GET_DESC_DATA(ring, start_index); 1437 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_HI, 1438 upper_32_bits(rdata->rdesc_dma)); 1439 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_LO, 1440 lower_32_bits(rdata->rdesc_dma)); 1441 1442 DBGPR("<--tx_desc_init\n"); 1443 } 1444 1445 static void xgbe_rx_desc_reset(struct xgbe_prv_data *pdata, 1446 struct xgbe_ring_data *rdata, unsigned int index) 1447 { 1448 struct xgbe_ring_desc *rdesc = rdata->rdesc; 1449 unsigned int rx_usecs = pdata->rx_usecs; 1450 unsigned int rx_frames = pdata->rx_frames; 1451 unsigned int inte; 1452 dma_addr_t hdr_dma, buf_dma; 1453 1454 if (!rx_usecs && !rx_frames) { 1455 /* No coalescing, interrupt for every descriptor */ 1456 inte = 1; 1457 } else { 1458 /* Set interrupt based on Rx frame coalescing setting */ 1459 if (rx_frames && !((index + 1) % rx_frames)) 1460 inte = 1; 1461 else 1462 inte = 0; 1463 } 1464 1465 /* Reset the Rx descriptor 1466 * Set buffer 1 (lo) address to header dma address (lo) 1467 * Set buffer 1 (hi) address to header dma address (hi) 1468 * Set buffer 2 (lo) address to buffer dma address (lo) 1469 * Set buffer 2 (hi) address to buffer dma address (hi) and 1470 * set control bits OWN and INTE 1471 */ 1472 hdr_dma = rdata->rx.hdr.dma_base + rdata->rx.hdr.dma_off; 1473 buf_dma = rdata->rx.buf.dma_base + rdata->rx.buf.dma_off; 1474 rdesc->desc0 = cpu_to_le32(lower_32_bits(hdr_dma)); 1475 rdesc->desc1 = cpu_to_le32(upper_32_bits(hdr_dma)); 1476 rdesc->desc2 = cpu_to_le32(lower_32_bits(buf_dma)); 1477 rdesc->desc3 = cpu_to_le32(upper_32_bits(buf_dma)); 1478 1479 XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, INTE, inte); 1480 1481 /* Since the Rx DMA engine is likely running, make sure everything 1482 * is written to the descriptor(s) before setting the OWN bit 1483 * for the descriptor 1484 */ 1485 dma_wmb(); 1486 1487 XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN, 1); 1488 1489 /* Make sure ownership is written to the descriptor */ 1490 dma_wmb(); 1491 } 1492 1493 static void xgbe_rx_desc_init(struct xgbe_channel *channel) 1494 { 1495 struct xgbe_prv_data *pdata = channel->pdata; 1496 struct xgbe_ring *ring = channel->rx_ring; 1497 struct xgbe_ring_data *rdata; 1498 unsigned int start_index = ring->cur; 1499 unsigned int i; 1500 1501 DBGPR("-->rx_desc_init\n"); 1502 1503 /* Initialize all descriptors */ 1504 for (i = 0; i < ring->rdesc_count; i++) { 1505 rdata = XGBE_GET_DESC_DATA(ring, i); 1506 1507 /* Initialize Rx descriptor */ 1508 xgbe_rx_desc_reset(pdata, rdata, i); 1509 } 1510 1511 /* Update the total number of Rx descriptors */ 1512 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDRLR, ring->rdesc_count - 1); 1513 1514 /* Update the starting address of descriptor ring */ 1515 rdata = XGBE_GET_DESC_DATA(ring, start_index); 1516 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_HI, 1517 upper_32_bits(rdata->rdesc_dma)); 1518 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_LO, 1519 lower_32_bits(rdata->rdesc_dma)); 1520 1521 /* Update the Rx Descriptor Tail Pointer */ 1522 rdata = XGBE_GET_DESC_DATA(ring, start_index + ring->rdesc_count - 1); 1523 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO, 1524 lower_32_bits(rdata->rdesc_dma)); 1525 1526 DBGPR("<--rx_desc_init\n"); 1527 } 1528 1529 static void xgbe_update_tstamp_addend(struct xgbe_prv_data *pdata, 1530 unsigned int addend) 1531 { 1532 unsigned int count = 10000; 1533 1534 /* Set the addend register value and tell the device */ 1535 XGMAC_IOWRITE(pdata, MAC_TSAR, addend); 1536 XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 1); 1537 1538 /* Wait for addend update to complete */ 1539 while (--count && XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSADDREG)) 1540 udelay(5); 1541 1542 if (!count) 1543 netdev_err(pdata->netdev, 1544 "timed out updating timestamp addend register\n"); 1545 } 1546 1547 static void xgbe_set_tstamp_time(struct xgbe_prv_data *pdata, unsigned int sec, 1548 unsigned int nsec) 1549 { 1550 unsigned int count = 10000; 1551 1552 /* Set the time values and tell the device */ 1553 XGMAC_IOWRITE(pdata, MAC_STSUR, sec); 1554 XGMAC_IOWRITE(pdata, MAC_STNUR, nsec); 1555 XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSINIT, 1); 1556 1557 /* Wait for time update to complete */ 1558 while (--count && XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSINIT)) 1559 udelay(5); 1560 1561 if (!count) 1562 netdev_err(pdata->netdev, "timed out initializing timestamp\n"); 1563 } 1564 1565 static u64 xgbe_get_tstamp_time(struct xgbe_prv_data *pdata) 1566 { 1567 u64 nsec; 1568 1569 nsec = XGMAC_IOREAD(pdata, MAC_STSR); 1570 nsec *= NSEC_PER_SEC; 1571 nsec += XGMAC_IOREAD(pdata, MAC_STNR); 1572 1573 return nsec; 1574 } 1575 1576 static u64 xgbe_get_tx_tstamp(struct xgbe_prv_data *pdata) 1577 { 1578 unsigned int tx_snr, tx_ssr; 1579 u64 nsec; 1580 1581 if (pdata->vdata->tx_tstamp_workaround) { 1582 tx_snr = XGMAC_IOREAD(pdata, MAC_TXSNR); 1583 tx_ssr = XGMAC_IOREAD(pdata, MAC_TXSSR); 1584 } else { 1585 tx_ssr = XGMAC_IOREAD(pdata, MAC_TXSSR); 1586 tx_snr = XGMAC_IOREAD(pdata, MAC_TXSNR); 1587 } 1588 1589 if (XGMAC_GET_BITS(tx_snr, MAC_TXSNR, TXTSSTSMIS)) 1590 return 0; 1591 1592 nsec = tx_ssr; 1593 nsec *= NSEC_PER_SEC; 1594 nsec += tx_snr; 1595 1596 return nsec; 1597 } 1598 1599 static void xgbe_get_rx_tstamp(struct xgbe_packet_data *packet, 1600 struct xgbe_ring_desc *rdesc) 1601 { 1602 u64 nsec; 1603 1604 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_CONTEXT_DESC3, TSA) && 1605 !XGMAC_GET_BITS_LE(rdesc->desc3, RX_CONTEXT_DESC3, TSD)) { 1606 nsec = le32_to_cpu(rdesc->desc1); 1607 nsec <<= 32; 1608 nsec |= le32_to_cpu(rdesc->desc0); 1609 if (nsec != 0xffffffffffffffffULL) { 1610 packet->rx_tstamp = nsec; 1611 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1612 RX_TSTAMP, 1); 1613 } 1614 } 1615 } 1616 1617 static int xgbe_config_tstamp(struct xgbe_prv_data *pdata, 1618 unsigned int mac_tscr) 1619 { 1620 /* Set one nano-second accuracy */ 1621 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCTRLSSR, 1); 1622 1623 /* Set fine timestamp update */ 1624 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 1); 1625 1626 /* Overwrite earlier timestamps */ 1627 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TXTSSTSM, 1); 1628 1629 XGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr); 1630 1631 /* Exit if timestamping is not enabled */ 1632 if (!XGMAC_GET_BITS(mac_tscr, MAC_TSCR, TSENA)) 1633 return 0; 1634 1635 /* Initialize time registers */ 1636 XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SSINC, XGBE_TSTAMP_SSINC); 1637 XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SNSINC, XGBE_TSTAMP_SNSINC); 1638 xgbe_update_tstamp_addend(pdata, pdata->tstamp_addend); 1639 xgbe_set_tstamp_time(pdata, 0, 0); 1640 1641 /* Initialize the timecounter */ 1642 timecounter_init(&pdata->tstamp_tc, &pdata->tstamp_cc, 1643 ktime_to_ns(ktime_get_real())); 1644 1645 return 0; 1646 } 1647 1648 static void xgbe_tx_start_xmit(struct xgbe_channel *channel, 1649 struct xgbe_ring *ring) 1650 { 1651 struct xgbe_prv_data *pdata = channel->pdata; 1652 struct xgbe_ring_data *rdata; 1653 1654 /* Make sure everything is written before the register write */ 1655 wmb(); 1656 1657 /* Issue a poll command to Tx DMA by writing address 1658 * of next immediate free descriptor */ 1659 rdata = XGBE_GET_DESC_DATA(ring, ring->cur); 1660 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDTR_LO, 1661 lower_32_bits(rdata->rdesc_dma)); 1662 1663 /* Start the Tx timer */ 1664 if (pdata->tx_usecs && !channel->tx_timer_active) { 1665 channel->tx_timer_active = 1; 1666 mod_timer(&channel->tx_timer, 1667 jiffies + usecs_to_jiffies(pdata->tx_usecs)); 1668 } 1669 1670 ring->tx.xmit_more = 0; 1671 } 1672 1673 static void xgbe_dev_xmit(struct xgbe_channel *channel) 1674 { 1675 struct xgbe_prv_data *pdata = channel->pdata; 1676 struct xgbe_ring *ring = channel->tx_ring; 1677 struct xgbe_ring_data *rdata; 1678 struct xgbe_ring_desc *rdesc; 1679 struct xgbe_packet_data *packet = &ring->packet_data; 1680 unsigned int tx_packets, tx_bytes; 1681 unsigned int csum, tso, vlan, vxlan; 1682 unsigned int tso_context, vlan_context; 1683 unsigned int tx_set_ic; 1684 int start_index = ring->cur; 1685 int cur_index = ring->cur; 1686 int i; 1687 1688 DBGPR("-->xgbe_dev_xmit\n"); 1689 1690 tx_packets = packet->tx_packets; 1691 tx_bytes = packet->tx_bytes; 1692 1693 csum = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, 1694 CSUM_ENABLE); 1695 tso = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, 1696 TSO_ENABLE); 1697 vlan = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, 1698 VLAN_CTAG); 1699 vxlan = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, 1700 VXLAN); 1701 1702 if (tso && (packet->mss != ring->tx.cur_mss)) 1703 tso_context = 1; 1704 else 1705 tso_context = 0; 1706 1707 if (vlan && (packet->vlan_ctag != ring->tx.cur_vlan_ctag)) 1708 vlan_context = 1; 1709 else 1710 vlan_context = 0; 1711 1712 /* Determine if an interrupt should be generated for this Tx: 1713 * Interrupt: 1714 * - Tx frame count exceeds the frame count setting 1715 * - Addition of Tx frame count to the frame count since the 1716 * last interrupt was set exceeds the frame count setting 1717 * No interrupt: 1718 * - No frame count setting specified (ethtool -C ethX tx-frames 0) 1719 * - Addition of Tx frame count to the frame count since the 1720 * last interrupt was set does not exceed the frame count setting 1721 */ 1722 ring->coalesce_count += tx_packets; 1723 if (!pdata->tx_frames) 1724 tx_set_ic = 0; 1725 else if (tx_packets > pdata->tx_frames) 1726 tx_set_ic = 1; 1727 else if ((ring->coalesce_count % pdata->tx_frames) < tx_packets) 1728 tx_set_ic = 1; 1729 else 1730 tx_set_ic = 0; 1731 1732 rdata = XGBE_GET_DESC_DATA(ring, cur_index); 1733 rdesc = rdata->rdesc; 1734 1735 /* Create a context descriptor if this is a TSO packet */ 1736 if (tso_context || vlan_context) { 1737 if (tso_context) { 1738 netif_dbg(pdata, tx_queued, pdata->netdev, 1739 "TSO context descriptor, mss=%u\n", 1740 packet->mss); 1741 1742 /* Set the MSS size */ 1743 XGMAC_SET_BITS_LE(rdesc->desc2, TX_CONTEXT_DESC2, 1744 MSS, packet->mss); 1745 1746 /* Mark it as a CONTEXT descriptor */ 1747 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, 1748 CTXT, 1); 1749 1750 /* Indicate this descriptor contains the MSS */ 1751 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, 1752 TCMSSV, 1); 1753 1754 ring->tx.cur_mss = packet->mss; 1755 } 1756 1757 if (vlan_context) { 1758 netif_dbg(pdata, tx_queued, pdata->netdev, 1759 "VLAN context descriptor, ctag=%u\n", 1760 packet->vlan_ctag); 1761 1762 /* Mark it as a CONTEXT descriptor */ 1763 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, 1764 CTXT, 1); 1765 1766 /* Set the VLAN tag */ 1767 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, 1768 VT, packet->vlan_ctag); 1769 1770 /* Indicate this descriptor contains the VLAN tag */ 1771 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, 1772 VLTV, 1); 1773 1774 ring->tx.cur_vlan_ctag = packet->vlan_ctag; 1775 } 1776 1777 cur_index++; 1778 rdata = XGBE_GET_DESC_DATA(ring, cur_index); 1779 rdesc = rdata->rdesc; 1780 } 1781 1782 /* Update buffer address (for TSO this is the header) */ 1783 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma)); 1784 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma)); 1785 1786 /* Update the buffer length */ 1787 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, HL_B1L, 1788 rdata->skb_dma_len); 1789 1790 /* VLAN tag insertion check */ 1791 if (vlan) 1792 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, VTIR, 1793 TX_NORMAL_DESC2_VLAN_INSERT); 1794 1795 /* Timestamp enablement check */ 1796 if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP)) 1797 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, TTSE, 1); 1798 1799 /* Mark it as First Descriptor */ 1800 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FD, 1); 1801 1802 /* Mark it as a NORMAL descriptor */ 1803 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT, 0); 1804 1805 /* Set OWN bit if not the first descriptor */ 1806 if (cur_index != start_index) 1807 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1); 1808 1809 if (tso) { 1810 /* Enable TSO */ 1811 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TSE, 1); 1812 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TCPPL, 1813 packet->tcp_payload_len); 1814 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TCPHDRLEN, 1815 packet->tcp_header_len / 4); 1816 1817 pdata->ext_stats.tx_tso_packets += tx_packets; 1818 } else { 1819 /* Enable CRC and Pad Insertion */ 1820 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CPC, 0); 1821 1822 /* Enable HW CSUM */ 1823 if (csum) 1824 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, 1825 CIC, 0x3); 1826 1827 /* Set the total length to be transmitted */ 1828 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FL, 1829 packet->length); 1830 } 1831 1832 if (vxlan) { 1833 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, VNP, 1834 TX_NORMAL_DESC3_VXLAN_PACKET); 1835 1836 pdata->ext_stats.tx_vxlan_packets += packet->tx_packets; 1837 } 1838 1839 for (i = cur_index - start_index + 1; i < packet->rdesc_count; i++) { 1840 cur_index++; 1841 rdata = XGBE_GET_DESC_DATA(ring, cur_index); 1842 rdesc = rdata->rdesc; 1843 1844 /* Update buffer address */ 1845 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma)); 1846 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma)); 1847 1848 /* Update the buffer length */ 1849 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, HL_B1L, 1850 rdata->skb_dma_len); 1851 1852 /* Set OWN bit */ 1853 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1); 1854 1855 /* Mark it as NORMAL descriptor */ 1856 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT, 0); 1857 1858 /* Enable HW CSUM */ 1859 if (csum) 1860 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, 1861 CIC, 0x3); 1862 } 1863 1864 /* Set LAST bit for the last descriptor */ 1865 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD, 1); 1866 1867 /* Set IC bit based on Tx coalescing settings */ 1868 if (tx_set_ic) 1869 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, IC, 1); 1870 1871 /* Save the Tx info to report back during cleanup */ 1872 rdata->tx.packets = tx_packets; 1873 rdata->tx.bytes = tx_bytes; 1874 1875 pdata->ext_stats.txq_packets[channel->queue_index] += tx_packets; 1876 pdata->ext_stats.txq_bytes[channel->queue_index] += tx_bytes; 1877 1878 /* In case the Tx DMA engine is running, make sure everything 1879 * is written to the descriptor(s) before setting the OWN bit 1880 * for the first descriptor 1881 */ 1882 dma_wmb(); 1883 1884 /* Set OWN bit for the first descriptor */ 1885 rdata = XGBE_GET_DESC_DATA(ring, start_index); 1886 rdesc = rdata->rdesc; 1887 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1); 1888 1889 if (netif_msg_tx_queued(pdata)) 1890 xgbe_dump_tx_desc(pdata, ring, start_index, 1891 packet->rdesc_count, 1); 1892 1893 /* Make sure ownership is written to the descriptor */ 1894 smp_wmb(); 1895 1896 ring->cur = cur_index + 1; 1897 if (!netdev_xmit_more() || 1898 netif_xmit_stopped(netdev_get_tx_queue(pdata->netdev, 1899 channel->queue_index))) 1900 xgbe_tx_start_xmit(channel, ring); 1901 else 1902 ring->tx.xmit_more = 1; 1903 1904 DBGPR(" %s: descriptors %u to %u written\n", 1905 channel->name, start_index & (ring->rdesc_count - 1), 1906 (ring->cur - 1) & (ring->rdesc_count - 1)); 1907 1908 DBGPR("<--xgbe_dev_xmit\n"); 1909 } 1910 1911 static int xgbe_dev_read(struct xgbe_channel *channel) 1912 { 1913 struct xgbe_prv_data *pdata = channel->pdata; 1914 struct xgbe_ring *ring = channel->rx_ring; 1915 struct xgbe_ring_data *rdata; 1916 struct xgbe_ring_desc *rdesc; 1917 struct xgbe_packet_data *packet = &ring->packet_data; 1918 struct net_device *netdev = pdata->netdev; 1919 unsigned int err, etlt, l34t; 1920 1921 DBGPR("-->xgbe_dev_read: cur = %d\n", ring->cur); 1922 1923 rdata = XGBE_GET_DESC_DATA(ring, ring->cur); 1924 rdesc = rdata->rdesc; 1925 1926 /* Check for data availability */ 1927 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN)) 1928 return 1; 1929 1930 /* Make sure descriptor fields are read after reading the OWN bit */ 1931 dma_rmb(); 1932 1933 if (netif_msg_rx_status(pdata)) 1934 xgbe_dump_rx_desc(pdata, ring, ring->cur); 1935 1936 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CTXT)) { 1937 /* Timestamp Context Descriptor */ 1938 xgbe_get_rx_tstamp(packet, rdesc); 1939 1940 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1941 CONTEXT, 1); 1942 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1943 CONTEXT_NEXT, 0); 1944 return 0; 1945 } 1946 1947 /* Normal Descriptor, be sure Context Descriptor bit is off */ 1948 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, CONTEXT, 0); 1949 1950 /* Indicate if a Context Descriptor is next */ 1951 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CDA)) 1952 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1953 CONTEXT_NEXT, 1); 1954 1955 /* Get the header length */ 1956 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, FD)) { 1957 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1958 FIRST, 1); 1959 rdata->rx.hdr_len = XGMAC_GET_BITS_LE(rdesc->desc2, 1960 RX_NORMAL_DESC2, HL); 1961 if (rdata->rx.hdr_len) 1962 pdata->ext_stats.rx_split_header_packets++; 1963 } else { 1964 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1965 FIRST, 0); 1966 } 1967 1968 /* Get the RSS hash */ 1969 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, RSV)) { 1970 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1971 RSS_HASH, 1); 1972 1973 packet->rss_hash = le32_to_cpu(rdesc->desc1); 1974 1975 l34t = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, L34T); 1976 switch (l34t) { 1977 case RX_DESC3_L34T_IPV4_TCP: 1978 case RX_DESC3_L34T_IPV4_UDP: 1979 case RX_DESC3_L34T_IPV6_TCP: 1980 case RX_DESC3_L34T_IPV6_UDP: 1981 packet->rss_hash_type = PKT_HASH_TYPE_L4; 1982 break; 1983 default: 1984 packet->rss_hash_type = PKT_HASH_TYPE_L3; 1985 } 1986 } 1987 1988 /* Not all the data has been transferred for this packet */ 1989 if (!XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, LD)) 1990 return 0; 1991 1992 /* This is the last of the data for this packet */ 1993 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1994 LAST, 1); 1995 1996 /* Get the packet length */ 1997 rdata->rx.len = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, PL); 1998 1999 /* Set checksum done indicator as appropriate */ 2000 if (netdev->features & NETIF_F_RXCSUM) { 2001 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 2002 CSUM_DONE, 1); 2003 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 2004 TNPCSUM_DONE, 1); 2005 } 2006 2007 /* Set the tunneled packet indicator */ 2008 if (XGMAC_GET_BITS_LE(rdesc->desc2, RX_NORMAL_DESC2, TNP)) { 2009 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 2010 TNP, 1); 2011 pdata->ext_stats.rx_vxlan_packets++; 2012 2013 l34t = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, L34T); 2014 switch (l34t) { 2015 case RX_DESC3_L34T_IPV4_UNKNOWN: 2016 case RX_DESC3_L34T_IPV6_UNKNOWN: 2017 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 2018 TNPCSUM_DONE, 0); 2019 break; 2020 } 2021 } 2022 2023 /* Check for errors (only valid in last descriptor) */ 2024 err = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ES); 2025 etlt = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ETLT); 2026 netif_dbg(pdata, rx_status, netdev, "err=%u, etlt=%#x\n", err, etlt); 2027 2028 if (!err || !etlt) { 2029 /* No error if err is 0 or etlt is 0 */ 2030 if ((etlt == 0x09) && 2031 (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)) { 2032 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 2033 VLAN_CTAG, 1); 2034 packet->vlan_ctag = XGMAC_GET_BITS_LE(rdesc->desc0, 2035 RX_NORMAL_DESC0, 2036 OVT); 2037 netif_dbg(pdata, rx_status, netdev, "vlan-ctag=%#06x\n", 2038 packet->vlan_ctag); 2039 } 2040 } else { 2041 unsigned int tnp = XGMAC_GET_BITS(packet->attributes, 2042 RX_PACKET_ATTRIBUTES, TNP); 2043 2044 if ((etlt == 0x05) || (etlt == 0x06)) { 2045 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 2046 CSUM_DONE, 0); 2047 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 2048 TNPCSUM_DONE, 0); 2049 pdata->ext_stats.rx_csum_errors++; 2050 } else if (tnp && ((etlt == 0x09) || (etlt == 0x0a))) { 2051 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 2052 CSUM_DONE, 0); 2053 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 2054 TNPCSUM_DONE, 0); 2055 pdata->ext_stats.rx_vxlan_csum_errors++; 2056 } else { 2057 XGMAC_SET_BITS(packet->errors, RX_PACKET_ERRORS, 2058 FRAME, 1); 2059 } 2060 } 2061 2062 pdata->ext_stats.rxq_packets[channel->queue_index]++; 2063 pdata->ext_stats.rxq_bytes[channel->queue_index] += rdata->rx.len; 2064 2065 DBGPR("<--xgbe_dev_read: %s - descriptor=%u (cur=%d)\n", channel->name, 2066 ring->cur & (ring->rdesc_count - 1), ring->cur); 2067 2068 return 0; 2069 } 2070 2071 static int xgbe_is_context_desc(struct xgbe_ring_desc *rdesc) 2072 { 2073 /* Rx and Tx share CTXT bit, so check TDES3.CTXT bit */ 2074 return XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT); 2075 } 2076 2077 static int xgbe_is_last_desc(struct xgbe_ring_desc *rdesc) 2078 { 2079 /* Rx and Tx share LD bit, so check TDES3.LD bit */ 2080 return XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD); 2081 } 2082 2083 static int xgbe_enable_int(struct xgbe_channel *channel, 2084 enum xgbe_int int_id) 2085 { 2086 switch (int_id) { 2087 case XGMAC_INT_DMA_CH_SR_TI: 2088 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 1); 2089 break; 2090 case XGMAC_INT_DMA_CH_SR_TPS: 2091 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TXSE, 1); 2092 break; 2093 case XGMAC_INT_DMA_CH_SR_TBU: 2094 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TBUE, 1); 2095 break; 2096 case XGMAC_INT_DMA_CH_SR_RI: 2097 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 1); 2098 break; 2099 case XGMAC_INT_DMA_CH_SR_RBU: 2100 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RBUE, 1); 2101 break; 2102 case XGMAC_INT_DMA_CH_SR_RPS: 2103 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RSE, 1); 2104 break; 2105 case XGMAC_INT_DMA_CH_SR_TI_RI: 2106 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 1); 2107 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 1); 2108 break; 2109 case XGMAC_INT_DMA_CH_SR_FBE: 2110 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, FBEE, 1); 2111 break; 2112 case XGMAC_INT_DMA_ALL: 2113 channel->curr_ier |= channel->saved_ier; 2114 break; 2115 default: 2116 return -1; 2117 } 2118 2119 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, channel->curr_ier); 2120 2121 return 0; 2122 } 2123 2124 static int xgbe_disable_int(struct xgbe_channel *channel, 2125 enum xgbe_int int_id) 2126 { 2127 switch (int_id) { 2128 case XGMAC_INT_DMA_CH_SR_TI: 2129 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 0); 2130 break; 2131 case XGMAC_INT_DMA_CH_SR_TPS: 2132 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TXSE, 0); 2133 break; 2134 case XGMAC_INT_DMA_CH_SR_TBU: 2135 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TBUE, 0); 2136 break; 2137 case XGMAC_INT_DMA_CH_SR_RI: 2138 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 0); 2139 break; 2140 case XGMAC_INT_DMA_CH_SR_RBU: 2141 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RBUE, 0); 2142 break; 2143 case XGMAC_INT_DMA_CH_SR_RPS: 2144 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RSE, 0); 2145 break; 2146 case XGMAC_INT_DMA_CH_SR_TI_RI: 2147 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 0); 2148 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 0); 2149 break; 2150 case XGMAC_INT_DMA_CH_SR_FBE: 2151 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, FBEE, 0); 2152 break; 2153 case XGMAC_INT_DMA_ALL: 2154 channel->saved_ier = channel->curr_ier; 2155 channel->curr_ier = 0; 2156 break; 2157 default: 2158 return -1; 2159 } 2160 2161 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, channel->curr_ier); 2162 2163 return 0; 2164 } 2165 2166 static int __xgbe_exit(struct xgbe_prv_data *pdata) 2167 { 2168 unsigned int count = 2000; 2169 2170 DBGPR("-->xgbe_exit\n"); 2171 2172 /* Issue a software reset */ 2173 XGMAC_IOWRITE_BITS(pdata, DMA_MR, SWR, 1); 2174 usleep_range(10, 15); 2175 2176 /* Poll Until Poll Condition */ 2177 while (--count && XGMAC_IOREAD_BITS(pdata, DMA_MR, SWR)) 2178 usleep_range(500, 600); 2179 2180 if (!count) 2181 return -EBUSY; 2182 2183 DBGPR("<--xgbe_exit\n"); 2184 2185 return 0; 2186 } 2187 2188 static int xgbe_exit(struct xgbe_prv_data *pdata) 2189 { 2190 int ret; 2191 2192 /* To guard against possible incorrectly generated interrupts, 2193 * issue the software reset twice. 2194 */ 2195 ret = __xgbe_exit(pdata); 2196 if (ret) 2197 return ret; 2198 2199 return __xgbe_exit(pdata); 2200 } 2201 2202 static int xgbe_flush_tx_queues(struct xgbe_prv_data *pdata) 2203 { 2204 unsigned int i, count; 2205 2206 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) < 0x21) 2207 return 0; 2208 2209 for (i = 0; i < pdata->tx_q_count; i++) 2210 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, FTQ, 1); 2211 2212 /* Poll Until Poll Condition */ 2213 for (i = 0; i < pdata->tx_q_count; i++) { 2214 count = 2000; 2215 while (--count && XGMAC_MTL_IOREAD_BITS(pdata, i, 2216 MTL_Q_TQOMR, FTQ)) 2217 usleep_range(500, 600); 2218 2219 if (!count) 2220 return -EBUSY; 2221 } 2222 2223 return 0; 2224 } 2225 2226 static void xgbe_config_dma_bus(struct xgbe_prv_data *pdata) 2227 { 2228 unsigned int sbmr; 2229 2230 sbmr = XGMAC_IOREAD(pdata, DMA_SBMR); 2231 2232 /* Set enhanced addressing mode */ 2233 XGMAC_SET_BITS(sbmr, DMA_SBMR, EAME, 1); 2234 2235 /* Set the System Bus mode */ 2236 XGMAC_SET_BITS(sbmr, DMA_SBMR, UNDEF, 1); 2237 XGMAC_SET_BITS(sbmr, DMA_SBMR, BLEN, pdata->blen >> 2); 2238 XGMAC_SET_BITS(sbmr, DMA_SBMR, AAL, pdata->aal); 2239 XGMAC_SET_BITS(sbmr, DMA_SBMR, RD_OSR_LMT, pdata->rd_osr_limit - 1); 2240 XGMAC_SET_BITS(sbmr, DMA_SBMR, WR_OSR_LMT, pdata->wr_osr_limit - 1); 2241 2242 XGMAC_IOWRITE(pdata, DMA_SBMR, sbmr); 2243 2244 /* Set descriptor fetching threshold */ 2245 if (pdata->vdata->tx_desc_prefetch) 2246 XGMAC_IOWRITE_BITS(pdata, DMA_TXEDMACR, TDPS, 2247 pdata->vdata->tx_desc_prefetch); 2248 2249 if (pdata->vdata->rx_desc_prefetch) 2250 XGMAC_IOWRITE_BITS(pdata, DMA_RXEDMACR, RDPS, 2251 pdata->vdata->rx_desc_prefetch); 2252 } 2253 2254 static void xgbe_config_dma_cache(struct xgbe_prv_data *pdata) 2255 { 2256 XGMAC_IOWRITE(pdata, DMA_AXIARCR, pdata->arcr); 2257 XGMAC_IOWRITE(pdata, DMA_AXIAWCR, pdata->awcr); 2258 if (pdata->awarcr) 2259 XGMAC_IOWRITE(pdata, DMA_AXIAWARCR, pdata->awarcr); 2260 } 2261 2262 static void xgbe_config_mtl_mode(struct xgbe_prv_data *pdata) 2263 { 2264 unsigned int i; 2265 2266 /* Set Tx to weighted round robin scheduling algorithm */ 2267 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_WRR); 2268 2269 /* Set Tx traffic classes to use WRR algorithm with equal weights */ 2270 for (i = 0; i < pdata->hw_feat.tc_cnt; i++) { 2271 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA, 2272 MTL_TSA_ETS); 2273 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW, 1); 2274 } 2275 2276 /* Set Rx to strict priority algorithm */ 2277 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, RAA, MTL_RAA_SP); 2278 } 2279 2280 static void xgbe_queue_flow_control_threshold(struct xgbe_prv_data *pdata, 2281 unsigned int queue, 2282 unsigned int q_fifo_size) 2283 { 2284 unsigned int frame_fifo_size; 2285 unsigned int rfa, rfd; 2286 2287 frame_fifo_size = XGMAC_FLOW_CONTROL_ALIGN(xgbe_get_max_frame(pdata)); 2288 2289 if (pdata->pfcq[queue] && (q_fifo_size > pdata->pfc_rfa)) { 2290 /* PFC is active for this queue */ 2291 rfa = pdata->pfc_rfa; 2292 rfd = rfa + frame_fifo_size; 2293 if (rfd > XGMAC_FLOW_CONTROL_MAX) 2294 rfd = XGMAC_FLOW_CONTROL_MAX; 2295 if (rfa >= XGMAC_FLOW_CONTROL_MAX) 2296 rfa = XGMAC_FLOW_CONTROL_MAX - XGMAC_FLOW_CONTROL_UNIT; 2297 } else { 2298 /* This path deals with just maximum frame sizes which are 2299 * limited to a jumbo frame of 9,000 (plus headers, etc.) 2300 * so we can never exceed the maximum allowable RFA/RFD 2301 * values. 2302 */ 2303 if (q_fifo_size <= 2048) { 2304 /* rx_rfd to zero to signal no flow control */ 2305 pdata->rx_rfa[queue] = 0; 2306 pdata->rx_rfd[queue] = 0; 2307 return; 2308 } 2309 2310 if (q_fifo_size <= 4096) { 2311 /* Between 2048 and 4096 */ 2312 pdata->rx_rfa[queue] = 0; /* Full - 1024 bytes */ 2313 pdata->rx_rfd[queue] = 1; /* Full - 1536 bytes */ 2314 return; 2315 } 2316 2317 if (q_fifo_size <= frame_fifo_size) { 2318 /* Between 4096 and max-frame */ 2319 pdata->rx_rfa[queue] = 2; /* Full - 2048 bytes */ 2320 pdata->rx_rfd[queue] = 5; /* Full - 3584 bytes */ 2321 return; 2322 } 2323 2324 if (q_fifo_size <= (frame_fifo_size * 3)) { 2325 /* Between max-frame and 3 max-frames, 2326 * trigger if we get just over a frame of data and 2327 * resume when we have just under half a frame left. 2328 */ 2329 rfa = q_fifo_size - frame_fifo_size; 2330 rfd = rfa + (frame_fifo_size / 2); 2331 } else { 2332 /* Above 3 max-frames - trigger when just over 2333 * 2 frames of space available 2334 */ 2335 rfa = frame_fifo_size * 2; 2336 rfa += XGMAC_FLOW_CONTROL_UNIT; 2337 rfd = rfa + frame_fifo_size; 2338 } 2339 } 2340 2341 pdata->rx_rfa[queue] = XGMAC_FLOW_CONTROL_VALUE(rfa); 2342 pdata->rx_rfd[queue] = XGMAC_FLOW_CONTROL_VALUE(rfd); 2343 } 2344 2345 static void xgbe_calculate_flow_control_threshold(struct xgbe_prv_data *pdata, 2346 unsigned int *fifo) 2347 { 2348 unsigned int q_fifo_size; 2349 unsigned int i; 2350 2351 for (i = 0; i < pdata->rx_q_count; i++) { 2352 q_fifo_size = (fifo[i] + 1) * XGMAC_FIFO_UNIT; 2353 2354 xgbe_queue_flow_control_threshold(pdata, i, q_fifo_size); 2355 } 2356 } 2357 2358 static void xgbe_config_flow_control_threshold(struct xgbe_prv_data *pdata) 2359 { 2360 unsigned int i; 2361 2362 for (i = 0; i < pdata->rx_q_count; i++) { 2363 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFA, 2364 pdata->rx_rfa[i]); 2365 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFD, 2366 pdata->rx_rfd[i]); 2367 } 2368 } 2369 2370 static unsigned int xgbe_get_tx_fifo_size(struct xgbe_prv_data *pdata) 2371 { 2372 /* The configured value may not be the actual amount of fifo RAM */ 2373 return min_t(unsigned int, pdata->tx_max_fifo_size, 2374 pdata->hw_feat.tx_fifo_size); 2375 } 2376 2377 static unsigned int xgbe_get_rx_fifo_size(struct xgbe_prv_data *pdata) 2378 { 2379 /* The configured value may not be the actual amount of fifo RAM */ 2380 return min_t(unsigned int, pdata->rx_max_fifo_size, 2381 pdata->hw_feat.rx_fifo_size); 2382 } 2383 2384 static void xgbe_calculate_equal_fifo(unsigned int fifo_size, 2385 unsigned int queue_count, 2386 unsigned int *fifo) 2387 { 2388 unsigned int q_fifo_size; 2389 unsigned int p_fifo; 2390 unsigned int i; 2391 2392 q_fifo_size = fifo_size / queue_count; 2393 2394 /* Calculate the fifo setting by dividing the queue's fifo size 2395 * by the fifo allocation increment (with 0 representing the 2396 * base allocation increment so decrement the result by 1). 2397 */ 2398 p_fifo = q_fifo_size / XGMAC_FIFO_UNIT; 2399 if (p_fifo) 2400 p_fifo--; 2401 2402 /* Distribute the fifo equally amongst the queues */ 2403 for (i = 0; i < queue_count; i++) 2404 fifo[i] = p_fifo; 2405 } 2406 2407 static unsigned int xgbe_set_nonprio_fifos(unsigned int fifo_size, 2408 unsigned int queue_count, 2409 unsigned int *fifo) 2410 { 2411 unsigned int i; 2412 2413 BUILD_BUG_ON_NOT_POWER_OF_2(XGMAC_FIFO_MIN_ALLOC); 2414 2415 if (queue_count <= IEEE_8021QAZ_MAX_TCS) 2416 return fifo_size; 2417 2418 /* Rx queues 9 and up are for specialized packets, 2419 * such as PTP or DCB control packets, etc. and 2420 * don't require a large fifo 2421 */ 2422 for (i = IEEE_8021QAZ_MAX_TCS; i < queue_count; i++) { 2423 fifo[i] = (XGMAC_FIFO_MIN_ALLOC / XGMAC_FIFO_UNIT) - 1; 2424 fifo_size -= XGMAC_FIFO_MIN_ALLOC; 2425 } 2426 2427 return fifo_size; 2428 } 2429 2430 static unsigned int xgbe_get_pfc_delay(struct xgbe_prv_data *pdata) 2431 { 2432 unsigned int delay; 2433 2434 /* If a delay has been provided, use that */ 2435 if (pdata->pfc->delay) 2436 return pdata->pfc->delay / 8; 2437 2438 /* Allow for two maximum size frames */ 2439 delay = xgbe_get_max_frame(pdata); 2440 delay += XGMAC_ETH_PREAMBLE; 2441 delay *= 2; 2442 2443 /* Allow for PFC frame */ 2444 delay += XGMAC_PFC_DATA_LEN; 2445 delay += ETH_HLEN + ETH_FCS_LEN; 2446 delay += XGMAC_ETH_PREAMBLE; 2447 2448 /* Allow for miscellaneous delays (LPI exit, cable, etc.) */ 2449 delay += XGMAC_PFC_DELAYS; 2450 2451 return delay; 2452 } 2453 2454 static unsigned int xgbe_get_pfc_queues(struct xgbe_prv_data *pdata) 2455 { 2456 unsigned int count, prio_queues; 2457 unsigned int i; 2458 2459 if (!pdata->pfc->pfc_en) 2460 return 0; 2461 2462 count = 0; 2463 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count); 2464 for (i = 0; i < prio_queues; i++) { 2465 if (!xgbe_is_pfc_queue(pdata, i)) 2466 continue; 2467 2468 pdata->pfcq[i] = 1; 2469 count++; 2470 } 2471 2472 return count; 2473 } 2474 2475 static void xgbe_calculate_dcb_fifo(struct xgbe_prv_data *pdata, 2476 unsigned int fifo_size, 2477 unsigned int *fifo) 2478 { 2479 unsigned int q_fifo_size, rem_fifo, addn_fifo; 2480 unsigned int prio_queues; 2481 unsigned int pfc_count; 2482 unsigned int i; 2483 2484 q_fifo_size = XGMAC_FIFO_ALIGN(xgbe_get_max_frame(pdata)); 2485 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count); 2486 pfc_count = xgbe_get_pfc_queues(pdata); 2487 2488 if (!pfc_count || ((q_fifo_size * prio_queues) > fifo_size)) { 2489 /* No traffic classes with PFC enabled or can't do lossless */ 2490 xgbe_calculate_equal_fifo(fifo_size, prio_queues, fifo); 2491 return; 2492 } 2493 2494 /* Calculate how much fifo we have to play with */ 2495 rem_fifo = fifo_size - (q_fifo_size * prio_queues); 2496 2497 /* Calculate how much more than base fifo PFC needs, which also 2498 * becomes the threshold activation point (RFA) 2499 */ 2500 pdata->pfc_rfa = xgbe_get_pfc_delay(pdata); 2501 pdata->pfc_rfa = XGMAC_FLOW_CONTROL_ALIGN(pdata->pfc_rfa); 2502 2503 if (pdata->pfc_rfa > q_fifo_size) { 2504 addn_fifo = pdata->pfc_rfa - q_fifo_size; 2505 addn_fifo = XGMAC_FIFO_ALIGN(addn_fifo); 2506 } else { 2507 addn_fifo = 0; 2508 } 2509 2510 /* Calculate DCB fifo settings: 2511 * - distribute remaining fifo between the VLAN priority 2512 * queues based on traffic class PFC enablement and overall 2513 * priority (0 is lowest priority, so start at highest) 2514 */ 2515 i = prio_queues; 2516 while (i > 0) { 2517 i--; 2518 2519 fifo[i] = (q_fifo_size / XGMAC_FIFO_UNIT) - 1; 2520 2521 if (!pdata->pfcq[i] || !addn_fifo) 2522 continue; 2523 2524 if (addn_fifo > rem_fifo) { 2525 netdev_warn(pdata->netdev, 2526 "RXq%u cannot set needed fifo size\n", i); 2527 if (!rem_fifo) 2528 continue; 2529 2530 addn_fifo = rem_fifo; 2531 } 2532 2533 fifo[i] += (addn_fifo / XGMAC_FIFO_UNIT); 2534 rem_fifo -= addn_fifo; 2535 } 2536 2537 if (rem_fifo) { 2538 unsigned int inc_fifo = rem_fifo / prio_queues; 2539 2540 /* Distribute remaining fifo across queues */ 2541 for (i = 0; i < prio_queues; i++) 2542 fifo[i] += (inc_fifo / XGMAC_FIFO_UNIT); 2543 } 2544 } 2545 2546 static void xgbe_config_tx_fifo_size(struct xgbe_prv_data *pdata) 2547 { 2548 unsigned int fifo_size; 2549 unsigned int fifo[XGBE_MAX_QUEUES]; 2550 unsigned int i; 2551 2552 fifo_size = xgbe_get_tx_fifo_size(pdata); 2553 2554 xgbe_calculate_equal_fifo(fifo_size, pdata->tx_q_count, fifo); 2555 2556 for (i = 0; i < pdata->tx_q_count; i++) 2557 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TQS, fifo[i]); 2558 2559 netif_info(pdata, drv, pdata->netdev, 2560 "%d Tx hardware queues, %d byte fifo per queue\n", 2561 pdata->tx_q_count, ((fifo[0] + 1) * XGMAC_FIFO_UNIT)); 2562 } 2563 2564 static void xgbe_config_rx_fifo_size(struct xgbe_prv_data *pdata) 2565 { 2566 unsigned int fifo_size; 2567 unsigned int fifo[XGBE_MAX_QUEUES]; 2568 unsigned int prio_queues; 2569 unsigned int i; 2570 2571 /* Clear any DCB related fifo/queue information */ 2572 memset(pdata->pfcq, 0, sizeof(pdata->pfcq)); 2573 pdata->pfc_rfa = 0; 2574 2575 fifo_size = xgbe_get_rx_fifo_size(pdata); 2576 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count); 2577 2578 /* Assign a minimum fifo to the non-VLAN priority queues */ 2579 fifo_size = xgbe_set_nonprio_fifos(fifo_size, pdata->rx_q_count, fifo); 2580 2581 if (pdata->pfc && pdata->ets) 2582 xgbe_calculate_dcb_fifo(pdata, fifo_size, fifo); 2583 else 2584 xgbe_calculate_equal_fifo(fifo_size, prio_queues, fifo); 2585 2586 for (i = 0; i < pdata->rx_q_count; i++) 2587 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RQS, fifo[i]); 2588 2589 xgbe_calculate_flow_control_threshold(pdata, fifo); 2590 xgbe_config_flow_control_threshold(pdata); 2591 2592 if (pdata->pfc && pdata->ets && pdata->pfc->pfc_en) { 2593 netif_info(pdata, drv, pdata->netdev, 2594 "%u Rx hardware queues\n", pdata->rx_q_count); 2595 for (i = 0; i < pdata->rx_q_count; i++) 2596 netif_info(pdata, drv, pdata->netdev, 2597 "RxQ%u, %u byte fifo queue\n", i, 2598 ((fifo[i] + 1) * XGMAC_FIFO_UNIT)); 2599 } else { 2600 netif_info(pdata, drv, pdata->netdev, 2601 "%u Rx hardware queues, %u byte fifo per queue\n", 2602 pdata->rx_q_count, 2603 ((fifo[0] + 1) * XGMAC_FIFO_UNIT)); 2604 } 2605 } 2606 2607 static void xgbe_config_queue_mapping(struct xgbe_prv_data *pdata) 2608 { 2609 unsigned int qptc, qptc_extra, queue; 2610 unsigned int prio_queues; 2611 unsigned int ppq, ppq_extra, prio; 2612 unsigned int mask; 2613 unsigned int i, j, reg, reg_val; 2614 2615 /* Map the MTL Tx Queues to Traffic Classes 2616 * Note: Tx Queues >= Traffic Classes 2617 */ 2618 qptc = pdata->tx_q_count / pdata->hw_feat.tc_cnt; 2619 qptc_extra = pdata->tx_q_count % pdata->hw_feat.tc_cnt; 2620 2621 for (i = 0, queue = 0; i < pdata->hw_feat.tc_cnt; i++) { 2622 for (j = 0; j < qptc; j++) { 2623 netif_dbg(pdata, drv, pdata->netdev, 2624 "TXq%u mapped to TC%u\n", queue, i); 2625 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR, 2626 Q2TCMAP, i); 2627 pdata->q2tc_map[queue++] = i; 2628 } 2629 2630 if (i < qptc_extra) { 2631 netif_dbg(pdata, drv, pdata->netdev, 2632 "TXq%u mapped to TC%u\n", queue, i); 2633 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR, 2634 Q2TCMAP, i); 2635 pdata->q2tc_map[queue++] = i; 2636 } 2637 } 2638 2639 /* Map the 8 VLAN priority values to available MTL Rx queues */ 2640 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count); 2641 ppq = IEEE_8021QAZ_MAX_TCS / prio_queues; 2642 ppq_extra = IEEE_8021QAZ_MAX_TCS % prio_queues; 2643 2644 reg = MAC_RQC2R; 2645 reg_val = 0; 2646 for (i = 0, prio = 0; i < prio_queues;) { 2647 mask = 0; 2648 for (j = 0; j < ppq; j++) { 2649 netif_dbg(pdata, drv, pdata->netdev, 2650 "PRIO%u mapped to RXq%u\n", prio, i); 2651 mask |= (1 << prio); 2652 pdata->prio2q_map[prio++] = i; 2653 } 2654 2655 if (i < ppq_extra) { 2656 netif_dbg(pdata, drv, pdata->netdev, 2657 "PRIO%u mapped to RXq%u\n", prio, i); 2658 mask |= (1 << prio); 2659 pdata->prio2q_map[prio++] = i; 2660 } 2661 2662 reg_val |= (mask << ((i++ % MAC_RQC2_Q_PER_REG) << 3)); 2663 2664 if ((i % MAC_RQC2_Q_PER_REG) && (i != prio_queues)) 2665 continue; 2666 2667 XGMAC_IOWRITE(pdata, reg, reg_val); 2668 reg += MAC_RQC2_INC; 2669 reg_val = 0; 2670 } 2671 2672 /* Select dynamic mapping of MTL Rx queue to DMA Rx channel */ 2673 reg = MTL_RQDCM0R; 2674 reg_val = 0; 2675 for (i = 0; i < pdata->rx_q_count;) { 2676 reg_val |= (0x80 << ((i++ % MTL_RQDCM_Q_PER_REG) << 3)); 2677 2678 if ((i % MTL_RQDCM_Q_PER_REG) && (i != pdata->rx_q_count)) 2679 continue; 2680 2681 XGMAC_IOWRITE(pdata, reg, reg_val); 2682 2683 reg += MTL_RQDCM_INC; 2684 reg_val = 0; 2685 } 2686 } 2687 2688 static void xgbe_config_tc(struct xgbe_prv_data *pdata) 2689 { 2690 unsigned int offset, queue, prio; 2691 u8 i; 2692 2693 netdev_reset_tc(pdata->netdev); 2694 if (!pdata->num_tcs) 2695 return; 2696 2697 netdev_set_num_tc(pdata->netdev, pdata->num_tcs); 2698 2699 for (i = 0, queue = 0, offset = 0; i < pdata->num_tcs; i++) { 2700 while ((queue < pdata->tx_q_count) && 2701 (pdata->q2tc_map[queue] == i)) 2702 queue++; 2703 2704 netif_dbg(pdata, drv, pdata->netdev, "TC%u using TXq%u-%u\n", 2705 i, offset, queue - 1); 2706 netdev_set_tc_queue(pdata->netdev, i, queue - offset, offset); 2707 offset = queue; 2708 } 2709 2710 if (!pdata->ets) 2711 return; 2712 2713 for (prio = 0; prio < IEEE_8021QAZ_MAX_TCS; prio++) 2714 netdev_set_prio_tc_map(pdata->netdev, prio, 2715 pdata->ets->prio_tc[prio]); 2716 } 2717 2718 static void xgbe_config_dcb_tc(struct xgbe_prv_data *pdata) 2719 { 2720 struct ieee_ets *ets = pdata->ets; 2721 unsigned int total_weight, min_weight, weight; 2722 unsigned int mask, reg, reg_val; 2723 unsigned int i, prio; 2724 2725 if (!ets) 2726 return; 2727 2728 /* Set Tx to deficit weighted round robin scheduling algorithm (when 2729 * traffic class is using ETS algorithm) 2730 */ 2731 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_DWRR); 2732 2733 /* Set Traffic Class algorithms */ 2734 total_weight = pdata->netdev->mtu * pdata->hw_feat.tc_cnt; 2735 min_weight = total_weight / 100; 2736 if (!min_weight) 2737 min_weight = 1; 2738 2739 for (i = 0; i < pdata->hw_feat.tc_cnt; i++) { 2740 /* Map the priorities to the traffic class */ 2741 mask = 0; 2742 for (prio = 0; prio < IEEE_8021QAZ_MAX_TCS; prio++) { 2743 if (ets->prio_tc[prio] == i) 2744 mask |= (1 << prio); 2745 } 2746 mask &= 0xff; 2747 2748 netif_dbg(pdata, drv, pdata->netdev, "TC%u PRIO mask=%#x\n", 2749 i, mask); 2750 reg = MTL_TCPM0R + (MTL_TCPM_INC * (i / MTL_TCPM_TC_PER_REG)); 2751 reg_val = XGMAC_IOREAD(pdata, reg); 2752 2753 reg_val &= ~(0xff << ((i % MTL_TCPM_TC_PER_REG) << 3)); 2754 reg_val |= (mask << ((i % MTL_TCPM_TC_PER_REG) << 3)); 2755 2756 XGMAC_IOWRITE(pdata, reg, reg_val); 2757 2758 /* Set the traffic class algorithm */ 2759 switch (ets->tc_tsa[i]) { 2760 case IEEE_8021QAZ_TSA_STRICT: 2761 netif_dbg(pdata, drv, pdata->netdev, 2762 "TC%u using SP\n", i); 2763 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA, 2764 MTL_TSA_SP); 2765 break; 2766 case IEEE_8021QAZ_TSA_ETS: 2767 weight = total_weight * ets->tc_tx_bw[i] / 100; 2768 weight = clamp(weight, min_weight, total_weight); 2769 2770 netif_dbg(pdata, drv, pdata->netdev, 2771 "TC%u using DWRR (weight %u)\n", i, weight); 2772 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA, 2773 MTL_TSA_ETS); 2774 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW, 2775 weight); 2776 break; 2777 } 2778 } 2779 2780 xgbe_config_tc(pdata); 2781 } 2782 2783 static void xgbe_config_dcb_pfc(struct xgbe_prv_data *pdata) 2784 { 2785 if (!test_bit(XGBE_DOWN, &pdata->dev_state)) { 2786 /* Just stop the Tx queues while Rx fifo is changed */ 2787 netif_tx_stop_all_queues(pdata->netdev); 2788 2789 /* Suspend Rx so that fifo's can be adjusted */ 2790 pdata->hw_if.disable_rx(pdata); 2791 } 2792 2793 xgbe_config_rx_fifo_size(pdata); 2794 xgbe_config_flow_control(pdata); 2795 2796 if (!test_bit(XGBE_DOWN, &pdata->dev_state)) { 2797 /* Resume Rx */ 2798 pdata->hw_if.enable_rx(pdata); 2799 2800 /* Resume Tx queues */ 2801 netif_tx_start_all_queues(pdata->netdev); 2802 } 2803 } 2804 2805 static void xgbe_config_mac_address(struct xgbe_prv_data *pdata) 2806 { 2807 xgbe_set_mac_address(pdata, pdata->netdev->dev_addr); 2808 2809 /* Filtering is done using perfect filtering and hash filtering */ 2810 if (pdata->hw_feat.hash_table_size) { 2811 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1); 2812 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1); 2813 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HMC, 1); 2814 } 2815 } 2816 2817 static void xgbe_config_jumbo_enable(struct xgbe_prv_data *pdata) 2818 { 2819 unsigned int val; 2820 2821 val = (pdata->netdev->mtu > XGMAC_STD_PACKET_MTU) ? 1 : 0; 2822 2823 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, JE, val); 2824 } 2825 2826 static void xgbe_config_mac_speed(struct xgbe_prv_data *pdata) 2827 { 2828 xgbe_set_speed(pdata, pdata->phy_speed); 2829 } 2830 2831 static void xgbe_config_checksum_offload(struct xgbe_prv_data *pdata) 2832 { 2833 if (pdata->netdev->features & NETIF_F_RXCSUM) 2834 xgbe_enable_rx_csum(pdata); 2835 else 2836 xgbe_disable_rx_csum(pdata); 2837 } 2838 2839 static void xgbe_config_vlan_support(struct xgbe_prv_data *pdata) 2840 { 2841 /* Indicate that VLAN Tx CTAGs come from context descriptors */ 2842 XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, CSVL, 0); 2843 XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, VLTI, 1); 2844 2845 /* Set the current VLAN Hash Table register value */ 2846 xgbe_update_vlan_hash_table(pdata); 2847 2848 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER) 2849 xgbe_enable_rx_vlan_filtering(pdata); 2850 else 2851 xgbe_disable_rx_vlan_filtering(pdata); 2852 2853 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) 2854 xgbe_enable_rx_vlan_stripping(pdata); 2855 else 2856 xgbe_disable_rx_vlan_stripping(pdata); 2857 } 2858 2859 static u64 xgbe_mmc_read(struct xgbe_prv_data *pdata, unsigned int reg_lo) 2860 { 2861 bool read_hi; 2862 u64 val; 2863 2864 if (pdata->vdata->mmc_64bit) { 2865 switch (reg_lo) { 2866 /* These registers are always 32 bit */ 2867 case MMC_RXRUNTERROR: 2868 case MMC_RXJABBERERROR: 2869 case MMC_RXUNDERSIZE_G: 2870 case MMC_RXOVERSIZE_G: 2871 case MMC_RXWATCHDOGERROR: 2872 read_hi = false; 2873 break; 2874 2875 default: 2876 read_hi = true; 2877 } 2878 } else { 2879 switch (reg_lo) { 2880 /* These registers are always 64 bit */ 2881 case MMC_TXOCTETCOUNT_GB_LO: 2882 case MMC_TXOCTETCOUNT_G_LO: 2883 case MMC_RXOCTETCOUNT_GB_LO: 2884 case MMC_RXOCTETCOUNT_G_LO: 2885 read_hi = true; 2886 break; 2887 2888 default: 2889 read_hi = false; 2890 } 2891 } 2892 2893 val = XGMAC_IOREAD(pdata, reg_lo); 2894 2895 if (read_hi) 2896 val |= ((u64)XGMAC_IOREAD(pdata, reg_lo + 4) << 32); 2897 2898 return val; 2899 } 2900 2901 static void xgbe_tx_mmc_int(struct xgbe_prv_data *pdata) 2902 { 2903 struct xgbe_mmc_stats *stats = &pdata->mmc_stats; 2904 unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_TISR); 2905 2906 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXOCTETCOUNT_GB)) 2907 stats->txoctetcount_gb += 2908 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO); 2909 2910 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXFRAMECOUNT_GB)) 2911 stats->txframecount_gb += 2912 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO); 2913 2914 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXBROADCASTFRAMES_G)) 2915 stats->txbroadcastframes_g += 2916 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO); 2917 2918 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXMULTICASTFRAMES_G)) 2919 stats->txmulticastframes_g += 2920 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO); 2921 2922 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX64OCTETS_GB)) 2923 stats->tx64octets_gb += 2924 xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO); 2925 2926 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX65TO127OCTETS_GB)) 2927 stats->tx65to127octets_gb += 2928 xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO); 2929 2930 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX128TO255OCTETS_GB)) 2931 stats->tx128to255octets_gb += 2932 xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO); 2933 2934 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX256TO511OCTETS_GB)) 2935 stats->tx256to511octets_gb += 2936 xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO); 2937 2938 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX512TO1023OCTETS_GB)) 2939 stats->tx512to1023octets_gb += 2940 xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO); 2941 2942 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX1024TOMAXOCTETS_GB)) 2943 stats->tx1024tomaxoctets_gb += 2944 xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO); 2945 2946 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXUNICASTFRAMES_GB)) 2947 stats->txunicastframes_gb += 2948 xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO); 2949 2950 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXMULTICASTFRAMES_GB)) 2951 stats->txmulticastframes_gb += 2952 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO); 2953 2954 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXBROADCASTFRAMES_GB)) 2955 stats->txbroadcastframes_g += 2956 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO); 2957 2958 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXUNDERFLOWERROR)) 2959 stats->txunderflowerror += 2960 xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO); 2961 2962 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXOCTETCOUNT_G)) 2963 stats->txoctetcount_g += 2964 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO); 2965 2966 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXFRAMECOUNT_G)) 2967 stats->txframecount_g += 2968 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO); 2969 2970 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXPAUSEFRAMES)) 2971 stats->txpauseframes += 2972 xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO); 2973 2974 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXVLANFRAMES_G)) 2975 stats->txvlanframes_g += 2976 xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO); 2977 } 2978 2979 static void xgbe_rx_mmc_int(struct xgbe_prv_data *pdata) 2980 { 2981 struct xgbe_mmc_stats *stats = &pdata->mmc_stats; 2982 unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_RISR); 2983 2984 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXFRAMECOUNT_GB)) 2985 stats->rxframecount_gb += 2986 xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO); 2987 2988 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOCTETCOUNT_GB)) 2989 stats->rxoctetcount_gb += 2990 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO); 2991 2992 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOCTETCOUNT_G)) 2993 stats->rxoctetcount_g += 2994 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO); 2995 2996 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXBROADCASTFRAMES_G)) 2997 stats->rxbroadcastframes_g += 2998 xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO); 2999 3000 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXMULTICASTFRAMES_G)) 3001 stats->rxmulticastframes_g += 3002 xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO); 3003 3004 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXCRCERROR)) 3005 stats->rxcrcerror += 3006 xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO); 3007 3008 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXRUNTERROR)) 3009 stats->rxrunterror += 3010 xgbe_mmc_read(pdata, MMC_RXRUNTERROR); 3011 3012 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXJABBERERROR)) 3013 stats->rxjabbererror += 3014 xgbe_mmc_read(pdata, MMC_RXJABBERERROR); 3015 3016 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXUNDERSIZE_G)) 3017 stats->rxundersize_g += 3018 xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G); 3019 3020 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOVERSIZE_G)) 3021 stats->rxoversize_g += 3022 xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G); 3023 3024 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX64OCTETS_GB)) 3025 stats->rx64octets_gb += 3026 xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO); 3027 3028 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX65TO127OCTETS_GB)) 3029 stats->rx65to127octets_gb += 3030 xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO); 3031 3032 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX128TO255OCTETS_GB)) 3033 stats->rx128to255octets_gb += 3034 xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO); 3035 3036 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX256TO511OCTETS_GB)) 3037 stats->rx256to511octets_gb += 3038 xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO); 3039 3040 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX512TO1023OCTETS_GB)) 3041 stats->rx512to1023octets_gb += 3042 xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO); 3043 3044 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX1024TOMAXOCTETS_GB)) 3045 stats->rx1024tomaxoctets_gb += 3046 xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO); 3047 3048 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXUNICASTFRAMES_G)) 3049 stats->rxunicastframes_g += 3050 xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO); 3051 3052 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXLENGTHERROR)) 3053 stats->rxlengtherror += 3054 xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO); 3055 3056 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOUTOFRANGETYPE)) 3057 stats->rxoutofrangetype += 3058 xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO); 3059 3060 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXPAUSEFRAMES)) 3061 stats->rxpauseframes += 3062 xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO); 3063 3064 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXFIFOOVERFLOW)) 3065 stats->rxfifooverflow += 3066 xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO); 3067 3068 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXVLANFRAMES_GB)) 3069 stats->rxvlanframes_gb += 3070 xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO); 3071 3072 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXWATCHDOGERROR)) 3073 stats->rxwatchdogerror += 3074 xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR); 3075 } 3076 3077 static void xgbe_read_mmc_stats(struct xgbe_prv_data *pdata) 3078 { 3079 struct xgbe_mmc_stats *stats = &pdata->mmc_stats; 3080 3081 /* Freeze counters */ 3082 XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 1); 3083 3084 stats->txoctetcount_gb += 3085 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO); 3086 3087 stats->txframecount_gb += 3088 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO); 3089 3090 stats->txbroadcastframes_g += 3091 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO); 3092 3093 stats->txmulticastframes_g += 3094 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO); 3095 3096 stats->tx64octets_gb += 3097 xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO); 3098 3099 stats->tx65to127octets_gb += 3100 xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO); 3101 3102 stats->tx128to255octets_gb += 3103 xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO); 3104 3105 stats->tx256to511octets_gb += 3106 xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO); 3107 3108 stats->tx512to1023octets_gb += 3109 xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO); 3110 3111 stats->tx1024tomaxoctets_gb += 3112 xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO); 3113 3114 stats->txunicastframes_gb += 3115 xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO); 3116 3117 stats->txmulticastframes_gb += 3118 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO); 3119 3120 stats->txbroadcastframes_g += 3121 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO); 3122 3123 stats->txunderflowerror += 3124 xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO); 3125 3126 stats->txoctetcount_g += 3127 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO); 3128 3129 stats->txframecount_g += 3130 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO); 3131 3132 stats->txpauseframes += 3133 xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO); 3134 3135 stats->txvlanframes_g += 3136 xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO); 3137 3138 stats->rxframecount_gb += 3139 xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO); 3140 3141 stats->rxoctetcount_gb += 3142 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO); 3143 3144 stats->rxoctetcount_g += 3145 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO); 3146 3147 stats->rxbroadcastframes_g += 3148 xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO); 3149 3150 stats->rxmulticastframes_g += 3151 xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO); 3152 3153 stats->rxcrcerror += 3154 xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO); 3155 3156 stats->rxrunterror += 3157 xgbe_mmc_read(pdata, MMC_RXRUNTERROR); 3158 3159 stats->rxjabbererror += 3160 xgbe_mmc_read(pdata, MMC_RXJABBERERROR); 3161 3162 stats->rxundersize_g += 3163 xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G); 3164 3165 stats->rxoversize_g += 3166 xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G); 3167 3168 stats->rx64octets_gb += 3169 xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO); 3170 3171 stats->rx65to127octets_gb += 3172 xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO); 3173 3174 stats->rx128to255octets_gb += 3175 xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO); 3176 3177 stats->rx256to511octets_gb += 3178 xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO); 3179 3180 stats->rx512to1023octets_gb += 3181 xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO); 3182 3183 stats->rx1024tomaxoctets_gb += 3184 xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO); 3185 3186 stats->rxunicastframes_g += 3187 xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO); 3188 3189 stats->rxlengtherror += 3190 xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO); 3191 3192 stats->rxoutofrangetype += 3193 xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO); 3194 3195 stats->rxpauseframes += 3196 xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO); 3197 3198 stats->rxfifooverflow += 3199 xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO); 3200 3201 stats->rxvlanframes_gb += 3202 xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO); 3203 3204 stats->rxwatchdogerror += 3205 xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR); 3206 3207 /* Un-freeze counters */ 3208 XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 0); 3209 } 3210 3211 static void xgbe_config_mmc(struct xgbe_prv_data *pdata) 3212 { 3213 /* Set counters to reset on read */ 3214 XGMAC_IOWRITE_BITS(pdata, MMC_CR, ROR, 1); 3215 3216 /* Reset the counters */ 3217 XGMAC_IOWRITE_BITS(pdata, MMC_CR, CR, 1); 3218 } 3219 3220 static void xgbe_txq_prepare_tx_stop(struct xgbe_prv_data *pdata, 3221 unsigned int queue) 3222 { 3223 unsigned int tx_status; 3224 unsigned long tx_timeout; 3225 3226 /* The Tx engine cannot be stopped if it is actively processing 3227 * packets. Wait for the Tx queue to empty the Tx fifo. Don't 3228 * wait forever though... 3229 */ 3230 tx_timeout = jiffies + (XGBE_DMA_STOP_TIMEOUT * HZ); 3231 while (time_before(jiffies, tx_timeout)) { 3232 tx_status = XGMAC_MTL_IOREAD(pdata, queue, MTL_Q_TQDR); 3233 if ((XGMAC_GET_BITS(tx_status, MTL_Q_TQDR, TRCSTS) != 1) && 3234 (XGMAC_GET_BITS(tx_status, MTL_Q_TQDR, TXQSTS) == 0)) 3235 break; 3236 3237 usleep_range(500, 1000); 3238 } 3239 3240 if (!time_before(jiffies, tx_timeout)) 3241 netdev_info(pdata->netdev, 3242 "timed out waiting for Tx queue %u to empty\n", 3243 queue); 3244 } 3245 3246 static void xgbe_prepare_tx_stop(struct xgbe_prv_data *pdata, 3247 unsigned int queue) 3248 { 3249 unsigned int tx_dsr, tx_pos, tx_qidx; 3250 unsigned int tx_status; 3251 unsigned long tx_timeout; 3252 3253 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) > 0x20) 3254 return xgbe_txq_prepare_tx_stop(pdata, queue); 3255 3256 /* Calculate the status register to read and the position within */ 3257 if (queue < DMA_DSRX_FIRST_QUEUE) { 3258 tx_dsr = DMA_DSR0; 3259 tx_pos = (queue * DMA_DSR_Q_WIDTH) + DMA_DSR0_TPS_START; 3260 } else { 3261 tx_qidx = queue - DMA_DSRX_FIRST_QUEUE; 3262 3263 tx_dsr = DMA_DSR1 + ((tx_qidx / DMA_DSRX_QPR) * DMA_DSRX_INC); 3264 tx_pos = ((tx_qidx % DMA_DSRX_QPR) * DMA_DSR_Q_WIDTH) + 3265 DMA_DSRX_TPS_START; 3266 } 3267 3268 /* The Tx engine cannot be stopped if it is actively processing 3269 * descriptors. Wait for the Tx engine to enter the stopped or 3270 * suspended state. Don't wait forever though... 3271 */ 3272 tx_timeout = jiffies + (XGBE_DMA_STOP_TIMEOUT * HZ); 3273 while (time_before(jiffies, tx_timeout)) { 3274 tx_status = XGMAC_IOREAD(pdata, tx_dsr); 3275 tx_status = GET_BITS(tx_status, tx_pos, DMA_DSR_TPS_WIDTH); 3276 if ((tx_status == DMA_TPS_STOPPED) || 3277 (tx_status == DMA_TPS_SUSPENDED)) 3278 break; 3279 3280 usleep_range(500, 1000); 3281 } 3282 3283 if (!time_before(jiffies, tx_timeout)) 3284 netdev_info(pdata->netdev, 3285 "timed out waiting for Tx DMA channel %u to stop\n", 3286 queue); 3287 } 3288 3289 static void xgbe_enable_tx(struct xgbe_prv_data *pdata) 3290 { 3291 unsigned int i; 3292 3293 /* Enable each Tx DMA channel */ 3294 for (i = 0; i < pdata->channel_count; i++) { 3295 if (!pdata->channel[i]->tx_ring) 3296 break; 3297 3298 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 1); 3299 } 3300 3301 /* Enable each Tx queue */ 3302 for (i = 0; i < pdata->tx_q_count; i++) 3303 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, 3304 MTL_Q_ENABLED); 3305 3306 /* Enable MAC Tx */ 3307 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1); 3308 } 3309 3310 static void xgbe_disable_tx(struct xgbe_prv_data *pdata) 3311 { 3312 unsigned int i; 3313 3314 /* Prepare for Tx DMA channel stop */ 3315 for (i = 0; i < pdata->tx_q_count; i++) 3316 xgbe_prepare_tx_stop(pdata, i); 3317 3318 /* Disable MAC Tx */ 3319 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0); 3320 3321 /* Disable each Tx queue */ 3322 for (i = 0; i < pdata->tx_q_count; i++) 3323 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, 0); 3324 3325 /* Disable each Tx DMA channel */ 3326 for (i = 0; i < pdata->channel_count; i++) { 3327 if (!pdata->channel[i]->tx_ring) 3328 break; 3329 3330 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 0); 3331 } 3332 } 3333 3334 static void xgbe_prepare_rx_stop(struct xgbe_prv_data *pdata, 3335 unsigned int queue) 3336 { 3337 unsigned int rx_status; 3338 unsigned long rx_timeout; 3339 3340 /* The Rx engine cannot be stopped if it is actively processing 3341 * packets. Wait for the Rx queue to empty the Rx fifo. Don't 3342 * wait forever though... 3343 */ 3344 rx_timeout = jiffies + (XGBE_DMA_STOP_TIMEOUT * HZ); 3345 while (time_before(jiffies, rx_timeout)) { 3346 rx_status = XGMAC_MTL_IOREAD(pdata, queue, MTL_Q_RQDR); 3347 if ((XGMAC_GET_BITS(rx_status, MTL_Q_RQDR, PRXQ) == 0) && 3348 (XGMAC_GET_BITS(rx_status, MTL_Q_RQDR, RXQSTS) == 0)) 3349 break; 3350 3351 usleep_range(500, 1000); 3352 } 3353 3354 if (!time_before(jiffies, rx_timeout)) 3355 netdev_info(pdata->netdev, 3356 "timed out waiting for Rx queue %u to empty\n", 3357 queue); 3358 } 3359 3360 static void xgbe_enable_rx(struct xgbe_prv_data *pdata) 3361 { 3362 unsigned int reg_val, i; 3363 3364 /* Enable each Rx DMA channel */ 3365 for (i = 0; i < pdata->channel_count; i++) { 3366 if (!pdata->channel[i]->rx_ring) 3367 break; 3368 3369 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 1); 3370 } 3371 3372 /* Enable each Rx queue */ 3373 reg_val = 0; 3374 for (i = 0; i < pdata->rx_q_count; i++) 3375 reg_val |= (0x02 << (i << 1)); 3376 XGMAC_IOWRITE(pdata, MAC_RQC0R, reg_val); 3377 3378 /* Enable MAC Rx */ 3379 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 1); 3380 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 1); 3381 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 1); 3382 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 1); 3383 } 3384 3385 static void xgbe_disable_rx(struct xgbe_prv_data *pdata) 3386 { 3387 unsigned int i; 3388 3389 /* Disable MAC Rx */ 3390 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 0); 3391 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 0); 3392 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 0); 3393 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 0); 3394 3395 /* Prepare for Rx DMA channel stop */ 3396 for (i = 0; i < pdata->rx_q_count; i++) 3397 xgbe_prepare_rx_stop(pdata, i); 3398 3399 /* Disable each Rx queue */ 3400 XGMAC_IOWRITE(pdata, MAC_RQC0R, 0); 3401 3402 /* Disable each Rx DMA channel */ 3403 for (i = 0; i < pdata->channel_count; i++) { 3404 if (!pdata->channel[i]->rx_ring) 3405 break; 3406 3407 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 0); 3408 } 3409 } 3410 3411 static void xgbe_powerup_tx(struct xgbe_prv_data *pdata) 3412 { 3413 unsigned int i; 3414 3415 /* Enable each Tx DMA channel */ 3416 for (i = 0; i < pdata->channel_count; i++) { 3417 if (!pdata->channel[i]->tx_ring) 3418 break; 3419 3420 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 1); 3421 } 3422 3423 /* Enable MAC Tx */ 3424 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1); 3425 } 3426 3427 static void xgbe_powerdown_tx(struct xgbe_prv_data *pdata) 3428 { 3429 unsigned int i; 3430 3431 /* Prepare for Tx DMA channel stop */ 3432 for (i = 0; i < pdata->tx_q_count; i++) 3433 xgbe_prepare_tx_stop(pdata, i); 3434 3435 /* Disable MAC Tx */ 3436 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0); 3437 3438 /* Disable each Tx DMA channel */ 3439 for (i = 0; i < pdata->channel_count; i++) { 3440 if (!pdata->channel[i]->tx_ring) 3441 break; 3442 3443 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 0); 3444 } 3445 } 3446 3447 static void xgbe_powerup_rx(struct xgbe_prv_data *pdata) 3448 { 3449 unsigned int i; 3450 3451 /* Enable each Rx DMA channel */ 3452 for (i = 0; i < pdata->channel_count; i++) { 3453 if (!pdata->channel[i]->rx_ring) 3454 break; 3455 3456 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 1); 3457 } 3458 } 3459 3460 static void xgbe_powerdown_rx(struct xgbe_prv_data *pdata) 3461 { 3462 unsigned int i; 3463 3464 /* Disable each Rx DMA channel */ 3465 for (i = 0; i < pdata->channel_count; i++) { 3466 if (!pdata->channel[i]->rx_ring) 3467 break; 3468 3469 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 0); 3470 } 3471 } 3472 3473 static int xgbe_init(struct xgbe_prv_data *pdata) 3474 { 3475 struct xgbe_desc_if *desc_if = &pdata->desc_if; 3476 int ret; 3477 3478 DBGPR("-->xgbe_init\n"); 3479 3480 /* Flush Tx queues */ 3481 ret = xgbe_flush_tx_queues(pdata); 3482 if (ret) { 3483 netdev_err(pdata->netdev, "error flushing TX queues\n"); 3484 return ret; 3485 } 3486 3487 /* 3488 * Initialize DMA related features 3489 */ 3490 xgbe_config_dma_bus(pdata); 3491 xgbe_config_dma_cache(pdata); 3492 xgbe_config_osp_mode(pdata); 3493 xgbe_config_pbl_val(pdata); 3494 xgbe_config_rx_coalesce(pdata); 3495 xgbe_config_tx_coalesce(pdata); 3496 xgbe_config_rx_buffer_size(pdata); 3497 xgbe_config_tso_mode(pdata); 3498 xgbe_config_sph_mode(pdata); 3499 xgbe_config_rss(pdata); 3500 desc_if->wrapper_tx_desc_init(pdata); 3501 desc_if->wrapper_rx_desc_init(pdata); 3502 xgbe_enable_dma_interrupts(pdata); 3503 3504 /* 3505 * Initialize MTL related features 3506 */ 3507 xgbe_config_mtl_mode(pdata); 3508 xgbe_config_queue_mapping(pdata); 3509 xgbe_config_tsf_mode(pdata, pdata->tx_sf_mode); 3510 xgbe_config_rsf_mode(pdata, pdata->rx_sf_mode); 3511 xgbe_config_tx_threshold(pdata, pdata->tx_threshold); 3512 xgbe_config_rx_threshold(pdata, pdata->rx_threshold); 3513 xgbe_config_tx_fifo_size(pdata); 3514 xgbe_config_rx_fifo_size(pdata); 3515 /*TODO: Error Packet and undersized good Packet forwarding enable 3516 (FEP and FUP) 3517 */ 3518 xgbe_config_dcb_tc(pdata); 3519 xgbe_enable_mtl_interrupts(pdata); 3520 3521 /* 3522 * Initialize MAC related features 3523 */ 3524 xgbe_config_mac_address(pdata); 3525 xgbe_config_rx_mode(pdata); 3526 xgbe_config_jumbo_enable(pdata); 3527 xgbe_config_flow_control(pdata); 3528 xgbe_config_mac_speed(pdata); 3529 xgbe_config_checksum_offload(pdata); 3530 xgbe_config_vlan_support(pdata); 3531 xgbe_config_mmc(pdata); 3532 xgbe_enable_mac_interrupts(pdata); 3533 3534 /* 3535 * Initialize ECC related features 3536 */ 3537 xgbe_enable_ecc_interrupts(pdata); 3538 3539 DBGPR("<--xgbe_init\n"); 3540 3541 return 0; 3542 } 3543 3544 void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *hw_if) 3545 { 3546 DBGPR("-->xgbe_init_function_ptrs\n"); 3547 3548 hw_if->tx_complete = xgbe_tx_complete; 3549 3550 hw_if->set_mac_address = xgbe_set_mac_address; 3551 hw_if->config_rx_mode = xgbe_config_rx_mode; 3552 3553 hw_if->enable_rx_csum = xgbe_enable_rx_csum; 3554 hw_if->disable_rx_csum = xgbe_disable_rx_csum; 3555 3556 hw_if->enable_rx_vlan_stripping = xgbe_enable_rx_vlan_stripping; 3557 hw_if->disable_rx_vlan_stripping = xgbe_disable_rx_vlan_stripping; 3558 hw_if->enable_rx_vlan_filtering = xgbe_enable_rx_vlan_filtering; 3559 hw_if->disable_rx_vlan_filtering = xgbe_disable_rx_vlan_filtering; 3560 hw_if->update_vlan_hash_table = xgbe_update_vlan_hash_table; 3561 3562 hw_if->read_mmd_regs = xgbe_read_mmd_regs; 3563 hw_if->write_mmd_regs = xgbe_write_mmd_regs; 3564 3565 hw_if->set_speed = xgbe_set_speed; 3566 3567 hw_if->set_ext_mii_mode = xgbe_set_ext_mii_mode; 3568 hw_if->read_ext_mii_regs = xgbe_read_ext_mii_regs; 3569 hw_if->write_ext_mii_regs = xgbe_write_ext_mii_regs; 3570 3571 hw_if->set_gpio = xgbe_set_gpio; 3572 hw_if->clr_gpio = xgbe_clr_gpio; 3573 3574 hw_if->enable_tx = xgbe_enable_tx; 3575 hw_if->disable_tx = xgbe_disable_tx; 3576 hw_if->enable_rx = xgbe_enable_rx; 3577 hw_if->disable_rx = xgbe_disable_rx; 3578 3579 hw_if->powerup_tx = xgbe_powerup_tx; 3580 hw_if->powerdown_tx = xgbe_powerdown_tx; 3581 hw_if->powerup_rx = xgbe_powerup_rx; 3582 hw_if->powerdown_rx = xgbe_powerdown_rx; 3583 3584 hw_if->dev_xmit = xgbe_dev_xmit; 3585 hw_if->dev_read = xgbe_dev_read; 3586 hw_if->enable_int = xgbe_enable_int; 3587 hw_if->disable_int = xgbe_disable_int; 3588 hw_if->init = xgbe_init; 3589 hw_if->exit = xgbe_exit; 3590 3591 /* Descriptor related Sequences have to be initialized here */ 3592 hw_if->tx_desc_init = xgbe_tx_desc_init; 3593 hw_if->rx_desc_init = xgbe_rx_desc_init; 3594 hw_if->tx_desc_reset = xgbe_tx_desc_reset; 3595 hw_if->rx_desc_reset = xgbe_rx_desc_reset; 3596 hw_if->is_last_desc = xgbe_is_last_desc; 3597 hw_if->is_context_desc = xgbe_is_context_desc; 3598 hw_if->tx_start_xmit = xgbe_tx_start_xmit; 3599 3600 /* For FLOW ctrl */ 3601 hw_if->config_tx_flow_control = xgbe_config_tx_flow_control; 3602 hw_if->config_rx_flow_control = xgbe_config_rx_flow_control; 3603 3604 /* For RX coalescing */ 3605 hw_if->config_rx_coalesce = xgbe_config_rx_coalesce; 3606 hw_if->config_tx_coalesce = xgbe_config_tx_coalesce; 3607 hw_if->usec_to_riwt = xgbe_usec_to_riwt; 3608 hw_if->riwt_to_usec = xgbe_riwt_to_usec; 3609 3610 /* For RX and TX threshold config */ 3611 hw_if->config_rx_threshold = xgbe_config_rx_threshold; 3612 hw_if->config_tx_threshold = xgbe_config_tx_threshold; 3613 3614 /* For RX and TX Store and Forward Mode config */ 3615 hw_if->config_rsf_mode = xgbe_config_rsf_mode; 3616 hw_if->config_tsf_mode = xgbe_config_tsf_mode; 3617 3618 /* For TX DMA Operating on Second Frame config */ 3619 hw_if->config_osp_mode = xgbe_config_osp_mode; 3620 3621 /* For MMC statistics support */ 3622 hw_if->tx_mmc_int = xgbe_tx_mmc_int; 3623 hw_if->rx_mmc_int = xgbe_rx_mmc_int; 3624 hw_if->read_mmc_stats = xgbe_read_mmc_stats; 3625 3626 /* For PTP config */ 3627 hw_if->config_tstamp = xgbe_config_tstamp; 3628 hw_if->update_tstamp_addend = xgbe_update_tstamp_addend; 3629 hw_if->set_tstamp_time = xgbe_set_tstamp_time; 3630 hw_if->get_tstamp_time = xgbe_get_tstamp_time; 3631 hw_if->get_tx_tstamp = xgbe_get_tx_tstamp; 3632 3633 /* For Data Center Bridging config */ 3634 hw_if->config_tc = xgbe_config_tc; 3635 hw_if->config_dcb_tc = xgbe_config_dcb_tc; 3636 hw_if->config_dcb_pfc = xgbe_config_dcb_pfc; 3637 3638 /* For Receive Side Scaling */ 3639 hw_if->enable_rss = xgbe_enable_rss; 3640 hw_if->disable_rss = xgbe_disable_rss; 3641 hw_if->set_rss_hash_key = xgbe_set_rss_hash_key; 3642 hw_if->set_rss_lookup_table = xgbe_set_rss_lookup_table; 3643 3644 /* For ECC */ 3645 hw_if->disable_ecc_ded = xgbe_disable_ecc_ded; 3646 hw_if->disable_ecc_sec = xgbe_disable_ecc_sec; 3647 3648 /* For VXLAN */ 3649 hw_if->enable_vxlan = xgbe_enable_vxlan; 3650 hw_if->disable_vxlan = xgbe_disable_vxlan; 3651 hw_if->set_vxlan_id = xgbe_set_vxlan_id; 3652 3653 DBGPR("<--xgbe_init_function_ptrs\n"); 3654 } 3655