1 /* 2 * AMD 10Gb Ethernet driver 3 * 4 * This file is available to you under your choice of the following two 5 * licenses: 6 * 7 * License 1: GPLv2 8 * 9 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. 10 * 11 * This file is free software; you may copy, redistribute and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation, either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program. If not, see <http://www.gnu.org/licenses/>. 23 * 24 * This file incorporates work covered by the following copyright and 25 * permission notice: 26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 28 * Inc. unless otherwise expressly agreed to in writing between Synopsys 29 * and you. 30 * 31 * The Software IS NOT an item of Licensed Software or Licensed Product 32 * under any End User Software License Agreement or Agreement for Licensed 33 * Product with Synopsys or any supplement thereto. Permission is hereby 34 * granted, free of charge, to any person obtaining a copy of this software 35 * annotated with this license and the Software, to deal in the Software 36 * without restriction, including without limitation the rights to use, 37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 38 * of the Software, and to permit persons to whom the Software is furnished 39 * to do so, subject to the following conditions: 40 * 41 * The above copyright notice and this permission notice shall be included 42 * in all copies or substantial portions of the Software. 43 * 44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 54 * THE POSSIBILITY OF SUCH DAMAGE. 55 * 56 * 57 * License 2: Modified BSD 58 * 59 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. 60 * All rights reserved. 61 * 62 * Redistribution and use in source and binary forms, with or without 63 * modification, are permitted provided that the following conditions are met: 64 * * Redistributions of source code must retain the above copyright 65 * notice, this list of conditions and the following disclaimer. 66 * * Redistributions in binary form must reproduce the above copyright 67 * notice, this list of conditions and the following disclaimer in the 68 * documentation and/or other materials provided with the distribution. 69 * * Neither the name of Advanced Micro Devices, Inc. nor the 70 * names of its contributors may be used to endorse or promote products 71 * derived from this software without specific prior written permission. 72 * 73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY 77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 83 * 84 * This file incorporates work covered by the following copyright and 85 * permission notice: 86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 88 * Inc. unless otherwise expressly agreed to in writing between Synopsys 89 * and you. 90 * 91 * The Software IS NOT an item of Licensed Software or Licensed Product 92 * under any End User Software License Agreement or Agreement for Licensed 93 * Product with Synopsys or any supplement thereto. Permission is hereby 94 * granted, free of charge, to any person obtaining a copy of this software 95 * annotated with this license and the Software, to deal in the Software 96 * without restriction, including without limitation the rights to use, 97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 98 * of the Software, and to permit persons to whom the Software is furnished 99 * to do so, subject to the following conditions: 100 * 101 * The above copyright notice and this permission notice shall be included 102 * in all copies or substantial portions of the Software. 103 * 104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 114 * THE POSSIBILITY OF SUCH DAMAGE. 115 */ 116 117 #include <linux/phy.h> 118 #include <linux/mdio.h> 119 #include <linux/clk.h> 120 #include <linux/bitrev.h> 121 #include <linux/crc32.h> 122 #include <linux/crc32poly.h> 123 124 #include "xgbe.h" 125 #include "xgbe-common.h" 126 127 static inline unsigned int xgbe_get_max_frame(struct xgbe_prv_data *pdata) 128 { 129 return pdata->netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 130 } 131 132 static unsigned int xgbe_usec_to_riwt(struct xgbe_prv_data *pdata, 133 unsigned int usec) 134 { 135 unsigned long rate; 136 unsigned int ret; 137 138 DBGPR("-->xgbe_usec_to_riwt\n"); 139 140 rate = pdata->sysclk_rate; 141 142 /* 143 * Convert the input usec value to the watchdog timer value. Each 144 * watchdog timer value is equivalent to 256 clock cycles. 145 * Calculate the required value as: 146 * ( usec * ( system_clock_mhz / 10^6 ) / 256 147 */ 148 ret = (usec * (rate / 1000000)) / 256; 149 150 DBGPR("<--xgbe_usec_to_riwt\n"); 151 152 return ret; 153 } 154 155 static unsigned int xgbe_riwt_to_usec(struct xgbe_prv_data *pdata, 156 unsigned int riwt) 157 { 158 unsigned long rate; 159 unsigned int ret; 160 161 DBGPR("-->xgbe_riwt_to_usec\n"); 162 163 rate = pdata->sysclk_rate; 164 165 /* 166 * Convert the input watchdog timer value to the usec value. Each 167 * watchdog timer value is equivalent to 256 clock cycles. 168 * Calculate the required value as: 169 * ( riwt * 256 ) / ( system_clock_mhz / 10^6 ) 170 */ 171 ret = (riwt * 256) / (rate / 1000000); 172 173 DBGPR("<--xgbe_riwt_to_usec\n"); 174 175 return ret; 176 } 177 178 static int xgbe_config_pbl_val(struct xgbe_prv_data *pdata) 179 { 180 unsigned int pblx8, pbl; 181 unsigned int i; 182 183 pblx8 = DMA_PBL_X8_DISABLE; 184 pbl = pdata->pbl; 185 186 if (pdata->pbl > 32) { 187 pblx8 = DMA_PBL_X8_ENABLE; 188 pbl >>= 3; 189 } 190 191 for (i = 0; i < pdata->channel_count; i++) { 192 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, PBLX8, 193 pblx8); 194 195 if (pdata->channel[i]->tx_ring) 196 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, 197 PBL, pbl); 198 199 if (pdata->channel[i]->rx_ring) 200 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, 201 PBL, pbl); 202 } 203 204 return 0; 205 } 206 207 static int xgbe_config_osp_mode(struct xgbe_prv_data *pdata) 208 { 209 unsigned int i; 210 211 for (i = 0; i < pdata->channel_count; i++) { 212 if (!pdata->channel[i]->tx_ring) 213 break; 214 215 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, OSP, 216 pdata->tx_osp_mode); 217 } 218 219 return 0; 220 } 221 222 static int xgbe_config_rsf_mode(struct xgbe_prv_data *pdata, unsigned int val) 223 { 224 unsigned int i; 225 226 for (i = 0; i < pdata->rx_q_count; i++) 227 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RSF, val); 228 229 return 0; 230 } 231 232 static int xgbe_config_tsf_mode(struct xgbe_prv_data *pdata, unsigned int val) 233 { 234 unsigned int i; 235 236 for (i = 0; i < pdata->tx_q_count; i++) 237 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TSF, val); 238 239 return 0; 240 } 241 242 static int xgbe_config_rx_threshold(struct xgbe_prv_data *pdata, 243 unsigned int val) 244 { 245 unsigned int i; 246 247 for (i = 0; i < pdata->rx_q_count; i++) 248 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RTC, val); 249 250 return 0; 251 } 252 253 static int xgbe_config_tx_threshold(struct xgbe_prv_data *pdata, 254 unsigned int val) 255 { 256 unsigned int i; 257 258 for (i = 0; i < pdata->tx_q_count; i++) 259 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TTC, val); 260 261 return 0; 262 } 263 264 static int xgbe_config_rx_coalesce(struct xgbe_prv_data *pdata) 265 { 266 unsigned int i; 267 268 for (i = 0; i < pdata->channel_count; i++) { 269 if (!pdata->channel[i]->rx_ring) 270 break; 271 272 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RIWT, RWT, 273 pdata->rx_riwt); 274 } 275 276 return 0; 277 } 278 279 static int xgbe_config_tx_coalesce(struct xgbe_prv_data *pdata) 280 { 281 return 0; 282 } 283 284 static void xgbe_config_rx_buffer_size(struct xgbe_prv_data *pdata) 285 { 286 unsigned int i; 287 288 for (i = 0; i < pdata->channel_count; i++) { 289 if (!pdata->channel[i]->rx_ring) 290 break; 291 292 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, RBSZ, 293 pdata->rx_buf_size); 294 } 295 } 296 297 static void xgbe_config_tso_mode(struct xgbe_prv_data *pdata) 298 { 299 unsigned int i; 300 301 for (i = 0; i < pdata->channel_count; i++) { 302 if (!pdata->channel[i]->tx_ring) 303 break; 304 305 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, TSE, 1); 306 } 307 } 308 309 static void xgbe_config_sph_mode(struct xgbe_prv_data *pdata) 310 { 311 unsigned int i; 312 313 for (i = 0; i < pdata->channel_count; i++) { 314 if (!pdata->channel[i]->rx_ring) 315 break; 316 317 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, SPH, 1); 318 } 319 320 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, HDSMS, XGBE_SPH_HDSMS_SIZE); 321 } 322 323 static void xgbe_disable_sph_mode(struct xgbe_prv_data *pdata) 324 { 325 unsigned int i; 326 327 for (i = 0; i < pdata->channel_count; i++) { 328 if (!pdata->channel[i]->rx_ring) 329 break; 330 331 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, SPH, 0); 332 } 333 } 334 335 static int xgbe_write_rss_reg(struct xgbe_prv_data *pdata, unsigned int type, 336 unsigned int index, unsigned int val) 337 { 338 unsigned int wait; 339 int ret = 0; 340 341 mutex_lock(&pdata->rss_mutex); 342 343 if (XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB)) { 344 ret = -EBUSY; 345 goto unlock; 346 } 347 348 XGMAC_IOWRITE(pdata, MAC_RSSDR, val); 349 350 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, RSSIA, index); 351 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, ADDRT, type); 352 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, CT, 0); 353 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, OB, 1); 354 355 wait = 1000; 356 while (wait--) { 357 if (!XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB)) 358 goto unlock; 359 360 usleep_range(1000, 1500); 361 } 362 363 ret = -EBUSY; 364 365 unlock: 366 mutex_unlock(&pdata->rss_mutex); 367 368 return ret; 369 } 370 371 static int xgbe_write_rss_hash_key(struct xgbe_prv_data *pdata) 372 { 373 unsigned int key_regs = sizeof(pdata->rss_key) / sizeof(u32); 374 unsigned int *key = (unsigned int *)&pdata->rss_key; 375 int ret; 376 377 while (key_regs--) { 378 ret = xgbe_write_rss_reg(pdata, XGBE_RSS_HASH_KEY_TYPE, 379 key_regs, *key++); 380 if (ret) 381 return ret; 382 } 383 384 return 0; 385 } 386 387 static int xgbe_write_rss_lookup_table(struct xgbe_prv_data *pdata) 388 { 389 unsigned int i; 390 int ret; 391 392 for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) { 393 ret = xgbe_write_rss_reg(pdata, 394 XGBE_RSS_LOOKUP_TABLE_TYPE, i, 395 pdata->rss_table[i]); 396 if (ret) 397 return ret; 398 } 399 400 return 0; 401 } 402 403 static int xgbe_set_rss_hash_key(struct xgbe_prv_data *pdata, const u8 *key) 404 { 405 memcpy(pdata->rss_key, key, sizeof(pdata->rss_key)); 406 407 return xgbe_write_rss_hash_key(pdata); 408 } 409 410 static int xgbe_set_rss_lookup_table(struct xgbe_prv_data *pdata, 411 const u32 *table) 412 { 413 unsigned int i; 414 415 for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) 416 XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH, table[i]); 417 418 return xgbe_write_rss_lookup_table(pdata); 419 } 420 421 static int xgbe_enable_rss(struct xgbe_prv_data *pdata) 422 { 423 int ret; 424 425 if (!pdata->hw_feat.rss) 426 return -EOPNOTSUPP; 427 428 /* Program the hash key */ 429 ret = xgbe_write_rss_hash_key(pdata); 430 if (ret) 431 return ret; 432 433 /* Program the lookup table */ 434 ret = xgbe_write_rss_lookup_table(pdata); 435 if (ret) 436 return ret; 437 438 /* Set the RSS options */ 439 XGMAC_IOWRITE(pdata, MAC_RSSCR, pdata->rss_options); 440 441 /* Enable RSS */ 442 XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 1); 443 444 return 0; 445 } 446 447 static int xgbe_disable_rss(struct xgbe_prv_data *pdata) 448 { 449 if (!pdata->hw_feat.rss) 450 return -EOPNOTSUPP; 451 452 XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 0); 453 454 return 0; 455 } 456 457 static void xgbe_config_rss(struct xgbe_prv_data *pdata) 458 { 459 int ret; 460 461 if (!pdata->hw_feat.rss) 462 return; 463 464 if (pdata->netdev->features & NETIF_F_RXHASH) 465 ret = xgbe_enable_rss(pdata); 466 else 467 ret = xgbe_disable_rss(pdata); 468 469 if (ret) 470 netdev_err(pdata->netdev, 471 "error configuring RSS, RSS disabled\n"); 472 } 473 474 static bool xgbe_is_pfc_queue(struct xgbe_prv_data *pdata, 475 unsigned int queue) 476 { 477 unsigned int prio, tc; 478 479 for (prio = 0; prio < IEEE_8021QAZ_MAX_TCS; prio++) { 480 /* Does this queue handle the priority? */ 481 if (pdata->prio2q_map[prio] != queue) 482 continue; 483 484 /* Get the Traffic Class for this priority */ 485 tc = pdata->ets->prio_tc[prio]; 486 487 /* Check if PFC is enabled for this traffic class */ 488 if (pdata->pfc->pfc_en & (1 << tc)) 489 return true; 490 } 491 492 return false; 493 } 494 495 static void xgbe_set_vxlan_id(struct xgbe_prv_data *pdata) 496 { 497 /* Program the VXLAN port */ 498 XGMAC_IOWRITE_BITS(pdata, MAC_TIR, TNID, pdata->vxlan_port); 499 500 netif_dbg(pdata, drv, pdata->netdev, "VXLAN tunnel id set to %hx\n", 501 pdata->vxlan_port); 502 } 503 504 static void xgbe_enable_vxlan(struct xgbe_prv_data *pdata) 505 { 506 if (!pdata->hw_feat.vxn) 507 return; 508 509 /* Program the VXLAN port */ 510 xgbe_set_vxlan_id(pdata); 511 512 /* Allow for IPv6/UDP zero-checksum VXLAN packets */ 513 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VUCC, 1); 514 515 /* Enable VXLAN tunneling mode */ 516 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, VNM, 0); 517 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, VNE, 1); 518 519 netif_dbg(pdata, drv, pdata->netdev, "VXLAN acceleration enabled\n"); 520 } 521 522 static void xgbe_disable_vxlan(struct xgbe_prv_data *pdata) 523 { 524 if (!pdata->hw_feat.vxn) 525 return; 526 527 /* Disable tunneling mode */ 528 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, VNE, 0); 529 530 /* Clear IPv6/UDP zero-checksum VXLAN packets setting */ 531 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VUCC, 0); 532 533 /* Clear the VXLAN port */ 534 XGMAC_IOWRITE_BITS(pdata, MAC_TIR, TNID, 0); 535 536 netif_dbg(pdata, drv, pdata->netdev, "VXLAN acceleration disabled\n"); 537 } 538 539 static unsigned int xgbe_get_fc_queue_count(struct xgbe_prv_data *pdata) 540 { 541 unsigned int max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES; 542 543 /* From MAC ver 30H the TFCR is per priority, instead of per queue */ 544 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) >= 0x30) 545 return max_q_count; 546 else 547 return min_t(unsigned int, pdata->tx_q_count, max_q_count); 548 } 549 550 static int xgbe_disable_tx_flow_control(struct xgbe_prv_data *pdata) 551 { 552 unsigned int reg, reg_val; 553 unsigned int i, q_count; 554 555 /* Clear MTL flow control */ 556 for (i = 0; i < pdata->rx_q_count; i++) 557 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 0); 558 559 /* Clear MAC flow control */ 560 q_count = xgbe_get_fc_queue_count(pdata); 561 reg = MAC_Q0TFCR; 562 for (i = 0; i < q_count; i++) { 563 reg_val = XGMAC_IOREAD(pdata, reg); 564 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 0); 565 XGMAC_IOWRITE(pdata, reg, reg_val); 566 567 reg += MAC_QTFCR_INC; 568 } 569 570 return 0; 571 } 572 573 static int xgbe_enable_tx_flow_control(struct xgbe_prv_data *pdata) 574 { 575 struct ieee_pfc *pfc = pdata->pfc; 576 struct ieee_ets *ets = pdata->ets; 577 unsigned int reg, reg_val; 578 unsigned int i, q_count; 579 580 /* Set MTL flow control */ 581 for (i = 0; i < pdata->rx_q_count; i++) { 582 unsigned int ehfc = 0; 583 584 if (pdata->rx_rfd[i]) { 585 /* Flow control thresholds are established */ 586 if (pfc && ets) { 587 if (xgbe_is_pfc_queue(pdata, i)) 588 ehfc = 1; 589 } else { 590 ehfc = 1; 591 } 592 } 593 594 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, ehfc); 595 596 netif_dbg(pdata, drv, pdata->netdev, 597 "flow control %s for RXq%u\n", 598 ehfc ? "enabled" : "disabled", i); 599 } 600 601 /* Set MAC flow control */ 602 q_count = xgbe_get_fc_queue_count(pdata); 603 reg = MAC_Q0TFCR; 604 for (i = 0; i < q_count; i++) { 605 reg_val = XGMAC_IOREAD(pdata, reg); 606 607 /* Enable transmit flow control */ 608 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 1); 609 /* Set pause time */ 610 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, PT, 0xffff); 611 612 XGMAC_IOWRITE(pdata, reg, reg_val); 613 614 reg += MAC_QTFCR_INC; 615 } 616 617 return 0; 618 } 619 620 static int xgbe_disable_rx_flow_control(struct xgbe_prv_data *pdata) 621 { 622 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 0); 623 624 return 0; 625 } 626 627 static int xgbe_enable_rx_flow_control(struct xgbe_prv_data *pdata) 628 { 629 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 1); 630 631 return 0; 632 } 633 634 static int xgbe_config_tx_flow_control(struct xgbe_prv_data *pdata) 635 { 636 struct ieee_pfc *pfc = pdata->pfc; 637 638 if (pdata->tx_pause || (pfc && pfc->pfc_en)) 639 xgbe_enable_tx_flow_control(pdata); 640 else 641 xgbe_disable_tx_flow_control(pdata); 642 643 return 0; 644 } 645 646 static int xgbe_config_rx_flow_control(struct xgbe_prv_data *pdata) 647 { 648 struct ieee_pfc *pfc = pdata->pfc; 649 650 if (pdata->rx_pause || (pfc && pfc->pfc_en)) 651 xgbe_enable_rx_flow_control(pdata); 652 else 653 xgbe_disable_rx_flow_control(pdata); 654 655 return 0; 656 } 657 658 static void xgbe_config_flow_control(struct xgbe_prv_data *pdata) 659 { 660 struct ieee_pfc *pfc = pdata->pfc; 661 662 xgbe_config_tx_flow_control(pdata); 663 xgbe_config_rx_flow_control(pdata); 664 665 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 666 (pfc && pfc->pfc_en) ? 1 : 0); 667 } 668 669 static void xgbe_enable_dma_interrupts(struct xgbe_prv_data *pdata) 670 { 671 struct xgbe_channel *channel; 672 unsigned int i, ver; 673 674 /* Set the interrupt mode if supported */ 675 if (pdata->channel_irq_mode) 676 XGMAC_IOWRITE_BITS(pdata, DMA_MR, INTM, 677 pdata->channel_irq_mode); 678 679 ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER); 680 681 for (i = 0; i < pdata->channel_count; i++) { 682 channel = pdata->channel[i]; 683 684 /* Clear all the interrupts which are set */ 685 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, 686 XGMAC_DMA_IOREAD(channel, DMA_CH_SR)); 687 688 /* Clear all interrupt enable bits */ 689 channel->curr_ier = 0; 690 691 /* Enable following interrupts 692 * NIE - Normal Interrupt Summary Enable 693 * AIE - Abnormal Interrupt Summary Enable 694 * FBEE - Fatal Bus Error Enable 695 */ 696 if (ver < 0x21) { 697 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, NIE20, 1); 698 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, AIE20, 1); 699 } else { 700 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, NIE, 1); 701 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, AIE, 1); 702 } 703 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, FBEE, 1); 704 705 if (channel->tx_ring) { 706 /* Enable the following Tx interrupts 707 * TIE - Transmit Interrupt Enable (unless using 708 * per channel interrupts in edge triggered 709 * mode) 710 */ 711 if (!pdata->per_channel_irq || pdata->channel_irq_mode) 712 XGMAC_SET_BITS(channel->curr_ier, 713 DMA_CH_IER, TIE, 1); 714 } 715 if (channel->rx_ring) { 716 /* Enable following Rx interrupts 717 * RBUE - Receive Buffer Unavailable Enable 718 * RIE - Receive Interrupt Enable (unless using 719 * per channel interrupts in edge triggered 720 * mode) 721 */ 722 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RBUE, 1); 723 if (!pdata->per_channel_irq || pdata->channel_irq_mode) 724 XGMAC_SET_BITS(channel->curr_ier, 725 DMA_CH_IER, RIE, 1); 726 } 727 728 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, channel->curr_ier); 729 } 730 } 731 732 static void xgbe_enable_mtl_interrupts(struct xgbe_prv_data *pdata) 733 { 734 unsigned int mtl_q_isr; 735 unsigned int q_count, i; 736 737 q_count = max(pdata->hw_feat.tx_q_cnt, pdata->hw_feat.rx_q_cnt); 738 for (i = 0; i < q_count; i++) { 739 /* Clear all the interrupts which are set */ 740 mtl_q_isr = XGMAC_MTL_IOREAD(pdata, i, MTL_Q_ISR); 741 XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_ISR, mtl_q_isr); 742 743 /* No MTL interrupts to be enabled */ 744 XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_IER, 0); 745 } 746 } 747 748 static void xgbe_enable_mac_interrupts(struct xgbe_prv_data *pdata) 749 { 750 unsigned int mac_ier = 0; 751 752 /* Enable Timestamp interrupt */ 753 XGMAC_SET_BITS(mac_ier, MAC_IER, TSIE, 1); 754 755 XGMAC_IOWRITE(pdata, MAC_IER, mac_ier); 756 757 /* Enable all counter interrupts */ 758 XGMAC_IOWRITE_BITS(pdata, MMC_RIER, ALL_INTERRUPTS, 0xffffffff); 759 XGMAC_IOWRITE_BITS(pdata, MMC_TIER, ALL_INTERRUPTS, 0xffffffff); 760 761 /* Enable MDIO single command completion interrupt */ 762 XGMAC_IOWRITE_BITS(pdata, MAC_MDIOIER, SNGLCOMPIE, 1); 763 } 764 765 static void xgbe_enable_ecc_interrupts(struct xgbe_prv_data *pdata) 766 { 767 unsigned int ecc_isr, ecc_ier = 0; 768 769 if (!pdata->vdata->ecc_support) 770 return; 771 772 /* Clear all the interrupts which are set */ 773 ecc_isr = XP_IOREAD(pdata, XP_ECC_ISR); 774 XP_IOWRITE(pdata, XP_ECC_ISR, ecc_isr); 775 776 /* Enable ECC interrupts */ 777 XP_SET_BITS(ecc_ier, XP_ECC_IER, TX_DED, 1); 778 XP_SET_BITS(ecc_ier, XP_ECC_IER, TX_SEC, 1); 779 XP_SET_BITS(ecc_ier, XP_ECC_IER, RX_DED, 1); 780 XP_SET_BITS(ecc_ier, XP_ECC_IER, RX_SEC, 1); 781 XP_SET_BITS(ecc_ier, XP_ECC_IER, DESC_DED, 1); 782 XP_SET_BITS(ecc_ier, XP_ECC_IER, DESC_SEC, 1); 783 784 XP_IOWRITE(pdata, XP_ECC_IER, ecc_ier); 785 } 786 787 static void xgbe_disable_ecc_ded(struct xgbe_prv_data *pdata) 788 { 789 unsigned int ecc_ier; 790 791 ecc_ier = XP_IOREAD(pdata, XP_ECC_IER); 792 793 /* Disable ECC DED interrupts */ 794 XP_SET_BITS(ecc_ier, XP_ECC_IER, TX_DED, 0); 795 XP_SET_BITS(ecc_ier, XP_ECC_IER, RX_DED, 0); 796 XP_SET_BITS(ecc_ier, XP_ECC_IER, DESC_DED, 0); 797 798 XP_IOWRITE(pdata, XP_ECC_IER, ecc_ier); 799 } 800 801 static void xgbe_disable_ecc_sec(struct xgbe_prv_data *pdata, 802 enum xgbe_ecc_sec sec) 803 { 804 unsigned int ecc_ier; 805 806 ecc_ier = XP_IOREAD(pdata, XP_ECC_IER); 807 808 /* Disable ECC SEC interrupt */ 809 switch (sec) { 810 case XGBE_ECC_SEC_TX: 811 XP_SET_BITS(ecc_ier, XP_ECC_IER, TX_SEC, 0); 812 break; 813 case XGBE_ECC_SEC_RX: 814 XP_SET_BITS(ecc_ier, XP_ECC_IER, RX_SEC, 0); 815 break; 816 case XGBE_ECC_SEC_DESC: 817 XP_SET_BITS(ecc_ier, XP_ECC_IER, DESC_SEC, 0); 818 break; 819 } 820 821 XP_IOWRITE(pdata, XP_ECC_IER, ecc_ier); 822 } 823 824 static int xgbe_set_speed(struct xgbe_prv_data *pdata, int speed) 825 { 826 unsigned int ss; 827 828 switch (speed) { 829 case SPEED_10: 830 ss = 0x07; 831 break; 832 case SPEED_1000: 833 ss = 0x03; 834 break; 835 case SPEED_2500: 836 ss = 0x02; 837 break; 838 case SPEED_10000: 839 ss = 0x00; 840 break; 841 default: 842 return -EINVAL; 843 } 844 845 if (XGMAC_IOREAD_BITS(pdata, MAC_TCR, SS) != ss) 846 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, ss); 847 848 return 0; 849 } 850 851 static int xgbe_enable_rx_vlan_stripping(struct xgbe_prv_data *pdata) 852 { 853 /* Put the VLAN tag in the Rx descriptor */ 854 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLRXS, 1); 855 856 /* Don't check the VLAN type */ 857 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, DOVLTC, 1); 858 859 /* Check only C-TAG (0x8100) packets */ 860 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ERSVLM, 0); 861 862 /* Don't consider an S-TAG (0x88A8) packet as a VLAN packet */ 863 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ESVL, 0); 864 865 /* Enable VLAN tag stripping */ 866 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0x3); 867 868 return 0; 869 } 870 871 static int xgbe_disable_rx_vlan_stripping(struct xgbe_prv_data *pdata) 872 { 873 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0); 874 875 return 0; 876 } 877 878 static int xgbe_enable_rx_vlan_filtering(struct xgbe_prv_data *pdata) 879 { 880 /* Enable VLAN filtering */ 881 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 1); 882 883 /* Enable VLAN Hash Table filtering */ 884 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTHM, 1); 885 886 /* Disable VLAN tag inverse matching */ 887 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTIM, 0); 888 889 /* Only filter on the lower 12-bits of the VLAN tag */ 890 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ETV, 1); 891 892 /* In order for the VLAN Hash Table filtering to be effective, 893 * the VLAN tag identifier in the VLAN Tag Register must not 894 * be zero. Set the VLAN tag identifier to "1" to enable the 895 * VLAN Hash Table filtering. This implies that a VLAN tag of 896 * 1 will always pass filtering. 897 */ 898 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VL, 1); 899 900 return 0; 901 } 902 903 static int xgbe_disable_rx_vlan_filtering(struct xgbe_prv_data *pdata) 904 { 905 /* Disable VLAN filtering */ 906 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 0); 907 908 return 0; 909 } 910 911 static u32 xgbe_vid_crc32_le(__le16 vid_le) 912 { 913 u32 crc = ~0; 914 u32 temp = 0; 915 unsigned char *data = (unsigned char *)&vid_le; 916 unsigned char data_byte = 0; 917 int i, bits; 918 919 bits = get_bitmask_order(VLAN_VID_MASK); 920 for (i = 0; i < bits; i++) { 921 if ((i % 8) == 0) 922 data_byte = data[i / 8]; 923 924 temp = ((crc & 1) ^ data_byte) & 1; 925 crc >>= 1; 926 data_byte >>= 1; 927 928 if (temp) 929 crc ^= CRC32_POLY_LE; 930 } 931 932 return crc; 933 } 934 935 static int xgbe_update_vlan_hash_table(struct xgbe_prv_data *pdata) 936 { 937 u32 crc; 938 u16 vid; 939 __le16 vid_le; 940 u16 vlan_hash_table = 0; 941 942 /* Generate the VLAN Hash Table value */ 943 for_each_set_bit(vid, pdata->active_vlans, VLAN_N_VID) { 944 /* Get the CRC32 value of the VLAN ID */ 945 vid_le = cpu_to_le16(vid); 946 crc = bitrev32(~xgbe_vid_crc32_le(vid_le)) >> 28; 947 948 vlan_hash_table |= (1 << crc); 949 } 950 951 /* Set the VLAN Hash Table filtering register */ 952 XGMAC_IOWRITE_BITS(pdata, MAC_VLANHTR, VLHT, vlan_hash_table); 953 954 return 0; 955 } 956 957 static int xgbe_set_promiscuous_mode(struct xgbe_prv_data *pdata, 958 unsigned int enable) 959 { 960 unsigned int val = enable ? 1 : 0; 961 962 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PR) == val) 963 return 0; 964 965 netif_dbg(pdata, drv, pdata->netdev, "%s promiscuous mode\n", 966 enable ? "entering" : "leaving"); 967 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, val); 968 969 /* Hardware will still perform VLAN filtering in promiscuous mode */ 970 if (enable) { 971 xgbe_disable_rx_vlan_filtering(pdata); 972 } else { 973 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER) 974 xgbe_enable_rx_vlan_filtering(pdata); 975 } 976 977 return 0; 978 } 979 980 static int xgbe_set_all_multicast_mode(struct xgbe_prv_data *pdata, 981 unsigned int enable) 982 { 983 unsigned int val = enable ? 1 : 0; 984 985 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PM) == val) 986 return 0; 987 988 netif_dbg(pdata, drv, pdata->netdev, "%s allmulti mode\n", 989 enable ? "entering" : "leaving"); 990 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, val); 991 992 return 0; 993 } 994 995 static void xgbe_set_mac_reg(struct xgbe_prv_data *pdata, 996 struct netdev_hw_addr *ha, unsigned int *mac_reg) 997 { 998 unsigned int mac_addr_hi, mac_addr_lo; 999 u8 *mac_addr; 1000 1001 mac_addr_lo = 0; 1002 mac_addr_hi = 0; 1003 1004 if (ha) { 1005 mac_addr = (u8 *)&mac_addr_lo; 1006 mac_addr[0] = ha->addr[0]; 1007 mac_addr[1] = ha->addr[1]; 1008 mac_addr[2] = ha->addr[2]; 1009 mac_addr[3] = ha->addr[3]; 1010 mac_addr = (u8 *)&mac_addr_hi; 1011 mac_addr[0] = ha->addr[4]; 1012 mac_addr[1] = ha->addr[5]; 1013 1014 netif_dbg(pdata, drv, pdata->netdev, 1015 "adding mac address %pM at %#x\n", 1016 ha->addr, *mac_reg); 1017 1018 XGMAC_SET_BITS(mac_addr_hi, MAC_MACA1HR, AE, 1); 1019 } 1020 1021 XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_hi); 1022 *mac_reg += MAC_MACA_INC; 1023 XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_lo); 1024 *mac_reg += MAC_MACA_INC; 1025 } 1026 1027 static void xgbe_set_mac_addn_addrs(struct xgbe_prv_data *pdata) 1028 { 1029 struct net_device *netdev = pdata->netdev; 1030 struct netdev_hw_addr *ha; 1031 unsigned int mac_reg; 1032 unsigned int addn_macs; 1033 1034 mac_reg = MAC_MACA1HR; 1035 addn_macs = pdata->hw_feat.addn_mac; 1036 1037 if (netdev_uc_count(netdev) > addn_macs) { 1038 xgbe_set_promiscuous_mode(pdata, 1); 1039 } else { 1040 netdev_for_each_uc_addr(ha, netdev) { 1041 xgbe_set_mac_reg(pdata, ha, &mac_reg); 1042 addn_macs--; 1043 } 1044 1045 if (netdev_mc_count(netdev) > addn_macs) { 1046 xgbe_set_all_multicast_mode(pdata, 1); 1047 } else { 1048 netdev_for_each_mc_addr(ha, netdev) { 1049 xgbe_set_mac_reg(pdata, ha, &mac_reg); 1050 addn_macs--; 1051 } 1052 } 1053 } 1054 1055 /* Clear remaining additional MAC address entries */ 1056 while (addn_macs--) 1057 xgbe_set_mac_reg(pdata, NULL, &mac_reg); 1058 } 1059 1060 static void xgbe_set_mac_hash_table(struct xgbe_prv_data *pdata) 1061 { 1062 struct net_device *netdev = pdata->netdev; 1063 struct netdev_hw_addr *ha; 1064 unsigned int hash_reg; 1065 unsigned int hash_table_shift, hash_table_count; 1066 u32 hash_table[XGBE_MAC_HASH_TABLE_SIZE]; 1067 u32 crc; 1068 unsigned int i; 1069 1070 hash_table_shift = 26 - (pdata->hw_feat.hash_table_size >> 7); 1071 hash_table_count = pdata->hw_feat.hash_table_size / 32; 1072 memset(hash_table, 0, sizeof(hash_table)); 1073 1074 /* Build the MAC Hash Table register values */ 1075 netdev_for_each_uc_addr(ha, netdev) { 1076 crc = bitrev32(~crc32_le(~0, ha->addr, ETH_ALEN)); 1077 crc >>= hash_table_shift; 1078 hash_table[crc >> 5] |= (1 << (crc & 0x1f)); 1079 } 1080 1081 netdev_for_each_mc_addr(ha, netdev) { 1082 crc = bitrev32(~crc32_le(~0, ha->addr, ETH_ALEN)); 1083 crc >>= hash_table_shift; 1084 hash_table[crc >> 5] |= (1 << (crc & 0x1f)); 1085 } 1086 1087 /* Set the MAC Hash Table registers */ 1088 hash_reg = MAC_HTR0; 1089 for (i = 0; i < hash_table_count; i++) { 1090 XGMAC_IOWRITE(pdata, hash_reg, hash_table[i]); 1091 hash_reg += MAC_HTR_INC; 1092 } 1093 } 1094 1095 static int xgbe_add_mac_addresses(struct xgbe_prv_data *pdata) 1096 { 1097 if (pdata->hw_feat.hash_table_size) 1098 xgbe_set_mac_hash_table(pdata); 1099 else 1100 xgbe_set_mac_addn_addrs(pdata); 1101 1102 return 0; 1103 } 1104 1105 static int xgbe_set_mac_address(struct xgbe_prv_data *pdata, const u8 *addr) 1106 { 1107 unsigned int mac_addr_hi, mac_addr_lo; 1108 1109 mac_addr_hi = (addr[5] << 8) | (addr[4] << 0); 1110 mac_addr_lo = (addr[3] << 24) | (addr[2] << 16) | 1111 (addr[1] << 8) | (addr[0] << 0); 1112 1113 XGMAC_IOWRITE(pdata, MAC_MACA0HR, mac_addr_hi); 1114 XGMAC_IOWRITE(pdata, MAC_MACA0LR, mac_addr_lo); 1115 1116 return 0; 1117 } 1118 1119 static int xgbe_config_rx_mode(struct xgbe_prv_data *pdata) 1120 { 1121 struct net_device *netdev = pdata->netdev; 1122 unsigned int pr_mode, am_mode; 1123 1124 pr_mode = ((netdev->flags & IFF_PROMISC) != 0); 1125 am_mode = ((netdev->flags & IFF_ALLMULTI) != 0); 1126 1127 xgbe_set_promiscuous_mode(pdata, pr_mode); 1128 xgbe_set_all_multicast_mode(pdata, am_mode); 1129 1130 xgbe_add_mac_addresses(pdata); 1131 1132 return 0; 1133 } 1134 1135 static int xgbe_clr_gpio(struct xgbe_prv_data *pdata, unsigned int gpio) 1136 { 1137 unsigned int reg; 1138 1139 if (gpio > 15) 1140 return -EINVAL; 1141 1142 reg = XGMAC_IOREAD(pdata, MAC_GPIOSR); 1143 1144 reg &= ~(1 << (gpio + 16)); 1145 XGMAC_IOWRITE(pdata, MAC_GPIOSR, reg); 1146 1147 return 0; 1148 } 1149 1150 static int xgbe_set_gpio(struct xgbe_prv_data *pdata, unsigned int gpio) 1151 { 1152 unsigned int reg; 1153 1154 if (gpio > 15) 1155 return -EINVAL; 1156 1157 reg = XGMAC_IOREAD(pdata, MAC_GPIOSR); 1158 1159 reg |= (1 << (gpio + 16)); 1160 XGMAC_IOWRITE(pdata, MAC_GPIOSR, reg); 1161 1162 return 0; 1163 } 1164 1165 static int xgbe_read_mmd_regs_v2(struct xgbe_prv_data *pdata, int prtad, 1166 int mmd_reg) 1167 { 1168 unsigned long flags; 1169 unsigned int mmd_address, index, offset; 1170 int mmd_data; 1171 1172 if (mmd_reg & XGBE_ADDR_C45) 1173 mmd_address = mmd_reg & ~XGBE_ADDR_C45; 1174 else 1175 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); 1176 1177 /* The PCS registers are accessed using mmio. The underlying 1178 * management interface uses indirect addressing to access the MMD 1179 * register sets. This requires accessing of the PCS register in two 1180 * phases, an address phase and a data phase. 1181 * 1182 * The mmio interface is based on 16-bit offsets and values. All 1183 * register offsets must therefore be adjusted by left shifting the 1184 * offset 1 bit and reading 16 bits of data. 1185 */ 1186 mmd_address <<= 1; 1187 index = mmd_address & ~pdata->xpcs_window_mask; 1188 offset = pdata->xpcs_window + (mmd_address & pdata->xpcs_window_mask); 1189 1190 spin_lock_irqsave(&pdata->xpcs_lock, flags); 1191 XPCS32_IOWRITE(pdata, pdata->xpcs_window_sel_reg, index); 1192 mmd_data = XPCS16_IOREAD(pdata, offset); 1193 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); 1194 1195 return mmd_data; 1196 } 1197 1198 static void xgbe_write_mmd_regs_v2(struct xgbe_prv_data *pdata, int prtad, 1199 int mmd_reg, int mmd_data) 1200 { 1201 unsigned long flags; 1202 unsigned int mmd_address, index, offset; 1203 1204 if (mmd_reg & XGBE_ADDR_C45) 1205 mmd_address = mmd_reg & ~XGBE_ADDR_C45; 1206 else 1207 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); 1208 1209 /* The PCS registers are accessed using mmio. The underlying 1210 * management interface uses indirect addressing to access the MMD 1211 * register sets. This requires accessing of the PCS register in two 1212 * phases, an address phase and a data phase. 1213 * 1214 * The mmio interface is based on 16-bit offsets and values. All 1215 * register offsets must therefore be adjusted by left shifting the 1216 * offset 1 bit and writing 16 bits of data. 1217 */ 1218 mmd_address <<= 1; 1219 index = mmd_address & ~pdata->xpcs_window_mask; 1220 offset = pdata->xpcs_window + (mmd_address & pdata->xpcs_window_mask); 1221 1222 spin_lock_irqsave(&pdata->xpcs_lock, flags); 1223 XPCS32_IOWRITE(pdata, pdata->xpcs_window_sel_reg, index); 1224 XPCS16_IOWRITE(pdata, offset, mmd_data); 1225 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); 1226 } 1227 1228 static int xgbe_read_mmd_regs_v1(struct xgbe_prv_data *pdata, int prtad, 1229 int mmd_reg) 1230 { 1231 unsigned long flags; 1232 unsigned int mmd_address; 1233 int mmd_data; 1234 1235 if (mmd_reg & XGBE_ADDR_C45) 1236 mmd_address = mmd_reg & ~XGBE_ADDR_C45; 1237 else 1238 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); 1239 1240 /* The PCS registers are accessed using mmio. The underlying APB3 1241 * management interface uses indirect addressing to access the MMD 1242 * register sets. This requires accessing of the PCS register in two 1243 * phases, an address phase and a data phase. 1244 * 1245 * The mmio interface is based on 32-bit offsets and values. All 1246 * register offsets must therefore be adjusted by left shifting the 1247 * offset 2 bits and reading 32 bits of data. 1248 */ 1249 spin_lock_irqsave(&pdata->xpcs_lock, flags); 1250 XPCS32_IOWRITE(pdata, PCS_V1_WINDOW_SELECT, mmd_address >> 8); 1251 mmd_data = XPCS32_IOREAD(pdata, (mmd_address & 0xff) << 2); 1252 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); 1253 1254 return mmd_data; 1255 } 1256 1257 static void xgbe_write_mmd_regs_v1(struct xgbe_prv_data *pdata, int prtad, 1258 int mmd_reg, int mmd_data) 1259 { 1260 unsigned int mmd_address; 1261 unsigned long flags; 1262 1263 if (mmd_reg & XGBE_ADDR_C45) 1264 mmd_address = mmd_reg & ~XGBE_ADDR_C45; 1265 else 1266 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); 1267 1268 /* The PCS registers are accessed using mmio. The underlying APB3 1269 * management interface uses indirect addressing to access the MMD 1270 * register sets. This requires accessing of the PCS register in two 1271 * phases, an address phase and a data phase. 1272 * 1273 * The mmio interface is based on 32-bit offsets and values. All 1274 * register offsets must therefore be adjusted by left shifting the 1275 * offset 2 bits and writing 32 bits of data. 1276 */ 1277 spin_lock_irqsave(&pdata->xpcs_lock, flags); 1278 XPCS32_IOWRITE(pdata, PCS_V1_WINDOW_SELECT, mmd_address >> 8); 1279 XPCS32_IOWRITE(pdata, (mmd_address & 0xff) << 2, mmd_data); 1280 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); 1281 } 1282 1283 static int xgbe_read_mmd_regs(struct xgbe_prv_data *pdata, int prtad, 1284 int mmd_reg) 1285 { 1286 switch (pdata->vdata->xpcs_access) { 1287 case XGBE_XPCS_ACCESS_V1: 1288 return xgbe_read_mmd_regs_v1(pdata, prtad, mmd_reg); 1289 1290 case XGBE_XPCS_ACCESS_V2: 1291 default: 1292 return xgbe_read_mmd_regs_v2(pdata, prtad, mmd_reg); 1293 } 1294 } 1295 1296 static void xgbe_write_mmd_regs(struct xgbe_prv_data *pdata, int prtad, 1297 int mmd_reg, int mmd_data) 1298 { 1299 switch (pdata->vdata->xpcs_access) { 1300 case XGBE_XPCS_ACCESS_V1: 1301 return xgbe_write_mmd_regs_v1(pdata, prtad, mmd_reg, mmd_data); 1302 1303 case XGBE_XPCS_ACCESS_V2: 1304 default: 1305 return xgbe_write_mmd_regs_v2(pdata, prtad, mmd_reg, mmd_data); 1306 } 1307 } 1308 1309 static unsigned int xgbe_create_mdio_sca_c22(int port, int reg) 1310 { 1311 unsigned int mdio_sca; 1312 1313 mdio_sca = 0; 1314 XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, RA, reg); 1315 XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, PA, port); 1316 1317 return mdio_sca; 1318 } 1319 1320 static unsigned int xgbe_create_mdio_sca_c45(int port, unsigned int da, int reg) 1321 { 1322 unsigned int mdio_sca; 1323 1324 mdio_sca = 0; 1325 XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, RA, reg); 1326 XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, PA, port); 1327 XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, DA, da); 1328 1329 return mdio_sca; 1330 } 1331 1332 static int xgbe_write_ext_mii_regs(struct xgbe_prv_data *pdata, 1333 unsigned int mdio_sca, u16 val) 1334 { 1335 unsigned int mdio_sccd; 1336 1337 reinit_completion(&pdata->mdio_complete); 1338 1339 XGMAC_IOWRITE(pdata, MAC_MDIOSCAR, mdio_sca); 1340 1341 mdio_sccd = 0; 1342 XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, DATA, val); 1343 XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, CMD, 1); 1344 XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, BUSY, 1); 1345 XGMAC_IOWRITE(pdata, MAC_MDIOSCCDR, mdio_sccd); 1346 1347 if (!wait_for_completion_timeout(&pdata->mdio_complete, HZ)) { 1348 netdev_err(pdata->netdev, "mdio write operation timed out\n"); 1349 return -ETIMEDOUT; 1350 } 1351 1352 return 0; 1353 } 1354 1355 static int xgbe_write_ext_mii_regs_c22(struct xgbe_prv_data *pdata, int addr, 1356 int reg, u16 val) 1357 { 1358 unsigned int mdio_sca; 1359 1360 mdio_sca = xgbe_create_mdio_sca_c22(addr, reg); 1361 1362 return xgbe_write_ext_mii_regs(pdata, mdio_sca, val); 1363 } 1364 1365 static int xgbe_write_ext_mii_regs_c45(struct xgbe_prv_data *pdata, int addr, 1366 int devad, int reg, u16 val) 1367 { 1368 unsigned int mdio_sca; 1369 1370 mdio_sca = xgbe_create_mdio_sca_c45(addr, devad, reg); 1371 1372 return xgbe_write_ext_mii_regs(pdata, mdio_sca, val); 1373 } 1374 1375 static int xgbe_read_ext_mii_regs(struct xgbe_prv_data *pdata, 1376 unsigned int mdio_sca) 1377 { 1378 unsigned int mdio_sccd; 1379 1380 reinit_completion(&pdata->mdio_complete); 1381 1382 XGMAC_IOWRITE(pdata, MAC_MDIOSCAR, mdio_sca); 1383 1384 mdio_sccd = 0; 1385 XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, CMD, 3); 1386 XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, BUSY, 1); 1387 XGMAC_IOWRITE(pdata, MAC_MDIOSCCDR, mdio_sccd); 1388 1389 if (!wait_for_completion_timeout(&pdata->mdio_complete, HZ)) { 1390 netdev_err(pdata->netdev, "mdio read operation timed out\n"); 1391 return -ETIMEDOUT; 1392 } 1393 1394 return XGMAC_IOREAD_BITS(pdata, MAC_MDIOSCCDR, DATA); 1395 } 1396 1397 static int xgbe_read_ext_mii_regs_c22(struct xgbe_prv_data *pdata, int addr, 1398 int reg) 1399 { 1400 unsigned int mdio_sca; 1401 1402 mdio_sca = xgbe_create_mdio_sca_c22(addr, reg); 1403 1404 return xgbe_read_ext_mii_regs(pdata, mdio_sca); 1405 } 1406 1407 static int xgbe_read_ext_mii_regs_c45(struct xgbe_prv_data *pdata, int addr, 1408 int devad, int reg) 1409 { 1410 unsigned int mdio_sca; 1411 1412 mdio_sca = xgbe_create_mdio_sca_c45(addr, devad, reg); 1413 1414 return xgbe_read_ext_mii_regs(pdata, mdio_sca); 1415 } 1416 1417 static int xgbe_set_ext_mii_mode(struct xgbe_prv_data *pdata, unsigned int port, 1418 enum xgbe_mdio_mode mode) 1419 { 1420 unsigned int reg_val = XGMAC_IOREAD(pdata, MAC_MDIOCL22R); 1421 1422 switch (mode) { 1423 case XGBE_MDIO_MODE_CL22: 1424 if (port > XGMAC_MAX_C22_PORT) 1425 return -EINVAL; 1426 reg_val |= (1 << port); 1427 break; 1428 case XGBE_MDIO_MODE_CL45: 1429 break; 1430 default: 1431 return -EINVAL; 1432 } 1433 1434 XGMAC_IOWRITE(pdata, MAC_MDIOCL22R, reg_val); 1435 1436 return 0; 1437 } 1438 1439 static int xgbe_tx_complete(struct xgbe_ring_desc *rdesc) 1440 { 1441 return !XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN); 1442 } 1443 1444 static int xgbe_disable_rx_csum(struct xgbe_prv_data *pdata) 1445 { 1446 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 0); 1447 1448 return 0; 1449 } 1450 1451 static int xgbe_enable_rx_csum(struct xgbe_prv_data *pdata) 1452 { 1453 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 1); 1454 1455 return 0; 1456 } 1457 1458 static void xgbe_tx_desc_reset(struct xgbe_ring_data *rdata) 1459 { 1460 struct xgbe_ring_desc *rdesc = rdata->rdesc; 1461 1462 /* Reset the Tx descriptor 1463 * Set buffer 1 (lo) address to zero 1464 * Set buffer 1 (hi) address to zero 1465 * Reset all other control bits (IC, TTSE, B2L & B1L) 1466 * Reset all other control bits (OWN, CTXT, FD, LD, CPC, CIC, etc) 1467 */ 1468 rdesc->desc0 = 0; 1469 rdesc->desc1 = 0; 1470 rdesc->desc2 = 0; 1471 rdesc->desc3 = 0; 1472 1473 /* Make sure ownership is written to the descriptor */ 1474 dma_wmb(); 1475 } 1476 1477 static void xgbe_tx_desc_init(struct xgbe_channel *channel) 1478 { 1479 struct xgbe_ring *ring = channel->tx_ring; 1480 struct xgbe_ring_data *rdata; 1481 int i; 1482 int start_index = ring->cur; 1483 1484 DBGPR("-->tx_desc_init\n"); 1485 1486 /* Initialze all descriptors */ 1487 for (i = 0; i < ring->rdesc_count; i++) { 1488 rdata = XGBE_GET_DESC_DATA(ring, i); 1489 1490 /* Initialize Tx descriptor */ 1491 xgbe_tx_desc_reset(rdata); 1492 } 1493 1494 /* Update the total number of Tx descriptors */ 1495 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDRLR, ring->rdesc_count - 1); 1496 1497 /* Update the starting address of descriptor ring */ 1498 rdata = XGBE_GET_DESC_DATA(ring, start_index); 1499 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_HI, 1500 upper_32_bits(rdata->rdesc_dma)); 1501 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_LO, 1502 lower_32_bits(rdata->rdesc_dma)); 1503 1504 DBGPR("<--tx_desc_init\n"); 1505 } 1506 1507 static void xgbe_rx_desc_reset(struct xgbe_prv_data *pdata, 1508 struct xgbe_ring_data *rdata, unsigned int index) 1509 { 1510 struct xgbe_ring_desc *rdesc = rdata->rdesc; 1511 unsigned int rx_usecs = pdata->rx_usecs; 1512 unsigned int rx_frames = pdata->rx_frames; 1513 unsigned int inte; 1514 dma_addr_t hdr_dma, buf_dma; 1515 1516 if (!rx_usecs && !rx_frames) { 1517 /* No coalescing, interrupt for every descriptor */ 1518 inte = 1; 1519 } else { 1520 /* Set interrupt based on Rx frame coalescing setting */ 1521 if (rx_frames && !((index + 1) % rx_frames)) 1522 inte = 1; 1523 else 1524 inte = 0; 1525 } 1526 1527 /* Reset the Rx descriptor 1528 * Set buffer 1 (lo) address to header dma address (lo) 1529 * Set buffer 1 (hi) address to header dma address (hi) 1530 * Set buffer 2 (lo) address to buffer dma address (lo) 1531 * Set buffer 2 (hi) address to buffer dma address (hi) and 1532 * set control bits OWN and INTE 1533 */ 1534 hdr_dma = rdata->rx.hdr.dma_base + rdata->rx.hdr.dma_off; 1535 buf_dma = rdata->rx.buf.dma_base + rdata->rx.buf.dma_off; 1536 rdesc->desc0 = cpu_to_le32(lower_32_bits(hdr_dma)); 1537 rdesc->desc1 = cpu_to_le32(upper_32_bits(hdr_dma)); 1538 rdesc->desc2 = cpu_to_le32(lower_32_bits(buf_dma)); 1539 rdesc->desc3 = cpu_to_le32(upper_32_bits(buf_dma)); 1540 1541 XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, INTE, inte); 1542 1543 /* Since the Rx DMA engine is likely running, make sure everything 1544 * is written to the descriptor(s) before setting the OWN bit 1545 * for the descriptor 1546 */ 1547 dma_wmb(); 1548 1549 XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN, 1); 1550 1551 /* Make sure ownership is written to the descriptor */ 1552 dma_wmb(); 1553 } 1554 1555 static void xgbe_rx_desc_init(struct xgbe_channel *channel) 1556 { 1557 struct xgbe_prv_data *pdata = channel->pdata; 1558 struct xgbe_ring *ring = channel->rx_ring; 1559 struct xgbe_ring_data *rdata; 1560 unsigned int start_index = ring->cur; 1561 unsigned int i; 1562 1563 DBGPR("-->rx_desc_init\n"); 1564 1565 /* Initialize all descriptors */ 1566 for (i = 0; i < ring->rdesc_count; i++) { 1567 rdata = XGBE_GET_DESC_DATA(ring, i); 1568 1569 /* Initialize Rx descriptor */ 1570 xgbe_rx_desc_reset(pdata, rdata, i); 1571 } 1572 1573 /* Update the total number of Rx descriptors */ 1574 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDRLR, ring->rdesc_count - 1); 1575 1576 /* Update the starting address of descriptor ring */ 1577 rdata = XGBE_GET_DESC_DATA(ring, start_index); 1578 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_HI, 1579 upper_32_bits(rdata->rdesc_dma)); 1580 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_LO, 1581 lower_32_bits(rdata->rdesc_dma)); 1582 1583 /* Update the Rx Descriptor Tail Pointer */ 1584 rdata = XGBE_GET_DESC_DATA(ring, start_index + ring->rdesc_count - 1); 1585 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO, 1586 lower_32_bits(rdata->rdesc_dma)); 1587 1588 DBGPR("<--rx_desc_init\n"); 1589 } 1590 1591 static void xgbe_update_tstamp_addend(struct xgbe_prv_data *pdata, 1592 unsigned int addend) 1593 { 1594 unsigned int count = 10000; 1595 1596 /* Set the addend register value and tell the device */ 1597 XGMAC_IOWRITE(pdata, MAC_TSAR, addend); 1598 XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 1); 1599 1600 /* Wait for addend update to complete */ 1601 while (--count && XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSADDREG)) 1602 udelay(5); 1603 1604 if (!count) 1605 netdev_err(pdata->netdev, 1606 "timed out updating timestamp addend register\n"); 1607 } 1608 1609 static void xgbe_set_tstamp_time(struct xgbe_prv_data *pdata, unsigned int sec, 1610 unsigned int nsec) 1611 { 1612 unsigned int count = 10000; 1613 1614 /* Set the time values and tell the device */ 1615 XGMAC_IOWRITE(pdata, MAC_STSUR, sec); 1616 XGMAC_IOWRITE(pdata, MAC_STNUR, nsec); 1617 XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSINIT, 1); 1618 1619 /* Wait for time update to complete */ 1620 while (--count && XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSINIT)) 1621 udelay(5); 1622 1623 if (!count) 1624 netdev_err(pdata->netdev, "timed out initializing timestamp\n"); 1625 } 1626 1627 static u64 xgbe_get_tstamp_time(struct xgbe_prv_data *pdata) 1628 { 1629 u64 nsec; 1630 1631 nsec = XGMAC_IOREAD(pdata, MAC_STSR); 1632 nsec *= NSEC_PER_SEC; 1633 nsec += XGMAC_IOREAD(pdata, MAC_STNR); 1634 1635 return nsec; 1636 } 1637 1638 static u64 xgbe_get_tx_tstamp(struct xgbe_prv_data *pdata) 1639 { 1640 unsigned int tx_snr, tx_ssr; 1641 u64 nsec; 1642 1643 if (pdata->vdata->tx_tstamp_workaround) { 1644 tx_snr = XGMAC_IOREAD(pdata, MAC_TXSNR); 1645 tx_ssr = XGMAC_IOREAD(pdata, MAC_TXSSR); 1646 } else { 1647 tx_ssr = XGMAC_IOREAD(pdata, MAC_TXSSR); 1648 tx_snr = XGMAC_IOREAD(pdata, MAC_TXSNR); 1649 } 1650 1651 if (XGMAC_GET_BITS(tx_snr, MAC_TXSNR, TXTSSTSMIS)) 1652 return 0; 1653 1654 nsec = tx_ssr; 1655 nsec *= NSEC_PER_SEC; 1656 nsec += tx_snr; 1657 1658 return nsec; 1659 } 1660 1661 static void xgbe_get_rx_tstamp(struct xgbe_packet_data *packet, 1662 struct xgbe_ring_desc *rdesc) 1663 { 1664 u64 nsec; 1665 1666 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_CONTEXT_DESC3, TSA) && 1667 !XGMAC_GET_BITS_LE(rdesc->desc3, RX_CONTEXT_DESC3, TSD)) { 1668 nsec = le32_to_cpu(rdesc->desc1); 1669 nsec <<= 32; 1670 nsec |= le32_to_cpu(rdesc->desc0); 1671 if (nsec != 0xffffffffffffffffULL) { 1672 packet->rx_tstamp = nsec; 1673 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1674 RX_TSTAMP, 1); 1675 } 1676 } 1677 } 1678 1679 static int xgbe_config_tstamp(struct xgbe_prv_data *pdata, 1680 unsigned int mac_tscr) 1681 { 1682 /* Set one nano-second accuracy */ 1683 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCTRLSSR, 1); 1684 1685 /* Set fine timestamp update */ 1686 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 1); 1687 1688 /* Overwrite earlier timestamps */ 1689 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TXTSSTSM, 1); 1690 1691 XGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr); 1692 1693 /* Exit if timestamping is not enabled */ 1694 if (!XGMAC_GET_BITS(mac_tscr, MAC_TSCR, TSENA)) 1695 return 0; 1696 1697 /* Initialize time registers */ 1698 XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SSINC, XGBE_TSTAMP_SSINC); 1699 XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SNSINC, XGBE_TSTAMP_SNSINC); 1700 xgbe_update_tstamp_addend(pdata, pdata->tstamp_addend); 1701 xgbe_set_tstamp_time(pdata, 0, 0); 1702 1703 /* Initialize the timecounter */ 1704 timecounter_init(&pdata->tstamp_tc, &pdata->tstamp_cc, 1705 ktime_to_ns(ktime_get_real())); 1706 1707 return 0; 1708 } 1709 1710 static void xgbe_tx_start_xmit(struct xgbe_channel *channel, 1711 struct xgbe_ring *ring) 1712 { 1713 struct xgbe_prv_data *pdata = channel->pdata; 1714 struct xgbe_ring_data *rdata; 1715 1716 /* Make sure everything is written before the register write */ 1717 wmb(); 1718 1719 /* Issue a poll command to Tx DMA by writing address 1720 * of next immediate free descriptor */ 1721 rdata = XGBE_GET_DESC_DATA(ring, ring->cur); 1722 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDTR_LO, 1723 lower_32_bits(rdata->rdesc_dma)); 1724 1725 /* Start the Tx timer */ 1726 if (pdata->tx_usecs && !channel->tx_timer_active) { 1727 channel->tx_timer_active = 1; 1728 mod_timer(&channel->tx_timer, 1729 jiffies + usecs_to_jiffies(pdata->tx_usecs)); 1730 } 1731 1732 ring->tx.xmit_more = 0; 1733 } 1734 1735 static void xgbe_dev_xmit(struct xgbe_channel *channel) 1736 { 1737 struct xgbe_prv_data *pdata = channel->pdata; 1738 struct xgbe_ring *ring = channel->tx_ring; 1739 struct xgbe_ring_data *rdata; 1740 struct xgbe_ring_desc *rdesc; 1741 struct xgbe_packet_data *packet = &ring->packet_data; 1742 unsigned int tx_packets, tx_bytes; 1743 unsigned int csum, tso, vlan, vxlan; 1744 unsigned int tso_context, vlan_context; 1745 unsigned int tx_set_ic; 1746 int start_index = ring->cur; 1747 int cur_index = ring->cur; 1748 int i; 1749 1750 DBGPR("-->xgbe_dev_xmit\n"); 1751 1752 tx_packets = packet->tx_packets; 1753 tx_bytes = packet->tx_bytes; 1754 1755 csum = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, 1756 CSUM_ENABLE); 1757 tso = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, 1758 TSO_ENABLE); 1759 vlan = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, 1760 VLAN_CTAG); 1761 vxlan = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, 1762 VXLAN); 1763 1764 if (tso && (packet->mss != ring->tx.cur_mss)) 1765 tso_context = 1; 1766 else 1767 tso_context = 0; 1768 1769 if (vlan && (packet->vlan_ctag != ring->tx.cur_vlan_ctag)) 1770 vlan_context = 1; 1771 else 1772 vlan_context = 0; 1773 1774 /* Determine if an interrupt should be generated for this Tx: 1775 * Interrupt: 1776 * - Tx frame count exceeds the frame count setting 1777 * - Addition of Tx frame count to the frame count since the 1778 * last interrupt was set exceeds the frame count setting 1779 * No interrupt: 1780 * - No frame count setting specified (ethtool -C ethX tx-frames 0) 1781 * - Addition of Tx frame count to the frame count since the 1782 * last interrupt was set does not exceed the frame count setting 1783 */ 1784 ring->coalesce_count += tx_packets; 1785 if (!pdata->tx_frames) 1786 tx_set_ic = 0; 1787 else if (tx_packets > pdata->tx_frames) 1788 tx_set_ic = 1; 1789 else if ((ring->coalesce_count % pdata->tx_frames) < tx_packets) 1790 tx_set_ic = 1; 1791 else 1792 tx_set_ic = 0; 1793 1794 rdata = XGBE_GET_DESC_DATA(ring, cur_index); 1795 rdesc = rdata->rdesc; 1796 1797 /* Create a context descriptor if this is a TSO packet */ 1798 if (tso_context || vlan_context) { 1799 if (tso_context) { 1800 netif_dbg(pdata, tx_queued, pdata->netdev, 1801 "TSO context descriptor, mss=%u\n", 1802 packet->mss); 1803 1804 /* Set the MSS size */ 1805 XGMAC_SET_BITS_LE(rdesc->desc2, TX_CONTEXT_DESC2, 1806 MSS, packet->mss); 1807 1808 /* Mark it as a CONTEXT descriptor */ 1809 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, 1810 CTXT, 1); 1811 1812 /* Indicate this descriptor contains the MSS */ 1813 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, 1814 TCMSSV, 1); 1815 1816 ring->tx.cur_mss = packet->mss; 1817 } 1818 1819 if (vlan_context) { 1820 netif_dbg(pdata, tx_queued, pdata->netdev, 1821 "VLAN context descriptor, ctag=%u\n", 1822 packet->vlan_ctag); 1823 1824 /* Mark it as a CONTEXT descriptor */ 1825 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, 1826 CTXT, 1); 1827 1828 /* Set the VLAN tag */ 1829 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, 1830 VT, packet->vlan_ctag); 1831 1832 /* Indicate this descriptor contains the VLAN tag */ 1833 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, 1834 VLTV, 1); 1835 1836 ring->tx.cur_vlan_ctag = packet->vlan_ctag; 1837 } 1838 1839 cur_index++; 1840 rdata = XGBE_GET_DESC_DATA(ring, cur_index); 1841 rdesc = rdata->rdesc; 1842 } 1843 1844 /* Update buffer address (for TSO this is the header) */ 1845 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma)); 1846 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma)); 1847 1848 /* Update the buffer length */ 1849 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, HL_B1L, 1850 rdata->skb_dma_len); 1851 1852 /* VLAN tag insertion check */ 1853 if (vlan) 1854 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, VTIR, 1855 TX_NORMAL_DESC2_VLAN_INSERT); 1856 1857 /* Timestamp enablement check */ 1858 if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP)) 1859 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, TTSE, 1); 1860 1861 /* Mark it as First Descriptor */ 1862 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FD, 1); 1863 1864 /* Mark it as a NORMAL descriptor */ 1865 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT, 0); 1866 1867 /* Set OWN bit if not the first descriptor */ 1868 if (cur_index != start_index) 1869 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1); 1870 1871 if (tso) { 1872 /* Enable TSO */ 1873 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TSE, 1); 1874 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TCPPL, 1875 packet->tcp_payload_len); 1876 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TCPHDRLEN, 1877 packet->tcp_header_len / 4); 1878 1879 pdata->ext_stats.tx_tso_packets += tx_packets; 1880 } else { 1881 /* Enable CRC and Pad Insertion */ 1882 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CPC, 0); 1883 1884 /* Enable HW CSUM */ 1885 if (csum) 1886 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, 1887 CIC, 0x3); 1888 1889 /* Set the total length to be transmitted */ 1890 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FL, 1891 packet->length); 1892 } 1893 1894 if (vxlan) { 1895 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, VNP, 1896 TX_NORMAL_DESC3_VXLAN_PACKET); 1897 1898 pdata->ext_stats.tx_vxlan_packets += packet->tx_packets; 1899 } 1900 1901 for (i = cur_index - start_index + 1; i < packet->rdesc_count; i++) { 1902 cur_index++; 1903 rdata = XGBE_GET_DESC_DATA(ring, cur_index); 1904 rdesc = rdata->rdesc; 1905 1906 /* Update buffer address */ 1907 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma)); 1908 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma)); 1909 1910 /* Update the buffer length */ 1911 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, HL_B1L, 1912 rdata->skb_dma_len); 1913 1914 /* Set OWN bit */ 1915 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1); 1916 1917 /* Mark it as NORMAL descriptor */ 1918 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT, 0); 1919 1920 /* Enable HW CSUM */ 1921 if (csum) 1922 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, 1923 CIC, 0x3); 1924 } 1925 1926 /* Set LAST bit for the last descriptor */ 1927 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD, 1); 1928 1929 /* Set IC bit based on Tx coalescing settings */ 1930 if (tx_set_ic) 1931 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, IC, 1); 1932 1933 /* Save the Tx info to report back during cleanup */ 1934 rdata->tx.packets = tx_packets; 1935 rdata->tx.bytes = tx_bytes; 1936 1937 pdata->ext_stats.txq_packets[channel->queue_index] += tx_packets; 1938 pdata->ext_stats.txq_bytes[channel->queue_index] += tx_bytes; 1939 1940 /* In case the Tx DMA engine is running, make sure everything 1941 * is written to the descriptor(s) before setting the OWN bit 1942 * for the first descriptor 1943 */ 1944 dma_wmb(); 1945 1946 /* Set OWN bit for the first descriptor */ 1947 rdata = XGBE_GET_DESC_DATA(ring, start_index); 1948 rdesc = rdata->rdesc; 1949 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1); 1950 1951 if (netif_msg_tx_queued(pdata)) 1952 xgbe_dump_tx_desc(pdata, ring, start_index, 1953 packet->rdesc_count, 1); 1954 1955 /* Make sure ownership is written to the descriptor */ 1956 smp_wmb(); 1957 1958 ring->cur = cur_index + 1; 1959 if (!netdev_xmit_more() || 1960 netif_xmit_stopped(netdev_get_tx_queue(pdata->netdev, 1961 channel->queue_index))) 1962 xgbe_tx_start_xmit(channel, ring); 1963 else 1964 ring->tx.xmit_more = 1; 1965 1966 DBGPR(" %s: descriptors %u to %u written\n", 1967 channel->name, start_index & (ring->rdesc_count - 1), 1968 (ring->cur - 1) & (ring->rdesc_count - 1)); 1969 1970 DBGPR("<--xgbe_dev_xmit\n"); 1971 } 1972 1973 static int xgbe_dev_read(struct xgbe_channel *channel) 1974 { 1975 struct xgbe_prv_data *pdata = channel->pdata; 1976 struct xgbe_ring *ring = channel->rx_ring; 1977 struct xgbe_ring_data *rdata; 1978 struct xgbe_ring_desc *rdesc; 1979 struct xgbe_packet_data *packet = &ring->packet_data; 1980 struct net_device *netdev = pdata->netdev; 1981 unsigned int err, etlt, l34t; 1982 1983 DBGPR("-->xgbe_dev_read: cur = %d\n", ring->cur); 1984 1985 rdata = XGBE_GET_DESC_DATA(ring, ring->cur); 1986 rdesc = rdata->rdesc; 1987 1988 /* Check for data availability */ 1989 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN)) 1990 return 1; 1991 1992 /* Make sure descriptor fields are read after reading the OWN bit */ 1993 dma_rmb(); 1994 1995 if (netif_msg_rx_status(pdata)) 1996 xgbe_dump_rx_desc(pdata, ring, ring->cur); 1997 1998 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CTXT)) { 1999 /* Timestamp Context Descriptor */ 2000 xgbe_get_rx_tstamp(packet, rdesc); 2001 2002 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 2003 CONTEXT, 1); 2004 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 2005 CONTEXT_NEXT, 0); 2006 return 0; 2007 } 2008 2009 /* Normal Descriptor, be sure Context Descriptor bit is off */ 2010 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, CONTEXT, 0); 2011 2012 /* Indicate if a Context Descriptor is next */ 2013 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CDA)) 2014 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 2015 CONTEXT_NEXT, 1); 2016 2017 /* Get the header length */ 2018 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, FD)) { 2019 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 2020 FIRST, 1); 2021 rdata->rx.hdr_len = XGMAC_GET_BITS_LE(rdesc->desc2, 2022 RX_NORMAL_DESC2, HL); 2023 if (rdata->rx.hdr_len) 2024 pdata->ext_stats.rx_split_header_packets++; 2025 } else { 2026 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 2027 FIRST, 0); 2028 } 2029 2030 /* Get the RSS hash */ 2031 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, RSV)) { 2032 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 2033 RSS_HASH, 1); 2034 2035 packet->rss_hash = le32_to_cpu(rdesc->desc1); 2036 2037 l34t = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, L34T); 2038 switch (l34t) { 2039 case RX_DESC3_L34T_IPV4_TCP: 2040 case RX_DESC3_L34T_IPV4_UDP: 2041 case RX_DESC3_L34T_IPV6_TCP: 2042 case RX_DESC3_L34T_IPV6_UDP: 2043 packet->rss_hash_type = PKT_HASH_TYPE_L4; 2044 break; 2045 default: 2046 packet->rss_hash_type = PKT_HASH_TYPE_L3; 2047 } 2048 } 2049 2050 /* Not all the data has been transferred for this packet */ 2051 if (!XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, LD)) 2052 return 0; 2053 2054 /* This is the last of the data for this packet */ 2055 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 2056 LAST, 1); 2057 2058 /* Get the packet length */ 2059 rdata->rx.len = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, PL); 2060 2061 /* Set checksum done indicator as appropriate */ 2062 if (netdev->features & NETIF_F_RXCSUM) { 2063 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 2064 CSUM_DONE, 1); 2065 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 2066 TNPCSUM_DONE, 1); 2067 } 2068 2069 /* Set the tunneled packet indicator */ 2070 if (XGMAC_GET_BITS_LE(rdesc->desc2, RX_NORMAL_DESC2, TNP)) { 2071 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 2072 TNP, 1); 2073 pdata->ext_stats.rx_vxlan_packets++; 2074 2075 l34t = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, L34T); 2076 switch (l34t) { 2077 case RX_DESC3_L34T_IPV4_UNKNOWN: 2078 case RX_DESC3_L34T_IPV6_UNKNOWN: 2079 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 2080 TNPCSUM_DONE, 0); 2081 break; 2082 } 2083 } 2084 2085 /* Check for errors (only valid in last descriptor) */ 2086 err = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ES); 2087 etlt = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ETLT); 2088 netif_dbg(pdata, rx_status, netdev, "err=%u, etlt=%#x\n", err, etlt); 2089 2090 if (!err || !etlt) { 2091 /* No error if err is 0 or etlt is 0 */ 2092 if ((etlt == 0x09) && 2093 (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)) { 2094 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 2095 VLAN_CTAG, 1); 2096 packet->vlan_ctag = XGMAC_GET_BITS_LE(rdesc->desc0, 2097 RX_NORMAL_DESC0, 2098 OVT); 2099 netif_dbg(pdata, rx_status, netdev, "vlan-ctag=%#06x\n", 2100 packet->vlan_ctag); 2101 } 2102 } else { 2103 unsigned int tnp = XGMAC_GET_BITS(packet->attributes, 2104 RX_PACKET_ATTRIBUTES, TNP); 2105 2106 if ((etlt == 0x05) || (etlt == 0x06)) { 2107 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 2108 CSUM_DONE, 0); 2109 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 2110 TNPCSUM_DONE, 0); 2111 pdata->ext_stats.rx_csum_errors++; 2112 } else if (tnp && ((etlt == 0x09) || (etlt == 0x0a))) { 2113 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 2114 CSUM_DONE, 0); 2115 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 2116 TNPCSUM_DONE, 0); 2117 pdata->ext_stats.rx_vxlan_csum_errors++; 2118 } else { 2119 XGMAC_SET_BITS(packet->errors, RX_PACKET_ERRORS, 2120 FRAME, 1); 2121 } 2122 } 2123 2124 pdata->ext_stats.rxq_packets[channel->queue_index]++; 2125 pdata->ext_stats.rxq_bytes[channel->queue_index] += rdata->rx.len; 2126 2127 DBGPR("<--xgbe_dev_read: %s - descriptor=%u (cur=%d)\n", channel->name, 2128 ring->cur & (ring->rdesc_count - 1), ring->cur); 2129 2130 return 0; 2131 } 2132 2133 static int xgbe_is_context_desc(struct xgbe_ring_desc *rdesc) 2134 { 2135 /* Rx and Tx share CTXT bit, so check TDES3.CTXT bit */ 2136 return XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT); 2137 } 2138 2139 static int xgbe_is_last_desc(struct xgbe_ring_desc *rdesc) 2140 { 2141 /* Rx and Tx share LD bit, so check TDES3.LD bit */ 2142 return XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD); 2143 } 2144 2145 static int xgbe_enable_int(struct xgbe_channel *channel, 2146 enum xgbe_int int_id) 2147 { 2148 switch (int_id) { 2149 case XGMAC_INT_DMA_CH_SR_TI: 2150 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 1); 2151 break; 2152 case XGMAC_INT_DMA_CH_SR_TPS: 2153 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TXSE, 1); 2154 break; 2155 case XGMAC_INT_DMA_CH_SR_TBU: 2156 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TBUE, 1); 2157 break; 2158 case XGMAC_INT_DMA_CH_SR_RI: 2159 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 1); 2160 break; 2161 case XGMAC_INT_DMA_CH_SR_RBU: 2162 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RBUE, 1); 2163 break; 2164 case XGMAC_INT_DMA_CH_SR_RPS: 2165 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RSE, 1); 2166 break; 2167 case XGMAC_INT_DMA_CH_SR_TI_RI: 2168 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 1); 2169 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 1); 2170 break; 2171 case XGMAC_INT_DMA_CH_SR_FBE: 2172 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, FBEE, 1); 2173 break; 2174 case XGMAC_INT_DMA_ALL: 2175 channel->curr_ier |= channel->saved_ier; 2176 break; 2177 default: 2178 return -1; 2179 } 2180 2181 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, channel->curr_ier); 2182 2183 return 0; 2184 } 2185 2186 static int xgbe_disable_int(struct xgbe_channel *channel, 2187 enum xgbe_int int_id) 2188 { 2189 switch (int_id) { 2190 case XGMAC_INT_DMA_CH_SR_TI: 2191 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 0); 2192 break; 2193 case XGMAC_INT_DMA_CH_SR_TPS: 2194 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TXSE, 0); 2195 break; 2196 case XGMAC_INT_DMA_CH_SR_TBU: 2197 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TBUE, 0); 2198 break; 2199 case XGMAC_INT_DMA_CH_SR_RI: 2200 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 0); 2201 break; 2202 case XGMAC_INT_DMA_CH_SR_RBU: 2203 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RBUE, 0); 2204 break; 2205 case XGMAC_INT_DMA_CH_SR_RPS: 2206 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RSE, 0); 2207 break; 2208 case XGMAC_INT_DMA_CH_SR_TI_RI: 2209 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 0); 2210 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 0); 2211 break; 2212 case XGMAC_INT_DMA_CH_SR_FBE: 2213 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, FBEE, 0); 2214 break; 2215 case XGMAC_INT_DMA_ALL: 2216 channel->saved_ier = channel->curr_ier; 2217 channel->curr_ier = 0; 2218 break; 2219 default: 2220 return -1; 2221 } 2222 2223 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, channel->curr_ier); 2224 2225 return 0; 2226 } 2227 2228 static int __xgbe_exit(struct xgbe_prv_data *pdata) 2229 { 2230 unsigned int count = 2000; 2231 2232 DBGPR("-->xgbe_exit\n"); 2233 2234 /* Issue a software reset */ 2235 XGMAC_IOWRITE_BITS(pdata, DMA_MR, SWR, 1); 2236 usleep_range(10, 15); 2237 2238 /* Poll Until Poll Condition */ 2239 while (--count && XGMAC_IOREAD_BITS(pdata, DMA_MR, SWR)) 2240 usleep_range(500, 600); 2241 2242 if (!count) 2243 return -EBUSY; 2244 2245 DBGPR("<--xgbe_exit\n"); 2246 2247 return 0; 2248 } 2249 2250 static int xgbe_exit(struct xgbe_prv_data *pdata) 2251 { 2252 int ret; 2253 2254 /* To guard against possible incorrectly generated interrupts, 2255 * issue the software reset twice. 2256 */ 2257 ret = __xgbe_exit(pdata); 2258 if (ret) 2259 return ret; 2260 2261 return __xgbe_exit(pdata); 2262 } 2263 2264 static int xgbe_flush_tx_queues(struct xgbe_prv_data *pdata) 2265 { 2266 unsigned int i, count; 2267 2268 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) < 0x21) 2269 return 0; 2270 2271 for (i = 0; i < pdata->tx_q_count; i++) 2272 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, FTQ, 1); 2273 2274 /* Poll Until Poll Condition */ 2275 for (i = 0; i < pdata->tx_q_count; i++) { 2276 count = 2000; 2277 while (--count && XGMAC_MTL_IOREAD_BITS(pdata, i, 2278 MTL_Q_TQOMR, FTQ)) 2279 usleep_range(500, 600); 2280 2281 if (!count) 2282 return -EBUSY; 2283 } 2284 2285 return 0; 2286 } 2287 2288 static void xgbe_config_dma_bus(struct xgbe_prv_data *pdata) 2289 { 2290 unsigned int sbmr; 2291 2292 sbmr = XGMAC_IOREAD(pdata, DMA_SBMR); 2293 2294 /* Set enhanced addressing mode */ 2295 XGMAC_SET_BITS(sbmr, DMA_SBMR, EAME, 1); 2296 2297 /* Set the System Bus mode */ 2298 XGMAC_SET_BITS(sbmr, DMA_SBMR, UNDEF, 1); 2299 XGMAC_SET_BITS(sbmr, DMA_SBMR, BLEN, pdata->blen >> 2); 2300 XGMAC_SET_BITS(sbmr, DMA_SBMR, AAL, pdata->aal); 2301 XGMAC_SET_BITS(sbmr, DMA_SBMR, RD_OSR_LMT, pdata->rd_osr_limit - 1); 2302 XGMAC_SET_BITS(sbmr, DMA_SBMR, WR_OSR_LMT, pdata->wr_osr_limit - 1); 2303 2304 XGMAC_IOWRITE(pdata, DMA_SBMR, sbmr); 2305 2306 /* Set descriptor fetching threshold */ 2307 if (pdata->vdata->tx_desc_prefetch) 2308 XGMAC_IOWRITE_BITS(pdata, DMA_TXEDMACR, TDPS, 2309 pdata->vdata->tx_desc_prefetch); 2310 2311 if (pdata->vdata->rx_desc_prefetch) 2312 XGMAC_IOWRITE_BITS(pdata, DMA_RXEDMACR, RDPS, 2313 pdata->vdata->rx_desc_prefetch); 2314 } 2315 2316 static void xgbe_config_dma_cache(struct xgbe_prv_data *pdata) 2317 { 2318 XGMAC_IOWRITE(pdata, DMA_AXIARCR, pdata->arcr); 2319 XGMAC_IOWRITE(pdata, DMA_AXIAWCR, pdata->awcr); 2320 if (pdata->awarcr) 2321 XGMAC_IOWRITE(pdata, DMA_AXIAWARCR, pdata->awarcr); 2322 } 2323 2324 static void xgbe_config_mtl_mode(struct xgbe_prv_data *pdata) 2325 { 2326 unsigned int i; 2327 2328 /* Set Tx to weighted round robin scheduling algorithm */ 2329 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_WRR); 2330 2331 /* Set Tx traffic classes to use WRR algorithm with equal weights */ 2332 for (i = 0; i < pdata->hw_feat.tc_cnt; i++) { 2333 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA, 2334 MTL_TSA_ETS); 2335 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW, 1); 2336 } 2337 2338 /* Set Rx to strict priority algorithm */ 2339 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, RAA, MTL_RAA_SP); 2340 } 2341 2342 static void xgbe_queue_flow_control_threshold(struct xgbe_prv_data *pdata, 2343 unsigned int queue, 2344 unsigned int q_fifo_size) 2345 { 2346 unsigned int frame_fifo_size; 2347 unsigned int rfa, rfd; 2348 2349 frame_fifo_size = XGMAC_FLOW_CONTROL_ALIGN(xgbe_get_max_frame(pdata)); 2350 2351 if (pdata->pfcq[queue] && (q_fifo_size > pdata->pfc_rfa)) { 2352 /* PFC is active for this queue */ 2353 rfa = pdata->pfc_rfa; 2354 rfd = rfa + frame_fifo_size; 2355 if (rfd > XGMAC_FLOW_CONTROL_MAX) 2356 rfd = XGMAC_FLOW_CONTROL_MAX; 2357 if (rfa >= XGMAC_FLOW_CONTROL_MAX) 2358 rfa = XGMAC_FLOW_CONTROL_MAX - XGMAC_FLOW_CONTROL_UNIT; 2359 } else { 2360 /* This path deals with just maximum frame sizes which are 2361 * limited to a jumbo frame of 9,000 (plus headers, etc.) 2362 * so we can never exceed the maximum allowable RFA/RFD 2363 * values. 2364 */ 2365 if (q_fifo_size <= 2048) { 2366 /* rx_rfd to zero to signal no flow control */ 2367 pdata->rx_rfa[queue] = 0; 2368 pdata->rx_rfd[queue] = 0; 2369 return; 2370 } 2371 2372 if (q_fifo_size <= 4096) { 2373 /* Between 2048 and 4096 */ 2374 pdata->rx_rfa[queue] = 0; /* Full - 1024 bytes */ 2375 pdata->rx_rfd[queue] = 1; /* Full - 1536 bytes */ 2376 return; 2377 } 2378 2379 if (q_fifo_size <= frame_fifo_size) { 2380 /* Between 4096 and max-frame */ 2381 pdata->rx_rfa[queue] = 2; /* Full - 2048 bytes */ 2382 pdata->rx_rfd[queue] = 5; /* Full - 3584 bytes */ 2383 return; 2384 } 2385 2386 if (q_fifo_size <= (frame_fifo_size * 3)) { 2387 /* Between max-frame and 3 max-frames, 2388 * trigger if we get just over a frame of data and 2389 * resume when we have just under half a frame left. 2390 */ 2391 rfa = q_fifo_size - frame_fifo_size; 2392 rfd = rfa + (frame_fifo_size / 2); 2393 } else { 2394 /* Above 3 max-frames - trigger when just over 2395 * 2 frames of space available 2396 */ 2397 rfa = frame_fifo_size * 2; 2398 rfa += XGMAC_FLOW_CONTROL_UNIT; 2399 rfd = rfa + frame_fifo_size; 2400 } 2401 } 2402 2403 pdata->rx_rfa[queue] = XGMAC_FLOW_CONTROL_VALUE(rfa); 2404 pdata->rx_rfd[queue] = XGMAC_FLOW_CONTROL_VALUE(rfd); 2405 } 2406 2407 static void xgbe_calculate_flow_control_threshold(struct xgbe_prv_data *pdata, 2408 unsigned int *fifo) 2409 { 2410 unsigned int q_fifo_size; 2411 unsigned int i; 2412 2413 for (i = 0; i < pdata->rx_q_count; i++) { 2414 q_fifo_size = (fifo[i] + 1) * XGMAC_FIFO_UNIT; 2415 2416 xgbe_queue_flow_control_threshold(pdata, i, q_fifo_size); 2417 } 2418 } 2419 2420 static void xgbe_config_flow_control_threshold(struct xgbe_prv_data *pdata) 2421 { 2422 unsigned int i; 2423 2424 for (i = 0; i < pdata->rx_q_count; i++) { 2425 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFA, 2426 pdata->rx_rfa[i]); 2427 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFD, 2428 pdata->rx_rfd[i]); 2429 } 2430 } 2431 2432 static unsigned int xgbe_get_tx_fifo_size(struct xgbe_prv_data *pdata) 2433 { 2434 /* The configured value may not be the actual amount of fifo RAM */ 2435 return min_t(unsigned int, pdata->tx_max_fifo_size, 2436 pdata->hw_feat.tx_fifo_size); 2437 } 2438 2439 static unsigned int xgbe_get_rx_fifo_size(struct xgbe_prv_data *pdata) 2440 { 2441 /* The configured value may not be the actual amount of fifo RAM */ 2442 return min_t(unsigned int, pdata->rx_max_fifo_size, 2443 pdata->hw_feat.rx_fifo_size); 2444 } 2445 2446 static void xgbe_calculate_equal_fifo(unsigned int fifo_size, 2447 unsigned int queue_count, 2448 unsigned int *fifo) 2449 { 2450 unsigned int q_fifo_size; 2451 unsigned int p_fifo; 2452 unsigned int i; 2453 2454 q_fifo_size = fifo_size / queue_count; 2455 2456 /* Calculate the fifo setting by dividing the queue's fifo size 2457 * by the fifo allocation increment (with 0 representing the 2458 * base allocation increment so decrement the result by 1). 2459 */ 2460 p_fifo = q_fifo_size / XGMAC_FIFO_UNIT; 2461 if (p_fifo) 2462 p_fifo--; 2463 2464 /* Distribute the fifo equally amongst the queues */ 2465 for (i = 0; i < queue_count; i++) 2466 fifo[i] = p_fifo; 2467 } 2468 2469 static unsigned int xgbe_set_nonprio_fifos(unsigned int fifo_size, 2470 unsigned int queue_count, 2471 unsigned int *fifo) 2472 { 2473 unsigned int i; 2474 2475 BUILD_BUG_ON_NOT_POWER_OF_2(XGMAC_FIFO_MIN_ALLOC); 2476 2477 if (queue_count <= IEEE_8021QAZ_MAX_TCS) 2478 return fifo_size; 2479 2480 /* Rx queues 9 and up are for specialized packets, 2481 * such as PTP or DCB control packets, etc. and 2482 * don't require a large fifo 2483 */ 2484 for (i = IEEE_8021QAZ_MAX_TCS; i < queue_count; i++) { 2485 fifo[i] = (XGMAC_FIFO_MIN_ALLOC / XGMAC_FIFO_UNIT) - 1; 2486 fifo_size -= XGMAC_FIFO_MIN_ALLOC; 2487 } 2488 2489 return fifo_size; 2490 } 2491 2492 static unsigned int xgbe_get_pfc_delay(struct xgbe_prv_data *pdata) 2493 { 2494 unsigned int delay; 2495 2496 /* If a delay has been provided, use that */ 2497 if (pdata->pfc->delay) 2498 return pdata->pfc->delay / 8; 2499 2500 /* Allow for two maximum size frames */ 2501 delay = xgbe_get_max_frame(pdata); 2502 delay += XGMAC_ETH_PREAMBLE; 2503 delay *= 2; 2504 2505 /* Allow for PFC frame */ 2506 delay += XGMAC_PFC_DATA_LEN; 2507 delay += ETH_HLEN + ETH_FCS_LEN; 2508 delay += XGMAC_ETH_PREAMBLE; 2509 2510 /* Allow for miscellaneous delays (LPI exit, cable, etc.) */ 2511 delay += XGMAC_PFC_DELAYS; 2512 2513 return delay; 2514 } 2515 2516 static unsigned int xgbe_get_pfc_queues(struct xgbe_prv_data *pdata) 2517 { 2518 unsigned int count, prio_queues; 2519 unsigned int i; 2520 2521 if (!pdata->pfc->pfc_en) 2522 return 0; 2523 2524 count = 0; 2525 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count); 2526 for (i = 0; i < prio_queues; i++) { 2527 if (!xgbe_is_pfc_queue(pdata, i)) 2528 continue; 2529 2530 pdata->pfcq[i] = 1; 2531 count++; 2532 } 2533 2534 return count; 2535 } 2536 2537 static void xgbe_calculate_dcb_fifo(struct xgbe_prv_data *pdata, 2538 unsigned int fifo_size, 2539 unsigned int *fifo) 2540 { 2541 unsigned int q_fifo_size, rem_fifo, addn_fifo; 2542 unsigned int prio_queues; 2543 unsigned int pfc_count; 2544 unsigned int i; 2545 2546 q_fifo_size = XGMAC_FIFO_ALIGN(xgbe_get_max_frame(pdata)); 2547 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count); 2548 pfc_count = xgbe_get_pfc_queues(pdata); 2549 2550 if (!pfc_count || ((q_fifo_size * prio_queues) > fifo_size)) { 2551 /* No traffic classes with PFC enabled or can't do lossless */ 2552 xgbe_calculate_equal_fifo(fifo_size, prio_queues, fifo); 2553 return; 2554 } 2555 2556 /* Calculate how much fifo we have to play with */ 2557 rem_fifo = fifo_size - (q_fifo_size * prio_queues); 2558 2559 /* Calculate how much more than base fifo PFC needs, which also 2560 * becomes the threshold activation point (RFA) 2561 */ 2562 pdata->pfc_rfa = xgbe_get_pfc_delay(pdata); 2563 pdata->pfc_rfa = XGMAC_FLOW_CONTROL_ALIGN(pdata->pfc_rfa); 2564 2565 if (pdata->pfc_rfa > q_fifo_size) { 2566 addn_fifo = pdata->pfc_rfa - q_fifo_size; 2567 addn_fifo = XGMAC_FIFO_ALIGN(addn_fifo); 2568 } else { 2569 addn_fifo = 0; 2570 } 2571 2572 /* Calculate DCB fifo settings: 2573 * - distribute remaining fifo between the VLAN priority 2574 * queues based on traffic class PFC enablement and overall 2575 * priority (0 is lowest priority, so start at highest) 2576 */ 2577 i = prio_queues; 2578 while (i > 0) { 2579 i--; 2580 2581 fifo[i] = (q_fifo_size / XGMAC_FIFO_UNIT) - 1; 2582 2583 if (!pdata->pfcq[i] || !addn_fifo) 2584 continue; 2585 2586 if (addn_fifo > rem_fifo) { 2587 netdev_warn(pdata->netdev, 2588 "RXq%u cannot set needed fifo size\n", i); 2589 if (!rem_fifo) 2590 continue; 2591 2592 addn_fifo = rem_fifo; 2593 } 2594 2595 fifo[i] += (addn_fifo / XGMAC_FIFO_UNIT); 2596 rem_fifo -= addn_fifo; 2597 } 2598 2599 if (rem_fifo) { 2600 unsigned int inc_fifo = rem_fifo / prio_queues; 2601 2602 /* Distribute remaining fifo across queues */ 2603 for (i = 0; i < prio_queues; i++) 2604 fifo[i] += (inc_fifo / XGMAC_FIFO_UNIT); 2605 } 2606 } 2607 2608 static void xgbe_config_tx_fifo_size(struct xgbe_prv_data *pdata) 2609 { 2610 unsigned int fifo_size; 2611 unsigned int fifo[XGBE_MAX_QUEUES]; 2612 unsigned int i; 2613 2614 fifo_size = xgbe_get_tx_fifo_size(pdata); 2615 2616 xgbe_calculate_equal_fifo(fifo_size, pdata->tx_q_count, fifo); 2617 2618 for (i = 0; i < pdata->tx_q_count; i++) 2619 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TQS, fifo[i]); 2620 2621 netif_info(pdata, drv, pdata->netdev, 2622 "%d Tx hardware queues, %d byte fifo per queue\n", 2623 pdata->tx_q_count, ((fifo[0] + 1) * XGMAC_FIFO_UNIT)); 2624 } 2625 2626 static void xgbe_config_rx_fifo_size(struct xgbe_prv_data *pdata) 2627 { 2628 unsigned int fifo_size; 2629 unsigned int fifo[XGBE_MAX_QUEUES]; 2630 unsigned int prio_queues; 2631 unsigned int i; 2632 2633 /* Clear any DCB related fifo/queue information */ 2634 memset(pdata->pfcq, 0, sizeof(pdata->pfcq)); 2635 pdata->pfc_rfa = 0; 2636 2637 fifo_size = xgbe_get_rx_fifo_size(pdata); 2638 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count); 2639 2640 /* Assign a minimum fifo to the non-VLAN priority queues */ 2641 fifo_size = xgbe_set_nonprio_fifos(fifo_size, pdata->rx_q_count, fifo); 2642 2643 if (pdata->pfc && pdata->ets) 2644 xgbe_calculate_dcb_fifo(pdata, fifo_size, fifo); 2645 else 2646 xgbe_calculate_equal_fifo(fifo_size, prio_queues, fifo); 2647 2648 for (i = 0; i < pdata->rx_q_count; i++) 2649 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RQS, fifo[i]); 2650 2651 xgbe_calculate_flow_control_threshold(pdata, fifo); 2652 xgbe_config_flow_control_threshold(pdata); 2653 2654 if (pdata->pfc && pdata->ets && pdata->pfc->pfc_en) { 2655 netif_info(pdata, drv, pdata->netdev, 2656 "%u Rx hardware queues\n", pdata->rx_q_count); 2657 for (i = 0; i < pdata->rx_q_count; i++) 2658 netif_info(pdata, drv, pdata->netdev, 2659 "RxQ%u, %u byte fifo queue\n", i, 2660 ((fifo[i] + 1) * XGMAC_FIFO_UNIT)); 2661 } else { 2662 netif_info(pdata, drv, pdata->netdev, 2663 "%u Rx hardware queues, %u byte fifo per queue\n", 2664 pdata->rx_q_count, 2665 ((fifo[0] + 1) * XGMAC_FIFO_UNIT)); 2666 } 2667 } 2668 2669 static void xgbe_config_queue_mapping(struct xgbe_prv_data *pdata) 2670 { 2671 unsigned int qptc, qptc_extra, queue; 2672 unsigned int prio_queues; 2673 unsigned int ppq, ppq_extra, prio; 2674 unsigned int mask; 2675 unsigned int i, j, reg, reg_val; 2676 2677 /* Map the MTL Tx Queues to Traffic Classes 2678 * Note: Tx Queues >= Traffic Classes 2679 */ 2680 qptc = pdata->tx_q_count / pdata->hw_feat.tc_cnt; 2681 qptc_extra = pdata->tx_q_count % pdata->hw_feat.tc_cnt; 2682 2683 for (i = 0, queue = 0; i < pdata->hw_feat.tc_cnt; i++) { 2684 for (j = 0; j < qptc; j++) { 2685 netif_dbg(pdata, drv, pdata->netdev, 2686 "TXq%u mapped to TC%u\n", queue, i); 2687 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR, 2688 Q2TCMAP, i); 2689 pdata->q2tc_map[queue++] = i; 2690 } 2691 2692 if (i < qptc_extra) { 2693 netif_dbg(pdata, drv, pdata->netdev, 2694 "TXq%u mapped to TC%u\n", queue, i); 2695 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR, 2696 Q2TCMAP, i); 2697 pdata->q2tc_map[queue++] = i; 2698 } 2699 } 2700 2701 /* Map the 8 VLAN priority values to available MTL Rx queues */ 2702 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count); 2703 ppq = IEEE_8021QAZ_MAX_TCS / prio_queues; 2704 ppq_extra = IEEE_8021QAZ_MAX_TCS % prio_queues; 2705 2706 reg = MAC_RQC2R; 2707 reg_val = 0; 2708 for (i = 0, prio = 0; i < prio_queues;) { 2709 mask = 0; 2710 for (j = 0; j < ppq; j++) { 2711 netif_dbg(pdata, drv, pdata->netdev, 2712 "PRIO%u mapped to RXq%u\n", prio, i); 2713 mask |= (1 << prio); 2714 pdata->prio2q_map[prio++] = i; 2715 } 2716 2717 if (i < ppq_extra) { 2718 netif_dbg(pdata, drv, pdata->netdev, 2719 "PRIO%u mapped to RXq%u\n", prio, i); 2720 mask |= (1 << prio); 2721 pdata->prio2q_map[prio++] = i; 2722 } 2723 2724 reg_val |= (mask << ((i++ % MAC_RQC2_Q_PER_REG) << 3)); 2725 2726 if ((i % MAC_RQC2_Q_PER_REG) && (i != prio_queues)) 2727 continue; 2728 2729 XGMAC_IOWRITE(pdata, reg, reg_val); 2730 reg += MAC_RQC2_INC; 2731 reg_val = 0; 2732 } 2733 2734 /* Select dynamic mapping of MTL Rx queue to DMA Rx channel */ 2735 reg = MTL_RQDCM0R; 2736 reg_val = 0; 2737 for (i = 0; i < pdata->rx_q_count;) { 2738 reg_val |= (0x80 << ((i++ % MTL_RQDCM_Q_PER_REG) << 3)); 2739 2740 if ((i % MTL_RQDCM_Q_PER_REG) && (i != pdata->rx_q_count)) 2741 continue; 2742 2743 XGMAC_IOWRITE(pdata, reg, reg_val); 2744 2745 reg += MTL_RQDCM_INC; 2746 reg_val = 0; 2747 } 2748 } 2749 2750 static void xgbe_config_tc(struct xgbe_prv_data *pdata) 2751 { 2752 unsigned int offset, queue, prio; 2753 u8 i; 2754 2755 netdev_reset_tc(pdata->netdev); 2756 if (!pdata->num_tcs) 2757 return; 2758 2759 netdev_set_num_tc(pdata->netdev, pdata->num_tcs); 2760 2761 for (i = 0, queue = 0, offset = 0; i < pdata->num_tcs; i++) { 2762 while ((queue < pdata->tx_q_count) && 2763 (pdata->q2tc_map[queue] == i)) 2764 queue++; 2765 2766 netif_dbg(pdata, drv, pdata->netdev, "TC%u using TXq%u-%u\n", 2767 i, offset, queue - 1); 2768 netdev_set_tc_queue(pdata->netdev, i, queue - offset, offset); 2769 offset = queue; 2770 } 2771 2772 if (!pdata->ets) 2773 return; 2774 2775 for (prio = 0; prio < IEEE_8021QAZ_MAX_TCS; prio++) 2776 netdev_set_prio_tc_map(pdata->netdev, prio, 2777 pdata->ets->prio_tc[prio]); 2778 } 2779 2780 static void xgbe_config_dcb_tc(struct xgbe_prv_data *pdata) 2781 { 2782 struct ieee_ets *ets = pdata->ets; 2783 unsigned int total_weight, min_weight, weight; 2784 unsigned int mask, reg, reg_val; 2785 unsigned int i, prio; 2786 2787 if (!ets) 2788 return; 2789 2790 /* Set Tx to deficit weighted round robin scheduling algorithm (when 2791 * traffic class is using ETS algorithm) 2792 */ 2793 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_DWRR); 2794 2795 /* Set Traffic Class algorithms */ 2796 total_weight = pdata->netdev->mtu * pdata->hw_feat.tc_cnt; 2797 min_weight = total_weight / 100; 2798 if (!min_weight) 2799 min_weight = 1; 2800 2801 for (i = 0; i < pdata->hw_feat.tc_cnt; i++) { 2802 /* Map the priorities to the traffic class */ 2803 mask = 0; 2804 for (prio = 0; prio < IEEE_8021QAZ_MAX_TCS; prio++) { 2805 if (ets->prio_tc[prio] == i) 2806 mask |= (1 << prio); 2807 } 2808 mask &= 0xff; 2809 2810 netif_dbg(pdata, drv, pdata->netdev, "TC%u PRIO mask=%#x\n", 2811 i, mask); 2812 reg = MTL_TCPM0R + (MTL_TCPM_INC * (i / MTL_TCPM_TC_PER_REG)); 2813 reg_val = XGMAC_IOREAD(pdata, reg); 2814 2815 reg_val &= ~(0xff << ((i % MTL_TCPM_TC_PER_REG) << 3)); 2816 reg_val |= (mask << ((i % MTL_TCPM_TC_PER_REG) << 3)); 2817 2818 XGMAC_IOWRITE(pdata, reg, reg_val); 2819 2820 /* Set the traffic class algorithm */ 2821 switch (ets->tc_tsa[i]) { 2822 case IEEE_8021QAZ_TSA_STRICT: 2823 netif_dbg(pdata, drv, pdata->netdev, 2824 "TC%u using SP\n", i); 2825 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA, 2826 MTL_TSA_SP); 2827 break; 2828 case IEEE_8021QAZ_TSA_ETS: 2829 weight = total_weight * ets->tc_tx_bw[i] / 100; 2830 weight = clamp(weight, min_weight, total_weight); 2831 2832 netif_dbg(pdata, drv, pdata->netdev, 2833 "TC%u using DWRR (weight %u)\n", i, weight); 2834 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA, 2835 MTL_TSA_ETS); 2836 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW, 2837 weight); 2838 break; 2839 } 2840 } 2841 2842 xgbe_config_tc(pdata); 2843 } 2844 2845 static void xgbe_config_dcb_pfc(struct xgbe_prv_data *pdata) 2846 { 2847 if (!test_bit(XGBE_DOWN, &pdata->dev_state)) { 2848 /* Just stop the Tx queues while Rx fifo is changed */ 2849 netif_tx_stop_all_queues(pdata->netdev); 2850 2851 /* Suspend Rx so that fifo's can be adjusted */ 2852 pdata->hw_if.disable_rx(pdata); 2853 } 2854 2855 xgbe_config_rx_fifo_size(pdata); 2856 xgbe_config_flow_control(pdata); 2857 2858 if (!test_bit(XGBE_DOWN, &pdata->dev_state)) { 2859 /* Resume Rx */ 2860 pdata->hw_if.enable_rx(pdata); 2861 2862 /* Resume Tx queues */ 2863 netif_tx_start_all_queues(pdata->netdev); 2864 } 2865 } 2866 2867 static void xgbe_config_mac_address(struct xgbe_prv_data *pdata) 2868 { 2869 xgbe_set_mac_address(pdata, pdata->netdev->dev_addr); 2870 2871 /* Filtering is done using perfect filtering and hash filtering */ 2872 if (pdata->hw_feat.hash_table_size) { 2873 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1); 2874 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1); 2875 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HMC, 1); 2876 } 2877 } 2878 2879 static void xgbe_config_jumbo_enable(struct xgbe_prv_data *pdata) 2880 { 2881 unsigned int val; 2882 2883 val = (pdata->netdev->mtu > XGMAC_STD_PACKET_MTU) ? 1 : 0; 2884 2885 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, JE, val); 2886 } 2887 2888 static void xgbe_config_mac_speed(struct xgbe_prv_data *pdata) 2889 { 2890 xgbe_set_speed(pdata, pdata->phy_speed); 2891 } 2892 2893 static void xgbe_config_checksum_offload(struct xgbe_prv_data *pdata) 2894 { 2895 if (pdata->netdev->features & NETIF_F_RXCSUM) 2896 xgbe_enable_rx_csum(pdata); 2897 else 2898 xgbe_disable_rx_csum(pdata); 2899 } 2900 2901 static void xgbe_config_vlan_support(struct xgbe_prv_data *pdata) 2902 { 2903 /* Indicate that VLAN Tx CTAGs come from context descriptors */ 2904 XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, CSVL, 0); 2905 XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, VLTI, 1); 2906 2907 /* Set the current VLAN Hash Table register value */ 2908 xgbe_update_vlan_hash_table(pdata); 2909 2910 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER) 2911 xgbe_enable_rx_vlan_filtering(pdata); 2912 else 2913 xgbe_disable_rx_vlan_filtering(pdata); 2914 2915 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) 2916 xgbe_enable_rx_vlan_stripping(pdata); 2917 else 2918 xgbe_disable_rx_vlan_stripping(pdata); 2919 } 2920 2921 static u64 xgbe_mmc_read(struct xgbe_prv_data *pdata, unsigned int reg_lo) 2922 { 2923 bool read_hi; 2924 u64 val; 2925 2926 if (pdata->vdata->mmc_64bit) { 2927 switch (reg_lo) { 2928 /* These registers are always 32 bit */ 2929 case MMC_RXRUNTERROR: 2930 case MMC_RXJABBERERROR: 2931 case MMC_RXUNDERSIZE_G: 2932 case MMC_RXOVERSIZE_G: 2933 case MMC_RXWATCHDOGERROR: 2934 read_hi = false; 2935 break; 2936 2937 default: 2938 read_hi = true; 2939 } 2940 } else { 2941 switch (reg_lo) { 2942 /* These registers are always 64 bit */ 2943 case MMC_TXOCTETCOUNT_GB_LO: 2944 case MMC_TXOCTETCOUNT_G_LO: 2945 case MMC_RXOCTETCOUNT_GB_LO: 2946 case MMC_RXOCTETCOUNT_G_LO: 2947 read_hi = true; 2948 break; 2949 2950 default: 2951 read_hi = false; 2952 } 2953 } 2954 2955 val = XGMAC_IOREAD(pdata, reg_lo); 2956 2957 if (read_hi) 2958 val |= ((u64)XGMAC_IOREAD(pdata, reg_lo + 4) << 32); 2959 2960 return val; 2961 } 2962 2963 static void xgbe_tx_mmc_int(struct xgbe_prv_data *pdata) 2964 { 2965 struct xgbe_mmc_stats *stats = &pdata->mmc_stats; 2966 unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_TISR); 2967 2968 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXOCTETCOUNT_GB)) 2969 stats->txoctetcount_gb += 2970 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO); 2971 2972 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXFRAMECOUNT_GB)) 2973 stats->txframecount_gb += 2974 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO); 2975 2976 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXBROADCASTFRAMES_G)) 2977 stats->txbroadcastframes_g += 2978 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO); 2979 2980 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXMULTICASTFRAMES_G)) 2981 stats->txmulticastframes_g += 2982 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO); 2983 2984 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX64OCTETS_GB)) 2985 stats->tx64octets_gb += 2986 xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO); 2987 2988 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX65TO127OCTETS_GB)) 2989 stats->tx65to127octets_gb += 2990 xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO); 2991 2992 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX128TO255OCTETS_GB)) 2993 stats->tx128to255octets_gb += 2994 xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO); 2995 2996 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX256TO511OCTETS_GB)) 2997 stats->tx256to511octets_gb += 2998 xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO); 2999 3000 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX512TO1023OCTETS_GB)) 3001 stats->tx512to1023octets_gb += 3002 xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO); 3003 3004 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX1024TOMAXOCTETS_GB)) 3005 stats->tx1024tomaxoctets_gb += 3006 xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO); 3007 3008 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXUNICASTFRAMES_GB)) 3009 stats->txunicastframes_gb += 3010 xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO); 3011 3012 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXMULTICASTFRAMES_GB)) 3013 stats->txmulticastframes_gb += 3014 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO); 3015 3016 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXBROADCASTFRAMES_GB)) 3017 stats->txbroadcastframes_g += 3018 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO); 3019 3020 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXUNDERFLOWERROR)) 3021 stats->txunderflowerror += 3022 xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO); 3023 3024 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXOCTETCOUNT_G)) 3025 stats->txoctetcount_g += 3026 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO); 3027 3028 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXFRAMECOUNT_G)) 3029 stats->txframecount_g += 3030 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO); 3031 3032 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXPAUSEFRAMES)) 3033 stats->txpauseframes += 3034 xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO); 3035 3036 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXVLANFRAMES_G)) 3037 stats->txvlanframes_g += 3038 xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO); 3039 } 3040 3041 static void xgbe_rx_mmc_int(struct xgbe_prv_data *pdata) 3042 { 3043 struct xgbe_mmc_stats *stats = &pdata->mmc_stats; 3044 unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_RISR); 3045 3046 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXFRAMECOUNT_GB)) 3047 stats->rxframecount_gb += 3048 xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO); 3049 3050 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOCTETCOUNT_GB)) 3051 stats->rxoctetcount_gb += 3052 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO); 3053 3054 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOCTETCOUNT_G)) 3055 stats->rxoctetcount_g += 3056 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO); 3057 3058 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXBROADCASTFRAMES_G)) 3059 stats->rxbroadcastframes_g += 3060 xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO); 3061 3062 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXMULTICASTFRAMES_G)) 3063 stats->rxmulticastframes_g += 3064 xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO); 3065 3066 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXCRCERROR)) 3067 stats->rxcrcerror += 3068 xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO); 3069 3070 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXRUNTERROR)) 3071 stats->rxrunterror += 3072 xgbe_mmc_read(pdata, MMC_RXRUNTERROR); 3073 3074 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXJABBERERROR)) 3075 stats->rxjabbererror += 3076 xgbe_mmc_read(pdata, MMC_RXJABBERERROR); 3077 3078 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXUNDERSIZE_G)) 3079 stats->rxundersize_g += 3080 xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G); 3081 3082 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOVERSIZE_G)) 3083 stats->rxoversize_g += 3084 xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G); 3085 3086 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX64OCTETS_GB)) 3087 stats->rx64octets_gb += 3088 xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO); 3089 3090 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX65TO127OCTETS_GB)) 3091 stats->rx65to127octets_gb += 3092 xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO); 3093 3094 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX128TO255OCTETS_GB)) 3095 stats->rx128to255octets_gb += 3096 xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO); 3097 3098 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX256TO511OCTETS_GB)) 3099 stats->rx256to511octets_gb += 3100 xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO); 3101 3102 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX512TO1023OCTETS_GB)) 3103 stats->rx512to1023octets_gb += 3104 xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO); 3105 3106 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX1024TOMAXOCTETS_GB)) 3107 stats->rx1024tomaxoctets_gb += 3108 xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO); 3109 3110 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXUNICASTFRAMES_G)) 3111 stats->rxunicastframes_g += 3112 xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO); 3113 3114 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXLENGTHERROR)) 3115 stats->rxlengtherror += 3116 xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO); 3117 3118 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOUTOFRANGETYPE)) 3119 stats->rxoutofrangetype += 3120 xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO); 3121 3122 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXPAUSEFRAMES)) 3123 stats->rxpauseframes += 3124 xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO); 3125 3126 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXFIFOOVERFLOW)) 3127 stats->rxfifooverflow += 3128 xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO); 3129 3130 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXVLANFRAMES_GB)) 3131 stats->rxvlanframes_gb += 3132 xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO); 3133 3134 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXWATCHDOGERROR)) 3135 stats->rxwatchdogerror += 3136 xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR); 3137 } 3138 3139 static void xgbe_read_mmc_stats(struct xgbe_prv_data *pdata) 3140 { 3141 struct xgbe_mmc_stats *stats = &pdata->mmc_stats; 3142 3143 /* Freeze counters */ 3144 XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 1); 3145 3146 stats->txoctetcount_gb += 3147 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO); 3148 3149 stats->txframecount_gb += 3150 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO); 3151 3152 stats->txbroadcastframes_g += 3153 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO); 3154 3155 stats->txmulticastframes_g += 3156 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO); 3157 3158 stats->tx64octets_gb += 3159 xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO); 3160 3161 stats->tx65to127octets_gb += 3162 xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO); 3163 3164 stats->tx128to255octets_gb += 3165 xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO); 3166 3167 stats->tx256to511octets_gb += 3168 xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO); 3169 3170 stats->tx512to1023octets_gb += 3171 xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO); 3172 3173 stats->tx1024tomaxoctets_gb += 3174 xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO); 3175 3176 stats->txunicastframes_gb += 3177 xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO); 3178 3179 stats->txmulticastframes_gb += 3180 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO); 3181 3182 stats->txbroadcastframes_g += 3183 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO); 3184 3185 stats->txunderflowerror += 3186 xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO); 3187 3188 stats->txoctetcount_g += 3189 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO); 3190 3191 stats->txframecount_g += 3192 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO); 3193 3194 stats->txpauseframes += 3195 xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO); 3196 3197 stats->txvlanframes_g += 3198 xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO); 3199 3200 stats->rxframecount_gb += 3201 xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO); 3202 3203 stats->rxoctetcount_gb += 3204 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO); 3205 3206 stats->rxoctetcount_g += 3207 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO); 3208 3209 stats->rxbroadcastframes_g += 3210 xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO); 3211 3212 stats->rxmulticastframes_g += 3213 xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO); 3214 3215 stats->rxcrcerror += 3216 xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO); 3217 3218 stats->rxrunterror += 3219 xgbe_mmc_read(pdata, MMC_RXRUNTERROR); 3220 3221 stats->rxjabbererror += 3222 xgbe_mmc_read(pdata, MMC_RXJABBERERROR); 3223 3224 stats->rxundersize_g += 3225 xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G); 3226 3227 stats->rxoversize_g += 3228 xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G); 3229 3230 stats->rx64octets_gb += 3231 xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO); 3232 3233 stats->rx65to127octets_gb += 3234 xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO); 3235 3236 stats->rx128to255octets_gb += 3237 xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO); 3238 3239 stats->rx256to511octets_gb += 3240 xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO); 3241 3242 stats->rx512to1023octets_gb += 3243 xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO); 3244 3245 stats->rx1024tomaxoctets_gb += 3246 xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO); 3247 3248 stats->rxunicastframes_g += 3249 xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO); 3250 3251 stats->rxlengtherror += 3252 xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO); 3253 3254 stats->rxoutofrangetype += 3255 xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO); 3256 3257 stats->rxpauseframes += 3258 xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO); 3259 3260 stats->rxfifooverflow += 3261 xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO); 3262 3263 stats->rxvlanframes_gb += 3264 xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO); 3265 3266 stats->rxwatchdogerror += 3267 xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR); 3268 3269 /* Un-freeze counters */ 3270 XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 0); 3271 } 3272 3273 static void xgbe_config_mmc(struct xgbe_prv_data *pdata) 3274 { 3275 /* Set counters to reset on read */ 3276 XGMAC_IOWRITE_BITS(pdata, MMC_CR, ROR, 1); 3277 3278 /* Reset the counters */ 3279 XGMAC_IOWRITE_BITS(pdata, MMC_CR, CR, 1); 3280 } 3281 3282 static void xgbe_txq_prepare_tx_stop(struct xgbe_prv_data *pdata, 3283 unsigned int queue) 3284 { 3285 unsigned int tx_status; 3286 unsigned long tx_timeout; 3287 3288 /* The Tx engine cannot be stopped if it is actively processing 3289 * packets. Wait for the Tx queue to empty the Tx fifo. Don't 3290 * wait forever though... 3291 */ 3292 tx_timeout = jiffies + (XGBE_DMA_STOP_TIMEOUT * HZ); 3293 while (time_before(jiffies, tx_timeout)) { 3294 tx_status = XGMAC_MTL_IOREAD(pdata, queue, MTL_Q_TQDR); 3295 if ((XGMAC_GET_BITS(tx_status, MTL_Q_TQDR, TRCSTS) != 1) && 3296 (XGMAC_GET_BITS(tx_status, MTL_Q_TQDR, TXQSTS) == 0)) 3297 break; 3298 3299 usleep_range(500, 1000); 3300 } 3301 3302 if (!time_before(jiffies, tx_timeout)) 3303 netdev_info(pdata->netdev, 3304 "timed out waiting for Tx queue %u to empty\n", 3305 queue); 3306 } 3307 3308 static void xgbe_prepare_tx_stop(struct xgbe_prv_data *pdata, 3309 unsigned int queue) 3310 { 3311 unsigned int tx_dsr, tx_pos, tx_qidx; 3312 unsigned int tx_status; 3313 unsigned long tx_timeout; 3314 3315 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) > 0x20) 3316 return xgbe_txq_prepare_tx_stop(pdata, queue); 3317 3318 /* Calculate the status register to read and the position within */ 3319 if (queue < DMA_DSRX_FIRST_QUEUE) { 3320 tx_dsr = DMA_DSR0; 3321 tx_pos = (queue * DMA_DSR_Q_WIDTH) + DMA_DSR0_TPS_START; 3322 } else { 3323 tx_qidx = queue - DMA_DSRX_FIRST_QUEUE; 3324 3325 tx_dsr = DMA_DSR1 + ((tx_qidx / DMA_DSRX_QPR) * DMA_DSRX_INC); 3326 tx_pos = ((tx_qidx % DMA_DSRX_QPR) * DMA_DSR_Q_WIDTH) + 3327 DMA_DSRX_TPS_START; 3328 } 3329 3330 /* The Tx engine cannot be stopped if it is actively processing 3331 * descriptors. Wait for the Tx engine to enter the stopped or 3332 * suspended state. Don't wait forever though... 3333 */ 3334 tx_timeout = jiffies + (XGBE_DMA_STOP_TIMEOUT * HZ); 3335 while (time_before(jiffies, tx_timeout)) { 3336 tx_status = XGMAC_IOREAD(pdata, tx_dsr); 3337 tx_status = GET_BITS(tx_status, tx_pos, DMA_DSR_TPS_WIDTH); 3338 if ((tx_status == DMA_TPS_STOPPED) || 3339 (tx_status == DMA_TPS_SUSPENDED)) 3340 break; 3341 3342 usleep_range(500, 1000); 3343 } 3344 3345 if (!time_before(jiffies, tx_timeout)) 3346 netdev_info(pdata->netdev, 3347 "timed out waiting for Tx DMA channel %u to stop\n", 3348 queue); 3349 } 3350 3351 static void xgbe_enable_tx(struct xgbe_prv_data *pdata) 3352 { 3353 unsigned int i; 3354 3355 /* Enable each Tx DMA channel */ 3356 for (i = 0; i < pdata->channel_count; i++) { 3357 if (!pdata->channel[i]->tx_ring) 3358 break; 3359 3360 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 1); 3361 } 3362 3363 /* Enable each Tx queue */ 3364 for (i = 0; i < pdata->tx_q_count; i++) 3365 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, 3366 MTL_Q_ENABLED); 3367 3368 /* Enable MAC Tx */ 3369 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1); 3370 } 3371 3372 static void xgbe_disable_tx(struct xgbe_prv_data *pdata) 3373 { 3374 unsigned int i; 3375 3376 /* Prepare for Tx DMA channel stop */ 3377 for (i = 0; i < pdata->tx_q_count; i++) 3378 xgbe_prepare_tx_stop(pdata, i); 3379 3380 /* Disable MAC Tx */ 3381 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0); 3382 3383 /* Disable each Tx queue */ 3384 for (i = 0; i < pdata->tx_q_count; i++) 3385 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, 0); 3386 3387 /* Disable each Tx DMA channel */ 3388 for (i = 0; i < pdata->channel_count; i++) { 3389 if (!pdata->channel[i]->tx_ring) 3390 break; 3391 3392 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 0); 3393 } 3394 } 3395 3396 static void xgbe_prepare_rx_stop(struct xgbe_prv_data *pdata, 3397 unsigned int queue) 3398 { 3399 unsigned int rx_status; 3400 unsigned long rx_timeout; 3401 3402 /* The Rx engine cannot be stopped if it is actively processing 3403 * packets. Wait for the Rx queue to empty the Rx fifo. Don't 3404 * wait forever though... 3405 */ 3406 rx_timeout = jiffies + (XGBE_DMA_STOP_TIMEOUT * HZ); 3407 while (time_before(jiffies, rx_timeout)) { 3408 rx_status = XGMAC_MTL_IOREAD(pdata, queue, MTL_Q_RQDR); 3409 if ((XGMAC_GET_BITS(rx_status, MTL_Q_RQDR, PRXQ) == 0) && 3410 (XGMAC_GET_BITS(rx_status, MTL_Q_RQDR, RXQSTS) == 0)) 3411 break; 3412 3413 usleep_range(500, 1000); 3414 } 3415 3416 if (!time_before(jiffies, rx_timeout)) 3417 netdev_info(pdata->netdev, 3418 "timed out waiting for Rx queue %u to empty\n", 3419 queue); 3420 } 3421 3422 static void xgbe_enable_rx(struct xgbe_prv_data *pdata) 3423 { 3424 unsigned int reg_val, i; 3425 3426 /* Enable each Rx DMA channel */ 3427 for (i = 0; i < pdata->channel_count; i++) { 3428 if (!pdata->channel[i]->rx_ring) 3429 break; 3430 3431 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 1); 3432 } 3433 3434 /* Enable each Rx queue */ 3435 reg_val = 0; 3436 for (i = 0; i < pdata->rx_q_count; i++) 3437 reg_val |= (0x02 << (i << 1)); 3438 XGMAC_IOWRITE(pdata, MAC_RQC0R, reg_val); 3439 3440 /* Enable MAC Rx */ 3441 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 1); 3442 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 1); 3443 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 1); 3444 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 1); 3445 } 3446 3447 static void xgbe_disable_rx(struct xgbe_prv_data *pdata) 3448 { 3449 unsigned int i; 3450 3451 /* Disable MAC Rx */ 3452 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 0); 3453 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 0); 3454 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 0); 3455 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 0); 3456 3457 /* Prepare for Rx DMA channel stop */ 3458 for (i = 0; i < pdata->rx_q_count; i++) 3459 xgbe_prepare_rx_stop(pdata, i); 3460 3461 /* Disable each Rx queue */ 3462 XGMAC_IOWRITE(pdata, MAC_RQC0R, 0); 3463 3464 /* Disable each Rx DMA channel */ 3465 for (i = 0; i < pdata->channel_count; i++) { 3466 if (!pdata->channel[i]->rx_ring) 3467 break; 3468 3469 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 0); 3470 } 3471 } 3472 3473 static void xgbe_powerup_tx(struct xgbe_prv_data *pdata) 3474 { 3475 unsigned int i; 3476 3477 /* Enable each Tx DMA channel */ 3478 for (i = 0; i < pdata->channel_count; i++) { 3479 if (!pdata->channel[i]->tx_ring) 3480 break; 3481 3482 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 1); 3483 } 3484 3485 /* Enable MAC Tx */ 3486 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1); 3487 } 3488 3489 static void xgbe_powerdown_tx(struct xgbe_prv_data *pdata) 3490 { 3491 unsigned int i; 3492 3493 /* Prepare for Tx DMA channel stop */ 3494 for (i = 0; i < pdata->tx_q_count; i++) 3495 xgbe_prepare_tx_stop(pdata, i); 3496 3497 /* Disable MAC Tx */ 3498 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0); 3499 3500 /* Disable each Tx DMA channel */ 3501 for (i = 0; i < pdata->channel_count; i++) { 3502 if (!pdata->channel[i]->tx_ring) 3503 break; 3504 3505 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 0); 3506 } 3507 } 3508 3509 static void xgbe_powerup_rx(struct xgbe_prv_data *pdata) 3510 { 3511 unsigned int i; 3512 3513 /* Enable each Rx DMA channel */ 3514 for (i = 0; i < pdata->channel_count; i++) { 3515 if (!pdata->channel[i]->rx_ring) 3516 break; 3517 3518 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 1); 3519 } 3520 } 3521 3522 static void xgbe_powerdown_rx(struct xgbe_prv_data *pdata) 3523 { 3524 unsigned int i; 3525 3526 /* Disable each Rx DMA channel */ 3527 for (i = 0; i < pdata->channel_count; i++) { 3528 if (!pdata->channel[i]->rx_ring) 3529 break; 3530 3531 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 0); 3532 } 3533 } 3534 3535 static int xgbe_init(struct xgbe_prv_data *pdata) 3536 { 3537 struct xgbe_desc_if *desc_if = &pdata->desc_if; 3538 int ret; 3539 3540 DBGPR("-->xgbe_init\n"); 3541 3542 /* Flush Tx queues */ 3543 ret = xgbe_flush_tx_queues(pdata); 3544 if (ret) { 3545 netdev_err(pdata->netdev, "error flushing TX queues\n"); 3546 return ret; 3547 } 3548 3549 /* 3550 * Initialize DMA related features 3551 */ 3552 xgbe_config_dma_bus(pdata); 3553 xgbe_config_dma_cache(pdata); 3554 xgbe_config_osp_mode(pdata); 3555 xgbe_config_pbl_val(pdata); 3556 xgbe_config_rx_coalesce(pdata); 3557 xgbe_config_tx_coalesce(pdata); 3558 xgbe_config_rx_buffer_size(pdata); 3559 xgbe_config_tso_mode(pdata); 3560 3561 if (pdata->netdev->features & NETIF_F_RXCSUM) { 3562 xgbe_config_sph_mode(pdata); 3563 xgbe_config_rss(pdata); 3564 } 3565 3566 desc_if->wrapper_tx_desc_init(pdata); 3567 desc_if->wrapper_rx_desc_init(pdata); 3568 xgbe_enable_dma_interrupts(pdata); 3569 3570 /* 3571 * Initialize MTL related features 3572 */ 3573 xgbe_config_mtl_mode(pdata); 3574 xgbe_config_queue_mapping(pdata); 3575 xgbe_config_tsf_mode(pdata, pdata->tx_sf_mode); 3576 xgbe_config_rsf_mode(pdata, pdata->rx_sf_mode); 3577 xgbe_config_tx_threshold(pdata, pdata->tx_threshold); 3578 xgbe_config_rx_threshold(pdata, pdata->rx_threshold); 3579 xgbe_config_tx_fifo_size(pdata); 3580 xgbe_config_rx_fifo_size(pdata); 3581 /*TODO: Error Packet and undersized good Packet forwarding enable 3582 (FEP and FUP) 3583 */ 3584 xgbe_config_dcb_tc(pdata); 3585 xgbe_enable_mtl_interrupts(pdata); 3586 3587 /* 3588 * Initialize MAC related features 3589 */ 3590 xgbe_config_mac_address(pdata); 3591 xgbe_config_rx_mode(pdata); 3592 xgbe_config_jumbo_enable(pdata); 3593 xgbe_config_flow_control(pdata); 3594 xgbe_config_mac_speed(pdata); 3595 xgbe_config_checksum_offload(pdata); 3596 xgbe_config_vlan_support(pdata); 3597 xgbe_config_mmc(pdata); 3598 xgbe_enable_mac_interrupts(pdata); 3599 3600 /* 3601 * Initialize ECC related features 3602 */ 3603 xgbe_enable_ecc_interrupts(pdata); 3604 3605 DBGPR("<--xgbe_init\n"); 3606 3607 return 0; 3608 } 3609 3610 void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *hw_if) 3611 { 3612 DBGPR("-->xgbe_init_function_ptrs\n"); 3613 3614 hw_if->tx_complete = xgbe_tx_complete; 3615 3616 hw_if->set_mac_address = xgbe_set_mac_address; 3617 hw_if->config_rx_mode = xgbe_config_rx_mode; 3618 3619 hw_if->enable_rx_csum = xgbe_enable_rx_csum; 3620 hw_if->disable_rx_csum = xgbe_disable_rx_csum; 3621 3622 hw_if->enable_rx_vlan_stripping = xgbe_enable_rx_vlan_stripping; 3623 hw_if->disable_rx_vlan_stripping = xgbe_disable_rx_vlan_stripping; 3624 hw_if->enable_rx_vlan_filtering = xgbe_enable_rx_vlan_filtering; 3625 hw_if->disable_rx_vlan_filtering = xgbe_disable_rx_vlan_filtering; 3626 hw_if->update_vlan_hash_table = xgbe_update_vlan_hash_table; 3627 3628 hw_if->read_mmd_regs = xgbe_read_mmd_regs; 3629 hw_if->write_mmd_regs = xgbe_write_mmd_regs; 3630 3631 hw_if->set_speed = xgbe_set_speed; 3632 3633 hw_if->set_ext_mii_mode = xgbe_set_ext_mii_mode; 3634 hw_if->read_ext_mii_regs_c22 = xgbe_read_ext_mii_regs_c22; 3635 hw_if->write_ext_mii_regs_c22 = xgbe_write_ext_mii_regs_c22; 3636 hw_if->read_ext_mii_regs_c45 = xgbe_read_ext_mii_regs_c45; 3637 hw_if->write_ext_mii_regs_c45 = xgbe_write_ext_mii_regs_c45; 3638 3639 hw_if->set_gpio = xgbe_set_gpio; 3640 hw_if->clr_gpio = xgbe_clr_gpio; 3641 3642 hw_if->enable_tx = xgbe_enable_tx; 3643 hw_if->disable_tx = xgbe_disable_tx; 3644 hw_if->enable_rx = xgbe_enable_rx; 3645 hw_if->disable_rx = xgbe_disable_rx; 3646 3647 hw_if->powerup_tx = xgbe_powerup_tx; 3648 hw_if->powerdown_tx = xgbe_powerdown_tx; 3649 hw_if->powerup_rx = xgbe_powerup_rx; 3650 hw_if->powerdown_rx = xgbe_powerdown_rx; 3651 3652 hw_if->dev_xmit = xgbe_dev_xmit; 3653 hw_if->dev_read = xgbe_dev_read; 3654 hw_if->enable_int = xgbe_enable_int; 3655 hw_if->disable_int = xgbe_disable_int; 3656 hw_if->init = xgbe_init; 3657 hw_if->exit = xgbe_exit; 3658 3659 /* Descriptor related Sequences have to be initialized here */ 3660 hw_if->tx_desc_init = xgbe_tx_desc_init; 3661 hw_if->rx_desc_init = xgbe_rx_desc_init; 3662 hw_if->tx_desc_reset = xgbe_tx_desc_reset; 3663 hw_if->rx_desc_reset = xgbe_rx_desc_reset; 3664 hw_if->is_last_desc = xgbe_is_last_desc; 3665 hw_if->is_context_desc = xgbe_is_context_desc; 3666 hw_if->tx_start_xmit = xgbe_tx_start_xmit; 3667 3668 /* For FLOW ctrl */ 3669 hw_if->config_tx_flow_control = xgbe_config_tx_flow_control; 3670 hw_if->config_rx_flow_control = xgbe_config_rx_flow_control; 3671 3672 /* For RX coalescing */ 3673 hw_if->config_rx_coalesce = xgbe_config_rx_coalesce; 3674 hw_if->config_tx_coalesce = xgbe_config_tx_coalesce; 3675 hw_if->usec_to_riwt = xgbe_usec_to_riwt; 3676 hw_if->riwt_to_usec = xgbe_riwt_to_usec; 3677 3678 /* For RX and TX threshold config */ 3679 hw_if->config_rx_threshold = xgbe_config_rx_threshold; 3680 hw_if->config_tx_threshold = xgbe_config_tx_threshold; 3681 3682 /* For RX and TX Store and Forward Mode config */ 3683 hw_if->config_rsf_mode = xgbe_config_rsf_mode; 3684 hw_if->config_tsf_mode = xgbe_config_tsf_mode; 3685 3686 /* For TX DMA Operating on Second Frame config */ 3687 hw_if->config_osp_mode = xgbe_config_osp_mode; 3688 3689 /* For MMC statistics support */ 3690 hw_if->tx_mmc_int = xgbe_tx_mmc_int; 3691 hw_if->rx_mmc_int = xgbe_rx_mmc_int; 3692 hw_if->read_mmc_stats = xgbe_read_mmc_stats; 3693 3694 /* For PTP config */ 3695 hw_if->config_tstamp = xgbe_config_tstamp; 3696 hw_if->update_tstamp_addend = xgbe_update_tstamp_addend; 3697 hw_if->set_tstamp_time = xgbe_set_tstamp_time; 3698 hw_if->get_tstamp_time = xgbe_get_tstamp_time; 3699 hw_if->get_tx_tstamp = xgbe_get_tx_tstamp; 3700 3701 /* For Data Center Bridging config */ 3702 hw_if->config_tc = xgbe_config_tc; 3703 hw_if->config_dcb_tc = xgbe_config_dcb_tc; 3704 hw_if->config_dcb_pfc = xgbe_config_dcb_pfc; 3705 3706 /* For Receive Side Scaling */ 3707 hw_if->enable_rss = xgbe_enable_rss; 3708 hw_if->disable_rss = xgbe_disable_rss; 3709 hw_if->set_rss_hash_key = xgbe_set_rss_hash_key; 3710 hw_if->set_rss_lookup_table = xgbe_set_rss_lookup_table; 3711 3712 /* For ECC */ 3713 hw_if->disable_ecc_ded = xgbe_disable_ecc_ded; 3714 hw_if->disable_ecc_sec = xgbe_disable_ecc_sec; 3715 3716 /* For VXLAN */ 3717 hw_if->enable_vxlan = xgbe_enable_vxlan; 3718 hw_if->disable_vxlan = xgbe_disable_vxlan; 3719 hw_if->set_vxlan_id = xgbe_set_vxlan_id; 3720 3721 /* For Split Header*/ 3722 hw_if->enable_sph = xgbe_config_sph_mode; 3723 hw_if->disable_sph = xgbe_disable_sph_mode; 3724 3725 DBGPR("<--xgbe_init_function_ptrs\n"); 3726 } 3727