1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) 2 /* 3 * Copyright (c) 2014-2025, Advanced Micro Devices, Inc. 4 * Copyright (c) 2014, Synopsys, Inc. 5 * All rights reserved 6 */ 7 8 #include <linux/phy.h> 9 #include <linux/mdio.h> 10 #include <linux/clk.h> 11 #include <linux/bitrev.h> 12 #include <linux/crc32.h> 13 #include <linux/crc32poly.h> 14 15 #include "xgbe.h" 16 #include "xgbe-common.h" 17 18 static inline unsigned int xgbe_get_max_frame(struct xgbe_prv_data *pdata) 19 { 20 return pdata->netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 21 } 22 23 static unsigned int xgbe_usec_to_riwt(struct xgbe_prv_data *pdata, 24 unsigned int usec) 25 { 26 unsigned long rate; 27 unsigned int ret; 28 29 DBGPR("-->xgbe_usec_to_riwt\n"); 30 31 rate = pdata->sysclk_rate; 32 33 /* 34 * Convert the input usec value to the watchdog timer value. Each 35 * watchdog timer value is equivalent to 256 clock cycles. 36 * Calculate the required value as: 37 * ( usec * ( system_clock_mhz / 10^6 ) / 256 38 */ 39 ret = (usec * (rate / 1000000)) / 256; 40 41 DBGPR("<--xgbe_usec_to_riwt\n"); 42 43 return ret; 44 } 45 46 static unsigned int xgbe_riwt_to_usec(struct xgbe_prv_data *pdata, 47 unsigned int riwt) 48 { 49 unsigned long rate; 50 unsigned int ret; 51 52 DBGPR("-->xgbe_riwt_to_usec\n"); 53 54 rate = pdata->sysclk_rate; 55 56 /* 57 * Convert the input watchdog timer value to the usec value. Each 58 * watchdog timer value is equivalent to 256 clock cycles. 59 * Calculate the required value as: 60 * ( riwt * 256 ) / ( system_clock_mhz / 10^6 ) 61 */ 62 ret = (riwt * 256) / (rate / 1000000); 63 64 DBGPR("<--xgbe_riwt_to_usec\n"); 65 66 return ret; 67 } 68 69 static int xgbe_config_pbl_val(struct xgbe_prv_data *pdata) 70 { 71 unsigned int pblx8, pbl; 72 unsigned int i; 73 74 pblx8 = DMA_PBL_X8_DISABLE; 75 pbl = pdata->pbl; 76 77 if (pdata->pbl > 32) { 78 pblx8 = DMA_PBL_X8_ENABLE; 79 pbl >>= 3; 80 } 81 82 for (i = 0; i < pdata->channel_count; i++) { 83 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, PBLX8, 84 pblx8); 85 86 if (pdata->channel[i]->tx_ring) 87 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, 88 PBL, pbl); 89 90 if (pdata->channel[i]->rx_ring) 91 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, 92 PBL, pbl); 93 } 94 95 return 0; 96 } 97 98 static int xgbe_config_osp_mode(struct xgbe_prv_data *pdata) 99 { 100 unsigned int i; 101 102 for (i = 0; i < pdata->channel_count; i++) { 103 if (!pdata->channel[i]->tx_ring) 104 break; 105 106 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, OSP, 107 pdata->tx_osp_mode); 108 } 109 110 return 0; 111 } 112 113 static int xgbe_config_rsf_mode(struct xgbe_prv_data *pdata, unsigned int val) 114 { 115 unsigned int i; 116 117 for (i = 0; i < pdata->rx_q_count; i++) 118 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RSF, val); 119 120 return 0; 121 } 122 123 static int xgbe_config_tsf_mode(struct xgbe_prv_data *pdata, unsigned int val) 124 { 125 unsigned int i; 126 127 for (i = 0; i < pdata->tx_q_count; i++) 128 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TSF, val); 129 130 return 0; 131 } 132 133 static int xgbe_config_rx_threshold(struct xgbe_prv_data *pdata, 134 unsigned int val) 135 { 136 unsigned int i; 137 138 for (i = 0; i < pdata->rx_q_count; i++) 139 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RTC, val); 140 141 return 0; 142 } 143 144 static int xgbe_config_tx_threshold(struct xgbe_prv_data *pdata, 145 unsigned int val) 146 { 147 unsigned int i; 148 149 for (i = 0; i < pdata->tx_q_count; i++) 150 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TTC, val); 151 152 return 0; 153 } 154 155 static int xgbe_config_rx_coalesce(struct xgbe_prv_data *pdata) 156 { 157 unsigned int i; 158 159 for (i = 0; i < pdata->channel_count; i++) { 160 if (!pdata->channel[i]->rx_ring) 161 break; 162 163 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RIWT, RWT, 164 pdata->rx_riwt); 165 } 166 167 return 0; 168 } 169 170 static int xgbe_config_tx_coalesce(struct xgbe_prv_data *pdata) 171 { 172 return 0; 173 } 174 175 static void xgbe_config_rx_buffer_size(struct xgbe_prv_data *pdata) 176 { 177 unsigned int i; 178 179 for (i = 0; i < pdata->channel_count; i++) { 180 if (!pdata->channel[i]->rx_ring) 181 break; 182 183 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, RBSZ, 184 pdata->rx_buf_size); 185 } 186 } 187 188 static void xgbe_config_tso_mode(struct xgbe_prv_data *pdata) 189 { 190 unsigned int i; 191 192 for (i = 0; i < pdata->channel_count; i++) { 193 if (!pdata->channel[i]->tx_ring) 194 break; 195 196 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, TSE, 1); 197 } 198 } 199 200 static void xgbe_config_sph_mode(struct xgbe_prv_data *pdata) 201 { 202 unsigned int i; 203 204 for (i = 0; i < pdata->channel_count; i++) { 205 if (!pdata->channel[i]->rx_ring) 206 break; 207 208 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, SPH, 1); 209 } 210 211 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, HDSMS, XGBE_SPH_HDSMS_SIZE); 212 } 213 214 static int xgbe_write_rss_reg(struct xgbe_prv_data *pdata, unsigned int type, 215 unsigned int index, unsigned int val) 216 { 217 unsigned int wait; 218 int ret = 0; 219 220 mutex_lock(&pdata->rss_mutex); 221 222 if (XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB)) { 223 ret = -EBUSY; 224 goto unlock; 225 } 226 227 XGMAC_IOWRITE(pdata, MAC_RSSDR, val); 228 229 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, RSSIA, index); 230 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, ADDRT, type); 231 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, CT, 0); 232 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, OB, 1); 233 234 wait = 1000; 235 while (wait--) { 236 if (!XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB)) 237 goto unlock; 238 239 usleep_range(1000, 1500); 240 } 241 242 ret = -EBUSY; 243 244 unlock: 245 mutex_unlock(&pdata->rss_mutex); 246 247 return ret; 248 } 249 250 static int xgbe_write_rss_hash_key(struct xgbe_prv_data *pdata) 251 { 252 unsigned int key_regs = sizeof(pdata->rss_key) / sizeof(u32); 253 unsigned int *key = (unsigned int *)&pdata->rss_key; 254 int ret; 255 256 while (key_regs--) { 257 ret = xgbe_write_rss_reg(pdata, XGBE_RSS_HASH_KEY_TYPE, 258 key_regs, *key++); 259 if (ret) 260 return ret; 261 } 262 263 return 0; 264 } 265 266 static int xgbe_write_rss_lookup_table(struct xgbe_prv_data *pdata) 267 { 268 unsigned int i; 269 int ret; 270 271 for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) { 272 ret = xgbe_write_rss_reg(pdata, 273 XGBE_RSS_LOOKUP_TABLE_TYPE, i, 274 pdata->rss_table[i]); 275 if (ret) 276 return ret; 277 } 278 279 return 0; 280 } 281 282 static int xgbe_set_rss_hash_key(struct xgbe_prv_data *pdata, const u8 *key) 283 { 284 memcpy(pdata->rss_key, key, sizeof(pdata->rss_key)); 285 286 return xgbe_write_rss_hash_key(pdata); 287 } 288 289 static int xgbe_set_rss_lookup_table(struct xgbe_prv_data *pdata, 290 const u32 *table) 291 { 292 unsigned int i; 293 294 for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) 295 XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH, table[i]); 296 297 return xgbe_write_rss_lookup_table(pdata); 298 } 299 300 static int xgbe_enable_rss(struct xgbe_prv_data *pdata) 301 { 302 int ret; 303 304 if (!pdata->hw_feat.rss) 305 return -EOPNOTSUPP; 306 307 /* Program the hash key */ 308 ret = xgbe_write_rss_hash_key(pdata); 309 if (ret) 310 return ret; 311 312 /* Program the lookup table */ 313 ret = xgbe_write_rss_lookup_table(pdata); 314 if (ret) 315 return ret; 316 317 /* Set the RSS options */ 318 XGMAC_IOWRITE(pdata, MAC_RSSCR, pdata->rss_options); 319 320 /* Enable RSS */ 321 XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 1); 322 323 return 0; 324 } 325 326 static int xgbe_disable_rss(struct xgbe_prv_data *pdata) 327 { 328 if (!pdata->hw_feat.rss) 329 return -EOPNOTSUPP; 330 331 XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 0); 332 333 return 0; 334 } 335 336 static void xgbe_config_rss(struct xgbe_prv_data *pdata) 337 { 338 int ret; 339 340 if (!pdata->hw_feat.rss) 341 return; 342 343 if (pdata->netdev->features & NETIF_F_RXHASH) 344 ret = xgbe_enable_rss(pdata); 345 else 346 ret = xgbe_disable_rss(pdata); 347 348 if (ret) 349 netdev_err(pdata->netdev, 350 "error configuring RSS, RSS disabled\n"); 351 } 352 353 static bool xgbe_is_pfc_queue(struct xgbe_prv_data *pdata, 354 unsigned int queue) 355 { 356 unsigned int prio, tc; 357 358 for (prio = 0; prio < IEEE_8021QAZ_MAX_TCS; prio++) { 359 /* Does this queue handle the priority? */ 360 if (pdata->prio2q_map[prio] != queue) 361 continue; 362 363 /* Get the Traffic Class for this priority */ 364 tc = pdata->ets->prio_tc[prio]; 365 366 /* Check if PFC is enabled for this traffic class */ 367 if (pdata->pfc->pfc_en & (1 << tc)) 368 return true; 369 } 370 371 return false; 372 } 373 374 static void xgbe_set_vxlan_id(struct xgbe_prv_data *pdata) 375 { 376 /* Program the VXLAN port */ 377 XGMAC_IOWRITE_BITS(pdata, MAC_TIR, TNID, pdata->vxlan_port); 378 379 netif_dbg(pdata, drv, pdata->netdev, "VXLAN tunnel id set to %hx\n", 380 pdata->vxlan_port); 381 } 382 383 static void xgbe_enable_vxlan(struct xgbe_prv_data *pdata) 384 { 385 if (!pdata->hw_feat.vxn) 386 return; 387 388 /* Program the VXLAN port */ 389 xgbe_set_vxlan_id(pdata); 390 391 /* Allow for IPv6/UDP zero-checksum VXLAN packets */ 392 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VUCC, 1); 393 394 /* Enable VXLAN tunneling mode */ 395 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, VNM, 0); 396 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, VNE, 1); 397 398 netif_dbg(pdata, drv, pdata->netdev, "VXLAN acceleration enabled\n"); 399 } 400 401 static void xgbe_disable_vxlan(struct xgbe_prv_data *pdata) 402 { 403 if (!pdata->hw_feat.vxn) 404 return; 405 406 /* Disable tunneling mode */ 407 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, VNE, 0); 408 409 /* Clear IPv6/UDP zero-checksum VXLAN packets setting */ 410 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VUCC, 0); 411 412 /* Clear the VXLAN port */ 413 XGMAC_IOWRITE_BITS(pdata, MAC_TIR, TNID, 0); 414 415 netif_dbg(pdata, drv, pdata->netdev, "VXLAN acceleration disabled\n"); 416 } 417 418 static unsigned int xgbe_get_fc_queue_count(struct xgbe_prv_data *pdata) 419 { 420 unsigned int max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES; 421 422 /* From MAC ver 30H the TFCR is per priority, instead of per queue */ 423 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) >= 0x30) 424 return max_q_count; 425 else 426 return min_t(unsigned int, pdata->tx_q_count, max_q_count); 427 } 428 429 static int xgbe_disable_tx_flow_control(struct xgbe_prv_data *pdata) 430 { 431 unsigned int reg, reg_val; 432 unsigned int i, q_count; 433 434 /* Clear MTL flow control */ 435 for (i = 0; i < pdata->rx_q_count; i++) 436 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 0); 437 438 /* Clear MAC flow control */ 439 q_count = xgbe_get_fc_queue_count(pdata); 440 reg = MAC_Q0TFCR; 441 for (i = 0; i < q_count; i++) { 442 reg_val = XGMAC_IOREAD(pdata, reg); 443 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 0); 444 XGMAC_IOWRITE(pdata, reg, reg_val); 445 446 reg += MAC_QTFCR_INC; 447 } 448 449 return 0; 450 } 451 452 static int xgbe_enable_tx_flow_control(struct xgbe_prv_data *pdata) 453 { 454 struct ieee_pfc *pfc = pdata->pfc; 455 struct ieee_ets *ets = pdata->ets; 456 unsigned int reg, reg_val; 457 unsigned int i, q_count; 458 459 /* Set MTL flow control */ 460 for (i = 0; i < pdata->rx_q_count; i++) { 461 unsigned int ehfc = 0; 462 463 if (pdata->rx_rfd[i]) { 464 /* Flow control thresholds are established */ 465 if (pfc && ets) { 466 if (xgbe_is_pfc_queue(pdata, i)) 467 ehfc = 1; 468 } else { 469 ehfc = 1; 470 } 471 } 472 473 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, ehfc); 474 475 netif_dbg(pdata, drv, pdata->netdev, 476 "flow control %s for RXq%u\n", 477 ehfc ? "enabled" : "disabled", i); 478 } 479 480 /* Set MAC flow control */ 481 q_count = xgbe_get_fc_queue_count(pdata); 482 reg = MAC_Q0TFCR; 483 for (i = 0; i < q_count; i++) { 484 reg_val = XGMAC_IOREAD(pdata, reg); 485 486 /* Enable transmit flow control */ 487 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 1); 488 /* Set pause time */ 489 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, PT, 0xffff); 490 491 XGMAC_IOWRITE(pdata, reg, reg_val); 492 493 reg += MAC_QTFCR_INC; 494 } 495 496 return 0; 497 } 498 499 static int xgbe_disable_rx_flow_control(struct xgbe_prv_data *pdata) 500 { 501 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 0); 502 503 return 0; 504 } 505 506 static int xgbe_enable_rx_flow_control(struct xgbe_prv_data *pdata) 507 { 508 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 1); 509 510 return 0; 511 } 512 513 static int xgbe_config_tx_flow_control(struct xgbe_prv_data *pdata) 514 { 515 struct ieee_pfc *pfc = pdata->pfc; 516 517 if (pdata->tx_pause || (pfc && pfc->pfc_en)) 518 xgbe_enable_tx_flow_control(pdata); 519 else 520 xgbe_disable_tx_flow_control(pdata); 521 522 return 0; 523 } 524 525 static int xgbe_config_rx_flow_control(struct xgbe_prv_data *pdata) 526 { 527 struct ieee_pfc *pfc = pdata->pfc; 528 529 if (pdata->rx_pause || (pfc && pfc->pfc_en)) 530 xgbe_enable_rx_flow_control(pdata); 531 else 532 xgbe_disable_rx_flow_control(pdata); 533 534 return 0; 535 } 536 537 static void xgbe_config_flow_control(struct xgbe_prv_data *pdata) 538 { 539 struct ieee_pfc *pfc = pdata->pfc; 540 541 xgbe_config_tx_flow_control(pdata); 542 xgbe_config_rx_flow_control(pdata); 543 544 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 545 (pfc && pfc->pfc_en) ? 1 : 0); 546 } 547 548 static void xgbe_enable_dma_interrupts(struct xgbe_prv_data *pdata) 549 { 550 struct xgbe_channel *channel; 551 unsigned int i, ver; 552 553 /* Set the interrupt mode if supported */ 554 if (pdata->channel_irq_mode) 555 XGMAC_IOWRITE_BITS(pdata, DMA_MR, INTM, 556 pdata->channel_irq_mode); 557 558 ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER); 559 560 for (i = 0; i < pdata->channel_count; i++) { 561 channel = pdata->channel[i]; 562 563 /* Clear all the interrupts which are set */ 564 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, 565 XGMAC_DMA_IOREAD(channel, DMA_CH_SR)); 566 567 /* Clear all interrupt enable bits */ 568 channel->curr_ier = 0; 569 570 /* Enable following interrupts 571 * NIE - Normal Interrupt Summary Enable 572 * AIE - Abnormal Interrupt Summary Enable 573 * FBEE - Fatal Bus Error Enable 574 */ 575 if (ver < 0x21) { 576 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, NIE20, 1); 577 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, AIE20, 1); 578 } else { 579 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, NIE, 1); 580 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, AIE, 1); 581 } 582 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, FBEE, 1); 583 584 if (channel->tx_ring) { 585 /* Enable the following Tx interrupts 586 * TIE - Transmit Interrupt Enable (unless using 587 * per channel interrupts in edge triggered 588 * mode) 589 */ 590 if (!pdata->per_channel_irq || pdata->channel_irq_mode) 591 XGMAC_SET_BITS(channel->curr_ier, 592 DMA_CH_IER, TIE, 1); 593 } 594 if (channel->rx_ring) { 595 /* Enable following Rx interrupts 596 * RBUE - Receive Buffer Unavailable Enable 597 * RIE - Receive Interrupt Enable (unless using 598 * per channel interrupts in edge triggered 599 * mode) 600 */ 601 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RBUE, 1); 602 if (!pdata->per_channel_irq || pdata->channel_irq_mode) 603 XGMAC_SET_BITS(channel->curr_ier, 604 DMA_CH_IER, RIE, 1); 605 } 606 607 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, channel->curr_ier); 608 } 609 } 610 611 static void xgbe_enable_mtl_interrupts(struct xgbe_prv_data *pdata) 612 { 613 unsigned int mtl_q_isr; 614 unsigned int q_count, i; 615 616 q_count = max(pdata->hw_feat.tx_q_cnt, pdata->hw_feat.rx_q_cnt); 617 for (i = 0; i < q_count; i++) { 618 /* Clear all the interrupts which are set */ 619 mtl_q_isr = XGMAC_MTL_IOREAD(pdata, i, MTL_Q_ISR); 620 XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_ISR, mtl_q_isr); 621 622 /* No MTL interrupts to be enabled */ 623 XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_IER, 0); 624 } 625 } 626 627 static void xgbe_enable_mac_interrupts(struct xgbe_prv_data *pdata) 628 { 629 unsigned int mac_ier = 0; 630 631 /* Enable Timestamp interrupt */ 632 XGMAC_SET_BITS(mac_ier, MAC_IER, TSIE, 1); 633 634 XGMAC_IOWRITE(pdata, MAC_IER, mac_ier); 635 636 /* Enable all counter interrupts */ 637 XGMAC_IOWRITE_BITS(pdata, MMC_RIER, ALL_INTERRUPTS, 0xffffffff); 638 XGMAC_IOWRITE_BITS(pdata, MMC_TIER, ALL_INTERRUPTS, 0xffffffff); 639 640 /* Enable MDIO single command completion interrupt */ 641 XGMAC_IOWRITE_BITS(pdata, MAC_MDIOIER, SNGLCOMPIE, 1); 642 } 643 644 static void xgbe_enable_ecc_interrupts(struct xgbe_prv_data *pdata) 645 { 646 unsigned int ecc_isr, ecc_ier = 0; 647 648 if (!pdata->vdata->ecc_support) 649 return; 650 651 /* Clear all the interrupts which are set */ 652 ecc_isr = XP_IOREAD(pdata, XP_ECC_ISR); 653 XP_IOWRITE(pdata, XP_ECC_ISR, ecc_isr); 654 655 /* Enable ECC interrupts */ 656 XP_SET_BITS(ecc_ier, XP_ECC_IER, TX_DED, 1); 657 XP_SET_BITS(ecc_ier, XP_ECC_IER, TX_SEC, 1); 658 XP_SET_BITS(ecc_ier, XP_ECC_IER, RX_DED, 1); 659 XP_SET_BITS(ecc_ier, XP_ECC_IER, RX_SEC, 1); 660 XP_SET_BITS(ecc_ier, XP_ECC_IER, DESC_DED, 1); 661 XP_SET_BITS(ecc_ier, XP_ECC_IER, DESC_SEC, 1); 662 663 XP_IOWRITE(pdata, XP_ECC_IER, ecc_ier); 664 } 665 666 static void xgbe_disable_ecc_ded(struct xgbe_prv_data *pdata) 667 { 668 unsigned int ecc_ier; 669 670 ecc_ier = XP_IOREAD(pdata, XP_ECC_IER); 671 672 /* Disable ECC DED interrupts */ 673 XP_SET_BITS(ecc_ier, XP_ECC_IER, TX_DED, 0); 674 XP_SET_BITS(ecc_ier, XP_ECC_IER, RX_DED, 0); 675 XP_SET_BITS(ecc_ier, XP_ECC_IER, DESC_DED, 0); 676 677 XP_IOWRITE(pdata, XP_ECC_IER, ecc_ier); 678 } 679 680 static void xgbe_disable_ecc_sec(struct xgbe_prv_data *pdata, 681 enum xgbe_ecc_sec sec) 682 { 683 unsigned int ecc_ier; 684 685 ecc_ier = XP_IOREAD(pdata, XP_ECC_IER); 686 687 /* Disable ECC SEC interrupt */ 688 switch (sec) { 689 case XGBE_ECC_SEC_TX: 690 XP_SET_BITS(ecc_ier, XP_ECC_IER, TX_SEC, 0); 691 break; 692 case XGBE_ECC_SEC_RX: 693 XP_SET_BITS(ecc_ier, XP_ECC_IER, RX_SEC, 0); 694 break; 695 case XGBE_ECC_SEC_DESC: 696 XP_SET_BITS(ecc_ier, XP_ECC_IER, DESC_SEC, 0); 697 break; 698 } 699 700 XP_IOWRITE(pdata, XP_ECC_IER, ecc_ier); 701 } 702 703 static int xgbe_set_speed(struct xgbe_prv_data *pdata, int speed) 704 { 705 unsigned int ss; 706 707 switch (speed) { 708 case SPEED_10: 709 ss = 0x07; 710 break; 711 case SPEED_1000: 712 ss = 0x03; 713 break; 714 case SPEED_2500: 715 ss = 0x02; 716 break; 717 case SPEED_10000: 718 ss = 0x00; 719 break; 720 default: 721 return -EINVAL; 722 } 723 724 if (XGMAC_IOREAD_BITS(pdata, MAC_TCR, SS) != ss) 725 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, ss); 726 727 return 0; 728 } 729 730 static int xgbe_enable_rx_vlan_stripping(struct xgbe_prv_data *pdata) 731 { 732 /* Put the VLAN tag in the Rx descriptor */ 733 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLRXS, 1); 734 735 /* Don't check the VLAN type */ 736 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, DOVLTC, 1); 737 738 /* Check only C-TAG (0x8100) packets */ 739 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ERSVLM, 0); 740 741 /* Don't consider an S-TAG (0x88A8) packet as a VLAN packet */ 742 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ESVL, 0); 743 744 /* Enable VLAN tag stripping */ 745 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0x3); 746 747 return 0; 748 } 749 750 static int xgbe_disable_rx_vlan_stripping(struct xgbe_prv_data *pdata) 751 { 752 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0); 753 754 return 0; 755 } 756 757 static int xgbe_enable_rx_vlan_filtering(struct xgbe_prv_data *pdata) 758 { 759 /* Enable VLAN filtering */ 760 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 1); 761 762 /* Enable VLAN Hash Table filtering */ 763 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTHM, 1); 764 765 /* Disable VLAN tag inverse matching */ 766 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTIM, 0); 767 768 /* Only filter on the lower 12-bits of the VLAN tag */ 769 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ETV, 1); 770 771 /* In order for the VLAN Hash Table filtering to be effective, 772 * the VLAN tag identifier in the VLAN Tag Register must not 773 * be zero. Set the VLAN tag identifier to "1" to enable the 774 * VLAN Hash Table filtering. This implies that a VLAN tag of 775 * 1 will always pass filtering. 776 */ 777 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VL, 1); 778 779 return 0; 780 } 781 782 static int xgbe_disable_rx_vlan_filtering(struct xgbe_prv_data *pdata) 783 { 784 /* Disable VLAN filtering */ 785 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 0); 786 787 return 0; 788 } 789 790 static u32 xgbe_vid_crc32_le(__le16 vid_le) 791 { 792 u32 crc = ~0; 793 u32 temp = 0; 794 unsigned char *data = (unsigned char *)&vid_le; 795 unsigned char data_byte = 0; 796 int i, bits; 797 798 bits = get_bitmask_order(VLAN_VID_MASK); 799 for (i = 0; i < bits; i++) { 800 if ((i % 8) == 0) 801 data_byte = data[i / 8]; 802 803 temp = ((crc & 1) ^ data_byte) & 1; 804 crc >>= 1; 805 data_byte >>= 1; 806 807 if (temp) 808 crc ^= CRC32_POLY_LE; 809 } 810 811 return crc; 812 } 813 814 static int xgbe_update_vlan_hash_table(struct xgbe_prv_data *pdata) 815 { 816 u32 crc; 817 u16 vid; 818 __le16 vid_le; 819 u16 vlan_hash_table = 0; 820 821 /* Generate the VLAN Hash Table value */ 822 for_each_set_bit(vid, pdata->active_vlans, VLAN_N_VID) { 823 /* Get the CRC32 value of the VLAN ID */ 824 vid_le = cpu_to_le16(vid); 825 crc = bitrev32(~xgbe_vid_crc32_le(vid_le)) >> 28; 826 827 vlan_hash_table |= (1 << crc); 828 } 829 830 /* Set the VLAN Hash Table filtering register */ 831 XGMAC_IOWRITE_BITS(pdata, MAC_VLANHTR, VLHT, vlan_hash_table); 832 833 return 0; 834 } 835 836 static int xgbe_set_promiscuous_mode(struct xgbe_prv_data *pdata, 837 unsigned int enable) 838 { 839 unsigned int val = enable ? 1 : 0; 840 841 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PR) == val) 842 return 0; 843 844 netif_dbg(pdata, drv, pdata->netdev, "%s promiscuous mode\n", 845 enable ? "entering" : "leaving"); 846 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, val); 847 848 /* Hardware will still perform VLAN filtering in promiscuous mode */ 849 if (enable) { 850 xgbe_disable_rx_vlan_filtering(pdata); 851 } else { 852 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER) 853 xgbe_enable_rx_vlan_filtering(pdata); 854 } 855 856 return 0; 857 } 858 859 static int xgbe_set_all_multicast_mode(struct xgbe_prv_data *pdata, 860 unsigned int enable) 861 { 862 unsigned int val = enable ? 1 : 0; 863 864 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PM) == val) 865 return 0; 866 867 netif_dbg(pdata, drv, pdata->netdev, "%s allmulti mode\n", 868 enable ? "entering" : "leaving"); 869 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, val); 870 871 return 0; 872 } 873 874 static void xgbe_set_mac_reg(struct xgbe_prv_data *pdata, 875 struct netdev_hw_addr *ha, unsigned int *mac_reg) 876 { 877 unsigned int mac_addr_hi, mac_addr_lo; 878 u8 *mac_addr; 879 880 mac_addr_lo = 0; 881 mac_addr_hi = 0; 882 883 if (ha) { 884 mac_addr = (u8 *)&mac_addr_lo; 885 mac_addr[0] = ha->addr[0]; 886 mac_addr[1] = ha->addr[1]; 887 mac_addr[2] = ha->addr[2]; 888 mac_addr[3] = ha->addr[3]; 889 mac_addr = (u8 *)&mac_addr_hi; 890 mac_addr[0] = ha->addr[4]; 891 mac_addr[1] = ha->addr[5]; 892 893 netif_dbg(pdata, drv, pdata->netdev, 894 "adding mac address %pM at %#x\n", 895 ha->addr, *mac_reg); 896 897 XGMAC_SET_BITS(mac_addr_hi, MAC_MACA1HR, AE, 1); 898 } 899 900 XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_hi); 901 *mac_reg += MAC_MACA_INC; 902 XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_lo); 903 *mac_reg += MAC_MACA_INC; 904 } 905 906 static void xgbe_set_mac_addn_addrs(struct xgbe_prv_data *pdata) 907 { 908 struct net_device *netdev = pdata->netdev; 909 struct netdev_hw_addr *ha; 910 unsigned int mac_reg; 911 unsigned int addn_macs; 912 913 mac_reg = MAC_MACA1HR; 914 addn_macs = pdata->hw_feat.addn_mac; 915 916 if (netdev_uc_count(netdev) > addn_macs) { 917 xgbe_set_promiscuous_mode(pdata, 1); 918 } else { 919 netdev_for_each_uc_addr(ha, netdev) { 920 xgbe_set_mac_reg(pdata, ha, &mac_reg); 921 addn_macs--; 922 } 923 924 if (netdev_mc_count(netdev) > addn_macs) { 925 xgbe_set_all_multicast_mode(pdata, 1); 926 } else { 927 netdev_for_each_mc_addr(ha, netdev) { 928 xgbe_set_mac_reg(pdata, ha, &mac_reg); 929 addn_macs--; 930 } 931 } 932 } 933 934 /* Clear remaining additional MAC address entries */ 935 while (addn_macs--) 936 xgbe_set_mac_reg(pdata, NULL, &mac_reg); 937 } 938 939 static void xgbe_set_mac_hash_table(struct xgbe_prv_data *pdata) 940 { 941 struct net_device *netdev = pdata->netdev; 942 struct netdev_hw_addr *ha; 943 unsigned int hash_reg; 944 unsigned int hash_table_shift, hash_table_count; 945 u32 hash_table[XGBE_MAC_HASH_TABLE_SIZE]; 946 u32 crc; 947 unsigned int i; 948 949 hash_table_shift = 26 - (pdata->hw_feat.hash_table_size >> 7); 950 hash_table_count = pdata->hw_feat.hash_table_size / 32; 951 memset(hash_table, 0, sizeof(hash_table)); 952 953 /* Build the MAC Hash Table register values */ 954 netdev_for_each_uc_addr(ha, netdev) { 955 crc = bitrev32(~crc32_le(~0, ha->addr, ETH_ALEN)); 956 crc >>= hash_table_shift; 957 hash_table[crc >> 5] |= (1 << (crc & 0x1f)); 958 } 959 960 netdev_for_each_mc_addr(ha, netdev) { 961 crc = bitrev32(~crc32_le(~0, ha->addr, ETH_ALEN)); 962 crc >>= hash_table_shift; 963 hash_table[crc >> 5] |= (1 << (crc & 0x1f)); 964 } 965 966 /* Set the MAC Hash Table registers */ 967 hash_reg = MAC_HTR0; 968 for (i = 0; i < hash_table_count; i++) { 969 XGMAC_IOWRITE(pdata, hash_reg, hash_table[i]); 970 hash_reg += MAC_HTR_INC; 971 } 972 } 973 974 static int xgbe_add_mac_addresses(struct xgbe_prv_data *pdata) 975 { 976 if (pdata->hw_feat.hash_table_size) 977 xgbe_set_mac_hash_table(pdata); 978 else 979 xgbe_set_mac_addn_addrs(pdata); 980 981 return 0; 982 } 983 984 static int xgbe_set_mac_address(struct xgbe_prv_data *pdata, const u8 *addr) 985 { 986 unsigned int mac_addr_hi, mac_addr_lo; 987 988 mac_addr_hi = (addr[5] << 8) | (addr[4] << 0); 989 mac_addr_lo = (addr[3] << 24) | (addr[2] << 16) | 990 (addr[1] << 8) | (addr[0] << 0); 991 992 XGMAC_IOWRITE(pdata, MAC_MACA0HR, mac_addr_hi); 993 XGMAC_IOWRITE(pdata, MAC_MACA0LR, mac_addr_lo); 994 995 return 0; 996 } 997 998 static int xgbe_config_rx_mode(struct xgbe_prv_data *pdata) 999 { 1000 struct net_device *netdev = pdata->netdev; 1001 unsigned int pr_mode, am_mode; 1002 1003 pr_mode = ((netdev->flags & IFF_PROMISC) != 0); 1004 am_mode = ((netdev->flags & IFF_ALLMULTI) != 0); 1005 1006 xgbe_set_promiscuous_mode(pdata, pr_mode); 1007 xgbe_set_all_multicast_mode(pdata, am_mode); 1008 1009 xgbe_add_mac_addresses(pdata); 1010 1011 return 0; 1012 } 1013 1014 static int xgbe_clr_gpio(struct xgbe_prv_data *pdata, unsigned int gpio) 1015 { 1016 unsigned int reg; 1017 1018 if (gpio > 15) 1019 return -EINVAL; 1020 1021 reg = XGMAC_IOREAD(pdata, MAC_GPIOSR); 1022 1023 reg &= ~(1 << (gpio + 16)); 1024 XGMAC_IOWRITE(pdata, MAC_GPIOSR, reg); 1025 1026 return 0; 1027 } 1028 1029 static int xgbe_set_gpio(struct xgbe_prv_data *pdata, unsigned int gpio) 1030 { 1031 unsigned int reg; 1032 1033 if (gpio > 15) 1034 return -EINVAL; 1035 1036 reg = XGMAC_IOREAD(pdata, MAC_GPIOSR); 1037 1038 reg |= (1 << (gpio + 16)); 1039 XGMAC_IOWRITE(pdata, MAC_GPIOSR, reg); 1040 1041 return 0; 1042 } 1043 1044 static int xgbe_read_mmd_regs_v2(struct xgbe_prv_data *pdata, int prtad, 1045 int mmd_reg) 1046 { 1047 unsigned long flags; 1048 unsigned int mmd_address, index, offset; 1049 int mmd_data; 1050 1051 if (mmd_reg & XGBE_ADDR_C45) 1052 mmd_address = mmd_reg & ~XGBE_ADDR_C45; 1053 else 1054 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); 1055 1056 /* The PCS registers are accessed using mmio. The underlying 1057 * management interface uses indirect addressing to access the MMD 1058 * register sets. This requires accessing of the PCS register in two 1059 * phases, an address phase and a data phase. 1060 * 1061 * The mmio interface is based on 16-bit offsets and values. All 1062 * register offsets must therefore be adjusted by left shifting the 1063 * offset 1 bit and reading 16 bits of data. 1064 */ 1065 mmd_address <<= 1; 1066 index = mmd_address & ~pdata->xpcs_window_mask; 1067 offset = pdata->xpcs_window + (mmd_address & pdata->xpcs_window_mask); 1068 1069 spin_lock_irqsave(&pdata->xpcs_lock, flags); 1070 XPCS32_IOWRITE(pdata, pdata->xpcs_window_sel_reg, index); 1071 mmd_data = XPCS16_IOREAD(pdata, offset); 1072 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); 1073 1074 return mmd_data; 1075 } 1076 1077 static void xgbe_write_mmd_regs_v2(struct xgbe_prv_data *pdata, int prtad, 1078 int mmd_reg, int mmd_data) 1079 { 1080 unsigned long flags; 1081 unsigned int mmd_address, index, offset; 1082 1083 if (mmd_reg & XGBE_ADDR_C45) 1084 mmd_address = mmd_reg & ~XGBE_ADDR_C45; 1085 else 1086 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); 1087 1088 /* The PCS registers are accessed using mmio. The underlying 1089 * management interface uses indirect addressing to access the MMD 1090 * register sets. This requires accessing of the PCS register in two 1091 * phases, an address phase and a data phase. 1092 * 1093 * The mmio interface is based on 16-bit offsets and values. All 1094 * register offsets must therefore be adjusted by left shifting the 1095 * offset 1 bit and writing 16 bits of data. 1096 */ 1097 mmd_address <<= 1; 1098 index = mmd_address & ~pdata->xpcs_window_mask; 1099 offset = pdata->xpcs_window + (mmd_address & pdata->xpcs_window_mask); 1100 1101 spin_lock_irqsave(&pdata->xpcs_lock, flags); 1102 XPCS32_IOWRITE(pdata, pdata->xpcs_window_sel_reg, index); 1103 XPCS16_IOWRITE(pdata, offset, mmd_data); 1104 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); 1105 } 1106 1107 static int xgbe_read_mmd_regs_v1(struct xgbe_prv_data *pdata, int prtad, 1108 int mmd_reg) 1109 { 1110 unsigned long flags; 1111 unsigned int mmd_address; 1112 int mmd_data; 1113 1114 if (mmd_reg & XGBE_ADDR_C45) 1115 mmd_address = mmd_reg & ~XGBE_ADDR_C45; 1116 else 1117 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); 1118 1119 /* The PCS registers are accessed using mmio. The underlying APB3 1120 * management interface uses indirect addressing to access the MMD 1121 * register sets. This requires accessing of the PCS register in two 1122 * phases, an address phase and a data phase. 1123 * 1124 * The mmio interface is based on 32-bit offsets and values. All 1125 * register offsets must therefore be adjusted by left shifting the 1126 * offset 2 bits and reading 32 bits of data. 1127 */ 1128 spin_lock_irqsave(&pdata->xpcs_lock, flags); 1129 XPCS32_IOWRITE(pdata, PCS_V1_WINDOW_SELECT, mmd_address >> 8); 1130 mmd_data = XPCS32_IOREAD(pdata, (mmd_address & 0xff) << 2); 1131 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); 1132 1133 return mmd_data; 1134 } 1135 1136 static void xgbe_write_mmd_regs_v1(struct xgbe_prv_data *pdata, int prtad, 1137 int mmd_reg, int mmd_data) 1138 { 1139 unsigned int mmd_address; 1140 unsigned long flags; 1141 1142 if (mmd_reg & XGBE_ADDR_C45) 1143 mmd_address = mmd_reg & ~XGBE_ADDR_C45; 1144 else 1145 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); 1146 1147 /* The PCS registers are accessed using mmio. The underlying APB3 1148 * management interface uses indirect addressing to access the MMD 1149 * register sets. This requires accessing of the PCS register in two 1150 * phases, an address phase and a data phase. 1151 * 1152 * The mmio interface is based on 32-bit offsets and values. All 1153 * register offsets must therefore be adjusted by left shifting the 1154 * offset 2 bits and writing 32 bits of data. 1155 */ 1156 spin_lock_irqsave(&pdata->xpcs_lock, flags); 1157 XPCS32_IOWRITE(pdata, PCS_V1_WINDOW_SELECT, mmd_address >> 8); 1158 XPCS32_IOWRITE(pdata, (mmd_address & 0xff) << 2, mmd_data); 1159 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); 1160 } 1161 1162 static int xgbe_read_mmd_regs(struct xgbe_prv_data *pdata, int prtad, 1163 int mmd_reg) 1164 { 1165 switch (pdata->vdata->xpcs_access) { 1166 case XGBE_XPCS_ACCESS_V1: 1167 return xgbe_read_mmd_regs_v1(pdata, prtad, mmd_reg); 1168 1169 case XGBE_XPCS_ACCESS_V2: 1170 default: 1171 return xgbe_read_mmd_regs_v2(pdata, prtad, mmd_reg); 1172 } 1173 } 1174 1175 static void xgbe_write_mmd_regs(struct xgbe_prv_data *pdata, int prtad, 1176 int mmd_reg, int mmd_data) 1177 { 1178 switch (pdata->vdata->xpcs_access) { 1179 case XGBE_XPCS_ACCESS_V1: 1180 return xgbe_write_mmd_regs_v1(pdata, prtad, mmd_reg, mmd_data); 1181 1182 case XGBE_XPCS_ACCESS_V2: 1183 default: 1184 return xgbe_write_mmd_regs_v2(pdata, prtad, mmd_reg, mmd_data); 1185 } 1186 } 1187 1188 static unsigned int xgbe_create_mdio_sca_c22(int port, int reg) 1189 { 1190 unsigned int mdio_sca; 1191 1192 mdio_sca = 0; 1193 XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, RA, reg); 1194 XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, PA, port); 1195 1196 return mdio_sca; 1197 } 1198 1199 static unsigned int xgbe_create_mdio_sca_c45(int port, unsigned int da, int reg) 1200 { 1201 unsigned int mdio_sca; 1202 1203 mdio_sca = 0; 1204 XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, RA, reg); 1205 XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, PA, port); 1206 XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, DA, da); 1207 1208 return mdio_sca; 1209 } 1210 1211 static int xgbe_write_ext_mii_regs(struct xgbe_prv_data *pdata, 1212 unsigned int mdio_sca, u16 val) 1213 { 1214 unsigned int mdio_sccd; 1215 1216 reinit_completion(&pdata->mdio_complete); 1217 1218 XGMAC_IOWRITE(pdata, MAC_MDIOSCAR, mdio_sca); 1219 1220 mdio_sccd = 0; 1221 XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, DATA, val); 1222 XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, CMD, 1); 1223 XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, BUSY, 1); 1224 XGMAC_IOWRITE(pdata, MAC_MDIOSCCDR, mdio_sccd); 1225 1226 if (!wait_for_completion_timeout(&pdata->mdio_complete, HZ)) { 1227 netdev_err(pdata->netdev, "mdio write operation timed out\n"); 1228 return -ETIMEDOUT; 1229 } 1230 1231 return 0; 1232 } 1233 1234 static int xgbe_write_ext_mii_regs_c22(struct xgbe_prv_data *pdata, int addr, 1235 int reg, u16 val) 1236 { 1237 unsigned int mdio_sca; 1238 1239 mdio_sca = xgbe_create_mdio_sca_c22(addr, reg); 1240 1241 return xgbe_write_ext_mii_regs(pdata, mdio_sca, val); 1242 } 1243 1244 static int xgbe_write_ext_mii_regs_c45(struct xgbe_prv_data *pdata, int addr, 1245 int devad, int reg, u16 val) 1246 { 1247 unsigned int mdio_sca; 1248 1249 mdio_sca = xgbe_create_mdio_sca_c45(addr, devad, reg); 1250 1251 return xgbe_write_ext_mii_regs(pdata, mdio_sca, val); 1252 } 1253 1254 static int xgbe_read_ext_mii_regs(struct xgbe_prv_data *pdata, 1255 unsigned int mdio_sca) 1256 { 1257 unsigned int mdio_sccd; 1258 1259 reinit_completion(&pdata->mdio_complete); 1260 1261 XGMAC_IOWRITE(pdata, MAC_MDIOSCAR, mdio_sca); 1262 1263 mdio_sccd = 0; 1264 XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, CMD, 3); 1265 XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, BUSY, 1); 1266 XGMAC_IOWRITE(pdata, MAC_MDIOSCCDR, mdio_sccd); 1267 1268 if (!wait_for_completion_timeout(&pdata->mdio_complete, HZ)) { 1269 netdev_err(pdata->netdev, "mdio read operation timed out\n"); 1270 return -ETIMEDOUT; 1271 } 1272 1273 return XGMAC_IOREAD_BITS(pdata, MAC_MDIOSCCDR, DATA); 1274 } 1275 1276 static int xgbe_read_ext_mii_regs_c22(struct xgbe_prv_data *pdata, int addr, 1277 int reg) 1278 { 1279 unsigned int mdio_sca; 1280 1281 mdio_sca = xgbe_create_mdio_sca_c22(addr, reg); 1282 1283 return xgbe_read_ext_mii_regs(pdata, mdio_sca); 1284 } 1285 1286 static int xgbe_read_ext_mii_regs_c45(struct xgbe_prv_data *pdata, int addr, 1287 int devad, int reg) 1288 { 1289 unsigned int mdio_sca; 1290 1291 mdio_sca = xgbe_create_mdio_sca_c45(addr, devad, reg); 1292 1293 return xgbe_read_ext_mii_regs(pdata, mdio_sca); 1294 } 1295 1296 static int xgbe_set_ext_mii_mode(struct xgbe_prv_data *pdata, unsigned int port, 1297 enum xgbe_mdio_mode mode) 1298 { 1299 unsigned int reg_val = XGMAC_IOREAD(pdata, MAC_MDIOCL22R); 1300 1301 switch (mode) { 1302 case XGBE_MDIO_MODE_CL22: 1303 if (port > XGMAC_MAX_C22_PORT) 1304 return -EINVAL; 1305 reg_val |= (1 << port); 1306 break; 1307 case XGBE_MDIO_MODE_CL45: 1308 break; 1309 default: 1310 return -EINVAL; 1311 } 1312 1313 XGMAC_IOWRITE(pdata, MAC_MDIOCL22R, reg_val); 1314 1315 return 0; 1316 } 1317 1318 static int xgbe_tx_complete(struct xgbe_ring_desc *rdesc) 1319 { 1320 return !XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN); 1321 } 1322 1323 static int xgbe_disable_rx_csum(struct xgbe_prv_data *pdata) 1324 { 1325 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 0); 1326 1327 return 0; 1328 } 1329 1330 static int xgbe_enable_rx_csum(struct xgbe_prv_data *pdata) 1331 { 1332 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 1); 1333 1334 return 0; 1335 } 1336 1337 static void xgbe_tx_desc_reset(struct xgbe_ring_data *rdata) 1338 { 1339 struct xgbe_ring_desc *rdesc = rdata->rdesc; 1340 1341 /* Reset the Tx descriptor 1342 * Set buffer 1 (lo) address to zero 1343 * Set buffer 1 (hi) address to zero 1344 * Reset all other control bits (IC, TTSE, B2L & B1L) 1345 * Reset all other control bits (OWN, CTXT, FD, LD, CPC, CIC, etc) 1346 */ 1347 rdesc->desc0 = 0; 1348 rdesc->desc1 = 0; 1349 rdesc->desc2 = 0; 1350 rdesc->desc3 = 0; 1351 1352 /* Make sure ownership is written to the descriptor */ 1353 dma_wmb(); 1354 } 1355 1356 static void xgbe_tx_desc_init(struct xgbe_channel *channel) 1357 { 1358 struct xgbe_ring *ring = channel->tx_ring; 1359 struct xgbe_ring_data *rdata; 1360 int i; 1361 int start_index = ring->cur; 1362 1363 DBGPR("-->tx_desc_init\n"); 1364 1365 /* Initialze all descriptors */ 1366 for (i = 0; i < ring->rdesc_count; i++) { 1367 rdata = XGBE_GET_DESC_DATA(ring, i); 1368 1369 /* Initialize Tx descriptor */ 1370 xgbe_tx_desc_reset(rdata); 1371 } 1372 1373 /* Update the total number of Tx descriptors */ 1374 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDRLR, ring->rdesc_count - 1); 1375 1376 /* Update the starting address of descriptor ring */ 1377 rdata = XGBE_GET_DESC_DATA(ring, start_index); 1378 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_HI, 1379 upper_32_bits(rdata->rdesc_dma)); 1380 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_LO, 1381 lower_32_bits(rdata->rdesc_dma)); 1382 1383 DBGPR("<--tx_desc_init\n"); 1384 } 1385 1386 static void xgbe_rx_desc_reset(struct xgbe_prv_data *pdata, 1387 struct xgbe_ring_data *rdata, unsigned int index) 1388 { 1389 struct xgbe_ring_desc *rdesc = rdata->rdesc; 1390 unsigned int rx_usecs = pdata->rx_usecs; 1391 unsigned int rx_frames = pdata->rx_frames; 1392 unsigned int inte; 1393 dma_addr_t hdr_dma, buf_dma; 1394 1395 if (!rx_usecs && !rx_frames) { 1396 /* No coalescing, interrupt for every descriptor */ 1397 inte = 1; 1398 } else { 1399 /* Set interrupt based on Rx frame coalescing setting */ 1400 if (rx_frames && !((index + 1) % rx_frames)) 1401 inte = 1; 1402 else 1403 inte = 0; 1404 } 1405 1406 /* Reset the Rx descriptor 1407 * Set buffer 1 (lo) address to header dma address (lo) 1408 * Set buffer 1 (hi) address to header dma address (hi) 1409 * Set buffer 2 (lo) address to buffer dma address (lo) 1410 * Set buffer 2 (hi) address to buffer dma address (hi) and 1411 * set control bits OWN and INTE 1412 */ 1413 hdr_dma = rdata->rx.hdr.dma_base + rdata->rx.hdr.dma_off; 1414 buf_dma = rdata->rx.buf.dma_base + rdata->rx.buf.dma_off; 1415 rdesc->desc0 = cpu_to_le32(lower_32_bits(hdr_dma)); 1416 rdesc->desc1 = cpu_to_le32(upper_32_bits(hdr_dma)); 1417 rdesc->desc2 = cpu_to_le32(lower_32_bits(buf_dma)); 1418 rdesc->desc3 = cpu_to_le32(upper_32_bits(buf_dma)); 1419 1420 XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, INTE, inte); 1421 1422 /* Since the Rx DMA engine is likely running, make sure everything 1423 * is written to the descriptor(s) before setting the OWN bit 1424 * for the descriptor 1425 */ 1426 dma_wmb(); 1427 1428 XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN, 1); 1429 1430 /* Make sure ownership is written to the descriptor */ 1431 dma_wmb(); 1432 } 1433 1434 static void xgbe_rx_desc_init(struct xgbe_channel *channel) 1435 { 1436 struct xgbe_prv_data *pdata = channel->pdata; 1437 struct xgbe_ring *ring = channel->rx_ring; 1438 struct xgbe_ring_data *rdata; 1439 unsigned int start_index = ring->cur; 1440 unsigned int i; 1441 1442 DBGPR("-->rx_desc_init\n"); 1443 1444 /* Initialize all descriptors */ 1445 for (i = 0; i < ring->rdesc_count; i++) { 1446 rdata = XGBE_GET_DESC_DATA(ring, i); 1447 1448 /* Initialize Rx descriptor */ 1449 xgbe_rx_desc_reset(pdata, rdata, i); 1450 } 1451 1452 /* Update the total number of Rx descriptors */ 1453 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDRLR, ring->rdesc_count - 1); 1454 1455 /* Update the starting address of descriptor ring */ 1456 rdata = XGBE_GET_DESC_DATA(ring, start_index); 1457 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_HI, 1458 upper_32_bits(rdata->rdesc_dma)); 1459 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_LO, 1460 lower_32_bits(rdata->rdesc_dma)); 1461 1462 /* Update the Rx Descriptor Tail Pointer */ 1463 rdata = XGBE_GET_DESC_DATA(ring, start_index + ring->rdesc_count - 1); 1464 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO, 1465 lower_32_bits(rdata->rdesc_dma)); 1466 1467 DBGPR("<--rx_desc_init\n"); 1468 } 1469 1470 static void xgbe_update_tstamp_addend(struct xgbe_prv_data *pdata, 1471 unsigned int addend) 1472 { 1473 unsigned int count = 10000; 1474 1475 /* Set the addend register value and tell the device */ 1476 XGMAC_IOWRITE(pdata, MAC_TSAR, addend); 1477 XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 1); 1478 1479 /* Wait for addend update to complete */ 1480 while (--count && XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSADDREG)) 1481 udelay(5); 1482 1483 if (!count) 1484 netdev_err(pdata->netdev, 1485 "timed out updating timestamp addend register\n"); 1486 } 1487 1488 static void xgbe_set_tstamp_time(struct xgbe_prv_data *pdata, unsigned int sec, 1489 unsigned int nsec) 1490 { 1491 unsigned int count = 10000; 1492 1493 /* Set the time values and tell the device */ 1494 XGMAC_IOWRITE(pdata, MAC_STSUR, sec); 1495 XGMAC_IOWRITE(pdata, MAC_STNUR, nsec); 1496 XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSINIT, 1); 1497 1498 /* Wait for time update to complete */ 1499 while (--count && XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSINIT)) 1500 udelay(5); 1501 1502 if (!count) 1503 netdev_err(pdata->netdev, "timed out initializing timestamp\n"); 1504 } 1505 1506 static u64 xgbe_get_tstamp_time(struct xgbe_prv_data *pdata) 1507 { 1508 u64 nsec; 1509 1510 nsec = XGMAC_IOREAD(pdata, MAC_STSR); 1511 nsec *= NSEC_PER_SEC; 1512 nsec += XGMAC_IOREAD(pdata, MAC_STNR); 1513 1514 return nsec; 1515 } 1516 1517 static u64 xgbe_get_tx_tstamp(struct xgbe_prv_data *pdata) 1518 { 1519 unsigned int tx_snr, tx_ssr; 1520 u64 nsec; 1521 1522 if (pdata->vdata->tx_tstamp_workaround) { 1523 tx_snr = XGMAC_IOREAD(pdata, MAC_TXSNR); 1524 tx_ssr = XGMAC_IOREAD(pdata, MAC_TXSSR); 1525 } else { 1526 tx_ssr = XGMAC_IOREAD(pdata, MAC_TXSSR); 1527 tx_snr = XGMAC_IOREAD(pdata, MAC_TXSNR); 1528 } 1529 1530 if (XGMAC_GET_BITS(tx_snr, MAC_TXSNR, TXTSSTSMIS)) 1531 return 0; 1532 1533 nsec = tx_ssr; 1534 nsec *= NSEC_PER_SEC; 1535 nsec += tx_snr; 1536 1537 return nsec; 1538 } 1539 1540 static void xgbe_get_rx_tstamp(struct xgbe_packet_data *packet, 1541 struct xgbe_ring_desc *rdesc) 1542 { 1543 u64 nsec; 1544 1545 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_CONTEXT_DESC3, TSA) && 1546 !XGMAC_GET_BITS_LE(rdesc->desc3, RX_CONTEXT_DESC3, TSD)) { 1547 nsec = le32_to_cpu(rdesc->desc1); 1548 nsec <<= 32; 1549 nsec |= le32_to_cpu(rdesc->desc0); 1550 if (nsec != 0xffffffffffffffffULL) { 1551 packet->rx_tstamp = nsec; 1552 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1553 RX_TSTAMP, 1); 1554 } 1555 } 1556 } 1557 1558 static int xgbe_config_tstamp(struct xgbe_prv_data *pdata, 1559 unsigned int mac_tscr) 1560 { 1561 /* Set one nano-second accuracy */ 1562 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCTRLSSR, 1); 1563 1564 /* Set fine timestamp update */ 1565 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 1); 1566 1567 /* Overwrite earlier timestamps */ 1568 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TXTSSTSM, 1); 1569 1570 XGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr); 1571 1572 /* Exit if timestamping is not enabled */ 1573 if (!XGMAC_GET_BITS(mac_tscr, MAC_TSCR, TSENA)) 1574 return 0; 1575 1576 /* Initialize time registers */ 1577 XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SSINC, XGBE_TSTAMP_SSINC); 1578 XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SNSINC, XGBE_TSTAMP_SNSINC); 1579 xgbe_update_tstamp_addend(pdata, pdata->tstamp_addend); 1580 xgbe_set_tstamp_time(pdata, 0, 0); 1581 1582 /* Initialize the timecounter */ 1583 timecounter_init(&pdata->tstamp_tc, &pdata->tstamp_cc, 1584 ktime_to_ns(ktime_get_real())); 1585 1586 return 0; 1587 } 1588 1589 static void xgbe_tx_start_xmit(struct xgbe_channel *channel, 1590 struct xgbe_ring *ring) 1591 { 1592 struct xgbe_prv_data *pdata = channel->pdata; 1593 struct xgbe_ring_data *rdata; 1594 1595 /* Make sure everything is written before the register write */ 1596 wmb(); 1597 1598 /* Issue a poll command to Tx DMA by writing address 1599 * of next immediate free descriptor */ 1600 rdata = XGBE_GET_DESC_DATA(ring, ring->cur); 1601 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDTR_LO, 1602 lower_32_bits(rdata->rdesc_dma)); 1603 1604 /* Start the Tx timer */ 1605 if (pdata->tx_usecs && !channel->tx_timer_active) { 1606 channel->tx_timer_active = 1; 1607 mod_timer(&channel->tx_timer, 1608 jiffies + usecs_to_jiffies(pdata->tx_usecs)); 1609 } 1610 1611 ring->tx.xmit_more = 0; 1612 } 1613 1614 static void xgbe_dev_xmit(struct xgbe_channel *channel) 1615 { 1616 struct xgbe_prv_data *pdata = channel->pdata; 1617 struct xgbe_ring *ring = channel->tx_ring; 1618 struct xgbe_ring_data *rdata; 1619 struct xgbe_ring_desc *rdesc; 1620 struct xgbe_packet_data *packet = &ring->packet_data; 1621 unsigned int tx_packets, tx_bytes; 1622 unsigned int csum, tso, vlan, vxlan; 1623 unsigned int tso_context, vlan_context; 1624 unsigned int tx_set_ic; 1625 int start_index = ring->cur; 1626 int cur_index = ring->cur; 1627 int i; 1628 1629 DBGPR("-->xgbe_dev_xmit\n"); 1630 1631 tx_packets = packet->tx_packets; 1632 tx_bytes = packet->tx_bytes; 1633 1634 csum = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, 1635 CSUM_ENABLE); 1636 tso = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, 1637 TSO_ENABLE); 1638 vlan = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, 1639 VLAN_CTAG); 1640 vxlan = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, 1641 VXLAN); 1642 1643 if (tso && (packet->mss != ring->tx.cur_mss)) 1644 tso_context = 1; 1645 else 1646 tso_context = 0; 1647 1648 if (vlan && (packet->vlan_ctag != ring->tx.cur_vlan_ctag)) 1649 vlan_context = 1; 1650 else 1651 vlan_context = 0; 1652 1653 /* Determine if an interrupt should be generated for this Tx: 1654 * Interrupt: 1655 * - Tx frame count exceeds the frame count setting 1656 * - Addition of Tx frame count to the frame count since the 1657 * last interrupt was set exceeds the frame count setting 1658 * No interrupt: 1659 * - No frame count setting specified (ethtool -C ethX tx-frames 0) 1660 * - Addition of Tx frame count to the frame count since the 1661 * last interrupt was set does not exceed the frame count setting 1662 */ 1663 ring->coalesce_count += tx_packets; 1664 if (!pdata->tx_frames) 1665 tx_set_ic = 0; 1666 else if (tx_packets > pdata->tx_frames) 1667 tx_set_ic = 1; 1668 else if ((ring->coalesce_count % pdata->tx_frames) < tx_packets) 1669 tx_set_ic = 1; 1670 else 1671 tx_set_ic = 0; 1672 1673 rdata = XGBE_GET_DESC_DATA(ring, cur_index); 1674 rdesc = rdata->rdesc; 1675 1676 /* Create a context descriptor if this is a TSO packet */ 1677 if (tso_context || vlan_context) { 1678 if (tso_context) { 1679 netif_dbg(pdata, tx_queued, pdata->netdev, 1680 "TSO context descriptor, mss=%u\n", 1681 packet->mss); 1682 1683 /* Set the MSS size */ 1684 XGMAC_SET_BITS_LE(rdesc->desc2, TX_CONTEXT_DESC2, 1685 MSS, packet->mss); 1686 1687 /* Mark it as a CONTEXT descriptor */ 1688 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, 1689 CTXT, 1); 1690 1691 /* Indicate this descriptor contains the MSS */ 1692 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, 1693 TCMSSV, 1); 1694 1695 ring->tx.cur_mss = packet->mss; 1696 } 1697 1698 if (vlan_context) { 1699 netif_dbg(pdata, tx_queued, pdata->netdev, 1700 "VLAN context descriptor, ctag=%u\n", 1701 packet->vlan_ctag); 1702 1703 /* Mark it as a CONTEXT descriptor */ 1704 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, 1705 CTXT, 1); 1706 1707 /* Set the VLAN tag */ 1708 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, 1709 VT, packet->vlan_ctag); 1710 1711 /* Indicate this descriptor contains the VLAN tag */ 1712 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3, 1713 VLTV, 1); 1714 1715 ring->tx.cur_vlan_ctag = packet->vlan_ctag; 1716 } 1717 1718 cur_index++; 1719 rdata = XGBE_GET_DESC_DATA(ring, cur_index); 1720 rdesc = rdata->rdesc; 1721 } 1722 1723 /* Update buffer address (for TSO this is the header) */ 1724 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma)); 1725 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma)); 1726 1727 /* Update the buffer length */ 1728 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, HL_B1L, 1729 rdata->skb_dma_len); 1730 1731 /* VLAN tag insertion check */ 1732 if (vlan) 1733 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, VTIR, 1734 TX_NORMAL_DESC2_VLAN_INSERT); 1735 1736 /* Timestamp enablement check */ 1737 if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP)) 1738 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, TTSE, 1); 1739 1740 /* Mark it as First Descriptor */ 1741 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FD, 1); 1742 1743 /* Mark it as a NORMAL descriptor */ 1744 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT, 0); 1745 1746 /* Set OWN bit if not the first descriptor */ 1747 if (cur_index != start_index) 1748 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1); 1749 1750 if (tso) { 1751 /* Enable TSO */ 1752 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TSE, 1); 1753 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TCPPL, 1754 packet->tcp_payload_len); 1755 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TCPHDRLEN, 1756 packet->tcp_header_len / 4); 1757 1758 pdata->ext_stats.tx_tso_packets += tx_packets; 1759 } else { 1760 /* Enable CRC and Pad Insertion */ 1761 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CPC, 0); 1762 1763 /* Enable HW CSUM */ 1764 if (csum) 1765 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, 1766 CIC, 0x3); 1767 1768 /* Set the total length to be transmitted */ 1769 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FL, 1770 packet->length); 1771 } 1772 1773 if (vxlan) { 1774 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, VNP, 1775 TX_NORMAL_DESC3_VXLAN_PACKET); 1776 1777 pdata->ext_stats.tx_vxlan_packets += packet->tx_packets; 1778 } 1779 1780 for (i = cur_index - start_index + 1; i < packet->rdesc_count; i++) { 1781 cur_index++; 1782 rdata = XGBE_GET_DESC_DATA(ring, cur_index); 1783 rdesc = rdata->rdesc; 1784 1785 /* Update buffer address */ 1786 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma)); 1787 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma)); 1788 1789 /* Update the buffer length */ 1790 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, HL_B1L, 1791 rdata->skb_dma_len); 1792 1793 /* Set OWN bit */ 1794 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1); 1795 1796 /* Mark it as NORMAL descriptor */ 1797 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT, 0); 1798 1799 /* Enable HW CSUM */ 1800 if (csum) 1801 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, 1802 CIC, 0x3); 1803 } 1804 1805 /* Set LAST bit for the last descriptor */ 1806 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD, 1); 1807 1808 /* Set IC bit based on Tx coalescing settings */ 1809 if (tx_set_ic) 1810 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, IC, 1); 1811 1812 /* Save the Tx info to report back during cleanup */ 1813 rdata->tx.packets = tx_packets; 1814 rdata->tx.bytes = tx_bytes; 1815 1816 pdata->ext_stats.txq_packets[channel->queue_index] += tx_packets; 1817 pdata->ext_stats.txq_bytes[channel->queue_index] += tx_bytes; 1818 1819 /* In case the Tx DMA engine is running, make sure everything 1820 * is written to the descriptor(s) before setting the OWN bit 1821 * for the first descriptor 1822 */ 1823 dma_wmb(); 1824 1825 /* Set OWN bit for the first descriptor */ 1826 rdata = XGBE_GET_DESC_DATA(ring, start_index); 1827 rdesc = rdata->rdesc; 1828 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1); 1829 1830 if (netif_msg_tx_queued(pdata)) 1831 xgbe_dump_tx_desc(pdata, ring, start_index, 1832 packet->rdesc_count, 1); 1833 1834 /* Make sure ownership is written to the descriptor */ 1835 smp_wmb(); 1836 1837 ring->cur = cur_index + 1; 1838 if (!netdev_xmit_more() || 1839 netif_xmit_stopped(netdev_get_tx_queue(pdata->netdev, 1840 channel->queue_index))) 1841 xgbe_tx_start_xmit(channel, ring); 1842 else 1843 ring->tx.xmit_more = 1; 1844 1845 DBGPR(" %s: descriptors %u to %u written\n", 1846 channel->name, start_index & (ring->rdesc_count - 1), 1847 (ring->cur - 1) & (ring->rdesc_count - 1)); 1848 1849 DBGPR("<--xgbe_dev_xmit\n"); 1850 } 1851 1852 static int xgbe_dev_read(struct xgbe_channel *channel) 1853 { 1854 struct xgbe_prv_data *pdata = channel->pdata; 1855 struct xgbe_ring *ring = channel->rx_ring; 1856 struct xgbe_ring_data *rdata; 1857 struct xgbe_ring_desc *rdesc; 1858 struct xgbe_packet_data *packet = &ring->packet_data; 1859 struct net_device *netdev = pdata->netdev; 1860 unsigned int err, etlt, l34t; 1861 1862 DBGPR("-->xgbe_dev_read: cur = %d\n", ring->cur); 1863 1864 rdata = XGBE_GET_DESC_DATA(ring, ring->cur); 1865 rdesc = rdata->rdesc; 1866 1867 /* Check for data availability */ 1868 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN)) 1869 return 1; 1870 1871 /* Make sure descriptor fields are read after reading the OWN bit */ 1872 dma_rmb(); 1873 1874 if (netif_msg_rx_status(pdata)) 1875 xgbe_dump_rx_desc(pdata, ring, ring->cur); 1876 1877 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CTXT)) { 1878 /* Timestamp Context Descriptor */ 1879 xgbe_get_rx_tstamp(packet, rdesc); 1880 1881 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1882 CONTEXT, 1); 1883 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1884 CONTEXT_NEXT, 0); 1885 return 0; 1886 } 1887 1888 /* Normal Descriptor, be sure Context Descriptor bit is off */ 1889 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, CONTEXT, 0); 1890 1891 /* Indicate if a Context Descriptor is next */ 1892 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CDA)) 1893 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1894 CONTEXT_NEXT, 1); 1895 1896 /* Get the header length */ 1897 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, FD)) { 1898 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1899 FIRST, 1); 1900 rdata->rx.hdr_len = XGMAC_GET_BITS_LE(rdesc->desc2, 1901 RX_NORMAL_DESC2, HL); 1902 if (rdata->rx.hdr_len) 1903 pdata->ext_stats.rx_split_header_packets++; 1904 } else { 1905 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1906 FIRST, 0); 1907 } 1908 1909 /* Get the RSS hash */ 1910 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, RSV)) { 1911 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1912 RSS_HASH, 1); 1913 1914 packet->rss_hash = le32_to_cpu(rdesc->desc1); 1915 1916 l34t = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, L34T); 1917 switch (l34t) { 1918 case RX_DESC3_L34T_IPV4_TCP: 1919 case RX_DESC3_L34T_IPV4_UDP: 1920 case RX_DESC3_L34T_IPV6_TCP: 1921 case RX_DESC3_L34T_IPV6_UDP: 1922 packet->rss_hash_type = PKT_HASH_TYPE_L4; 1923 break; 1924 default: 1925 packet->rss_hash_type = PKT_HASH_TYPE_L3; 1926 } 1927 } 1928 1929 /* Not all the data has been transferred for this packet */ 1930 if (!XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, LD)) 1931 return 0; 1932 1933 /* This is the last of the data for this packet */ 1934 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1935 LAST, 1); 1936 1937 /* Get the packet length */ 1938 rdata->rx.len = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, PL); 1939 1940 /* Set checksum done indicator as appropriate */ 1941 if (netdev->features & NETIF_F_RXCSUM) { 1942 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1943 CSUM_DONE, 1); 1944 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1945 TNPCSUM_DONE, 1); 1946 } 1947 1948 /* Set the tunneled packet indicator */ 1949 if (XGMAC_GET_BITS_LE(rdesc->desc2, RX_NORMAL_DESC2, TNP)) { 1950 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1951 TNP, 1); 1952 pdata->ext_stats.rx_vxlan_packets++; 1953 1954 l34t = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, L34T); 1955 switch (l34t) { 1956 case RX_DESC3_L34T_IPV4_UNKNOWN: 1957 case RX_DESC3_L34T_IPV6_UNKNOWN: 1958 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1959 TNPCSUM_DONE, 0); 1960 break; 1961 } 1962 } 1963 1964 /* Check for errors (only valid in last descriptor) */ 1965 err = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ES); 1966 etlt = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ETLT); 1967 netif_dbg(pdata, rx_status, netdev, "err=%u, etlt=%#x\n", err, etlt); 1968 1969 if (!err || !etlt) { 1970 /* No error if err is 0 or etlt is 0 */ 1971 if ((etlt == 0x09) && 1972 (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)) { 1973 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1974 VLAN_CTAG, 1); 1975 packet->vlan_ctag = XGMAC_GET_BITS_LE(rdesc->desc0, 1976 RX_NORMAL_DESC0, 1977 OVT); 1978 netif_dbg(pdata, rx_status, netdev, "vlan-ctag=%#06x\n", 1979 packet->vlan_ctag); 1980 } 1981 } else { 1982 unsigned int tnp = XGMAC_GET_BITS(packet->attributes, 1983 RX_PACKET_ATTRIBUTES, TNP); 1984 1985 if ((etlt == 0x05) || (etlt == 0x06)) { 1986 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1987 CSUM_DONE, 0); 1988 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1989 TNPCSUM_DONE, 0); 1990 pdata->ext_stats.rx_csum_errors++; 1991 } else if (tnp && ((etlt == 0x09) || (etlt == 0x0a))) { 1992 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1993 CSUM_DONE, 0); 1994 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1995 TNPCSUM_DONE, 0); 1996 pdata->ext_stats.rx_vxlan_csum_errors++; 1997 } else { 1998 XGMAC_SET_BITS(packet->errors, RX_PACKET_ERRORS, 1999 FRAME, 1); 2000 } 2001 } 2002 2003 pdata->ext_stats.rxq_packets[channel->queue_index]++; 2004 pdata->ext_stats.rxq_bytes[channel->queue_index] += rdata->rx.len; 2005 2006 DBGPR("<--xgbe_dev_read: %s - descriptor=%u (cur=%d)\n", channel->name, 2007 ring->cur & (ring->rdesc_count - 1), ring->cur); 2008 2009 return 0; 2010 } 2011 2012 static int xgbe_is_context_desc(struct xgbe_ring_desc *rdesc) 2013 { 2014 /* Rx and Tx share CTXT bit, so check TDES3.CTXT bit */ 2015 return XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT); 2016 } 2017 2018 static int xgbe_is_last_desc(struct xgbe_ring_desc *rdesc) 2019 { 2020 /* Rx and Tx share LD bit, so check TDES3.LD bit */ 2021 return XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD); 2022 } 2023 2024 static int xgbe_enable_int(struct xgbe_channel *channel, 2025 enum xgbe_int int_id) 2026 { 2027 switch (int_id) { 2028 case XGMAC_INT_DMA_CH_SR_TI: 2029 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 1); 2030 break; 2031 case XGMAC_INT_DMA_CH_SR_TPS: 2032 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TXSE, 1); 2033 break; 2034 case XGMAC_INT_DMA_CH_SR_TBU: 2035 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TBUE, 1); 2036 break; 2037 case XGMAC_INT_DMA_CH_SR_RI: 2038 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 1); 2039 break; 2040 case XGMAC_INT_DMA_CH_SR_RBU: 2041 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RBUE, 1); 2042 break; 2043 case XGMAC_INT_DMA_CH_SR_RPS: 2044 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RSE, 1); 2045 break; 2046 case XGMAC_INT_DMA_CH_SR_TI_RI: 2047 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 1); 2048 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 1); 2049 break; 2050 case XGMAC_INT_DMA_CH_SR_FBE: 2051 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, FBEE, 1); 2052 break; 2053 case XGMAC_INT_DMA_ALL: 2054 channel->curr_ier |= channel->saved_ier; 2055 break; 2056 default: 2057 return -1; 2058 } 2059 2060 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, channel->curr_ier); 2061 2062 return 0; 2063 } 2064 2065 static int xgbe_disable_int(struct xgbe_channel *channel, 2066 enum xgbe_int int_id) 2067 { 2068 switch (int_id) { 2069 case XGMAC_INT_DMA_CH_SR_TI: 2070 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 0); 2071 break; 2072 case XGMAC_INT_DMA_CH_SR_TPS: 2073 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TXSE, 0); 2074 break; 2075 case XGMAC_INT_DMA_CH_SR_TBU: 2076 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TBUE, 0); 2077 break; 2078 case XGMAC_INT_DMA_CH_SR_RI: 2079 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 0); 2080 break; 2081 case XGMAC_INT_DMA_CH_SR_RBU: 2082 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RBUE, 0); 2083 break; 2084 case XGMAC_INT_DMA_CH_SR_RPS: 2085 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RSE, 0); 2086 break; 2087 case XGMAC_INT_DMA_CH_SR_TI_RI: 2088 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 0); 2089 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 0); 2090 break; 2091 case XGMAC_INT_DMA_CH_SR_FBE: 2092 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, FBEE, 0); 2093 break; 2094 case XGMAC_INT_DMA_ALL: 2095 channel->saved_ier = channel->curr_ier; 2096 channel->curr_ier = 0; 2097 break; 2098 default: 2099 return -1; 2100 } 2101 2102 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, channel->curr_ier); 2103 2104 return 0; 2105 } 2106 2107 static int __xgbe_exit(struct xgbe_prv_data *pdata) 2108 { 2109 unsigned int count = 2000; 2110 2111 DBGPR("-->xgbe_exit\n"); 2112 2113 /* Issue a software reset */ 2114 XGMAC_IOWRITE_BITS(pdata, DMA_MR, SWR, 1); 2115 usleep_range(10, 15); 2116 2117 /* Poll Until Poll Condition */ 2118 while (--count && XGMAC_IOREAD_BITS(pdata, DMA_MR, SWR)) 2119 usleep_range(500, 600); 2120 2121 if (!count) 2122 return -EBUSY; 2123 2124 DBGPR("<--xgbe_exit\n"); 2125 2126 return 0; 2127 } 2128 2129 static int xgbe_exit(struct xgbe_prv_data *pdata) 2130 { 2131 int ret; 2132 2133 /* To guard against possible incorrectly generated interrupts, 2134 * issue the software reset twice. 2135 */ 2136 ret = __xgbe_exit(pdata); 2137 if (ret) 2138 return ret; 2139 2140 return __xgbe_exit(pdata); 2141 } 2142 2143 static int xgbe_flush_tx_queues(struct xgbe_prv_data *pdata) 2144 { 2145 unsigned int i, count; 2146 2147 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) < 0x21) 2148 return 0; 2149 2150 for (i = 0; i < pdata->tx_q_count; i++) 2151 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, FTQ, 1); 2152 2153 /* Poll Until Poll Condition */ 2154 for (i = 0; i < pdata->tx_q_count; i++) { 2155 count = 2000; 2156 while (--count && XGMAC_MTL_IOREAD_BITS(pdata, i, 2157 MTL_Q_TQOMR, FTQ)) 2158 usleep_range(500, 600); 2159 2160 if (!count) 2161 return -EBUSY; 2162 } 2163 2164 return 0; 2165 } 2166 2167 static void xgbe_config_dma_bus(struct xgbe_prv_data *pdata) 2168 { 2169 unsigned int sbmr; 2170 2171 sbmr = XGMAC_IOREAD(pdata, DMA_SBMR); 2172 2173 /* Set enhanced addressing mode */ 2174 XGMAC_SET_BITS(sbmr, DMA_SBMR, EAME, 1); 2175 2176 /* Set the System Bus mode */ 2177 XGMAC_SET_BITS(sbmr, DMA_SBMR, UNDEF, 1); 2178 XGMAC_SET_BITS(sbmr, DMA_SBMR, BLEN, pdata->blen >> 2); 2179 XGMAC_SET_BITS(sbmr, DMA_SBMR, AAL, pdata->aal); 2180 XGMAC_SET_BITS(sbmr, DMA_SBMR, RD_OSR_LMT, pdata->rd_osr_limit - 1); 2181 XGMAC_SET_BITS(sbmr, DMA_SBMR, WR_OSR_LMT, pdata->wr_osr_limit - 1); 2182 2183 XGMAC_IOWRITE(pdata, DMA_SBMR, sbmr); 2184 2185 /* Set descriptor fetching threshold */ 2186 if (pdata->vdata->tx_desc_prefetch) 2187 XGMAC_IOWRITE_BITS(pdata, DMA_TXEDMACR, TDPS, 2188 pdata->vdata->tx_desc_prefetch); 2189 2190 if (pdata->vdata->rx_desc_prefetch) 2191 XGMAC_IOWRITE_BITS(pdata, DMA_RXEDMACR, RDPS, 2192 pdata->vdata->rx_desc_prefetch); 2193 } 2194 2195 static void xgbe_config_dma_cache(struct xgbe_prv_data *pdata) 2196 { 2197 XGMAC_IOWRITE(pdata, DMA_AXIARCR, pdata->arcr); 2198 XGMAC_IOWRITE(pdata, DMA_AXIAWCR, pdata->awcr); 2199 if (pdata->awarcr) 2200 XGMAC_IOWRITE(pdata, DMA_AXIAWARCR, pdata->awarcr); 2201 } 2202 2203 static void xgbe_config_mtl_mode(struct xgbe_prv_data *pdata) 2204 { 2205 unsigned int i; 2206 2207 /* Set Tx to weighted round robin scheduling algorithm */ 2208 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_WRR); 2209 2210 /* Set Tx traffic classes to use WRR algorithm with equal weights */ 2211 for (i = 0; i < pdata->hw_feat.tc_cnt; i++) { 2212 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA, 2213 MTL_TSA_ETS); 2214 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW, 1); 2215 } 2216 2217 /* Set Rx to strict priority algorithm */ 2218 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, RAA, MTL_RAA_SP); 2219 } 2220 2221 static void xgbe_queue_flow_control_threshold(struct xgbe_prv_data *pdata, 2222 unsigned int queue, 2223 unsigned int q_fifo_size) 2224 { 2225 unsigned int frame_fifo_size; 2226 unsigned int rfa, rfd; 2227 2228 frame_fifo_size = XGMAC_FLOW_CONTROL_ALIGN(xgbe_get_max_frame(pdata)); 2229 2230 if (pdata->pfcq[queue] && (q_fifo_size > pdata->pfc_rfa)) { 2231 /* PFC is active for this queue */ 2232 rfa = pdata->pfc_rfa; 2233 rfd = rfa + frame_fifo_size; 2234 if (rfd > XGMAC_FLOW_CONTROL_MAX) 2235 rfd = XGMAC_FLOW_CONTROL_MAX; 2236 if (rfa >= XGMAC_FLOW_CONTROL_MAX) 2237 rfa = XGMAC_FLOW_CONTROL_MAX - XGMAC_FLOW_CONTROL_UNIT; 2238 } else { 2239 /* This path deals with just maximum frame sizes which are 2240 * limited to a jumbo frame of 9,000 (plus headers, etc.) 2241 * so we can never exceed the maximum allowable RFA/RFD 2242 * values. 2243 */ 2244 if (q_fifo_size <= 2048) { 2245 /* rx_rfd to zero to signal no flow control */ 2246 pdata->rx_rfa[queue] = 0; 2247 pdata->rx_rfd[queue] = 0; 2248 return; 2249 } 2250 2251 if (q_fifo_size <= 4096) { 2252 /* Between 2048 and 4096 */ 2253 pdata->rx_rfa[queue] = 0; /* Full - 1024 bytes */ 2254 pdata->rx_rfd[queue] = 1; /* Full - 1536 bytes */ 2255 return; 2256 } 2257 2258 if (q_fifo_size <= frame_fifo_size) { 2259 /* Between 4096 and max-frame */ 2260 pdata->rx_rfa[queue] = 2; /* Full - 2048 bytes */ 2261 pdata->rx_rfd[queue] = 5; /* Full - 3584 bytes */ 2262 return; 2263 } 2264 2265 if (q_fifo_size <= (frame_fifo_size * 3)) { 2266 /* Between max-frame and 3 max-frames, 2267 * trigger if we get just over a frame of data and 2268 * resume when we have just under half a frame left. 2269 */ 2270 rfa = q_fifo_size - frame_fifo_size; 2271 rfd = rfa + (frame_fifo_size / 2); 2272 } else { 2273 /* Above 3 max-frames - trigger when just over 2274 * 2 frames of space available 2275 */ 2276 rfa = frame_fifo_size * 2; 2277 rfa += XGMAC_FLOW_CONTROL_UNIT; 2278 rfd = rfa + frame_fifo_size; 2279 } 2280 } 2281 2282 pdata->rx_rfa[queue] = XGMAC_FLOW_CONTROL_VALUE(rfa); 2283 pdata->rx_rfd[queue] = XGMAC_FLOW_CONTROL_VALUE(rfd); 2284 } 2285 2286 static void xgbe_calculate_flow_control_threshold(struct xgbe_prv_data *pdata, 2287 unsigned int *fifo) 2288 { 2289 unsigned int q_fifo_size; 2290 unsigned int i; 2291 2292 for (i = 0; i < pdata->rx_q_count; i++) { 2293 q_fifo_size = (fifo[i] + 1) * XGMAC_FIFO_UNIT; 2294 2295 xgbe_queue_flow_control_threshold(pdata, i, q_fifo_size); 2296 } 2297 } 2298 2299 static void xgbe_config_flow_control_threshold(struct xgbe_prv_data *pdata) 2300 { 2301 unsigned int i; 2302 2303 for (i = 0; i < pdata->rx_q_count; i++) { 2304 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFA, 2305 pdata->rx_rfa[i]); 2306 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFD, 2307 pdata->rx_rfd[i]); 2308 } 2309 } 2310 2311 static unsigned int xgbe_get_tx_fifo_size(struct xgbe_prv_data *pdata) 2312 { 2313 /* The configured value may not be the actual amount of fifo RAM */ 2314 return min_t(unsigned int, pdata->tx_max_fifo_size, 2315 pdata->hw_feat.tx_fifo_size); 2316 } 2317 2318 static unsigned int xgbe_get_rx_fifo_size(struct xgbe_prv_data *pdata) 2319 { 2320 /* The configured value may not be the actual amount of fifo RAM */ 2321 return min_t(unsigned int, pdata->rx_max_fifo_size, 2322 pdata->hw_feat.rx_fifo_size); 2323 } 2324 2325 static void xgbe_calculate_equal_fifo(unsigned int fifo_size, 2326 unsigned int queue_count, 2327 unsigned int *fifo) 2328 { 2329 unsigned int q_fifo_size; 2330 unsigned int p_fifo; 2331 unsigned int i; 2332 2333 q_fifo_size = fifo_size / queue_count; 2334 2335 /* Calculate the fifo setting by dividing the queue's fifo size 2336 * by the fifo allocation increment (with 0 representing the 2337 * base allocation increment so decrement the result by 1). 2338 */ 2339 p_fifo = q_fifo_size / XGMAC_FIFO_UNIT; 2340 if (p_fifo) 2341 p_fifo--; 2342 2343 /* Distribute the fifo equally amongst the queues */ 2344 for (i = 0; i < queue_count; i++) 2345 fifo[i] = p_fifo; 2346 } 2347 2348 static unsigned int xgbe_set_nonprio_fifos(unsigned int fifo_size, 2349 unsigned int queue_count, 2350 unsigned int *fifo) 2351 { 2352 unsigned int i; 2353 2354 BUILD_BUG_ON_NOT_POWER_OF_2(XGMAC_FIFO_MIN_ALLOC); 2355 2356 if (queue_count <= IEEE_8021QAZ_MAX_TCS) 2357 return fifo_size; 2358 2359 /* Rx queues 9 and up are for specialized packets, 2360 * such as PTP or DCB control packets, etc. and 2361 * don't require a large fifo 2362 */ 2363 for (i = IEEE_8021QAZ_MAX_TCS; i < queue_count; i++) { 2364 fifo[i] = (XGMAC_FIFO_MIN_ALLOC / XGMAC_FIFO_UNIT) - 1; 2365 fifo_size -= XGMAC_FIFO_MIN_ALLOC; 2366 } 2367 2368 return fifo_size; 2369 } 2370 2371 static unsigned int xgbe_get_pfc_delay(struct xgbe_prv_data *pdata) 2372 { 2373 unsigned int delay; 2374 2375 /* If a delay has been provided, use that */ 2376 if (pdata->pfc->delay) 2377 return pdata->pfc->delay / 8; 2378 2379 /* Allow for two maximum size frames */ 2380 delay = xgbe_get_max_frame(pdata); 2381 delay += XGMAC_ETH_PREAMBLE; 2382 delay *= 2; 2383 2384 /* Allow for PFC frame */ 2385 delay += XGMAC_PFC_DATA_LEN; 2386 delay += ETH_HLEN + ETH_FCS_LEN; 2387 delay += XGMAC_ETH_PREAMBLE; 2388 2389 /* Allow for miscellaneous delays (LPI exit, cable, etc.) */ 2390 delay += XGMAC_PFC_DELAYS; 2391 2392 return delay; 2393 } 2394 2395 static unsigned int xgbe_get_pfc_queues(struct xgbe_prv_data *pdata) 2396 { 2397 unsigned int count, prio_queues; 2398 unsigned int i; 2399 2400 if (!pdata->pfc->pfc_en) 2401 return 0; 2402 2403 count = 0; 2404 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count); 2405 for (i = 0; i < prio_queues; i++) { 2406 if (!xgbe_is_pfc_queue(pdata, i)) 2407 continue; 2408 2409 pdata->pfcq[i] = 1; 2410 count++; 2411 } 2412 2413 return count; 2414 } 2415 2416 static void xgbe_calculate_dcb_fifo(struct xgbe_prv_data *pdata, 2417 unsigned int fifo_size, 2418 unsigned int *fifo) 2419 { 2420 unsigned int q_fifo_size, rem_fifo, addn_fifo; 2421 unsigned int prio_queues; 2422 unsigned int pfc_count; 2423 unsigned int i; 2424 2425 q_fifo_size = XGMAC_FIFO_ALIGN(xgbe_get_max_frame(pdata)); 2426 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count); 2427 pfc_count = xgbe_get_pfc_queues(pdata); 2428 2429 if (!pfc_count || ((q_fifo_size * prio_queues) > fifo_size)) { 2430 /* No traffic classes with PFC enabled or can't do lossless */ 2431 xgbe_calculate_equal_fifo(fifo_size, prio_queues, fifo); 2432 return; 2433 } 2434 2435 /* Calculate how much fifo we have to play with */ 2436 rem_fifo = fifo_size - (q_fifo_size * prio_queues); 2437 2438 /* Calculate how much more than base fifo PFC needs, which also 2439 * becomes the threshold activation point (RFA) 2440 */ 2441 pdata->pfc_rfa = xgbe_get_pfc_delay(pdata); 2442 pdata->pfc_rfa = XGMAC_FLOW_CONTROL_ALIGN(pdata->pfc_rfa); 2443 2444 if (pdata->pfc_rfa > q_fifo_size) { 2445 addn_fifo = pdata->pfc_rfa - q_fifo_size; 2446 addn_fifo = XGMAC_FIFO_ALIGN(addn_fifo); 2447 } else { 2448 addn_fifo = 0; 2449 } 2450 2451 /* Calculate DCB fifo settings: 2452 * - distribute remaining fifo between the VLAN priority 2453 * queues based on traffic class PFC enablement and overall 2454 * priority (0 is lowest priority, so start at highest) 2455 */ 2456 i = prio_queues; 2457 while (i > 0) { 2458 i--; 2459 2460 fifo[i] = (q_fifo_size / XGMAC_FIFO_UNIT) - 1; 2461 2462 if (!pdata->pfcq[i] || !addn_fifo) 2463 continue; 2464 2465 if (addn_fifo > rem_fifo) { 2466 netdev_warn(pdata->netdev, 2467 "RXq%u cannot set needed fifo size\n", i); 2468 if (!rem_fifo) 2469 continue; 2470 2471 addn_fifo = rem_fifo; 2472 } 2473 2474 fifo[i] += (addn_fifo / XGMAC_FIFO_UNIT); 2475 rem_fifo -= addn_fifo; 2476 } 2477 2478 if (rem_fifo) { 2479 unsigned int inc_fifo = rem_fifo / prio_queues; 2480 2481 /* Distribute remaining fifo across queues */ 2482 for (i = 0; i < prio_queues; i++) 2483 fifo[i] += (inc_fifo / XGMAC_FIFO_UNIT); 2484 } 2485 } 2486 2487 static void xgbe_config_tx_fifo_size(struct xgbe_prv_data *pdata) 2488 { 2489 unsigned int fifo_size; 2490 unsigned int fifo[XGBE_MAX_QUEUES]; 2491 unsigned int i; 2492 2493 fifo_size = xgbe_get_tx_fifo_size(pdata); 2494 2495 xgbe_calculate_equal_fifo(fifo_size, pdata->tx_q_count, fifo); 2496 2497 for (i = 0; i < pdata->tx_q_count; i++) 2498 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TQS, fifo[i]); 2499 2500 netif_info(pdata, drv, pdata->netdev, 2501 "%d Tx hardware queues, %d byte fifo per queue\n", 2502 pdata->tx_q_count, ((fifo[0] + 1) * XGMAC_FIFO_UNIT)); 2503 } 2504 2505 static void xgbe_config_rx_fifo_size(struct xgbe_prv_data *pdata) 2506 { 2507 unsigned int fifo_size; 2508 unsigned int fifo[XGBE_MAX_QUEUES]; 2509 unsigned int prio_queues; 2510 unsigned int i; 2511 2512 /* Clear any DCB related fifo/queue information */ 2513 memset(pdata->pfcq, 0, sizeof(pdata->pfcq)); 2514 pdata->pfc_rfa = 0; 2515 2516 fifo_size = xgbe_get_rx_fifo_size(pdata); 2517 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count); 2518 2519 /* Assign a minimum fifo to the non-VLAN priority queues */ 2520 fifo_size = xgbe_set_nonprio_fifos(fifo_size, pdata->rx_q_count, fifo); 2521 2522 if (pdata->pfc && pdata->ets) 2523 xgbe_calculate_dcb_fifo(pdata, fifo_size, fifo); 2524 else 2525 xgbe_calculate_equal_fifo(fifo_size, prio_queues, fifo); 2526 2527 for (i = 0; i < pdata->rx_q_count; i++) 2528 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RQS, fifo[i]); 2529 2530 xgbe_calculate_flow_control_threshold(pdata, fifo); 2531 xgbe_config_flow_control_threshold(pdata); 2532 2533 if (pdata->pfc && pdata->ets && pdata->pfc->pfc_en) { 2534 netif_info(pdata, drv, pdata->netdev, 2535 "%u Rx hardware queues\n", pdata->rx_q_count); 2536 for (i = 0; i < pdata->rx_q_count; i++) 2537 netif_info(pdata, drv, pdata->netdev, 2538 "RxQ%u, %u byte fifo queue\n", i, 2539 ((fifo[i] + 1) * XGMAC_FIFO_UNIT)); 2540 } else { 2541 netif_info(pdata, drv, pdata->netdev, 2542 "%u Rx hardware queues, %u byte fifo per queue\n", 2543 pdata->rx_q_count, 2544 ((fifo[0] + 1) * XGMAC_FIFO_UNIT)); 2545 } 2546 } 2547 2548 static void xgbe_config_queue_mapping(struct xgbe_prv_data *pdata) 2549 { 2550 unsigned int qptc, qptc_extra, queue; 2551 unsigned int prio_queues; 2552 unsigned int ppq, ppq_extra, prio; 2553 unsigned int mask; 2554 unsigned int i, j, reg, reg_val; 2555 2556 /* Map the MTL Tx Queues to Traffic Classes 2557 * Note: Tx Queues >= Traffic Classes 2558 */ 2559 qptc = pdata->tx_q_count / pdata->hw_feat.tc_cnt; 2560 qptc_extra = pdata->tx_q_count % pdata->hw_feat.tc_cnt; 2561 2562 for (i = 0, queue = 0; i < pdata->hw_feat.tc_cnt; i++) { 2563 for (j = 0; j < qptc; j++) { 2564 netif_dbg(pdata, drv, pdata->netdev, 2565 "TXq%u mapped to TC%u\n", queue, i); 2566 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR, 2567 Q2TCMAP, i); 2568 pdata->q2tc_map[queue++] = i; 2569 } 2570 2571 if (i < qptc_extra) { 2572 netif_dbg(pdata, drv, pdata->netdev, 2573 "TXq%u mapped to TC%u\n", queue, i); 2574 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR, 2575 Q2TCMAP, i); 2576 pdata->q2tc_map[queue++] = i; 2577 } 2578 } 2579 2580 /* Map the 8 VLAN priority values to available MTL Rx queues */ 2581 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count); 2582 ppq = IEEE_8021QAZ_MAX_TCS / prio_queues; 2583 ppq_extra = IEEE_8021QAZ_MAX_TCS % prio_queues; 2584 2585 reg = MAC_RQC2R; 2586 reg_val = 0; 2587 for (i = 0, prio = 0; i < prio_queues;) { 2588 mask = 0; 2589 for (j = 0; j < ppq; j++) { 2590 netif_dbg(pdata, drv, pdata->netdev, 2591 "PRIO%u mapped to RXq%u\n", prio, i); 2592 mask |= (1 << prio); 2593 pdata->prio2q_map[prio++] = i; 2594 } 2595 2596 if (i < ppq_extra) { 2597 netif_dbg(pdata, drv, pdata->netdev, 2598 "PRIO%u mapped to RXq%u\n", prio, i); 2599 mask |= (1 << prio); 2600 pdata->prio2q_map[prio++] = i; 2601 } 2602 2603 reg_val |= (mask << ((i++ % MAC_RQC2_Q_PER_REG) << 3)); 2604 2605 if ((i % MAC_RQC2_Q_PER_REG) && (i != prio_queues)) 2606 continue; 2607 2608 XGMAC_IOWRITE(pdata, reg, reg_val); 2609 reg += MAC_RQC2_INC; 2610 reg_val = 0; 2611 } 2612 2613 /* Select dynamic mapping of MTL Rx queue to DMA Rx channel */ 2614 reg = MTL_RQDCM0R; 2615 reg_val = 0; 2616 for (i = 0; i < pdata->rx_q_count;) { 2617 reg_val |= (0x80 << ((i++ % MTL_RQDCM_Q_PER_REG) << 3)); 2618 2619 if ((i % MTL_RQDCM_Q_PER_REG) && (i != pdata->rx_q_count)) 2620 continue; 2621 2622 XGMAC_IOWRITE(pdata, reg, reg_val); 2623 2624 reg += MTL_RQDCM_INC; 2625 reg_val = 0; 2626 } 2627 } 2628 2629 static void xgbe_config_tc(struct xgbe_prv_data *pdata) 2630 { 2631 unsigned int offset, queue, prio; 2632 u8 i; 2633 2634 netdev_reset_tc(pdata->netdev); 2635 if (!pdata->num_tcs) 2636 return; 2637 2638 netdev_set_num_tc(pdata->netdev, pdata->num_tcs); 2639 2640 for (i = 0, queue = 0, offset = 0; i < pdata->num_tcs; i++) { 2641 while ((queue < pdata->tx_q_count) && 2642 (pdata->q2tc_map[queue] == i)) 2643 queue++; 2644 2645 netif_dbg(pdata, drv, pdata->netdev, "TC%u using TXq%u-%u\n", 2646 i, offset, queue - 1); 2647 netdev_set_tc_queue(pdata->netdev, i, queue - offset, offset); 2648 offset = queue; 2649 } 2650 2651 if (!pdata->ets) 2652 return; 2653 2654 for (prio = 0; prio < IEEE_8021QAZ_MAX_TCS; prio++) 2655 netdev_set_prio_tc_map(pdata->netdev, prio, 2656 pdata->ets->prio_tc[prio]); 2657 } 2658 2659 static void xgbe_config_dcb_tc(struct xgbe_prv_data *pdata) 2660 { 2661 struct ieee_ets *ets = pdata->ets; 2662 unsigned int total_weight, min_weight, weight; 2663 unsigned int mask, reg, reg_val; 2664 unsigned int i, prio; 2665 2666 if (!ets) 2667 return; 2668 2669 /* Set Tx to deficit weighted round robin scheduling algorithm (when 2670 * traffic class is using ETS algorithm) 2671 */ 2672 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_DWRR); 2673 2674 /* Set Traffic Class algorithms */ 2675 total_weight = pdata->netdev->mtu * pdata->hw_feat.tc_cnt; 2676 min_weight = total_weight / 100; 2677 if (!min_weight) 2678 min_weight = 1; 2679 2680 for (i = 0; i < pdata->hw_feat.tc_cnt; i++) { 2681 /* Map the priorities to the traffic class */ 2682 mask = 0; 2683 for (prio = 0; prio < IEEE_8021QAZ_MAX_TCS; prio++) { 2684 if (ets->prio_tc[prio] == i) 2685 mask |= (1 << prio); 2686 } 2687 mask &= 0xff; 2688 2689 netif_dbg(pdata, drv, pdata->netdev, "TC%u PRIO mask=%#x\n", 2690 i, mask); 2691 reg = MTL_TCPM0R + (MTL_TCPM_INC * (i / MTL_TCPM_TC_PER_REG)); 2692 reg_val = XGMAC_IOREAD(pdata, reg); 2693 2694 reg_val &= ~(0xff << ((i % MTL_TCPM_TC_PER_REG) << 3)); 2695 reg_val |= (mask << ((i % MTL_TCPM_TC_PER_REG) << 3)); 2696 2697 XGMAC_IOWRITE(pdata, reg, reg_val); 2698 2699 /* Set the traffic class algorithm */ 2700 switch (ets->tc_tsa[i]) { 2701 case IEEE_8021QAZ_TSA_STRICT: 2702 netif_dbg(pdata, drv, pdata->netdev, 2703 "TC%u using SP\n", i); 2704 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA, 2705 MTL_TSA_SP); 2706 break; 2707 case IEEE_8021QAZ_TSA_ETS: 2708 weight = total_weight * ets->tc_tx_bw[i] / 100; 2709 weight = clamp(weight, min_weight, total_weight); 2710 2711 netif_dbg(pdata, drv, pdata->netdev, 2712 "TC%u using DWRR (weight %u)\n", i, weight); 2713 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA, 2714 MTL_TSA_ETS); 2715 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW, 2716 weight); 2717 break; 2718 } 2719 } 2720 2721 xgbe_config_tc(pdata); 2722 } 2723 2724 static void xgbe_config_dcb_pfc(struct xgbe_prv_data *pdata) 2725 { 2726 if (!test_bit(XGBE_DOWN, &pdata->dev_state)) { 2727 /* Just stop the Tx queues while Rx fifo is changed */ 2728 netif_tx_stop_all_queues(pdata->netdev); 2729 2730 /* Suspend Rx so that fifo's can be adjusted */ 2731 pdata->hw_if.disable_rx(pdata); 2732 } 2733 2734 xgbe_config_rx_fifo_size(pdata); 2735 xgbe_config_flow_control(pdata); 2736 2737 if (!test_bit(XGBE_DOWN, &pdata->dev_state)) { 2738 /* Resume Rx */ 2739 pdata->hw_if.enable_rx(pdata); 2740 2741 /* Resume Tx queues */ 2742 netif_tx_start_all_queues(pdata->netdev); 2743 } 2744 } 2745 2746 static void xgbe_config_mac_address(struct xgbe_prv_data *pdata) 2747 { 2748 xgbe_set_mac_address(pdata, pdata->netdev->dev_addr); 2749 2750 /* Filtering is done using perfect filtering and hash filtering */ 2751 if (pdata->hw_feat.hash_table_size) { 2752 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1); 2753 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1); 2754 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HMC, 1); 2755 } 2756 } 2757 2758 static void xgbe_config_jumbo_enable(struct xgbe_prv_data *pdata) 2759 { 2760 unsigned int val; 2761 2762 val = (pdata->netdev->mtu > XGMAC_STD_PACKET_MTU) ? 1 : 0; 2763 2764 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, JE, val); 2765 } 2766 2767 static void xgbe_config_mac_speed(struct xgbe_prv_data *pdata) 2768 { 2769 xgbe_set_speed(pdata, pdata->phy_speed); 2770 } 2771 2772 static void xgbe_config_checksum_offload(struct xgbe_prv_data *pdata) 2773 { 2774 if (pdata->netdev->features & NETIF_F_RXCSUM) 2775 xgbe_enable_rx_csum(pdata); 2776 else 2777 xgbe_disable_rx_csum(pdata); 2778 } 2779 2780 static void xgbe_config_vlan_support(struct xgbe_prv_data *pdata) 2781 { 2782 /* Indicate that VLAN Tx CTAGs come from context descriptors */ 2783 XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, CSVL, 0); 2784 XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, VLTI, 1); 2785 2786 /* Set the current VLAN Hash Table register value */ 2787 xgbe_update_vlan_hash_table(pdata); 2788 2789 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER) 2790 xgbe_enable_rx_vlan_filtering(pdata); 2791 else 2792 xgbe_disable_rx_vlan_filtering(pdata); 2793 2794 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) 2795 xgbe_enable_rx_vlan_stripping(pdata); 2796 else 2797 xgbe_disable_rx_vlan_stripping(pdata); 2798 } 2799 2800 static u64 xgbe_mmc_read(struct xgbe_prv_data *pdata, unsigned int reg_lo) 2801 { 2802 bool read_hi; 2803 u64 val; 2804 2805 if (pdata->vdata->mmc_64bit) { 2806 switch (reg_lo) { 2807 /* These registers are always 32 bit */ 2808 case MMC_RXRUNTERROR: 2809 case MMC_RXJABBERERROR: 2810 case MMC_RXUNDERSIZE_G: 2811 case MMC_RXOVERSIZE_G: 2812 case MMC_RXWATCHDOGERROR: 2813 read_hi = false; 2814 break; 2815 2816 default: 2817 read_hi = true; 2818 } 2819 } else { 2820 switch (reg_lo) { 2821 /* These registers are always 64 bit */ 2822 case MMC_TXOCTETCOUNT_GB_LO: 2823 case MMC_TXOCTETCOUNT_G_LO: 2824 case MMC_RXOCTETCOUNT_GB_LO: 2825 case MMC_RXOCTETCOUNT_G_LO: 2826 read_hi = true; 2827 break; 2828 2829 default: 2830 read_hi = false; 2831 } 2832 } 2833 2834 val = XGMAC_IOREAD(pdata, reg_lo); 2835 2836 if (read_hi) 2837 val |= ((u64)XGMAC_IOREAD(pdata, reg_lo + 4) << 32); 2838 2839 return val; 2840 } 2841 2842 static void xgbe_tx_mmc_int(struct xgbe_prv_data *pdata) 2843 { 2844 struct xgbe_mmc_stats *stats = &pdata->mmc_stats; 2845 unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_TISR); 2846 2847 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXOCTETCOUNT_GB)) 2848 stats->txoctetcount_gb += 2849 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO); 2850 2851 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXFRAMECOUNT_GB)) 2852 stats->txframecount_gb += 2853 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO); 2854 2855 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXBROADCASTFRAMES_G)) 2856 stats->txbroadcastframes_g += 2857 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO); 2858 2859 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXMULTICASTFRAMES_G)) 2860 stats->txmulticastframes_g += 2861 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO); 2862 2863 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX64OCTETS_GB)) 2864 stats->tx64octets_gb += 2865 xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO); 2866 2867 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX65TO127OCTETS_GB)) 2868 stats->tx65to127octets_gb += 2869 xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO); 2870 2871 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX128TO255OCTETS_GB)) 2872 stats->tx128to255octets_gb += 2873 xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO); 2874 2875 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX256TO511OCTETS_GB)) 2876 stats->tx256to511octets_gb += 2877 xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO); 2878 2879 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX512TO1023OCTETS_GB)) 2880 stats->tx512to1023octets_gb += 2881 xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO); 2882 2883 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX1024TOMAXOCTETS_GB)) 2884 stats->tx1024tomaxoctets_gb += 2885 xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO); 2886 2887 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXUNICASTFRAMES_GB)) 2888 stats->txunicastframes_gb += 2889 xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO); 2890 2891 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXMULTICASTFRAMES_GB)) 2892 stats->txmulticastframes_gb += 2893 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO); 2894 2895 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXBROADCASTFRAMES_GB)) 2896 stats->txbroadcastframes_g += 2897 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO); 2898 2899 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXUNDERFLOWERROR)) 2900 stats->txunderflowerror += 2901 xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO); 2902 2903 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXOCTETCOUNT_G)) 2904 stats->txoctetcount_g += 2905 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO); 2906 2907 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXFRAMECOUNT_G)) 2908 stats->txframecount_g += 2909 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO); 2910 2911 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXPAUSEFRAMES)) 2912 stats->txpauseframes += 2913 xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO); 2914 2915 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXVLANFRAMES_G)) 2916 stats->txvlanframes_g += 2917 xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO); 2918 } 2919 2920 static void xgbe_rx_mmc_int(struct xgbe_prv_data *pdata) 2921 { 2922 struct xgbe_mmc_stats *stats = &pdata->mmc_stats; 2923 unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_RISR); 2924 2925 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXFRAMECOUNT_GB)) 2926 stats->rxframecount_gb += 2927 xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO); 2928 2929 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOCTETCOUNT_GB)) 2930 stats->rxoctetcount_gb += 2931 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO); 2932 2933 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOCTETCOUNT_G)) 2934 stats->rxoctetcount_g += 2935 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO); 2936 2937 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXBROADCASTFRAMES_G)) 2938 stats->rxbroadcastframes_g += 2939 xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO); 2940 2941 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXMULTICASTFRAMES_G)) 2942 stats->rxmulticastframes_g += 2943 xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO); 2944 2945 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXCRCERROR)) 2946 stats->rxcrcerror += 2947 xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO); 2948 2949 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXRUNTERROR)) 2950 stats->rxrunterror += 2951 xgbe_mmc_read(pdata, MMC_RXRUNTERROR); 2952 2953 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXJABBERERROR)) 2954 stats->rxjabbererror += 2955 xgbe_mmc_read(pdata, MMC_RXJABBERERROR); 2956 2957 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXUNDERSIZE_G)) 2958 stats->rxundersize_g += 2959 xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G); 2960 2961 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOVERSIZE_G)) 2962 stats->rxoversize_g += 2963 xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G); 2964 2965 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX64OCTETS_GB)) 2966 stats->rx64octets_gb += 2967 xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO); 2968 2969 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX65TO127OCTETS_GB)) 2970 stats->rx65to127octets_gb += 2971 xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO); 2972 2973 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX128TO255OCTETS_GB)) 2974 stats->rx128to255octets_gb += 2975 xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO); 2976 2977 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX256TO511OCTETS_GB)) 2978 stats->rx256to511octets_gb += 2979 xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO); 2980 2981 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX512TO1023OCTETS_GB)) 2982 stats->rx512to1023octets_gb += 2983 xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO); 2984 2985 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX1024TOMAXOCTETS_GB)) 2986 stats->rx1024tomaxoctets_gb += 2987 xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO); 2988 2989 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXUNICASTFRAMES_G)) 2990 stats->rxunicastframes_g += 2991 xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO); 2992 2993 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXLENGTHERROR)) 2994 stats->rxlengtherror += 2995 xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO); 2996 2997 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOUTOFRANGETYPE)) 2998 stats->rxoutofrangetype += 2999 xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO); 3000 3001 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXPAUSEFRAMES)) 3002 stats->rxpauseframes += 3003 xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO); 3004 3005 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXFIFOOVERFLOW)) 3006 stats->rxfifooverflow += 3007 xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO); 3008 3009 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXVLANFRAMES_GB)) 3010 stats->rxvlanframes_gb += 3011 xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO); 3012 3013 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXWATCHDOGERROR)) 3014 stats->rxwatchdogerror += 3015 xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR); 3016 } 3017 3018 static void xgbe_read_mmc_stats(struct xgbe_prv_data *pdata) 3019 { 3020 struct xgbe_mmc_stats *stats = &pdata->mmc_stats; 3021 3022 /* Freeze counters */ 3023 XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 1); 3024 3025 stats->txoctetcount_gb += 3026 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO); 3027 3028 stats->txframecount_gb += 3029 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO); 3030 3031 stats->txbroadcastframes_g += 3032 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO); 3033 3034 stats->txmulticastframes_g += 3035 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO); 3036 3037 stats->tx64octets_gb += 3038 xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO); 3039 3040 stats->tx65to127octets_gb += 3041 xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO); 3042 3043 stats->tx128to255octets_gb += 3044 xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO); 3045 3046 stats->tx256to511octets_gb += 3047 xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO); 3048 3049 stats->tx512to1023octets_gb += 3050 xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO); 3051 3052 stats->tx1024tomaxoctets_gb += 3053 xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO); 3054 3055 stats->txunicastframes_gb += 3056 xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO); 3057 3058 stats->txmulticastframes_gb += 3059 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO); 3060 3061 stats->txbroadcastframes_g += 3062 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO); 3063 3064 stats->txunderflowerror += 3065 xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO); 3066 3067 stats->txoctetcount_g += 3068 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO); 3069 3070 stats->txframecount_g += 3071 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO); 3072 3073 stats->txpauseframes += 3074 xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO); 3075 3076 stats->txvlanframes_g += 3077 xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO); 3078 3079 stats->rxframecount_gb += 3080 xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO); 3081 3082 stats->rxoctetcount_gb += 3083 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO); 3084 3085 stats->rxoctetcount_g += 3086 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO); 3087 3088 stats->rxbroadcastframes_g += 3089 xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO); 3090 3091 stats->rxmulticastframes_g += 3092 xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO); 3093 3094 stats->rxcrcerror += 3095 xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO); 3096 3097 stats->rxrunterror += 3098 xgbe_mmc_read(pdata, MMC_RXRUNTERROR); 3099 3100 stats->rxjabbererror += 3101 xgbe_mmc_read(pdata, MMC_RXJABBERERROR); 3102 3103 stats->rxundersize_g += 3104 xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G); 3105 3106 stats->rxoversize_g += 3107 xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G); 3108 3109 stats->rx64octets_gb += 3110 xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO); 3111 3112 stats->rx65to127octets_gb += 3113 xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO); 3114 3115 stats->rx128to255octets_gb += 3116 xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO); 3117 3118 stats->rx256to511octets_gb += 3119 xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO); 3120 3121 stats->rx512to1023octets_gb += 3122 xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO); 3123 3124 stats->rx1024tomaxoctets_gb += 3125 xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO); 3126 3127 stats->rxunicastframes_g += 3128 xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO); 3129 3130 stats->rxlengtherror += 3131 xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO); 3132 3133 stats->rxoutofrangetype += 3134 xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO); 3135 3136 stats->rxpauseframes += 3137 xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO); 3138 3139 stats->rxfifooverflow += 3140 xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO); 3141 3142 stats->rxvlanframes_gb += 3143 xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO); 3144 3145 stats->rxwatchdogerror += 3146 xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR); 3147 3148 /* Un-freeze counters */ 3149 XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 0); 3150 } 3151 3152 static void xgbe_config_mmc(struct xgbe_prv_data *pdata) 3153 { 3154 /* Set counters to reset on read */ 3155 XGMAC_IOWRITE_BITS(pdata, MMC_CR, ROR, 1); 3156 3157 /* Reset the counters */ 3158 XGMAC_IOWRITE_BITS(pdata, MMC_CR, CR, 1); 3159 } 3160 3161 static void xgbe_txq_prepare_tx_stop(struct xgbe_prv_data *pdata, 3162 unsigned int queue) 3163 { 3164 unsigned int tx_status; 3165 unsigned long tx_timeout; 3166 3167 /* The Tx engine cannot be stopped if it is actively processing 3168 * packets. Wait for the Tx queue to empty the Tx fifo. Don't 3169 * wait forever though... 3170 */ 3171 tx_timeout = jiffies + (XGBE_DMA_STOP_TIMEOUT * HZ); 3172 while (time_before(jiffies, tx_timeout)) { 3173 tx_status = XGMAC_MTL_IOREAD(pdata, queue, MTL_Q_TQDR); 3174 if ((XGMAC_GET_BITS(tx_status, MTL_Q_TQDR, TRCSTS) != 1) && 3175 (XGMAC_GET_BITS(tx_status, MTL_Q_TQDR, TXQSTS) == 0)) 3176 break; 3177 3178 usleep_range(500, 1000); 3179 } 3180 3181 if (!time_before(jiffies, tx_timeout)) 3182 netdev_info(pdata->netdev, 3183 "timed out waiting for Tx queue %u to empty\n", 3184 queue); 3185 } 3186 3187 static void xgbe_prepare_tx_stop(struct xgbe_prv_data *pdata, 3188 unsigned int queue) 3189 { 3190 unsigned int tx_dsr, tx_pos, tx_qidx; 3191 unsigned int tx_status; 3192 unsigned long tx_timeout; 3193 3194 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) > 0x20) 3195 return xgbe_txq_prepare_tx_stop(pdata, queue); 3196 3197 /* Calculate the status register to read and the position within */ 3198 if (queue < DMA_DSRX_FIRST_QUEUE) { 3199 tx_dsr = DMA_DSR0; 3200 tx_pos = (queue * DMA_DSR_Q_WIDTH) + DMA_DSR0_TPS_START; 3201 } else { 3202 tx_qidx = queue - DMA_DSRX_FIRST_QUEUE; 3203 3204 tx_dsr = DMA_DSR1 + ((tx_qidx / DMA_DSRX_QPR) * DMA_DSRX_INC); 3205 tx_pos = ((tx_qidx % DMA_DSRX_QPR) * DMA_DSR_Q_WIDTH) + 3206 DMA_DSRX_TPS_START; 3207 } 3208 3209 /* The Tx engine cannot be stopped if it is actively processing 3210 * descriptors. Wait for the Tx engine to enter the stopped or 3211 * suspended state. Don't wait forever though... 3212 */ 3213 tx_timeout = jiffies + (XGBE_DMA_STOP_TIMEOUT * HZ); 3214 while (time_before(jiffies, tx_timeout)) { 3215 tx_status = XGMAC_IOREAD(pdata, tx_dsr); 3216 tx_status = GET_BITS(tx_status, tx_pos, DMA_DSR_TPS_WIDTH); 3217 if ((tx_status == DMA_TPS_STOPPED) || 3218 (tx_status == DMA_TPS_SUSPENDED)) 3219 break; 3220 3221 usleep_range(500, 1000); 3222 } 3223 3224 if (!time_before(jiffies, tx_timeout)) 3225 netdev_info(pdata->netdev, 3226 "timed out waiting for Tx DMA channel %u to stop\n", 3227 queue); 3228 } 3229 3230 static void xgbe_enable_tx(struct xgbe_prv_data *pdata) 3231 { 3232 unsigned int i; 3233 3234 /* Enable each Tx DMA channel */ 3235 for (i = 0; i < pdata->channel_count; i++) { 3236 if (!pdata->channel[i]->tx_ring) 3237 break; 3238 3239 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 1); 3240 } 3241 3242 /* Enable each Tx queue */ 3243 for (i = 0; i < pdata->tx_q_count; i++) 3244 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, 3245 MTL_Q_ENABLED); 3246 3247 /* Enable MAC Tx */ 3248 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1); 3249 } 3250 3251 static void xgbe_disable_tx(struct xgbe_prv_data *pdata) 3252 { 3253 unsigned int i; 3254 3255 /* Prepare for Tx DMA channel stop */ 3256 for (i = 0; i < pdata->tx_q_count; i++) 3257 xgbe_prepare_tx_stop(pdata, i); 3258 3259 /* Disable MAC Tx */ 3260 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0); 3261 3262 /* Disable each Tx queue */ 3263 for (i = 0; i < pdata->tx_q_count; i++) 3264 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, 0); 3265 3266 /* Disable each Tx DMA channel */ 3267 for (i = 0; i < pdata->channel_count; i++) { 3268 if (!pdata->channel[i]->tx_ring) 3269 break; 3270 3271 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 0); 3272 } 3273 } 3274 3275 static void xgbe_prepare_rx_stop(struct xgbe_prv_data *pdata, 3276 unsigned int queue) 3277 { 3278 unsigned int rx_status; 3279 unsigned long rx_timeout; 3280 3281 /* The Rx engine cannot be stopped if it is actively processing 3282 * packets. Wait for the Rx queue to empty the Rx fifo. Don't 3283 * wait forever though... 3284 */ 3285 rx_timeout = jiffies + (XGBE_DMA_STOP_TIMEOUT * HZ); 3286 while (time_before(jiffies, rx_timeout)) { 3287 rx_status = XGMAC_MTL_IOREAD(pdata, queue, MTL_Q_RQDR); 3288 if ((XGMAC_GET_BITS(rx_status, MTL_Q_RQDR, PRXQ) == 0) && 3289 (XGMAC_GET_BITS(rx_status, MTL_Q_RQDR, RXQSTS) == 0)) 3290 break; 3291 3292 usleep_range(500, 1000); 3293 } 3294 3295 if (!time_before(jiffies, rx_timeout)) 3296 netdev_info(pdata->netdev, 3297 "timed out waiting for Rx queue %u to empty\n", 3298 queue); 3299 } 3300 3301 static void xgbe_enable_rx(struct xgbe_prv_data *pdata) 3302 { 3303 unsigned int reg_val, i; 3304 3305 /* Enable each Rx DMA channel */ 3306 for (i = 0; i < pdata->channel_count; i++) { 3307 if (!pdata->channel[i]->rx_ring) 3308 break; 3309 3310 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 1); 3311 } 3312 3313 /* Enable each Rx queue */ 3314 reg_val = 0; 3315 for (i = 0; i < pdata->rx_q_count; i++) 3316 reg_val |= (0x02 << (i << 1)); 3317 XGMAC_IOWRITE(pdata, MAC_RQC0R, reg_val); 3318 3319 /* Enable MAC Rx */ 3320 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 1); 3321 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 1); 3322 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 1); 3323 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 1); 3324 } 3325 3326 static void xgbe_disable_rx(struct xgbe_prv_data *pdata) 3327 { 3328 unsigned int i; 3329 3330 /* Disable MAC Rx */ 3331 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 0); 3332 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 0); 3333 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 0); 3334 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 0); 3335 3336 /* Prepare for Rx DMA channel stop */ 3337 for (i = 0; i < pdata->rx_q_count; i++) 3338 xgbe_prepare_rx_stop(pdata, i); 3339 3340 /* Disable each Rx queue */ 3341 XGMAC_IOWRITE(pdata, MAC_RQC0R, 0); 3342 3343 /* Disable each Rx DMA channel */ 3344 for (i = 0; i < pdata->channel_count; i++) { 3345 if (!pdata->channel[i]->rx_ring) 3346 break; 3347 3348 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 0); 3349 } 3350 } 3351 3352 static void xgbe_powerup_tx(struct xgbe_prv_data *pdata) 3353 { 3354 unsigned int i; 3355 3356 /* Enable each Tx DMA channel */ 3357 for (i = 0; i < pdata->channel_count; i++) { 3358 if (!pdata->channel[i]->tx_ring) 3359 break; 3360 3361 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 1); 3362 } 3363 3364 /* Enable MAC Tx */ 3365 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1); 3366 } 3367 3368 static void xgbe_powerdown_tx(struct xgbe_prv_data *pdata) 3369 { 3370 unsigned int i; 3371 3372 /* Prepare for Tx DMA channel stop */ 3373 for (i = 0; i < pdata->tx_q_count; i++) 3374 xgbe_prepare_tx_stop(pdata, i); 3375 3376 /* Disable MAC Tx */ 3377 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0); 3378 3379 /* Disable each Tx DMA channel */ 3380 for (i = 0; i < pdata->channel_count; i++) { 3381 if (!pdata->channel[i]->tx_ring) 3382 break; 3383 3384 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 0); 3385 } 3386 } 3387 3388 static void xgbe_powerup_rx(struct xgbe_prv_data *pdata) 3389 { 3390 unsigned int i; 3391 3392 /* Enable each Rx DMA channel */ 3393 for (i = 0; i < pdata->channel_count; i++) { 3394 if (!pdata->channel[i]->rx_ring) 3395 break; 3396 3397 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 1); 3398 } 3399 } 3400 3401 static void xgbe_powerdown_rx(struct xgbe_prv_data *pdata) 3402 { 3403 unsigned int i; 3404 3405 /* Disable each Rx DMA channel */ 3406 for (i = 0; i < pdata->channel_count; i++) { 3407 if (!pdata->channel[i]->rx_ring) 3408 break; 3409 3410 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 0); 3411 } 3412 } 3413 3414 static int xgbe_init(struct xgbe_prv_data *pdata) 3415 { 3416 struct xgbe_desc_if *desc_if = &pdata->desc_if; 3417 int ret; 3418 3419 DBGPR("-->xgbe_init\n"); 3420 3421 /* Flush Tx queues */ 3422 ret = xgbe_flush_tx_queues(pdata); 3423 if (ret) { 3424 netdev_err(pdata->netdev, "error flushing TX queues\n"); 3425 return ret; 3426 } 3427 3428 /* 3429 * Initialize DMA related features 3430 */ 3431 xgbe_config_dma_bus(pdata); 3432 xgbe_config_dma_cache(pdata); 3433 xgbe_config_osp_mode(pdata); 3434 xgbe_config_pbl_val(pdata); 3435 xgbe_config_rx_coalesce(pdata); 3436 xgbe_config_tx_coalesce(pdata); 3437 xgbe_config_rx_buffer_size(pdata); 3438 xgbe_config_tso_mode(pdata); 3439 xgbe_config_sph_mode(pdata); 3440 xgbe_config_rss(pdata); 3441 desc_if->wrapper_tx_desc_init(pdata); 3442 desc_if->wrapper_rx_desc_init(pdata); 3443 xgbe_enable_dma_interrupts(pdata); 3444 3445 /* 3446 * Initialize MTL related features 3447 */ 3448 xgbe_config_mtl_mode(pdata); 3449 xgbe_config_queue_mapping(pdata); 3450 xgbe_config_tsf_mode(pdata, pdata->tx_sf_mode); 3451 xgbe_config_rsf_mode(pdata, pdata->rx_sf_mode); 3452 xgbe_config_tx_threshold(pdata, pdata->tx_threshold); 3453 xgbe_config_rx_threshold(pdata, pdata->rx_threshold); 3454 xgbe_config_tx_fifo_size(pdata); 3455 xgbe_config_rx_fifo_size(pdata); 3456 /*TODO: Error Packet and undersized good Packet forwarding enable 3457 (FEP and FUP) 3458 */ 3459 xgbe_config_dcb_tc(pdata); 3460 xgbe_enable_mtl_interrupts(pdata); 3461 3462 /* 3463 * Initialize MAC related features 3464 */ 3465 xgbe_config_mac_address(pdata); 3466 xgbe_config_rx_mode(pdata); 3467 xgbe_config_jumbo_enable(pdata); 3468 xgbe_config_flow_control(pdata); 3469 xgbe_config_mac_speed(pdata); 3470 xgbe_config_checksum_offload(pdata); 3471 xgbe_config_vlan_support(pdata); 3472 xgbe_config_mmc(pdata); 3473 xgbe_enable_mac_interrupts(pdata); 3474 3475 /* 3476 * Initialize ECC related features 3477 */ 3478 xgbe_enable_ecc_interrupts(pdata); 3479 3480 DBGPR("<--xgbe_init\n"); 3481 3482 return 0; 3483 } 3484 3485 void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *hw_if) 3486 { 3487 DBGPR("-->xgbe_init_function_ptrs\n"); 3488 3489 hw_if->tx_complete = xgbe_tx_complete; 3490 3491 hw_if->set_mac_address = xgbe_set_mac_address; 3492 hw_if->config_rx_mode = xgbe_config_rx_mode; 3493 3494 hw_if->enable_rx_csum = xgbe_enable_rx_csum; 3495 hw_if->disable_rx_csum = xgbe_disable_rx_csum; 3496 3497 hw_if->enable_rx_vlan_stripping = xgbe_enable_rx_vlan_stripping; 3498 hw_if->disable_rx_vlan_stripping = xgbe_disable_rx_vlan_stripping; 3499 hw_if->enable_rx_vlan_filtering = xgbe_enable_rx_vlan_filtering; 3500 hw_if->disable_rx_vlan_filtering = xgbe_disable_rx_vlan_filtering; 3501 hw_if->update_vlan_hash_table = xgbe_update_vlan_hash_table; 3502 3503 hw_if->read_mmd_regs = xgbe_read_mmd_regs; 3504 hw_if->write_mmd_regs = xgbe_write_mmd_regs; 3505 3506 hw_if->set_speed = xgbe_set_speed; 3507 3508 hw_if->set_ext_mii_mode = xgbe_set_ext_mii_mode; 3509 hw_if->read_ext_mii_regs_c22 = xgbe_read_ext_mii_regs_c22; 3510 hw_if->write_ext_mii_regs_c22 = xgbe_write_ext_mii_regs_c22; 3511 hw_if->read_ext_mii_regs_c45 = xgbe_read_ext_mii_regs_c45; 3512 hw_if->write_ext_mii_regs_c45 = xgbe_write_ext_mii_regs_c45; 3513 3514 hw_if->set_gpio = xgbe_set_gpio; 3515 hw_if->clr_gpio = xgbe_clr_gpio; 3516 3517 hw_if->enable_tx = xgbe_enable_tx; 3518 hw_if->disable_tx = xgbe_disable_tx; 3519 hw_if->enable_rx = xgbe_enable_rx; 3520 hw_if->disable_rx = xgbe_disable_rx; 3521 3522 hw_if->powerup_tx = xgbe_powerup_tx; 3523 hw_if->powerdown_tx = xgbe_powerdown_tx; 3524 hw_if->powerup_rx = xgbe_powerup_rx; 3525 hw_if->powerdown_rx = xgbe_powerdown_rx; 3526 3527 hw_if->dev_xmit = xgbe_dev_xmit; 3528 hw_if->dev_read = xgbe_dev_read; 3529 hw_if->enable_int = xgbe_enable_int; 3530 hw_if->disable_int = xgbe_disable_int; 3531 hw_if->init = xgbe_init; 3532 hw_if->exit = xgbe_exit; 3533 3534 /* Descriptor related Sequences have to be initialized here */ 3535 hw_if->tx_desc_init = xgbe_tx_desc_init; 3536 hw_if->rx_desc_init = xgbe_rx_desc_init; 3537 hw_if->tx_desc_reset = xgbe_tx_desc_reset; 3538 hw_if->rx_desc_reset = xgbe_rx_desc_reset; 3539 hw_if->is_last_desc = xgbe_is_last_desc; 3540 hw_if->is_context_desc = xgbe_is_context_desc; 3541 hw_if->tx_start_xmit = xgbe_tx_start_xmit; 3542 3543 /* For FLOW ctrl */ 3544 hw_if->config_tx_flow_control = xgbe_config_tx_flow_control; 3545 hw_if->config_rx_flow_control = xgbe_config_rx_flow_control; 3546 3547 /* For RX coalescing */ 3548 hw_if->config_rx_coalesce = xgbe_config_rx_coalesce; 3549 hw_if->config_tx_coalesce = xgbe_config_tx_coalesce; 3550 hw_if->usec_to_riwt = xgbe_usec_to_riwt; 3551 hw_if->riwt_to_usec = xgbe_riwt_to_usec; 3552 3553 /* For RX and TX threshold config */ 3554 hw_if->config_rx_threshold = xgbe_config_rx_threshold; 3555 hw_if->config_tx_threshold = xgbe_config_tx_threshold; 3556 3557 /* For RX and TX Store and Forward Mode config */ 3558 hw_if->config_rsf_mode = xgbe_config_rsf_mode; 3559 hw_if->config_tsf_mode = xgbe_config_tsf_mode; 3560 3561 /* For TX DMA Operating on Second Frame config */ 3562 hw_if->config_osp_mode = xgbe_config_osp_mode; 3563 3564 /* For MMC statistics support */ 3565 hw_if->tx_mmc_int = xgbe_tx_mmc_int; 3566 hw_if->rx_mmc_int = xgbe_rx_mmc_int; 3567 hw_if->read_mmc_stats = xgbe_read_mmc_stats; 3568 3569 /* For PTP config */ 3570 hw_if->config_tstamp = xgbe_config_tstamp; 3571 hw_if->update_tstamp_addend = xgbe_update_tstamp_addend; 3572 hw_if->set_tstamp_time = xgbe_set_tstamp_time; 3573 hw_if->get_tstamp_time = xgbe_get_tstamp_time; 3574 hw_if->get_tx_tstamp = xgbe_get_tx_tstamp; 3575 3576 /* For Data Center Bridging config */ 3577 hw_if->config_tc = xgbe_config_tc; 3578 hw_if->config_dcb_tc = xgbe_config_dcb_tc; 3579 hw_if->config_dcb_pfc = xgbe_config_dcb_pfc; 3580 3581 /* For Receive Side Scaling */ 3582 hw_if->enable_rss = xgbe_enable_rss; 3583 hw_if->disable_rss = xgbe_disable_rss; 3584 hw_if->set_rss_hash_key = xgbe_set_rss_hash_key; 3585 hw_if->set_rss_lookup_table = xgbe_set_rss_lookup_table; 3586 3587 /* For ECC */ 3588 hw_if->disable_ecc_ded = xgbe_disable_ecc_ded; 3589 hw_if->disable_ecc_sec = xgbe_disable_ecc_sec; 3590 3591 /* For VXLAN */ 3592 hw_if->enable_vxlan = xgbe_enable_vxlan; 3593 hw_if->disable_vxlan = xgbe_disable_vxlan; 3594 hw_if->set_vxlan_id = xgbe_set_vxlan_id; 3595 3596 DBGPR("<--xgbe_init_function_ptrs\n"); 3597 } 3598