1 /* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */ 2 /* 3 * Copyright 1996-1999 Thomas Bogendoerfer 4 * 5 * Derived from the lance driver written 1993,1994,1995 by Donald Becker. 6 * 7 * Copyright 1993 United States Government as represented by the 8 * Director, National Security Agency. 9 * 10 * This software may be used and distributed according to the terms 11 * of the GNU General Public License, incorporated herein by reference. 12 * 13 * This driver is for PCnet32 and PCnetPCI based ethercards 14 */ 15 /************************************************************************** 16 * 23 Oct, 2000. 17 * Fixed a few bugs, related to running the controller in 32bit mode. 18 * 19 * Carsten Langgaard, carstenl@mips.com 20 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. 21 * 22 *************************************************************************/ 23 24 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 25 26 #define DRV_NAME "pcnet32" 27 #define DRV_VERSION "1.35" 28 #define DRV_RELDATE "21.Apr.2008" 29 #define PFX DRV_NAME ": " 30 31 static const char *const version = 32 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " tsbogend@alpha.franken.de\n"; 33 34 #include <linux/module.h> 35 #include <linux/kernel.h> 36 #include <linux/sched.h> 37 #include <linux/string.h> 38 #include <linux/errno.h> 39 #include <linux/ioport.h> 40 #include <linux/slab.h> 41 #include <linux/interrupt.h> 42 #include <linux/pci.h> 43 #include <linux/delay.h> 44 #include <linux/init.h> 45 #include <linux/ethtool.h> 46 #include <linux/mii.h> 47 #include <linux/crc32.h> 48 #include <linux/netdevice.h> 49 #include <linux/etherdevice.h> 50 #include <linux/if_ether.h> 51 #include <linux/skbuff.h> 52 #include <linux/spinlock.h> 53 #include <linux/moduleparam.h> 54 #include <linux/bitops.h> 55 #include <linux/io.h> 56 #include <linux/uaccess.h> 57 58 #include <asm/dma.h> 59 #include <asm/irq.h> 60 61 /* 62 * PCI device identifiers for "new style" Linux PCI Device Drivers 63 */ 64 static DEFINE_PCI_DEVICE_TABLE(pcnet32_pci_tbl) = { 65 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME), }, 66 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE), }, 67 68 /* 69 * Adapters that were sold with IBM's RS/6000 or pSeries hardware have 70 * the incorrect vendor id. 71 */ 72 { PCI_DEVICE(PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE), 73 .class = (PCI_CLASS_NETWORK_ETHERNET << 8), .class_mask = 0xffff00, }, 74 75 { } /* terminate list */ 76 }; 77 78 MODULE_DEVICE_TABLE(pci, pcnet32_pci_tbl); 79 80 static int cards_found; 81 82 /* 83 * VLB I/O addresses 84 */ 85 static unsigned int pcnet32_portlist[] = 86 { 0x300, 0x320, 0x340, 0x360, 0 }; 87 88 static int pcnet32_debug; 89 static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */ 90 static int pcnet32vlb; /* check for VLB cards ? */ 91 92 static struct net_device *pcnet32_dev; 93 94 static int max_interrupt_work = 2; 95 static int rx_copybreak = 200; 96 97 #define PCNET32_PORT_AUI 0x00 98 #define PCNET32_PORT_10BT 0x01 99 #define PCNET32_PORT_GPSI 0x02 100 #define PCNET32_PORT_MII 0x03 101 102 #define PCNET32_PORT_PORTSEL 0x03 103 #define PCNET32_PORT_ASEL 0x04 104 #define PCNET32_PORT_100 0x40 105 #define PCNET32_PORT_FD 0x80 106 107 #define PCNET32_DMA_MASK 0xffffffff 108 109 #define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ)) 110 #define PCNET32_BLINK_TIMEOUT (jiffies + (HZ/4)) 111 112 /* 113 * table to translate option values from tulip 114 * to internal options 115 */ 116 static const unsigned char options_mapping[] = { 117 PCNET32_PORT_ASEL, /* 0 Auto-select */ 118 PCNET32_PORT_AUI, /* 1 BNC/AUI */ 119 PCNET32_PORT_AUI, /* 2 AUI/BNC */ 120 PCNET32_PORT_ASEL, /* 3 not supported */ 121 PCNET32_PORT_10BT | PCNET32_PORT_FD, /* 4 10baseT-FD */ 122 PCNET32_PORT_ASEL, /* 5 not supported */ 123 PCNET32_PORT_ASEL, /* 6 not supported */ 124 PCNET32_PORT_ASEL, /* 7 not supported */ 125 PCNET32_PORT_ASEL, /* 8 not supported */ 126 PCNET32_PORT_MII, /* 9 MII 10baseT */ 127 PCNET32_PORT_MII | PCNET32_PORT_FD, /* 10 MII 10baseT-FD */ 128 PCNET32_PORT_MII, /* 11 MII (autosel) */ 129 PCNET32_PORT_10BT, /* 12 10BaseT */ 130 PCNET32_PORT_MII | PCNET32_PORT_100, /* 13 MII 100BaseTx */ 131 /* 14 MII 100BaseTx-FD */ 132 PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD, 133 PCNET32_PORT_ASEL /* 15 not supported */ 134 }; 135 136 static const char pcnet32_gstrings_test[][ETH_GSTRING_LEN] = { 137 "Loopback test (offline)" 138 }; 139 140 #define PCNET32_TEST_LEN ARRAY_SIZE(pcnet32_gstrings_test) 141 142 #define PCNET32_NUM_REGS 136 143 144 #define MAX_UNITS 8 /* More are supported, limit only on options */ 145 static int options[MAX_UNITS]; 146 static int full_duplex[MAX_UNITS]; 147 static int homepna[MAX_UNITS]; 148 149 /* 150 * Theory of Operation 151 * 152 * This driver uses the same software structure as the normal lance 153 * driver. So look for a verbose description in lance.c. The differences 154 * to the normal lance driver is the use of the 32bit mode of PCnet32 155 * and PCnetPCI chips. Because these chips are 32bit chips, there is no 156 * 16MB limitation and we don't need bounce buffers. 157 */ 158 159 /* 160 * Set the number of Tx and Rx buffers, using Log_2(# buffers). 161 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers. 162 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4). 163 */ 164 #ifndef PCNET32_LOG_TX_BUFFERS 165 #define PCNET32_LOG_TX_BUFFERS 4 166 #define PCNET32_LOG_RX_BUFFERS 5 167 #define PCNET32_LOG_MAX_TX_BUFFERS 9 /* 2^9 == 512 */ 168 #define PCNET32_LOG_MAX_RX_BUFFERS 9 169 #endif 170 171 #define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS)) 172 #define TX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_TX_BUFFERS)) 173 174 #define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS)) 175 #define RX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_RX_BUFFERS)) 176 177 #define PKT_BUF_SKB 1544 178 /* actual buffer length after being aligned */ 179 #define PKT_BUF_SIZE (PKT_BUF_SKB - NET_IP_ALIGN) 180 /* chip wants twos complement of the (aligned) buffer length */ 181 #define NEG_BUF_SIZE (NET_IP_ALIGN - PKT_BUF_SKB) 182 183 /* Offsets from base I/O address. */ 184 #define PCNET32_WIO_RDP 0x10 185 #define PCNET32_WIO_RAP 0x12 186 #define PCNET32_WIO_RESET 0x14 187 #define PCNET32_WIO_BDP 0x16 188 189 #define PCNET32_DWIO_RDP 0x10 190 #define PCNET32_DWIO_RAP 0x14 191 #define PCNET32_DWIO_RESET 0x18 192 #define PCNET32_DWIO_BDP 0x1C 193 194 #define PCNET32_TOTAL_SIZE 0x20 195 196 #define CSR0 0 197 #define CSR0_INIT 0x1 198 #define CSR0_START 0x2 199 #define CSR0_STOP 0x4 200 #define CSR0_TXPOLL 0x8 201 #define CSR0_INTEN 0x40 202 #define CSR0_IDON 0x0100 203 #define CSR0_NORMAL (CSR0_START | CSR0_INTEN) 204 #define PCNET32_INIT_LOW 1 205 #define PCNET32_INIT_HIGH 2 206 #define CSR3 3 207 #define CSR4 4 208 #define CSR5 5 209 #define CSR5_SUSPEND 0x0001 210 #define CSR15 15 211 #define PCNET32_MC_FILTER 8 212 213 #define PCNET32_79C970A 0x2621 214 215 /* The PCNET32 Rx and Tx ring descriptors. */ 216 struct pcnet32_rx_head { 217 __le32 base; 218 __le16 buf_length; /* two`s complement of length */ 219 __le16 status; 220 __le32 msg_length; 221 __le32 reserved; 222 }; 223 224 struct pcnet32_tx_head { 225 __le32 base; 226 __le16 length; /* two`s complement of length */ 227 __le16 status; 228 __le32 misc; 229 __le32 reserved; 230 }; 231 232 /* The PCNET32 32-Bit initialization block, described in databook. */ 233 struct pcnet32_init_block { 234 __le16 mode; 235 __le16 tlen_rlen; 236 u8 phys_addr[6]; 237 __le16 reserved; 238 __le32 filter[2]; 239 /* Receive and transmit ring base, along with extra bits. */ 240 __le32 rx_ring; 241 __le32 tx_ring; 242 }; 243 244 /* PCnet32 access functions */ 245 struct pcnet32_access { 246 u16 (*read_csr) (unsigned long, int); 247 void (*write_csr) (unsigned long, int, u16); 248 u16 (*read_bcr) (unsigned long, int); 249 void (*write_bcr) (unsigned long, int, u16); 250 u16 (*read_rap) (unsigned long); 251 void (*write_rap) (unsigned long, u16); 252 void (*reset) (unsigned long); 253 }; 254 255 /* 256 * The first field of pcnet32_private is read by the ethernet device 257 * so the structure should be allocated using pci_alloc_consistent(). 258 */ 259 struct pcnet32_private { 260 struct pcnet32_init_block *init_block; 261 /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */ 262 struct pcnet32_rx_head *rx_ring; 263 struct pcnet32_tx_head *tx_ring; 264 dma_addr_t init_dma_addr;/* DMA address of beginning of the init block, 265 returned by pci_alloc_consistent */ 266 struct pci_dev *pci_dev; 267 const char *name; 268 /* The saved address of a sent-in-place packet/buffer, for skfree(). */ 269 struct sk_buff **tx_skbuff; 270 struct sk_buff **rx_skbuff; 271 dma_addr_t *tx_dma_addr; 272 dma_addr_t *rx_dma_addr; 273 const struct pcnet32_access *a; 274 spinlock_t lock; /* Guard lock */ 275 unsigned int cur_rx, cur_tx; /* The next free ring entry */ 276 unsigned int rx_ring_size; /* current rx ring size */ 277 unsigned int tx_ring_size; /* current tx ring size */ 278 unsigned int rx_mod_mask; /* rx ring modular mask */ 279 unsigned int tx_mod_mask; /* tx ring modular mask */ 280 unsigned short rx_len_bits; 281 unsigned short tx_len_bits; 282 dma_addr_t rx_ring_dma_addr; 283 dma_addr_t tx_ring_dma_addr; 284 unsigned int dirty_rx, /* ring entries to be freed. */ 285 dirty_tx; 286 287 struct net_device *dev; 288 struct napi_struct napi; 289 char tx_full; 290 char phycount; /* number of phys found */ 291 int options; 292 unsigned int shared_irq:1, /* shared irq possible */ 293 dxsuflo:1, /* disable transmit stop on uflo */ 294 mii:1; /* mii port available */ 295 struct net_device *next; 296 struct mii_if_info mii_if; 297 struct timer_list watchdog_timer; 298 u32 msg_enable; /* debug message level */ 299 300 /* each bit indicates an available PHY */ 301 u32 phymask; 302 unsigned short chip_version; /* which variant this is */ 303 304 /* saved registers during ethtool blink */ 305 u16 save_regs[4]; 306 }; 307 308 static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *); 309 static int pcnet32_probe1(unsigned long, int, struct pci_dev *); 310 static int pcnet32_open(struct net_device *); 311 static int pcnet32_init_ring(struct net_device *); 312 static netdev_tx_t pcnet32_start_xmit(struct sk_buff *, 313 struct net_device *); 314 static void pcnet32_tx_timeout(struct net_device *dev); 315 static irqreturn_t pcnet32_interrupt(int, void *); 316 static int pcnet32_close(struct net_device *); 317 static struct net_device_stats *pcnet32_get_stats(struct net_device *); 318 static void pcnet32_load_multicast(struct net_device *dev); 319 static void pcnet32_set_multicast_list(struct net_device *); 320 static int pcnet32_ioctl(struct net_device *, struct ifreq *, int); 321 static void pcnet32_watchdog(struct net_device *); 322 static int mdio_read(struct net_device *dev, int phy_id, int reg_num); 323 static void mdio_write(struct net_device *dev, int phy_id, int reg_num, 324 int val); 325 static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits); 326 static void pcnet32_ethtool_test(struct net_device *dev, 327 struct ethtool_test *eth_test, u64 * data); 328 static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1); 329 static int pcnet32_get_regs_len(struct net_device *dev); 330 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs, 331 void *ptr); 332 static void pcnet32_purge_tx_ring(struct net_device *dev); 333 static int pcnet32_alloc_ring(struct net_device *dev, const char *name); 334 static void pcnet32_free_ring(struct net_device *dev); 335 static void pcnet32_check_media(struct net_device *dev, int verbose); 336 337 static u16 pcnet32_wio_read_csr(unsigned long addr, int index) 338 { 339 outw(index, addr + PCNET32_WIO_RAP); 340 return inw(addr + PCNET32_WIO_RDP); 341 } 342 343 static void pcnet32_wio_write_csr(unsigned long addr, int index, u16 val) 344 { 345 outw(index, addr + PCNET32_WIO_RAP); 346 outw(val, addr + PCNET32_WIO_RDP); 347 } 348 349 static u16 pcnet32_wio_read_bcr(unsigned long addr, int index) 350 { 351 outw(index, addr + PCNET32_WIO_RAP); 352 return inw(addr + PCNET32_WIO_BDP); 353 } 354 355 static void pcnet32_wio_write_bcr(unsigned long addr, int index, u16 val) 356 { 357 outw(index, addr + PCNET32_WIO_RAP); 358 outw(val, addr + PCNET32_WIO_BDP); 359 } 360 361 static u16 pcnet32_wio_read_rap(unsigned long addr) 362 { 363 return inw(addr + PCNET32_WIO_RAP); 364 } 365 366 static void pcnet32_wio_write_rap(unsigned long addr, u16 val) 367 { 368 outw(val, addr + PCNET32_WIO_RAP); 369 } 370 371 static void pcnet32_wio_reset(unsigned long addr) 372 { 373 inw(addr + PCNET32_WIO_RESET); 374 } 375 376 static int pcnet32_wio_check(unsigned long addr) 377 { 378 outw(88, addr + PCNET32_WIO_RAP); 379 return inw(addr + PCNET32_WIO_RAP) == 88; 380 } 381 382 static const struct pcnet32_access pcnet32_wio = { 383 .read_csr = pcnet32_wio_read_csr, 384 .write_csr = pcnet32_wio_write_csr, 385 .read_bcr = pcnet32_wio_read_bcr, 386 .write_bcr = pcnet32_wio_write_bcr, 387 .read_rap = pcnet32_wio_read_rap, 388 .write_rap = pcnet32_wio_write_rap, 389 .reset = pcnet32_wio_reset 390 }; 391 392 static u16 pcnet32_dwio_read_csr(unsigned long addr, int index) 393 { 394 outl(index, addr + PCNET32_DWIO_RAP); 395 return inl(addr + PCNET32_DWIO_RDP) & 0xffff; 396 } 397 398 static void pcnet32_dwio_write_csr(unsigned long addr, int index, u16 val) 399 { 400 outl(index, addr + PCNET32_DWIO_RAP); 401 outl(val, addr + PCNET32_DWIO_RDP); 402 } 403 404 static u16 pcnet32_dwio_read_bcr(unsigned long addr, int index) 405 { 406 outl(index, addr + PCNET32_DWIO_RAP); 407 return inl(addr + PCNET32_DWIO_BDP) & 0xffff; 408 } 409 410 static void pcnet32_dwio_write_bcr(unsigned long addr, int index, u16 val) 411 { 412 outl(index, addr + PCNET32_DWIO_RAP); 413 outl(val, addr + PCNET32_DWIO_BDP); 414 } 415 416 static u16 pcnet32_dwio_read_rap(unsigned long addr) 417 { 418 return inl(addr + PCNET32_DWIO_RAP) & 0xffff; 419 } 420 421 static void pcnet32_dwio_write_rap(unsigned long addr, u16 val) 422 { 423 outl(val, addr + PCNET32_DWIO_RAP); 424 } 425 426 static void pcnet32_dwio_reset(unsigned long addr) 427 { 428 inl(addr + PCNET32_DWIO_RESET); 429 } 430 431 static int pcnet32_dwio_check(unsigned long addr) 432 { 433 outl(88, addr + PCNET32_DWIO_RAP); 434 return (inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88; 435 } 436 437 static const struct pcnet32_access pcnet32_dwio = { 438 .read_csr = pcnet32_dwio_read_csr, 439 .write_csr = pcnet32_dwio_write_csr, 440 .read_bcr = pcnet32_dwio_read_bcr, 441 .write_bcr = pcnet32_dwio_write_bcr, 442 .read_rap = pcnet32_dwio_read_rap, 443 .write_rap = pcnet32_dwio_write_rap, 444 .reset = pcnet32_dwio_reset 445 }; 446 447 static void pcnet32_netif_stop(struct net_device *dev) 448 { 449 struct pcnet32_private *lp = netdev_priv(dev); 450 451 dev->trans_start = jiffies; /* prevent tx timeout */ 452 napi_disable(&lp->napi); 453 netif_tx_disable(dev); 454 } 455 456 static void pcnet32_netif_start(struct net_device *dev) 457 { 458 struct pcnet32_private *lp = netdev_priv(dev); 459 ulong ioaddr = dev->base_addr; 460 u16 val; 461 462 netif_wake_queue(dev); 463 val = lp->a->read_csr(ioaddr, CSR3); 464 val &= 0x00ff; 465 lp->a->write_csr(ioaddr, CSR3, val); 466 napi_enable(&lp->napi); 467 } 468 469 /* 470 * Allocate space for the new sized tx ring. 471 * Free old resources 472 * Save new resources. 473 * Any failure keeps old resources. 474 * Must be called with lp->lock held. 475 */ 476 static void pcnet32_realloc_tx_ring(struct net_device *dev, 477 struct pcnet32_private *lp, 478 unsigned int size) 479 { 480 dma_addr_t new_ring_dma_addr; 481 dma_addr_t *new_dma_addr_list; 482 struct pcnet32_tx_head *new_tx_ring; 483 struct sk_buff **new_skb_list; 484 485 pcnet32_purge_tx_ring(dev); 486 487 new_tx_ring = pci_alloc_consistent(lp->pci_dev, 488 sizeof(struct pcnet32_tx_head) * 489 (1 << size), 490 &new_ring_dma_addr); 491 if (new_tx_ring == NULL) { 492 netif_err(lp, drv, dev, "Consistent memory allocation failed\n"); 493 return; 494 } 495 memset(new_tx_ring, 0, sizeof(struct pcnet32_tx_head) * (1 << size)); 496 497 new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t), 498 GFP_ATOMIC); 499 if (!new_dma_addr_list) { 500 netif_err(lp, drv, dev, "Memory allocation failed\n"); 501 goto free_new_tx_ring; 502 } 503 504 new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *), 505 GFP_ATOMIC); 506 if (!new_skb_list) { 507 netif_err(lp, drv, dev, "Memory allocation failed\n"); 508 goto free_new_lists; 509 } 510 511 kfree(lp->tx_skbuff); 512 kfree(lp->tx_dma_addr); 513 pci_free_consistent(lp->pci_dev, 514 sizeof(struct pcnet32_tx_head) * 515 lp->tx_ring_size, lp->tx_ring, 516 lp->tx_ring_dma_addr); 517 518 lp->tx_ring_size = (1 << size); 519 lp->tx_mod_mask = lp->tx_ring_size - 1; 520 lp->tx_len_bits = (size << 12); 521 lp->tx_ring = new_tx_ring; 522 lp->tx_ring_dma_addr = new_ring_dma_addr; 523 lp->tx_dma_addr = new_dma_addr_list; 524 lp->tx_skbuff = new_skb_list; 525 return; 526 527 free_new_lists: 528 kfree(new_dma_addr_list); 529 free_new_tx_ring: 530 pci_free_consistent(lp->pci_dev, 531 sizeof(struct pcnet32_tx_head) * 532 (1 << size), 533 new_tx_ring, 534 new_ring_dma_addr); 535 } 536 537 /* 538 * Allocate space for the new sized rx ring. 539 * Re-use old receive buffers. 540 * alloc extra buffers 541 * free unneeded buffers 542 * free unneeded buffers 543 * Save new resources. 544 * Any failure keeps old resources. 545 * Must be called with lp->lock held. 546 */ 547 static void pcnet32_realloc_rx_ring(struct net_device *dev, 548 struct pcnet32_private *lp, 549 unsigned int size) 550 { 551 dma_addr_t new_ring_dma_addr; 552 dma_addr_t *new_dma_addr_list; 553 struct pcnet32_rx_head *new_rx_ring; 554 struct sk_buff **new_skb_list; 555 int new, overlap; 556 557 new_rx_ring = pci_alloc_consistent(lp->pci_dev, 558 sizeof(struct pcnet32_rx_head) * 559 (1 << size), 560 &new_ring_dma_addr); 561 if (new_rx_ring == NULL) { 562 netif_err(lp, drv, dev, "Consistent memory allocation failed\n"); 563 return; 564 } 565 memset(new_rx_ring, 0, sizeof(struct pcnet32_rx_head) * (1 << size)); 566 567 new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t), 568 GFP_ATOMIC); 569 if (!new_dma_addr_list) { 570 netif_err(lp, drv, dev, "Memory allocation failed\n"); 571 goto free_new_rx_ring; 572 } 573 574 new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *), 575 GFP_ATOMIC); 576 if (!new_skb_list) { 577 netif_err(lp, drv, dev, "Memory allocation failed\n"); 578 goto free_new_lists; 579 } 580 581 /* first copy the current receive buffers */ 582 overlap = min(size, lp->rx_ring_size); 583 for (new = 0; new < overlap; new++) { 584 new_rx_ring[new] = lp->rx_ring[new]; 585 new_dma_addr_list[new] = lp->rx_dma_addr[new]; 586 new_skb_list[new] = lp->rx_skbuff[new]; 587 } 588 /* now allocate any new buffers needed */ 589 for (; new < size; new++) { 590 struct sk_buff *rx_skbuff; 591 new_skb_list[new] = dev_alloc_skb(PKT_BUF_SKB); 592 rx_skbuff = new_skb_list[new]; 593 if (!rx_skbuff) { 594 /* keep the original lists and buffers */ 595 netif_err(lp, drv, dev, "%s dev_alloc_skb failed\n", 596 __func__); 597 goto free_all_new; 598 } 599 skb_reserve(rx_skbuff, NET_IP_ALIGN); 600 601 new_dma_addr_list[new] = 602 pci_map_single(lp->pci_dev, rx_skbuff->data, 603 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE); 604 new_rx_ring[new].base = cpu_to_le32(new_dma_addr_list[new]); 605 new_rx_ring[new].buf_length = cpu_to_le16(NEG_BUF_SIZE); 606 new_rx_ring[new].status = cpu_to_le16(0x8000); 607 } 608 /* and free any unneeded buffers */ 609 for (; new < lp->rx_ring_size; new++) { 610 if (lp->rx_skbuff[new]) { 611 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[new], 612 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE); 613 dev_kfree_skb(lp->rx_skbuff[new]); 614 } 615 } 616 617 kfree(lp->rx_skbuff); 618 kfree(lp->rx_dma_addr); 619 pci_free_consistent(lp->pci_dev, 620 sizeof(struct pcnet32_rx_head) * 621 lp->rx_ring_size, lp->rx_ring, 622 lp->rx_ring_dma_addr); 623 624 lp->rx_ring_size = (1 << size); 625 lp->rx_mod_mask = lp->rx_ring_size - 1; 626 lp->rx_len_bits = (size << 4); 627 lp->rx_ring = new_rx_ring; 628 lp->rx_ring_dma_addr = new_ring_dma_addr; 629 lp->rx_dma_addr = new_dma_addr_list; 630 lp->rx_skbuff = new_skb_list; 631 return; 632 633 free_all_new: 634 while (--new >= lp->rx_ring_size) { 635 if (new_skb_list[new]) { 636 pci_unmap_single(lp->pci_dev, new_dma_addr_list[new], 637 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE); 638 dev_kfree_skb(new_skb_list[new]); 639 } 640 } 641 kfree(new_skb_list); 642 free_new_lists: 643 kfree(new_dma_addr_list); 644 free_new_rx_ring: 645 pci_free_consistent(lp->pci_dev, 646 sizeof(struct pcnet32_rx_head) * 647 (1 << size), 648 new_rx_ring, 649 new_ring_dma_addr); 650 } 651 652 static void pcnet32_purge_rx_ring(struct net_device *dev) 653 { 654 struct pcnet32_private *lp = netdev_priv(dev); 655 int i; 656 657 /* free all allocated skbuffs */ 658 for (i = 0; i < lp->rx_ring_size; i++) { 659 lp->rx_ring[i].status = 0; /* CPU owns buffer */ 660 wmb(); /* Make sure adapter sees owner change */ 661 if (lp->rx_skbuff[i]) { 662 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i], 663 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE); 664 dev_kfree_skb_any(lp->rx_skbuff[i]); 665 } 666 lp->rx_skbuff[i] = NULL; 667 lp->rx_dma_addr[i] = 0; 668 } 669 } 670 671 #ifdef CONFIG_NET_POLL_CONTROLLER 672 static void pcnet32_poll_controller(struct net_device *dev) 673 { 674 disable_irq(dev->irq); 675 pcnet32_interrupt(0, dev); 676 enable_irq(dev->irq); 677 } 678 #endif 679 680 static int pcnet32_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 681 { 682 struct pcnet32_private *lp = netdev_priv(dev); 683 unsigned long flags; 684 int r = -EOPNOTSUPP; 685 686 if (lp->mii) { 687 spin_lock_irqsave(&lp->lock, flags); 688 mii_ethtool_gset(&lp->mii_if, cmd); 689 spin_unlock_irqrestore(&lp->lock, flags); 690 r = 0; 691 } 692 return r; 693 } 694 695 static int pcnet32_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 696 { 697 struct pcnet32_private *lp = netdev_priv(dev); 698 unsigned long flags; 699 int r = -EOPNOTSUPP; 700 701 if (lp->mii) { 702 spin_lock_irqsave(&lp->lock, flags); 703 r = mii_ethtool_sset(&lp->mii_if, cmd); 704 spin_unlock_irqrestore(&lp->lock, flags); 705 } 706 return r; 707 } 708 709 static void pcnet32_get_drvinfo(struct net_device *dev, 710 struct ethtool_drvinfo *info) 711 { 712 struct pcnet32_private *lp = netdev_priv(dev); 713 714 strcpy(info->driver, DRV_NAME); 715 strcpy(info->version, DRV_VERSION); 716 if (lp->pci_dev) 717 strcpy(info->bus_info, pci_name(lp->pci_dev)); 718 else 719 sprintf(info->bus_info, "VLB 0x%lx", dev->base_addr); 720 } 721 722 static u32 pcnet32_get_link(struct net_device *dev) 723 { 724 struct pcnet32_private *lp = netdev_priv(dev); 725 unsigned long flags; 726 int r; 727 728 spin_lock_irqsave(&lp->lock, flags); 729 if (lp->mii) { 730 r = mii_link_ok(&lp->mii_if); 731 } else if (lp->chip_version >= PCNET32_79C970A) { 732 ulong ioaddr = dev->base_addr; /* card base I/O address */ 733 r = (lp->a->read_bcr(ioaddr, 4) != 0xc0); 734 } else { /* can not detect link on really old chips */ 735 r = 1; 736 } 737 spin_unlock_irqrestore(&lp->lock, flags); 738 739 return r; 740 } 741 742 static u32 pcnet32_get_msglevel(struct net_device *dev) 743 { 744 struct pcnet32_private *lp = netdev_priv(dev); 745 return lp->msg_enable; 746 } 747 748 static void pcnet32_set_msglevel(struct net_device *dev, u32 value) 749 { 750 struct pcnet32_private *lp = netdev_priv(dev); 751 lp->msg_enable = value; 752 } 753 754 static int pcnet32_nway_reset(struct net_device *dev) 755 { 756 struct pcnet32_private *lp = netdev_priv(dev); 757 unsigned long flags; 758 int r = -EOPNOTSUPP; 759 760 if (lp->mii) { 761 spin_lock_irqsave(&lp->lock, flags); 762 r = mii_nway_restart(&lp->mii_if); 763 spin_unlock_irqrestore(&lp->lock, flags); 764 } 765 return r; 766 } 767 768 static void pcnet32_get_ringparam(struct net_device *dev, 769 struct ethtool_ringparam *ering) 770 { 771 struct pcnet32_private *lp = netdev_priv(dev); 772 773 ering->tx_max_pending = TX_MAX_RING_SIZE; 774 ering->tx_pending = lp->tx_ring_size; 775 ering->rx_max_pending = RX_MAX_RING_SIZE; 776 ering->rx_pending = lp->rx_ring_size; 777 } 778 779 static int pcnet32_set_ringparam(struct net_device *dev, 780 struct ethtool_ringparam *ering) 781 { 782 struct pcnet32_private *lp = netdev_priv(dev); 783 unsigned long flags; 784 unsigned int size; 785 ulong ioaddr = dev->base_addr; 786 int i; 787 788 if (ering->rx_mini_pending || ering->rx_jumbo_pending) 789 return -EINVAL; 790 791 if (netif_running(dev)) 792 pcnet32_netif_stop(dev); 793 794 spin_lock_irqsave(&lp->lock, flags); 795 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */ 796 797 size = min(ering->tx_pending, (unsigned int)TX_MAX_RING_SIZE); 798 799 /* set the minimum ring size to 4, to allow the loopback test to work 800 * unchanged. 801 */ 802 for (i = 2; i <= PCNET32_LOG_MAX_TX_BUFFERS; i++) { 803 if (size <= (1 << i)) 804 break; 805 } 806 if ((1 << i) != lp->tx_ring_size) 807 pcnet32_realloc_tx_ring(dev, lp, i); 808 809 size = min(ering->rx_pending, (unsigned int)RX_MAX_RING_SIZE); 810 for (i = 2; i <= PCNET32_LOG_MAX_RX_BUFFERS; i++) { 811 if (size <= (1 << i)) 812 break; 813 } 814 if ((1 << i) != lp->rx_ring_size) 815 pcnet32_realloc_rx_ring(dev, lp, i); 816 817 lp->napi.weight = lp->rx_ring_size / 2; 818 819 if (netif_running(dev)) { 820 pcnet32_netif_start(dev); 821 pcnet32_restart(dev, CSR0_NORMAL); 822 } 823 824 spin_unlock_irqrestore(&lp->lock, flags); 825 826 netif_info(lp, drv, dev, "Ring Param Settings: RX: %d, TX: %d\n", 827 lp->rx_ring_size, lp->tx_ring_size); 828 829 return 0; 830 } 831 832 static void pcnet32_get_strings(struct net_device *dev, u32 stringset, 833 u8 *data) 834 { 835 memcpy(data, pcnet32_gstrings_test, sizeof(pcnet32_gstrings_test)); 836 } 837 838 static int pcnet32_get_sset_count(struct net_device *dev, int sset) 839 { 840 switch (sset) { 841 case ETH_SS_TEST: 842 return PCNET32_TEST_LEN; 843 default: 844 return -EOPNOTSUPP; 845 } 846 } 847 848 static void pcnet32_ethtool_test(struct net_device *dev, 849 struct ethtool_test *test, u64 * data) 850 { 851 struct pcnet32_private *lp = netdev_priv(dev); 852 int rc; 853 854 if (test->flags == ETH_TEST_FL_OFFLINE) { 855 rc = pcnet32_loopback_test(dev, data); 856 if (rc) { 857 netif_printk(lp, hw, KERN_DEBUG, dev, 858 "Loopback test failed\n"); 859 test->flags |= ETH_TEST_FL_FAILED; 860 } else 861 netif_printk(lp, hw, KERN_DEBUG, dev, 862 "Loopback test passed\n"); 863 } else 864 netif_printk(lp, hw, KERN_DEBUG, dev, 865 "No tests to run (specify 'Offline' on ethtool)\n"); 866 } /* end pcnet32_ethtool_test */ 867 868 static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1) 869 { 870 struct pcnet32_private *lp = netdev_priv(dev); 871 const struct pcnet32_access *a = lp->a; /* access to registers */ 872 ulong ioaddr = dev->base_addr; /* card base I/O address */ 873 struct sk_buff *skb; /* sk buff */ 874 int x, i; /* counters */ 875 int numbuffs = 4; /* number of TX/RX buffers and descs */ 876 u16 status = 0x8300; /* TX ring status */ 877 __le16 teststatus; /* test of ring status */ 878 int rc; /* return code */ 879 int size; /* size of packets */ 880 unsigned char *packet; /* source packet data */ 881 static const int data_len = 60; /* length of source packets */ 882 unsigned long flags; 883 unsigned long ticks; 884 885 rc = 1; /* default to fail */ 886 887 if (netif_running(dev)) 888 pcnet32_netif_stop(dev); 889 890 spin_lock_irqsave(&lp->lock, flags); 891 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */ 892 893 numbuffs = min(numbuffs, (int)min(lp->rx_ring_size, lp->tx_ring_size)); 894 895 /* Reset the PCNET32 */ 896 lp->a->reset(ioaddr); 897 lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */ 898 899 /* switch pcnet32 to 32bit mode */ 900 lp->a->write_bcr(ioaddr, 20, 2); 901 902 /* purge & init rings but don't actually restart */ 903 pcnet32_restart(dev, 0x0000); 904 905 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */ 906 907 /* Initialize Transmit buffers. */ 908 size = data_len + 15; 909 for (x = 0; x < numbuffs; x++) { 910 skb = dev_alloc_skb(size); 911 if (!skb) { 912 netif_printk(lp, hw, KERN_DEBUG, dev, 913 "Cannot allocate skb at line: %d!\n", 914 __LINE__); 915 goto clean_up; 916 } 917 packet = skb->data; 918 skb_put(skb, size); /* create space for data */ 919 lp->tx_skbuff[x] = skb; 920 lp->tx_ring[x].length = cpu_to_le16(-skb->len); 921 lp->tx_ring[x].misc = 0; 922 923 /* put DA and SA into the skb */ 924 for (i = 0; i < 6; i++) 925 *packet++ = dev->dev_addr[i]; 926 for (i = 0; i < 6; i++) 927 *packet++ = dev->dev_addr[i]; 928 /* type */ 929 *packet++ = 0x08; 930 *packet++ = 0x06; 931 /* packet number */ 932 *packet++ = x; 933 /* fill packet with data */ 934 for (i = 0; i < data_len; i++) 935 *packet++ = i; 936 937 lp->tx_dma_addr[x] = 938 pci_map_single(lp->pci_dev, skb->data, skb->len, 939 PCI_DMA_TODEVICE); 940 lp->tx_ring[x].base = cpu_to_le32(lp->tx_dma_addr[x]); 941 wmb(); /* Make sure owner changes after all others are visible */ 942 lp->tx_ring[x].status = cpu_to_le16(status); 943 } 944 945 x = a->read_bcr(ioaddr, 32); /* set internal loopback in BCR32 */ 946 a->write_bcr(ioaddr, 32, x | 0x0002); 947 948 /* set int loopback in CSR15 */ 949 x = a->read_csr(ioaddr, CSR15) & 0xfffc; 950 lp->a->write_csr(ioaddr, CSR15, x | 0x0044); 951 952 teststatus = cpu_to_le16(0x8000); 953 lp->a->write_csr(ioaddr, CSR0, CSR0_START); /* Set STRT bit */ 954 955 /* Check status of descriptors */ 956 for (x = 0; x < numbuffs; x++) { 957 ticks = 0; 958 rmb(); 959 while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) { 960 spin_unlock_irqrestore(&lp->lock, flags); 961 msleep(1); 962 spin_lock_irqsave(&lp->lock, flags); 963 rmb(); 964 ticks++; 965 } 966 if (ticks == 200) { 967 netif_err(lp, hw, dev, "Desc %d failed to reset!\n", x); 968 break; 969 } 970 } 971 972 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */ 973 wmb(); 974 if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) { 975 netdev_printk(KERN_DEBUG, dev, "RX loopback packets:\n"); 976 977 for (x = 0; x < numbuffs; x++) { 978 netdev_printk(KERN_DEBUG, dev, "Packet %d: ", x); 979 skb = lp->rx_skbuff[x]; 980 for (i = 0; i < size; i++) 981 pr_cont(" %02x", *(skb->data + i)); 982 pr_cont("\n"); 983 } 984 } 985 986 x = 0; 987 rc = 0; 988 while (x < numbuffs && !rc) { 989 skb = lp->rx_skbuff[x]; 990 packet = lp->tx_skbuff[x]->data; 991 for (i = 0; i < size; i++) { 992 if (*(skb->data + i) != packet[i]) { 993 netif_printk(lp, hw, KERN_DEBUG, dev, 994 "Error in compare! %2x - %02x %02x\n", 995 i, *(skb->data + i), packet[i]); 996 rc = 1; 997 break; 998 } 999 } 1000 x++; 1001 } 1002 1003 clean_up: 1004 *data1 = rc; 1005 pcnet32_purge_tx_ring(dev); 1006 1007 x = a->read_csr(ioaddr, CSR15); 1008 a->write_csr(ioaddr, CSR15, (x & ~0x0044)); /* reset bits 6 and 2 */ 1009 1010 x = a->read_bcr(ioaddr, 32); /* reset internal loopback */ 1011 a->write_bcr(ioaddr, 32, (x & ~0x0002)); 1012 1013 if (netif_running(dev)) { 1014 pcnet32_netif_start(dev); 1015 pcnet32_restart(dev, CSR0_NORMAL); 1016 } else { 1017 pcnet32_purge_rx_ring(dev); 1018 lp->a->write_bcr(ioaddr, 20, 4); /* return to 16bit mode */ 1019 } 1020 spin_unlock_irqrestore(&lp->lock, flags); 1021 1022 return rc; 1023 } /* end pcnet32_loopback_test */ 1024 1025 static int pcnet32_set_phys_id(struct net_device *dev, 1026 enum ethtool_phys_id_state state) 1027 { 1028 struct pcnet32_private *lp = netdev_priv(dev); 1029 const struct pcnet32_access *a = lp->a; 1030 ulong ioaddr = dev->base_addr; 1031 unsigned long flags; 1032 int i; 1033 1034 switch (state) { 1035 case ETHTOOL_ID_ACTIVE: 1036 /* Save the current value of the bcrs */ 1037 spin_lock_irqsave(&lp->lock, flags); 1038 for (i = 4; i < 8; i++) 1039 lp->save_regs[i - 4] = a->read_bcr(ioaddr, i); 1040 spin_unlock_irqrestore(&lp->lock, flags); 1041 return 2; /* cycle on/off twice per second */ 1042 1043 case ETHTOOL_ID_ON: 1044 case ETHTOOL_ID_OFF: 1045 /* Blink the led */ 1046 spin_lock_irqsave(&lp->lock, flags); 1047 for (i = 4; i < 8; i++) 1048 a->write_bcr(ioaddr, i, a->read_bcr(ioaddr, i) ^ 0x4000); 1049 spin_unlock_irqrestore(&lp->lock, flags); 1050 break; 1051 1052 case ETHTOOL_ID_INACTIVE: 1053 /* Restore the original value of the bcrs */ 1054 spin_lock_irqsave(&lp->lock, flags); 1055 for (i = 4; i < 8; i++) 1056 a->write_bcr(ioaddr, i, lp->save_regs[i - 4]); 1057 spin_unlock_irqrestore(&lp->lock, flags); 1058 } 1059 return 0; 1060 } 1061 1062 /* 1063 * lp->lock must be held. 1064 */ 1065 static int pcnet32_suspend(struct net_device *dev, unsigned long *flags, 1066 int can_sleep) 1067 { 1068 int csr5; 1069 struct pcnet32_private *lp = netdev_priv(dev); 1070 const struct pcnet32_access *a = lp->a; 1071 ulong ioaddr = dev->base_addr; 1072 int ticks; 1073 1074 /* really old chips have to be stopped. */ 1075 if (lp->chip_version < PCNET32_79C970A) 1076 return 0; 1077 1078 /* set SUSPEND (SPND) - CSR5 bit 0 */ 1079 csr5 = a->read_csr(ioaddr, CSR5); 1080 a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND); 1081 1082 /* poll waiting for bit to be set */ 1083 ticks = 0; 1084 while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) { 1085 spin_unlock_irqrestore(&lp->lock, *flags); 1086 if (can_sleep) 1087 msleep(1); 1088 else 1089 mdelay(1); 1090 spin_lock_irqsave(&lp->lock, *flags); 1091 ticks++; 1092 if (ticks > 200) { 1093 netif_printk(lp, hw, KERN_DEBUG, dev, 1094 "Error getting into suspend!\n"); 1095 return 0; 1096 } 1097 } 1098 return 1; 1099 } 1100 1101 /* 1102 * process one receive descriptor entry 1103 */ 1104 1105 static void pcnet32_rx_entry(struct net_device *dev, 1106 struct pcnet32_private *lp, 1107 struct pcnet32_rx_head *rxp, 1108 int entry) 1109 { 1110 int status = (short)le16_to_cpu(rxp->status) >> 8; 1111 int rx_in_place = 0; 1112 struct sk_buff *skb; 1113 short pkt_len; 1114 1115 if (status != 0x03) { /* There was an error. */ 1116 /* 1117 * There is a tricky error noted by John Murphy, 1118 * <murf@perftech.com> to Russ Nelson: Even with full-sized 1119 * buffers it's possible for a jabber packet to use two 1120 * buffers, with only the last correctly noting the error. 1121 */ 1122 if (status & 0x01) /* Only count a general error at the */ 1123 dev->stats.rx_errors++; /* end of a packet. */ 1124 if (status & 0x20) 1125 dev->stats.rx_frame_errors++; 1126 if (status & 0x10) 1127 dev->stats.rx_over_errors++; 1128 if (status & 0x08) 1129 dev->stats.rx_crc_errors++; 1130 if (status & 0x04) 1131 dev->stats.rx_fifo_errors++; 1132 return; 1133 } 1134 1135 pkt_len = (le32_to_cpu(rxp->msg_length) & 0xfff) - 4; 1136 1137 /* Discard oversize frames. */ 1138 if (unlikely(pkt_len > PKT_BUF_SIZE)) { 1139 netif_err(lp, drv, dev, "Impossible packet size %d!\n", 1140 pkt_len); 1141 dev->stats.rx_errors++; 1142 return; 1143 } 1144 if (pkt_len < 60) { 1145 netif_err(lp, rx_err, dev, "Runt packet!\n"); 1146 dev->stats.rx_errors++; 1147 return; 1148 } 1149 1150 if (pkt_len > rx_copybreak) { 1151 struct sk_buff *newskb; 1152 1153 newskb = dev_alloc_skb(PKT_BUF_SKB); 1154 if (newskb) { 1155 skb_reserve(newskb, NET_IP_ALIGN); 1156 skb = lp->rx_skbuff[entry]; 1157 pci_unmap_single(lp->pci_dev, 1158 lp->rx_dma_addr[entry], 1159 PKT_BUF_SIZE, 1160 PCI_DMA_FROMDEVICE); 1161 skb_put(skb, pkt_len); 1162 lp->rx_skbuff[entry] = newskb; 1163 lp->rx_dma_addr[entry] = 1164 pci_map_single(lp->pci_dev, 1165 newskb->data, 1166 PKT_BUF_SIZE, 1167 PCI_DMA_FROMDEVICE); 1168 rxp->base = cpu_to_le32(lp->rx_dma_addr[entry]); 1169 rx_in_place = 1; 1170 } else 1171 skb = NULL; 1172 } else 1173 skb = dev_alloc_skb(pkt_len + NET_IP_ALIGN); 1174 1175 if (skb == NULL) { 1176 netif_err(lp, drv, dev, "Memory squeeze, dropping packet\n"); 1177 dev->stats.rx_dropped++; 1178 return; 1179 } 1180 if (!rx_in_place) { 1181 skb_reserve(skb, NET_IP_ALIGN); 1182 skb_put(skb, pkt_len); /* Make room */ 1183 pci_dma_sync_single_for_cpu(lp->pci_dev, 1184 lp->rx_dma_addr[entry], 1185 pkt_len, 1186 PCI_DMA_FROMDEVICE); 1187 skb_copy_to_linear_data(skb, 1188 (unsigned char *)(lp->rx_skbuff[entry]->data), 1189 pkt_len); 1190 pci_dma_sync_single_for_device(lp->pci_dev, 1191 lp->rx_dma_addr[entry], 1192 pkt_len, 1193 PCI_DMA_FROMDEVICE); 1194 } 1195 dev->stats.rx_bytes += skb->len; 1196 skb->protocol = eth_type_trans(skb, dev); 1197 netif_receive_skb(skb); 1198 dev->stats.rx_packets++; 1199 } 1200 1201 static int pcnet32_rx(struct net_device *dev, int budget) 1202 { 1203 struct pcnet32_private *lp = netdev_priv(dev); 1204 int entry = lp->cur_rx & lp->rx_mod_mask; 1205 struct pcnet32_rx_head *rxp = &lp->rx_ring[entry]; 1206 int npackets = 0; 1207 1208 /* If we own the next entry, it's a new packet. Send it up. */ 1209 while (npackets < budget && (short)le16_to_cpu(rxp->status) >= 0) { 1210 pcnet32_rx_entry(dev, lp, rxp, entry); 1211 npackets += 1; 1212 /* 1213 * The docs say that the buffer length isn't touched, but Andrew 1214 * Boyd of QNX reports that some revs of the 79C965 clear it. 1215 */ 1216 rxp->buf_length = cpu_to_le16(NEG_BUF_SIZE); 1217 wmb(); /* Make sure owner changes after others are visible */ 1218 rxp->status = cpu_to_le16(0x8000); 1219 entry = (++lp->cur_rx) & lp->rx_mod_mask; 1220 rxp = &lp->rx_ring[entry]; 1221 } 1222 1223 return npackets; 1224 } 1225 1226 static int pcnet32_tx(struct net_device *dev) 1227 { 1228 struct pcnet32_private *lp = netdev_priv(dev); 1229 unsigned int dirty_tx = lp->dirty_tx; 1230 int delta; 1231 int must_restart = 0; 1232 1233 while (dirty_tx != lp->cur_tx) { 1234 int entry = dirty_tx & lp->tx_mod_mask; 1235 int status = (short)le16_to_cpu(lp->tx_ring[entry].status); 1236 1237 if (status < 0) 1238 break; /* It still hasn't been Txed */ 1239 1240 lp->tx_ring[entry].base = 0; 1241 1242 if (status & 0x4000) { 1243 /* There was a major error, log it. */ 1244 int err_status = le32_to_cpu(lp->tx_ring[entry].misc); 1245 dev->stats.tx_errors++; 1246 netif_err(lp, tx_err, dev, 1247 "Tx error status=%04x err_status=%08x\n", 1248 status, err_status); 1249 if (err_status & 0x04000000) 1250 dev->stats.tx_aborted_errors++; 1251 if (err_status & 0x08000000) 1252 dev->stats.tx_carrier_errors++; 1253 if (err_status & 0x10000000) 1254 dev->stats.tx_window_errors++; 1255 #ifndef DO_DXSUFLO 1256 if (err_status & 0x40000000) { 1257 dev->stats.tx_fifo_errors++; 1258 /* Ackk! On FIFO errors the Tx unit is turned off! */ 1259 /* Remove this verbosity later! */ 1260 netif_err(lp, tx_err, dev, "Tx FIFO error!\n"); 1261 must_restart = 1; 1262 } 1263 #else 1264 if (err_status & 0x40000000) { 1265 dev->stats.tx_fifo_errors++; 1266 if (!lp->dxsuflo) { /* If controller doesn't recover ... */ 1267 /* Ackk! On FIFO errors the Tx unit is turned off! */ 1268 /* Remove this verbosity later! */ 1269 netif_err(lp, tx_err, dev, "Tx FIFO error!\n"); 1270 must_restart = 1; 1271 } 1272 } 1273 #endif 1274 } else { 1275 if (status & 0x1800) 1276 dev->stats.collisions++; 1277 dev->stats.tx_packets++; 1278 } 1279 1280 /* We must free the original skb */ 1281 if (lp->tx_skbuff[entry]) { 1282 pci_unmap_single(lp->pci_dev, 1283 lp->tx_dma_addr[entry], 1284 lp->tx_skbuff[entry]-> 1285 len, PCI_DMA_TODEVICE); 1286 dev_kfree_skb_any(lp->tx_skbuff[entry]); 1287 lp->tx_skbuff[entry] = NULL; 1288 lp->tx_dma_addr[entry] = 0; 1289 } 1290 dirty_tx++; 1291 } 1292 1293 delta = (lp->cur_tx - dirty_tx) & (lp->tx_mod_mask + lp->tx_ring_size); 1294 if (delta > lp->tx_ring_size) { 1295 netif_err(lp, drv, dev, "out-of-sync dirty pointer, %d vs. %d, full=%d\n", 1296 dirty_tx, lp->cur_tx, lp->tx_full); 1297 dirty_tx += lp->tx_ring_size; 1298 delta -= lp->tx_ring_size; 1299 } 1300 1301 if (lp->tx_full && 1302 netif_queue_stopped(dev) && 1303 delta < lp->tx_ring_size - 2) { 1304 /* The ring is no longer full, clear tbusy. */ 1305 lp->tx_full = 0; 1306 netif_wake_queue(dev); 1307 } 1308 lp->dirty_tx = dirty_tx; 1309 1310 return must_restart; 1311 } 1312 1313 static int pcnet32_poll(struct napi_struct *napi, int budget) 1314 { 1315 struct pcnet32_private *lp = container_of(napi, struct pcnet32_private, napi); 1316 struct net_device *dev = lp->dev; 1317 unsigned long ioaddr = dev->base_addr; 1318 unsigned long flags; 1319 int work_done; 1320 u16 val; 1321 1322 work_done = pcnet32_rx(dev, budget); 1323 1324 spin_lock_irqsave(&lp->lock, flags); 1325 if (pcnet32_tx(dev)) { 1326 /* reset the chip to clear the error condition, then restart */ 1327 lp->a->reset(ioaddr); 1328 lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */ 1329 pcnet32_restart(dev, CSR0_START); 1330 netif_wake_queue(dev); 1331 } 1332 spin_unlock_irqrestore(&lp->lock, flags); 1333 1334 if (work_done < budget) { 1335 spin_lock_irqsave(&lp->lock, flags); 1336 1337 __napi_complete(napi); 1338 1339 /* clear interrupt masks */ 1340 val = lp->a->read_csr(ioaddr, CSR3); 1341 val &= 0x00ff; 1342 lp->a->write_csr(ioaddr, CSR3, val); 1343 1344 /* Set interrupt enable. */ 1345 lp->a->write_csr(ioaddr, CSR0, CSR0_INTEN); 1346 1347 spin_unlock_irqrestore(&lp->lock, flags); 1348 } 1349 return work_done; 1350 } 1351 1352 #define PCNET32_REGS_PER_PHY 32 1353 #define PCNET32_MAX_PHYS 32 1354 static int pcnet32_get_regs_len(struct net_device *dev) 1355 { 1356 struct pcnet32_private *lp = netdev_priv(dev); 1357 int j = lp->phycount * PCNET32_REGS_PER_PHY; 1358 1359 return (PCNET32_NUM_REGS + j) * sizeof(u16); 1360 } 1361 1362 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1363 void *ptr) 1364 { 1365 int i, csr0; 1366 u16 *buff = ptr; 1367 struct pcnet32_private *lp = netdev_priv(dev); 1368 const struct pcnet32_access *a = lp->a; 1369 ulong ioaddr = dev->base_addr; 1370 unsigned long flags; 1371 1372 spin_lock_irqsave(&lp->lock, flags); 1373 1374 csr0 = a->read_csr(ioaddr, CSR0); 1375 if (!(csr0 & CSR0_STOP)) /* If not stopped */ 1376 pcnet32_suspend(dev, &flags, 1); 1377 1378 /* read address PROM */ 1379 for (i = 0; i < 16; i += 2) 1380 *buff++ = inw(ioaddr + i); 1381 1382 /* read control and status registers */ 1383 for (i = 0; i < 90; i++) 1384 *buff++ = a->read_csr(ioaddr, i); 1385 1386 *buff++ = a->read_csr(ioaddr, 112); 1387 *buff++ = a->read_csr(ioaddr, 114); 1388 1389 /* read bus configuration registers */ 1390 for (i = 0; i < 30; i++) 1391 *buff++ = a->read_bcr(ioaddr, i); 1392 1393 *buff++ = 0; /* skip bcr30 so as not to hang 79C976 */ 1394 1395 for (i = 31; i < 36; i++) 1396 *buff++ = a->read_bcr(ioaddr, i); 1397 1398 /* read mii phy registers */ 1399 if (lp->mii) { 1400 int j; 1401 for (j = 0; j < PCNET32_MAX_PHYS; j++) { 1402 if (lp->phymask & (1 << j)) { 1403 for (i = 0; i < PCNET32_REGS_PER_PHY; i++) { 1404 lp->a->write_bcr(ioaddr, 33, 1405 (j << 5) | i); 1406 *buff++ = lp->a->read_bcr(ioaddr, 34); 1407 } 1408 } 1409 } 1410 } 1411 1412 if (!(csr0 & CSR0_STOP)) { /* If not stopped */ 1413 int csr5; 1414 1415 /* clear SUSPEND (SPND) - CSR5 bit 0 */ 1416 csr5 = a->read_csr(ioaddr, CSR5); 1417 a->write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND)); 1418 } 1419 1420 spin_unlock_irqrestore(&lp->lock, flags); 1421 } 1422 1423 static const struct ethtool_ops pcnet32_ethtool_ops = { 1424 .get_settings = pcnet32_get_settings, 1425 .set_settings = pcnet32_set_settings, 1426 .get_drvinfo = pcnet32_get_drvinfo, 1427 .get_msglevel = pcnet32_get_msglevel, 1428 .set_msglevel = pcnet32_set_msglevel, 1429 .nway_reset = pcnet32_nway_reset, 1430 .get_link = pcnet32_get_link, 1431 .get_ringparam = pcnet32_get_ringparam, 1432 .set_ringparam = pcnet32_set_ringparam, 1433 .get_strings = pcnet32_get_strings, 1434 .self_test = pcnet32_ethtool_test, 1435 .set_phys_id = pcnet32_set_phys_id, 1436 .get_regs_len = pcnet32_get_regs_len, 1437 .get_regs = pcnet32_get_regs, 1438 .get_sset_count = pcnet32_get_sset_count, 1439 }; 1440 1441 /* only probes for non-PCI devices, the rest are handled by 1442 * pci_register_driver via pcnet32_probe_pci */ 1443 1444 static void __devinit pcnet32_probe_vlbus(unsigned int *pcnet32_portlist) 1445 { 1446 unsigned int *port, ioaddr; 1447 1448 /* search for PCnet32 VLB cards at known addresses */ 1449 for (port = pcnet32_portlist; (ioaddr = *port); port++) { 1450 if (request_region 1451 (ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_vlbus")) { 1452 /* check if there is really a pcnet chip on that ioaddr */ 1453 if ((inb(ioaddr + 14) == 0x57) && 1454 (inb(ioaddr + 15) == 0x57)) { 1455 pcnet32_probe1(ioaddr, 0, NULL); 1456 } else { 1457 release_region(ioaddr, PCNET32_TOTAL_SIZE); 1458 } 1459 } 1460 } 1461 } 1462 1463 static int __devinit 1464 pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent) 1465 { 1466 unsigned long ioaddr; 1467 int err; 1468 1469 err = pci_enable_device(pdev); 1470 if (err < 0) { 1471 if (pcnet32_debug & NETIF_MSG_PROBE) 1472 pr_err("failed to enable device -- err=%d\n", err); 1473 return err; 1474 } 1475 pci_set_master(pdev); 1476 1477 ioaddr = pci_resource_start(pdev, 0); 1478 if (!ioaddr) { 1479 if (pcnet32_debug & NETIF_MSG_PROBE) 1480 pr_err("card has no PCI IO resources, aborting\n"); 1481 return -ENODEV; 1482 } 1483 1484 if (!pci_dma_supported(pdev, PCNET32_DMA_MASK)) { 1485 if (pcnet32_debug & NETIF_MSG_PROBE) 1486 pr_err("architecture does not support 32bit PCI busmaster DMA\n"); 1487 return -ENODEV; 1488 } 1489 if (!request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_pci")) { 1490 if (pcnet32_debug & NETIF_MSG_PROBE) 1491 pr_err("io address range already allocated\n"); 1492 return -EBUSY; 1493 } 1494 1495 err = pcnet32_probe1(ioaddr, 1, pdev); 1496 if (err < 0) 1497 pci_disable_device(pdev); 1498 1499 return err; 1500 } 1501 1502 static const struct net_device_ops pcnet32_netdev_ops = { 1503 .ndo_open = pcnet32_open, 1504 .ndo_stop = pcnet32_close, 1505 .ndo_start_xmit = pcnet32_start_xmit, 1506 .ndo_tx_timeout = pcnet32_tx_timeout, 1507 .ndo_get_stats = pcnet32_get_stats, 1508 .ndo_set_rx_mode = pcnet32_set_multicast_list, 1509 .ndo_do_ioctl = pcnet32_ioctl, 1510 .ndo_change_mtu = eth_change_mtu, 1511 .ndo_set_mac_address = eth_mac_addr, 1512 .ndo_validate_addr = eth_validate_addr, 1513 #ifdef CONFIG_NET_POLL_CONTROLLER 1514 .ndo_poll_controller = pcnet32_poll_controller, 1515 #endif 1516 }; 1517 1518 /* pcnet32_probe1 1519 * Called from both pcnet32_probe_vlbus and pcnet_probe_pci. 1520 * pdev will be NULL when called from pcnet32_probe_vlbus. 1521 */ 1522 static int __devinit 1523 pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev) 1524 { 1525 struct pcnet32_private *lp; 1526 int i, media; 1527 int fdx, mii, fset, dxsuflo; 1528 int chip_version; 1529 char *chipname; 1530 struct net_device *dev; 1531 const struct pcnet32_access *a = NULL; 1532 u8 promaddr[6]; 1533 int ret = -ENODEV; 1534 1535 /* reset the chip */ 1536 pcnet32_wio_reset(ioaddr); 1537 1538 /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */ 1539 if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) { 1540 a = &pcnet32_wio; 1541 } else { 1542 pcnet32_dwio_reset(ioaddr); 1543 if (pcnet32_dwio_read_csr(ioaddr, 0) == 4 && 1544 pcnet32_dwio_check(ioaddr)) { 1545 a = &pcnet32_dwio; 1546 } else { 1547 if (pcnet32_debug & NETIF_MSG_PROBE) 1548 pr_err("No access methods\n"); 1549 goto err_release_region; 1550 } 1551 } 1552 1553 chip_version = 1554 a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr, 89) << 16); 1555 if ((pcnet32_debug & NETIF_MSG_PROBE) && (pcnet32_debug & NETIF_MSG_HW)) 1556 pr_info(" PCnet chip version is %#x\n", chip_version); 1557 if ((chip_version & 0xfff) != 0x003) { 1558 if (pcnet32_debug & NETIF_MSG_PROBE) 1559 pr_info("Unsupported chip version\n"); 1560 goto err_release_region; 1561 } 1562 1563 /* initialize variables */ 1564 fdx = mii = fset = dxsuflo = 0; 1565 chip_version = (chip_version >> 12) & 0xffff; 1566 1567 switch (chip_version) { 1568 case 0x2420: 1569 chipname = "PCnet/PCI 79C970"; /* PCI */ 1570 break; 1571 case 0x2430: 1572 if (shared) 1573 chipname = "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */ 1574 else 1575 chipname = "PCnet/32 79C965"; /* 486/VL bus */ 1576 break; 1577 case 0x2621: 1578 chipname = "PCnet/PCI II 79C970A"; /* PCI */ 1579 fdx = 1; 1580 break; 1581 case 0x2623: 1582 chipname = "PCnet/FAST 79C971"; /* PCI */ 1583 fdx = 1; 1584 mii = 1; 1585 fset = 1; 1586 break; 1587 case 0x2624: 1588 chipname = "PCnet/FAST+ 79C972"; /* PCI */ 1589 fdx = 1; 1590 mii = 1; 1591 fset = 1; 1592 break; 1593 case 0x2625: 1594 chipname = "PCnet/FAST III 79C973"; /* PCI */ 1595 fdx = 1; 1596 mii = 1; 1597 break; 1598 case 0x2626: 1599 chipname = "PCnet/Home 79C978"; /* PCI */ 1600 fdx = 1; 1601 /* 1602 * This is based on specs published at www.amd.com. This section 1603 * assumes that a card with a 79C978 wants to go into standard 1604 * ethernet mode. The 79C978 can also go into 1Mb HomePNA mode, 1605 * and the module option homepna=1 can select this instead. 1606 */ 1607 media = a->read_bcr(ioaddr, 49); 1608 media &= ~3; /* default to 10Mb ethernet */ 1609 if (cards_found < MAX_UNITS && homepna[cards_found]) 1610 media |= 1; /* switch to home wiring mode */ 1611 if (pcnet32_debug & NETIF_MSG_PROBE) 1612 printk(KERN_DEBUG PFX "media set to %sMbit mode\n", 1613 (media & 1) ? "1" : "10"); 1614 a->write_bcr(ioaddr, 49, media); 1615 break; 1616 case 0x2627: 1617 chipname = "PCnet/FAST III 79C975"; /* PCI */ 1618 fdx = 1; 1619 mii = 1; 1620 break; 1621 case 0x2628: 1622 chipname = "PCnet/PRO 79C976"; 1623 fdx = 1; 1624 mii = 1; 1625 break; 1626 default: 1627 if (pcnet32_debug & NETIF_MSG_PROBE) 1628 pr_info("PCnet version %#x, no PCnet32 chip\n", 1629 chip_version); 1630 goto err_release_region; 1631 } 1632 1633 /* 1634 * On selected chips turn on the BCR18:NOUFLO bit. This stops transmit 1635 * starting until the packet is loaded. Strike one for reliability, lose 1636 * one for latency - although on PCI this isn't a big loss. Older chips 1637 * have FIFO's smaller than a packet, so you can't do this. 1638 * Turn on BCR18:BurstRdEn and BCR18:BurstWrEn. 1639 */ 1640 1641 if (fset) { 1642 a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0860)); 1643 a->write_csr(ioaddr, 80, 1644 (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00); 1645 dxsuflo = 1; 1646 } 1647 1648 dev = alloc_etherdev(sizeof(*lp)); 1649 if (!dev) { 1650 if (pcnet32_debug & NETIF_MSG_PROBE) 1651 pr_err("Memory allocation failed\n"); 1652 ret = -ENOMEM; 1653 goto err_release_region; 1654 } 1655 1656 if (pdev) 1657 SET_NETDEV_DEV(dev, &pdev->dev); 1658 1659 if (pcnet32_debug & NETIF_MSG_PROBE) 1660 pr_info("%s at %#3lx,", chipname, ioaddr); 1661 1662 /* In most chips, after a chip reset, the ethernet address is read from the 1663 * station address PROM at the base address and programmed into the 1664 * "Physical Address Registers" CSR12-14. 1665 * As a precautionary measure, we read the PROM values and complain if 1666 * they disagree with the CSRs. If they miscompare, and the PROM addr 1667 * is valid, then the PROM addr is used. 1668 */ 1669 for (i = 0; i < 3; i++) { 1670 unsigned int val; 1671 val = a->read_csr(ioaddr, i + 12) & 0x0ffff; 1672 /* There may be endianness issues here. */ 1673 dev->dev_addr[2 * i] = val & 0x0ff; 1674 dev->dev_addr[2 * i + 1] = (val >> 8) & 0x0ff; 1675 } 1676 1677 /* read PROM address and compare with CSR address */ 1678 for (i = 0; i < 6; i++) 1679 promaddr[i] = inb(ioaddr + i); 1680 1681 if (memcmp(promaddr, dev->dev_addr, 6) || 1682 !is_valid_ether_addr(dev->dev_addr)) { 1683 if (is_valid_ether_addr(promaddr)) { 1684 if (pcnet32_debug & NETIF_MSG_PROBE) { 1685 pr_cont(" warning: CSR address invalid,\n"); 1686 pr_info(" using instead PROM address of"); 1687 } 1688 memcpy(dev->dev_addr, promaddr, 6); 1689 } 1690 } 1691 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); 1692 1693 /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */ 1694 if (!is_valid_ether_addr(dev->perm_addr)) 1695 memset(dev->dev_addr, 0, ETH_ALEN); 1696 1697 if (pcnet32_debug & NETIF_MSG_PROBE) { 1698 pr_cont(" %pM", dev->dev_addr); 1699 1700 /* Version 0x2623 and 0x2624 */ 1701 if (((chip_version + 1) & 0xfffe) == 0x2624) { 1702 i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */ 1703 pr_info(" tx_start_pt(0x%04x):", i); 1704 switch (i >> 10) { 1705 case 0: 1706 pr_cont(" 20 bytes,"); 1707 break; 1708 case 1: 1709 pr_cont(" 64 bytes,"); 1710 break; 1711 case 2: 1712 pr_cont(" 128 bytes,"); 1713 break; 1714 case 3: 1715 pr_cont("~220 bytes,"); 1716 break; 1717 } 1718 i = a->read_bcr(ioaddr, 18); /* Check Burst/Bus control */ 1719 pr_cont(" BCR18(%x):", i & 0xffff); 1720 if (i & (1 << 5)) 1721 pr_cont("BurstWrEn "); 1722 if (i & (1 << 6)) 1723 pr_cont("BurstRdEn "); 1724 if (i & (1 << 7)) 1725 pr_cont("DWordIO "); 1726 if (i & (1 << 11)) 1727 pr_cont("NoUFlow "); 1728 i = a->read_bcr(ioaddr, 25); 1729 pr_info(" SRAMSIZE=0x%04x,", i << 8); 1730 i = a->read_bcr(ioaddr, 26); 1731 pr_cont(" SRAM_BND=0x%04x,", i << 8); 1732 i = a->read_bcr(ioaddr, 27); 1733 if (i & (1 << 14)) 1734 pr_cont("LowLatRx"); 1735 } 1736 } 1737 1738 dev->base_addr = ioaddr; 1739 lp = netdev_priv(dev); 1740 /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */ 1741 lp->init_block = pci_alloc_consistent(pdev, sizeof(*lp->init_block), 1742 &lp->init_dma_addr); 1743 if (!lp->init_block) { 1744 if (pcnet32_debug & NETIF_MSG_PROBE) 1745 pr_err("Consistent memory allocation failed\n"); 1746 ret = -ENOMEM; 1747 goto err_free_netdev; 1748 } 1749 lp->pci_dev = pdev; 1750 1751 lp->dev = dev; 1752 1753 spin_lock_init(&lp->lock); 1754 1755 lp->name = chipname; 1756 lp->shared_irq = shared; 1757 lp->tx_ring_size = TX_RING_SIZE; /* default tx ring size */ 1758 lp->rx_ring_size = RX_RING_SIZE; /* default rx ring size */ 1759 lp->tx_mod_mask = lp->tx_ring_size - 1; 1760 lp->rx_mod_mask = lp->rx_ring_size - 1; 1761 lp->tx_len_bits = (PCNET32_LOG_TX_BUFFERS << 12); 1762 lp->rx_len_bits = (PCNET32_LOG_RX_BUFFERS << 4); 1763 lp->mii_if.full_duplex = fdx; 1764 lp->mii_if.phy_id_mask = 0x1f; 1765 lp->mii_if.reg_num_mask = 0x1f; 1766 lp->dxsuflo = dxsuflo; 1767 lp->mii = mii; 1768 lp->chip_version = chip_version; 1769 lp->msg_enable = pcnet32_debug; 1770 if ((cards_found >= MAX_UNITS) || 1771 (options[cards_found] >= sizeof(options_mapping))) 1772 lp->options = PCNET32_PORT_ASEL; 1773 else 1774 lp->options = options_mapping[options[cards_found]]; 1775 lp->mii_if.dev = dev; 1776 lp->mii_if.mdio_read = mdio_read; 1777 lp->mii_if.mdio_write = mdio_write; 1778 1779 /* napi.weight is used in both the napi and non-napi cases */ 1780 lp->napi.weight = lp->rx_ring_size / 2; 1781 1782 netif_napi_add(dev, &lp->napi, pcnet32_poll, lp->rx_ring_size / 2); 1783 1784 if (fdx && !(lp->options & PCNET32_PORT_ASEL) && 1785 ((cards_found >= MAX_UNITS) || full_duplex[cards_found])) 1786 lp->options |= PCNET32_PORT_FD; 1787 1788 lp->a = a; 1789 1790 /* prior to register_netdev, dev->name is not yet correct */ 1791 if (pcnet32_alloc_ring(dev, pci_name(lp->pci_dev))) { 1792 ret = -ENOMEM; 1793 goto err_free_ring; 1794 } 1795 /* detect special T1/E1 WAN card by checking for MAC address */ 1796 if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0 && 1797 dev->dev_addr[2] == 0x75) 1798 lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI; 1799 1800 lp->init_block->mode = cpu_to_le16(0x0003); /* Disable Rx and Tx. */ 1801 lp->init_block->tlen_rlen = 1802 cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits); 1803 for (i = 0; i < 6; i++) 1804 lp->init_block->phys_addr[i] = dev->dev_addr[i]; 1805 lp->init_block->filter[0] = 0x00000000; 1806 lp->init_block->filter[1] = 0x00000000; 1807 lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr); 1808 lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr); 1809 1810 /* switch pcnet32 to 32bit mode */ 1811 a->write_bcr(ioaddr, 20, 2); 1812 1813 a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff)); 1814 a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16)); 1815 1816 if (pdev) { /* use the IRQ provided by PCI */ 1817 dev->irq = pdev->irq; 1818 if (pcnet32_debug & NETIF_MSG_PROBE) 1819 pr_cont(" assigned IRQ %d\n", dev->irq); 1820 } else { 1821 unsigned long irq_mask = probe_irq_on(); 1822 1823 /* 1824 * To auto-IRQ we enable the initialization-done and DMA error 1825 * interrupts. For ISA boards we get a DMA error, but VLB and PCI 1826 * boards will work. 1827 */ 1828 /* Trigger an initialization just for the interrupt. */ 1829 a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_INIT); 1830 mdelay(1); 1831 1832 dev->irq = probe_irq_off(irq_mask); 1833 if (!dev->irq) { 1834 if (pcnet32_debug & NETIF_MSG_PROBE) 1835 pr_cont(", failed to detect IRQ line\n"); 1836 ret = -ENODEV; 1837 goto err_free_ring; 1838 } 1839 if (pcnet32_debug & NETIF_MSG_PROBE) 1840 pr_cont(", probed IRQ %d\n", dev->irq); 1841 } 1842 1843 /* Set the mii phy_id so that we can query the link state */ 1844 if (lp->mii) { 1845 /* lp->phycount and lp->phymask are set to 0 by memset above */ 1846 1847 lp->mii_if.phy_id = ((lp->a->read_bcr(ioaddr, 33)) >> 5) & 0x1f; 1848 /* scan for PHYs */ 1849 for (i = 0; i < PCNET32_MAX_PHYS; i++) { 1850 unsigned short id1, id2; 1851 1852 id1 = mdio_read(dev, i, MII_PHYSID1); 1853 if (id1 == 0xffff) 1854 continue; 1855 id2 = mdio_read(dev, i, MII_PHYSID2); 1856 if (id2 == 0xffff) 1857 continue; 1858 if (i == 31 && ((chip_version + 1) & 0xfffe) == 0x2624) 1859 continue; /* 79C971 & 79C972 have phantom phy at id 31 */ 1860 lp->phycount++; 1861 lp->phymask |= (1 << i); 1862 lp->mii_if.phy_id = i; 1863 if (pcnet32_debug & NETIF_MSG_PROBE) 1864 pr_info("Found PHY %04x:%04x at address %d\n", 1865 id1, id2, i); 1866 } 1867 lp->a->write_bcr(ioaddr, 33, (lp->mii_if.phy_id) << 5); 1868 if (lp->phycount > 1) 1869 lp->options |= PCNET32_PORT_MII; 1870 } 1871 1872 init_timer(&lp->watchdog_timer); 1873 lp->watchdog_timer.data = (unsigned long)dev; 1874 lp->watchdog_timer.function = (void *)&pcnet32_watchdog; 1875 1876 /* The PCNET32-specific entries in the device structure. */ 1877 dev->netdev_ops = &pcnet32_netdev_ops; 1878 dev->ethtool_ops = &pcnet32_ethtool_ops; 1879 dev->watchdog_timeo = (5 * HZ); 1880 1881 /* Fill in the generic fields of the device structure. */ 1882 if (register_netdev(dev)) 1883 goto err_free_ring; 1884 1885 if (pdev) { 1886 pci_set_drvdata(pdev, dev); 1887 } else { 1888 lp->next = pcnet32_dev; 1889 pcnet32_dev = dev; 1890 } 1891 1892 if (pcnet32_debug & NETIF_MSG_PROBE) 1893 pr_info("%s: registered as %s\n", dev->name, lp->name); 1894 cards_found++; 1895 1896 /* enable LED writes */ 1897 a->write_bcr(ioaddr, 2, a->read_bcr(ioaddr, 2) | 0x1000); 1898 1899 return 0; 1900 1901 err_free_ring: 1902 pcnet32_free_ring(dev); 1903 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block), 1904 lp->init_block, lp->init_dma_addr); 1905 err_free_netdev: 1906 free_netdev(dev); 1907 err_release_region: 1908 release_region(ioaddr, PCNET32_TOTAL_SIZE); 1909 return ret; 1910 } 1911 1912 /* if any allocation fails, caller must also call pcnet32_free_ring */ 1913 static int pcnet32_alloc_ring(struct net_device *dev, const char *name) 1914 { 1915 struct pcnet32_private *lp = netdev_priv(dev); 1916 1917 lp->tx_ring = pci_alloc_consistent(lp->pci_dev, 1918 sizeof(struct pcnet32_tx_head) * 1919 lp->tx_ring_size, 1920 &lp->tx_ring_dma_addr); 1921 if (lp->tx_ring == NULL) { 1922 netif_err(lp, drv, dev, "Consistent memory allocation failed\n"); 1923 return -ENOMEM; 1924 } 1925 1926 lp->rx_ring = pci_alloc_consistent(lp->pci_dev, 1927 sizeof(struct pcnet32_rx_head) * 1928 lp->rx_ring_size, 1929 &lp->rx_ring_dma_addr); 1930 if (lp->rx_ring == NULL) { 1931 netif_err(lp, drv, dev, "Consistent memory allocation failed\n"); 1932 return -ENOMEM; 1933 } 1934 1935 lp->tx_dma_addr = kcalloc(lp->tx_ring_size, sizeof(dma_addr_t), 1936 GFP_ATOMIC); 1937 if (!lp->tx_dma_addr) { 1938 netif_err(lp, drv, dev, "Memory allocation failed\n"); 1939 return -ENOMEM; 1940 } 1941 1942 lp->rx_dma_addr = kcalloc(lp->rx_ring_size, sizeof(dma_addr_t), 1943 GFP_ATOMIC); 1944 if (!lp->rx_dma_addr) { 1945 netif_err(lp, drv, dev, "Memory allocation failed\n"); 1946 return -ENOMEM; 1947 } 1948 1949 lp->tx_skbuff = kcalloc(lp->tx_ring_size, sizeof(struct sk_buff *), 1950 GFP_ATOMIC); 1951 if (!lp->tx_skbuff) { 1952 netif_err(lp, drv, dev, "Memory allocation failed\n"); 1953 return -ENOMEM; 1954 } 1955 1956 lp->rx_skbuff = kcalloc(lp->rx_ring_size, sizeof(struct sk_buff *), 1957 GFP_ATOMIC); 1958 if (!lp->rx_skbuff) { 1959 netif_err(lp, drv, dev, "Memory allocation failed\n"); 1960 return -ENOMEM; 1961 } 1962 1963 return 0; 1964 } 1965 1966 static void pcnet32_free_ring(struct net_device *dev) 1967 { 1968 struct pcnet32_private *lp = netdev_priv(dev); 1969 1970 kfree(lp->tx_skbuff); 1971 lp->tx_skbuff = NULL; 1972 1973 kfree(lp->rx_skbuff); 1974 lp->rx_skbuff = NULL; 1975 1976 kfree(lp->tx_dma_addr); 1977 lp->tx_dma_addr = NULL; 1978 1979 kfree(lp->rx_dma_addr); 1980 lp->rx_dma_addr = NULL; 1981 1982 if (lp->tx_ring) { 1983 pci_free_consistent(lp->pci_dev, 1984 sizeof(struct pcnet32_tx_head) * 1985 lp->tx_ring_size, lp->tx_ring, 1986 lp->tx_ring_dma_addr); 1987 lp->tx_ring = NULL; 1988 } 1989 1990 if (lp->rx_ring) { 1991 pci_free_consistent(lp->pci_dev, 1992 sizeof(struct pcnet32_rx_head) * 1993 lp->rx_ring_size, lp->rx_ring, 1994 lp->rx_ring_dma_addr); 1995 lp->rx_ring = NULL; 1996 } 1997 } 1998 1999 static int pcnet32_open(struct net_device *dev) 2000 { 2001 struct pcnet32_private *lp = netdev_priv(dev); 2002 struct pci_dev *pdev = lp->pci_dev; 2003 unsigned long ioaddr = dev->base_addr; 2004 u16 val; 2005 int i; 2006 int rc; 2007 unsigned long flags; 2008 2009 if (request_irq(dev->irq, pcnet32_interrupt, 2010 lp->shared_irq ? IRQF_SHARED : 0, dev->name, 2011 (void *)dev)) { 2012 return -EAGAIN; 2013 } 2014 2015 spin_lock_irqsave(&lp->lock, flags); 2016 /* Check for a valid station address */ 2017 if (!is_valid_ether_addr(dev->dev_addr)) { 2018 rc = -EINVAL; 2019 goto err_free_irq; 2020 } 2021 2022 /* Reset the PCNET32 */ 2023 lp->a->reset(ioaddr); 2024 2025 /* switch pcnet32 to 32bit mode */ 2026 lp->a->write_bcr(ioaddr, 20, 2); 2027 2028 netif_printk(lp, ifup, KERN_DEBUG, dev, 2029 "%s() irq %d tx/rx rings %#x/%#x init %#x\n", 2030 __func__, dev->irq, (u32) (lp->tx_ring_dma_addr), 2031 (u32) (lp->rx_ring_dma_addr), 2032 (u32) (lp->init_dma_addr)); 2033 2034 /* set/reset autoselect bit */ 2035 val = lp->a->read_bcr(ioaddr, 2) & ~2; 2036 if (lp->options & PCNET32_PORT_ASEL) 2037 val |= 2; 2038 lp->a->write_bcr(ioaddr, 2, val); 2039 2040 /* handle full duplex setting */ 2041 if (lp->mii_if.full_duplex) { 2042 val = lp->a->read_bcr(ioaddr, 9) & ~3; 2043 if (lp->options & PCNET32_PORT_FD) { 2044 val |= 1; 2045 if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI)) 2046 val |= 2; 2047 } else if (lp->options & PCNET32_PORT_ASEL) { 2048 /* workaround of xSeries250, turn on for 79C975 only */ 2049 if (lp->chip_version == 0x2627) 2050 val |= 3; 2051 } 2052 lp->a->write_bcr(ioaddr, 9, val); 2053 } 2054 2055 /* set/reset GPSI bit in test register */ 2056 val = lp->a->read_csr(ioaddr, 124) & ~0x10; 2057 if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI) 2058 val |= 0x10; 2059 lp->a->write_csr(ioaddr, 124, val); 2060 2061 /* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */ 2062 if (pdev && pdev->subsystem_vendor == PCI_VENDOR_ID_AT && 2063 (pdev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX || 2064 pdev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) { 2065 if (lp->options & PCNET32_PORT_ASEL) { 2066 lp->options = PCNET32_PORT_FD | PCNET32_PORT_100; 2067 netif_printk(lp, link, KERN_DEBUG, dev, 2068 "Setting 100Mb-Full Duplex\n"); 2069 } 2070 } 2071 if (lp->phycount < 2) { 2072 /* 2073 * 24 Jun 2004 according AMD, in order to change the PHY, 2074 * DANAS (or DISPM for 79C976) must be set; then select the speed, 2075 * duplex, and/or enable auto negotiation, and clear DANAS 2076 */ 2077 if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) { 2078 lp->a->write_bcr(ioaddr, 32, 2079 lp->a->read_bcr(ioaddr, 32) | 0x0080); 2080 /* disable Auto Negotiation, set 10Mpbs, HD */ 2081 val = lp->a->read_bcr(ioaddr, 32) & ~0xb8; 2082 if (lp->options & PCNET32_PORT_FD) 2083 val |= 0x10; 2084 if (lp->options & PCNET32_PORT_100) 2085 val |= 0x08; 2086 lp->a->write_bcr(ioaddr, 32, val); 2087 } else { 2088 if (lp->options & PCNET32_PORT_ASEL) { 2089 lp->a->write_bcr(ioaddr, 32, 2090 lp->a->read_bcr(ioaddr, 2091 32) | 0x0080); 2092 /* enable auto negotiate, setup, disable fd */ 2093 val = lp->a->read_bcr(ioaddr, 32) & ~0x98; 2094 val |= 0x20; 2095 lp->a->write_bcr(ioaddr, 32, val); 2096 } 2097 } 2098 } else { 2099 int first_phy = -1; 2100 u16 bmcr; 2101 u32 bcr9; 2102 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET }; 2103 2104 /* 2105 * There is really no good other way to handle multiple PHYs 2106 * other than turning off all automatics 2107 */ 2108 val = lp->a->read_bcr(ioaddr, 2); 2109 lp->a->write_bcr(ioaddr, 2, val & ~2); 2110 val = lp->a->read_bcr(ioaddr, 32); 2111 lp->a->write_bcr(ioaddr, 32, val & ~(1 << 7)); /* stop MII manager */ 2112 2113 if (!(lp->options & PCNET32_PORT_ASEL)) { 2114 /* setup ecmd */ 2115 ecmd.port = PORT_MII; 2116 ecmd.transceiver = XCVR_INTERNAL; 2117 ecmd.autoneg = AUTONEG_DISABLE; 2118 ethtool_cmd_speed_set(&ecmd, 2119 (lp->options & PCNET32_PORT_100) ? 2120 SPEED_100 : SPEED_10); 2121 bcr9 = lp->a->read_bcr(ioaddr, 9); 2122 2123 if (lp->options & PCNET32_PORT_FD) { 2124 ecmd.duplex = DUPLEX_FULL; 2125 bcr9 |= (1 << 0); 2126 } else { 2127 ecmd.duplex = DUPLEX_HALF; 2128 bcr9 |= ~(1 << 0); 2129 } 2130 lp->a->write_bcr(ioaddr, 9, bcr9); 2131 } 2132 2133 for (i = 0; i < PCNET32_MAX_PHYS; i++) { 2134 if (lp->phymask & (1 << i)) { 2135 /* isolate all but the first PHY */ 2136 bmcr = mdio_read(dev, i, MII_BMCR); 2137 if (first_phy == -1) { 2138 first_phy = i; 2139 mdio_write(dev, i, MII_BMCR, 2140 bmcr & ~BMCR_ISOLATE); 2141 } else { 2142 mdio_write(dev, i, MII_BMCR, 2143 bmcr | BMCR_ISOLATE); 2144 } 2145 /* use mii_ethtool_sset to setup PHY */ 2146 lp->mii_if.phy_id = i; 2147 ecmd.phy_address = i; 2148 if (lp->options & PCNET32_PORT_ASEL) { 2149 mii_ethtool_gset(&lp->mii_if, &ecmd); 2150 ecmd.autoneg = AUTONEG_ENABLE; 2151 } 2152 mii_ethtool_sset(&lp->mii_if, &ecmd); 2153 } 2154 } 2155 lp->mii_if.phy_id = first_phy; 2156 netif_info(lp, link, dev, "Using PHY number %d\n", first_phy); 2157 } 2158 2159 #ifdef DO_DXSUFLO 2160 if (lp->dxsuflo) { /* Disable transmit stop on underflow */ 2161 val = lp->a->read_csr(ioaddr, CSR3); 2162 val |= 0x40; 2163 lp->a->write_csr(ioaddr, CSR3, val); 2164 } 2165 #endif 2166 2167 lp->init_block->mode = 2168 cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7); 2169 pcnet32_load_multicast(dev); 2170 2171 if (pcnet32_init_ring(dev)) { 2172 rc = -ENOMEM; 2173 goto err_free_ring; 2174 } 2175 2176 napi_enable(&lp->napi); 2177 2178 /* Re-initialize the PCNET32, and start it when done. */ 2179 lp->a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff)); 2180 lp->a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16)); 2181 2182 lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */ 2183 lp->a->write_csr(ioaddr, CSR0, CSR0_INIT); 2184 2185 netif_start_queue(dev); 2186 2187 if (lp->chip_version >= PCNET32_79C970A) { 2188 /* Print the link status and start the watchdog */ 2189 pcnet32_check_media(dev, 1); 2190 mod_timer(&lp->watchdog_timer, PCNET32_WATCHDOG_TIMEOUT); 2191 } 2192 2193 i = 0; 2194 while (i++ < 100) 2195 if (lp->a->read_csr(ioaddr, CSR0) & CSR0_IDON) 2196 break; 2197 /* 2198 * We used to clear the InitDone bit, 0x0100, here but Mark Stockton 2199 * reports that doing so triggers a bug in the '974. 2200 */ 2201 lp->a->write_csr(ioaddr, CSR0, CSR0_NORMAL); 2202 2203 netif_printk(lp, ifup, KERN_DEBUG, dev, 2204 "pcnet32 open after %d ticks, init block %#x csr0 %4.4x\n", 2205 i, 2206 (u32) (lp->init_dma_addr), 2207 lp->a->read_csr(ioaddr, CSR0)); 2208 2209 spin_unlock_irqrestore(&lp->lock, flags); 2210 2211 return 0; /* Always succeed */ 2212 2213 err_free_ring: 2214 /* free any allocated skbuffs */ 2215 pcnet32_purge_rx_ring(dev); 2216 2217 /* 2218 * Switch back to 16bit mode to avoid problems with dumb 2219 * DOS packet driver after a warm reboot 2220 */ 2221 lp->a->write_bcr(ioaddr, 20, 4); 2222 2223 err_free_irq: 2224 spin_unlock_irqrestore(&lp->lock, flags); 2225 free_irq(dev->irq, dev); 2226 return rc; 2227 } 2228 2229 /* 2230 * The LANCE has been halted for one reason or another (busmaster memory 2231 * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure, 2232 * etc.). Modern LANCE variants always reload their ring-buffer 2233 * configuration when restarted, so we must reinitialize our ring 2234 * context before restarting. As part of this reinitialization, 2235 * find all packets still on the Tx ring and pretend that they had been 2236 * sent (in effect, drop the packets on the floor) - the higher-level 2237 * protocols will time out and retransmit. It'd be better to shuffle 2238 * these skbs to a temp list and then actually re-Tx them after 2239 * restarting the chip, but I'm too lazy to do so right now. dplatt@3do.com 2240 */ 2241 2242 static void pcnet32_purge_tx_ring(struct net_device *dev) 2243 { 2244 struct pcnet32_private *lp = netdev_priv(dev); 2245 int i; 2246 2247 for (i = 0; i < lp->tx_ring_size; i++) { 2248 lp->tx_ring[i].status = 0; /* CPU owns buffer */ 2249 wmb(); /* Make sure adapter sees owner change */ 2250 if (lp->tx_skbuff[i]) { 2251 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i], 2252 lp->tx_skbuff[i]->len, 2253 PCI_DMA_TODEVICE); 2254 dev_kfree_skb_any(lp->tx_skbuff[i]); 2255 } 2256 lp->tx_skbuff[i] = NULL; 2257 lp->tx_dma_addr[i] = 0; 2258 } 2259 } 2260 2261 /* Initialize the PCNET32 Rx and Tx rings. */ 2262 static int pcnet32_init_ring(struct net_device *dev) 2263 { 2264 struct pcnet32_private *lp = netdev_priv(dev); 2265 int i; 2266 2267 lp->tx_full = 0; 2268 lp->cur_rx = lp->cur_tx = 0; 2269 lp->dirty_rx = lp->dirty_tx = 0; 2270 2271 for (i = 0; i < lp->rx_ring_size; i++) { 2272 struct sk_buff *rx_skbuff = lp->rx_skbuff[i]; 2273 if (rx_skbuff == NULL) { 2274 lp->rx_skbuff[i] = dev_alloc_skb(PKT_BUF_SKB); 2275 rx_skbuff = lp->rx_skbuff[i]; 2276 if (!rx_skbuff) { 2277 /* there is not much we can do at this point */ 2278 netif_err(lp, drv, dev, "%s dev_alloc_skb failed\n", 2279 __func__); 2280 return -1; 2281 } 2282 skb_reserve(rx_skbuff, NET_IP_ALIGN); 2283 } 2284 2285 rmb(); 2286 if (lp->rx_dma_addr[i] == 0) 2287 lp->rx_dma_addr[i] = 2288 pci_map_single(lp->pci_dev, rx_skbuff->data, 2289 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE); 2290 lp->rx_ring[i].base = cpu_to_le32(lp->rx_dma_addr[i]); 2291 lp->rx_ring[i].buf_length = cpu_to_le16(NEG_BUF_SIZE); 2292 wmb(); /* Make sure owner changes after all others are visible */ 2293 lp->rx_ring[i].status = cpu_to_le16(0x8000); 2294 } 2295 /* The Tx buffer address is filled in as needed, but we do need to clear 2296 * the upper ownership bit. */ 2297 for (i = 0; i < lp->tx_ring_size; i++) { 2298 lp->tx_ring[i].status = 0; /* CPU owns buffer */ 2299 wmb(); /* Make sure adapter sees owner change */ 2300 lp->tx_ring[i].base = 0; 2301 lp->tx_dma_addr[i] = 0; 2302 } 2303 2304 lp->init_block->tlen_rlen = 2305 cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits); 2306 for (i = 0; i < 6; i++) 2307 lp->init_block->phys_addr[i] = dev->dev_addr[i]; 2308 lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr); 2309 lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr); 2310 wmb(); /* Make sure all changes are visible */ 2311 return 0; 2312 } 2313 2314 /* the pcnet32 has been issued a stop or reset. Wait for the stop bit 2315 * then flush the pending transmit operations, re-initialize the ring, 2316 * and tell the chip to initialize. 2317 */ 2318 static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits) 2319 { 2320 struct pcnet32_private *lp = netdev_priv(dev); 2321 unsigned long ioaddr = dev->base_addr; 2322 int i; 2323 2324 /* wait for stop */ 2325 for (i = 0; i < 100; i++) 2326 if (lp->a->read_csr(ioaddr, CSR0) & CSR0_STOP) 2327 break; 2328 2329 if (i >= 100) 2330 netif_err(lp, drv, dev, "%s timed out waiting for stop\n", 2331 __func__); 2332 2333 pcnet32_purge_tx_ring(dev); 2334 if (pcnet32_init_ring(dev)) 2335 return; 2336 2337 /* ReInit Ring */ 2338 lp->a->write_csr(ioaddr, CSR0, CSR0_INIT); 2339 i = 0; 2340 while (i++ < 1000) 2341 if (lp->a->read_csr(ioaddr, CSR0) & CSR0_IDON) 2342 break; 2343 2344 lp->a->write_csr(ioaddr, CSR0, csr0_bits); 2345 } 2346 2347 static void pcnet32_tx_timeout(struct net_device *dev) 2348 { 2349 struct pcnet32_private *lp = netdev_priv(dev); 2350 unsigned long ioaddr = dev->base_addr, flags; 2351 2352 spin_lock_irqsave(&lp->lock, flags); 2353 /* Transmitter timeout, serious problems. */ 2354 if (pcnet32_debug & NETIF_MSG_DRV) 2355 pr_err("%s: transmit timed out, status %4.4x, resetting\n", 2356 dev->name, lp->a->read_csr(ioaddr, CSR0)); 2357 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); 2358 dev->stats.tx_errors++; 2359 if (netif_msg_tx_err(lp)) { 2360 int i; 2361 printk(KERN_DEBUG 2362 " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.", 2363 lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "", 2364 lp->cur_rx); 2365 for (i = 0; i < lp->rx_ring_size; i++) 2366 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ", 2367 le32_to_cpu(lp->rx_ring[i].base), 2368 (-le16_to_cpu(lp->rx_ring[i].buf_length)) & 2369 0xffff, le32_to_cpu(lp->rx_ring[i].msg_length), 2370 le16_to_cpu(lp->rx_ring[i].status)); 2371 for (i = 0; i < lp->tx_ring_size; i++) 2372 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ", 2373 le32_to_cpu(lp->tx_ring[i].base), 2374 (-le16_to_cpu(lp->tx_ring[i].length)) & 0xffff, 2375 le32_to_cpu(lp->tx_ring[i].misc), 2376 le16_to_cpu(lp->tx_ring[i].status)); 2377 printk("\n"); 2378 } 2379 pcnet32_restart(dev, CSR0_NORMAL); 2380 2381 dev->trans_start = jiffies; /* prevent tx timeout */ 2382 netif_wake_queue(dev); 2383 2384 spin_unlock_irqrestore(&lp->lock, flags); 2385 } 2386 2387 static netdev_tx_t pcnet32_start_xmit(struct sk_buff *skb, 2388 struct net_device *dev) 2389 { 2390 struct pcnet32_private *lp = netdev_priv(dev); 2391 unsigned long ioaddr = dev->base_addr; 2392 u16 status; 2393 int entry; 2394 unsigned long flags; 2395 2396 spin_lock_irqsave(&lp->lock, flags); 2397 2398 netif_printk(lp, tx_queued, KERN_DEBUG, dev, 2399 "%s() called, csr0 %4.4x\n", 2400 __func__, lp->a->read_csr(ioaddr, CSR0)); 2401 2402 /* Default status -- will not enable Successful-TxDone 2403 * interrupt when that option is available to us. 2404 */ 2405 status = 0x8300; 2406 2407 /* Fill in a Tx ring entry */ 2408 2409 /* Mask to ring buffer boundary. */ 2410 entry = lp->cur_tx & lp->tx_mod_mask; 2411 2412 /* Caution: the write order is important here, set the status 2413 * with the "ownership" bits last. */ 2414 2415 lp->tx_ring[entry].length = cpu_to_le16(-skb->len); 2416 2417 lp->tx_ring[entry].misc = 0x00000000; 2418 2419 lp->tx_skbuff[entry] = skb; 2420 lp->tx_dma_addr[entry] = 2421 pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE); 2422 lp->tx_ring[entry].base = cpu_to_le32(lp->tx_dma_addr[entry]); 2423 wmb(); /* Make sure owner changes after all others are visible */ 2424 lp->tx_ring[entry].status = cpu_to_le16(status); 2425 2426 lp->cur_tx++; 2427 dev->stats.tx_bytes += skb->len; 2428 2429 /* Trigger an immediate send poll. */ 2430 lp->a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_TXPOLL); 2431 2432 if (lp->tx_ring[(entry + 1) & lp->tx_mod_mask].base != 0) { 2433 lp->tx_full = 1; 2434 netif_stop_queue(dev); 2435 } 2436 spin_unlock_irqrestore(&lp->lock, flags); 2437 return NETDEV_TX_OK; 2438 } 2439 2440 /* The PCNET32 interrupt handler. */ 2441 static irqreturn_t 2442 pcnet32_interrupt(int irq, void *dev_id) 2443 { 2444 struct net_device *dev = dev_id; 2445 struct pcnet32_private *lp; 2446 unsigned long ioaddr; 2447 u16 csr0; 2448 int boguscnt = max_interrupt_work; 2449 2450 ioaddr = dev->base_addr; 2451 lp = netdev_priv(dev); 2452 2453 spin_lock(&lp->lock); 2454 2455 csr0 = lp->a->read_csr(ioaddr, CSR0); 2456 while ((csr0 & 0x8f00) && --boguscnt >= 0) { 2457 if (csr0 == 0xffff) 2458 break; /* PCMCIA remove happened */ 2459 /* Acknowledge all of the current interrupt sources ASAP. */ 2460 lp->a->write_csr(ioaddr, CSR0, csr0 & ~0x004f); 2461 2462 netif_printk(lp, intr, KERN_DEBUG, dev, 2463 "interrupt csr0=%#2.2x new csr=%#2.2x\n", 2464 csr0, lp->a->read_csr(ioaddr, CSR0)); 2465 2466 /* Log misc errors. */ 2467 if (csr0 & 0x4000) 2468 dev->stats.tx_errors++; /* Tx babble. */ 2469 if (csr0 & 0x1000) { 2470 /* 2471 * This happens when our receive ring is full. This 2472 * shouldn't be a problem as we will see normal rx 2473 * interrupts for the frames in the receive ring. But 2474 * there are some PCI chipsets (I can reproduce this 2475 * on SP3G with Intel saturn chipset) which have 2476 * sometimes problems and will fill up the receive 2477 * ring with error descriptors. In this situation we 2478 * don't get a rx interrupt, but a missed frame 2479 * interrupt sooner or later. 2480 */ 2481 dev->stats.rx_errors++; /* Missed a Rx frame. */ 2482 } 2483 if (csr0 & 0x0800) { 2484 netif_err(lp, drv, dev, "Bus master arbitration failure, status %4.4x\n", 2485 csr0); 2486 /* unlike for the lance, there is no restart needed */ 2487 } 2488 if (napi_schedule_prep(&lp->napi)) { 2489 u16 val; 2490 /* set interrupt masks */ 2491 val = lp->a->read_csr(ioaddr, CSR3); 2492 val |= 0x5f00; 2493 lp->a->write_csr(ioaddr, CSR3, val); 2494 2495 __napi_schedule(&lp->napi); 2496 break; 2497 } 2498 csr0 = lp->a->read_csr(ioaddr, CSR0); 2499 } 2500 2501 netif_printk(lp, intr, KERN_DEBUG, dev, 2502 "exiting interrupt, csr0=%#4.4x\n", 2503 lp->a->read_csr(ioaddr, CSR0)); 2504 2505 spin_unlock(&lp->lock); 2506 2507 return IRQ_HANDLED; 2508 } 2509 2510 static int pcnet32_close(struct net_device *dev) 2511 { 2512 unsigned long ioaddr = dev->base_addr; 2513 struct pcnet32_private *lp = netdev_priv(dev); 2514 unsigned long flags; 2515 2516 del_timer_sync(&lp->watchdog_timer); 2517 2518 netif_stop_queue(dev); 2519 napi_disable(&lp->napi); 2520 2521 spin_lock_irqsave(&lp->lock, flags); 2522 2523 dev->stats.rx_missed_errors = lp->a->read_csr(ioaddr, 112); 2524 2525 netif_printk(lp, ifdown, KERN_DEBUG, dev, 2526 "Shutting down ethercard, status was %2.2x\n", 2527 lp->a->read_csr(ioaddr, CSR0)); 2528 2529 /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */ 2530 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); 2531 2532 /* 2533 * Switch back to 16bit mode to avoid problems with dumb 2534 * DOS packet driver after a warm reboot 2535 */ 2536 lp->a->write_bcr(ioaddr, 20, 4); 2537 2538 spin_unlock_irqrestore(&lp->lock, flags); 2539 2540 free_irq(dev->irq, dev); 2541 2542 spin_lock_irqsave(&lp->lock, flags); 2543 2544 pcnet32_purge_rx_ring(dev); 2545 pcnet32_purge_tx_ring(dev); 2546 2547 spin_unlock_irqrestore(&lp->lock, flags); 2548 2549 return 0; 2550 } 2551 2552 static struct net_device_stats *pcnet32_get_stats(struct net_device *dev) 2553 { 2554 struct pcnet32_private *lp = netdev_priv(dev); 2555 unsigned long ioaddr = dev->base_addr; 2556 unsigned long flags; 2557 2558 spin_lock_irqsave(&lp->lock, flags); 2559 dev->stats.rx_missed_errors = lp->a->read_csr(ioaddr, 112); 2560 spin_unlock_irqrestore(&lp->lock, flags); 2561 2562 return &dev->stats; 2563 } 2564 2565 /* taken from the sunlance driver, which it took from the depca driver */ 2566 static void pcnet32_load_multicast(struct net_device *dev) 2567 { 2568 struct pcnet32_private *lp = netdev_priv(dev); 2569 volatile struct pcnet32_init_block *ib = lp->init_block; 2570 volatile __le16 *mcast_table = (__le16 *)ib->filter; 2571 struct netdev_hw_addr *ha; 2572 unsigned long ioaddr = dev->base_addr; 2573 int i; 2574 u32 crc; 2575 2576 /* set all multicast bits */ 2577 if (dev->flags & IFF_ALLMULTI) { 2578 ib->filter[0] = cpu_to_le32(~0U); 2579 ib->filter[1] = cpu_to_le32(~0U); 2580 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER, 0xffff); 2581 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+1, 0xffff); 2582 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+2, 0xffff); 2583 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+3, 0xffff); 2584 return; 2585 } 2586 /* clear the multicast filter */ 2587 ib->filter[0] = 0; 2588 ib->filter[1] = 0; 2589 2590 /* Add addresses */ 2591 netdev_for_each_mc_addr(ha, dev) { 2592 crc = ether_crc_le(6, ha->addr); 2593 crc = crc >> 26; 2594 mcast_table[crc >> 4] |= cpu_to_le16(1 << (crc & 0xf)); 2595 } 2596 for (i = 0; i < 4; i++) 2597 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER + i, 2598 le16_to_cpu(mcast_table[i])); 2599 } 2600 2601 /* 2602 * Set or clear the multicast filter for this adaptor. 2603 */ 2604 static void pcnet32_set_multicast_list(struct net_device *dev) 2605 { 2606 unsigned long ioaddr = dev->base_addr, flags; 2607 struct pcnet32_private *lp = netdev_priv(dev); 2608 int csr15, suspended; 2609 2610 spin_lock_irqsave(&lp->lock, flags); 2611 suspended = pcnet32_suspend(dev, &flags, 0); 2612 csr15 = lp->a->read_csr(ioaddr, CSR15); 2613 if (dev->flags & IFF_PROMISC) { 2614 /* Log any net taps. */ 2615 netif_info(lp, hw, dev, "Promiscuous mode enabled\n"); 2616 lp->init_block->mode = 2617 cpu_to_le16(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) << 2618 7); 2619 lp->a->write_csr(ioaddr, CSR15, csr15 | 0x8000); 2620 } else { 2621 lp->init_block->mode = 2622 cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7); 2623 lp->a->write_csr(ioaddr, CSR15, csr15 & 0x7fff); 2624 pcnet32_load_multicast(dev); 2625 } 2626 2627 if (suspended) { 2628 int csr5; 2629 /* clear SUSPEND (SPND) - CSR5 bit 0 */ 2630 csr5 = lp->a->read_csr(ioaddr, CSR5); 2631 lp->a->write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND)); 2632 } else { 2633 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); 2634 pcnet32_restart(dev, CSR0_NORMAL); 2635 netif_wake_queue(dev); 2636 } 2637 2638 spin_unlock_irqrestore(&lp->lock, flags); 2639 } 2640 2641 /* This routine assumes that the lp->lock is held */ 2642 static int mdio_read(struct net_device *dev, int phy_id, int reg_num) 2643 { 2644 struct pcnet32_private *lp = netdev_priv(dev); 2645 unsigned long ioaddr = dev->base_addr; 2646 u16 val_out; 2647 2648 if (!lp->mii) 2649 return 0; 2650 2651 lp->a->write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f)); 2652 val_out = lp->a->read_bcr(ioaddr, 34); 2653 2654 return val_out; 2655 } 2656 2657 /* This routine assumes that the lp->lock is held */ 2658 static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val) 2659 { 2660 struct pcnet32_private *lp = netdev_priv(dev); 2661 unsigned long ioaddr = dev->base_addr; 2662 2663 if (!lp->mii) 2664 return; 2665 2666 lp->a->write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f)); 2667 lp->a->write_bcr(ioaddr, 34, val); 2668 } 2669 2670 static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 2671 { 2672 struct pcnet32_private *lp = netdev_priv(dev); 2673 int rc; 2674 unsigned long flags; 2675 2676 /* SIOC[GS]MIIxxx ioctls */ 2677 if (lp->mii) { 2678 spin_lock_irqsave(&lp->lock, flags); 2679 rc = generic_mii_ioctl(&lp->mii_if, if_mii(rq), cmd, NULL); 2680 spin_unlock_irqrestore(&lp->lock, flags); 2681 } else { 2682 rc = -EOPNOTSUPP; 2683 } 2684 2685 return rc; 2686 } 2687 2688 static int pcnet32_check_otherphy(struct net_device *dev) 2689 { 2690 struct pcnet32_private *lp = netdev_priv(dev); 2691 struct mii_if_info mii = lp->mii_if; 2692 u16 bmcr; 2693 int i; 2694 2695 for (i = 0; i < PCNET32_MAX_PHYS; i++) { 2696 if (i == lp->mii_if.phy_id) 2697 continue; /* skip active phy */ 2698 if (lp->phymask & (1 << i)) { 2699 mii.phy_id = i; 2700 if (mii_link_ok(&mii)) { 2701 /* found PHY with active link */ 2702 netif_info(lp, link, dev, "Using PHY number %d\n", 2703 i); 2704 2705 /* isolate inactive phy */ 2706 bmcr = 2707 mdio_read(dev, lp->mii_if.phy_id, MII_BMCR); 2708 mdio_write(dev, lp->mii_if.phy_id, MII_BMCR, 2709 bmcr | BMCR_ISOLATE); 2710 2711 /* de-isolate new phy */ 2712 bmcr = mdio_read(dev, i, MII_BMCR); 2713 mdio_write(dev, i, MII_BMCR, 2714 bmcr & ~BMCR_ISOLATE); 2715 2716 /* set new phy address */ 2717 lp->mii_if.phy_id = i; 2718 return 1; 2719 } 2720 } 2721 } 2722 return 0; 2723 } 2724 2725 /* 2726 * Show the status of the media. Similar to mii_check_media however it 2727 * correctly shows the link speed for all (tested) pcnet32 variants. 2728 * Devices with no mii just report link state without speed. 2729 * 2730 * Caller is assumed to hold and release the lp->lock. 2731 */ 2732 2733 static void pcnet32_check_media(struct net_device *dev, int verbose) 2734 { 2735 struct pcnet32_private *lp = netdev_priv(dev); 2736 int curr_link; 2737 int prev_link = netif_carrier_ok(dev) ? 1 : 0; 2738 u32 bcr9; 2739 2740 if (lp->mii) { 2741 curr_link = mii_link_ok(&lp->mii_if); 2742 } else { 2743 ulong ioaddr = dev->base_addr; /* card base I/O address */ 2744 curr_link = (lp->a->read_bcr(ioaddr, 4) != 0xc0); 2745 } 2746 if (!curr_link) { 2747 if (prev_link || verbose) { 2748 netif_carrier_off(dev); 2749 netif_info(lp, link, dev, "link down\n"); 2750 } 2751 if (lp->phycount > 1) { 2752 curr_link = pcnet32_check_otherphy(dev); 2753 prev_link = 0; 2754 } 2755 } else if (verbose || !prev_link) { 2756 netif_carrier_on(dev); 2757 if (lp->mii) { 2758 if (netif_msg_link(lp)) { 2759 struct ethtool_cmd ecmd = { 2760 .cmd = ETHTOOL_GSET }; 2761 mii_ethtool_gset(&lp->mii_if, &ecmd); 2762 netdev_info(dev, "link up, %uMbps, %s-duplex\n", 2763 ethtool_cmd_speed(&ecmd), 2764 (ecmd.duplex == DUPLEX_FULL) 2765 ? "full" : "half"); 2766 } 2767 bcr9 = lp->a->read_bcr(dev->base_addr, 9); 2768 if ((bcr9 & (1 << 0)) != lp->mii_if.full_duplex) { 2769 if (lp->mii_if.full_duplex) 2770 bcr9 |= (1 << 0); 2771 else 2772 bcr9 &= ~(1 << 0); 2773 lp->a->write_bcr(dev->base_addr, 9, bcr9); 2774 } 2775 } else { 2776 netif_info(lp, link, dev, "link up\n"); 2777 } 2778 } 2779 } 2780 2781 /* 2782 * Check for loss of link and link establishment. 2783 * Can not use mii_check_media because it does nothing if mode is forced. 2784 */ 2785 2786 static void pcnet32_watchdog(struct net_device *dev) 2787 { 2788 struct pcnet32_private *lp = netdev_priv(dev); 2789 unsigned long flags; 2790 2791 /* Print the link status if it has changed */ 2792 spin_lock_irqsave(&lp->lock, flags); 2793 pcnet32_check_media(dev, 0); 2794 spin_unlock_irqrestore(&lp->lock, flags); 2795 2796 mod_timer(&lp->watchdog_timer, round_jiffies(PCNET32_WATCHDOG_TIMEOUT)); 2797 } 2798 2799 static int pcnet32_pm_suspend(struct pci_dev *pdev, pm_message_t state) 2800 { 2801 struct net_device *dev = pci_get_drvdata(pdev); 2802 2803 if (netif_running(dev)) { 2804 netif_device_detach(dev); 2805 pcnet32_close(dev); 2806 } 2807 pci_save_state(pdev); 2808 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 2809 return 0; 2810 } 2811 2812 static int pcnet32_pm_resume(struct pci_dev *pdev) 2813 { 2814 struct net_device *dev = pci_get_drvdata(pdev); 2815 2816 pci_set_power_state(pdev, PCI_D0); 2817 pci_restore_state(pdev); 2818 2819 if (netif_running(dev)) { 2820 pcnet32_open(dev); 2821 netif_device_attach(dev); 2822 } 2823 return 0; 2824 } 2825 2826 static void __devexit pcnet32_remove_one(struct pci_dev *pdev) 2827 { 2828 struct net_device *dev = pci_get_drvdata(pdev); 2829 2830 if (dev) { 2831 struct pcnet32_private *lp = netdev_priv(dev); 2832 2833 unregister_netdev(dev); 2834 pcnet32_free_ring(dev); 2835 release_region(dev->base_addr, PCNET32_TOTAL_SIZE); 2836 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block), 2837 lp->init_block, lp->init_dma_addr); 2838 free_netdev(dev); 2839 pci_disable_device(pdev); 2840 pci_set_drvdata(pdev, NULL); 2841 } 2842 } 2843 2844 static struct pci_driver pcnet32_driver = { 2845 .name = DRV_NAME, 2846 .probe = pcnet32_probe_pci, 2847 .remove = __devexit_p(pcnet32_remove_one), 2848 .id_table = pcnet32_pci_tbl, 2849 .suspend = pcnet32_pm_suspend, 2850 .resume = pcnet32_pm_resume, 2851 }; 2852 2853 /* An additional parameter that may be passed in... */ 2854 static int debug = -1; 2855 static int tx_start_pt = -1; 2856 static int pcnet32_have_pci; 2857 2858 module_param(debug, int, 0); 2859 MODULE_PARM_DESC(debug, DRV_NAME " debug level"); 2860 module_param(max_interrupt_work, int, 0); 2861 MODULE_PARM_DESC(max_interrupt_work, 2862 DRV_NAME " maximum events handled per interrupt"); 2863 module_param(rx_copybreak, int, 0); 2864 MODULE_PARM_DESC(rx_copybreak, 2865 DRV_NAME " copy breakpoint for copy-only-tiny-frames"); 2866 module_param(tx_start_pt, int, 0); 2867 MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)"); 2868 module_param(pcnet32vlb, int, 0); 2869 MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)"); 2870 module_param_array(options, int, NULL, 0); 2871 MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)"); 2872 module_param_array(full_duplex, int, NULL, 0); 2873 MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)"); 2874 /* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */ 2875 module_param_array(homepna, int, NULL, 0); 2876 MODULE_PARM_DESC(homepna, 2877 DRV_NAME 2878 " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet"); 2879 2880 MODULE_AUTHOR("Thomas Bogendoerfer"); 2881 MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards"); 2882 MODULE_LICENSE("GPL"); 2883 2884 #define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK) 2885 2886 static int __init pcnet32_init_module(void) 2887 { 2888 pr_info("%s", version); 2889 2890 pcnet32_debug = netif_msg_init(debug, PCNET32_MSG_DEFAULT); 2891 2892 if ((tx_start_pt >= 0) && (tx_start_pt <= 3)) 2893 tx_start = tx_start_pt; 2894 2895 /* find the PCI devices */ 2896 if (!pci_register_driver(&pcnet32_driver)) 2897 pcnet32_have_pci = 1; 2898 2899 /* should we find any remaining VLbus devices ? */ 2900 if (pcnet32vlb) 2901 pcnet32_probe_vlbus(pcnet32_portlist); 2902 2903 if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE)) 2904 pr_info("%d cards_found\n", cards_found); 2905 2906 return (pcnet32_have_pci + cards_found) ? 0 : -ENODEV; 2907 } 2908 2909 static void __exit pcnet32_cleanup_module(void) 2910 { 2911 struct net_device *next_dev; 2912 2913 while (pcnet32_dev) { 2914 struct pcnet32_private *lp = netdev_priv(pcnet32_dev); 2915 next_dev = lp->next; 2916 unregister_netdev(pcnet32_dev); 2917 pcnet32_free_ring(pcnet32_dev); 2918 release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE); 2919 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block), 2920 lp->init_block, lp->init_dma_addr); 2921 free_netdev(pcnet32_dev); 2922 pcnet32_dev = next_dev; 2923 } 2924 2925 if (pcnet32_have_pci) 2926 pci_unregister_driver(&pcnet32_driver); 2927 } 2928 2929 module_init(pcnet32_init_module); 2930 module_exit(pcnet32_cleanup_module); 2931 2932 /* 2933 * Local variables: 2934 * c-indent-level: 4 2935 * tab-width: 8 2936 * End: 2937 */ 2938