1 /* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */ 2 /* 3 * Copyright 1996-1999 Thomas Bogendoerfer 4 * 5 * Derived from the lance driver written 1993,1994,1995 by Donald Becker. 6 * 7 * Copyright 1993 United States Government as represented by the 8 * Director, National Security Agency. 9 * 10 * This software may be used and distributed according to the terms 11 * of the GNU General Public License, incorporated herein by reference. 12 * 13 * This driver is for PCnet32 and PCnetPCI based ethercards 14 */ 15 /************************************************************************** 16 * 23 Oct, 2000. 17 * Fixed a few bugs, related to running the controller in 32bit mode. 18 * 19 * Carsten Langgaard, carstenl@mips.com 20 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. 21 * 22 *************************************************************************/ 23 24 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 25 26 #define DRV_NAME "pcnet32" 27 #define DRV_VERSION "1.35" 28 #define DRV_RELDATE "21.Apr.2008" 29 #define PFX DRV_NAME ": " 30 31 static const char *const version = 32 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " tsbogend@alpha.franken.de\n"; 33 34 #include <linux/module.h> 35 #include <linux/kernel.h> 36 #include <linux/sched.h> 37 #include <linux/string.h> 38 #include <linux/errno.h> 39 #include <linux/ioport.h> 40 #include <linux/slab.h> 41 #include <linux/interrupt.h> 42 #include <linux/pci.h> 43 #include <linux/delay.h> 44 #include <linux/init.h> 45 #include <linux/ethtool.h> 46 #include <linux/mii.h> 47 #include <linux/crc32.h> 48 #include <linux/netdevice.h> 49 #include <linux/etherdevice.h> 50 #include <linux/if_ether.h> 51 #include <linux/skbuff.h> 52 #include <linux/spinlock.h> 53 #include <linux/moduleparam.h> 54 #include <linux/bitops.h> 55 #include <linux/io.h> 56 #include <linux/uaccess.h> 57 58 #include <asm/dma.h> 59 #include <asm/irq.h> 60 61 /* 62 * PCI device identifiers for "new style" Linux PCI Device Drivers 63 */ 64 static const struct pci_device_id pcnet32_pci_tbl[] = { 65 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME), }, 66 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE), }, 67 68 /* 69 * Adapters that were sold with IBM's RS/6000 or pSeries hardware have 70 * the incorrect vendor id. 71 */ 72 { PCI_DEVICE(PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE), 73 .class = (PCI_CLASS_NETWORK_ETHERNET << 8), .class_mask = 0xffff00, }, 74 75 { } /* terminate list */ 76 }; 77 78 MODULE_DEVICE_TABLE(pci, pcnet32_pci_tbl); 79 80 static int cards_found; 81 82 /* 83 * VLB I/O addresses 84 */ 85 static unsigned int pcnet32_portlist[] = 86 { 0x300, 0x320, 0x340, 0x360, 0 }; 87 88 static int pcnet32_debug; 89 static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */ 90 static int pcnet32vlb; /* check for VLB cards ? */ 91 92 static struct net_device *pcnet32_dev; 93 94 static int max_interrupt_work = 2; 95 static int rx_copybreak = 200; 96 97 #define PCNET32_PORT_AUI 0x00 98 #define PCNET32_PORT_10BT 0x01 99 #define PCNET32_PORT_GPSI 0x02 100 #define PCNET32_PORT_MII 0x03 101 102 #define PCNET32_PORT_PORTSEL 0x03 103 #define PCNET32_PORT_ASEL 0x04 104 #define PCNET32_PORT_100 0x40 105 #define PCNET32_PORT_FD 0x80 106 107 #define PCNET32_DMA_MASK 0xffffffff 108 109 #define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ)) 110 #define PCNET32_BLINK_TIMEOUT (jiffies + (HZ/4)) 111 112 /* 113 * table to translate option values from tulip 114 * to internal options 115 */ 116 static const unsigned char options_mapping[] = { 117 PCNET32_PORT_ASEL, /* 0 Auto-select */ 118 PCNET32_PORT_AUI, /* 1 BNC/AUI */ 119 PCNET32_PORT_AUI, /* 2 AUI/BNC */ 120 PCNET32_PORT_ASEL, /* 3 not supported */ 121 PCNET32_PORT_10BT | PCNET32_PORT_FD, /* 4 10baseT-FD */ 122 PCNET32_PORT_ASEL, /* 5 not supported */ 123 PCNET32_PORT_ASEL, /* 6 not supported */ 124 PCNET32_PORT_ASEL, /* 7 not supported */ 125 PCNET32_PORT_ASEL, /* 8 not supported */ 126 PCNET32_PORT_MII, /* 9 MII 10baseT */ 127 PCNET32_PORT_MII | PCNET32_PORT_FD, /* 10 MII 10baseT-FD */ 128 PCNET32_PORT_MII, /* 11 MII (autosel) */ 129 PCNET32_PORT_10BT, /* 12 10BaseT */ 130 PCNET32_PORT_MII | PCNET32_PORT_100, /* 13 MII 100BaseTx */ 131 /* 14 MII 100BaseTx-FD */ 132 PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD, 133 PCNET32_PORT_ASEL /* 15 not supported */ 134 }; 135 136 static const char pcnet32_gstrings_test[][ETH_GSTRING_LEN] = { 137 "Loopback test (offline)" 138 }; 139 140 #define PCNET32_TEST_LEN ARRAY_SIZE(pcnet32_gstrings_test) 141 142 #define PCNET32_NUM_REGS 136 143 144 #define MAX_UNITS 8 /* More are supported, limit only on options */ 145 static int options[MAX_UNITS]; 146 static int full_duplex[MAX_UNITS]; 147 static int homepna[MAX_UNITS]; 148 149 /* 150 * Theory of Operation 151 * 152 * This driver uses the same software structure as the normal lance 153 * driver. So look for a verbose description in lance.c. The differences 154 * to the normal lance driver is the use of the 32bit mode of PCnet32 155 * and PCnetPCI chips. Because these chips are 32bit chips, there is no 156 * 16MB limitation and we don't need bounce buffers. 157 */ 158 159 /* 160 * Set the number of Tx and Rx buffers, using Log_2(# buffers). 161 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers. 162 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4). 163 */ 164 #ifndef PCNET32_LOG_TX_BUFFERS 165 #define PCNET32_LOG_TX_BUFFERS 4 166 #define PCNET32_LOG_RX_BUFFERS 5 167 #define PCNET32_LOG_MAX_TX_BUFFERS 9 /* 2^9 == 512 */ 168 #define PCNET32_LOG_MAX_RX_BUFFERS 9 169 #endif 170 171 #define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS)) 172 #define TX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_TX_BUFFERS)) 173 174 #define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS)) 175 #define RX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_RX_BUFFERS)) 176 177 #define PKT_BUF_SKB 1544 178 /* actual buffer length after being aligned */ 179 #define PKT_BUF_SIZE (PKT_BUF_SKB - NET_IP_ALIGN) 180 /* chip wants twos complement of the (aligned) buffer length */ 181 #define NEG_BUF_SIZE (NET_IP_ALIGN - PKT_BUF_SKB) 182 183 /* Offsets from base I/O address. */ 184 #define PCNET32_WIO_RDP 0x10 185 #define PCNET32_WIO_RAP 0x12 186 #define PCNET32_WIO_RESET 0x14 187 #define PCNET32_WIO_BDP 0x16 188 189 #define PCNET32_DWIO_RDP 0x10 190 #define PCNET32_DWIO_RAP 0x14 191 #define PCNET32_DWIO_RESET 0x18 192 #define PCNET32_DWIO_BDP 0x1C 193 194 #define PCNET32_TOTAL_SIZE 0x20 195 196 #define CSR0 0 197 #define CSR0_INIT 0x1 198 #define CSR0_START 0x2 199 #define CSR0_STOP 0x4 200 #define CSR0_TXPOLL 0x8 201 #define CSR0_INTEN 0x40 202 #define CSR0_IDON 0x0100 203 #define CSR0_NORMAL (CSR0_START | CSR0_INTEN) 204 #define PCNET32_INIT_LOW 1 205 #define PCNET32_INIT_HIGH 2 206 #define CSR3 3 207 #define CSR4 4 208 #define CSR5 5 209 #define CSR5_SUSPEND 0x0001 210 #define CSR15 15 211 #define PCNET32_MC_FILTER 8 212 213 #define PCNET32_79C970A 0x2621 214 215 /* The PCNET32 Rx and Tx ring descriptors. */ 216 struct pcnet32_rx_head { 217 __le32 base; 218 __le16 buf_length; /* two`s complement of length */ 219 __le16 status; 220 __le32 msg_length; 221 __le32 reserved; 222 }; 223 224 struct pcnet32_tx_head { 225 __le32 base; 226 __le16 length; /* two`s complement of length */ 227 __le16 status; 228 __le32 misc; 229 __le32 reserved; 230 }; 231 232 /* The PCNET32 32-Bit initialization block, described in databook. */ 233 struct pcnet32_init_block { 234 __le16 mode; 235 __le16 tlen_rlen; 236 u8 phys_addr[6]; 237 __le16 reserved; 238 __le32 filter[2]; 239 /* Receive and transmit ring base, along with extra bits. */ 240 __le32 rx_ring; 241 __le32 tx_ring; 242 }; 243 244 /* PCnet32 access functions */ 245 struct pcnet32_access { 246 u16 (*read_csr) (unsigned long, int); 247 void (*write_csr) (unsigned long, int, u16); 248 u16 (*read_bcr) (unsigned long, int); 249 void (*write_bcr) (unsigned long, int, u16); 250 u16 (*read_rap) (unsigned long); 251 void (*write_rap) (unsigned long, u16); 252 void (*reset) (unsigned long); 253 }; 254 255 /* 256 * The first field of pcnet32_private is read by the ethernet device 257 * so the structure should be allocated using pci_alloc_consistent(). 258 */ 259 struct pcnet32_private { 260 struct pcnet32_init_block *init_block; 261 /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */ 262 struct pcnet32_rx_head *rx_ring; 263 struct pcnet32_tx_head *tx_ring; 264 dma_addr_t init_dma_addr;/* DMA address of beginning of the init block, 265 returned by pci_alloc_consistent */ 266 struct pci_dev *pci_dev; 267 const char *name; 268 /* The saved address of a sent-in-place packet/buffer, for skfree(). */ 269 struct sk_buff **tx_skbuff; 270 struct sk_buff **rx_skbuff; 271 dma_addr_t *tx_dma_addr; 272 dma_addr_t *rx_dma_addr; 273 const struct pcnet32_access *a; 274 spinlock_t lock; /* Guard lock */ 275 unsigned int cur_rx, cur_tx; /* The next free ring entry */ 276 unsigned int rx_ring_size; /* current rx ring size */ 277 unsigned int tx_ring_size; /* current tx ring size */ 278 unsigned int rx_mod_mask; /* rx ring modular mask */ 279 unsigned int tx_mod_mask; /* tx ring modular mask */ 280 unsigned short rx_len_bits; 281 unsigned short tx_len_bits; 282 dma_addr_t rx_ring_dma_addr; 283 dma_addr_t tx_ring_dma_addr; 284 unsigned int dirty_rx, /* ring entries to be freed. */ 285 dirty_tx; 286 287 struct net_device *dev; 288 struct napi_struct napi; 289 char tx_full; 290 char phycount; /* number of phys found */ 291 int options; 292 unsigned int shared_irq:1, /* shared irq possible */ 293 dxsuflo:1, /* disable transmit stop on uflo */ 294 mii:1; /* mii port available */ 295 struct net_device *next; 296 struct mii_if_info mii_if; 297 struct timer_list watchdog_timer; 298 u32 msg_enable; /* debug message level */ 299 300 /* each bit indicates an available PHY */ 301 u32 phymask; 302 unsigned short chip_version; /* which variant this is */ 303 304 /* saved registers during ethtool blink */ 305 u16 save_regs[4]; 306 }; 307 308 static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *); 309 static int pcnet32_probe1(unsigned long, int, struct pci_dev *); 310 static int pcnet32_open(struct net_device *); 311 static int pcnet32_init_ring(struct net_device *); 312 static netdev_tx_t pcnet32_start_xmit(struct sk_buff *, 313 struct net_device *); 314 static void pcnet32_tx_timeout(struct net_device *dev); 315 static irqreturn_t pcnet32_interrupt(int, void *); 316 static int pcnet32_close(struct net_device *); 317 static struct net_device_stats *pcnet32_get_stats(struct net_device *); 318 static void pcnet32_load_multicast(struct net_device *dev); 319 static void pcnet32_set_multicast_list(struct net_device *); 320 static int pcnet32_ioctl(struct net_device *, struct ifreq *, int); 321 static void pcnet32_watchdog(struct net_device *); 322 static int mdio_read(struct net_device *dev, int phy_id, int reg_num); 323 static void mdio_write(struct net_device *dev, int phy_id, int reg_num, 324 int val); 325 static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits); 326 static void pcnet32_ethtool_test(struct net_device *dev, 327 struct ethtool_test *eth_test, u64 * data); 328 static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1); 329 static int pcnet32_get_regs_len(struct net_device *dev); 330 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs, 331 void *ptr); 332 static void pcnet32_purge_tx_ring(struct net_device *dev); 333 static int pcnet32_alloc_ring(struct net_device *dev, const char *name); 334 static void pcnet32_free_ring(struct net_device *dev); 335 static void pcnet32_check_media(struct net_device *dev, int verbose); 336 337 static u16 pcnet32_wio_read_csr(unsigned long addr, int index) 338 { 339 outw(index, addr + PCNET32_WIO_RAP); 340 return inw(addr + PCNET32_WIO_RDP); 341 } 342 343 static void pcnet32_wio_write_csr(unsigned long addr, int index, u16 val) 344 { 345 outw(index, addr + PCNET32_WIO_RAP); 346 outw(val, addr + PCNET32_WIO_RDP); 347 } 348 349 static u16 pcnet32_wio_read_bcr(unsigned long addr, int index) 350 { 351 outw(index, addr + PCNET32_WIO_RAP); 352 return inw(addr + PCNET32_WIO_BDP); 353 } 354 355 static void pcnet32_wio_write_bcr(unsigned long addr, int index, u16 val) 356 { 357 outw(index, addr + PCNET32_WIO_RAP); 358 outw(val, addr + PCNET32_WIO_BDP); 359 } 360 361 static u16 pcnet32_wio_read_rap(unsigned long addr) 362 { 363 return inw(addr + PCNET32_WIO_RAP); 364 } 365 366 static void pcnet32_wio_write_rap(unsigned long addr, u16 val) 367 { 368 outw(val, addr + PCNET32_WIO_RAP); 369 } 370 371 static void pcnet32_wio_reset(unsigned long addr) 372 { 373 inw(addr + PCNET32_WIO_RESET); 374 } 375 376 static int pcnet32_wio_check(unsigned long addr) 377 { 378 outw(88, addr + PCNET32_WIO_RAP); 379 return inw(addr + PCNET32_WIO_RAP) == 88; 380 } 381 382 static const struct pcnet32_access pcnet32_wio = { 383 .read_csr = pcnet32_wio_read_csr, 384 .write_csr = pcnet32_wio_write_csr, 385 .read_bcr = pcnet32_wio_read_bcr, 386 .write_bcr = pcnet32_wio_write_bcr, 387 .read_rap = pcnet32_wio_read_rap, 388 .write_rap = pcnet32_wio_write_rap, 389 .reset = pcnet32_wio_reset 390 }; 391 392 static u16 pcnet32_dwio_read_csr(unsigned long addr, int index) 393 { 394 outl(index, addr + PCNET32_DWIO_RAP); 395 return inl(addr + PCNET32_DWIO_RDP) & 0xffff; 396 } 397 398 static void pcnet32_dwio_write_csr(unsigned long addr, int index, u16 val) 399 { 400 outl(index, addr + PCNET32_DWIO_RAP); 401 outl(val, addr + PCNET32_DWIO_RDP); 402 } 403 404 static u16 pcnet32_dwio_read_bcr(unsigned long addr, int index) 405 { 406 outl(index, addr + PCNET32_DWIO_RAP); 407 return inl(addr + PCNET32_DWIO_BDP) & 0xffff; 408 } 409 410 static void pcnet32_dwio_write_bcr(unsigned long addr, int index, u16 val) 411 { 412 outl(index, addr + PCNET32_DWIO_RAP); 413 outl(val, addr + PCNET32_DWIO_BDP); 414 } 415 416 static u16 pcnet32_dwio_read_rap(unsigned long addr) 417 { 418 return inl(addr + PCNET32_DWIO_RAP) & 0xffff; 419 } 420 421 static void pcnet32_dwio_write_rap(unsigned long addr, u16 val) 422 { 423 outl(val, addr + PCNET32_DWIO_RAP); 424 } 425 426 static void pcnet32_dwio_reset(unsigned long addr) 427 { 428 inl(addr + PCNET32_DWIO_RESET); 429 } 430 431 static int pcnet32_dwio_check(unsigned long addr) 432 { 433 outl(88, addr + PCNET32_DWIO_RAP); 434 return (inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88; 435 } 436 437 static const struct pcnet32_access pcnet32_dwio = { 438 .read_csr = pcnet32_dwio_read_csr, 439 .write_csr = pcnet32_dwio_write_csr, 440 .read_bcr = pcnet32_dwio_read_bcr, 441 .write_bcr = pcnet32_dwio_write_bcr, 442 .read_rap = pcnet32_dwio_read_rap, 443 .write_rap = pcnet32_dwio_write_rap, 444 .reset = pcnet32_dwio_reset 445 }; 446 447 static void pcnet32_netif_stop(struct net_device *dev) 448 { 449 struct pcnet32_private *lp = netdev_priv(dev); 450 451 netif_trans_update(dev); /* prevent tx timeout */ 452 napi_disable(&lp->napi); 453 netif_tx_disable(dev); 454 } 455 456 static void pcnet32_netif_start(struct net_device *dev) 457 { 458 struct pcnet32_private *lp = netdev_priv(dev); 459 ulong ioaddr = dev->base_addr; 460 u16 val; 461 462 netif_wake_queue(dev); 463 val = lp->a->read_csr(ioaddr, CSR3); 464 val &= 0x00ff; 465 lp->a->write_csr(ioaddr, CSR3, val); 466 napi_enable(&lp->napi); 467 } 468 469 /* 470 * Allocate space for the new sized tx ring. 471 * Free old resources 472 * Save new resources. 473 * Any failure keeps old resources. 474 * Must be called with lp->lock held. 475 */ 476 static void pcnet32_realloc_tx_ring(struct net_device *dev, 477 struct pcnet32_private *lp, 478 unsigned int size) 479 { 480 dma_addr_t new_ring_dma_addr; 481 dma_addr_t *new_dma_addr_list; 482 struct pcnet32_tx_head *new_tx_ring; 483 struct sk_buff **new_skb_list; 484 unsigned int entries = BIT(size); 485 486 pcnet32_purge_tx_ring(dev); 487 488 new_tx_ring = 489 pci_zalloc_consistent(lp->pci_dev, 490 sizeof(struct pcnet32_tx_head) * entries, 491 &new_ring_dma_addr); 492 if (new_tx_ring == NULL) 493 return; 494 495 new_dma_addr_list = kcalloc(entries, sizeof(dma_addr_t), GFP_ATOMIC); 496 if (!new_dma_addr_list) 497 goto free_new_tx_ring; 498 499 new_skb_list = kcalloc(entries, sizeof(struct sk_buff *), GFP_ATOMIC); 500 if (!new_skb_list) 501 goto free_new_lists; 502 503 kfree(lp->tx_skbuff); 504 kfree(lp->tx_dma_addr); 505 pci_free_consistent(lp->pci_dev, 506 sizeof(struct pcnet32_tx_head) * lp->tx_ring_size, 507 lp->tx_ring, lp->tx_ring_dma_addr); 508 509 lp->tx_ring_size = entries; 510 lp->tx_mod_mask = lp->tx_ring_size - 1; 511 lp->tx_len_bits = (size << 12); 512 lp->tx_ring = new_tx_ring; 513 lp->tx_ring_dma_addr = new_ring_dma_addr; 514 lp->tx_dma_addr = new_dma_addr_list; 515 lp->tx_skbuff = new_skb_list; 516 return; 517 518 free_new_lists: 519 kfree(new_dma_addr_list); 520 free_new_tx_ring: 521 pci_free_consistent(lp->pci_dev, 522 sizeof(struct pcnet32_tx_head) * entries, 523 new_tx_ring, 524 new_ring_dma_addr); 525 } 526 527 /* 528 * Allocate space for the new sized rx ring. 529 * Re-use old receive buffers. 530 * alloc extra buffers 531 * free unneeded buffers 532 * free unneeded buffers 533 * Save new resources. 534 * Any failure keeps old resources. 535 * Must be called with lp->lock held. 536 */ 537 static void pcnet32_realloc_rx_ring(struct net_device *dev, 538 struct pcnet32_private *lp, 539 unsigned int size) 540 { 541 dma_addr_t new_ring_dma_addr; 542 dma_addr_t *new_dma_addr_list; 543 struct pcnet32_rx_head *new_rx_ring; 544 struct sk_buff **new_skb_list; 545 int new, overlap; 546 unsigned int entries = BIT(size); 547 548 new_rx_ring = 549 pci_zalloc_consistent(lp->pci_dev, 550 sizeof(struct pcnet32_rx_head) * entries, 551 &new_ring_dma_addr); 552 if (new_rx_ring == NULL) 553 return; 554 555 new_dma_addr_list = kcalloc(entries, sizeof(dma_addr_t), GFP_ATOMIC); 556 if (!new_dma_addr_list) 557 goto free_new_rx_ring; 558 559 new_skb_list = kcalloc(entries, sizeof(struct sk_buff *), GFP_ATOMIC); 560 if (!new_skb_list) 561 goto free_new_lists; 562 563 /* first copy the current receive buffers */ 564 overlap = min(entries, lp->rx_ring_size); 565 for (new = 0; new < overlap; new++) { 566 new_rx_ring[new] = lp->rx_ring[new]; 567 new_dma_addr_list[new] = lp->rx_dma_addr[new]; 568 new_skb_list[new] = lp->rx_skbuff[new]; 569 } 570 /* now allocate any new buffers needed */ 571 for (; new < entries; new++) { 572 struct sk_buff *rx_skbuff; 573 new_skb_list[new] = netdev_alloc_skb(dev, PKT_BUF_SKB); 574 rx_skbuff = new_skb_list[new]; 575 if (!rx_skbuff) { 576 /* keep the original lists and buffers */ 577 netif_err(lp, drv, dev, "%s netdev_alloc_skb failed\n", 578 __func__); 579 goto free_all_new; 580 } 581 skb_reserve(rx_skbuff, NET_IP_ALIGN); 582 583 new_dma_addr_list[new] = 584 pci_map_single(lp->pci_dev, rx_skbuff->data, 585 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE); 586 if (pci_dma_mapping_error(lp->pci_dev, 587 new_dma_addr_list[new])) { 588 netif_err(lp, drv, dev, "%s dma mapping failed\n", 589 __func__); 590 dev_kfree_skb(new_skb_list[new]); 591 goto free_all_new; 592 } 593 new_rx_ring[new].base = cpu_to_le32(new_dma_addr_list[new]); 594 new_rx_ring[new].buf_length = cpu_to_le16(NEG_BUF_SIZE); 595 new_rx_ring[new].status = cpu_to_le16(0x8000); 596 } 597 /* and free any unneeded buffers */ 598 for (; new < lp->rx_ring_size; new++) { 599 if (lp->rx_skbuff[new]) { 600 if (!pci_dma_mapping_error(lp->pci_dev, 601 lp->rx_dma_addr[new])) 602 pci_unmap_single(lp->pci_dev, 603 lp->rx_dma_addr[new], 604 PKT_BUF_SIZE, 605 PCI_DMA_FROMDEVICE); 606 dev_kfree_skb(lp->rx_skbuff[new]); 607 } 608 } 609 610 kfree(lp->rx_skbuff); 611 kfree(lp->rx_dma_addr); 612 pci_free_consistent(lp->pci_dev, 613 sizeof(struct pcnet32_rx_head) * 614 lp->rx_ring_size, lp->rx_ring, 615 lp->rx_ring_dma_addr); 616 617 lp->rx_ring_size = entries; 618 lp->rx_mod_mask = lp->rx_ring_size - 1; 619 lp->rx_len_bits = (size << 4); 620 lp->rx_ring = new_rx_ring; 621 lp->rx_ring_dma_addr = new_ring_dma_addr; 622 lp->rx_dma_addr = new_dma_addr_list; 623 lp->rx_skbuff = new_skb_list; 624 return; 625 626 free_all_new: 627 while (--new >= lp->rx_ring_size) { 628 if (new_skb_list[new]) { 629 if (!pci_dma_mapping_error(lp->pci_dev, 630 new_dma_addr_list[new])) 631 pci_unmap_single(lp->pci_dev, 632 new_dma_addr_list[new], 633 PKT_BUF_SIZE, 634 PCI_DMA_FROMDEVICE); 635 dev_kfree_skb(new_skb_list[new]); 636 } 637 } 638 kfree(new_skb_list); 639 free_new_lists: 640 kfree(new_dma_addr_list); 641 free_new_rx_ring: 642 pci_free_consistent(lp->pci_dev, 643 sizeof(struct pcnet32_rx_head) * entries, 644 new_rx_ring, 645 new_ring_dma_addr); 646 } 647 648 static void pcnet32_purge_rx_ring(struct net_device *dev) 649 { 650 struct pcnet32_private *lp = netdev_priv(dev); 651 int i; 652 653 /* free all allocated skbuffs */ 654 for (i = 0; i < lp->rx_ring_size; i++) { 655 lp->rx_ring[i].status = 0; /* CPU owns buffer */ 656 wmb(); /* Make sure adapter sees owner change */ 657 if (lp->rx_skbuff[i]) { 658 if (!pci_dma_mapping_error(lp->pci_dev, 659 lp->rx_dma_addr[i])) 660 pci_unmap_single(lp->pci_dev, 661 lp->rx_dma_addr[i], 662 PKT_BUF_SIZE, 663 PCI_DMA_FROMDEVICE); 664 dev_kfree_skb_any(lp->rx_skbuff[i]); 665 } 666 lp->rx_skbuff[i] = NULL; 667 lp->rx_dma_addr[i] = 0; 668 } 669 } 670 671 #ifdef CONFIG_NET_POLL_CONTROLLER 672 static void pcnet32_poll_controller(struct net_device *dev) 673 { 674 disable_irq(dev->irq); 675 pcnet32_interrupt(0, dev); 676 enable_irq(dev->irq); 677 } 678 #endif 679 680 static int pcnet32_get_link_ksettings(struct net_device *dev, 681 struct ethtool_link_ksettings *cmd) 682 { 683 struct pcnet32_private *lp = netdev_priv(dev); 684 unsigned long flags; 685 int r = -EOPNOTSUPP; 686 687 if (lp->mii) { 688 spin_lock_irqsave(&lp->lock, flags); 689 mii_ethtool_get_link_ksettings(&lp->mii_if, cmd); 690 spin_unlock_irqrestore(&lp->lock, flags); 691 r = 0; 692 } 693 return r; 694 } 695 696 static int pcnet32_set_link_ksettings(struct net_device *dev, 697 const struct ethtool_link_ksettings *cmd) 698 { 699 struct pcnet32_private *lp = netdev_priv(dev); 700 unsigned long flags; 701 int r = -EOPNOTSUPP; 702 703 if (lp->mii) { 704 spin_lock_irqsave(&lp->lock, flags); 705 r = mii_ethtool_set_link_ksettings(&lp->mii_if, cmd); 706 spin_unlock_irqrestore(&lp->lock, flags); 707 } 708 return r; 709 } 710 711 static void pcnet32_get_drvinfo(struct net_device *dev, 712 struct ethtool_drvinfo *info) 713 { 714 struct pcnet32_private *lp = netdev_priv(dev); 715 716 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 717 strlcpy(info->version, DRV_VERSION, sizeof(info->version)); 718 if (lp->pci_dev) 719 strlcpy(info->bus_info, pci_name(lp->pci_dev), 720 sizeof(info->bus_info)); 721 else 722 snprintf(info->bus_info, sizeof(info->bus_info), 723 "VLB 0x%lx", dev->base_addr); 724 } 725 726 static u32 pcnet32_get_link(struct net_device *dev) 727 { 728 struct pcnet32_private *lp = netdev_priv(dev); 729 unsigned long flags; 730 int r; 731 732 spin_lock_irqsave(&lp->lock, flags); 733 if (lp->mii) { 734 r = mii_link_ok(&lp->mii_if); 735 } else if (lp->chip_version >= PCNET32_79C970A) { 736 ulong ioaddr = dev->base_addr; /* card base I/O address */ 737 r = (lp->a->read_bcr(ioaddr, 4) != 0xc0); 738 } else { /* can not detect link on really old chips */ 739 r = 1; 740 } 741 spin_unlock_irqrestore(&lp->lock, flags); 742 743 return r; 744 } 745 746 static u32 pcnet32_get_msglevel(struct net_device *dev) 747 { 748 struct pcnet32_private *lp = netdev_priv(dev); 749 return lp->msg_enable; 750 } 751 752 static void pcnet32_set_msglevel(struct net_device *dev, u32 value) 753 { 754 struct pcnet32_private *lp = netdev_priv(dev); 755 lp->msg_enable = value; 756 } 757 758 static int pcnet32_nway_reset(struct net_device *dev) 759 { 760 struct pcnet32_private *lp = netdev_priv(dev); 761 unsigned long flags; 762 int r = -EOPNOTSUPP; 763 764 if (lp->mii) { 765 spin_lock_irqsave(&lp->lock, flags); 766 r = mii_nway_restart(&lp->mii_if); 767 spin_unlock_irqrestore(&lp->lock, flags); 768 } 769 return r; 770 } 771 772 static void pcnet32_get_ringparam(struct net_device *dev, 773 struct ethtool_ringparam *ering) 774 { 775 struct pcnet32_private *lp = netdev_priv(dev); 776 777 ering->tx_max_pending = TX_MAX_RING_SIZE; 778 ering->tx_pending = lp->tx_ring_size; 779 ering->rx_max_pending = RX_MAX_RING_SIZE; 780 ering->rx_pending = lp->rx_ring_size; 781 } 782 783 static int pcnet32_set_ringparam(struct net_device *dev, 784 struct ethtool_ringparam *ering) 785 { 786 struct pcnet32_private *lp = netdev_priv(dev); 787 unsigned long flags; 788 unsigned int size; 789 ulong ioaddr = dev->base_addr; 790 int i; 791 792 if (ering->rx_mini_pending || ering->rx_jumbo_pending) 793 return -EINVAL; 794 795 if (netif_running(dev)) 796 pcnet32_netif_stop(dev); 797 798 spin_lock_irqsave(&lp->lock, flags); 799 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */ 800 801 size = min(ering->tx_pending, (unsigned int)TX_MAX_RING_SIZE); 802 803 /* set the minimum ring size to 4, to allow the loopback test to work 804 * unchanged. 805 */ 806 for (i = 2; i <= PCNET32_LOG_MAX_TX_BUFFERS; i++) { 807 if (size <= (1 << i)) 808 break; 809 } 810 if ((1 << i) != lp->tx_ring_size) 811 pcnet32_realloc_tx_ring(dev, lp, i); 812 813 size = min(ering->rx_pending, (unsigned int)RX_MAX_RING_SIZE); 814 for (i = 2; i <= PCNET32_LOG_MAX_RX_BUFFERS; i++) { 815 if (size <= (1 << i)) 816 break; 817 } 818 if ((1 << i) != lp->rx_ring_size) 819 pcnet32_realloc_rx_ring(dev, lp, i); 820 821 lp->napi.weight = lp->rx_ring_size / 2; 822 823 if (netif_running(dev)) { 824 pcnet32_netif_start(dev); 825 pcnet32_restart(dev, CSR0_NORMAL); 826 } 827 828 spin_unlock_irqrestore(&lp->lock, flags); 829 830 netif_info(lp, drv, dev, "Ring Param Settings: RX: %d, TX: %d\n", 831 lp->rx_ring_size, lp->tx_ring_size); 832 833 return 0; 834 } 835 836 static void pcnet32_get_strings(struct net_device *dev, u32 stringset, 837 u8 *data) 838 { 839 memcpy(data, pcnet32_gstrings_test, sizeof(pcnet32_gstrings_test)); 840 } 841 842 static int pcnet32_get_sset_count(struct net_device *dev, int sset) 843 { 844 switch (sset) { 845 case ETH_SS_TEST: 846 return PCNET32_TEST_LEN; 847 default: 848 return -EOPNOTSUPP; 849 } 850 } 851 852 static void pcnet32_ethtool_test(struct net_device *dev, 853 struct ethtool_test *test, u64 * data) 854 { 855 struct pcnet32_private *lp = netdev_priv(dev); 856 int rc; 857 858 if (test->flags == ETH_TEST_FL_OFFLINE) { 859 rc = pcnet32_loopback_test(dev, data); 860 if (rc) { 861 netif_printk(lp, hw, KERN_DEBUG, dev, 862 "Loopback test failed\n"); 863 test->flags |= ETH_TEST_FL_FAILED; 864 } else 865 netif_printk(lp, hw, KERN_DEBUG, dev, 866 "Loopback test passed\n"); 867 } else 868 netif_printk(lp, hw, KERN_DEBUG, dev, 869 "No tests to run (specify 'Offline' on ethtool)\n"); 870 } /* end pcnet32_ethtool_test */ 871 872 static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1) 873 { 874 struct pcnet32_private *lp = netdev_priv(dev); 875 const struct pcnet32_access *a = lp->a; /* access to registers */ 876 ulong ioaddr = dev->base_addr; /* card base I/O address */ 877 struct sk_buff *skb; /* sk buff */ 878 int x, i; /* counters */ 879 int numbuffs = 4; /* number of TX/RX buffers and descs */ 880 u16 status = 0x8300; /* TX ring status */ 881 __le16 teststatus; /* test of ring status */ 882 int rc; /* return code */ 883 int size; /* size of packets */ 884 unsigned char *packet; /* source packet data */ 885 static const int data_len = 60; /* length of source packets */ 886 unsigned long flags; 887 unsigned long ticks; 888 889 rc = 1; /* default to fail */ 890 891 if (netif_running(dev)) 892 pcnet32_netif_stop(dev); 893 894 spin_lock_irqsave(&lp->lock, flags); 895 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */ 896 897 numbuffs = min(numbuffs, (int)min(lp->rx_ring_size, lp->tx_ring_size)); 898 899 /* Reset the PCNET32 */ 900 lp->a->reset(ioaddr); 901 lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */ 902 903 /* switch pcnet32 to 32bit mode */ 904 lp->a->write_bcr(ioaddr, 20, 2); 905 906 /* purge & init rings but don't actually restart */ 907 pcnet32_restart(dev, 0x0000); 908 909 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */ 910 911 /* Initialize Transmit buffers. */ 912 size = data_len + 15; 913 for (x = 0; x < numbuffs; x++) { 914 skb = netdev_alloc_skb(dev, size); 915 if (!skb) { 916 netif_printk(lp, hw, KERN_DEBUG, dev, 917 "Cannot allocate skb at line: %d!\n", 918 __LINE__); 919 goto clean_up; 920 } 921 packet = skb->data; 922 skb_put(skb, size); /* create space for data */ 923 lp->tx_skbuff[x] = skb; 924 lp->tx_ring[x].length = cpu_to_le16(-skb->len); 925 lp->tx_ring[x].misc = 0; 926 927 /* put DA and SA into the skb */ 928 for (i = 0; i < 6; i++) 929 *packet++ = dev->dev_addr[i]; 930 for (i = 0; i < 6; i++) 931 *packet++ = dev->dev_addr[i]; 932 /* type */ 933 *packet++ = 0x08; 934 *packet++ = 0x06; 935 /* packet number */ 936 *packet++ = x; 937 /* fill packet with data */ 938 for (i = 0; i < data_len; i++) 939 *packet++ = i; 940 941 lp->tx_dma_addr[x] = 942 pci_map_single(lp->pci_dev, skb->data, skb->len, 943 PCI_DMA_TODEVICE); 944 if (pci_dma_mapping_error(lp->pci_dev, lp->tx_dma_addr[x])) { 945 netif_printk(lp, hw, KERN_DEBUG, dev, 946 "DMA mapping error at line: %d!\n", 947 __LINE__); 948 goto clean_up; 949 } 950 lp->tx_ring[x].base = cpu_to_le32(lp->tx_dma_addr[x]); 951 wmb(); /* Make sure owner changes after all others are visible */ 952 lp->tx_ring[x].status = cpu_to_le16(status); 953 } 954 955 x = a->read_bcr(ioaddr, 32); /* set internal loopback in BCR32 */ 956 a->write_bcr(ioaddr, 32, x | 0x0002); 957 958 /* set int loopback in CSR15 */ 959 x = a->read_csr(ioaddr, CSR15) & 0xfffc; 960 lp->a->write_csr(ioaddr, CSR15, x | 0x0044); 961 962 teststatus = cpu_to_le16(0x8000); 963 lp->a->write_csr(ioaddr, CSR0, CSR0_START); /* Set STRT bit */ 964 965 /* Check status of descriptors */ 966 for (x = 0; x < numbuffs; x++) { 967 ticks = 0; 968 rmb(); 969 while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) { 970 spin_unlock_irqrestore(&lp->lock, flags); 971 msleep(1); 972 spin_lock_irqsave(&lp->lock, flags); 973 rmb(); 974 ticks++; 975 } 976 if (ticks == 200) { 977 netif_err(lp, hw, dev, "Desc %d failed to reset!\n", x); 978 break; 979 } 980 } 981 982 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */ 983 wmb(); 984 if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) { 985 netdev_printk(KERN_DEBUG, dev, "RX loopback packets:\n"); 986 987 for (x = 0; x < numbuffs; x++) { 988 netdev_printk(KERN_DEBUG, dev, "Packet %d: ", x); 989 skb = lp->rx_skbuff[x]; 990 for (i = 0; i < size; i++) 991 pr_cont(" %02x", *(skb->data + i)); 992 pr_cont("\n"); 993 } 994 } 995 996 x = 0; 997 rc = 0; 998 while (x < numbuffs && !rc) { 999 skb = lp->rx_skbuff[x]; 1000 packet = lp->tx_skbuff[x]->data; 1001 for (i = 0; i < size; i++) { 1002 if (*(skb->data + i) != packet[i]) { 1003 netif_printk(lp, hw, KERN_DEBUG, dev, 1004 "Error in compare! %2x - %02x %02x\n", 1005 i, *(skb->data + i), packet[i]); 1006 rc = 1; 1007 break; 1008 } 1009 } 1010 x++; 1011 } 1012 1013 clean_up: 1014 *data1 = rc; 1015 pcnet32_purge_tx_ring(dev); 1016 1017 x = a->read_csr(ioaddr, CSR15); 1018 a->write_csr(ioaddr, CSR15, (x & ~0x0044)); /* reset bits 6 and 2 */ 1019 1020 x = a->read_bcr(ioaddr, 32); /* reset internal loopback */ 1021 a->write_bcr(ioaddr, 32, (x & ~0x0002)); 1022 1023 if (netif_running(dev)) { 1024 pcnet32_netif_start(dev); 1025 pcnet32_restart(dev, CSR0_NORMAL); 1026 } else { 1027 pcnet32_purge_rx_ring(dev); 1028 lp->a->write_bcr(ioaddr, 20, 4); /* return to 16bit mode */ 1029 } 1030 spin_unlock_irqrestore(&lp->lock, flags); 1031 1032 return rc; 1033 } /* end pcnet32_loopback_test */ 1034 1035 static int pcnet32_set_phys_id(struct net_device *dev, 1036 enum ethtool_phys_id_state state) 1037 { 1038 struct pcnet32_private *lp = netdev_priv(dev); 1039 const struct pcnet32_access *a = lp->a; 1040 ulong ioaddr = dev->base_addr; 1041 unsigned long flags; 1042 int i; 1043 1044 switch (state) { 1045 case ETHTOOL_ID_ACTIVE: 1046 /* Save the current value of the bcrs */ 1047 spin_lock_irqsave(&lp->lock, flags); 1048 for (i = 4; i < 8; i++) 1049 lp->save_regs[i - 4] = a->read_bcr(ioaddr, i); 1050 spin_unlock_irqrestore(&lp->lock, flags); 1051 return 2; /* cycle on/off twice per second */ 1052 1053 case ETHTOOL_ID_ON: 1054 case ETHTOOL_ID_OFF: 1055 /* Blink the led */ 1056 spin_lock_irqsave(&lp->lock, flags); 1057 for (i = 4; i < 8; i++) 1058 a->write_bcr(ioaddr, i, a->read_bcr(ioaddr, i) ^ 0x4000); 1059 spin_unlock_irqrestore(&lp->lock, flags); 1060 break; 1061 1062 case ETHTOOL_ID_INACTIVE: 1063 /* Restore the original value of the bcrs */ 1064 spin_lock_irqsave(&lp->lock, flags); 1065 for (i = 4; i < 8; i++) 1066 a->write_bcr(ioaddr, i, lp->save_regs[i - 4]); 1067 spin_unlock_irqrestore(&lp->lock, flags); 1068 } 1069 return 0; 1070 } 1071 1072 /* 1073 * lp->lock must be held. 1074 */ 1075 static int pcnet32_suspend(struct net_device *dev, unsigned long *flags, 1076 int can_sleep) 1077 { 1078 int csr5; 1079 struct pcnet32_private *lp = netdev_priv(dev); 1080 const struct pcnet32_access *a = lp->a; 1081 ulong ioaddr = dev->base_addr; 1082 int ticks; 1083 1084 /* really old chips have to be stopped. */ 1085 if (lp->chip_version < PCNET32_79C970A) 1086 return 0; 1087 1088 /* set SUSPEND (SPND) - CSR5 bit 0 */ 1089 csr5 = a->read_csr(ioaddr, CSR5); 1090 a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND); 1091 1092 /* poll waiting for bit to be set */ 1093 ticks = 0; 1094 while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) { 1095 spin_unlock_irqrestore(&lp->lock, *flags); 1096 if (can_sleep) 1097 msleep(1); 1098 else 1099 mdelay(1); 1100 spin_lock_irqsave(&lp->lock, *flags); 1101 ticks++; 1102 if (ticks > 200) { 1103 netif_printk(lp, hw, KERN_DEBUG, dev, 1104 "Error getting into suspend!\n"); 1105 return 0; 1106 } 1107 } 1108 return 1; 1109 } 1110 1111 /* 1112 * process one receive descriptor entry 1113 */ 1114 1115 static void pcnet32_rx_entry(struct net_device *dev, 1116 struct pcnet32_private *lp, 1117 struct pcnet32_rx_head *rxp, 1118 int entry) 1119 { 1120 int status = (short)le16_to_cpu(rxp->status) >> 8; 1121 int rx_in_place = 0; 1122 struct sk_buff *skb; 1123 short pkt_len; 1124 1125 if (status != 0x03) { /* There was an error. */ 1126 /* 1127 * There is a tricky error noted by John Murphy, 1128 * <murf@perftech.com> to Russ Nelson: Even with full-sized 1129 * buffers it's possible for a jabber packet to use two 1130 * buffers, with only the last correctly noting the error. 1131 */ 1132 if (status & 0x01) /* Only count a general error at the */ 1133 dev->stats.rx_errors++; /* end of a packet. */ 1134 if (status & 0x20) 1135 dev->stats.rx_frame_errors++; 1136 if (status & 0x10) 1137 dev->stats.rx_over_errors++; 1138 if (status & 0x08) 1139 dev->stats.rx_crc_errors++; 1140 if (status & 0x04) 1141 dev->stats.rx_fifo_errors++; 1142 return; 1143 } 1144 1145 pkt_len = (le32_to_cpu(rxp->msg_length) & 0xfff) - 4; 1146 1147 /* Discard oversize frames. */ 1148 if (unlikely(pkt_len > PKT_BUF_SIZE)) { 1149 netif_err(lp, drv, dev, "Impossible packet size %d!\n", 1150 pkt_len); 1151 dev->stats.rx_errors++; 1152 return; 1153 } 1154 if (pkt_len < 60) { 1155 netif_err(lp, rx_err, dev, "Runt packet!\n"); 1156 dev->stats.rx_errors++; 1157 return; 1158 } 1159 1160 if (pkt_len > rx_copybreak) { 1161 struct sk_buff *newskb; 1162 dma_addr_t new_dma_addr; 1163 1164 newskb = netdev_alloc_skb(dev, PKT_BUF_SKB); 1165 /* 1166 * map the new buffer, if mapping fails, drop the packet and 1167 * reuse the old buffer 1168 */ 1169 if (newskb) { 1170 skb_reserve(newskb, NET_IP_ALIGN); 1171 new_dma_addr = pci_map_single(lp->pci_dev, 1172 newskb->data, 1173 PKT_BUF_SIZE, 1174 PCI_DMA_FROMDEVICE); 1175 if (pci_dma_mapping_error(lp->pci_dev, new_dma_addr)) { 1176 netif_err(lp, rx_err, dev, 1177 "DMA mapping error.\n"); 1178 dev_kfree_skb(newskb); 1179 skb = NULL; 1180 } else { 1181 skb = lp->rx_skbuff[entry]; 1182 pci_unmap_single(lp->pci_dev, 1183 lp->rx_dma_addr[entry], 1184 PKT_BUF_SIZE, 1185 PCI_DMA_FROMDEVICE); 1186 skb_put(skb, pkt_len); 1187 lp->rx_skbuff[entry] = newskb; 1188 lp->rx_dma_addr[entry] = new_dma_addr; 1189 rxp->base = cpu_to_le32(new_dma_addr); 1190 rx_in_place = 1; 1191 } 1192 } else 1193 skb = NULL; 1194 } else 1195 skb = netdev_alloc_skb(dev, pkt_len + NET_IP_ALIGN); 1196 1197 if (skb == NULL) { 1198 dev->stats.rx_dropped++; 1199 return; 1200 } 1201 if (!rx_in_place) { 1202 skb_reserve(skb, NET_IP_ALIGN); 1203 skb_put(skb, pkt_len); /* Make room */ 1204 pci_dma_sync_single_for_cpu(lp->pci_dev, 1205 lp->rx_dma_addr[entry], 1206 pkt_len, 1207 PCI_DMA_FROMDEVICE); 1208 skb_copy_to_linear_data(skb, 1209 (unsigned char *)(lp->rx_skbuff[entry]->data), 1210 pkt_len); 1211 pci_dma_sync_single_for_device(lp->pci_dev, 1212 lp->rx_dma_addr[entry], 1213 pkt_len, 1214 PCI_DMA_FROMDEVICE); 1215 } 1216 dev->stats.rx_bytes += skb->len; 1217 skb->protocol = eth_type_trans(skb, dev); 1218 netif_receive_skb(skb); 1219 dev->stats.rx_packets++; 1220 } 1221 1222 static int pcnet32_rx(struct net_device *dev, int budget) 1223 { 1224 struct pcnet32_private *lp = netdev_priv(dev); 1225 int entry = lp->cur_rx & lp->rx_mod_mask; 1226 struct pcnet32_rx_head *rxp = &lp->rx_ring[entry]; 1227 int npackets = 0; 1228 1229 /* If we own the next entry, it's a new packet. Send it up. */ 1230 while (npackets < budget && (short)le16_to_cpu(rxp->status) >= 0) { 1231 pcnet32_rx_entry(dev, lp, rxp, entry); 1232 npackets += 1; 1233 /* 1234 * The docs say that the buffer length isn't touched, but Andrew 1235 * Boyd of QNX reports that some revs of the 79C965 clear it. 1236 */ 1237 rxp->buf_length = cpu_to_le16(NEG_BUF_SIZE); 1238 wmb(); /* Make sure owner changes after others are visible */ 1239 rxp->status = cpu_to_le16(0x8000); 1240 entry = (++lp->cur_rx) & lp->rx_mod_mask; 1241 rxp = &lp->rx_ring[entry]; 1242 } 1243 1244 return npackets; 1245 } 1246 1247 static int pcnet32_tx(struct net_device *dev) 1248 { 1249 struct pcnet32_private *lp = netdev_priv(dev); 1250 unsigned int dirty_tx = lp->dirty_tx; 1251 int delta; 1252 int must_restart = 0; 1253 1254 while (dirty_tx != lp->cur_tx) { 1255 int entry = dirty_tx & lp->tx_mod_mask; 1256 int status = (short)le16_to_cpu(lp->tx_ring[entry].status); 1257 1258 if (status < 0) 1259 break; /* It still hasn't been Txed */ 1260 1261 lp->tx_ring[entry].base = 0; 1262 1263 if (status & 0x4000) { 1264 /* There was a major error, log it. */ 1265 int err_status = le32_to_cpu(lp->tx_ring[entry].misc); 1266 dev->stats.tx_errors++; 1267 netif_err(lp, tx_err, dev, 1268 "Tx error status=%04x err_status=%08x\n", 1269 status, err_status); 1270 if (err_status & 0x04000000) 1271 dev->stats.tx_aborted_errors++; 1272 if (err_status & 0x08000000) 1273 dev->stats.tx_carrier_errors++; 1274 if (err_status & 0x10000000) 1275 dev->stats.tx_window_errors++; 1276 #ifndef DO_DXSUFLO 1277 if (err_status & 0x40000000) { 1278 dev->stats.tx_fifo_errors++; 1279 /* Ackk! On FIFO errors the Tx unit is turned off! */ 1280 /* Remove this verbosity later! */ 1281 netif_err(lp, tx_err, dev, "Tx FIFO error!\n"); 1282 must_restart = 1; 1283 } 1284 #else 1285 if (err_status & 0x40000000) { 1286 dev->stats.tx_fifo_errors++; 1287 if (!lp->dxsuflo) { /* If controller doesn't recover ... */ 1288 /* Ackk! On FIFO errors the Tx unit is turned off! */ 1289 /* Remove this verbosity later! */ 1290 netif_err(lp, tx_err, dev, "Tx FIFO error!\n"); 1291 must_restart = 1; 1292 } 1293 } 1294 #endif 1295 } else { 1296 if (status & 0x1800) 1297 dev->stats.collisions++; 1298 dev->stats.tx_packets++; 1299 } 1300 1301 /* We must free the original skb */ 1302 if (lp->tx_skbuff[entry]) { 1303 pci_unmap_single(lp->pci_dev, 1304 lp->tx_dma_addr[entry], 1305 lp->tx_skbuff[entry]-> 1306 len, PCI_DMA_TODEVICE); 1307 dev_kfree_skb_any(lp->tx_skbuff[entry]); 1308 lp->tx_skbuff[entry] = NULL; 1309 lp->tx_dma_addr[entry] = 0; 1310 } 1311 dirty_tx++; 1312 } 1313 1314 delta = (lp->cur_tx - dirty_tx) & (lp->tx_mod_mask + lp->tx_ring_size); 1315 if (delta > lp->tx_ring_size) { 1316 netif_err(lp, drv, dev, "out-of-sync dirty pointer, %d vs. %d, full=%d\n", 1317 dirty_tx, lp->cur_tx, lp->tx_full); 1318 dirty_tx += lp->tx_ring_size; 1319 delta -= lp->tx_ring_size; 1320 } 1321 1322 if (lp->tx_full && 1323 netif_queue_stopped(dev) && 1324 delta < lp->tx_ring_size - 2) { 1325 /* The ring is no longer full, clear tbusy. */ 1326 lp->tx_full = 0; 1327 netif_wake_queue(dev); 1328 } 1329 lp->dirty_tx = dirty_tx; 1330 1331 return must_restart; 1332 } 1333 1334 static int pcnet32_poll(struct napi_struct *napi, int budget) 1335 { 1336 struct pcnet32_private *lp = container_of(napi, struct pcnet32_private, napi); 1337 struct net_device *dev = lp->dev; 1338 unsigned long ioaddr = dev->base_addr; 1339 unsigned long flags; 1340 int work_done; 1341 u16 val; 1342 1343 work_done = pcnet32_rx(dev, budget); 1344 1345 spin_lock_irqsave(&lp->lock, flags); 1346 if (pcnet32_tx(dev)) { 1347 /* reset the chip to clear the error condition, then restart */ 1348 lp->a->reset(ioaddr); 1349 lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */ 1350 pcnet32_restart(dev, CSR0_START); 1351 netif_wake_queue(dev); 1352 } 1353 spin_unlock_irqrestore(&lp->lock, flags); 1354 1355 if (work_done < budget) { 1356 spin_lock_irqsave(&lp->lock, flags); 1357 1358 __napi_complete(napi); 1359 1360 /* clear interrupt masks */ 1361 val = lp->a->read_csr(ioaddr, CSR3); 1362 val &= 0x00ff; 1363 lp->a->write_csr(ioaddr, CSR3, val); 1364 1365 /* Set interrupt enable. */ 1366 lp->a->write_csr(ioaddr, CSR0, CSR0_INTEN); 1367 1368 spin_unlock_irqrestore(&lp->lock, flags); 1369 } 1370 return work_done; 1371 } 1372 1373 #define PCNET32_REGS_PER_PHY 32 1374 #define PCNET32_MAX_PHYS 32 1375 static int pcnet32_get_regs_len(struct net_device *dev) 1376 { 1377 struct pcnet32_private *lp = netdev_priv(dev); 1378 int j = lp->phycount * PCNET32_REGS_PER_PHY; 1379 1380 return (PCNET32_NUM_REGS + j) * sizeof(u16); 1381 } 1382 1383 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1384 void *ptr) 1385 { 1386 int i, csr0; 1387 u16 *buff = ptr; 1388 struct pcnet32_private *lp = netdev_priv(dev); 1389 const struct pcnet32_access *a = lp->a; 1390 ulong ioaddr = dev->base_addr; 1391 unsigned long flags; 1392 1393 spin_lock_irqsave(&lp->lock, flags); 1394 1395 csr0 = a->read_csr(ioaddr, CSR0); 1396 if (!(csr0 & CSR0_STOP)) /* If not stopped */ 1397 pcnet32_suspend(dev, &flags, 1); 1398 1399 /* read address PROM */ 1400 for (i = 0; i < 16; i += 2) 1401 *buff++ = inw(ioaddr + i); 1402 1403 /* read control and status registers */ 1404 for (i = 0; i < 90; i++) 1405 *buff++ = a->read_csr(ioaddr, i); 1406 1407 *buff++ = a->read_csr(ioaddr, 112); 1408 *buff++ = a->read_csr(ioaddr, 114); 1409 1410 /* read bus configuration registers */ 1411 for (i = 0; i < 30; i++) 1412 *buff++ = a->read_bcr(ioaddr, i); 1413 1414 *buff++ = 0; /* skip bcr30 so as not to hang 79C976 */ 1415 1416 for (i = 31; i < 36; i++) 1417 *buff++ = a->read_bcr(ioaddr, i); 1418 1419 /* read mii phy registers */ 1420 if (lp->mii) { 1421 int j; 1422 for (j = 0; j < PCNET32_MAX_PHYS; j++) { 1423 if (lp->phymask & (1 << j)) { 1424 for (i = 0; i < PCNET32_REGS_PER_PHY; i++) { 1425 lp->a->write_bcr(ioaddr, 33, 1426 (j << 5) | i); 1427 *buff++ = lp->a->read_bcr(ioaddr, 34); 1428 } 1429 } 1430 } 1431 } 1432 1433 if (!(csr0 & CSR0_STOP)) { /* If not stopped */ 1434 int csr5; 1435 1436 /* clear SUSPEND (SPND) - CSR5 bit 0 */ 1437 csr5 = a->read_csr(ioaddr, CSR5); 1438 a->write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND)); 1439 } 1440 1441 spin_unlock_irqrestore(&lp->lock, flags); 1442 } 1443 1444 static const struct ethtool_ops pcnet32_ethtool_ops = { 1445 .get_drvinfo = pcnet32_get_drvinfo, 1446 .get_msglevel = pcnet32_get_msglevel, 1447 .set_msglevel = pcnet32_set_msglevel, 1448 .nway_reset = pcnet32_nway_reset, 1449 .get_link = pcnet32_get_link, 1450 .get_ringparam = pcnet32_get_ringparam, 1451 .set_ringparam = pcnet32_set_ringparam, 1452 .get_strings = pcnet32_get_strings, 1453 .self_test = pcnet32_ethtool_test, 1454 .set_phys_id = pcnet32_set_phys_id, 1455 .get_regs_len = pcnet32_get_regs_len, 1456 .get_regs = pcnet32_get_regs, 1457 .get_sset_count = pcnet32_get_sset_count, 1458 .get_link_ksettings = pcnet32_get_link_ksettings, 1459 .set_link_ksettings = pcnet32_set_link_ksettings, 1460 }; 1461 1462 /* only probes for non-PCI devices, the rest are handled by 1463 * pci_register_driver via pcnet32_probe_pci */ 1464 1465 static void pcnet32_probe_vlbus(unsigned int *pcnet32_portlist) 1466 { 1467 unsigned int *port, ioaddr; 1468 1469 /* search for PCnet32 VLB cards at known addresses */ 1470 for (port = pcnet32_portlist; (ioaddr = *port); port++) { 1471 if (request_region 1472 (ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_vlbus")) { 1473 /* check if there is really a pcnet chip on that ioaddr */ 1474 if ((inb(ioaddr + 14) == 0x57) && 1475 (inb(ioaddr + 15) == 0x57)) { 1476 pcnet32_probe1(ioaddr, 0, NULL); 1477 } else { 1478 release_region(ioaddr, PCNET32_TOTAL_SIZE); 1479 } 1480 } 1481 } 1482 } 1483 1484 static int 1485 pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent) 1486 { 1487 unsigned long ioaddr; 1488 int err; 1489 1490 err = pci_enable_device(pdev); 1491 if (err < 0) { 1492 if (pcnet32_debug & NETIF_MSG_PROBE) 1493 pr_err("failed to enable device -- err=%d\n", err); 1494 return err; 1495 } 1496 pci_set_master(pdev); 1497 1498 ioaddr = pci_resource_start(pdev, 0); 1499 if (!ioaddr) { 1500 if (pcnet32_debug & NETIF_MSG_PROBE) 1501 pr_err("card has no PCI IO resources, aborting\n"); 1502 return -ENODEV; 1503 } 1504 1505 err = pci_set_dma_mask(pdev, PCNET32_DMA_MASK); 1506 if (err) { 1507 if (pcnet32_debug & NETIF_MSG_PROBE) 1508 pr_err("architecture does not support 32bit PCI busmaster DMA\n"); 1509 return err; 1510 } 1511 if (!request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_pci")) { 1512 if (pcnet32_debug & NETIF_MSG_PROBE) 1513 pr_err("io address range already allocated\n"); 1514 return -EBUSY; 1515 } 1516 1517 err = pcnet32_probe1(ioaddr, 1, pdev); 1518 if (err < 0) 1519 pci_disable_device(pdev); 1520 1521 return err; 1522 } 1523 1524 static const struct net_device_ops pcnet32_netdev_ops = { 1525 .ndo_open = pcnet32_open, 1526 .ndo_stop = pcnet32_close, 1527 .ndo_start_xmit = pcnet32_start_xmit, 1528 .ndo_tx_timeout = pcnet32_tx_timeout, 1529 .ndo_get_stats = pcnet32_get_stats, 1530 .ndo_set_rx_mode = pcnet32_set_multicast_list, 1531 .ndo_do_ioctl = pcnet32_ioctl, 1532 .ndo_set_mac_address = eth_mac_addr, 1533 .ndo_validate_addr = eth_validate_addr, 1534 #ifdef CONFIG_NET_POLL_CONTROLLER 1535 .ndo_poll_controller = pcnet32_poll_controller, 1536 #endif 1537 }; 1538 1539 /* pcnet32_probe1 1540 * Called from both pcnet32_probe_vlbus and pcnet_probe_pci. 1541 * pdev will be NULL when called from pcnet32_probe_vlbus. 1542 */ 1543 static int 1544 pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev) 1545 { 1546 struct pcnet32_private *lp; 1547 int i, media; 1548 int fdx, mii, fset, dxsuflo, sram; 1549 int chip_version; 1550 char *chipname; 1551 struct net_device *dev; 1552 const struct pcnet32_access *a = NULL; 1553 u8 promaddr[ETH_ALEN]; 1554 int ret = -ENODEV; 1555 1556 /* reset the chip */ 1557 pcnet32_wio_reset(ioaddr); 1558 1559 /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */ 1560 if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) { 1561 a = &pcnet32_wio; 1562 } else { 1563 pcnet32_dwio_reset(ioaddr); 1564 if (pcnet32_dwio_read_csr(ioaddr, 0) == 4 && 1565 pcnet32_dwio_check(ioaddr)) { 1566 a = &pcnet32_dwio; 1567 } else { 1568 if (pcnet32_debug & NETIF_MSG_PROBE) 1569 pr_err("No access methods\n"); 1570 goto err_release_region; 1571 } 1572 } 1573 1574 chip_version = 1575 a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr, 89) << 16); 1576 if ((pcnet32_debug & NETIF_MSG_PROBE) && (pcnet32_debug & NETIF_MSG_HW)) 1577 pr_info(" PCnet chip version is %#x\n", chip_version); 1578 if ((chip_version & 0xfff) != 0x003) { 1579 if (pcnet32_debug & NETIF_MSG_PROBE) 1580 pr_info("Unsupported chip version\n"); 1581 goto err_release_region; 1582 } 1583 1584 /* initialize variables */ 1585 fdx = mii = fset = dxsuflo = sram = 0; 1586 chip_version = (chip_version >> 12) & 0xffff; 1587 1588 switch (chip_version) { 1589 case 0x2420: 1590 chipname = "PCnet/PCI 79C970"; /* PCI */ 1591 break; 1592 case 0x2430: 1593 if (shared) 1594 chipname = "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */ 1595 else 1596 chipname = "PCnet/32 79C965"; /* 486/VL bus */ 1597 break; 1598 case 0x2621: 1599 chipname = "PCnet/PCI II 79C970A"; /* PCI */ 1600 fdx = 1; 1601 break; 1602 case 0x2623: 1603 chipname = "PCnet/FAST 79C971"; /* PCI */ 1604 fdx = 1; 1605 mii = 1; 1606 fset = 1; 1607 break; 1608 case 0x2624: 1609 chipname = "PCnet/FAST+ 79C972"; /* PCI */ 1610 fdx = 1; 1611 mii = 1; 1612 fset = 1; 1613 break; 1614 case 0x2625: 1615 chipname = "PCnet/FAST III 79C973"; /* PCI */ 1616 fdx = 1; 1617 mii = 1; 1618 sram = 1; 1619 break; 1620 case 0x2626: 1621 chipname = "PCnet/Home 79C978"; /* PCI */ 1622 fdx = 1; 1623 /* 1624 * This is based on specs published at www.amd.com. This section 1625 * assumes that a card with a 79C978 wants to go into standard 1626 * ethernet mode. The 79C978 can also go into 1Mb HomePNA mode, 1627 * and the module option homepna=1 can select this instead. 1628 */ 1629 media = a->read_bcr(ioaddr, 49); 1630 media &= ~3; /* default to 10Mb ethernet */ 1631 if (cards_found < MAX_UNITS && homepna[cards_found]) 1632 media |= 1; /* switch to home wiring mode */ 1633 if (pcnet32_debug & NETIF_MSG_PROBE) 1634 printk(KERN_DEBUG PFX "media set to %sMbit mode\n", 1635 (media & 1) ? "1" : "10"); 1636 a->write_bcr(ioaddr, 49, media); 1637 break; 1638 case 0x2627: 1639 chipname = "PCnet/FAST III 79C975"; /* PCI */ 1640 fdx = 1; 1641 mii = 1; 1642 sram = 1; 1643 break; 1644 case 0x2628: 1645 chipname = "PCnet/PRO 79C976"; 1646 fdx = 1; 1647 mii = 1; 1648 break; 1649 default: 1650 if (pcnet32_debug & NETIF_MSG_PROBE) 1651 pr_info("PCnet version %#x, no PCnet32 chip\n", 1652 chip_version); 1653 goto err_release_region; 1654 } 1655 1656 /* 1657 * On selected chips turn on the BCR18:NOUFLO bit. This stops transmit 1658 * starting until the packet is loaded. Strike one for reliability, lose 1659 * one for latency - although on PCI this isn't a big loss. Older chips 1660 * have FIFO's smaller than a packet, so you can't do this. 1661 * Turn on BCR18:BurstRdEn and BCR18:BurstWrEn. 1662 */ 1663 1664 if (fset) { 1665 a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0860)); 1666 a->write_csr(ioaddr, 80, 1667 (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00); 1668 dxsuflo = 1; 1669 } 1670 1671 /* 1672 * The Am79C973/Am79C975 controllers come with 12K of SRAM 1673 * which we can use for the Tx/Rx buffers but most importantly, 1674 * the use of SRAM allow us to use the BCR18:NOUFLO bit to avoid 1675 * Tx fifo underflows. 1676 */ 1677 if (sram) { 1678 /* 1679 * The SRAM is being configured in two steps. First we 1680 * set the SRAM size in the BCR25:SRAM_SIZE bits. According 1681 * to the datasheet, each bit corresponds to a 512-byte 1682 * page so we can have at most 24 pages. The SRAM_SIZE 1683 * holds the value of the upper 8 bits of the 16-bit SRAM size. 1684 * The low 8-bits start at 0x00 and end at 0xff. So the 1685 * address range is from 0x0000 up to 0x17ff. Therefore, 1686 * the SRAM_SIZE is set to 0x17. The next step is to set 1687 * the BCR26:SRAM_BND midway through so the Tx and Rx 1688 * buffers can share the SRAM equally. 1689 */ 1690 a->write_bcr(ioaddr, 25, 0x17); 1691 a->write_bcr(ioaddr, 26, 0xc); 1692 /* And finally enable the NOUFLO bit */ 1693 a->write_bcr(ioaddr, 18, a->read_bcr(ioaddr, 18) | (1 << 11)); 1694 } 1695 1696 dev = alloc_etherdev(sizeof(*lp)); 1697 if (!dev) { 1698 ret = -ENOMEM; 1699 goto err_release_region; 1700 } 1701 1702 if (pdev) 1703 SET_NETDEV_DEV(dev, &pdev->dev); 1704 1705 if (pcnet32_debug & NETIF_MSG_PROBE) 1706 pr_info("%s at %#3lx,", chipname, ioaddr); 1707 1708 /* In most chips, after a chip reset, the ethernet address is read from the 1709 * station address PROM at the base address and programmed into the 1710 * "Physical Address Registers" CSR12-14. 1711 * As a precautionary measure, we read the PROM values and complain if 1712 * they disagree with the CSRs. If they miscompare, and the PROM addr 1713 * is valid, then the PROM addr is used. 1714 */ 1715 for (i = 0; i < 3; i++) { 1716 unsigned int val; 1717 val = a->read_csr(ioaddr, i + 12) & 0x0ffff; 1718 /* There may be endianness issues here. */ 1719 dev->dev_addr[2 * i] = val & 0x0ff; 1720 dev->dev_addr[2 * i + 1] = (val >> 8) & 0x0ff; 1721 } 1722 1723 /* read PROM address and compare with CSR address */ 1724 for (i = 0; i < ETH_ALEN; i++) 1725 promaddr[i] = inb(ioaddr + i); 1726 1727 if (!ether_addr_equal(promaddr, dev->dev_addr) || 1728 !is_valid_ether_addr(dev->dev_addr)) { 1729 if (is_valid_ether_addr(promaddr)) { 1730 if (pcnet32_debug & NETIF_MSG_PROBE) { 1731 pr_cont(" warning: CSR address invalid,\n"); 1732 pr_info(" using instead PROM address of"); 1733 } 1734 memcpy(dev->dev_addr, promaddr, ETH_ALEN); 1735 } 1736 } 1737 1738 /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */ 1739 if (!is_valid_ether_addr(dev->dev_addr)) 1740 eth_zero_addr(dev->dev_addr); 1741 1742 if (pcnet32_debug & NETIF_MSG_PROBE) { 1743 pr_cont(" %pM", dev->dev_addr); 1744 1745 /* Version 0x2623 and 0x2624 */ 1746 if (((chip_version + 1) & 0xfffe) == 0x2624) { 1747 i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */ 1748 pr_info(" tx_start_pt(0x%04x):", i); 1749 switch (i >> 10) { 1750 case 0: 1751 pr_cont(" 20 bytes,"); 1752 break; 1753 case 1: 1754 pr_cont(" 64 bytes,"); 1755 break; 1756 case 2: 1757 pr_cont(" 128 bytes,"); 1758 break; 1759 case 3: 1760 pr_cont("~220 bytes,"); 1761 break; 1762 } 1763 i = a->read_bcr(ioaddr, 18); /* Check Burst/Bus control */ 1764 pr_cont(" BCR18(%x):", i & 0xffff); 1765 if (i & (1 << 5)) 1766 pr_cont("BurstWrEn "); 1767 if (i & (1 << 6)) 1768 pr_cont("BurstRdEn "); 1769 if (i & (1 << 7)) 1770 pr_cont("DWordIO "); 1771 if (i & (1 << 11)) 1772 pr_cont("NoUFlow "); 1773 i = a->read_bcr(ioaddr, 25); 1774 pr_info(" SRAMSIZE=0x%04x,", i << 8); 1775 i = a->read_bcr(ioaddr, 26); 1776 pr_cont(" SRAM_BND=0x%04x,", i << 8); 1777 i = a->read_bcr(ioaddr, 27); 1778 if (i & (1 << 14)) 1779 pr_cont("LowLatRx"); 1780 } 1781 } 1782 1783 dev->base_addr = ioaddr; 1784 lp = netdev_priv(dev); 1785 /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */ 1786 lp->init_block = pci_alloc_consistent(pdev, sizeof(*lp->init_block), 1787 &lp->init_dma_addr); 1788 if (!lp->init_block) { 1789 if (pcnet32_debug & NETIF_MSG_PROBE) 1790 pr_err("Consistent memory allocation failed\n"); 1791 ret = -ENOMEM; 1792 goto err_free_netdev; 1793 } 1794 lp->pci_dev = pdev; 1795 1796 lp->dev = dev; 1797 1798 spin_lock_init(&lp->lock); 1799 1800 lp->name = chipname; 1801 lp->shared_irq = shared; 1802 lp->tx_ring_size = TX_RING_SIZE; /* default tx ring size */ 1803 lp->rx_ring_size = RX_RING_SIZE; /* default rx ring size */ 1804 lp->tx_mod_mask = lp->tx_ring_size - 1; 1805 lp->rx_mod_mask = lp->rx_ring_size - 1; 1806 lp->tx_len_bits = (PCNET32_LOG_TX_BUFFERS << 12); 1807 lp->rx_len_bits = (PCNET32_LOG_RX_BUFFERS << 4); 1808 lp->mii_if.full_duplex = fdx; 1809 lp->mii_if.phy_id_mask = 0x1f; 1810 lp->mii_if.reg_num_mask = 0x1f; 1811 lp->dxsuflo = dxsuflo; 1812 lp->mii = mii; 1813 lp->chip_version = chip_version; 1814 lp->msg_enable = pcnet32_debug; 1815 if ((cards_found >= MAX_UNITS) || 1816 (options[cards_found] >= sizeof(options_mapping))) 1817 lp->options = PCNET32_PORT_ASEL; 1818 else 1819 lp->options = options_mapping[options[cards_found]]; 1820 lp->mii_if.dev = dev; 1821 lp->mii_if.mdio_read = mdio_read; 1822 lp->mii_if.mdio_write = mdio_write; 1823 1824 /* napi.weight is used in both the napi and non-napi cases */ 1825 lp->napi.weight = lp->rx_ring_size / 2; 1826 1827 netif_napi_add(dev, &lp->napi, pcnet32_poll, lp->rx_ring_size / 2); 1828 1829 if (fdx && !(lp->options & PCNET32_PORT_ASEL) && 1830 ((cards_found >= MAX_UNITS) || full_duplex[cards_found])) 1831 lp->options |= PCNET32_PORT_FD; 1832 1833 lp->a = a; 1834 1835 /* prior to register_netdev, dev->name is not yet correct */ 1836 if (pcnet32_alloc_ring(dev, pci_name(lp->pci_dev))) { 1837 ret = -ENOMEM; 1838 goto err_free_ring; 1839 } 1840 /* detect special T1/E1 WAN card by checking for MAC address */ 1841 if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0 && 1842 dev->dev_addr[2] == 0x75) 1843 lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI; 1844 1845 lp->init_block->mode = cpu_to_le16(0x0003); /* Disable Rx and Tx. */ 1846 lp->init_block->tlen_rlen = 1847 cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits); 1848 for (i = 0; i < 6; i++) 1849 lp->init_block->phys_addr[i] = dev->dev_addr[i]; 1850 lp->init_block->filter[0] = 0x00000000; 1851 lp->init_block->filter[1] = 0x00000000; 1852 lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr); 1853 lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr); 1854 1855 /* switch pcnet32 to 32bit mode */ 1856 a->write_bcr(ioaddr, 20, 2); 1857 1858 a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff)); 1859 a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16)); 1860 1861 if (pdev) { /* use the IRQ provided by PCI */ 1862 dev->irq = pdev->irq; 1863 if (pcnet32_debug & NETIF_MSG_PROBE) 1864 pr_cont(" assigned IRQ %d\n", dev->irq); 1865 } else { 1866 unsigned long irq_mask = probe_irq_on(); 1867 1868 /* 1869 * To auto-IRQ we enable the initialization-done and DMA error 1870 * interrupts. For ISA boards we get a DMA error, but VLB and PCI 1871 * boards will work. 1872 */ 1873 /* Trigger an initialization just for the interrupt. */ 1874 a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_INIT); 1875 mdelay(1); 1876 1877 dev->irq = probe_irq_off(irq_mask); 1878 if (!dev->irq) { 1879 if (pcnet32_debug & NETIF_MSG_PROBE) 1880 pr_cont(", failed to detect IRQ line\n"); 1881 ret = -ENODEV; 1882 goto err_free_ring; 1883 } 1884 if (pcnet32_debug & NETIF_MSG_PROBE) 1885 pr_cont(", probed IRQ %d\n", dev->irq); 1886 } 1887 1888 /* Set the mii phy_id so that we can query the link state */ 1889 if (lp->mii) { 1890 /* lp->phycount and lp->phymask are set to 0 by memset above */ 1891 1892 lp->mii_if.phy_id = ((lp->a->read_bcr(ioaddr, 33)) >> 5) & 0x1f; 1893 /* scan for PHYs */ 1894 for (i = 0; i < PCNET32_MAX_PHYS; i++) { 1895 unsigned short id1, id2; 1896 1897 id1 = mdio_read(dev, i, MII_PHYSID1); 1898 if (id1 == 0xffff) 1899 continue; 1900 id2 = mdio_read(dev, i, MII_PHYSID2); 1901 if (id2 == 0xffff) 1902 continue; 1903 if (i == 31 && ((chip_version + 1) & 0xfffe) == 0x2624) 1904 continue; /* 79C971 & 79C972 have phantom phy at id 31 */ 1905 lp->phycount++; 1906 lp->phymask |= (1 << i); 1907 lp->mii_if.phy_id = i; 1908 if (pcnet32_debug & NETIF_MSG_PROBE) 1909 pr_info("Found PHY %04x:%04x at address %d\n", 1910 id1, id2, i); 1911 } 1912 lp->a->write_bcr(ioaddr, 33, (lp->mii_if.phy_id) << 5); 1913 if (lp->phycount > 1) 1914 lp->options |= PCNET32_PORT_MII; 1915 } 1916 1917 init_timer(&lp->watchdog_timer); 1918 lp->watchdog_timer.data = (unsigned long)dev; 1919 lp->watchdog_timer.function = (void *)&pcnet32_watchdog; 1920 1921 /* The PCNET32-specific entries in the device structure. */ 1922 dev->netdev_ops = &pcnet32_netdev_ops; 1923 dev->ethtool_ops = &pcnet32_ethtool_ops; 1924 dev->watchdog_timeo = (5 * HZ); 1925 1926 /* Fill in the generic fields of the device structure. */ 1927 if (register_netdev(dev)) 1928 goto err_free_ring; 1929 1930 if (pdev) { 1931 pci_set_drvdata(pdev, dev); 1932 } else { 1933 lp->next = pcnet32_dev; 1934 pcnet32_dev = dev; 1935 } 1936 1937 if (pcnet32_debug & NETIF_MSG_PROBE) 1938 pr_info("%s: registered as %s\n", dev->name, lp->name); 1939 cards_found++; 1940 1941 /* enable LED writes */ 1942 a->write_bcr(ioaddr, 2, a->read_bcr(ioaddr, 2) | 0x1000); 1943 1944 return 0; 1945 1946 err_free_ring: 1947 pcnet32_free_ring(dev); 1948 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block), 1949 lp->init_block, lp->init_dma_addr); 1950 err_free_netdev: 1951 free_netdev(dev); 1952 err_release_region: 1953 release_region(ioaddr, PCNET32_TOTAL_SIZE); 1954 return ret; 1955 } 1956 1957 /* if any allocation fails, caller must also call pcnet32_free_ring */ 1958 static int pcnet32_alloc_ring(struct net_device *dev, const char *name) 1959 { 1960 struct pcnet32_private *lp = netdev_priv(dev); 1961 1962 lp->tx_ring = pci_alloc_consistent(lp->pci_dev, 1963 sizeof(struct pcnet32_tx_head) * 1964 lp->tx_ring_size, 1965 &lp->tx_ring_dma_addr); 1966 if (lp->tx_ring == NULL) { 1967 netif_err(lp, drv, dev, "Consistent memory allocation failed\n"); 1968 return -ENOMEM; 1969 } 1970 1971 lp->rx_ring = pci_alloc_consistent(lp->pci_dev, 1972 sizeof(struct pcnet32_rx_head) * 1973 lp->rx_ring_size, 1974 &lp->rx_ring_dma_addr); 1975 if (lp->rx_ring == NULL) { 1976 netif_err(lp, drv, dev, "Consistent memory allocation failed\n"); 1977 return -ENOMEM; 1978 } 1979 1980 lp->tx_dma_addr = kcalloc(lp->tx_ring_size, sizeof(dma_addr_t), 1981 GFP_ATOMIC); 1982 if (!lp->tx_dma_addr) 1983 return -ENOMEM; 1984 1985 lp->rx_dma_addr = kcalloc(lp->rx_ring_size, sizeof(dma_addr_t), 1986 GFP_ATOMIC); 1987 if (!lp->rx_dma_addr) 1988 return -ENOMEM; 1989 1990 lp->tx_skbuff = kcalloc(lp->tx_ring_size, sizeof(struct sk_buff *), 1991 GFP_ATOMIC); 1992 if (!lp->tx_skbuff) 1993 return -ENOMEM; 1994 1995 lp->rx_skbuff = kcalloc(lp->rx_ring_size, sizeof(struct sk_buff *), 1996 GFP_ATOMIC); 1997 if (!lp->rx_skbuff) 1998 return -ENOMEM; 1999 2000 return 0; 2001 } 2002 2003 static void pcnet32_free_ring(struct net_device *dev) 2004 { 2005 struct pcnet32_private *lp = netdev_priv(dev); 2006 2007 kfree(lp->tx_skbuff); 2008 lp->tx_skbuff = NULL; 2009 2010 kfree(lp->rx_skbuff); 2011 lp->rx_skbuff = NULL; 2012 2013 kfree(lp->tx_dma_addr); 2014 lp->tx_dma_addr = NULL; 2015 2016 kfree(lp->rx_dma_addr); 2017 lp->rx_dma_addr = NULL; 2018 2019 if (lp->tx_ring) { 2020 pci_free_consistent(lp->pci_dev, 2021 sizeof(struct pcnet32_tx_head) * 2022 lp->tx_ring_size, lp->tx_ring, 2023 lp->tx_ring_dma_addr); 2024 lp->tx_ring = NULL; 2025 } 2026 2027 if (lp->rx_ring) { 2028 pci_free_consistent(lp->pci_dev, 2029 sizeof(struct pcnet32_rx_head) * 2030 lp->rx_ring_size, lp->rx_ring, 2031 lp->rx_ring_dma_addr); 2032 lp->rx_ring = NULL; 2033 } 2034 } 2035 2036 static int pcnet32_open(struct net_device *dev) 2037 { 2038 struct pcnet32_private *lp = netdev_priv(dev); 2039 struct pci_dev *pdev = lp->pci_dev; 2040 unsigned long ioaddr = dev->base_addr; 2041 u16 val; 2042 int i; 2043 int rc; 2044 unsigned long flags; 2045 2046 if (request_irq(dev->irq, pcnet32_interrupt, 2047 lp->shared_irq ? IRQF_SHARED : 0, dev->name, 2048 (void *)dev)) { 2049 return -EAGAIN; 2050 } 2051 2052 spin_lock_irqsave(&lp->lock, flags); 2053 /* Check for a valid station address */ 2054 if (!is_valid_ether_addr(dev->dev_addr)) { 2055 rc = -EINVAL; 2056 goto err_free_irq; 2057 } 2058 2059 /* Reset the PCNET32 */ 2060 lp->a->reset(ioaddr); 2061 2062 /* switch pcnet32 to 32bit mode */ 2063 lp->a->write_bcr(ioaddr, 20, 2); 2064 2065 netif_printk(lp, ifup, KERN_DEBUG, dev, 2066 "%s() irq %d tx/rx rings %#x/%#x init %#x\n", 2067 __func__, dev->irq, (u32) (lp->tx_ring_dma_addr), 2068 (u32) (lp->rx_ring_dma_addr), 2069 (u32) (lp->init_dma_addr)); 2070 2071 /* set/reset autoselect bit */ 2072 val = lp->a->read_bcr(ioaddr, 2) & ~2; 2073 if (lp->options & PCNET32_PORT_ASEL) 2074 val |= 2; 2075 lp->a->write_bcr(ioaddr, 2, val); 2076 2077 /* handle full duplex setting */ 2078 if (lp->mii_if.full_duplex) { 2079 val = lp->a->read_bcr(ioaddr, 9) & ~3; 2080 if (lp->options & PCNET32_PORT_FD) { 2081 val |= 1; 2082 if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI)) 2083 val |= 2; 2084 } else if (lp->options & PCNET32_PORT_ASEL) { 2085 /* workaround of xSeries250, turn on for 79C975 only */ 2086 if (lp->chip_version == 0x2627) 2087 val |= 3; 2088 } 2089 lp->a->write_bcr(ioaddr, 9, val); 2090 } 2091 2092 /* set/reset GPSI bit in test register */ 2093 val = lp->a->read_csr(ioaddr, 124) & ~0x10; 2094 if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI) 2095 val |= 0x10; 2096 lp->a->write_csr(ioaddr, 124, val); 2097 2098 /* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */ 2099 if (pdev && pdev->subsystem_vendor == PCI_VENDOR_ID_AT && 2100 (pdev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX || 2101 pdev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) { 2102 if (lp->options & PCNET32_PORT_ASEL) { 2103 lp->options = PCNET32_PORT_FD | PCNET32_PORT_100; 2104 netif_printk(lp, link, KERN_DEBUG, dev, 2105 "Setting 100Mb-Full Duplex\n"); 2106 } 2107 } 2108 if (lp->phycount < 2) { 2109 /* 2110 * 24 Jun 2004 according AMD, in order to change the PHY, 2111 * DANAS (or DISPM for 79C976) must be set; then select the speed, 2112 * duplex, and/or enable auto negotiation, and clear DANAS 2113 */ 2114 if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) { 2115 lp->a->write_bcr(ioaddr, 32, 2116 lp->a->read_bcr(ioaddr, 32) | 0x0080); 2117 /* disable Auto Negotiation, set 10Mpbs, HD */ 2118 val = lp->a->read_bcr(ioaddr, 32) & ~0xb8; 2119 if (lp->options & PCNET32_PORT_FD) 2120 val |= 0x10; 2121 if (lp->options & PCNET32_PORT_100) 2122 val |= 0x08; 2123 lp->a->write_bcr(ioaddr, 32, val); 2124 } else { 2125 if (lp->options & PCNET32_PORT_ASEL) { 2126 lp->a->write_bcr(ioaddr, 32, 2127 lp->a->read_bcr(ioaddr, 2128 32) | 0x0080); 2129 /* enable auto negotiate, setup, disable fd */ 2130 val = lp->a->read_bcr(ioaddr, 32) & ~0x98; 2131 val |= 0x20; 2132 lp->a->write_bcr(ioaddr, 32, val); 2133 } 2134 } 2135 } else { 2136 int first_phy = -1; 2137 u16 bmcr; 2138 u32 bcr9; 2139 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET }; 2140 2141 /* 2142 * There is really no good other way to handle multiple PHYs 2143 * other than turning off all automatics 2144 */ 2145 val = lp->a->read_bcr(ioaddr, 2); 2146 lp->a->write_bcr(ioaddr, 2, val & ~2); 2147 val = lp->a->read_bcr(ioaddr, 32); 2148 lp->a->write_bcr(ioaddr, 32, val & ~(1 << 7)); /* stop MII manager */ 2149 2150 if (!(lp->options & PCNET32_PORT_ASEL)) { 2151 /* setup ecmd */ 2152 ecmd.port = PORT_MII; 2153 ecmd.transceiver = XCVR_INTERNAL; 2154 ecmd.autoneg = AUTONEG_DISABLE; 2155 ethtool_cmd_speed_set(&ecmd, 2156 (lp->options & PCNET32_PORT_100) ? 2157 SPEED_100 : SPEED_10); 2158 bcr9 = lp->a->read_bcr(ioaddr, 9); 2159 2160 if (lp->options & PCNET32_PORT_FD) { 2161 ecmd.duplex = DUPLEX_FULL; 2162 bcr9 |= (1 << 0); 2163 } else { 2164 ecmd.duplex = DUPLEX_HALF; 2165 bcr9 |= ~(1 << 0); 2166 } 2167 lp->a->write_bcr(ioaddr, 9, bcr9); 2168 } 2169 2170 for (i = 0; i < PCNET32_MAX_PHYS; i++) { 2171 if (lp->phymask & (1 << i)) { 2172 /* isolate all but the first PHY */ 2173 bmcr = mdio_read(dev, i, MII_BMCR); 2174 if (first_phy == -1) { 2175 first_phy = i; 2176 mdio_write(dev, i, MII_BMCR, 2177 bmcr & ~BMCR_ISOLATE); 2178 } else { 2179 mdio_write(dev, i, MII_BMCR, 2180 bmcr | BMCR_ISOLATE); 2181 } 2182 /* use mii_ethtool_sset to setup PHY */ 2183 lp->mii_if.phy_id = i; 2184 ecmd.phy_address = i; 2185 if (lp->options & PCNET32_PORT_ASEL) { 2186 mii_ethtool_gset(&lp->mii_if, &ecmd); 2187 ecmd.autoneg = AUTONEG_ENABLE; 2188 } 2189 mii_ethtool_sset(&lp->mii_if, &ecmd); 2190 } 2191 } 2192 lp->mii_if.phy_id = first_phy; 2193 netif_info(lp, link, dev, "Using PHY number %d\n", first_phy); 2194 } 2195 2196 #ifdef DO_DXSUFLO 2197 if (lp->dxsuflo) { /* Disable transmit stop on underflow */ 2198 val = lp->a->read_csr(ioaddr, CSR3); 2199 val |= 0x40; 2200 lp->a->write_csr(ioaddr, CSR3, val); 2201 } 2202 #endif 2203 2204 lp->init_block->mode = 2205 cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7); 2206 pcnet32_load_multicast(dev); 2207 2208 if (pcnet32_init_ring(dev)) { 2209 rc = -ENOMEM; 2210 goto err_free_ring; 2211 } 2212 2213 napi_enable(&lp->napi); 2214 2215 /* Re-initialize the PCNET32, and start it when done. */ 2216 lp->a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff)); 2217 lp->a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16)); 2218 2219 lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */ 2220 lp->a->write_csr(ioaddr, CSR0, CSR0_INIT); 2221 2222 netif_start_queue(dev); 2223 2224 if (lp->chip_version >= PCNET32_79C970A) { 2225 /* Print the link status and start the watchdog */ 2226 pcnet32_check_media(dev, 1); 2227 mod_timer(&lp->watchdog_timer, PCNET32_WATCHDOG_TIMEOUT); 2228 } 2229 2230 i = 0; 2231 while (i++ < 100) 2232 if (lp->a->read_csr(ioaddr, CSR0) & CSR0_IDON) 2233 break; 2234 /* 2235 * We used to clear the InitDone bit, 0x0100, here but Mark Stockton 2236 * reports that doing so triggers a bug in the '974. 2237 */ 2238 lp->a->write_csr(ioaddr, CSR0, CSR0_NORMAL); 2239 2240 netif_printk(lp, ifup, KERN_DEBUG, dev, 2241 "pcnet32 open after %d ticks, init block %#x csr0 %4.4x\n", 2242 i, 2243 (u32) (lp->init_dma_addr), 2244 lp->a->read_csr(ioaddr, CSR0)); 2245 2246 spin_unlock_irqrestore(&lp->lock, flags); 2247 2248 return 0; /* Always succeed */ 2249 2250 err_free_ring: 2251 /* free any allocated skbuffs */ 2252 pcnet32_purge_rx_ring(dev); 2253 2254 /* 2255 * Switch back to 16bit mode to avoid problems with dumb 2256 * DOS packet driver after a warm reboot 2257 */ 2258 lp->a->write_bcr(ioaddr, 20, 4); 2259 2260 err_free_irq: 2261 spin_unlock_irqrestore(&lp->lock, flags); 2262 free_irq(dev->irq, dev); 2263 return rc; 2264 } 2265 2266 /* 2267 * The LANCE has been halted for one reason or another (busmaster memory 2268 * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure, 2269 * etc.). Modern LANCE variants always reload their ring-buffer 2270 * configuration when restarted, so we must reinitialize our ring 2271 * context before restarting. As part of this reinitialization, 2272 * find all packets still on the Tx ring and pretend that they had been 2273 * sent (in effect, drop the packets on the floor) - the higher-level 2274 * protocols will time out and retransmit. It'd be better to shuffle 2275 * these skbs to a temp list and then actually re-Tx them after 2276 * restarting the chip, but I'm too lazy to do so right now. dplatt@3do.com 2277 */ 2278 2279 static void pcnet32_purge_tx_ring(struct net_device *dev) 2280 { 2281 struct pcnet32_private *lp = netdev_priv(dev); 2282 int i; 2283 2284 for (i = 0; i < lp->tx_ring_size; i++) { 2285 lp->tx_ring[i].status = 0; /* CPU owns buffer */ 2286 wmb(); /* Make sure adapter sees owner change */ 2287 if (lp->tx_skbuff[i]) { 2288 if (!pci_dma_mapping_error(lp->pci_dev, 2289 lp->tx_dma_addr[i])) 2290 pci_unmap_single(lp->pci_dev, 2291 lp->tx_dma_addr[i], 2292 lp->tx_skbuff[i]->len, 2293 PCI_DMA_TODEVICE); 2294 dev_kfree_skb_any(lp->tx_skbuff[i]); 2295 } 2296 lp->tx_skbuff[i] = NULL; 2297 lp->tx_dma_addr[i] = 0; 2298 } 2299 } 2300 2301 /* Initialize the PCNET32 Rx and Tx rings. */ 2302 static int pcnet32_init_ring(struct net_device *dev) 2303 { 2304 struct pcnet32_private *lp = netdev_priv(dev); 2305 int i; 2306 2307 lp->tx_full = 0; 2308 lp->cur_rx = lp->cur_tx = 0; 2309 lp->dirty_rx = lp->dirty_tx = 0; 2310 2311 for (i = 0; i < lp->rx_ring_size; i++) { 2312 struct sk_buff *rx_skbuff = lp->rx_skbuff[i]; 2313 if (rx_skbuff == NULL) { 2314 lp->rx_skbuff[i] = netdev_alloc_skb(dev, PKT_BUF_SKB); 2315 rx_skbuff = lp->rx_skbuff[i]; 2316 if (!rx_skbuff) { 2317 /* there is not much we can do at this point */ 2318 netif_err(lp, drv, dev, "%s netdev_alloc_skb failed\n", 2319 __func__); 2320 return -1; 2321 } 2322 skb_reserve(rx_skbuff, NET_IP_ALIGN); 2323 } 2324 2325 rmb(); 2326 if (lp->rx_dma_addr[i] == 0) { 2327 lp->rx_dma_addr[i] = 2328 pci_map_single(lp->pci_dev, rx_skbuff->data, 2329 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE); 2330 if (pci_dma_mapping_error(lp->pci_dev, 2331 lp->rx_dma_addr[i])) { 2332 /* there is not much we can do at this point */ 2333 netif_err(lp, drv, dev, 2334 "%s pci dma mapping error\n", 2335 __func__); 2336 return -1; 2337 } 2338 } 2339 lp->rx_ring[i].base = cpu_to_le32(lp->rx_dma_addr[i]); 2340 lp->rx_ring[i].buf_length = cpu_to_le16(NEG_BUF_SIZE); 2341 wmb(); /* Make sure owner changes after all others are visible */ 2342 lp->rx_ring[i].status = cpu_to_le16(0x8000); 2343 } 2344 /* The Tx buffer address is filled in as needed, but we do need to clear 2345 * the upper ownership bit. */ 2346 for (i = 0; i < lp->tx_ring_size; i++) { 2347 lp->tx_ring[i].status = 0; /* CPU owns buffer */ 2348 wmb(); /* Make sure adapter sees owner change */ 2349 lp->tx_ring[i].base = 0; 2350 lp->tx_dma_addr[i] = 0; 2351 } 2352 2353 lp->init_block->tlen_rlen = 2354 cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits); 2355 for (i = 0; i < 6; i++) 2356 lp->init_block->phys_addr[i] = dev->dev_addr[i]; 2357 lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr); 2358 lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr); 2359 wmb(); /* Make sure all changes are visible */ 2360 return 0; 2361 } 2362 2363 /* the pcnet32 has been issued a stop or reset. Wait for the stop bit 2364 * then flush the pending transmit operations, re-initialize the ring, 2365 * and tell the chip to initialize. 2366 */ 2367 static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits) 2368 { 2369 struct pcnet32_private *lp = netdev_priv(dev); 2370 unsigned long ioaddr = dev->base_addr; 2371 int i; 2372 2373 /* wait for stop */ 2374 for (i = 0; i < 100; i++) 2375 if (lp->a->read_csr(ioaddr, CSR0) & CSR0_STOP) 2376 break; 2377 2378 if (i >= 100) 2379 netif_err(lp, drv, dev, "%s timed out waiting for stop\n", 2380 __func__); 2381 2382 pcnet32_purge_tx_ring(dev); 2383 if (pcnet32_init_ring(dev)) 2384 return; 2385 2386 /* ReInit Ring */ 2387 lp->a->write_csr(ioaddr, CSR0, CSR0_INIT); 2388 i = 0; 2389 while (i++ < 1000) 2390 if (lp->a->read_csr(ioaddr, CSR0) & CSR0_IDON) 2391 break; 2392 2393 lp->a->write_csr(ioaddr, CSR0, csr0_bits); 2394 } 2395 2396 static void pcnet32_tx_timeout(struct net_device *dev) 2397 { 2398 struct pcnet32_private *lp = netdev_priv(dev); 2399 unsigned long ioaddr = dev->base_addr, flags; 2400 2401 spin_lock_irqsave(&lp->lock, flags); 2402 /* Transmitter timeout, serious problems. */ 2403 if (pcnet32_debug & NETIF_MSG_DRV) 2404 pr_err("%s: transmit timed out, status %4.4x, resetting\n", 2405 dev->name, lp->a->read_csr(ioaddr, CSR0)); 2406 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); 2407 dev->stats.tx_errors++; 2408 if (netif_msg_tx_err(lp)) { 2409 int i; 2410 printk(KERN_DEBUG 2411 " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.", 2412 lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "", 2413 lp->cur_rx); 2414 for (i = 0; i < lp->rx_ring_size; i++) 2415 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ", 2416 le32_to_cpu(lp->rx_ring[i].base), 2417 (-le16_to_cpu(lp->rx_ring[i].buf_length)) & 2418 0xffff, le32_to_cpu(lp->rx_ring[i].msg_length), 2419 le16_to_cpu(lp->rx_ring[i].status)); 2420 for (i = 0; i < lp->tx_ring_size; i++) 2421 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ", 2422 le32_to_cpu(lp->tx_ring[i].base), 2423 (-le16_to_cpu(lp->tx_ring[i].length)) & 0xffff, 2424 le32_to_cpu(lp->tx_ring[i].misc), 2425 le16_to_cpu(lp->tx_ring[i].status)); 2426 printk("\n"); 2427 } 2428 pcnet32_restart(dev, CSR0_NORMAL); 2429 2430 netif_trans_update(dev); /* prevent tx timeout */ 2431 netif_wake_queue(dev); 2432 2433 spin_unlock_irqrestore(&lp->lock, flags); 2434 } 2435 2436 static netdev_tx_t pcnet32_start_xmit(struct sk_buff *skb, 2437 struct net_device *dev) 2438 { 2439 struct pcnet32_private *lp = netdev_priv(dev); 2440 unsigned long ioaddr = dev->base_addr; 2441 u16 status; 2442 int entry; 2443 unsigned long flags; 2444 2445 spin_lock_irqsave(&lp->lock, flags); 2446 2447 netif_printk(lp, tx_queued, KERN_DEBUG, dev, 2448 "%s() called, csr0 %4.4x\n", 2449 __func__, lp->a->read_csr(ioaddr, CSR0)); 2450 2451 /* Default status -- will not enable Successful-TxDone 2452 * interrupt when that option is available to us. 2453 */ 2454 status = 0x8300; 2455 2456 /* Fill in a Tx ring entry */ 2457 2458 /* Mask to ring buffer boundary. */ 2459 entry = lp->cur_tx & lp->tx_mod_mask; 2460 2461 /* Caution: the write order is important here, set the status 2462 * with the "ownership" bits last. */ 2463 2464 lp->tx_ring[entry].length = cpu_to_le16(-skb->len); 2465 2466 lp->tx_ring[entry].misc = 0x00000000; 2467 2468 lp->tx_dma_addr[entry] = 2469 pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE); 2470 if (pci_dma_mapping_error(lp->pci_dev, lp->tx_dma_addr[entry])) { 2471 dev_kfree_skb_any(skb); 2472 dev->stats.tx_dropped++; 2473 goto drop_packet; 2474 } 2475 lp->tx_skbuff[entry] = skb; 2476 lp->tx_ring[entry].base = cpu_to_le32(lp->tx_dma_addr[entry]); 2477 wmb(); /* Make sure owner changes after all others are visible */ 2478 lp->tx_ring[entry].status = cpu_to_le16(status); 2479 2480 lp->cur_tx++; 2481 dev->stats.tx_bytes += skb->len; 2482 2483 /* Trigger an immediate send poll. */ 2484 lp->a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_TXPOLL); 2485 2486 if (lp->tx_ring[(entry + 1) & lp->tx_mod_mask].base != 0) { 2487 lp->tx_full = 1; 2488 netif_stop_queue(dev); 2489 } 2490 drop_packet: 2491 spin_unlock_irqrestore(&lp->lock, flags); 2492 return NETDEV_TX_OK; 2493 } 2494 2495 /* The PCNET32 interrupt handler. */ 2496 static irqreturn_t 2497 pcnet32_interrupt(int irq, void *dev_id) 2498 { 2499 struct net_device *dev = dev_id; 2500 struct pcnet32_private *lp; 2501 unsigned long ioaddr; 2502 u16 csr0; 2503 int boguscnt = max_interrupt_work; 2504 2505 ioaddr = dev->base_addr; 2506 lp = netdev_priv(dev); 2507 2508 spin_lock(&lp->lock); 2509 2510 csr0 = lp->a->read_csr(ioaddr, CSR0); 2511 while ((csr0 & 0x8f00) && --boguscnt >= 0) { 2512 if (csr0 == 0xffff) 2513 break; /* PCMCIA remove happened */ 2514 /* Acknowledge all of the current interrupt sources ASAP. */ 2515 lp->a->write_csr(ioaddr, CSR0, csr0 & ~0x004f); 2516 2517 netif_printk(lp, intr, KERN_DEBUG, dev, 2518 "interrupt csr0=%#2.2x new csr=%#2.2x\n", 2519 csr0, lp->a->read_csr(ioaddr, CSR0)); 2520 2521 /* Log misc errors. */ 2522 if (csr0 & 0x4000) 2523 dev->stats.tx_errors++; /* Tx babble. */ 2524 if (csr0 & 0x1000) { 2525 /* 2526 * This happens when our receive ring is full. This 2527 * shouldn't be a problem as we will see normal rx 2528 * interrupts for the frames in the receive ring. But 2529 * there are some PCI chipsets (I can reproduce this 2530 * on SP3G with Intel saturn chipset) which have 2531 * sometimes problems and will fill up the receive 2532 * ring with error descriptors. In this situation we 2533 * don't get a rx interrupt, but a missed frame 2534 * interrupt sooner or later. 2535 */ 2536 dev->stats.rx_errors++; /* Missed a Rx frame. */ 2537 } 2538 if (csr0 & 0x0800) { 2539 netif_err(lp, drv, dev, "Bus master arbitration failure, status %4.4x\n", 2540 csr0); 2541 /* unlike for the lance, there is no restart needed */ 2542 } 2543 if (napi_schedule_prep(&lp->napi)) { 2544 u16 val; 2545 /* set interrupt masks */ 2546 val = lp->a->read_csr(ioaddr, CSR3); 2547 val |= 0x5f00; 2548 lp->a->write_csr(ioaddr, CSR3, val); 2549 2550 __napi_schedule(&lp->napi); 2551 break; 2552 } 2553 csr0 = lp->a->read_csr(ioaddr, CSR0); 2554 } 2555 2556 netif_printk(lp, intr, KERN_DEBUG, dev, 2557 "exiting interrupt, csr0=%#4.4x\n", 2558 lp->a->read_csr(ioaddr, CSR0)); 2559 2560 spin_unlock(&lp->lock); 2561 2562 return IRQ_HANDLED; 2563 } 2564 2565 static int pcnet32_close(struct net_device *dev) 2566 { 2567 unsigned long ioaddr = dev->base_addr; 2568 struct pcnet32_private *lp = netdev_priv(dev); 2569 unsigned long flags; 2570 2571 del_timer_sync(&lp->watchdog_timer); 2572 2573 netif_stop_queue(dev); 2574 napi_disable(&lp->napi); 2575 2576 spin_lock_irqsave(&lp->lock, flags); 2577 2578 dev->stats.rx_missed_errors = lp->a->read_csr(ioaddr, 112); 2579 2580 netif_printk(lp, ifdown, KERN_DEBUG, dev, 2581 "Shutting down ethercard, status was %2.2x\n", 2582 lp->a->read_csr(ioaddr, CSR0)); 2583 2584 /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */ 2585 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); 2586 2587 /* 2588 * Switch back to 16bit mode to avoid problems with dumb 2589 * DOS packet driver after a warm reboot 2590 */ 2591 lp->a->write_bcr(ioaddr, 20, 4); 2592 2593 spin_unlock_irqrestore(&lp->lock, flags); 2594 2595 free_irq(dev->irq, dev); 2596 2597 spin_lock_irqsave(&lp->lock, flags); 2598 2599 pcnet32_purge_rx_ring(dev); 2600 pcnet32_purge_tx_ring(dev); 2601 2602 spin_unlock_irqrestore(&lp->lock, flags); 2603 2604 return 0; 2605 } 2606 2607 static struct net_device_stats *pcnet32_get_stats(struct net_device *dev) 2608 { 2609 struct pcnet32_private *lp = netdev_priv(dev); 2610 unsigned long ioaddr = dev->base_addr; 2611 unsigned long flags; 2612 2613 spin_lock_irqsave(&lp->lock, flags); 2614 dev->stats.rx_missed_errors = lp->a->read_csr(ioaddr, 112); 2615 spin_unlock_irqrestore(&lp->lock, flags); 2616 2617 return &dev->stats; 2618 } 2619 2620 /* taken from the sunlance driver, which it took from the depca driver */ 2621 static void pcnet32_load_multicast(struct net_device *dev) 2622 { 2623 struct pcnet32_private *lp = netdev_priv(dev); 2624 volatile struct pcnet32_init_block *ib = lp->init_block; 2625 volatile __le16 *mcast_table = (__le16 *)ib->filter; 2626 struct netdev_hw_addr *ha; 2627 unsigned long ioaddr = dev->base_addr; 2628 int i; 2629 u32 crc; 2630 2631 /* set all multicast bits */ 2632 if (dev->flags & IFF_ALLMULTI) { 2633 ib->filter[0] = cpu_to_le32(~0U); 2634 ib->filter[1] = cpu_to_le32(~0U); 2635 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER, 0xffff); 2636 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+1, 0xffff); 2637 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+2, 0xffff); 2638 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+3, 0xffff); 2639 return; 2640 } 2641 /* clear the multicast filter */ 2642 ib->filter[0] = 0; 2643 ib->filter[1] = 0; 2644 2645 /* Add addresses */ 2646 netdev_for_each_mc_addr(ha, dev) { 2647 crc = ether_crc_le(6, ha->addr); 2648 crc = crc >> 26; 2649 mcast_table[crc >> 4] |= cpu_to_le16(1 << (crc & 0xf)); 2650 } 2651 for (i = 0; i < 4; i++) 2652 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER + i, 2653 le16_to_cpu(mcast_table[i])); 2654 } 2655 2656 /* 2657 * Set or clear the multicast filter for this adaptor. 2658 */ 2659 static void pcnet32_set_multicast_list(struct net_device *dev) 2660 { 2661 unsigned long ioaddr = dev->base_addr, flags; 2662 struct pcnet32_private *lp = netdev_priv(dev); 2663 int csr15, suspended; 2664 2665 spin_lock_irqsave(&lp->lock, flags); 2666 suspended = pcnet32_suspend(dev, &flags, 0); 2667 csr15 = lp->a->read_csr(ioaddr, CSR15); 2668 if (dev->flags & IFF_PROMISC) { 2669 /* Log any net taps. */ 2670 netif_info(lp, hw, dev, "Promiscuous mode enabled\n"); 2671 lp->init_block->mode = 2672 cpu_to_le16(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) << 2673 7); 2674 lp->a->write_csr(ioaddr, CSR15, csr15 | 0x8000); 2675 } else { 2676 lp->init_block->mode = 2677 cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7); 2678 lp->a->write_csr(ioaddr, CSR15, csr15 & 0x7fff); 2679 pcnet32_load_multicast(dev); 2680 } 2681 2682 if (suspended) { 2683 int csr5; 2684 /* clear SUSPEND (SPND) - CSR5 bit 0 */ 2685 csr5 = lp->a->read_csr(ioaddr, CSR5); 2686 lp->a->write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND)); 2687 } else { 2688 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); 2689 pcnet32_restart(dev, CSR0_NORMAL); 2690 netif_wake_queue(dev); 2691 } 2692 2693 spin_unlock_irqrestore(&lp->lock, flags); 2694 } 2695 2696 /* This routine assumes that the lp->lock is held */ 2697 static int mdio_read(struct net_device *dev, int phy_id, int reg_num) 2698 { 2699 struct pcnet32_private *lp = netdev_priv(dev); 2700 unsigned long ioaddr = dev->base_addr; 2701 u16 val_out; 2702 2703 if (!lp->mii) 2704 return 0; 2705 2706 lp->a->write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f)); 2707 val_out = lp->a->read_bcr(ioaddr, 34); 2708 2709 return val_out; 2710 } 2711 2712 /* This routine assumes that the lp->lock is held */ 2713 static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val) 2714 { 2715 struct pcnet32_private *lp = netdev_priv(dev); 2716 unsigned long ioaddr = dev->base_addr; 2717 2718 if (!lp->mii) 2719 return; 2720 2721 lp->a->write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f)); 2722 lp->a->write_bcr(ioaddr, 34, val); 2723 } 2724 2725 static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 2726 { 2727 struct pcnet32_private *lp = netdev_priv(dev); 2728 int rc; 2729 unsigned long flags; 2730 2731 /* SIOC[GS]MIIxxx ioctls */ 2732 if (lp->mii) { 2733 spin_lock_irqsave(&lp->lock, flags); 2734 rc = generic_mii_ioctl(&lp->mii_if, if_mii(rq), cmd, NULL); 2735 spin_unlock_irqrestore(&lp->lock, flags); 2736 } else { 2737 rc = -EOPNOTSUPP; 2738 } 2739 2740 return rc; 2741 } 2742 2743 static int pcnet32_check_otherphy(struct net_device *dev) 2744 { 2745 struct pcnet32_private *lp = netdev_priv(dev); 2746 struct mii_if_info mii = lp->mii_if; 2747 u16 bmcr; 2748 int i; 2749 2750 for (i = 0; i < PCNET32_MAX_PHYS; i++) { 2751 if (i == lp->mii_if.phy_id) 2752 continue; /* skip active phy */ 2753 if (lp->phymask & (1 << i)) { 2754 mii.phy_id = i; 2755 if (mii_link_ok(&mii)) { 2756 /* found PHY with active link */ 2757 netif_info(lp, link, dev, "Using PHY number %d\n", 2758 i); 2759 2760 /* isolate inactive phy */ 2761 bmcr = 2762 mdio_read(dev, lp->mii_if.phy_id, MII_BMCR); 2763 mdio_write(dev, lp->mii_if.phy_id, MII_BMCR, 2764 bmcr | BMCR_ISOLATE); 2765 2766 /* de-isolate new phy */ 2767 bmcr = mdio_read(dev, i, MII_BMCR); 2768 mdio_write(dev, i, MII_BMCR, 2769 bmcr & ~BMCR_ISOLATE); 2770 2771 /* set new phy address */ 2772 lp->mii_if.phy_id = i; 2773 return 1; 2774 } 2775 } 2776 } 2777 return 0; 2778 } 2779 2780 /* 2781 * Show the status of the media. Similar to mii_check_media however it 2782 * correctly shows the link speed for all (tested) pcnet32 variants. 2783 * Devices with no mii just report link state without speed. 2784 * 2785 * Caller is assumed to hold and release the lp->lock. 2786 */ 2787 2788 static void pcnet32_check_media(struct net_device *dev, int verbose) 2789 { 2790 struct pcnet32_private *lp = netdev_priv(dev); 2791 int curr_link; 2792 int prev_link = netif_carrier_ok(dev) ? 1 : 0; 2793 u32 bcr9; 2794 2795 if (lp->mii) { 2796 curr_link = mii_link_ok(&lp->mii_if); 2797 } else { 2798 ulong ioaddr = dev->base_addr; /* card base I/O address */ 2799 curr_link = (lp->a->read_bcr(ioaddr, 4) != 0xc0); 2800 } 2801 if (!curr_link) { 2802 if (prev_link || verbose) { 2803 netif_carrier_off(dev); 2804 netif_info(lp, link, dev, "link down\n"); 2805 } 2806 if (lp->phycount > 1) { 2807 curr_link = pcnet32_check_otherphy(dev); 2808 prev_link = 0; 2809 } 2810 } else if (verbose || !prev_link) { 2811 netif_carrier_on(dev); 2812 if (lp->mii) { 2813 if (netif_msg_link(lp)) { 2814 struct ethtool_cmd ecmd = { 2815 .cmd = ETHTOOL_GSET }; 2816 mii_ethtool_gset(&lp->mii_if, &ecmd); 2817 netdev_info(dev, "link up, %uMbps, %s-duplex\n", 2818 ethtool_cmd_speed(&ecmd), 2819 (ecmd.duplex == DUPLEX_FULL) 2820 ? "full" : "half"); 2821 } 2822 bcr9 = lp->a->read_bcr(dev->base_addr, 9); 2823 if ((bcr9 & (1 << 0)) != lp->mii_if.full_duplex) { 2824 if (lp->mii_if.full_duplex) 2825 bcr9 |= (1 << 0); 2826 else 2827 bcr9 &= ~(1 << 0); 2828 lp->a->write_bcr(dev->base_addr, 9, bcr9); 2829 } 2830 } else { 2831 netif_info(lp, link, dev, "link up\n"); 2832 } 2833 } 2834 } 2835 2836 /* 2837 * Check for loss of link and link establishment. 2838 * Could possibly be changed to use mii_check_media instead. 2839 */ 2840 2841 static void pcnet32_watchdog(struct net_device *dev) 2842 { 2843 struct pcnet32_private *lp = netdev_priv(dev); 2844 unsigned long flags; 2845 2846 /* Print the link status if it has changed */ 2847 spin_lock_irqsave(&lp->lock, flags); 2848 pcnet32_check_media(dev, 0); 2849 spin_unlock_irqrestore(&lp->lock, flags); 2850 2851 mod_timer(&lp->watchdog_timer, round_jiffies(PCNET32_WATCHDOG_TIMEOUT)); 2852 } 2853 2854 static int pcnet32_pm_suspend(struct pci_dev *pdev, pm_message_t state) 2855 { 2856 struct net_device *dev = pci_get_drvdata(pdev); 2857 2858 if (netif_running(dev)) { 2859 netif_device_detach(dev); 2860 pcnet32_close(dev); 2861 } 2862 pci_save_state(pdev); 2863 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 2864 return 0; 2865 } 2866 2867 static int pcnet32_pm_resume(struct pci_dev *pdev) 2868 { 2869 struct net_device *dev = pci_get_drvdata(pdev); 2870 2871 pci_set_power_state(pdev, PCI_D0); 2872 pci_restore_state(pdev); 2873 2874 if (netif_running(dev)) { 2875 pcnet32_open(dev); 2876 netif_device_attach(dev); 2877 } 2878 return 0; 2879 } 2880 2881 static void pcnet32_remove_one(struct pci_dev *pdev) 2882 { 2883 struct net_device *dev = pci_get_drvdata(pdev); 2884 2885 if (dev) { 2886 struct pcnet32_private *lp = netdev_priv(dev); 2887 2888 unregister_netdev(dev); 2889 pcnet32_free_ring(dev); 2890 release_region(dev->base_addr, PCNET32_TOTAL_SIZE); 2891 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block), 2892 lp->init_block, lp->init_dma_addr); 2893 free_netdev(dev); 2894 pci_disable_device(pdev); 2895 } 2896 } 2897 2898 static struct pci_driver pcnet32_driver = { 2899 .name = DRV_NAME, 2900 .probe = pcnet32_probe_pci, 2901 .remove = pcnet32_remove_one, 2902 .id_table = pcnet32_pci_tbl, 2903 .suspend = pcnet32_pm_suspend, 2904 .resume = pcnet32_pm_resume, 2905 }; 2906 2907 /* An additional parameter that may be passed in... */ 2908 static int debug = -1; 2909 static int tx_start_pt = -1; 2910 static int pcnet32_have_pci; 2911 2912 module_param(debug, int, 0); 2913 MODULE_PARM_DESC(debug, DRV_NAME " debug level"); 2914 module_param(max_interrupt_work, int, 0); 2915 MODULE_PARM_DESC(max_interrupt_work, 2916 DRV_NAME " maximum events handled per interrupt"); 2917 module_param(rx_copybreak, int, 0); 2918 MODULE_PARM_DESC(rx_copybreak, 2919 DRV_NAME " copy breakpoint for copy-only-tiny-frames"); 2920 module_param(tx_start_pt, int, 0); 2921 MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)"); 2922 module_param(pcnet32vlb, int, 0); 2923 MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)"); 2924 module_param_array(options, int, NULL, 0); 2925 MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)"); 2926 module_param_array(full_duplex, int, NULL, 0); 2927 MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)"); 2928 /* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */ 2929 module_param_array(homepna, int, NULL, 0); 2930 MODULE_PARM_DESC(homepna, 2931 DRV_NAME 2932 " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet"); 2933 2934 MODULE_AUTHOR("Thomas Bogendoerfer"); 2935 MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards"); 2936 MODULE_LICENSE("GPL"); 2937 2938 #define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK) 2939 2940 static int __init pcnet32_init_module(void) 2941 { 2942 pr_info("%s", version); 2943 2944 pcnet32_debug = netif_msg_init(debug, PCNET32_MSG_DEFAULT); 2945 2946 if ((tx_start_pt >= 0) && (tx_start_pt <= 3)) 2947 tx_start = tx_start_pt; 2948 2949 /* find the PCI devices */ 2950 if (!pci_register_driver(&pcnet32_driver)) 2951 pcnet32_have_pci = 1; 2952 2953 /* should we find any remaining VLbus devices ? */ 2954 if (pcnet32vlb) 2955 pcnet32_probe_vlbus(pcnet32_portlist); 2956 2957 if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE)) 2958 pr_info("%d cards_found\n", cards_found); 2959 2960 return (pcnet32_have_pci + cards_found) ? 0 : -ENODEV; 2961 } 2962 2963 static void __exit pcnet32_cleanup_module(void) 2964 { 2965 struct net_device *next_dev; 2966 2967 while (pcnet32_dev) { 2968 struct pcnet32_private *lp = netdev_priv(pcnet32_dev); 2969 next_dev = lp->next; 2970 unregister_netdev(pcnet32_dev); 2971 pcnet32_free_ring(pcnet32_dev); 2972 release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE); 2973 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block), 2974 lp->init_block, lp->init_dma_addr); 2975 free_netdev(pcnet32_dev); 2976 pcnet32_dev = next_dev; 2977 } 2978 2979 if (pcnet32_have_pci) 2980 pci_unregister_driver(&pcnet32_driver); 2981 } 2982 2983 module_init(pcnet32_init_module); 2984 module_exit(pcnet32_cleanup_module); 2985 2986 /* 2987 * Local variables: 2988 * c-indent-level: 4 2989 * tab-width: 8 2990 * End: 2991 */ 2992