1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * Alchemy Au1x00 ethernet driver 5 * 6 * Copyright 2001-2003, 2006 MontaVista Software Inc. 7 * Copyright 2002 TimeSys Corp. 8 * Added ethtool/mii-tool support, 9 * Copyright 2004 Matt Porter <mporter@kernel.crashing.org> 10 * Update: 2004 Bjoern Riemer, riemer@fokus.fraunhofer.de 11 * or riemer@riemer-nt.de: fixed the link beat detection with 12 * ioctls (SIOCGMIIPHY) 13 * Copyright 2006 Herbert Valerio Riedel <hvr@gnu.org> 14 * converted to use linux-2.6.x's PHY framework 15 * 16 * Author: MontaVista Software, Inc. 17 * ppopov@mvista.com or source@mvista.com 18 */ 19 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 20 21 #include <linux/capability.h> 22 #include <linux/dma-mapping.h> 23 #include <linux/module.h> 24 #include <linux/kernel.h> 25 #include <linux/string.h> 26 #include <linux/timer.h> 27 #include <linux/errno.h> 28 #include <linux/in.h> 29 #include <linux/ioport.h> 30 #include <linux/bitops.h> 31 #include <linux/slab.h> 32 #include <linux/interrupt.h> 33 #include <linux/netdevice.h> 34 #include <linux/etherdevice.h> 35 #include <linux/ethtool.h> 36 #include <linux/mii.h> 37 #include <linux/skbuff.h> 38 #include <linux/delay.h> 39 #include <linux/crc32.h> 40 #include <linux/phy.h> 41 #include <linux/platform_device.h> 42 #include <linux/cpu.h> 43 #include <linux/io.h> 44 45 #include <asm/mipsregs.h> 46 #include <asm/irq.h> 47 #include <asm/processor.h> 48 49 #include <au1000.h> 50 #include <au1xxx_eth.h> 51 #include <prom.h> 52 53 #include "au1000_eth.h" 54 55 #ifdef AU1000_ETH_DEBUG 56 static int au1000_debug = 5; 57 #else 58 static int au1000_debug = 3; 59 #endif 60 61 #define AU1000_DEF_MSG_ENABLE (NETIF_MSG_DRV | \ 62 NETIF_MSG_PROBE | \ 63 NETIF_MSG_LINK) 64 65 #define DRV_NAME "au1000_eth" 66 #define DRV_AUTHOR "Pete Popov <ppopov@embeddedalley.com>" 67 #define DRV_DESC "Au1xxx on-chip Ethernet driver" 68 69 MODULE_AUTHOR(DRV_AUTHOR); 70 MODULE_DESCRIPTION(DRV_DESC); 71 MODULE_LICENSE("GPL"); 72 73 /* AU1000 MAC registers and bits */ 74 #define MAC_CONTROL 0x0 75 # define MAC_RX_ENABLE (1 << 2) 76 # define MAC_TX_ENABLE (1 << 3) 77 # define MAC_DEF_CHECK (1 << 5) 78 # define MAC_SET_BL(X) (((X) & 0x3) << 6) 79 # define MAC_AUTO_PAD (1 << 8) 80 # define MAC_DISABLE_RETRY (1 << 10) 81 # define MAC_DISABLE_BCAST (1 << 11) 82 # define MAC_LATE_COL (1 << 12) 83 # define MAC_HASH_MODE (1 << 13) 84 # define MAC_HASH_ONLY (1 << 15) 85 # define MAC_PASS_ALL (1 << 16) 86 # define MAC_INVERSE_FILTER (1 << 17) 87 # define MAC_PROMISCUOUS (1 << 18) 88 # define MAC_PASS_ALL_MULTI (1 << 19) 89 # define MAC_FULL_DUPLEX (1 << 20) 90 # define MAC_NORMAL_MODE 0 91 # define MAC_INT_LOOPBACK (1 << 21) 92 # define MAC_EXT_LOOPBACK (1 << 22) 93 # define MAC_DISABLE_RX_OWN (1 << 23) 94 # define MAC_BIG_ENDIAN (1 << 30) 95 # define MAC_RX_ALL (1 << 31) 96 #define MAC_ADDRESS_HIGH 0x4 97 #define MAC_ADDRESS_LOW 0x8 98 #define MAC_MCAST_HIGH 0xC 99 #define MAC_MCAST_LOW 0x10 100 #define MAC_MII_CNTRL 0x14 101 # define MAC_MII_BUSY (1 << 0) 102 # define MAC_MII_READ 0 103 # define MAC_MII_WRITE (1 << 1) 104 # define MAC_SET_MII_SELECT_REG(X) (((X) & 0x1f) << 6) 105 # define MAC_SET_MII_SELECT_PHY(X) (((X) & 0x1f) << 11) 106 #define MAC_MII_DATA 0x18 107 #define MAC_FLOW_CNTRL 0x1C 108 # define MAC_FLOW_CNTRL_BUSY (1 << 0) 109 # define MAC_FLOW_CNTRL_ENABLE (1 << 1) 110 # define MAC_PASS_CONTROL (1 << 2) 111 # define MAC_SET_PAUSE(X) (((X) & 0xffff) << 16) 112 #define MAC_VLAN1_TAG 0x20 113 #define MAC_VLAN2_TAG 0x24 114 115 /* Ethernet Controller Enable */ 116 # define MAC_EN_CLOCK_ENABLE (1 << 0) 117 # define MAC_EN_RESET0 (1 << 1) 118 # define MAC_EN_TOSS (0 << 2) 119 # define MAC_EN_CACHEABLE (1 << 3) 120 # define MAC_EN_RESET1 (1 << 4) 121 # define MAC_EN_RESET2 (1 << 5) 122 # define MAC_DMA_RESET (1 << 6) 123 124 /* Ethernet Controller DMA Channels */ 125 /* offsets from MAC_TX_RING_ADDR address */ 126 #define MAC_TX_BUFF0_STATUS 0x0 127 # define TX_FRAME_ABORTED (1 << 0) 128 # define TX_JAB_TIMEOUT (1 << 1) 129 # define TX_NO_CARRIER (1 << 2) 130 # define TX_LOSS_CARRIER (1 << 3) 131 # define TX_EXC_DEF (1 << 4) 132 # define TX_LATE_COLL_ABORT (1 << 5) 133 # define TX_EXC_COLL (1 << 6) 134 # define TX_UNDERRUN (1 << 7) 135 # define TX_DEFERRED (1 << 8) 136 # define TX_LATE_COLL (1 << 9) 137 # define TX_COLL_CNT_MASK (0xF << 10) 138 # define TX_PKT_RETRY (1 << 31) 139 #define MAC_TX_BUFF0_ADDR 0x4 140 # define TX_DMA_ENABLE (1 << 0) 141 # define TX_T_DONE (1 << 1) 142 # define TX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3) 143 #define MAC_TX_BUFF0_LEN 0x8 144 #define MAC_TX_BUFF1_STATUS 0x10 145 #define MAC_TX_BUFF1_ADDR 0x14 146 #define MAC_TX_BUFF1_LEN 0x18 147 #define MAC_TX_BUFF2_STATUS 0x20 148 #define MAC_TX_BUFF2_ADDR 0x24 149 #define MAC_TX_BUFF2_LEN 0x28 150 #define MAC_TX_BUFF3_STATUS 0x30 151 #define MAC_TX_BUFF3_ADDR 0x34 152 #define MAC_TX_BUFF3_LEN 0x38 153 154 /* offsets from MAC_RX_RING_ADDR */ 155 #define MAC_RX_BUFF0_STATUS 0x0 156 # define RX_FRAME_LEN_MASK 0x3fff 157 # define RX_WDOG_TIMER (1 << 14) 158 # define RX_RUNT (1 << 15) 159 # define RX_OVERLEN (1 << 16) 160 # define RX_COLL (1 << 17) 161 # define RX_ETHER (1 << 18) 162 # define RX_MII_ERROR (1 << 19) 163 # define RX_DRIBBLING (1 << 20) 164 # define RX_CRC_ERROR (1 << 21) 165 # define RX_VLAN1 (1 << 22) 166 # define RX_VLAN2 (1 << 23) 167 # define RX_LEN_ERROR (1 << 24) 168 # define RX_CNTRL_FRAME (1 << 25) 169 # define RX_U_CNTRL_FRAME (1 << 26) 170 # define RX_MCAST_FRAME (1 << 27) 171 # define RX_BCAST_FRAME (1 << 28) 172 # define RX_FILTER_FAIL (1 << 29) 173 # define RX_PACKET_FILTER (1 << 30) 174 # define RX_MISSED_FRAME (1 << 31) 175 176 # define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \ 177 RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \ 178 RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME) 179 #define MAC_RX_BUFF0_ADDR 0x4 180 # define RX_DMA_ENABLE (1 << 0) 181 # define RX_T_DONE (1 << 1) 182 # define RX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3) 183 # define RX_SET_BUFF_ADDR(X) ((X) & 0xffffffc0) 184 #define MAC_RX_BUFF1_STATUS 0x10 185 #define MAC_RX_BUFF1_ADDR 0x14 186 #define MAC_RX_BUFF2_STATUS 0x20 187 #define MAC_RX_BUFF2_ADDR 0x24 188 #define MAC_RX_BUFF3_STATUS 0x30 189 #define MAC_RX_BUFF3_ADDR 0x34 190 191 /* 192 * Theory of operation 193 * 194 * The Au1000 MACs use a simple rx and tx descriptor ring scheme. 195 * There are four receive and four transmit descriptors. These 196 * descriptors are not in memory; rather, they are just a set of 197 * hardware registers. 198 * 199 * Since the Au1000 has a coherent data cache, the receive and 200 * transmit buffers are allocated from the KSEG0 segment. The 201 * hardware registers, however, are still mapped at KSEG1 to 202 * make sure there's no out-of-order writes, and that all writes 203 * complete immediately. 204 */ 205 206 /* 207 * board-specific configurations 208 * 209 * PHY detection algorithm 210 * 211 * If phy_static_config is undefined, the PHY setup is 212 * autodetected: 213 * 214 * mii_probe() first searches the current MAC's MII bus for a PHY, 215 * selecting the first (or last, if phy_search_highest_addr is 216 * defined) PHY address not already claimed by another netdev. 217 * 218 * If nothing was found that way when searching for the 2nd ethernet 219 * controller's PHY and phy1_search_mac0 is defined, then 220 * the first MII bus is searched as well for an unclaimed PHY; this is 221 * needed in case of a dual-PHY accessible only through the MAC0's MII 222 * bus. 223 * 224 * Finally, if no PHY is found, then the corresponding ethernet 225 * controller is not registered to the network subsystem. 226 */ 227 228 /* autodetection defaults: phy1_search_mac0 */ 229 230 /* static PHY setup 231 * 232 * most boards PHY setup should be detectable properly with the 233 * autodetection algorithm in mii_probe(), but in some cases (e.g. if 234 * you have a switch attached, or want to use the PHY's interrupt 235 * notification capabilities) you can provide a static PHY 236 * configuration here 237 * 238 * IRQs may only be set, if a PHY address was configured 239 * If a PHY address is given, also a bus id is required to be set 240 * 241 * ps: make sure the used irqs are configured properly in the board 242 * specific irq-map 243 */ 244 245 static void au1000_enable_mac(struct net_device *dev, int force_reset) 246 { 247 unsigned long flags; 248 struct au1000_private *aup = netdev_priv(dev); 249 250 spin_lock_irqsave(&aup->lock, flags); 251 252 if (force_reset || (!aup->mac_enabled)) { 253 writel(MAC_EN_CLOCK_ENABLE, aup->enable); 254 wmb(); /* drain writebuffer */ 255 mdelay(2); 256 writel((MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2 257 | MAC_EN_CLOCK_ENABLE), aup->enable); 258 wmb(); /* drain writebuffer */ 259 mdelay(2); 260 261 aup->mac_enabled = 1; 262 } 263 264 spin_unlock_irqrestore(&aup->lock, flags); 265 } 266 267 /* 268 * MII operations 269 */ 270 static int au1000_mdio_read(struct net_device *dev, int phy_addr, int reg) 271 { 272 struct au1000_private *aup = netdev_priv(dev); 273 u32 *const mii_control_reg = &aup->mac->mii_control; 274 u32 *const mii_data_reg = &aup->mac->mii_data; 275 u32 timedout = 20; 276 u32 mii_control; 277 278 while (readl(mii_control_reg) & MAC_MII_BUSY) { 279 mdelay(1); 280 if (--timedout == 0) { 281 netdev_err(dev, "read_MII busy timeout!!\n"); 282 return -1; 283 } 284 } 285 286 mii_control = MAC_SET_MII_SELECT_REG(reg) | 287 MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_READ; 288 289 writel(mii_control, mii_control_reg); 290 291 timedout = 20; 292 while (readl(mii_control_reg) & MAC_MII_BUSY) { 293 mdelay(1); 294 if (--timedout == 0) { 295 netdev_err(dev, "mdio_read busy timeout!!\n"); 296 return -1; 297 } 298 } 299 return readl(mii_data_reg); 300 } 301 302 static void au1000_mdio_write(struct net_device *dev, int phy_addr, 303 int reg, u16 value) 304 { 305 struct au1000_private *aup = netdev_priv(dev); 306 u32 *const mii_control_reg = &aup->mac->mii_control; 307 u32 *const mii_data_reg = &aup->mac->mii_data; 308 u32 timedout = 20; 309 u32 mii_control; 310 311 while (readl(mii_control_reg) & MAC_MII_BUSY) { 312 mdelay(1); 313 if (--timedout == 0) { 314 netdev_err(dev, "mdio_write busy timeout!!\n"); 315 return; 316 } 317 } 318 319 mii_control = MAC_SET_MII_SELECT_REG(reg) | 320 MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_WRITE; 321 322 writel(value, mii_data_reg); 323 writel(mii_control, mii_control_reg); 324 } 325 326 static int au1000_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum) 327 { 328 struct net_device *const dev = bus->priv; 329 330 /* make sure the MAC associated with this 331 * mii_bus is enabled 332 */ 333 au1000_enable_mac(dev, 0); 334 335 return au1000_mdio_read(dev, phy_addr, regnum); 336 } 337 338 static int au1000_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, 339 u16 value) 340 { 341 struct net_device *const dev = bus->priv; 342 343 /* make sure the MAC associated with this 344 * mii_bus is enabled 345 */ 346 au1000_enable_mac(dev, 0); 347 348 au1000_mdio_write(dev, phy_addr, regnum, value); 349 return 0; 350 } 351 352 static int au1000_mdiobus_reset(struct mii_bus *bus) 353 { 354 struct net_device *const dev = bus->priv; 355 356 /* make sure the MAC associated with this 357 * mii_bus is enabled 358 */ 359 au1000_enable_mac(dev, 0); 360 361 return 0; 362 } 363 364 static void au1000_hard_stop(struct net_device *dev) 365 { 366 struct au1000_private *aup = netdev_priv(dev); 367 u32 reg; 368 369 netif_dbg(aup, drv, dev, "hard stop\n"); 370 371 reg = readl(&aup->mac->control); 372 reg &= ~(MAC_RX_ENABLE | MAC_TX_ENABLE); 373 writel(reg, &aup->mac->control); 374 wmb(); /* drain writebuffer */ 375 mdelay(10); 376 } 377 378 static void au1000_enable_rx_tx(struct net_device *dev) 379 { 380 struct au1000_private *aup = netdev_priv(dev); 381 u32 reg; 382 383 netif_dbg(aup, hw, dev, "enable_rx_tx\n"); 384 385 reg = readl(&aup->mac->control); 386 reg |= (MAC_RX_ENABLE | MAC_TX_ENABLE); 387 writel(reg, &aup->mac->control); 388 wmb(); /* drain writebuffer */ 389 mdelay(10); 390 } 391 392 static void 393 au1000_adjust_link(struct net_device *dev) 394 { 395 struct au1000_private *aup = netdev_priv(dev); 396 struct phy_device *phydev = dev->phydev; 397 unsigned long flags; 398 u32 reg; 399 400 int status_change = 0; 401 402 BUG_ON(!phydev); 403 404 spin_lock_irqsave(&aup->lock, flags); 405 406 if (phydev->link && (aup->old_speed != phydev->speed)) { 407 /* speed changed */ 408 409 switch (phydev->speed) { 410 case SPEED_10: 411 case SPEED_100: 412 break; 413 default: 414 netdev_warn(dev, "Speed (%d) is not 10/100 ???\n", 415 phydev->speed); 416 break; 417 } 418 419 aup->old_speed = phydev->speed; 420 421 status_change = 1; 422 } 423 424 if (phydev->link && (aup->old_duplex != phydev->duplex)) { 425 /* duplex mode changed */ 426 427 /* switching duplex mode requires to disable rx and tx! */ 428 au1000_hard_stop(dev); 429 430 reg = readl(&aup->mac->control); 431 if (DUPLEX_FULL == phydev->duplex) { 432 reg |= MAC_FULL_DUPLEX; 433 reg &= ~MAC_DISABLE_RX_OWN; 434 } else { 435 reg &= ~MAC_FULL_DUPLEX; 436 reg |= MAC_DISABLE_RX_OWN; 437 } 438 writel(reg, &aup->mac->control); 439 wmb(); /* drain writebuffer */ 440 mdelay(1); 441 442 au1000_enable_rx_tx(dev); 443 aup->old_duplex = phydev->duplex; 444 445 status_change = 1; 446 } 447 448 if (phydev->link != aup->old_link) { 449 /* link state changed */ 450 451 if (!phydev->link) { 452 /* link went down */ 453 aup->old_speed = 0; 454 aup->old_duplex = -1; 455 } 456 457 aup->old_link = phydev->link; 458 status_change = 1; 459 } 460 461 spin_unlock_irqrestore(&aup->lock, flags); 462 463 if (status_change) { 464 if (phydev->link) 465 netdev_info(dev, "link up (%d/%s)\n", 466 phydev->speed, 467 DUPLEX_FULL == phydev->duplex ? "Full" : "Half"); 468 else 469 netdev_info(dev, "link down\n"); 470 } 471 } 472 473 static int au1000_mii_probe(struct net_device *dev) 474 { 475 struct au1000_private *const aup = netdev_priv(dev); 476 struct phy_device *phydev = NULL; 477 int phy_addr; 478 479 if (aup->phy_static_config) { 480 BUG_ON(aup->mac_id < 0 || aup->mac_id > 1); 481 482 if (aup->phy_addr) 483 phydev = mdiobus_get_phy(aup->mii_bus, aup->phy_addr); 484 else 485 netdev_info(dev, "using PHY-less setup\n"); 486 return 0; 487 } 488 489 /* find the first (lowest address) PHY 490 * on the current MAC's MII bus 491 */ 492 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) 493 if (mdiobus_get_phy(aup->mii_bus, phy_addr)) { 494 phydev = mdiobus_get_phy(aup->mii_bus, phy_addr); 495 if (!aup->phy_search_highest_addr) 496 /* break out with first one found */ 497 break; 498 } 499 500 if (aup->phy1_search_mac0) { 501 /* try harder to find a PHY */ 502 if (!phydev && (aup->mac_id == 1)) { 503 /* no PHY found, maybe we have a dual PHY? */ 504 dev_info(&dev->dev, ": no PHY found on MAC1, " 505 "let's see if it's attached to MAC0...\n"); 506 507 /* find the first (lowest address) non-attached 508 * PHY on the MAC0 MII bus 509 */ 510 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { 511 struct phy_device *const tmp_phydev = 512 mdiobus_get_phy(aup->mii_bus, 513 phy_addr); 514 515 if (aup->mac_id == 1) 516 break; 517 518 /* no PHY here... */ 519 if (!tmp_phydev) 520 continue; 521 522 /* already claimed by MAC0 */ 523 if (tmp_phydev->attached_dev) 524 continue; 525 526 phydev = tmp_phydev; 527 break; /* found it */ 528 } 529 } 530 } 531 532 if (!phydev) { 533 netdev_err(dev, "no PHY found\n"); 534 return -1; 535 } 536 537 /* now we are supposed to have a proper phydev, to attach to... */ 538 BUG_ON(phydev->attached_dev); 539 540 phydev = phy_connect(dev, phydev_name(phydev), 541 &au1000_adjust_link, PHY_INTERFACE_MODE_MII); 542 543 if (IS_ERR(phydev)) { 544 netdev_err(dev, "Could not attach to PHY\n"); 545 return PTR_ERR(phydev); 546 } 547 548 phy_set_max_speed(phydev, SPEED_100); 549 550 aup->old_link = 0; 551 aup->old_speed = 0; 552 aup->old_duplex = -1; 553 554 phy_attached_info(phydev); 555 556 return 0; 557 } 558 559 560 /* 561 * Buffer allocation/deallocation routines. The buffer descriptor returned 562 * has the virtual and dma address of a buffer suitable for 563 * both, receive and transmit operations. 564 */ 565 static struct db_dest *au1000_GetFreeDB(struct au1000_private *aup) 566 { 567 struct db_dest *pDB; 568 pDB = aup->pDBfree; 569 570 if (pDB) 571 aup->pDBfree = pDB->pnext; 572 573 return pDB; 574 } 575 576 void au1000_ReleaseDB(struct au1000_private *aup, struct db_dest *pDB) 577 { 578 struct db_dest *pDBfree = aup->pDBfree; 579 if (pDBfree) 580 pDBfree->pnext = pDB; 581 aup->pDBfree = pDB; 582 } 583 584 static void au1000_reset_mac_unlocked(struct net_device *dev) 585 { 586 struct au1000_private *const aup = netdev_priv(dev); 587 int i; 588 589 au1000_hard_stop(dev); 590 591 writel(MAC_EN_CLOCK_ENABLE, aup->enable); 592 wmb(); /* drain writebuffer */ 593 mdelay(2); 594 writel(0, aup->enable); 595 wmb(); /* drain writebuffer */ 596 mdelay(2); 597 598 aup->tx_full = 0; 599 for (i = 0; i < NUM_RX_DMA; i++) { 600 /* reset control bits */ 601 aup->rx_dma_ring[i]->buff_stat &= ~0xf; 602 } 603 for (i = 0; i < NUM_TX_DMA; i++) { 604 /* reset control bits */ 605 aup->tx_dma_ring[i]->buff_stat &= ~0xf; 606 } 607 608 aup->mac_enabled = 0; 609 610 } 611 612 static void au1000_reset_mac(struct net_device *dev) 613 { 614 struct au1000_private *const aup = netdev_priv(dev); 615 unsigned long flags; 616 617 netif_dbg(aup, hw, dev, "reset mac, aup %x\n", 618 (unsigned)aup); 619 620 spin_lock_irqsave(&aup->lock, flags); 621 622 au1000_reset_mac_unlocked(dev); 623 624 spin_unlock_irqrestore(&aup->lock, flags); 625 } 626 627 /* 628 * Setup the receive and transmit "rings". These pointers are the addresses 629 * of the rx and tx MAC DMA registers so they are fixed by the hardware -- 630 * these are not descriptors sitting in memory. 631 */ 632 static void 633 au1000_setup_hw_rings(struct au1000_private *aup, void __iomem *tx_base) 634 { 635 int i; 636 637 for (i = 0; i < NUM_RX_DMA; i++) { 638 aup->rx_dma_ring[i] = (struct rx_dma *) 639 (tx_base + 0x100 + sizeof(struct rx_dma) * i); 640 } 641 for (i = 0; i < NUM_TX_DMA; i++) { 642 aup->tx_dma_ring[i] = (struct tx_dma *) 643 (tx_base + sizeof(struct tx_dma) * i); 644 } 645 } 646 647 /* 648 * ethtool operations 649 */ 650 651 static void 652 au1000_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 653 { 654 struct au1000_private *aup = netdev_priv(dev); 655 656 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 657 snprintf(info->bus_info, sizeof(info->bus_info), "%s %d", DRV_NAME, 658 aup->mac_id); 659 } 660 661 static void au1000_set_msglevel(struct net_device *dev, u32 value) 662 { 663 struct au1000_private *aup = netdev_priv(dev); 664 aup->msg_enable = value; 665 } 666 667 static u32 au1000_get_msglevel(struct net_device *dev) 668 { 669 struct au1000_private *aup = netdev_priv(dev); 670 return aup->msg_enable; 671 } 672 673 static const struct ethtool_ops au1000_ethtool_ops = { 674 .get_drvinfo = au1000_get_drvinfo, 675 .get_link = ethtool_op_get_link, 676 .get_msglevel = au1000_get_msglevel, 677 .set_msglevel = au1000_set_msglevel, 678 .get_link_ksettings = phy_ethtool_get_link_ksettings, 679 .set_link_ksettings = phy_ethtool_set_link_ksettings, 680 }; 681 682 683 /* 684 * Initialize the interface. 685 * 686 * When the device powers up, the clocks are disabled and the 687 * mac is in reset state. When the interface is closed, we 688 * do the same -- reset the device and disable the clocks to 689 * conserve power. Thus, whenever au1000_init() is called, 690 * the device should already be in reset state. 691 */ 692 static int au1000_init(struct net_device *dev) 693 { 694 struct au1000_private *aup = netdev_priv(dev); 695 unsigned long flags; 696 int i; 697 u32 control; 698 699 netif_dbg(aup, hw, dev, "au1000_init\n"); 700 701 /* bring the device out of reset */ 702 au1000_enable_mac(dev, 1); 703 704 spin_lock_irqsave(&aup->lock, flags); 705 706 writel(0, &aup->mac->control); 707 aup->tx_head = (aup->tx_dma_ring[0]->buff_stat & 0xC) >> 2; 708 aup->tx_tail = aup->tx_head; 709 aup->rx_head = (aup->rx_dma_ring[0]->buff_stat & 0xC) >> 2; 710 711 writel(dev->dev_addr[5]<<8 | dev->dev_addr[4], 712 &aup->mac->mac_addr_high); 713 writel(dev->dev_addr[3]<<24 | dev->dev_addr[2]<<16 | 714 dev->dev_addr[1]<<8 | dev->dev_addr[0], 715 &aup->mac->mac_addr_low); 716 717 718 for (i = 0; i < NUM_RX_DMA; i++) 719 aup->rx_dma_ring[i]->buff_stat |= RX_DMA_ENABLE; 720 721 wmb(); /* drain writebuffer */ 722 723 control = MAC_RX_ENABLE | MAC_TX_ENABLE; 724 #ifndef CONFIG_CPU_LITTLE_ENDIAN 725 control |= MAC_BIG_ENDIAN; 726 #endif 727 if (dev->phydev) { 728 if (dev->phydev->link && (DUPLEX_FULL == dev->phydev->duplex)) 729 control |= MAC_FULL_DUPLEX; 730 else 731 control |= MAC_DISABLE_RX_OWN; 732 } else { /* PHY-less op, assume full-duplex */ 733 control |= MAC_FULL_DUPLEX; 734 } 735 736 writel(control, &aup->mac->control); 737 writel(0x8100, &aup->mac->vlan1_tag); /* activate vlan support */ 738 wmb(); /* drain writebuffer */ 739 740 spin_unlock_irqrestore(&aup->lock, flags); 741 return 0; 742 } 743 744 static inline void au1000_update_rx_stats(struct net_device *dev, u32 status) 745 { 746 struct net_device_stats *ps = &dev->stats; 747 748 ps->rx_packets++; 749 if (status & RX_MCAST_FRAME) 750 ps->multicast++; 751 752 if (status & RX_ERROR) { 753 ps->rx_errors++; 754 if (status & RX_MISSED_FRAME) 755 ps->rx_missed_errors++; 756 if (status & (RX_OVERLEN | RX_RUNT | RX_LEN_ERROR)) 757 ps->rx_length_errors++; 758 if (status & RX_CRC_ERROR) 759 ps->rx_crc_errors++; 760 if (status & RX_COLL) 761 ps->collisions++; 762 } else 763 ps->rx_bytes += status & RX_FRAME_LEN_MASK; 764 765 } 766 767 /* 768 * Au1000 receive routine. 769 */ 770 static int au1000_rx(struct net_device *dev) 771 { 772 struct au1000_private *aup = netdev_priv(dev); 773 struct sk_buff *skb; 774 struct rx_dma *prxd; 775 u32 buff_stat, status; 776 struct db_dest *pDB; 777 u32 frmlen; 778 779 netif_dbg(aup, rx_status, dev, "au1000_rx head %d\n", aup->rx_head); 780 781 prxd = aup->rx_dma_ring[aup->rx_head]; 782 buff_stat = prxd->buff_stat; 783 while (buff_stat & RX_T_DONE) { 784 status = prxd->status; 785 pDB = aup->rx_db_inuse[aup->rx_head]; 786 au1000_update_rx_stats(dev, status); 787 if (!(status & RX_ERROR)) { 788 789 /* good frame */ 790 frmlen = (status & RX_FRAME_LEN_MASK); 791 frmlen -= 4; /* Remove FCS */ 792 skb = netdev_alloc_skb(dev, frmlen + 2); 793 if (skb == NULL) { 794 dev->stats.rx_dropped++; 795 continue; 796 } 797 skb_reserve(skb, 2); /* 16 byte IP header align */ 798 skb_copy_to_linear_data(skb, 799 (unsigned char *)pDB->vaddr, frmlen); 800 skb_put(skb, frmlen); 801 skb->protocol = eth_type_trans(skb, dev); 802 netif_rx(skb); /* pass the packet to upper layers */ 803 } else { 804 if (au1000_debug > 4) { 805 pr_err("rx_error(s):"); 806 if (status & RX_MISSED_FRAME) 807 pr_cont(" miss"); 808 if (status & RX_WDOG_TIMER) 809 pr_cont(" wdog"); 810 if (status & RX_RUNT) 811 pr_cont(" runt"); 812 if (status & RX_OVERLEN) 813 pr_cont(" overlen"); 814 if (status & RX_COLL) 815 pr_cont(" coll"); 816 if (status & RX_MII_ERROR) 817 pr_cont(" mii error"); 818 if (status & RX_CRC_ERROR) 819 pr_cont(" crc error"); 820 if (status & RX_LEN_ERROR) 821 pr_cont(" len error"); 822 if (status & RX_U_CNTRL_FRAME) 823 pr_cont(" u control frame"); 824 pr_cont("\n"); 825 } 826 } 827 prxd->buff_stat = (u32)(pDB->dma_addr | RX_DMA_ENABLE); 828 aup->rx_head = (aup->rx_head + 1) & (NUM_RX_DMA - 1); 829 wmb(); /* drain writebuffer */ 830 831 /* next descriptor */ 832 prxd = aup->rx_dma_ring[aup->rx_head]; 833 buff_stat = prxd->buff_stat; 834 } 835 return 0; 836 } 837 838 static void au1000_update_tx_stats(struct net_device *dev, u32 status) 839 { 840 struct net_device_stats *ps = &dev->stats; 841 842 if (status & TX_FRAME_ABORTED) { 843 if (!dev->phydev || (DUPLEX_FULL == dev->phydev->duplex)) { 844 if (status & (TX_JAB_TIMEOUT | TX_UNDERRUN)) { 845 /* any other tx errors are only valid 846 * in half duplex mode 847 */ 848 ps->tx_errors++; 849 ps->tx_aborted_errors++; 850 } 851 } else { 852 ps->tx_errors++; 853 ps->tx_aborted_errors++; 854 if (status & (TX_NO_CARRIER | TX_LOSS_CARRIER)) 855 ps->tx_carrier_errors++; 856 } 857 } 858 } 859 860 /* 861 * Called from the interrupt service routine to acknowledge 862 * the TX DONE bits. This is a must if the irq is setup as 863 * edge triggered. 864 */ 865 static void au1000_tx_ack(struct net_device *dev) 866 { 867 struct au1000_private *aup = netdev_priv(dev); 868 struct tx_dma *ptxd; 869 870 ptxd = aup->tx_dma_ring[aup->tx_tail]; 871 872 while (ptxd->buff_stat & TX_T_DONE) { 873 au1000_update_tx_stats(dev, ptxd->status); 874 ptxd->buff_stat &= ~TX_T_DONE; 875 ptxd->len = 0; 876 wmb(); /* drain writebuffer */ 877 878 aup->tx_tail = (aup->tx_tail + 1) & (NUM_TX_DMA - 1); 879 ptxd = aup->tx_dma_ring[aup->tx_tail]; 880 881 if (aup->tx_full) { 882 aup->tx_full = 0; 883 netif_wake_queue(dev); 884 } 885 } 886 } 887 888 /* 889 * Au1000 interrupt service routine. 890 */ 891 static irqreturn_t au1000_interrupt(int irq, void *dev_id) 892 { 893 struct net_device *dev = dev_id; 894 895 /* Handle RX interrupts first to minimize chance of overrun */ 896 897 au1000_rx(dev); 898 au1000_tx_ack(dev); 899 return IRQ_RETVAL(1); 900 } 901 902 static int au1000_open(struct net_device *dev) 903 { 904 int retval; 905 struct au1000_private *aup = netdev_priv(dev); 906 907 netif_dbg(aup, drv, dev, "open: dev=%p\n", dev); 908 909 retval = request_irq(dev->irq, au1000_interrupt, 0, 910 dev->name, dev); 911 if (retval) { 912 netdev_err(dev, "unable to get IRQ %d\n", dev->irq); 913 return retval; 914 } 915 916 retval = au1000_init(dev); 917 if (retval) { 918 netdev_err(dev, "error in au1000_init\n"); 919 free_irq(dev->irq, dev); 920 return retval; 921 } 922 923 if (dev->phydev) 924 phy_start(dev->phydev); 925 926 netif_start_queue(dev); 927 928 netif_dbg(aup, drv, dev, "open: Initialization done.\n"); 929 930 return 0; 931 } 932 933 static int au1000_close(struct net_device *dev) 934 { 935 unsigned long flags; 936 struct au1000_private *const aup = netdev_priv(dev); 937 938 netif_dbg(aup, drv, dev, "close: dev=%p\n", dev); 939 940 if (dev->phydev) 941 phy_stop(dev->phydev); 942 943 spin_lock_irqsave(&aup->lock, flags); 944 945 au1000_reset_mac_unlocked(dev); 946 947 /* stop the device */ 948 netif_stop_queue(dev); 949 950 /* disable the interrupt */ 951 free_irq(dev->irq, dev); 952 spin_unlock_irqrestore(&aup->lock, flags); 953 954 return 0; 955 } 956 957 /* 958 * Au1000 transmit routine. 959 */ 960 static netdev_tx_t au1000_tx(struct sk_buff *skb, struct net_device *dev) 961 { 962 struct au1000_private *aup = netdev_priv(dev); 963 struct net_device_stats *ps = &dev->stats; 964 struct tx_dma *ptxd; 965 u32 buff_stat; 966 struct db_dest *pDB; 967 int i; 968 969 netif_dbg(aup, tx_queued, dev, "tx: aup %x len=%d, data=%p, head %d\n", 970 (unsigned)aup, skb->len, 971 skb->data, aup->tx_head); 972 973 ptxd = aup->tx_dma_ring[aup->tx_head]; 974 buff_stat = ptxd->buff_stat; 975 if (buff_stat & TX_DMA_ENABLE) { 976 /* We've wrapped around and the transmitter is still busy */ 977 netif_stop_queue(dev); 978 aup->tx_full = 1; 979 return NETDEV_TX_BUSY; 980 } else if (buff_stat & TX_T_DONE) { 981 au1000_update_tx_stats(dev, ptxd->status); 982 ptxd->len = 0; 983 } 984 985 if (aup->tx_full) { 986 aup->tx_full = 0; 987 netif_wake_queue(dev); 988 } 989 990 pDB = aup->tx_db_inuse[aup->tx_head]; 991 skb_copy_from_linear_data(skb, (void *)pDB->vaddr, skb->len); 992 if (skb->len < ETH_ZLEN) { 993 for (i = skb->len; i < ETH_ZLEN; i++) 994 ((char *)pDB->vaddr)[i] = 0; 995 996 ptxd->len = ETH_ZLEN; 997 } else 998 ptxd->len = skb->len; 999 1000 ps->tx_packets++; 1001 ps->tx_bytes += ptxd->len; 1002 1003 ptxd->buff_stat = pDB->dma_addr | TX_DMA_ENABLE; 1004 wmb(); /* drain writebuffer */ 1005 dev_kfree_skb(skb); 1006 aup->tx_head = (aup->tx_head + 1) & (NUM_TX_DMA - 1); 1007 return NETDEV_TX_OK; 1008 } 1009 1010 /* 1011 * The Tx ring has been full longer than the watchdog timeout 1012 * value. The transmitter must be hung? 1013 */ 1014 static void au1000_tx_timeout(struct net_device *dev, unsigned int txqueue) 1015 { 1016 netdev_err(dev, "au1000_tx_timeout: dev=%p\n", dev); 1017 au1000_reset_mac(dev); 1018 au1000_init(dev); 1019 netif_trans_update(dev); /* prevent tx timeout */ 1020 netif_wake_queue(dev); 1021 } 1022 1023 static void au1000_multicast_list(struct net_device *dev) 1024 { 1025 struct au1000_private *aup = netdev_priv(dev); 1026 u32 reg; 1027 1028 netif_dbg(aup, drv, dev, "%s: flags=%x\n", __func__, dev->flags); 1029 reg = readl(&aup->mac->control); 1030 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */ 1031 reg |= MAC_PROMISCUOUS; 1032 } else if ((dev->flags & IFF_ALLMULTI) || 1033 netdev_mc_count(dev) > MULTICAST_FILTER_LIMIT) { 1034 reg |= MAC_PASS_ALL_MULTI; 1035 reg &= ~MAC_PROMISCUOUS; 1036 netdev_info(dev, "Pass all multicast\n"); 1037 } else { 1038 struct netdev_hw_addr *ha; 1039 u32 mc_filter[2]; /* Multicast hash filter */ 1040 1041 mc_filter[1] = mc_filter[0] = 0; 1042 netdev_for_each_mc_addr(ha, dev) 1043 set_bit(ether_crc(ETH_ALEN, ha->addr)>>26, 1044 (long *)mc_filter); 1045 writel(mc_filter[1], &aup->mac->multi_hash_high); 1046 writel(mc_filter[0], &aup->mac->multi_hash_low); 1047 reg &= ~MAC_PROMISCUOUS; 1048 reg |= MAC_HASH_MODE; 1049 } 1050 writel(reg, &aup->mac->control); 1051 } 1052 1053 static const struct net_device_ops au1000_netdev_ops = { 1054 .ndo_open = au1000_open, 1055 .ndo_stop = au1000_close, 1056 .ndo_start_xmit = au1000_tx, 1057 .ndo_set_rx_mode = au1000_multicast_list, 1058 .ndo_do_ioctl = phy_do_ioctl_running, 1059 .ndo_tx_timeout = au1000_tx_timeout, 1060 .ndo_set_mac_address = eth_mac_addr, 1061 .ndo_validate_addr = eth_validate_addr, 1062 }; 1063 1064 static int au1000_probe(struct platform_device *pdev) 1065 { 1066 struct au1000_private *aup = NULL; 1067 struct au1000_eth_platform_data *pd; 1068 struct net_device *dev = NULL; 1069 struct db_dest *pDB, *pDBfree; 1070 int irq, i, err = 0; 1071 struct resource *base, *macen, *macdma; 1072 1073 base = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1074 if (!base) { 1075 dev_err(&pdev->dev, "failed to retrieve base register\n"); 1076 err = -ENODEV; 1077 goto out; 1078 } 1079 1080 macen = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1081 if (!macen) { 1082 dev_err(&pdev->dev, "failed to retrieve MAC Enable register\n"); 1083 err = -ENODEV; 1084 goto out; 1085 } 1086 1087 irq = platform_get_irq(pdev, 0); 1088 if (irq < 0) { 1089 err = -ENODEV; 1090 goto out; 1091 } 1092 1093 macdma = platform_get_resource(pdev, IORESOURCE_MEM, 2); 1094 if (!macdma) { 1095 dev_err(&pdev->dev, "failed to retrieve MACDMA registers\n"); 1096 err = -ENODEV; 1097 goto out; 1098 } 1099 1100 if (!request_mem_region(base->start, resource_size(base), 1101 pdev->name)) { 1102 dev_err(&pdev->dev, "failed to request memory region for base registers\n"); 1103 err = -ENXIO; 1104 goto out; 1105 } 1106 1107 if (!request_mem_region(macen->start, resource_size(macen), 1108 pdev->name)) { 1109 dev_err(&pdev->dev, "failed to request memory region for MAC enable register\n"); 1110 err = -ENXIO; 1111 goto err_request; 1112 } 1113 1114 if (!request_mem_region(macdma->start, resource_size(macdma), 1115 pdev->name)) { 1116 dev_err(&pdev->dev, "failed to request MACDMA memory region\n"); 1117 err = -ENXIO; 1118 goto err_macdma; 1119 } 1120 1121 dev = alloc_etherdev(sizeof(struct au1000_private)); 1122 if (!dev) { 1123 err = -ENOMEM; 1124 goto err_alloc; 1125 } 1126 1127 SET_NETDEV_DEV(dev, &pdev->dev); 1128 platform_set_drvdata(pdev, dev); 1129 aup = netdev_priv(dev); 1130 1131 spin_lock_init(&aup->lock); 1132 aup->msg_enable = (au1000_debug < 4 ? 1133 AU1000_DEF_MSG_ENABLE : au1000_debug); 1134 1135 /* Allocate the data buffers 1136 * Snooping works fine with eth on all au1xxx 1137 */ 1138 aup->vaddr = (u32)dma_alloc_attrs(&pdev->dev, MAX_BUF_SIZE * 1139 (NUM_TX_BUFFS + NUM_RX_BUFFS), 1140 &aup->dma_addr, 0, 1141 DMA_ATTR_NON_CONSISTENT); 1142 if (!aup->vaddr) { 1143 dev_err(&pdev->dev, "failed to allocate data buffers\n"); 1144 err = -ENOMEM; 1145 goto err_vaddr; 1146 } 1147 1148 /* aup->mac is the base address of the MAC's registers */ 1149 aup->mac = (struct mac_reg *) 1150 ioremap(base->start, resource_size(base)); 1151 if (!aup->mac) { 1152 dev_err(&pdev->dev, "failed to ioremap MAC registers\n"); 1153 err = -ENXIO; 1154 goto err_remap1; 1155 } 1156 1157 /* Setup some variables for quick register address access */ 1158 aup->enable = (u32 *)ioremap(macen->start, 1159 resource_size(macen)); 1160 if (!aup->enable) { 1161 dev_err(&pdev->dev, "failed to ioremap MAC enable register\n"); 1162 err = -ENXIO; 1163 goto err_remap2; 1164 } 1165 aup->mac_id = pdev->id; 1166 1167 aup->macdma = ioremap(macdma->start, resource_size(macdma)); 1168 if (!aup->macdma) { 1169 dev_err(&pdev->dev, "failed to ioremap MACDMA registers\n"); 1170 err = -ENXIO; 1171 goto err_remap3; 1172 } 1173 1174 au1000_setup_hw_rings(aup, aup->macdma); 1175 1176 writel(0, aup->enable); 1177 aup->mac_enabled = 0; 1178 1179 pd = dev_get_platdata(&pdev->dev); 1180 if (!pd) { 1181 dev_info(&pdev->dev, "no platform_data passed," 1182 " PHY search on MAC0\n"); 1183 aup->phy1_search_mac0 = 1; 1184 } else { 1185 if (is_valid_ether_addr(pd->mac)) { 1186 memcpy(dev->dev_addr, pd->mac, ETH_ALEN); 1187 } else { 1188 /* Set a random MAC since no valid provided by platform_data. */ 1189 eth_hw_addr_random(dev); 1190 } 1191 1192 aup->phy_static_config = pd->phy_static_config; 1193 aup->phy_search_highest_addr = pd->phy_search_highest_addr; 1194 aup->phy1_search_mac0 = pd->phy1_search_mac0; 1195 aup->phy_addr = pd->phy_addr; 1196 aup->phy_busid = pd->phy_busid; 1197 aup->phy_irq = pd->phy_irq; 1198 } 1199 1200 if (aup->phy_busid > 0) { 1201 dev_err(&pdev->dev, "MAC0-associated PHY attached 2nd MACs MII bus not supported yet\n"); 1202 err = -ENODEV; 1203 goto err_mdiobus_alloc; 1204 } 1205 1206 aup->mii_bus = mdiobus_alloc(); 1207 if (aup->mii_bus == NULL) { 1208 dev_err(&pdev->dev, "failed to allocate mdiobus structure\n"); 1209 err = -ENOMEM; 1210 goto err_mdiobus_alloc; 1211 } 1212 1213 aup->mii_bus->priv = dev; 1214 aup->mii_bus->read = au1000_mdiobus_read; 1215 aup->mii_bus->write = au1000_mdiobus_write; 1216 aup->mii_bus->reset = au1000_mdiobus_reset; 1217 aup->mii_bus->name = "au1000_eth_mii"; 1218 snprintf(aup->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 1219 pdev->name, aup->mac_id); 1220 1221 /* if known, set corresponding PHY IRQs */ 1222 if (aup->phy_static_config) 1223 if (aup->phy_irq && aup->phy_busid == aup->mac_id) 1224 aup->mii_bus->irq[aup->phy_addr] = aup->phy_irq; 1225 1226 err = mdiobus_register(aup->mii_bus); 1227 if (err) { 1228 dev_err(&pdev->dev, "failed to register MDIO bus\n"); 1229 goto err_mdiobus_reg; 1230 } 1231 1232 err = au1000_mii_probe(dev); 1233 if (err != 0) 1234 goto err_out; 1235 1236 pDBfree = NULL; 1237 /* setup the data buffer descriptors and attach a buffer to each one */ 1238 pDB = aup->db; 1239 for (i = 0; i < (NUM_TX_BUFFS+NUM_RX_BUFFS); i++) { 1240 pDB->pnext = pDBfree; 1241 pDBfree = pDB; 1242 pDB->vaddr = (u32 *)((unsigned)aup->vaddr + MAX_BUF_SIZE*i); 1243 pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr); 1244 pDB++; 1245 } 1246 aup->pDBfree = pDBfree; 1247 1248 err = -ENODEV; 1249 for (i = 0; i < NUM_RX_DMA; i++) { 1250 pDB = au1000_GetFreeDB(aup); 1251 if (!pDB) 1252 goto err_out; 1253 1254 aup->rx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr; 1255 aup->rx_db_inuse[i] = pDB; 1256 } 1257 1258 err = -ENODEV; 1259 for (i = 0; i < NUM_TX_DMA; i++) { 1260 pDB = au1000_GetFreeDB(aup); 1261 if (!pDB) 1262 goto err_out; 1263 1264 aup->tx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr; 1265 aup->tx_dma_ring[i]->len = 0; 1266 aup->tx_db_inuse[i] = pDB; 1267 } 1268 1269 dev->base_addr = base->start; 1270 dev->irq = irq; 1271 dev->netdev_ops = &au1000_netdev_ops; 1272 dev->ethtool_ops = &au1000_ethtool_ops; 1273 dev->watchdog_timeo = ETH_TX_TIMEOUT; 1274 1275 /* 1276 * The boot code uses the ethernet controller, so reset it to start 1277 * fresh. au1000_init() expects that the device is in reset state. 1278 */ 1279 au1000_reset_mac(dev); 1280 1281 err = register_netdev(dev); 1282 if (err) { 1283 netdev_err(dev, "Cannot register net device, aborting.\n"); 1284 goto err_out; 1285 } 1286 1287 netdev_info(dev, "Au1xx0 Ethernet found at 0x%lx, irq %d\n", 1288 (unsigned long)base->start, irq); 1289 1290 return 0; 1291 1292 err_out: 1293 if (aup->mii_bus != NULL) 1294 mdiobus_unregister(aup->mii_bus); 1295 1296 /* here we should have a valid dev plus aup-> register addresses 1297 * so we can reset the mac properly. 1298 */ 1299 au1000_reset_mac(dev); 1300 1301 for (i = 0; i < NUM_RX_DMA; i++) { 1302 if (aup->rx_db_inuse[i]) 1303 au1000_ReleaseDB(aup, aup->rx_db_inuse[i]); 1304 } 1305 for (i = 0; i < NUM_TX_DMA; i++) { 1306 if (aup->tx_db_inuse[i]) 1307 au1000_ReleaseDB(aup, aup->tx_db_inuse[i]); 1308 } 1309 err_mdiobus_reg: 1310 mdiobus_free(aup->mii_bus); 1311 err_mdiobus_alloc: 1312 iounmap(aup->macdma); 1313 err_remap3: 1314 iounmap(aup->enable); 1315 err_remap2: 1316 iounmap(aup->mac); 1317 err_remap1: 1318 dma_free_attrs(&pdev->dev, MAX_BUF_SIZE * (NUM_TX_BUFFS + NUM_RX_BUFFS), 1319 (void *)aup->vaddr, aup->dma_addr, 1320 DMA_ATTR_NON_CONSISTENT); 1321 err_vaddr: 1322 free_netdev(dev); 1323 err_alloc: 1324 release_mem_region(macdma->start, resource_size(macdma)); 1325 err_macdma: 1326 release_mem_region(macen->start, resource_size(macen)); 1327 err_request: 1328 release_mem_region(base->start, resource_size(base)); 1329 out: 1330 return err; 1331 } 1332 1333 static int au1000_remove(struct platform_device *pdev) 1334 { 1335 struct net_device *dev = platform_get_drvdata(pdev); 1336 struct au1000_private *aup = netdev_priv(dev); 1337 int i; 1338 struct resource *base, *macen; 1339 1340 unregister_netdev(dev); 1341 mdiobus_unregister(aup->mii_bus); 1342 mdiobus_free(aup->mii_bus); 1343 1344 for (i = 0; i < NUM_RX_DMA; i++) 1345 if (aup->rx_db_inuse[i]) 1346 au1000_ReleaseDB(aup, aup->rx_db_inuse[i]); 1347 1348 for (i = 0; i < NUM_TX_DMA; i++) 1349 if (aup->tx_db_inuse[i]) 1350 au1000_ReleaseDB(aup, aup->tx_db_inuse[i]); 1351 1352 dma_free_attrs(&pdev->dev, MAX_BUF_SIZE * (NUM_TX_BUFFS + NUM_RX_BUFFS), 1353 (void *)aup->vaddr, aup->dma_addr, 1354 DMA_ATTR_NON_CONSISTENT); 1355 1356 iounmap(aup->macdma); 1357 iounmap(aup->mac); 1358 iounmap(aup->enable); 1359 1360 base = platform_get_resource(pdev, IORESOURCE_MEM, 2); 1361 release_mem_region(base->start, resource_size(base)); 1362 1363 base = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1364 release_mem_region(base->start, resource_size(base)); 1365 1366 macen = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1367 release_mem_region(macen->start, resource_size(macen)); 1368 1369 free_netdev(dev); 1370 1371 return 0; 1372 } 1373 1374 static struct platform_driver au1000_eth_driver = { 1375 .probe = au1000_probe, 1376 .remove = au1000_remove, 1377 .driver = { 1378 .name = "au1000-eth", 1379 }, 1380 }; 1381 1382 module_platform_driver(au1000_eth_driver); 1383 1384 MODULE_ALIAS("platform:au1000-eth"); 1385