1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 /* 3 * Copyright 2015-2020 Amazon.com, Inc. or its affiliates. All rights reserved. 4 */ 5 6 #ifndef ENA_H 7 #define ENA_H 8 9 #include <linux/bitops.h> 10 #include <linux/dim.h> 11 #include <linux/etherdevice.h> 12 #include <linux/if_vlan.h> 13 #include <linux/inetdevice.h> 14 #include <linux/interrupt.h> 15 #include <linux/netdevice.h> 16 #include <linux/skbuff.h> 17 #include <uapi/linux/bpf.h> 18 19 #include "ena_com.h" 20 #include "ena_eth_com.h" 21 22 #define DRV_MODULE_GEN_MAJOR 2 23 #define DRV_MODULE_GEN_MINOR 1 24 #define DRV_MODULE_GEN_SUBMINOR 0 25 26 #define DRV_MODULE_NAME "ena" 27 28 #define DEVICE_NAME "Elastic Network Adapter (ENA)" 29 30 /* 1 for AENQ + ADMIN */ 31 #define ENA_ADMIN_MSIX_VEC 1 32 #define ENA_MAX_MSIX_VEC(io_queues) (ENA_ADMIN_MSIX_VEC + (io_queues)) 33 34 /* The ENA buffer length fields is 16 bit long. So when PAGE_SIZE == 64kB the 35 * driver passes 0. 36 * Since the max packet size the ENA handles is ~9kB limit the buffer length to 37 * 16kB. 38 */ 39 #if PAGE_SIZE > SZ_16K 40 #define ENA_PAGE_SIZE (_AC(SZ_16K, UL)) 41 #else 42 #define ENA_PAGE_SIZE PAGE_SIZE 43 #endif 44 45 #define ENA_MIN_MSIX_VEC 2 46 47 #define ENA_REG_BAR 0 48 #define ENA_MEM_BAR 2 49 #define ENA_BAR_MASK (BIT(ENA_REG_BAR) | BIT(ENA_MEM_BAR)) 50 51 #define ENA_DEFAULT_RING_SIZE (1024) 52 #define ENA_MIN_RING_SIZE (256) 53 54 #define ENA_MIN_NUM_IO_QUEUES (1) 55 56 #define ENA_TX_WAKEUP_THRESH (MAX_SKB_FRAGS + 2) 57 #define ENA_DEFAULT_RX_COPYBREAK (256 - NET_IP_ALIGN) 58 59 #define ENA_MIN_MTU 128 60 61 #define ENA_NAME_MAX_LEN 20 62 #define ENA_IRQNAME_SIZE 40 63 64 #define ENA_PKT_MAX_BUFS 19 65 66 #define ENA_RX_RSS_TABLE_LOG_SIZE 7 67 #define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE) 68 69 /* The number of tx packet completions that will be handled each NAPI poll 70 * cycle is ring_size / ENA_TX_POLL_BUDGET_DIVIDER. 71 */ 72 #define ENA_TX_POLL_BUDGET_DIVIDER 4 73 74 /* Refill Rx queue when number of required descriptors is above 75 * QUEUE_SIZE / ENA_RX_REFILL_THRESH_DIVIDER or ENA_RX_REFILL_THRESH_PACKET 76 */ 77 #define ENA_RX_REFILL_THRESH_DIVIDER 8 78 #define ENA_RX_REFILL_THRESH_PACKET 256 79 80 /* Number of queues to check for missing queues per timer service */ 81 #define ENA_MONITORED_TX_QUEUES 4 82 /* Max timeout packets before device reset */ 83 #define MAX_NUM_OF_TIMEOUTED_PACKETS 128 84 85 #define ENA_TX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1)) 86 87 #define ENA_RX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1)) 88 #define ENA_RX_RING_IDX_ADD(idx, n, ring_size) \ 89 (((idx) + (n)) & ((ring_size) - 1)) 90 91 #define ENA_IO_TXQ_IDX(q) (2 * (q)) 92 #define ENA_IO_RXQ_IDX(q) (2 * (q) + 1) 93 #define ENA_IO_TXQ_IDX_TO_COMBINED_IDX(q) ((q) / 2) 94 #define ENA_IO_RXQ_IDX_TO_COMBINED_IDX(q) (((q) - 1) / 2) 95 96 #define ENA_MGMNT_IRQ_IDX 0 97 #define ENA_IO_IRQ_FIRST_IDX 1 98 #define ENA_IO_IRQ_IDX(q) (ENA_IO_IRQ_FIRST_IDX + (q)) 99 100 #define ENA_ADMIN_POLL_DELAY_US 100 101 102 /* ENA device should send keep alive msg every 1 sec. 103 * We wait for 6 sec just to be on the safe side. 104 */ 105 #define ENA_DEVICE_KALIVE_TIMEOUT (6 * HZ) 106 #define ENA_MAX_NO_INTERRUPT_ITERATIONS 3 107 108 #define ENA_MMIO_DISABLE_REG_READ BIT(0) 109 110 /* The max MTU size is configured to be the ethernet frame size without 111 * the overhead of the ethernet header, which can have a VLAN header, and 112 * a frame check sequence (FCS). 113 * The buffer size we share with the device is defined to be ENA_PAGE_SIZE 114 */ 115 116 #define ENA_XDP_MAX_MTU (ENA_PAGE_SIZE - ETH_HLEN - ETH_FCS_LEN - \ 117 VLAN_HLEN - XDP_PACKET_HEADROOM - \ 118 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 119 120 #define ENA_IS_XDP_INDEX(adapter, index) (((index) >= (adapter)->xdp_first_ring) && \ 121 ((index) < (adapter)->xdp_first_ring + (adapter)->xdp_num_queues)) 122 123 struct ena_irq { 124 irq_handler_t handler; 125 void *data; 126 int cpu; 127 u32 vector; 128 cpumask_t affinity_hint_mask; 129 char name[ENA_IRQNAME_SIZE]; 130 }; 131 132 struct ena_napi { 133 u8 first_interrupt ____cacheline_aligned; 134 u8 interrupts_masked; 135 struct napi_struct napi; 136 struct ena_ring *tx_ring; 137 struct ena_ring *rx_ring; 138 struct ena_ring *xdp_ring; 139 u32 qid; 140 struct dim dim; 141 }; 142 143 struct ena_tx_buffer { 144 struct sk_buff *skb; 145 /* num of ena desc for this specific skb 146 * (includes data desc and metadata desc) 147 */ 148 u32 tx_descs; 149 /* num of buffers used by this skb */ 150 u32 num_of_bufs; 151 152 /* XDP buffer structure which is used for sending packets in 153 * the xdp queues 154 */ 155 struct xdp_frame *xdpf; 156 157 /* Indicate if bufs[0] map the linear data of the skb. */ 158 u8 map_linear_data; 159 160 /* Used for detect missing tx packets to limit the number of prints */ 161 u32 print_once; 162 /* Save the last jiffies to detect missing tx packets 163 * 164 * sets to non zero value on ena_start_xmit and set to zero on 165 * napi and timer_Service_routine. 166 * 167 * while this value is not protected by lock, 168 * a given packet is not expected to be handled by ena_start_xmit 169 * and by napi/timer_service at the same time. 170 */ 171 unsigned long last_jiffies; 172 struct ena_com_buf bufs[ENA_PKT_MAX_BUFS]; 173 } ____cacheline_aligned; 174 175 struct ena_rx_buffer { 176 struct sk_buff *skb; 177 struct page *page; 178 u32 page_offset; 179 struct ena_com_buf ena_buf; 180 } ____cacheline_aligned; 181 182 struct ena_stats_tx { 183 u64 cnt; 184 u64 bytes; 185 u64 queue_stop; 186 u64 prepare_ctx_err; 187 u64 queue_wakeup; 188 u64 dma_mapping_err; 189 u64 linearize; 190 u64 linearize_failed; 191 u64 napi_comp; 192 u64 tx_poll; 193 u64 doorbells; 194 u64 bad_req_id; 195 u64 llq_buffer_copy; 196 u64 missed_tx; 197 u64 unmask_interrupt; 198 u64 last_napi_jiffies; 199 }; 200 201 struct ena_stats_rx { 202 u64 cnt; 203 u64 bytes; 204 u64 rx_copybreak_pkt; 205 u64 csum_good; 206 u64 refil_partial; 207 u64 csum_bad; 208 u64 page_alloc_fail; 209 u64 skb_alloc_fail; 210 u64 dma_mapping_err; 211 u64 bad_desc_num; 212 u64 bad_req_id; 213 u64 empty_rx_ring; 214 u64 csum_unchecked; 215 u64 xdp_aborted; 216 u64 xdp_drop; 217 u64 xdp_pass; 218 u64 xdp_tx; 219 u64 xdp_invalid; 220 u64 xdp_redirect; 221 }; 222 223 struct ena_ring { 224 /* Holds the empty requests for TX/RX 225 * out of order completions 226 */ 227 u16 *free_ids; 228 229 union { 230 struct ena_tx_buffer *tx_buffer_info; 231 struct ena_rx_buffer *rx_buffer_info; 232 }; 233 234 /* cache ptr to avoid using the adapter */ 235 struct device *dev; 236 struct pci_dev *pdev; 237 struct napi_struct *napi; 238 struct net_device *netdev; 239 struct ena_com_dev *ena_dev; 240 struct ena_adapter *adapter; 241 struct ena_com_io_cq *ena_com_io_cq; 242 struct ena_com_io_sq *ena_com_io_sq; 243 struct bpf_prog *xdp_bpf_prog; 244 struct xdp_rxq_info xdp_rxq; 245 spinlock_t xdp_tx_lock; /* synchronize XDP TX/Redirect traffic */ 246 /* Used for rx queues only to point to the xdp tx ring, to 247 * which traffic should be redirected from this rx ring. 248 */ 249 struct ena_ring *xdp_ring; 250 251 u16 next_to_use; 252 u16 next_to_clean; 253 u16 rx_copybreak; 254 u16 rx_headroom; 255 u16 qid; 256 u16 mtu; 257 u16 sgl_size; 258 259 /* The maximum header length the device can handle */ 260 u8 tx_max_header_size; 261 262 bool disable_meta_caching; 263 u16 no_interrupt_event_cnt; 264 265 /* cpu and NUMA for TPH */ 266 int cpu; 267 int numa_node; 268 269 /* number of tx/rx_buffer_info's entries */ 270 int ring_size; 271 272 enum ena_admin_placement_policy_type tx_mem_queue_type; 273 274 struct ena_com_rx_buf_info ena_bufs[ENA_PKT_MAX_BUFS]; 275 u32 smoothed_interval; 276 u32 per_napi_packets; 277 u16 non_empty_napi_events; 278 struct u64_stats_sync syncp; 279 union { 280 struct ena_stats_tx tx_stats; 281 struct ena_stats_rx rx_stats; 282 }; 283 284 u8 *push_buf_intermediate_buf; 285 int empty_rx_queue; 286 } ____cacheline_aligned; 287 288 struct ena_stats_dev { 289 u64 tx_timeout; 290 u64 suspend; 291 u64 resume; 292 u64 wd_expired; 293 u64 interface_up; 294 u64 interface_down; 295 u64 admin_q_pause; 296 u64 rx_drops; 297 u64 tx_drops; 298 }; 299 300 enum ena_flags_t { 301 ENA_FLAG_DEVICE_RUNNING, 302 ENA_FLAG_DEV_UP, 303 ENA_FLAG_LINK_UP, 304 ENA_FLAG_MSIX_ENABLED, 305 ENA_FLAG_TRIGGER_RESET, 306 ENA_FLAG_ONGOING_RESET 307 }; 308 309 /* adapter specific private data structure */ 310 struct ena_adapter { 311 struct ena_com_dev *ena_dev; 312 /* OS defined structs */ 313 struct net_device *netdev; 314 struct pci_dev *pdev; 315 316 /* rx packets that shorter that this len will be copied to the skb 317 * header 318 */ 319 u32 rx_copybreak; 320 u32 max_mtu; 321 322 u32 num_io_queues; 323 u32 max_num_io_queues; 324 325 int msix_vecs; 326 327 u32 missing_tx_completion_threshold; 328 329 u32 requested_tx_ring_size; 330 u32 requested_rx_ring_size; 331 332 u32 max_tx_ring_size; 333 u32 max_rx_ring_size; 334 335 u32 msg_enable; 336 337 u16 max_tx_sgl_size; 338 u16 max_rx_sgl_size; 339 340 u8 mac_addr[ETH_ALEN]; 341 342 unsigned long keep_alive_timeout; 343 unsigned long missing_tx_completion_to; 344 345 char name[ENA_NAME_MAX_LEN]; 346 347 unsigned long flags; 348 /* TX */ 349 struct ena_ring tx_ring[ENA_MAX_NUM_IO_QUEUES] 350 ____cacheline_aligned_in_smp; 351 352 /* RX */ 353 struct ena_ring rx_ring[ENA_MAX_NUM_IO_QUEUES] 354 ____cacheline_aligned_in_smp; 355 356 struct ena_napi ena_napi[ENA_MAX_NUM_IO_QUEUES]; 357 358 struct ena_irq irq_tbl[ENA_MAX_MSIX_VEC(ENA_MAX_NUM_IO_QUEUES)]; 359 360 /* timer service */ 361 struct work_struct reset_task; 362 struct timer_list timer_service; 363 364 bool wd_state; 365 bool dev_up_before_reset; 366 bool disable_meta_caching; 367 unsigned long last_keep_alive_jiffies; 368 369 struct u64_stats_sync syncp; 370 struct ena_stats_dev dev_stats; 371 struct ena_admin_eni_stats eni_stats; 372 373 /* last queue index that was checked for uncompleted tx packets */ 374 u32 last_monitored_tx_qid; 375 376 enum ena_regs_reset_reason_types reset_reason; 377 378 struct bpf_prog *xdp_bpf_prog; 379 u32 xdp_first_ring; 380 u32 xdp_num_queues; 381 }; 382 383 void ena_set_ethtool_ops(struct net_device *netdev); 384 385 void ena_dump_stats_to_dmesg(struct ena_adapter *adapter); 386 387 void ena_dump_stats_to_buf(struct ena_adapter *adapter, u8 *buf); 388 389 int ena_update_hw_stats(struct ena_adapter *adapter); 390 391 int ena_update_queue_sizes(struct ena_adapter *adapter, 392 u32 new_tx_size, 393 u32 new_rx_size); 394 395 int ena_update_queue_count(struct ena_adapter *adapter, u32 new_channel_count); 396 397 int ena_set_rx_copybreak(struct ena_adapter *adapter, u32 rx_copybreak); 398 399 int ena_get_sset_count(struct net_device *netdev, int sset); 400 401 static inline void ena_reset_device(struct ena_adapter *adapter, 402 enum ena_regs_reset_reason_types reset_reason) 403 { 404 adapter->reset_reason = reset_reason; 405 /* Make sure reset reason is set before triggering the reset */ 406 smp_mb__before_atomic(); 407 set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags); 408 } 409 410 enum ena_xdp_errors_t { 411 ENA_XDP_ALLOWED = 0, 412 ENA_XDP_CURRENT_MTU_TOO_LARGE, 413 ENA_XDP_NO_ENOUGH_QUEUES, 414 }; 415 416 enum ENA_XDP_ACTIONS { 417 ENA_XDP_PASS = 0, 418 ENA_XDP_TX = BIT(0), 419 ENA_XDP_REDIRECT = BIT(1), 420 ENA_XDP_DROP = BIT(2) 421 }; 422 423 #define ENA_XDP_FORWARDED (ENA_XDP_TX | ENA_XDP_REDIRECT) 424 425 static inline bool ena_xdp_present(struct ena_adapter *adapter) 426 { 427 return !!adapter->xdp_bpf_prog; 428 } 429 430 static inline bool ena_xdp_present_ring(struct ena_ring *ring) 431 { 432 return !!ring->xdp_bpf_prog; 433 } 434 435 static inline bool ena_xdp_legal_queue_count(struct ena_adapter *adapter, 436 u32 queues) 437 { 438 return 2 * queues <= adapter->max_num_io_queues; 439 } 440 441 static inline enum ena_xdp_errors_t ena_xdp_allowed(struct ena_adapter *adapter) 442 { 443 enum ena_xdp_errors_t rc = ENA_XDP_ALLOWED; 444 445 if (adapter->netdev->mtu > ENA_XDP_MAX_MTU) 446 rc = ENA_XDP_CURRENT_MTU_TOO_LARGE; 447 else if (!ena_xdp_legal_queue_count(adapter, adapter->num_io_queues)) 448 rc = ENA_XDP_NO_ENOUGH_QUEUES; 449 450 return rc; 451 } 452 453 #endif /* !(ENA_H) */ 454